Datasets:
rtl-llm
/
vhdl_github

Dataset card Data Studio Files
xet
 Community
1
content
stringlengths
1
1.04M
⌀
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block pBqd8SbxnErWrX3lyBBDaDLKX8hSp/j5Yr+Qm9jRb/9JUTybH1McKspWz+db0YzfLoM8Rsbks3xZ F0QO+ZZlvg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block H9nfu/oUf72/R62OBj/4D944lb73dgO7fFOuMJCE4aenI7iF3utXSTO4hpgrQ8McaV+063uC1I2p SowtO/PmhlxRipVo5KEq7Hhzbtvt5amDIBC05YVti4pxjbEI/kmWeW6ApomatkIzigzghecNWi3O dw5/lv3XsuSXKGnf8V0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block LHYKr83oHemqUyK1Wezwr1z3qiqaCVVbCTepzFi2rZrXgOFTcCRhqXcHptrNPAEIVNUU983e0J/f 0KmoDwapS9jLRSEt/t44AcYzVSy/ai/iXQJgng7HtLlp+4d5yiOHFpGB54L6O3dBpou3h7caNhhL jjFv+2NQ8/vJ/xJXwO5fh2Ph6YYguOVQ53PyR/4efc4uuMmB69VXQ320viKRtmBbQCmyLZzeWtFu D4qzTizu+7+B9LccVDGFdS5MPG9ajzsWHD/tFElptKJXuLi1qfJlX0wCtTtXoY+3nkHdj+d8GtPf YHFzKsVl3XUte66S5MbnjiWHmaZaMtS1k7u0qg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 4MafVQvjuuBxvIjR+OYUlKEesGBWmyoKTpW4+3dmDKYdKobe8ekpI4KwM+KYTh1JKxG3Qgsr94sv sXNAR2TjWeHLAvJhva65Oh3N+FSqhrH0zjkmu9XvgIV/UwkRDNwOx9c4++PMmrK6Sc3dNZpoycaC lN9AukRoCBpCWkU/kGY= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Oe9rX9bCQUY9pDwkxKbbIf2ys0cqImU27qEFK2Dw17YylEZy1DE0fAY/RnVb+EPxtWACfGlXlONl m+j1F3QtQOlCfFGG+seFfsBQSPHUmFsJmINuxeAGpMhxfKpsTFjDqKjDpQa8VcnDwKWm4aO3goL8 ohfQk4XoUdGZKXOs6aDCwCjQ3NSG6AcZNW0ORDZyS9Kio2rZOPAl2Iatk0VLalSOSKS8f5tT86ig hcckTERcoJMSnJHpKMG0Uf46p6lF1NxyM72QA47lZHQTdUAqzyv8wPWp/x+9NpDScFU+0BwCqNgR Wwy5LWtdGsu9PzUszKuMs6YlHHcqBdvP6pV04w== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008) `protect data_block ugPchIic85pVoazhFaH2TWuQjqsMIDhfmCLDBUOtUS/RF04DCSHl4KkxPTtW6P+RbyiD3T+m3kTR N0N334mL4z3weuQnltN6rjwv5421Of+ebjf9jNPWmR9lf0e4KC1P2a+RqcNXNDLyWLeUSh5xhG/Z 78Dc0xYUHiF3d+hrOZnBHDBSzBMBxH85jBmUl3hJ6N8TJlBFLvzDJLAwx9rMqd+/ukKUbS92XXmq GUfEtXOD/kOjfUAMdbSYK383ZTVeO8P00Ys+990ShfmBjW11X5zfC8a6pcCnYMWovhs5zhxlg5VY 5qaNHLAk3jG98jGzfgSX7h68H0TVRR7JEDFOWoBp6nHeaNm3GUeQnBHvRRf9iGTHwtNoBo20CT3s B+8CdJKTLLUzk6qAj2GsiBGHS8LnYKmNkY/fLp6AmB2/qs4DlNFJIF8WLDrSqDSxN7vLmxfW02dn 97TZdyIIRU0sSDWmckU00Bj4DR6lVWvrorzqz+TKptQht1fc7GrTmUsh2hItQeA59cOw1AOmZDS9 1wq0ZKLVSXAjdB+CY84byFDq/ggnql+ym9df++F4CndyzeHn/77aqPKlsW1vloWWAkuV+/oxdhDW p20TyTT2O/VPp3m+EzlmnnWV4xK70h3N6PHM98xVk6mnffhh/Vgh2FPYUMBhFoA1R5ZkVo2hBFx+ BdBPaixrD1Bh0/1sYSrIxRoyOp3yESYfh6j5q6cxlNTa1qH+ifL4xeUh7yFpIAKcpGKV/BHZ4BXZ dzcowFS0zr5D1j59GJ2fBtclaFagM874kSHoT7saPkMwJZzu0a9Suyo2oyHeDY5u0tqwoOjIxSPD LgfMjS5eI/7kq2LRK6vuUkw4NPeUXfLEpGv5FCJ6L5qj3kBW2g6KAhG87smejtyOyPsvsfynrIc2 3VnDVEHbU7JdT+65asCO43n+F2twwXTbRz3siKaGFW/pSUKMJST4WLbItR8/WK8o1ze8PIiuzlcV 2q4JbKB8FDK4mLtzmIeYo7UTwNP6U9iXbLmMvu0dzyoUw3NDGJK4KUCMCVvDKN1R/+YL7Uwr/kfr H2I7nTHDRk6JDcgnN9lfHUT2S8C2BMkKRraWkqRs0K6NTq153MMgQ0I68tioSH/TpTwOz9oXVKBC IPIOjB4kXex4kXwRz23kXOxBtWL2ufKqg40K9aFi7BK+LFkdT9TJGBCwlY11kGcbWle5fHFUxBgl D7qMX2r59mWmGBSSP9gWsTMEGB58WJb0FCVJzJGA6OZLDvK1GTVkE3XRxGSmgNPHSS7w3jMJyMM1 LUnr75CCm+QeHuKzLZmM4W96dN4nPXd6yqiYEO85iAqDcN94rfIuZjKzOQpcTx9Oi4DIbX9uESmY tjGl70Xxr/adCaR8ilSvqqc+b4MBKqY7ELJDs0L3vXhscTGf4aQPSq6GF+yybBqE/m0z770fLOgC kzFPyfhoCNMoGzjgznhNFl/K2SBBjlumjwB4VoL4kPAv9g27PQzII7LCyKyJowsuyed1QFyLx6e0 zPEPygamJ5b2aKJfHjhq6Imar4DfdI9b/lJ2m3mKH5VW2TviID8sew7r/S+Cqsd1khcH0dn+JSpQ Cz5CskuqoPSTdJzTOv3pTxDL59oUgopc8EhlWAJY+mQaF0YTUq6eOMJWIqiTRPuWQs6VbYgRaUWq gGyiyprJEh8tjGjzF1g0t47LQBCmfF+ET+Qos0n0Wh5P3AuYe2d26zA4VHkOum3I/l6rLBKqZWgw 80FOjGL5rFavkxULg1QQ4CE5oihzlPEto13KkUan3UDd4FbgJCBwxe8aBRFgid7TZjfFiKmhUFt5 VQdmXePim15/U9KY4mMIYrnEKT0toYoS7SwJCXalf9S/2xU0+tvNWpw1X6qO/7v3BrnHauRDb8p7 DXnByUOEvR5Iwn7KTkPdDsC19IFFE44KJQW/TLM47NkLTnUgjtpw8GJXRgECeGgmVvN4zDWAz4kH JoZvUApvZD/k60yS9lZdKVETDuGnJLMPWqaE9URGx1F68zV/t6gNNzi4Vbw84HrncqaVQ9wkyUgz NG85xmeRL3PM9bycBzo2/5tEUhya/xB50ZheKo/wFA+vGxItbWD3A/cZCrWTA58Qp5cdb0eH8meI wFkrjyP9iCxkcXPvTVMY8oL8o5pJxxGdMvGwC7jjkK1ms7Vqxk+flNpQwFOxc8Bhi0iZ0/TmPVEf F+ZGV5tPUjYRSTzxofFD0jffamlYZQpqwKkMAfWbYnog1yK+fbQm41jBZ/ovWhcEWoIbKWZIjFSA OD5IG/kjBWkEXyU9LTohftglq69r0maNKbr7EKYPsDpvo8izUbasMLapY/Ny14fG6BWgAYo5xI4s djD2qS4vNfqRKU4rAsx+aRpvVQxZ6OeKvHYxiqiIPhOi8yi5g6zUu2EdUUni0ErRMnKL38mmI4KK 4xPf2PcduRPfhljJVhFLQAL/Vx9rs8TI2ixHSpthP0bZl7TycX1Ef3z74wUQ6nP/jp9Yi9pNL4Es OrsoIJiJrNwmzskoRB+FpS0XmnGK+WXeWg8mUkqP5uDqsrTxbhy1nUF9+bxAHJTjfax7I9UPhkOO g0Ms31UeKJczoUQXY4xQ2756Cr+BoXCCgUE63OOGha4EZNIFVDjshALTXX/K1Zamfq3M4naQOWi7 h36LS6E/7kjsvKD0qig3B+bw4eYn9D7xp9W/b/xnQX1Y6b+KJI1mq3ewFW6FWhzfiushu/g1D3BH IVDnqB2RNE5KByrzrzTWfPXtAzqwVypuv0uPzMYjP/HUWBWWxaM0698XRYq6tEjyEZmrbmcmdddB F+978ctayhLeGND3gjJzMD9GVyWbsp22+eKzIrPfgf+zir8BuPgUT2EfbWNhBLNuDCTbpqX3h5p5 UQgkeDx9fuGyyfEwSY01Gj+b0y0ZfFaPQ8GsQKQ544ltOq5D2c2hxCm8+bT33Xox9Byh0dE54yji mtCKhyFgjWGN+nc8kZemzz58Qc+tFgq33sNTvW+u613NDE6weCWYbSHGw+zKAAKUT3bn5wnjKlNP Za0+LvGGrSLhqhB1E+mDbzQz9WPa7pk2U5Yx8hXeWw49WqeFimySWFNJyPEM3fxsATP6UzAn8oSB gaeOEqF9ZAokKdVC3hxFEdR4hES9AH5L8QlOcAwytA0XEPo7+VJ1dvQy+CUJFMSViL4UyQ/1d3w3 /JflFzwiR+Pqp+4cC7R1OcxV41N/Xis6AjZZ+L7AUqsfgANI6OaDHJs7hPXGw7n3rtuNAlK2NiwM bWvK56olPYG7yuoHmsKWkg4wJLoG/MjMFjZEijGpYHYAri6CzgPrNOGFw45dmw2Adhf7PPKe3wyy LOw0Ka9N83vjMWPcpVP+2ScLxhfRWLsSQwqGhh8AaitW2OiTx7ekbXijvvIy/TeTns9LEnf2mN7s IBe+4wzrMc5PmHPVAy16ju/wQ6j1XAbp9cyi6gY0S6FWOq1l8lKsx96z6qBwWwgxdynUzi7lARod UBJaDyt9i7nIhqjp79HJziAlaRo1Xrnt+LN/sCHD7PBmqF50pCSW6YzEuP164twgaiGlAi/yYTc3 kt2l9rDpHVSNaJM0oz662UavJO7BxnuoM2PoAzBcoBY78upERvNQBQFzOo9XtFM6zaeXPNJPSIJz H8F3j7maBdtYWMjy4sDalZ7Fyxlo/lRm19Ds8/86OjGDBNR9PMmPiZAwnLvtNG3yp5gmgsW1sskF +jyaMoW9SFHOaU0dQ9hPXG6sflnNACAOh4LqrSjDxOdDGXJIBbCV85aakvibPiTbvRihxfcymks/ F3Vg2mB0MLQN1C41ypwTN41Z7iy6mmfowNrVB6suL0B4C23X5uXmksOWaa7Fqhue8voYHNYz87AX 1CmUnsx+ESMgq+Cnk/6CljrQ65N4INHD44SXvqqsH7KGdCK/VJXrSrd2MBqWddVIeoLXCuqYwOxj ezDRKd9jCIrgi/Tp6uGj5vAaqWNO0i6KQ+V1odyjNq7xhDwfSyL15I44zNRkGVJd7ttEs2zo+e9M tTkR1igHWulM5TMUdbMdej0p4q9rY2Vpez9BWoTMI+NMTosN/VBa1uoXg3e1i5Mey6pH68hXSc/y OOl6NP0lAsF6r0vso9xG+KIJcJZ1ldonn048etdsDOsRodP/ZiitgPAjFW8b3r38t2L5uZfsEwWr WnyK9Yy27tLFMgyfeBmKMin/bqqg+xVK4GGjb8oravkTjBVW9VCYc8nzEU0RlL3Kpd4DNscR6Chn fBK2UambbZE0jsrc/gF32wOzEjsRYq2t/NxyOzmZ6TBogtMcqTuJUWvDPcmPB7KFI1xve5KpTnFH b+AGLQebcHUjlzNAfV1aH3VZWNbetP9Op++JhuKwV84xkXVR7HuIdr3CIedCHKzWW9k6bDKi27rn MpImtyw+Jhjrdjb6GpTy/V9Mt35CVz0ilaAlzYnQJBMH+HbaZ2u8yveI4vSTZwSZ51DlN6u2fdtZ OHLA4WhhHPzW93UgL+Z3Yn1ZfGH8L0XL0rG0Wmi5mZuQTP2nfGHnKvEpiUV4uhQnQoO4ovh+VRRa UdTp3aYvOwcLa1Tbfxs0zG8896q6sLndM++95zagL7jOyZnFmQddlKEtNZvqtBxvKiZzUa4mudH8 2QAR8ewUfAWLEQ3FDWqtbRklVLgvxrbFK8SrAIE3lwO5YHXnIYHasG7Q8kSregntWeOmW9T414pQ js7uEMYE6soIZDftkj7r2aw7chVXBS+0VcsvZ/buAIoIiNyiZISKmnQvXIqWI/07V/7ZcJb1Mul7 iyxId91udFo7+4FtchFIwNV+RHeV4jxN6vLH4C160myH5id0QWN9saHX31nAzxNCLbI/8NdaMApz Pe14SASWdOWHeESkoxp32P0cnYi2VaV9dE8aaiiuHcNyfSbIndQdMiAHZADN8h5t9ZH+FUd3QsyF Sqpl5mKnkQ4Iee+gH/GeM4GoWyqumkfLSfvgpjCP+glKrnG8oarvPatTNQyzZxLcT3qc3gw+2qD3 w8EFzIZpIIllJuwyHGtnzdAofwWQ2t2QhS2nw4dvDoLydqXqtl22O0UF8tdDfG0ePnfvBF1OJ6tX 27vnuoiD7/sNn1iXhX00lrc+/ZM5JU80RRA1t6eEcOzVORKNgDQJFnuujNJH7wLQ7EHTUmeR+sAt Cv1KJNSHlVz/cK7/iUC0r6axtv8mKAVntAgTy/SGFP6roiqTVFExrldW4nVtzASpqjulJ4OusT++ eOEove+a0qg2KM7bTk0Bn45YeIrsgjan3/mlE07UhfoZ4SSfMl7EtZvaRR3ipwx6e71+8ku0ngoS qy8nRgtaRqRY7Jk1nDpdNe2iqhTgF6b7cG3phYYw/NBlzKtuyfmjvBqZyBwCH9LpIGKRL75azkK3 lLHg6yhSIhU+EORJ2y1YtfqGUmiG9Niiw6+HG4pf6osSsJn2bE5IAMUdFnPsLXbLZGp7eSXJQyFq 8hpiZMpF1xQkxYpxz/wk5LDqfQjjU8223MNGUH4fNxNkw+ADIhqqCZqHIOIpsfQzG71AfZu814ak jBTWPgeR/JYYF+PVJCvoxDhcgNL8XkOo2SzCjPaxCZFctxOkd/vDMvfhEwUgLbji10FGbOWGlVBq NZCJSflITRjCxkEaeIs4knmuyTIB7itLSpYbJz2ASoRzfyhtxl7lRvRhoI3I8JWSjaE0gzCDLYgi RDsCb2RiJ8XohoAuLRZKRVerVZcZf3rUI+0/K6zcdFL0klSPqnlt5vcgh5NgguKaJ9GabPGAD2NP 9fbfs1buAvi4uv69L1MqWzQSAvacBFAa4P9AT8u+t+aH0rU9nbdivFCa4QBcrbu4dIurpEOTlz6v Q4y+hklWTfxSNJo3P03O2zVvqDbYdlUSMVa47POuEwZqhOYuMHlll8NMSrwLAgOBiQ0GMCj71pVW mThWwktWKUqfgfmCpBcf1vO3YgSc0eGbNhSvwHYOyVLBPc7ySaMgxTOBJYVsnEQHWtVqoSnTAk3G QvSI8/SSOhE95/e4PurKfyZRuJflbeXE//Tnmh5ucLit5o7PbNAx+7Vgzx7QWY2EmPlpS1vNTfXL E8YrX+xRsIaJTA8fEBWnr/2c6i8iEenn++STYpXoY5RK8zeq8W+hGwmkOPtbQzLKXWJlpFkYVR4o nSLEIJnCAjsqDoVa8M9WHzmMxduRz+5JHd+ulXyw6HuVbSfxGl7+1vmiwX98jOJV/B2rnUnZ1WzQ frG/pjNNX8cyOnWkREdG+pBC3KYfZH9J7OP2KLdC7ZPxSR9hYJYqhq0xq0pyolbbeIXSnahGLH2A zQklbExh0qDnU0yp1f5U2TmWZDcf3jcHCvmJAm+cSplprSIUCHpP9yfCr087fRyet37UlxQTirZ2 Cu275t1hYOJ0EpvJYJ1S6sdM1QsbzskwSDC8Y0xP98UWE6/+AMHdv3GnE6SvwNZMvTGJkn96ab2o 5znQmV8122xq0E6e+2wD/XdQve42BvedJmozWGevKv7/RLHlK2YbqQsVKlDxeFIBunkkGOBmRsbL aBqwLRvIuO95OqqPOiRjf3RRcpxxM7y2a/uM3IuxuvLPfmYxV99uAcrvlwJkoiAnFLTlQKD7L8v8 0aeXoVkGq8/cq0354bbX7VSOJvu4cu5VUhtCS1YI7frRP2oJmWAeQRekteggVCoDflkDUqzUsZLQ tS+fjwPiGPLI1b4K4HZvtGwp+EUT7UUzfFeEJNhEPPa+GT1sHRDq43kuHJUO2l6pG02DdQwejKvE BgHQyX4JsLUlFp54yHA03+7z/+1+hVbZf1gG19WdyGmqON33qKq4fecMxXgb08hJbkLI/bzfiPJo GIIUI4ZgP80hbq3wJt3KVfhyMfbQNTfFTs1DiS/ZtB2YMSgErGn+A8gpB2VHPyovp1MWHUhPfsGl Cicec2BTQreiNhgJSU3tuYBD8HFEOkNuG8HxwffyjMrTOQUDf5/DcRSh8/QZN9aRP7vqMB5+ouLB BM3Cm3zzlWfS/lNhRsCrewOzfzFINfPGZqgmtF/1UyksiLB0VrU1KzHhWCMK6qwQepPPMmH1Ww+H dhP/5e4gNAw7t33+ciyoMyKCb/1I3sCedU6yjgejvKIdLhu4OloBAgbaBVAYhb2QP5GixZZruar8 K5r644IqRnPKDjNB2MY1tUwguYv2cPh3zYwZvI+maiWwHhQAHwjXFwx1y/zRxF9+OnpAHpeqga7K cmvuqKPjBhbGo0Vk/Dw7A1CQ4CG6b6M1AdZYpimNvVrzA7NKArpavLkGw2GCxuoWS2GCBqcumTKP MVGztQTL4F7W5ufN9sjaCh1Lh6LHjWq3ufgoEP3DK6R2KPwPrRnfEsTQLbdQS9SGjcpVRNcpQfAV i3OBYmpj60typMrGJyAP9EqSaOwlG6sWtz/p1e7AG72uyH2OT5PMSlQ7z3WCFYKRc/eI7/svcCLw TV3v7TH8B/1z+usu9X3y5Ad4fnvZ1jaSCKRO6KEjdKoIKJRsV9UnmMm8XyrUZtRcQpdWogyhqTKZ 3hODX4nK2UKq0ZPcoq4unvTXSvUW31Esqd5c3IcGDTMPHGceQHYmNfhkha6dJvTce7iJ/Dx4eMzW k5DDQml26ol8E9GGKeVa/awQmyAqtlmpvtHU/sBtxfrCTFmD2TcUGW6FdwFXMTu1MPwHJCE+Uwe0 VOmcC+/Mgaron1eLzMWV8XyW0ACztshoHbJfD9d9JsU1cJbGyOYQXu5pydYlv0r7f6HmDVxM7O1S rCuOYx2DZtSqmHzS1d8qCYlF2TkW0CVBcb8FCABSIM6caQ2aR+2MnCP+f/2uXHkH5acFGclk0M3n xc2A7ebD6mzZEOYWWxJBDElzxDKstwuB0ok5v2gwisV8CeuWAs8bjHOs5An7XdyM5g/9hyxXZivj fr0OMVLnw6u/Q+8rJV8/MoRSJ6wjs2qI8Z5MJSh4pBnHrwZbv2MWl+AIAMlq94qF4weEhBVNaHGH CfVPrMuRFwHVRkRhdFZAcsjaQBs+s+E3oenDYAe7Ko4bHmAA1sKKYLiatMXxmmwXSSCz6FewD4PM EFO9Gv7SsiECezHUmJxNcolWOsuk0RE9MakoNlaBgzKEkiDTqa13GwLnNg9Ck+cLCcHgnzIO1Njk L4b7LBFITgmMMm5B6INns4IdMbmaNO6KziwlBDOx22CmDUoV38m699UmEYCaUoDauHrMWbFAX2Nh 99QDJ0gI/4echrXMMbmcWyrizwN+QOYXN7WcSBMBW3iyy3ttsbDzaeq9/oPU18zzPAM+D+zFmeR2 zdbBrzQa9sESX1LphCo2CrKvbqZOJ65K3Sd+BlGnzi2uADnDnEqjwGRXXAnPihzVAbwbYxSLMvk6 bz6SW+eG9w6sZkC8M6DnGvKjF+Qm5tm241A6vyreUHmwA24lFL2F4DQ/wcOaGIxI1V/cxiaxxG24 bhp4Q3ZDgkwS12sHr+j/380mxAtPIeOyNv5Jc15jyBWwkCJ+pKuzrwu2la3lwDcbZaIRB3QwG7Jf +b1aBgR3kCCQkyUMFk+7nJuGWWpI26G89k9mbt7RGBKNhowreUdEkunfV3Ce6DswgpB0DHe7dO+x tYunTbfkcJvJCaDIg7MmBnaK7vEHSDIQ3vk1/JqRqFQj88Qiw5BwFV10oPymHswGDs5Y6PIHtWvN 0OdG7RqnNFk0sFTQkgR5IsxR6CcQIL7TUw/dBEwMvmQ8tO+jtpxMwOPKu5I1RjaTOYHWhHWp5c7V u016PT3exfxVU6/P2PRvvG5ppHbkirnTGwfDZ+0Z1HnVvBLbIeYkU9VlfXZdMcm7gBcbme7Lo2Ie NpSu2PZffaAlMGWZjninpfmmeGrjGRquaDcN3kbZA+M0d4d4v6QtTLCCZDKC5n/KD0pphYQ1yEwT 0e8gU+Q2n+LvWiAji6Ij6kRFmwkk/Ym2MuKGSakMztcBzZdTqCc22uHIwNPqU9lNGV64pnT+6O8s g7U9zg4/JzFhnIO8EtTmid/2CZhfhXsyAB3ze0Ak+sHyY9ad9eZNwnQkJ2UzOsaKXYa/8t+ZvTAS btPANzI6CtZktmDemOgTWKfrwG4Z77GYcEk4VOzTFeQfsVSqJ1SyAIMGgqQUF+pGk22sT6h/6xmx zv6T41noCLQD/2wf31d6iEkF+z5HA86qxKIduLnahwesrHJnZoQHLtO/hg6W9q4tpmy8dchOt3vR 7NcdOx9P1A9EUI3iNDQCD4ppzR08rxLqrO1f7wdD8FtZuyLGgcRceKh/9iBM5MYtFphzbai+Y/NT +30bD8xPgfqjtCtbeuAjR0Sh8WeIy9gDKwc52WwOe7ljeiABuBxt0WpaYOMY9vxWP9J/IyaUWi54 4bH72orR/xMzYfnJjD0qjxak7K+1Ebo1ieyrkJFUoqTJsM2nNolYkf281GAO7pp+BkzZyvUxT6c7 bJlMXA7bUFfEtIEw+Osw0rZ1RASz2N0aFrVISS0O9xN/TFlWN9N5ukA4cn2rjzxCAVg+qTkacZGj rCP9graLLlQOkF+pC5atmThyzkSWPYf+2oYU84nB5w1RwUxI4otUS9wKKkMgjXtp7d5S/fKAFVfG ysAivsHGSG5R4bKNY5QwjJ/6968hMuVya9rih0BjYQPX9VC4yTuyUtsn7qW89ivRqrKy1qYT/xQ7 bY+dA/ciLOIdM2mEWvwZgfCynEcS+Pzqx0w/WR2HUSB1r7hKIgyrXjOC7egRl+cM9BOFaQmJBL2F kJcdNUzEO7hPsyDvlbZ6G8pdkEZDeQXn5MtHpFw/KMAmLXuBxBoPMTDD7XjsZTR171GOdb1mcll9 19pbVmD2rH4l0dKbw2J8qX6swvH7+/eF/l7k40+b4jZQMmHSkbbxrHTbTTSqHrVlk6eWZ0CuujCm 9PrZ3s983CBMJnA3GlCkvwK50OoQFFweh/2Hd5bBoXZUg+SshWddUSlOoq5nZlfeB0hcXfpYkOwt C/TfGMV56JMsRwITN/SkKO04Hgc6fQc6qkEpag40qHmTNgDSWOfHuskqDoVpHBGBPqAE+saW6FMp YmcxpAKVJKxfvvyIEUBAlomVPep1FH1wK0Q6punWKQasWvG0qdmdjmDh01QIff56cAN1sefxkwYH k51x7eB6p2FZ/DN6fSB2fYfP7Yg9HFTKcj8ef1Bym7/QJRHw5PbTw1A+RX8sNM4dbuzQFX1WsaXN J/F26uB4ePpD5ukYZ6C/Fenm0EsDQ4ztrXPvoGT1UzkkHNNGS8EGXQvW5SYsScQWcO2l4JI3V9lr ayfyEkpYTAY/goJCjCLUTpecHTO+LW5xQMPp93TqgereowbY0WIDoU1978EVVQlcZr2XjnsoyO8u Tj9ddSY/bj52JU/ncZVEX+pcvAqiuo8L4jeeM2zQc8hBW2zvvlUFYSSqrukjrKIcx26CC3t92CyU 3344G28F5g8PpzlcvW/zQevzj8wXNI+0XkSEDZp9db6eJ0bCv3oCDxdwv0CA9wIAYq9XYqvn64RM lvol0JsLKJNQ+10znu/ocWJpvhlWYvvn2tt4Nb+V4NIZGmOZ4p9dpD0L/wBawvlgvT5bDKjEFIP8 1OBK3j3ho7+ai9XZqauvpF+aIBvqrzPZ7wj/fiyKCZpWcstSDSvXfcRhBBRkI+o86RC7vs0SOSqd T5rhbnqyil3D/1goL5PMVEoW00401lLrCd+zkkejZqK0Al6+zkepngWwOyEQAlM19owEMIaNM2cL dwEfWOcPpfx4Nxzpp36wUaaF/yAz1VMl6a+ovf/lIeFeFk4IceDOA0PapHAUjnWnInce8cgOdr2B p134X8lSBSmziEVvJW9sW9FP3M9Xou8+TaWQgkT8RkhzP5gzLkRbfz/kxE1m6V8e8n77J7JHmnK8 T3XM4sxf+sdEpaE6oOSzIRDT1NL7d5KC4r6bI9icoLS6Ug9fJL8HMLvOwFtrj+K78q8mqb0ut1bY fTCEyh39fot4pOBGhSJgBXjXEnDKOXvzM08S0rBwFVZhHHbtXf5wHNuPnWYFNXwArkCBPZLkrB8G azj++KGft7tP7KD2c4asdVZuzSKiI0UCRThyqY68yeLdJ4I5raRtfygrShHo5hnhUuZ+vcK4mZig MN9d5f2ncdrtDmQWQWCcJXsWoVUbD73fz9KCFSv+bJSVWtvGCotvRZQJkGCXGX4GywfgzwJL7Ia8 hdL+E8NMKcQ0Xyjqe8sF45B80bSzv/nILgAZezqqVHjgL8XfTvWDugeSMEZtd+XYVNcQ2r4hh1fV rfqgBcK7Lqhqik31Fcv6plYuZwlSdS6QLmFbGJmrM3aeRuCSITKzKv8b2vrPeSeQRnn0NYvjwN30 WdBH96SMxryYnzbcNbwt2cwyb47TC1ABhh4VSr8+dSAi5IpcfVH0lirSnmJn7iqlDNXk6nvEsXxA WMiUtohOXx3BXSU/ZPIHO74Vu9Goo9wm9l7aCiAcXXzF0Ke8GthcuJ8vHve0eeAu0XqxqgpwXLi1 Bs7OfGoNoC36vJNAqzCLaPXl5CJSSWuOTWHKPsy617fPHbicLO1I6pdea9nntSSamFVfisjxI3MW DfLj0R3udqh6X7qPxEX0Tzzlt+XyU20zKZgt1cDXGqKFDTmpJzQA4ko22drmws26lRXIA91KuoFZ p+BZ7czB8HyiwOzzWrBGA0ReUAV27py85PBMPJlh+gFMcG03zPXrNqGch9z8tFh/1VAls62/6Ddy 8GfAkltZyl8q/d8MRiDM5R2RonoC67YJl4an18W+qwN71gXOA5o8XbCa+7iBuJz92/d7GpMkDIHJ j/fOmyetG9ZdKfNEfWtcGTZ1vz9G+5odQjEgYSVC3RErKMREr5K1kR1mUdZiyHiJncWlvIAum26C G3+Hlwq9bIyE1ECmS6ZIm1VeE2VgycYhQTADzIYxLBKT+KjJiMaB32C7+w5VqoeFlPKK/DXXuH// r44w51JR7mvybF594ZYYds2yqXdrItNspSz1uU5f8DQ39F83vW/JBmQ1zv/lcuAkZdv8Uji2OxLL obq1EFFvP3+STnuRi4JZjmoxVCIBnidcHN0hq6lNDdEbrv1BJ9HxN6ppWUJHRsydw4RZT3ZXpXj7 5M235BkgZUyU0XUqfv0mjBIx5dd0p6NHmkQ2xo+op1W7dJRzfcRw0+sZWEwFC6mwPc13v2alCppr yml4wNPJ4rT+lfKt7vZrKM3d4zPFLqxUTAnP2f3BSm+j2aItYzm+Vybw73ITBU1IaLS/zgJ5nIm2 rbIUyJHdfedhzJ46x+Xv3jcs5Nu+oXZ4I8Qy0Myoyh7G6gAvU5rA2WwB7cR7uG+4Ib/quG/oAc+b E341x8TpKcVUIq0bVEf+I9q3+pvJ7dCRHunigoZzeQUfmqePNfN0LKuEn1+MVb8wrYwrty/3fpRp kC64tuZlmzVkdePyIIX69uw4IDqrdAjvPNRMLB0pxG5nrjf5iIP7qC60L09XpQdOIKNcuTgPDRw6 uVNwVaaftCIzLTmvK1qcubxea2lec3W63wzyCJ8pHO3j61l2uUr98GyqP0IbjhMe6sUihs0YB1Mf HFCnS71UcLFrQqjYs91ZHbNNBZSYfWxxCChRHflqqR3ZEpLyN6LUHXB99z1S71vcsWuWy1osz932 RGY+k2K6NVBTflCNylerKecDr4tjkw81N8j/7oxzC3rNGivhkTIewJtyCZV7SRaeCJzODXfTIFGh z68mTx3f2tuhGA+k9UU1OYLLl/f1MSQLXzEiyd+ydFsc6yTAYRtXkvLjnwFh3yA0V9H7rLx/P8nC iunAKO593zELp4AKBBPKMY0saoxvpZtddejn+YC7dLQXLavFrIeS4OUXVnkpoQU1aUKHLaiiOZLp lt+0O3aie7aWtihUXFQnvZD4194rsZE/v2w7SdUyrYWelW7s0IJ8OychbrGT3SwvSAkcXWsSDwLw X13XM/qkwIzky2FoovpDQDBNbaLNFTeV/oTLoNp/EZoxCm5kkqfadB4uMDGvU28Ut0xXOz/3wLCu iFeSrlo+Drn5Yu7NZnVKYy4KOT21lSo+0+VuazH96fB3wq35PG9puYjeih8Gbj1iHPg/XUJhuOZt ehsJc/SAhN/Z0QK+kXYLDH/k5eEPyMEADNfTZmXMvuDLpbqHwU/jIDpikOYhghTtcbRvpDRDdRSS U4pC+9FXZ9ACizUPzH1lFGlQs0buk1jzRSYnp+wPWeNE635Zo9zXG2nuLXwYo6sWmufeHpJLBGC/ rS4pL3zLnffVbMQc25hG12sGq6Gpxw/LLxZNMCBg0JievUQ3TcQ5JK6n6a57jb7/WfHUtzUtvaYf Qh728Q639I0tOVxvPe1wtwtkoOBA+ouVDElxhqy9Tn/FhNSyBHnQIAfrLC1lxpp/2KYvK9halNgU +KPe69LEGjFGxNeIMGMcJXBOVsUW4Wo09WHQCqA5fMckLi91kZEy3r7WsEuVouiF+2NpnXl5gcZY yBgv/9EnfOJUEHcC/kSIcMKUR64NdyYVNmOgHthLVHPMhcIrk3XPPxzKDj4FKJY7mhi1pLqOUiGM 1/L/4XjdtmAM4cG+wClRetoPHCwV1PuobCAxSdyRCcsDrcbItMiLtnc5DK6B4hK1Xj9tGKjpME18 M1KTAH0xP70UpEDGPb14A/Ecldf3q6K7GX6vHn/aio25Fqs9+1mgmABQ1C1rg7D3mJ0ckNRiexdd KCG3JuJYpB0lJPhd9zVxyNVwriqGxVBudweNf8IrAHzscfMvDi+3A7xohLJJWK7HRNC/ndxHMvxq 8PZkrDQVovaQbf+EBZqBe1thSH6N2KbKKE8kABhNrFHltnt8vMhNcz/9RqQYRmmRLhayTs/Lakhx XIfXj6jJndmo83miUReEFVlxwxCsjNsckDkX4MbQVsfTBHMyPXU8F75pAeP2CLkA0bKlWbbVc4L5 YxYBLNQFbJM3jCfdKlYh01q9CKWjxtoQZeO3SzfHVUiITFxnc8fxj2kIUKryilqTXBSurXTjjXvk mACBBoko4KGanV7DTBqmS62mKPs/J2kIQJ/JbRSQyZTzV+DUsfB0uV0KW6ajQaQ6yoFCCoVIDqeD +r9E1WeKGKvrFjzy/Lz7BEo2ymbE0xgBOE7XYdKXe2nUY71+K5p/IkubjPq2fZiwceowlRDSdyUt cZbvpRZc/vaYm+hsw2YxrivJr3ez7Be/3+3OMEZeQs5GrSitXbJLXRtMUoKjU3fK2sE0mc3aVTc3 QrFi15AtNyL7Wy6lzMbROkYxwMl+UrJ0iPAfDMpsF6bYr/sV+SA3mYB+1MREVLo/XJDqbyYVT0Yc 6w7i5vG8uFjKi/hr1Jie5vp8UuPQdpawPoxWbLQz2pEpeG9Z/vlNtvAwq0FflZR9Hiy0R2PfjGMm uBfjOwNzByOi6kKXfgMxPTgMwCLncOjGng9DZYG98a1paYiI8bf/Z+KqpgMKGkYg0dpJzj/m0WCY rqTsZM0lRsXBpo1jaOQYAxfUIvFKYztuAA68gm0a/YrJIBqqDocTZJVkp3pZ4r7ZZ6AzeHoaZf7E 74SUIlp9ow5Rx0FJhLyodHgP0JlvJtsPeYx6b0W3dqPDj/RqHVBeW8QKqSJjCcgEAtyTWmNebl2f e6LlunmSYqm3moX0NqLP/wEeYBDghM1R3+PSNfFTmiaqjwogHcnXNMdM72B9nx+Y+oT+fDRHxax0 HCYv4vgTs807cZVf85JuQl+WatT7YYXP+KiqX90qDM57qrzwLtcOf/hRig5qnj9+ksKikNdITAmf i0SVFXQHC+/dJ9Uygh1acgIHUfGVIhTupF09LChEIy0bmwWRSY9swIe/wccFl9bZRfNpC4eF1XxZ DOEOY9NhlJANvfh3PnZL7qXRa2PozfDYHgrHUYk6MI0KsXaN03CNGkPEUxc80g9ytkpsAd+TzTD1 WfcYV2qUCkST49D6Wd0mMJ42fAakqB4+drDuhXzR+bHvGrm9fw3/ZBI5HGZzc5PGCOSqUWCuvG7T fuYHUMdFwwEtFoy0ySgH9gTfsaLll1ZKSqD78tdEAVTBXGJj1n+diirnUgKAFH2ubr3QP03dK0IJ xZ4LBQ9PLah94xYFHVN43uypBCJOBxKbY3m6kLLCtyJOW2YCt/tbu0YOzKKHGIIR8WcfaVzP7c1P FezRlWgn4ntbt3F3GVWZYqN6FhQmd+ym6BUYR4BiGMs+/0Rn7YnqbkZVe8IwvYSRmaEO9z8E9I1Z 7bnpJpCUXucDF4p+Ohqw155sf2eUrevX4rxBj6WkV260495kjKZSKNlH0wdPt9mdTA5H5WeU6V4f NxcjdbqP7C6+KqnHa2dGePxZ8Lyhd09Hj9YzfCvyzCHRlGX8ROGRHpxaE9x6Jf/RNJz+zYlzhbzs /LlDnpN9JFFTsAQeMF6MfY3F7RGiBPqebWwFR8CsMQ4W8XPIOXuaKYyylOYb++Drw4CK3Vv9LFzl +A/fk4eZOHQ9IhX+EHwGNm4GWWESQNg9Fc9yUpyj+xXbQDqttvFID3u4MWNV31VQ2brn98h5F6NE 1QsfY6Dzcjey9H1CXFLdllcrBnF6mEar9xYpEyRNXLsOsNTrckLqzP2dnj4ACRICh4bDxoPZzcNW xXsvW0W8rOJId0P0vUoVruR0GUjpGX6rFxD1S3WssAnqpQecSJ4HE9ZbrntAw7zXL6aDxePQmjS7 +S5YTXFS4nKMOiGj3n0hx/yo6Lre2tDh0S8R+b5mb9Wa4NMTuAtGA9hAttlu++H1VYQf1Pj9TC0J 4/zNyetpYD2mAGW7UCWjwVesT2Yu8VIzLRmU4bttf2kf3/VE0YwCXDS5oAHkH85ufacusLmu17Kj vN9gqSnhIZxHH1nbUup2fz0rzfgpN9P1p4oAkjK0/NSDw8bZOSIqetArZSAVpg/SktGqowyg+O94 Xd70Q8ASaC+hTa+M055K6w/oAHSk/Pxu2nvrvmkqQ+bLKAMKp484IGjHSNVD///69jkgI+4IFnwA nu6lGc1Bd9ESQz02JDsXIwVvm3mTtwIgmlm+xgASGaEE36LNHKijHNNeZjPYGS4ruUE836OFzz4Z tTWapLGklaz34QdaIFpfombdnV1rQEvllFqeJ6DVo/qvaS7WzKqWXyKfPF62Y4oeXYXQPPe6sXtC xDwvU+s9nroMCX6VfJXipzRmNYPEycByt+Zc4VlwG3RUyGJRFSXpYwPHm7GTV5nRVvbFpFdtqOtU WlxA15+gcXG1fndKEZdwq6n0zzqpjP0mSSmB/QJIVeMpLmF7NJo+Oe/xOLdpZXf1jI7lccmihQVE 1tpqKZuPZm3DojCoSc5nbQ1ka7MXmUIwVE/Hoz6SlyjuNvkUZm8GufiIGf+Nzp6hSmY1+2IkgGWa l0DbdT3Cgh/JtPLA01D8dQoxkb9Ztx4NH3c4+3vBZ0Wu7N34W/E0GaRjgVbie2D/Tpz9yNjlGBpQ ZZBA8yrD3smw2NrGLmuG+ETQHQcoCKDO/sM4AAiYNvQXEXN+uuZuru3Ndh/ppWDwh/1qOP1kfvgf QI1QSY4EjEPwgV9EJ59Q0P+RpiiDzxa5D3/SF4vXfJ9iuY1Mt3V19DMchnLnQ592OqOEp3s6Exr7 th/cnhytGnZArdqtl/GU26TrvSuHH6QQ1gY1w3RQQRS2fuNZUtJPV+ImLzvTeYMtQoLUrBk8EU9f 20UDRCnAruVNLpM0YqoqxO0uUPCCCYM1RmAfbGf4+foDDRE143uk8lYfQVSSlfTy1SOZTY6AyByY udyCsxlRRG/2aAYbe0F1LMP8Bo7t+81Lyad4mgf27kxzDb6O4MMFm8rJRSYW4Z0x6WoAwK5HCuwB XSgRbXzA7R/tjyH1seP6xH5asIXCu3OklsXNmycZYjlRqoL5sABGu7HVm2OLpgEhaHLAEx6wbfcB bn0bzkudXZVhswT8f4/rX/wSGPLiGux9nGJGdl3g3HocR9IRmFqwwo7zwREhVaXtyVBfQqFYWKUA 8KXjyH0sTYlpr5/rg7OBSjjUAe4GwKPB5489Flm5YbnTqLnhnDJZf2psbRvaYcM7upugJbs4Fvcz RxGyzuOF1WoFQLSTm54TQiduwY6awsD197ugIKWQiYt3jkY+UWh2mUUpYlGNTN9aQobtH76RZdjj klFnCvKyzEjDPzkukgEunqFTXPM2zMxPvcZ1LSzKGwwcSkLppjjfVeAQKu4zX2m397JudSPLKH6j VZMuz4dqqTcZFB3krSCsQ3kos90MeESuIAjO7wAdXO2Gyp9Whfmar6v6JI4gvS8ON5RTa6Niegmv I8+RzgWl957LmvGefGfrj6p5B2hEZ7SUNW0O09Z11sdHa/sCsEBUyCiXgUDwmqZe6mM/PvDR9AS9 yfNP8OseoF3PEoH5 `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block pBqd8SbxnErWrX3lyBBDaDLKX8hSp/j5Yr+Qm9jRb/9JUTybH1McKspWz+db0YzfLoM8Rsbks3xZ F0QO+ZZlvg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block H9nfu/oUf72/R62OBj/4D944lb73dgO7fFOuMJCE4aenI7iF3utXSTO4hpgrQ8McaV+063uC1I2p SowtO/PmhlxRipVo5KEq7Hhzbtvt5amDIBC05YVti4pxjbEI/kmWeW6ApomatkIzigzghecNWi3O dw5/lv3XsuSXKGnf8V0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block LHYKr83oHemqUyK1Wezwr1z3qiqaCVVbCTepzFi2rZrXgOFTcCRhqXcHptrNPAEIVNUU983e0J/f 0KmoDwapS9jLRSEt/t44AcYzVSy/ai/iXQJgng7HtLlp+4d5yiOHFpGB54L6O3dBpou3h7caNhhL jjFv+2NQ8/vJ/xJXwO5fh2Ph6YYguOVQ53PyR/4efc4uuMmB69VXQ320viKRtmBbQCmyLZzeWtFu D4qzTizu+7+B9LccVDGFdS5MPG9ajzsWHD/tFElptKJXuLi1qfJlX0wCtTtXoY+3nkHdj+d8GtPf YHFzKsVl3XUte66S5MbnjiWHmaZaMtS1k7u0qg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 4MafVQvjuuBxvIjR+OYUlKEesGBWmyoKTpW4+3dmDKYdKobe8ekpI4KwM+KYTh1JKxG3Qgsr94sv sXNAR2TjWeHLAvJhva65Oh3N+FSqhrH0zjkmu9XvgIV/UwkRDNwOx9c4++PMmrK6Sc3dNZpoycaC lN9AukRoCBpCWkU/kGY= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Oe9rX9bCQUY9pDwkxKbbIf2ys0cqImU27qEFK2Dw17YylEZy1DE0fAY/RnVb+EPxtWACfGlXlONl m+j1F3QtQOlCfFGG+seFfsBQSPHUmFsJmINuxeAGpMhxfKpsTFjDqKjDpQa8VcnDwKWm4aO3goL8 ohfQk4XoUdGZKXOs6aDCwCjQ3NSG6AcZNW0ORDZyS9Kio2rZOPAl2Iatk0VLalSOSKS8f5tT86ig hcckTERcoJMSnJHpKMG0Uf46p6lF1NxyM72QA47lZHQTdUAqzyv8wPWp/x+9NpDScFU+0BwCqNgR Wwy5LWtdGsu9PzUszKuMs6YlHHcqBdvP6pV04w== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008) `protect data_block ugPchIic85pVoazhFaH2TWuQjqsMIDhfmCLDBUOtUS/RF04DCSHl4KkxPTtW6P+RbyiD3T+m3kTR N0N334mL4z3weuQnltN6rjwv5421Of+ebjf9jNPWmR9lf0e4KC1P2a+RqcNXNDLyWLeUSh5xhG/Z 78Dc0xYUHiF3d+hrOZnBHDBSzBMBxH85jBmUl3hJ6N8TJlBFLvzDJLAwx9rMqd+/ukKUbS92XXmq GUfEtXOD/kOjfUAMdbSYK383ZTVeO8P00Ys+990ShfmBjW11X5zfC8a6pcCnYMWovhs5zhxlg5VY 5qaNHLAk3jG98jGzfgSX7h68H0TVRR7JEDFOWoBp6nHeaNm3GUeQnBHvRRf9iGTHwtNoBo20CT3s B+8CdJKTLLUzk6qAj2GsiBGHS8LnYKmNkY/fLp6AmB2/qs4DlNFJIF8WLDrSqDSxN7vLmxfW02dn 97TZdyIIRU0sSDWmckU00Bj4DR6lVWvrorzqz+TKptQht1fc7GrTmUsh2hItQeA59cOw1AOmZDS9 1wq0ZKLVSXAjdB+CY84byFDq/ggnql+ym9df++F4CndyzeHn/77aqPKlsW1vloWWAkuV+/oxdhDW p20TyTT2O/VPp3m+EzlmnnWV4xK70h3N6PHM98xVk6mnffhh/Vgh2FPYUMBhFoA1R5ZkVo2hBFx+ BdBPaixrD1Bh0/1sYSrIxRoyOp3yESYfh6j5q6cxlNTa1qH+ifL4xeUh7yFpIAKcpGKV/BHZ4BXZ dzcowFS0zr5D1j59GJ2fBtclaFagM874kSHoT7saPkMwJZzu0a9Suyo2oyHeDY5u0tqwoOjIxSPD LgfMjS5eI/7kq2LRK6vuUkw4NPeUXfLEpGv5FCJ6L5qj3kBW2g6KAhG87smejtyOyPsvsfynrIc2 3VnDVEHbU7JdT+65asCO43n+F2twwXTbRz3siKaGFW/pSUKMJST4WLbItR8/WK8o1ze8PIiuzlcV 2q4JbKB8FDK4mLtzmIeYo7UTwNP6U9iXbLmMvu0dzyoUw3NDGJK4KUCMCVvDKN1R/+YL7Uwr/kfr H2I7nTHDRk6JDcgnN9lfHUT2S8C2BMkKRraWkqRs0K6NTq153MMgQ0I68tioSH/TpTwOz9oXVKBC IPIOjB4kXex4kXwRz23kXOxBtWL2ufKqg40K9aFi7BK+LFkdT9TJGBCwlY11kGcbWle5fHFUxBgl D7qMX2r59mWmGBSSP9gWsTMEGB58WJb0FCVJzJGA6OZLDvK1GTVkE3XRxGSmgNPHSS7w3jMJyMM1 LUnr75CCm+QeHuKzLZmM4W96dN4nPXd6yqiYEO85iAqDcN94rfIuZjKzOQpcTx9Oi4DIbX9uESmY tjGl70Xxr/adCaR8ilSvqqc+b4MBKqY7ELJDs0L3vXhscTGf4aQPSq6GF+yybBqE/m0z770fLOgC kzFPyfhoCNMoGzjgznhNFl/K2SBBjlumjwB4VoL4kPAv9g27PQzII7LCyKyJowsuyed1QFyLx6e0 zPEPygamJ5b2aKJfHjhq6Imar4DfdI9b/lJ2m3mKH5VW2TviID8sew7r/S+Cqsd1khcH0dn+JSpQ Cz5CskuqoPSTdJzTOv3pTxDL59oUgopc8EhlWAJY+mQaF0YTUq6eOMJWIqiTRPuWQs6VbYgRaUWq gGyiyprJEh8tjGjzF1g0t47LQBCmfF+ET+Qos0n0Wh5P3AuYe2d26zA4VHkOum3I/l6rLBKqZWgw 80FOjGL5rFavkxULg1QQ4CE5oihzlPEto13KkUan3UDd4FbgJCBwxe8aBRFgid7TZjfFiKmhUFt5 VQdmXePim15/U9KY4mMIYrnEKT0toYoS7SwJCXalf9S/2xU0+tvNWpw1X6qO/7v3BrnHauRDb8p7 DXnByUOEvR5Iwn7KTkPdDsC19IFFE44KJQW/TLM47NkLTnUgjtpw8GJXRgECeGgmVvN4zDWAz4kH JoZvUApvZD/k60yS9lZdKVETDuGnJLMPWqaE9URGx1F68zV/t6gNNzi4Vbw84HrncqaVQ9wkyUgz NG85xmeRL3PM9bycBzo2/5tEUhya/xB50ZheKo/wFA+vGxItbWD3A/cZCrWTA58Qp5cdb0eH8meI wFkrjyP9iCxkcXPvTVMY8oL8o5pJxxGdMvGwC7jjkK1ms7Vqxk+flNpQwFOxc8Bhi0iZ0/TmPVEf F+ZGV5tPUjYRSTzxofFD0jffamlYZQpqwKkMAfWbYnog1yK+fbQm41jBZ/ovWhcEWoIbKWZIjFSA OD5IG/kjBWkEXyU9LTohftglq69r0maNKbr7EKYPsDpvo8izUbasMLapY/Ny14fG6BWgAYo5xI4s djD2qS4vNfqRKU4rAsx+aRpvVQxZ6OeKvHYxiqiIPhOi8yi5g6zUu2EdUUni0ErRMnKL38mmI4KK 4xPf2PcduRPfhljJVhFLQAL/Vx9rs8TI2ixHSpthP0bZl7TycX1Ef3z74wUQ6nP/jp9Yi9pNL4Es OrsoIJiJrNwmzskoRB+FpS0XmnGK+WXeWg8mUkqP5uDqsrTxbhy1nUF9+bxAHJTjfax7I9UPhkOO g0Ms31UeKJczoUQXY4xQ2756Cr+BoXCCgUE63OOGha4EZNIFVDjshALTXX/K1Zamfq3M4naQOWi7 h36LS6E/7kjsvKD0qig3B+bw4eYn9D7xp9W/b/xnQX1Y6b+KJI1mq3ewFW6FWhzfiushu/g1D3BH IVDnqB2RNE5KByrzrzTWfPXtAzqwVypuv0uPzMYjP/HUWBWWxaM0698XRYq6tEjyEZmrbmcmdddB F+978ctayhLeGND3gjJzMD9GVyWbsp22+eKzIrPfgf+zir8BuPgUT2EfbWNhBLNuDCTbpqX3h5p5 UQgkeDx9fuGyyfEwSY01Gj+b0y0ZfFaPQ8GsQKQ544ltOq5D2c2hxCm8+bT33Xox9Byh0dE54yji mtCKhyFgjWGN+nc8kZemzz58Qc+tFgq33sNTvW+u613NDE6weCWYbSHGw+zKAAKUT3bn5wnjKlNP Za0+LvGGrSLhqhB1E+mDbzQz9WPa7pk2U5Yx8hXeWw49WqeFimySWFNJyPEM3fxsATP6UzAn8oSB gaeOEqF9ZAokKdVC3hxFEdR4hES9AH5L8QlOcAwytA0XEPo7+VJ1dvQy+CUJFMSViL4UyQ/1d3w3 /JflFzwiR+Pqp+4cC7R1OcxV41N/Xis6AjZZ+L7AUqsfgANI6OaDHJs7hPXGw7n3rtuNAlK2NiwM bWvK56olPYG7yuoHmsKWkg4wJLoG/MjMFjZEijGpYHYAri6CzgPrNOGFw45dmw2Adhf7PPKe3wyy LOw0Ka9N83vjMWPcpVP+2ScLxhfRWLsSQwqGhh8AaitW2OiTx7ekbXijvvIy/TeTns9LEnf2mN7s IBe+4wzrMc5PmHPVAy16ju/wQ6j1XAbp9cyi6gY0S6FWOq1l8lKsx96z6qBwWwgxdynUzi7lARod UBJaDyt9i7nIhqjp79HJziAlaRo1Xrnt+LN/sCHD7PBmqF50pCSW6YzEuP164twgaiGlAi/yYTc3 kt2l9rDpHVSNaJM0oz662UavJO7BxnuoM2PoAzBcoBY78upERvNQBQFzOo9XtFM6zaeXPNJPSIJz H8F3j7maBdtYWMjy4sDalZ7Fyxlo/lRm19Ds8/86OjGDBNR9PMmPiZAwnLvtNG3yp5gmgsW1sskF +jyaMoW9SFHOaU0dQ9hPXG6sflnNACAOh4LqrSjDxOdDGXJIBbCV85aakvibPiTbvRihxfcymks/ F3Vg2mB0MLQN1C41ypwTN41Z7iy6mmfowNrVB6suL0B4C23X5uXmksOWaa7Fqhue8voYHNYz87AX 1CmUnsx+ESMgq+Cnk/6CljrQ65N4INHD44SXvqqsH7KGdCK/VJXrSrd2MBqWddVIeoLXCuqYwOxj ezDRKd9jCIrgi/Tp6uGj5vAaqWNO0i6KQ+V1odyjNq7xhDwfSyL15I44zNRkGVJd7ttEs2zo+e9M tTkR1igHWulM5TMUdbMdej0p4q9rY2Vpez9BWoTMI+NMTosN/VBa1uoXg3e1i5Mey6pH68hXSc/y OOl6NP0lAsF6r0vso9xG+KIJcJZ1ldonn048etdsDOsRodP/ZiitgPAjFW8b3r38t2L5uZfsEwWr WnyK9Yy27tLFMgyfeBmKMin/bqqg+xVK4GGjb8oravkTjBVW9VCYc8nzEU0RlL3Kpd4DNscR6Chn fBK2UambbZE0jsrc/gF32wOzEjsRYq2t/NxyOzmZ6TBogtMcqTuJUWvDPcmPB7KFI1xve5KpTnFH b+AGLQebcHUjlzNAfV1aH3VZWNbetP9Op++JhuKwV84xkXVR7HuIdr3CIedCHKzWW9k6bDKi27rn MpImtyw+Jhjrdjb6GpTy/V9Mt35CVz0ilaAlzYnQJBMH+HbaZ2u8yveI4vSTZwSZ51DlN6u2fdtZ OHLA4WhhHPzW93UgL+Z3Yn1ZfGH8L0XL0rG0Wmi5mZuQTP2nfGHnKvEpiUV4uhQnQoO4ovh+VRRa UdTp3aYvOwcLa1Tbfxs0zG8896q6sLndM++95zagL7jOyZnFmQddlKEtNZvqtBxvKiZzUa4mudH8 2QAR8ewUfAWLEQ3FDWqtbRklVLgvxrbFK8SrAIE3lwO5YHXnIYHasG7Q8kSregntWeOmW9T414pQ js7uEMYE6soIZDftkj7r2aw7chVXBS+0VcsvZ/buAIoIiNyiZISKmnQvXIqWI/07V/7ZcJb1Mul7 iyxId91udFo7+4FtchFIwNV+RHeV4jxN6vLH4C160myH5id0QWN9saHX31nAzxNCLbI/8NdaMApz Pe14SASWdOWHeESkoxp32P0cnYi2VaV9dE8aaiiuHcNyfSbIndQdMiAHZADN8h5t9ZH+FUd3QsyF Sqpl5mKnkQ4Iee+gH/GeM4GoWyqumkfLSfvgpjCP+glKrnG8oarvPatTNQyzZxLcT3qc3gw+2qD3 w8EFzIZpIIllJuwyHGtnzdAofwWQ2t2QhS2nw4dvDoLydqXqtl22O0UF8tdDfG0ePnfvBF1OJ6tX 27vnuoiD7/sNn1iXhX00lrc+/ZM5JU80RRA1t6eEcOzVORKNgDQJFnuujNJH7wLQ7EHTUmeR+sAt Cv1KJNSHlVz/cK7/iUC0r6axtv8mKAVntAgTy/SGFP6roiqTVFExrldW4nVtzASpqjulJ4OusT++ eOEove+a0qg2KM7bTk0Bn45YeIrsgjan3/mlE07UhfoZ4SSfMl7EtZvaRR3ipwx6e71+8ku0ngoS qy8nRgtaRqRY7Jk1nDpdNe2iqhTgF6b7cG3phYYw/NBlzKtuyfmjvBqZyBwCH9LpIGKRL75azkK3 lLHg6yhSIhU+EORJ2y1YtfqGUmiG9Niiw6+HG4pf6osSsJn2bE5IAMUdFnPsLXbLZGp7eSXJQyFq 8hpiZMpF1xQkxYpxz/wk5LDqfQjjU8223MNGUH4fNxNkw+ADIhqqCZqHIOIpsfQzG71AfZu814ak jBTWPgeR/JYYF+PVJCvoxDhcgNL8XkOo2SzCjPaxCZFctxOkd/vDMvfhEwUgLbji10FGbOWGlVBq NZCJSflITRjCxkEaeIs4knmuyTIB7itLSpYbJz2ASoRzfyhtxl7lRvRhoI3I8JWSjaE0gzCDLYgi RDsCb2RiJ8XohoAuLRZKRVerVZcZf3rUI+0/K6zcdFL0klSPqnlt5vcgh5NgguKaJ9GabPGAD2NP 9fbfs1buAvi4uv69L1MqWzQSAvacBFAa4P9AT8u+t+aH0rU9nbdivFCa4QBcrbu4dIurpEOTlz6v Q4y+hklWTfxSNJo3P03O2zVvqDbYdlUSMVa47POuEwZqhOYuMHlll8NMSrwLAgOBiQ0GMCj71pVW mThWwktWKUqfgfmCpBcf1vO3YgSc0eGbNhSvwHYOyVLBPc7ySaMgxTOBJYVsnEQHWtVqoSnTAk3G QvSI8/SSOhE95/e4PurKfyZRuJflbeXE//Tnmh5ucLit5o7PbNAx+7Vgzx7QWY2EmPlpS1vNTfXL E8YrX+xRsIaJTA8fEBWnr/2c6i8iEenn++STYpXoY5RK8zeq8W+hGwmkOPtbQzLKXWJlpFkYVR4o nSLEIJnCAjsqDoVa8M9WHzmMxduRz+5JHd+ulXyw6HuVbSfxGl7+1vmiwX98jOJV/B2rnUnZ1WzQ frG/pjNNX8cyOnWkREdG+pBC3KYfZH9J7OP2KLdC7ZPxSR9hYJYqhq0xq0pyolbbeIXSnahGLH2A zQklbExh0qDnU0yp1f5U2TmWZDcf3jcHCvmJAm+cSplprSIUCHpP9yfCr087fRyet37UlxQTirZ2 Cu275t1hYOJ0EpvJYJ1S6sdM1QsbzskwSDC8Y0xP98UWE6/+AMHdv3GnE6SvwNZMvTGJkn96ab2o 5znQmV8122xq0E6e+2wD/XdQve42BvedJmozWGevKv7/RLHlK2YbqQsVKlDxeFIBunkkGOBmRsbL aBqwLRvIuO95OqqPOiRjf3RRcpxxM7y2a/uM3IuxuvLPfmYxV99uAcrvlwJkoiAnFLTlQKD7L8v8 0aeXoVkGq8/cq0354bbX7VSOJvu4cu5VUhtCS1YI7frRP2oJmWAeQRekteggVCoDflkDUqzUsZLQ tS+fjwPiGPLI1b4K4HZvtGwp+EUT7UUzfFeEJNhEPPa+GT1sHRDq43kuHJUO2l6pG02DdQwejKvE BgHQyX4JsLUlFp54yHA03+7z/+1+hVbZf1gG19WdyGmqON33qKq4fecMxXgb08hJbkLI/bzfiPJo GIIUI4ZgP80hbq3wJt3KVfhyMfbQNTfFTs1DiS/ZtB2YMSgErGn+A8gpB2VHPyovp1MWHUhPfsGl Cicec2BTQreiNhgJSU3tuYBD8HFEOkNuG8HxwffyjMrTOQUDf5/DcRSh8/QZN9aRP7vqMB5+ouLB BM3Cm3zzlWfS/lNhRsCrewOzfzFINfPGZqgmtF/1UyksiLB0VrU1KzHhWCMK6qwQepPPMmH1Ww+H dhP/5e4gNAw7t33+ciyoMyKCb/1I3sCedU6yjgejvKIdLhu4OloBAgbaBVAYhb2QP5GixZZruar8 K5r644IqRnPKDjNB2MY1tUwguYv2cPh3zYwZvI+maiWwHhQAHwjXFwx1y/zRxF9+OnpAHpeqga7K cmvuqKPjBhbGo0Vk/Dw7A1CQ4CG6b6M1AdZYpimNvVrzA7NKArpavLkGw2GCxuoWS2GCBqcumTKP MVGztQTL4F7W5ufN9sjaCh1Lh6LHjWq3ufgoEP3DK6R2KPwPrRnfEsTQLbdQS9SGjcpVRNcpQfAV i3OBYmpj60typMrGJyAP9EqSaOwlG6sWtz/p1e7AG72uyH2OT5PMSlQ7z3WCFYKRc/eI7/svcCLw TV3v7TH8B/1z+usu9X3y5Ad4fnvZ1jaSCKRO6KEjdKoIKJRsV9UnmMm8XyrUZtRcQpdWogyhqTKZ 3hODX4nK2UKq0ZPcoq4unvTXSvUW31Esqd5c3IcGDTMPHGceQHYmNfhkha6dJvTce7iJ/Dx4eMzW k5DDQml26ol8E9GGKeVa/awQmyAqtlmpvtHU/sBtxfrCTFmD2TcUGW6FdwFXMTu1MPwHJCE+Uwe0 VOmcC+/Mgaron1eLzMWV8XyW0ACztshoHbJfD9d9JsU1cJbGyOYQXu5pydYlv0r7f6HmDVxM7O1S rCuOYx2DZtSqmHzS1d8qCYlF2TkW0CVBcb8FCABSIM6caQ2aR+2MnCP+f/2uXHkH5acFGclk0M3n xc2A7ebD6mzZEOYWWxJBDElzxDKstwuB0ok5v2gwisV8CeuWAs8bjHOs5An7XdyM5g/9hyxXZivj fr0OMVLnw6u/Q+8rJV8/MoRSJ6wjs2qI8Z5MJSh4pBnHrwZbv2MWl+AIAMlq94qF4weEhBVNaHGH CfVPrMuRFwHVRkRhdFZAcsjaQBs+s+E3oenDYAe7Ko4bHmAA1sKKYLiatMXxmmwXSSCz6FewD4PM EFO9Gv7SsiECezHUmJxNcolWOsuk0RE9MakoNlaBgzKEkiDTqa13GwLnNg9Ck+cLCcHgnzIO1Njk L4b7LBFITgmMMm5B6INns4IdMbmaNO6KziwlBDOx22CmDUoV38m699UmEYCaUoDauHrMWbFAX2Nh 99QDJ0gI/4echrXMMbmcWyrizwN+QOYXN7WcSBMBW3iyy3ttsbDzaeq9/oPU18zzPAM+D+zFmeR2 zdbBrzQa9sESX1LphCo2CrKvbqZOJ65K3Sd+BlGnzi2uADnDnEqjwGRXXAnPihzVAbwbYxSLMvk6 bz6SW+eG9w6sZkC8M6DnGvKjF+Qm5tm241A6vyreUHmwA24lFL2F4DQ/wcOaGIxI1V/cxiaxxG24 bhp4Q3ZDgkwS12sHr+j/380mxAtPIeOyNv5Jc15jyBWwkCJ+pKuzrwu2la3lwDcbZaIRB3QwG7Jf +b1aBgR3kCCQkyUMFk+7nJuGWWpI26G89k9mbt7RGBKNhowreUdEkunfV3Ce6DswgpB0DHe7dO+x tYunTbfkcJvJCaDIg7MmBnaK7vEHSDIQ3vk1/JqRqFQj88Qiw5BwFV10oPymHswGDs5Y6PIHtWvN 0OdG7RqnNFk0sFTQkgR5IsxR6CcQIL7TUw/dBEwMvmQ8tO+jtpxMwOPKu5I1RjaTOYHWhHWp5c7V u016PT3exfxVU6/P2PRvvG5ppHbkirnTGwfDZ+0Z1HnVvBLbIeYkU9VlfXZdMcm7gBcbme7Lo2Ie NpSu2PZffaAlMGWZjninpfmmeGrjGRquaDcN3kbZA+M0d4d4v6QtTLCCZDKC5n/KD0pphYQ1yEwT 0e8gU+Q2n+LvWiAji6Ij6kRFmwkk/Ym2MuKGSakMztcBzZdTqCc22uHIwNPqU9lNGV64pnT+6O8s g7U9zg4/JzFhnIO8EtTmid/2CZhfhXsyAB3ze0Ak+sHyY9ad9eZNwnQkJ2UzOsaKXYa/8t+ZvTAS btPANzI6CtZktmDemOgTWKfrwG4Z77GYcEk4VOzTFeQfsVSqJ1SyAIMGgqQUF+pGk22sT6h/6xmx zv6T41noCLQD/2wf31d6iEkF+z5HA86qxKIduLnahwesrHJnZoQHLtO/hg6W9q4tpmy8dchOt3vR 7NcdOx9P1A9EUI3iNDQCD4ppzR08rxLqrO1f7wdD8FtZuyLGgcRceKh/9iBM5MYtFphzbai+Y/NT +30bD8xPgfqjtCtbeuAjR0Sh8WeIy9gDKwc52WwOe7ljeiABuBxt0WpaYOMY9vxWP9J/IyaUWi54 4bH72orR/xMzYfnJjD0qjxak7K+1Ebo1ieyrkJFUoqTJsM2nNolYkf281GAO7pp+BkzZyvUxT6c7 bJlMXA7bUFfEtIEw+Osw0rZ1RASz2N0aFrVISS0O9xN/TFlWN9N5ukA4cn2rjzxCAVg+qTkacZGj rCP9graLLlQOkF+pC5atmThyzkSWPYf+2oYU84nB5w1RwUxI4otUS9wKKkMgjXtp7d5S/fKAFVfG ysAivsHGSG5R4bKNY5QwjJ/6968hMuVya9rih0BjYQPX9VC4yTuyUtsn7qW89ivRqrKy1qYT/xQ7 bY+dA/ciLOIdM2mEWvwZgfCynEcS+Pzqx0w/WR2HUSB1r7hKIgyrXjOC7egRl+cM9BOFaQmJBL2F kJcdNUzEO7hPsyDvlbZ6G8pdkEZDeQXn5MtHpFw/KMAmLXuBxBoPMTDD7XjsZTR171GOdb1mcll9 19pbVmD2rH4l0dKbw2J8qX6swvH7+/eF/l7k40+b4jZQMmHSkbbxrHTbTTSqHrVlk6eWZ0CuujCm 9PrZ3s983CBMJnA3GlCkvwK50OoQFFweh/2Hd5bBoXZUg+SshWddUSlOoq5nZlfeB0hcXfpYkOwt C/TfGMV56JMsRwITN/SkKO04Hgc6fQc6qkEpag40qHmTNgDSWOfHuskqDoVpHBGBPqAE+saW6FMp YmcxpAKVJKxfvvyIEUBAlomVPep1FH1wK0Q6punWKQasWvG0qdmdjmDh01QIff56cAN1sefxkwYH k51x7eB6p2FZ/DN6fSB2fYfP7Yg9HFTKcj8ef1Bym7/QJRHw5PbTw1A+RX8sNM4dbuzQFX1WsaXN J/F26uB4ePpD5ukYZ6C/Fenm0EsDQ4ztrXPvoGT1UzkkHNNGS8EGXQvW5SYsScQWcO2l4JI3V9lr ayfyEkpYTAY/goJCjCLUTpecHTO+LW5xQMPp93TqgereowbY0WIDoU1978EVVQlcZr2XjnsoyO8u Tj9ddSY/bj52JU/ncZVEX+pcvAqiuo8L4jeeM2zQc8hBW2zvvlUFYSSqrukjrKIcx26CC3t92CyU 3344G28F5g8PpzlcvW/zQevzj8wXNI+0XkSEDZp9db6eJ0bCv3oCDxdwv0CA9wIAYq9XYqvn64RM lvol0JsLKJNQ+10znu/ocWJpvhlWYvvn2tt4Nb+V4NIZGmOZ4p9dpD0L/wBawvlgvT5bDKjEFIP8 1OBK3j3ho7+ai9XZqauvpF+aIBvqrzPZ7wj/fiyKCZpWcstSDSvXfcRhBBRkI+o86RC7vs0SOSqd T5rhbnqyil3D/1goL5PMVEoW00401lLrCd+zkkejZqK0Al6+zkepngWwOyEQAlM19owEMIaNM2cL dwEfWOcPpfx4Nxzpp36wUaaF/yAz1VMl6a+ovf/lIeFeFk4IceDOA0PapHAUjnWnInce8cgOdr2B p134X8lSBSmziEVvJW9sW9FP3M9Xou8+TaWQgkT8RkhzP5gzLkRbfz/kxE1m6V8e8n77J7JHmnK8 T3XM4sxf+sdEpaE6oOSzIRDT1NL7d5KC4r6bI9icoLS6Ug9fJL8HMLvOwFtrj+K78q8mqb0ut1bY fTCEyh39fot4pOBGhSJgBXjXEnDKOXvzM08S0rBwFVZhHHbtXf5wHNuPnWYFNXwArkCBPZLkrB8G azj++KGft7tP7KD2c4asdVZuzSKiI0UCRThyqY68yeLdJ4I5raRtfygrShHo5hnhUuZ+vcK4mZig MN9d5f2ncdrtDmQWQWCcJXsWoVUbD73fz9KCFSv+bJSVWtvGCotvRZQJkGCXGX4GywfgzwJL7Ia8 hdL+E8NMKcQ0Xyjqe8sF45B80bSzv/nILgAZezqqVHjgL8XfTvWDugeSMEZtd+XYVNcQ2r4hh1fV rfqgBcK7Lqhqik31Fcv6plYuZwlSdS6QLmFbGJmrM3aeRuCSITKzKv8b2vrPeSeQRnn0NYvjwN30 WdBH96SMxryYnzbcNbwt2cwyb47TC1ABhh4VSr8+dSAi5IpcfVH0lirSnmJn7iqlDNXk6nvEsXxA WMiUtohOXx3BXSU/ZPIHO74Vu9Goo9wm9l7aCiAcXXzF0Ke8GthcuJ8vHve0eeAu0XqxqgpwXLi1 Bs7OfGoNoC36vJNAqzCLaPXl5CJSSWuOTWHKPsy617fPHbicLO1I6pdea9nntSSamFVfisjxI3MW DfLj0R3udqh6X7qPxEX0Tzzlt+XyU20zKZgt1cDXGqKFDTmpJzQA4ko22drmws26lRXIA91KuoFZ p+BZ7czB8HyiwOzzWrBGA0ReUAV27py85PBMPJlh+gFMcG03zPXrNqGch9z8tFh/1VAls62/6Ddy 8GfAkltZyl8q/d8MRiDM5R2RonoC67YJl4an18W+qwN71gXOA5o8XbCa+7iBuJz92/d7GpMkDIHJ j/fOmyetG9ZdKfNEfWtcGTZ1vz9G+5odQjEgYSVC3RErKMREr5K1kR1mUdZiyHiJncWlvIAum26C G3+Hlwq9bIyE1ECmS6ZIm1VeE2VgycYhQTADzIYxLBKT+KjJiMaB32C7+w5VqoeFlPKK/DXXuH// r44w51JR7mvybF594ZYYds2yqXdrItNspSz1uU5f8DQ39F83vW/JBmQ1zv/lcuAkZdv8Uji2OxLL obq1EFFvP3+STnuRi4JZjmoxVCIBnidcHN0hq6lNDdEbrv1BJ9HxN6ppWUJHRsydw4RZT3ZXpXj7 5M235BkgZUyU0XUqfv0mjBIx5dd0p6NHmkQ2xo+op1W7dJRzfcRw0+sZWEwFC6mwPc13v2alCppr yml4wNPJ4rT+lfKt7vZrKM3d4zPFLqxUTAnP2f3BSm+j2aItYzm+Vybw73ITBU1IaLS/zgJ5nIm2 rbIUyJHdfedhzJ46x+Xv3jcs5Nu+oXZ4I8Qy0Myoyh7G6gAvU5rA2WwB7cR7uG+4Ib/quG/oAc+b E341x8TpKcVUIq0bVEf+I9q3+pvJ7dCRHunigoZzeQUfmqePNfN0LKuEn1+MVb8wrYwrty/3fpRp kC64tuZlmzVkdePyIIX69uw4IDqrdAjvPNRMLB0pxG5nrjf5iIP7qC60L09XpQdOIKNcuTgPDRw6 uVNwVaaftCIzLTmvK1qcubxea2lec3W63wzyCJ8pHO3j61l2uUr98GyqP0IbjhMe6sUihs0YB1Mf HFCnS71UcLFrQqjYs91ZHbNNBZSYfWxxCChRHflqqR3ZEpLyN6LUHXB99z1S71vcsWuWy1osz932 RGY+k2K6NVBTflCNylerKecDr4tjkw81N8j/7oxzC3rNGivhkTIewJtyCZV7SRaeCJzODXfTIFGh z68mTx3f2tuhGA+k9UU1OYLLl/f1MSQLXzEiyd+ydFsc6yTAYRtXkvLjnwFh3yA0V9H7rLx/P8nC iunAKO593zELp4AKBBPKMY0saoxvpZtddejn+YC7dLQXLavFrIeS4OUXVnkpoQU1aUKHLaiiOZLp lt+0O3aie7aWtihUXFQnvZD4194rsZE/v2w7SdUyrYWelW7s0IJ8OychbrGT3SwvSAkcXWsSDwLw X13XM/qkwIzky2FoovpDQDBNbaLNFTeV/oTLoNp/EZoxCm5kkqfadB4uMDGvU28Ut0xXOz/3wLCu iFeSrlo+Drn5Yu7NZnVKYy4KOT21lSo+0+VuazH96fB3wq35PG9puYjeih8Gbj1iHPg/XUJhuOZt ehsJc/SAhN/Z0QK+kXYLDH/k5eEPyMEADNfTZmXMvuDLpbqHwU/jIDpikOYhghTtcbRvpDRDdRSS U4pC+9FXZ9ACizUPzH1lFGlQs0buk1jzRSYnp+wPWeNE635Zo9zXG2nuLXwYo6sWmufeHpJLBGC/ rS4pL3zLnffVbMQc25hG12sGq6Gpxw/LLxZNMCBg0JievUQ3TcQ5JK6n6a57jb7/WfHUtzUtvaYf Qh728Q639I0tOVxvPe1wtwtkoOBA+ouVDElxhqy9Tn/FhNSyBHnQIAfrLC1lxpp/2KYvK9halNgU +KPe69LEGjFGxNeIMGMcJXBOVsUW4Wo09WHQCqA5fMckLi91kZEy3r7WsEuVouiF+2NpnXl5gcZY yBgv/9EnfOJUEHcC/kSIcMKUR64NdyYVNmOgHthLVHPMhcIrk3XPPxzKDj4FKJY7mhi1pLqOUiGM 1/L/4XjdtmAM4cG+wClRetoPHCwV1PuobCAxSdyRCcsDrcbItMiLtnc5DK6B4hK1Xj9tGKjpME18 M1KTAH0xP70UpEDGPb14A/Ecldf3q6K7GX6vHn/aio25Fqs9+1mgmABQ1C1rg7D3mJ0ckNRiexdd KCG3JuJYpB0lJPhd9zVxyNVwriqGxVBudweNf8IrAHzscfMvDi+3A7xohLJJWK7HRNC/ndxHMvxq 8PZkrDQVovaQbf+EBZqBe1thSH6N2KbKKE8kABhNrFHltnt8vMhNcz/9RqQYRmmRLhayTs/Lakhx XIfXj6jJndmo83miUReEFVlxwxCsjNsckDkX4MbQVsfTBHMyPXU8F75pAeP2CLkA0bKlWbbVc4L5 YxYBLNQFbJM3jCfdKlYh01q9CKWjxtoQZeO3SzfHVUiITFxnc8fxj2kIUKryilqTXBSurXTjjXvk mACBBoko4KGanV7DTBqmS62mKPs/J2kIQJ/JbRSQyZTzV+DUsfB0uV0KW6ajQaQ6yoFCCoVIDqeD +r9E1WeKGKvrFjzy/Lz7BEo2ymbE0xgBOE7XYdKXe2nUY71+K5p/IkubjPq2fZiwceowlRDSdyUt cZbvpRZc/vaYm+hsw2YxrivJr3ez7Be/3+3OMEZeQs5GrSitXbJLXRtMUoKjU3fK2sE0mc3aVTc3 QrFi15AtNyL7Wy6lzMbROkYxwMl+UrJ0iPAfDMpsF6bYr/sV+SA3mYB+1MREVLo/XJDqbyYVT0Yc 6w7i5vG8uFjKi/hr1Jie5vp8UuPQdpawPoxWbLQz2pEpeG9Z/vlNtvAwq0FflZR9Hiy0R2PfjGMm uBfjOwNzByOi6kKXfgMxPTgMwCLncOjGng9DZYG98a1paYiI8bf/Z+KqpgMKGkYg0dpJzj/m0WCY rqTsZM0lRsXBpo1jaOQYAxfUIvFKYztuAA68gm0a/YrJIBqqDocTZJVkp3pZ4r7ZZ6AzeHoaZf7E 74SUIlp9ow5Rx0FJhLyodHgP0JlvJtsPeYx6b0W3dqPDj/RqHVBeW8QKqSJjCcgEAtyTWmNebl2f e6LlunmSYqm3moX0NqLP/wEeYBDghM1R3+PSNfFTmiaqjwogHcnXNMdM72B9nx+Y+oT+fDRHxax0 HCYv4vgTs807cZVf85JuQl+WatT7YYXP+KiqX90qDM57qrzwLtcOf/hRig5qnj9+ksKikNdITAmf i0SVFXQHC+/dJ9Uygh1acgIHUfGVIhTupF09LChEIy0bmwWRSY9swIe/wccFl9bZRfNpC4eF1XxZ DOEOY9NhlJANvfh3PnZL7qXRa2PozfDYHgrHUYk6MI0KsXaN03CNGkPEUxc80g9ytkpsAd+TzTD1 WfcYV2qUCkST49D6Wd0mMJ42fAakqB4+drDuhXzR+bHvGrm9fw3/ZBI5HGZzc5PGCOSqUWCuvG7T fuYHUMdFwwEtFoy0ySgH9gTfsaLll1ZKSqD78tdEAVTBXGJj1n+diirnUgKAFH2ubr3QP03dK0IJ xZ4LBQ9PLah94xYFHVN43uypBCJOBxKbY3m6kLLCtyJOW2YCt/tbu0YOzKKHGIIR8WcfaVzP7c1P FezRlWgn4ntbt3F3GVWZYqN6FhQmd+ym6BUYR4BiGMs+/0Rn7YnqbkZVe8IwvYSRmaEO9z8E9I1Z 7bnpJpCUXucDF4p+Ohqw155sf2eUrevX4rxBj6WkV260495kjKZSKNlH0wdPt9mdTA5H5WeU6V4f NxcjdbqP7C6+KqnHa2dGePxZ8Lyhd09Hj9YzfCvyzCHRlGX8ROGRHpxaE9x6Jf/RNJz+zYlzhbzs /LlDnpN9JFFTsAQeMF6MfY3F7RGiBPqebWwFR8CsMQ4W8XPIOXuaKYyylOYb++Drw4CK3Vv9LFzl +A/fk4eZOHQ9IhX+EHwGNm4GWWESQNg9Fc9yUpyj+xXbQDqttvFID3u4MWNV31VQ2brn98h5F6NE 1QsfY6Dzcjey9H1CXFLdllcrBnF6mEar9xYpEyRNXLsOsNTrckLqzP2dnj4ACRICh4bDxoPZzcNW xXsvW0W8rOJId0P0vUoVruR0GUjpGX6rFxD1S3WssAnqpQecSJ4HE9ZbrntAw7zXL6aDxePQmjS7 +S5YTXFS4nKMOiGj3n0hx/yo6Lre2tDh0S8R+b5mb9Wa4NMTuAtGA9hAttlu++H1VYQf1Pj9TC0J 4/zNyetpYD2mAGW7UCWjwVesT2Yu8VIzLRmU4bttf2kf3/VE0YwCXDS5oAHkH85ufacusLmu17Kj vN9gqSnhIZxHH1nbUup2fz0rzfgpN9P1p4oAkjK0/NSDw8bZOSIqetArZSAVpg/SktGqowyg+O94 Xd70Q8ASaC+hTa+M055K6w/oAHSk/Pxu2nvrvmkqQ+bLKAMKp484IGjHSNVD///69jkgI+4IFnwA nu6lGc1Bd9ESQz02JDsXIwVvm3mTtwIgmlm+xgASGaEE36LNHKijHNNeZjPYGS4ruUE836OFzz4Z tTWapLGklaz34QdaIFpfombdnV1rQEvllFqeJ6DVo/qvaS7WzKqWXyKfPF62Y4oeXYXQPPe6sXtC xDwvU+s9nroMCX6VfJXipzRmNYPEycByt+Zc4VlwG3RUyGJRFSXpYwPHm7GTV5nRVvbFpFdtqOtU WlxA15+gcXG1fndKEZdwq6n0zzqpjP0mSSmB/QJIVeMpLmF7NJo+Oe/xOLdpZXf1jI7lccmihQVE 1tpqKZuPZm3DojCoSc5nbQ1ka7MXmUIwVE/Hoz6SlyjuNvkUZm8GufiIGf+Nzp6hSmY1+2IkgGWa l0DbdT3Cgh/JtPLA01D8dQoxkb9Ztx4NH3c4+3vBZ0Wu7N34W/E0GaRjgVbie2D/Tpz9yNjlGBpQ ZZBA8yrD3smw2NrGLmuG+ETQHQcoCKDO/sM4AAiYNvQXEXN+uuZuru3Ndh/ppWDwh/1qOP1kfvgf QI1QSY4EjEPwgV9EJ59Q0P+RpiiDzxa5D3/SF4vXfJ9iuY1Mt3V19DMchnLnQ592OqOEp3s6Exr7 th/cnhytGnZArdqtl/GU26TrvSuHH6QQ1gY1w3RQQRS2fuNZUtJPV+ImLzvTeYMtQoLUrBk8EU9f 20UDRCnAruVNLpM0YqoqxO0uUPCCCYM1RmAfbGf4+foDDRE143uk8lYfQVSSlfTy1SOZTY6AyByY udyCsxlRRG/2aAYbe0F1LMP8Bo7t+81Lyad4mgf27kxzDb6O4MMFm8rJRSYW4Z0x6WoAwK5HCuwB XSgRbXzA7R/tjyH1seP6xH5asIXCu3OklsXNmycZYjlRqoL5sABGu7HVm2OLpgEhaHLAEx6wbfcB bn0bzkudXZVhswT8f4/rX/wSGPLiGux9nGJGdl3g3HocR9IRmFqwwo7zwREhVaXtyVBfQqFYWKUA 8KXjyH0sTYlpr5/rg7OBSjjUAe4GwKPB5489Flm5YbnTqLnhnDJZf2psbRvaYcM7upugJbs4Fvcz RxGyzuOF1WoFQLSTm54TQiduwY6awsD197ugIKWQiYt3jkY+UWh2mUUpYlGNTN9aQobtH76RZdjj klFnCvKyzEjDPzkukgEunqFTXPM2zMxPvcZ1LSzKGwwcSkLppjjfVeAQKu4zX2m397JudSPLKH6j VZMuz4dqqTcZFB3krSCsQ3kos90MeESuIAjO7wAdXO2Gyp9Whfmar6v6JI4gvS8ON5RTa6Niegmv I8+RzgWl957LmvGefGfrj6p5B2hEZ7SUNW0O09Z11sdHa/sCsEBUyCiXgUDwmqZe6mM/PvDR9AS9 yfNP8OseoF3PEoH5 `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block pBqd8SbxnErWrX3lyBBDaDLKX8hSp/j5Yr+Qm9jRb/9JUTybH1McKspWz+db0YzfLoM8Rsbks3xZ F0QO+ZZlvg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block H9nfu/oUf72/R62OBj/4D944lb73dgO7fFOuMJCE4aenI7iF3utXSTO4hpgrQ8McaV+063uC1I2p SowtO/PmhlxRipVo5KEq7Hhzbtvt5amDIBC05YVti4pxjbEI/kmWeW6ApomatkIzigzghecNWi3O dw5/lv3XsuSXKGnf8V0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block LHYKr83oHemqUyK1Wezwr1z3qiqaCVVbCTepzFi2rZrXgOFTcCRhqXcHptrNPAEIVNUU983e0J/f 0KmoDwapS9jLRSEt/t44AcYzVSy/ai/iXQJgng7HtLlp+4d5yiOHFpGB54L6O3dBpou3h7caNhhL jjFv+2NQ8/vJ/xJXwO5fh2Ph6YYguOVQ53PyR/4efc4uuMmB69VXQ320viKRtmBbQCmyLZzeWtFu D4qzTizu+7+B9LccVDGFdS5MPG9ajzsWHD/tFElptKJXuLi1qfJlX0wCtTtXoY+3nkHdj+d8GtPf YHFzKsVl3XUte66S5MbnjiWHmaZaMtS1k7u0qg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 4MafVQvjuuBxvIjR+OYUlKEesGBWmyoKTpW4+3dmDKYdKobe8ekpI4KwM+KYTh1JKxG3Qgsr94sv sXNAR2TjWeHLAvJhva65Oh3N+FSqhrH0zjkmu9XvgIV/UwkRDNwOx9c4++PMmrK6Sc3dNZpoycaC lN9AukRoCBpCWkU/kGY= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Oe9rX9bCQUY9pDwkxKbbIf2ys0cqImU27qEFK2Dw17YylEZy1DE0fAY/RnVb+EPxtWACfGlXlONl m+j1F3QtQOlCfFGG+seFfsBQSPHUmFsJmINuxeAGpMhxfKpsTFjDqKjDpQa8VcnDwKWm4aO3goL8 ohfQk4XoUdGZKXOs6aDCwCjQ3NSG6AcZNW0ORDZyS9Kio2rZOPAl2Iatk0VLalSOSKS8f5tT86ig hcckTERcoJMSnJHpKMG0Uf46p6lF1NxyM72QA47lZHQTdUAqzyv8wPWp/x+9NpDScFU+0BwCqNgR Wwy5LWtdGsu9PzUszKuMs6YlHHcqBdvP6pV04w== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008) `protect data_block ugPchIic85pVoazhFaH2TWuQjqsMIDhfmCLDBUOtUS/RF04DCSHl4KkxPTtW6P+RbyiD3T+m3kTR N0N334mL4z3weuQnltN6rjwv5421Of+ebjf9jNPWmR9lf0e4KC1P2a+RqcNXNDLyWLeUSh5xhG/Z 78Dc0xYUHiF3d+hrOZnBHDBSzBMBxH85jBmUl3hJ6N8TJlBFLvzDJLAwx9rMqd+/ukKUbS92XXmq GUfEtXOD/kOjfUAMdbSYK383ZTVeO8P00Ys+990ShfmBjW11X5zfC8a6pcCnYMWovhs5zhxlg5VY 5qaNHLAk3jG98jGzfgSX7h68H0TVRR7JEDFOWoBp6nHeaNm3GUeQnBHvRRf9iGTHwtNoBo20CT3s B+8CdJKTLLUzk6qAj2GsiBGHS8LnYKmNkY/fLp6AmB2/qs4DlNFJIF8WLDrSqDSxN7vLmxfW02dn 97TZdyIIRU0sSDWmckU00Bj4DR6lVWvrorzqz+TKptQht1fc7GrTmUsh2hItQeA59cOw1AOmZDS9 1wq0ZKLVSXAjdB+CY84byFDq/ggnql+ym9df++F4CndyzeHn/77aqPKlsW1vloWWAkuV+/oxdhDW p20TyTT2O/VPp3m+EzlmnnWV4xK70h3N6PHM98xVk6mnffhh/Vgh2FPYUMBhFoA1R5ZkVo2hBFx+ BdBPaixrD1Bh0/1sYSrIxRoyOp3yESYfh6j5q6cxlNTa1qH+ifL4xeUh7yFpIAKcpGKV/BHZ4BXZ dzcowFS0zr5D1j59GJ2fBtclaFagM874kSHoT7saPkMwJZzu0a9Suyo2oyHeDY5u0tqwoOjIxSPD LgfMjS5eI/7kq2LRK6vuUkw4NPeUXfLEpGv5FCJ6L5qj3kBW2g6KAhG87smejtyOyPsvsfynrIc2 3VnDVEHbU7JdT+65asCO43n+F2twwXTbRz3siKaGFW/pSUKMJST4WLbItR8/WK8o1ze8PIiuzlcV 2q4JbKB8FDK4mLtzmIeYo7UTwNP6U9iXbLmMvu0dzyoUw3NDGJK4KUCMCVvDKN1R/+YL7Uwr/kfr H2I7nTHDRk6JDcgnN9lfHUT2S8C2BMkKRraWkqRs0K6NTq153MMgQ0I68tioSH/TpTwOz9oXVKBC IPIOjB4kXex4kXwRz23kXOxBtWL2ufKqg40K9aFi7BK+LFkdT9TJGBCwlY11kGcbWle5fHFUxBgl D7qMX2r59mWmGBSSP9gWsTMEGB58WJb0FCVJzJGA6OZLDvK1GTVkE3XRxGSmgNPHSS7w3jMJyMM1 LUnr75CCm+QeHuKzLZmM4W96dN4nPXd6yqiYEO85iAqDcN94rfIuZjKzOQpcTx9Oi4DIbX9uESmY tjGl70Xxr/adCaR8ilSvqqc+b4MBKqY7ELJDs0L3vXhscTGf4aQPSq6GF+yybBqE/m0z770fLOgC kzFPyfhoCNMoGzjgznhNFl/K2SBBjlumjwB4VoL4kPAv9g27PQzII7LCyKyJowsuyed1QFyLx6e0 zPEPygamJ5b2aKJfHjhq6Imar4DfdI9b/lJ2m3mKH5VW2TviID8sew7r/S+Cqsd1khcH0dn+JSpQ Cz5CskuqoPSTdJzTOv3pTxDL59oUgopc8EhlWAJY+mQaF0YTUq6eOMJWIqiTRPuWQs6VbYgRaUWq gGyiyprJEh8tjGjzF1g0t47LQBCmfF+ET+Qos0n0Wh5P3AuYe2d26zA4VHkOum3I/l6rLBKqZWgw 80FOjGL5rFavkxULg1QQ4CE5oihzlPEto13KkUan3UDd4FbgJCBwxe8aBRFgid7TZjfFiKmhUFt5 VQdmXePim15/U9KY4mMIYrnEKT0toYoS7SwJCXalf9S/2xU0+tvNWpw1X6qO/7v3BrnHauRDb8p7 DXnByUOEvR5Iwn7KTkPdDsC19IFFE44KJQW/TLM47NkLTnUgjtpw8GJXRgECeGgmVvN4zDWAz4kH JoZvUApvZD/k60yS9lZdKVETDuGnJLMPWqaE9URGx1F68zV/t6gNNzi4Vbw84HrncqaVQ9wkyUgz NG85xmeRL3PM9bycBzo2/5tEUhya/xB50ZheKo/wFA+vGxItbWD3A/cZCrWTA58Qp5cdb0eH8meI wFkrjyP9iCxkcXPvTVMY8oL8o5pJxxGdMvGwC7jjkK1ms7Vqxk+flNpQwFOxc8Bhi0iZ0/TmPVEf F+ZGV5tPUjYRSTzxofFD0jffamlYZQpqwKkMAfWbYnog1yK+fbQm41jBZ/ovWhcEWoIbKWZIjFSA OD5IG/kjBWkEXyU9LTohftglq69r0maNKbr7EKYPsDpvo8izUbasMLapY/Ny14fG6BWgAYo5xI4s djD2qS4vNfqRKU4rAsx+aRpvVQxZ6OeKvHYxiqiIPhOi8yi5g6zUu2EdUUni0ErRMnKL38mmI4KK 4xPf2PcduRPfhljJVhFLQAL/Vx9rs8TI2ixHSpthP0bZl7TycX1Ef3z74wUQ6nP/jp9Yi9pNL4Es OrsoIJiJrNwmzskoRB+FpS0XmnGK+WXeWg8mUkqP5uDqsrTxbhy1nUF9+bxAHJTjfax7I9UPhkOO g0Ms31UeKJczoUQXY4xQ2756Cr+BoXCCgUE63OOGha4EZNIFVDjshALTXX/K1Zamfq3M4naQOWi7 h36LS6E/7kjsvKD0qig3B+bw4eYn9D7xp9W/b/xnQX1Y6b+KJI1mq3ewFW6FWhzfiushu/g1D3BH IVDnqB2RNE5KByrzrzTWfPXtAzqwVypuv0uPzMYjP/HUWBWWxaM0698XRYq6tEjyEZmrbmcmdddB F+978ctayhLeGND3gjJzMD9GVyWbsp22+eKzIrPfgf+zir8BuPgUT2EfbWNhBLNuDCTbpqX3h5p5 UQgkeDx9fuGyyfEwSY01Gj+b0y0ZfFaPQ8GsQKQ544ltOq5D2c2hxCm8+bT33Xox9Byh0dE54yji mtCKhyFgjWGN+nc8kZemzz58Qc+tFgq33sNTvW+u613NDE6weCWYbSHGw+zKAAKUT3bn5wnjKlNP Za0+LvGGrSLhqhB1E+mDbzQz9WPa7pk2U5Yx8hXeWw49WqeFimySWFNJyPEM3fxsATP6UzAn8oSB gaeOEqF9ZAokKdVC3hxFEdR4hES9AH5L8QlOcAwytA0XEPo7+VJ1dvQy+CUJFMSViL4UyQ/1d3w3 /JflFzwiR+Pqp+4cC7R1OcxV41N/Xis6AjZZ+L7AUqsfgANI6OaDHJs7hPXGw7n3rtuNAlK2NiwM bWvK56olPYG7yuoHmsKWkg4wJLoG/MjMFjZEijGpYHYAri6CzgPrNOGFw45dmw2Adhf7PPKe3wyy LOw0Ka9N83vjMWPcpVP+2ScLxhfRWLsSQwqGhh8AaitW2OiTx7ekbXijvvIy/TeTns9LEnf2mN7s IBe+4wzrMc5PmHPVAy16ju/wQ6j1XAbp9cyi6gY0S6FWOq1l8lKsx96z6qBwWwgxdynUzi7lARod UBJaDyt9i7nIhqjp79HJziAlaRo1Xrnt+LN/sCHD7PBmqF50pCSW6YzEuP164twgaiGlAi/yYTc3 kt2l9rDpHVSNaJM0oz662UavJO7BxnuoM2PoAzBcoBY78upERvNQBQFzOo9XtFM6zaeXPNJPSIJz H8F3j7maBdtYWMjy4sDalZ7Fyxlo/lRm19Ds8/86OjGDBNR9PMmPiZAwnLvtNG3yp5gmgsW1sskF +jyaMoW9SFHOaU0dQ9hPXG6sflnNACAOh4LqrSjDxOdDGXJIBbCV85aakvibPiTbvRihxfcymks/ F3Vg2mB0MLQN1C41ypwTN41Z7iy6mmfowNrVB6suL0B4C23X5uXmksOWaa7Fqhue8voYHNYz87AX 1CmUnsx+ESMgq+Cnk/6CljrQ65N4INHD44SXvqqsH7KGdCK/VJXrSrd2MBqWddVIeoLXCuqYwOxj ezDRKd9jCIrgi/Tp6uGj5vAaqWNO0i6KQ+V1odyjNq7xhDwfSyL15I44zNRkGVJd7ttEs2zo+e9M tTkR1igHWulM5TMUdbMdej0p4q9rY2Vpez9BWoTMI+NMTosN/VBa1uoXg3e1i5Mey6pH68hXSc/y OOl6NP0lAsF6r0vso9xG+KIJcJZ1ldonn048etdsDOsRodP/ZiitgPAjFW8b3r38t2L5uZfsEwWr WnyK9Yy27tLFMgyfeBmKMin/bqqg+xVK4GGjb8oravkTjBVW9VCYc8nzEU0RlL3Kpd4DNscR6Chn fBK2UambbZE0jsrc/gF32wOzEjsRYq2t/NxyOzmZ6TBogtMcqTuJUWvDPcmPB7KFI1xve5KpTnFH b+AGLQebcHUjlzNAfV1aH3VZWNbetP9Op++JhuKwV84xkXVR7HuIdr3CIedCHKzWW9k6bDKi27rn MpImtyw+Jhjrdjb6GpTy/V9Mt35CVz0ilaAlzYnQJBMH+HbaZ2u8yveI4vSTZwSZ51DlN6u2fdtZ OHLA4WhhHPzW93UgL+Z3Yn1ZfGH8L0XL0rG0Wmi5mZuQTP2nfGHnKvEpiUV4uhQnQoO4ovh+VRRa UdTp3aYvOwcLa1Tbfxs0zG8896q6sLndM++95zagL7jOyZnFmQddlKEtNZvqtBxvKiZzUa4mudH8 2QAR8ewUfAWLEQ3FDWqtbRklVLgvxrbFK8SrAIE3lwO5YHXnIYHasG7Q8kSregntWeOmW9T414pQ js7uEMYE6soIZDftkj7r2aw7chVXBS+0VcsvZ/buAIoIiNyiZISKmnQvXIqWI/07V/7ZcJb1Mul7 iyxId91udFo7+4FtchFIwNV+RHeV4jxN6vLH4C160myH5id0QWN9saHX31nAzxNCLbI/8NdaMApz Pe14SASWdOWHeESkoxp32P0cnYi2VaV9dE8aaiiuHcNyfSbIndQdMiAHZADN8h5t9ZH+FUd3QsyF Sqpl5mKnkQ4Iee+gH/GeM4GoWyqumkfLSfvgpjCP+glKrnG8oarvPatTNQyzZxLcT3qc3gw+2qD3 w8EFzIZpIIllJuwyHGtnzdAofwWQ2t2QhS2nw4dvDoLydqXqtl22O0UF8tdDfG0ePnfvBF1OJ6tX 27vnuoiD7/sNn1iXhX00lrc+/ZM5JU80RRA1t6eEcOzVORKNgDQJFnuujNJH7wLQ7EHTUmeR+sAt Cv1KJNSHlVz/cK7/iUC0r6axtv8mKAVntAgTy/SGFP6roiqTVFExrldW4nVtzASpqjulJ4OusT++ eOEove+a0qg2KM7bTk0Bn45YeIrsgjan3/mlE07UhfoZ4SSfMl7EtZvaRR3ipwx6e71+8ku0ngoS qy8nRgtaRqRY7Jk1nDpdNe2iqhTgF6b7cG3phYYw/NBlzKtuyfmjvBqZyBwCH9LpIGKRL75azkK3 lLHg6yhSIhU+EORJ2y1YtfqGUmiG9Niiw6+HG4pf6osSsJn2bE5IAMUdFnPsLXbLZGp7eSXJQyFq 8hpiZMpF1xQkxYpxz/wk5LDqfQjjU8223MNGUH4fNxNkw+ADIhqqCZqHIOIpsfQzG71AfZu814ak jBTWPgeR/JYYF+PVJCvoxDhcgNL8XkOo2SzCjPaxCZFctxOkd/vDMvfhEwUgLbji10FGbOWGlVBq NZCJSflITRjCxkEaeIs4knmuyTIB7itLSpYbJz2ASoRzfyhtxl7lRvRhoI3I8JWSjaE0gzCDLYgi RDsCb2RiJ8XohoAuLRZKRVerVZcZf3rUI+0/K6zcdFL0klSPqnlt5vcgh5NgguKaJ9GabPGAD2NP 9fbfs1buAvi4uv69L1MqWzQSAvacBFAa4P9AT8u+t+aH0rU9nbdivFCa4QBcrbu4dIurpEOTlz6v Q4y+hklWTfxSNJo3P03O2zVvqDbYdlUSMVa47POuEwZqhOYuMHlll8NMSrwLAgOBiQ0GMCj71pVW mThWwktWKUqfgfmCpBcf1vO3YgSc0eGbNhSvwHYOyVLBPc7ySaMgxTOBJYVsnEQHWtVqoSnTAk3G QvSI8/SSOhE95/e4PurKfyZRuJflbeXE//Tnmh5ucLit5o7PbNAx+7Vgzx7QWY2EmPlpS1vNTfXL E8YrX+xRsIaJTA8fEBWnr/2c6i8iEenn++STYpXoY5RK8zeq8W+hGwmkOPtbQzLKXWJlpFkYVR4o nSLEIJnCAjsqDoVa8M9WHzmMxduRz+5JHd+ulXyw6HuVbSfxGl7+1vmiwX98jOJV/B2rnUnZ1WzQ frG/pjNNX8cyOnWkREdG+pBC3KYfZH9J7OP2KLdC7ZPxSR9hYJYqhq0xq0pyolbbeIXSnahGLH2A zQklbExh0qDnU0yp1f5U2TmWZDcf3jcHCvmJAm+cSplprSIUCHpP9yfCr087fRyet37UlxQTirZ2 Cu275t1hYOJ0EpvJYJ1S6sdM1QsbzskwSDC8Y0xP98UWE6/+AMHdv3GnE6SvwNZMvTGJkn96ab2o 5znQmV8122xq0E6e+2wD/XdQve42BvedJmozWGevKv7/RLHlK2YbqQsVKlDxeFIBunkkGOBmRsbL aBqwLRvIuO95OqqPOiRjf3RRcpxxM7y2a/uM3IuxuvLPfmYxV99uAcrvlwJkoiAnFLTlQKD7L8v8 0aeXoVkGq8/cq0354bbX7VSOJvu4cu5VUhtCS1YI7frRP2oJmWAeQRekteggVCoDflkDUqzUsZLQ tS+fjwPiGPLI1b4K4HZvtGwp+EUT7UUzfFeEJNhEPPa+GT1sHRDq43kuHJUO2l6pG02DdQwejKvE BgHQyX4JsLUlFp54yHA03+7z/+1+hVbZf1gG19WdyGmqON33qKq4fecMxXgb08hJbkLI/bzfiPJo GIIUI4ZgP80hbq3wJt3KVfhyMfbQNTfFTs1DiS/ZtB2YMSgErGn+A8gpB2VHPyovp1MWHUhPfsGl Cicec2BTQreiNhgJSU3tuYBD8HFEOkNuG8HxwffyjMrTOQUDf5/DcRSh8/QZN9aRP7vqMB5+ouLB BM3Cm3zzlWfS/lNhRsCrewOzfzFINfPGZqgmtF/1UyksiLB0VrU1KzHhWCMK6qwQepPPMmH1Ww+H dhP/5e4gNAw7t33+ciyoMyKCb/1I3sCedU6yjgejvKIdLhu4OloBAgbaBVAYhb2QP5GixZZruar8 K5r644IqRnPKDjNB2MY1tUwguYv2cPh3zYwZvI+maiWwHhQAHwjXFwx1y/zRxF9+OnpAHpeqga7K cmvuqKPjBhbGo0Vk/Dw7A1CQ4CG6b6M1AdZYpimNvVrzA7NKArpavLkGw2GCxuoWS2GCBqcumTKP MVGztQTL4F7W5ufN9sjaCh1Lh6LHjWq3ufgoEP3DK6R2KPwPrRnfEsTQLbdQS9SGjcpVRNcpQfAV i3OBYmpj60typMrGJyAP9EqSaOwlG6sWtz/p1e7AG72uyH2OT5PMSlQ7z3WCFYKRc/eI7/svcCLw TV3v7TH8B/1z+usu9X3y5Ad4fnvZ1jaSCKRO6KEjdKoIKJRsV9UnmMm8XyrUZtRcQpdWogyhqTKZ 3hODX4nK2UKq0ZPcoq4unvTXSvUW31Esqd5c3IcGDTMPHGceQHYmNfhkha6dJvTce7iJ/Dx4eMzW k5DDQml26ol8E9GGKeVa/awQmyAqtlmpvtHU/sBtxfrCTFmD2TcUGW6FdwFXMTu1MPwHJCE+Uwe0 VOmcC+/Mgaron1eLzMWV8XyW0ACztshoHbJfD9d9JsU1cJbGyOYQXu5pydYlv0r7f6HmDVxM7O1S rCuOYx2DZtSqmHzS1d8qCYlF2TkW0CVBcb8FCABSIM6caQ2aR+2MnCP+f/2uXHkH5acFGclk0M3n xc2A7ebD6mzZEOYWWxJBDElzxDKstwuB0ok5v2gwisV8CeuWAs8bjHOs5An7XdyM5g/9hyxXZivj fr0OMVLnw6u/Q+8rJV8/MoRSJ6wjs2qI8Z5MJSh4pBnHrwZbv2MWl+AIAMlq94qF4weEhBVNaHGH CfVPrMuRFwHVRkRhdFZAcsjaQBs+s+E3oenDYAe7Ko4bHmAA1sKKYLiatMXxmmwXSSCz6FewD4PM EFO9Gv7SsiECezHUmJxNcolWOsuk0RE9MakoNlaBgzKEkiDTqa13GwLnNg9Ck+cLCcHgnzIO1Njk L4b7LBFITgmMMm5B6INns4IdMbmaNO6KziwlBDOx22CmDUoV38m699UmEYCaUoDauHrMWbFAX2Nh 99QDJ0gI/4echrXMMbmcWyrizwN+QOYXN7WcSBMBW3iyy3ttsbDzaeq9/oPU18zzPAM+D+zFmeR2 zdbBrzQa9sESX1LphCo2CrKvbqZOJ65K3Sd+BlGnzi2uADnDnEqjwGRXXAnPihzVAbwbYxSLMvk6 bz6SW+eG9w6sZkC8M6DnGvKjF+Qm5tm241A6vyreUHmwA24lFL2F4DQ/wcOaGIxI1V/cxiaxxG24 bhp4Q3ZDgkwS12sHr+j/380mxAtPIeOyNv5Jc15jyBWwkCJ+pKuzrwu2la3lwDcbZaIRB3QwG7Jf +b1aBgR3kCCQkyUMFk+7nJuGWWpI26G89k9mbt7RGBKNhowreUdEkunfV3Ce6DswgpB0DHe7dO+x tYunTbfkcJvJCaDIg7MmBnaK7vEHSDIQ3vk1/JqRqFQj88Qiw5BwFV10oPymHswGDs5Y6PIHtWvN 0OdG7RqnNFk0sFTQkgR5IsxR6CcQIL7TUw/dBEwMvmQ8tO+jtpxMwOPKu5I1RjaTOYHWhHWp5c7V u016PT3exfxVU6/P2PRvvG5ppHbkirnTGwfDZ+0Z1HnVvBLbIeYkU9VlfXZdMcm7gBcbme7Lo2Ie NpSu2PZffaAlMGWZjninpfmmeGrjGRquaDcN3kbZA+M0d4d4v6QtTLCCZDKC5n/KD0pphYQ1yEwT 0e8gU+Q2n+LvWiAji6Ij6kRFmwkk/Ym2MuKGSakMztcBzZdTqCc22uHIwNPqU9lNGV64pnT+6O8s g7U9zg4/JzFhnIO8EtTmid/2CZhfhXsyAB3ze0Ak+sHyY9ad9eZNwnQkJ2UzOsaKXYa/8t+ZvTAS btPANzI6CtZktmDemOgTWKfrwG4Z77GYcEk4VOzTFeQfsVSqJ1SyAIMGgqQUF+pGk22sT6h/6xmx zv6T41noCLQD/2wf31d6iEkF+z5HA86qxKIduLnahwesrHJnZoQHLtO/hg6W9q4tpmy8dchOt3vR 7NcdOx9P1A9EUI3iNDQCD4ppzR08rxLqrO1f7wdD8FtZuyLGgcRceKh/9iBM5MYtFphzbai+Y/NT +30bD8xPgfqjtCtbeuAjR0Sh8WeIy9gDKwc52WwOe7ljeiABuBxt0WpaYOMY9vxWP9J/IyaUWi54 4bH72orR/xMzYfnJjD0qjxak7K+1Ebo1ieyrkJFUoqTJsM2nNolYkf281GAO7pp+BkzZyvUxT6c7 bJlMXA7bUFfEtIEw+Osw0rZ1RASz2N0aFrVISS0O9xN/TFlWN9N5ukA4cn2rjzxCAVg+qTkacZGj rCP9graLLlQOkF+pC5atmThyzkSWPYf+2oYU84nB5w1RwUxI4otUS9wKKkMgjXtp7d5S/fKAFVfG ysAivsHGSG5R4bKNY5QwjJ/6968hMuVya9rih0BjYQPX9VC4yTuyUtsn7qW89ivRqrKy1qYT/xQ7 bY+dA/ciLOIdM2mEWvwZgfCynEcS+Pzqx0w/WR2HUSB1r7hKIgyrXjOC7egRl+cM9BOFaQmJBL2F kJcdNUzEO7hPsyDvlbZ6G8pdkEZDeQXn5MtHpFw/KMAmLXuBxBoPMTDD7XjsZTR171GOdb1mcll9 19pbVmD2rH4l0dKbw2J8qX6swvH7+/eF/l7k40+b4jZQMmHSkbbxrHTbTTSqHrVlk6eWZ0CuujCm 9PrZ3s983CBMJnA3GlCkvwK50OoQFFweh/2Hd5bBoXZUg+SshWddUSlOoq5nZlfeB0hcXfpYkOwt C/TfGMV56JMsRwITN/SkKO04Hgc6fQc6qkEpag40qHmTNgDSWOfHuskqDoVpHBGBPqAE+saW6FMp YmcxpAKVJKxfvvyIEUBAlomVPep1FH1wK0Q6punWKQasWvG0qdmdjmDh01QIff56cAN1sefxkwYH k51x7eB6p2FZ/DN6fSB2fYfP7Yg9HFTKcj8ef1Bym7/QJRHw5PbTw1A+RX8sNM4dbuzQFX1WsaXN J/F26uB4ePpD5ukYZ6C/Fenm0EsDQ4ztrXPvoGT1UzkkHNNGS8EGXQvW5SYsScQWcO2l4JI3V9lr ayfyEkpYTAY/goJCjCLUTpecHTO+LW5xQMPp93TqgereowbY0WIDoU1978EVVQlcZr2XjnsoyO8u Tj9ddSY/bj52JU/ncZVEX+pcvAqiuo8L4jeeM2zQc8hBW2zvvlUFYSSqrukjrKIcx26CC3t92CyU 3344G28F5g8PpzlcvW/zQevzj8wXNI+0XkSEDZp9db6eJ0bCv3oCDxdwv0CA9wIAYq9XYqvn64RM lvol0JsLKJNQ+10znu/ocWJpvhlWYvvn2tt4Nb+V4NIZGmOZ4p9dpD0L/wBawvlgvT5bDKjEFIP8 1OBK3j3ho7+ai9XZqauvpF+aIBvqrzPZ7wj/fiyKCZpWcstSDSvXfcRhBBRkI+o86RC7vs0SOSqd T5rhbnqyil3D/1goL5PMVEoW00401lLrCd+zkkejZqK0Al6+zkepngWwOyEQAlM19owEMIaNM2cL dwEfWOcPpfx4Nxzpp36wUaaF/yAz1VMl6a+ovf/lIeFeFk4IceDOA0PapHAUjnWnInce8cgOdr2B p134X8lSBSmziEVvJW9sW9FP3M9Xou8+TaWQgkT8RkhzP5gzLkRbfz/kxE1m6V8e8n77J7JHmnK8 T3XM4sxf+sdEpaE6oOSzIRDT1NL7d5KC4r6bI9icoLS6Ug9fJL8HMLvOwFtrj+K78q8mqb0ut1bY fTCEyh39fot4pOBGhSJgBXjXEnDKOXvzM08S0rBwFVZhHHbtXf5wHNuPnWYFNXwArkCBPZLkrB8G azj++KGft7tP7KD2c4asdVZuzSKiI0UCRThyqY68yeLdJ4I5raRtfygrShHo5hnhUuZ+vcK4mZig MN9d5f2ncdrtDmQWQWCcJXsWoVUbD73fz9KCFSv+bJSVWtvGCotvRZQJkGCXGX4GywfgzwJL7Ia8 hdL+E8NMKcQ0Xyjqe8sF45B80bSzv/nILgAZezqqVHjgL8XfTvWDugeSMEZtd+XYVNcQ2r4hh1fV rfqgBcK7Lqhqik31Fcv6plYuZwlSdS6QLmFbGJmrM3aeRuCSITKzKv8b2vrPeSeQRnn0NYvjwN30 WdBH96SMxryYnzbcNbwt2cwyb47TC1ABhh4VSr8+dSAi5IpcfVH0lirSnmJn7iqlDNXk6nvEsXxA WMiUtohOXx3BXSU/ZPIHO74Vu9Goo9wm9l7aCiAcXXzF0Ke8GthcuJ8vHve0eeAu0XqxqgpwXLi1 Bs7OfGoNoC36vJNAqzCLaPXl5CJSSWuOTWHKPsy617fPHbicLO1I6pdea9nntSSamFVfisjxI3MW DfLj0R3udqh6X7qPxEX0Tzzlt+XyU20zKZgt1cDXGqKFDTmpJzQA4ko22drmws26lRXIA91KuoFZ p+BZ7czB8HyiwOzzWrBGA0ReUAV27py85PBMPJlh+gFMcG03zPXrNqGch9z8tFh/1VAls62/6Ddy 8GfAkltZyl8q/d8MRiDM5R2RonoC67YJl4an18W+qwN71gXOA5o8XbCa+7iBuJz92/d7GpMkDIHJ j/fOmyetG9ZdKfNEfWtcGTZ1vz9G+5odQjEgYSVC3RErKMREr5K1kR1mUdZiyHiJncWlvIAum26C G3+Hlwq9bIyE1ECmS6ZIm1VeE2VgycYhQTADzIYxLBKT+KjJiMaB32C7+w5VqoeFlPKK/DXXuH// r44w51JR7mvybF594ZYYds2yqXdrItNspSz1uU5f8DQ39F83vW/JBmQ1zv/lcuAkZdv8Uji2OxLL obq1EFFvP3+STnuRi4JZjmoxVCIBnidcHN0hq6lNDdEbrv1BJ9HxN6ppWUJHRsydw4RZT3ZXpXj7 5M235BkgZUyU0XUqfv0mjBIx5dd0p6NHmkQ2xo+op1W7dJRzfcRw0+sZWEwFC6mwPc13v2alCppr yml4wNPJ4rT+lfKt7vZrKM3d4zPFLqxUTAnP2f3BSm+j2aItYzm+Vybw73ITBU1IaLS/zgJ5nIm2 rbIUyJHdfedhzJ46x+Xv3jcs5Nu+oXZ4I8Qy0Myoyh7G6gAvU5rA2WwB7cR7uG+4Ib/quG/oAc+b E341x8TpKcVUIq0bVEf+I9q3+pvJ7dCRHunigoZzeQUfmqePNfN0LKuEn1+MVb8wrYwrty/3fpRp kC64tuZlmzVkdePyIIX69uw4IDqrdAjvPNRMLB0pxG5nrjf5iIP7qC60L09XpQdOIKNcuTgPDRw6 uVNwVaaftCIzLTmvK1qcubxea2lec3W63wzyCJ8pHO3j61l2uUr98GyqP0IbjhMe6sUihs0YB1Mf HFCnS71UcLFrQqjYs91ZHbNNBZSYfWxxCChRHflqqR3ZEpLyN6LUHXB99z1S71vcsWuWy1osz932 RGY+k2K6NVBTflCNylerKecDr4tjkw81N8j/7oxzC3rNGivhkTIewJtyCZV7SRaeCJzODXfTIFGh z68mTx3f2tuhGA+k9UU1OYLLl/f1MSQLXzEiyd+ydFsc6yTAYRtXkvLjnwFh3yA0V9H7rLx/P8nC iunAKO593zELp4AKBBPKMY0saoxvpZtddejn+YC7dLQXLavFrIeS4OUXVnkpoQU1aUKHLaiiOZLp lt+0O3aie7aWtihUXFQnvZD4194rsZE/v2w7SdUyrYWelW7s0IJ8OychbrGT3SwvSAkcXWsSDwLw X13XM/qkwIzky2FoovpDQDBNbaLNFTeV/oTLoNp/EZoxCm5kkqfadB4uMDGvU28Ut0xXOz/3wLCu iFeSrlo+Drn5Yu7NZnVKYy4KOT21lSo+0+VuazH96fB3wq35PG9puYjeih8Gbj1iHPg/XUJhuOZt ehsJc/SAhN/Z0QK+kXYLDH/k5eEPyMEADNfTZmXMvuDLpbqHwU/jIDpikOYhghTtcbRvpDRDdRSS U4pC+9FXZ9ACizUPzH1lFGlQs0buk1jzRSYnp+wPWeNE635Zo9zXG2nuLXwYo6sWmufeHpJLBGC/ rS4pL3zLnffVbMQc25hG12sGq6Gpxw/LLxZNMCBg0JievUQ3TcQ5JK6n6a57jb7/WfHUtzUtvaYf Qh728Q639I0tOVxvPe1wtwtkoOBA+ouVDElxhqy9Tn/FhNSyBHnQIAfrLC1lxpp/2KYvK9halNgU +KPe69LEGjFGxNeIMGMcJXBOVsUW4Wo09WHQCqA5fMckLi91kZEy3r7WsEuVouiF+2NpnXl5gcZY yBgv/9EnfOJUEHcC/kSIcMKUR64NdyYVNmOgHthLVHPMhcIrk3XPPxzKDj4FKJY7mhi1pLqOUiGM 1/L/4XjdtmAM4cG+wClRetoPHCwV1PuobCAxSdyRCcsDrcbItMiLtnc5DK6B4hK1Xj9tGKjpME18 M1KTAH0xP70UpEDGPb14A/Ecldf3q6K7GX6vHn/aio25Fqs9+1mgmABQ1C1rg7D3mJ0ckNRiexdd KCG3JuJYpB0lJPhd9zVxyNVwriqGxVBudweNf8IrAHzscfMvDi+3A7xohLJJWK7HRNC/ndxHMvxq 8PZkrDQVovaQbf+EBZqBe1thSH6N2KbKKE8kABhNrFHltnt8vMhNcz/9RqQYRmmRLhayTs/Lakhx XIfXj6jJndmo83miUReEFVlxwxCsjNsckDkX4MbQVsfTBHMyPXU8F75pAeP2CLkA0bKlWbbVc4L5 YxYBLNQFbJM3jCfdKlYh01q9CKWjxtoQZeO3SzfHVUiITFxnc8fxj2kIUKryilqTXBSurXTjjXvk mACBBoko4KGanV7DTBqmS62mKPs/J2kIQJ/JbRSQyZTzV+DUsfB0uV0KW6ajQaQ6yoFCCoVIDqeD +r9E1WeKGKvrFjzy/Lz7BEo2ymbE0xgBOE7XYdKXe2nUY71+K5p/IkubjPq2fZiwceowlRDSdyUt cZbvpRZc/vaYm+hsw2YxrivJr3ez7Be/3+3OMEZeQs5GrSitXbJLXRtMUoKjU3fK2sE0mc3aVTc3 QrFi15AtNyL7Wy6lzMbROkYxwMl+UrJ0iPAfDMpsF6bYr/sV+SA3mYB+1MREVLo/XJDqbyYVT0Yc 6w7i5vG8uFjKi/hr1Jie5vp8UuPQdpawPoxWbLQz2pEpeG9Z/vlNtvAwq0FflZR9Hiy0R2PfjGMm uBfjOwNzByOi6kKXfgMxPTgMwCLncOjGng9DZYG98a1paYiI8bf/Z+KqpgMKGkYg0dpJzj/m0WCY rqTsZM0lRsXBpo1jaOQYAxfUIvFKYztuAA68gm0a/YrJIBqqDocTZJVkp3pZ4r7ZZ6AzeHoaZf7E 74SUIlp9ow5Rx0FJhLyodHgP0JlvJtsPeYx6b0W3dqPDj/RqHVBeW8QKqSJjCcgEAtyTWmNebl2f e6LlunmSYqm3moX0NqLP/wEeYBDghM1R3+PSNfFTmiaqjwogHcnXNMdM72B9nx+Y+oT+fDRHxax0 HCYv4vgTs807cZVf85JuQl+WatT7YYXP+KiqX90qDM57qrzwLtcOf/hRig5qnj9+ksKikNdITAmf i0SVFXQHC+/dJ9Uygh1acgIHUfGVIhTupF09LChEIy0bmwWRSY9swIe/wccFl9bZRfNpC4eF1XxZ DOEOY9NhlJANvfh3PnZL7qXRa2PozfDYHgrHUYk6MI0KsXaN03CNGkPEUxc80g9ytkpsAd+TzTD1 WfcYV2qUCkST49D6Wd0mMJ42fAakqB4+drDuhXzR+bHvGrm9fw3/ZBI5HGZzc5PGCOSqUWCuvG7T fuYHUMdFwwEtFoy0ySgH9gTfsaLll1ZKSqD78tdEAVTBXGJj1n+diirnUgKAFH2ubr3QP03dK0IJ xZ4LBQ9PLah94xYFHVN43uypBCJOBxKbY3m6kLLCtyJOW2YCt/tbu0YOzKKHGIIR8WcfaVzP7c1P FezRlWgn4ntbt3F3GVWZYqN6FhQmd+ym6BUYR4BiGMs+/0Rn7YnqbkZVe8IwvYSRmaEO9z8E9I1Z 7bnpJpCUXucDF4p+Ohqw155sf2eUrevX4rxBj6WkV260495kjKZSKNlH0wdPt9mdTA5H5WeU6V4f NxcjdbqP7C6+KqnHa2dGePxZ8Lyhd09Hj9YzfCvyzCHRlGX8ROGRHpxaE9x6Jf/RNJz+zYlzhbzs /LlDnpN9JFFTsAQeMF6MfY3F7RGiBPqebWwFR8CsMQ4W8XPIOXuaKYyylOYb++Drw4CK3Vv9LFzl +A/fk4eZOHQ9IhX+EHwGNm4GWWESQNg9Fc9yUpyj+xXbQDqttvFID3u4MWNV31VQ2brn98h5F6NE 1QsfY6Dzcjey9H1CXFLdllcrBnF6mEar9xYpEyRNXLsOsNTrckLqzP2dnj4ACRICh4bDxoPZzcNW xXsvW0W8rOJId0P0vUoVruR0GUjpGX6rFxD1S3WssAnqpQecSJ4HE9ZbrntAw7zXL6aDxePQmjS7 +S5YTXFS4nKMOiGj3n0hx/yo6Lre2tDh0S8R+b5mb9Wa4NMTuAtGA9hAttlu++H1VYQf1Pj9TC0J 4/zNyetpYD2mAGW7UCWjwVesT2Yu8VIzLRmU4bttf2kf3/VE0YwCXDS5oAHkH85ufacusLmu17Kj vN9gqSnhIZxHH1nbUup2fz0rzfgpN9P1p4oAkjK0/NSDw8bZOSIqetArZSAVpg/SktGqowyg+O94 Xd70Q8ASaC+hTa+M055K6w/oAHSk/Pxu2nvrvmkqQ+bLKAMKp484IGjHSNVD///69jkgI+4IFnwA nu6lGc1Bd9ESQz02JDsXIwVvm3mTtwIgmlm+xgASGaEE36LNHKijHNNeZjPYGS4ruUE836OFzz4Z tTWapLGklaz34QdaIFpfombdnV1rQEvllFqeJ6DVo/qvaS7WzKqWXyKfPF62Y4oeXYXQPPe6sXtC xDwvU+s9nroMCX6VfJXipzRmNYPEycByt+Zc4VlwG3RUyGJRFSXpYwPHm7GTV5nRVvbFpFdtqOtU WlxA15+gcXG1fndKEZdwq6n0zzqpjP0mSSmB/QJIVeMpLmF7NJo+Oe/xOLdpZXf1jI7lccmihQVE 1tpqKZuPZm3DojCoSc5nbQ1ka7MXmUIwVE/Hoz6SlyjuNvkUZm8GufiIGf+Nzp6hSmY1+2IkgGWa l0DbdT3Cgh/JtPLA01D8dQoxkb9Ztx4NH3c4+3vBZ0Wu7N34W/E0GaRjgVbie2D/Tpz9yNjlGBpQ ZZBA8yrD3smw2NrGLmuG+ETQHQcoCKDO/sM4AAiYNvQXEXN+uuZuru3Ndh/ppWDwh/1qOP1kfvgf QI1QSY4EjEPwgV9EJ59Q0P+RpiiDzxa5D3/SF4vXfJ9iuY1Mt3V19DMchnLnQ592OqOEp3s6Exr7 th/cnhytGnZArdqtl/GU26TrvSuHH6QQ1gY1w3RQQRS2fuNZUtJPV+ImLzvTeYMtQoLUrBk8EU9f 20UDRCnAruVNLpM0YqoqxO0uUPCCCYM1RmAfbGf4+foDDRE143uk8lYfQVSSlfTy1SOZTY6AyByY udyCsxlRRG/2aAYbe0F1LMP8Bo7t+81Lyad4mgf27kxzDb6O4MMFm8rJRSYW4Z0x6WoAwK5HCuwB XSgRbXzA7R/tjyH1seP6xH5asIXCu3OklsXNmycZYjlRqoL5sABGu7HVm2OLpgEhaHLAEx6wbfcB bn0bzkudXZVhswT8f4/rX/wSGPLiGux9nGJGdl3g3HocR9IRmFqwwo7zwREhVaXtyVBfQqFYWKUA 8KXjyH0sTYlpr5/rg7OBSjjUAe4GwKPB5489Flm5YbnTqLnhnDJZf2psbRvaYcM7upugJbs4Fvcz RxGyzuOF1WoFQLSTm54TQiduwY6awsD197ugIKWQiYt3jkY+UWh2mUUpYlGNTN9aQobtH76RZdjj klFnCvKyzEjDPzkukgEunqFTXPM2zMxPvcZ1LSzKGwwcSkLppjjfVeAQKu4zX2m397JudSPLKH6j VZMuz4dqqTcZFB3krSCsQ3kos90MeESuIAjO7wAdXO2Gyp9Whfmar6v6JI4gvS8ON5RTa6Niegmv I8+RzgWl957LmvGefGfrj6p5B2hEZ7SUNW0O09Z11sdHa/sCsEBUyCiXgUDwmqZe6mM/PvDR9AS9 yfNP8OseoF3PEoH5 `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block pBqd8SbxnErWrX3lyBBDaDLKX8hSp/j5Yr+Qm9jRb/9JUTybH1McKspWz+db0YzfLoM8Rsbks3xZ F0QO+ZZlvg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block H9nfu/oUf72/R62OBj/4D944lb73dgO7fFOuMJCE4aenI7iF3utXSTO4hpgrQ8McaV+063uC1I2p SowtO/PmhlxRipVo5KEq7Hhzbtvt5amDIBC05YVti4pxjbEI/kmWeW6ApomatkIzigzghecNWi3O dw5/lv3XsuSXKGnf8V0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block LHYKr83oHemqUyK1Wezwr1z3qiqaCVVbCTepzFi2rZrXgOFTcCRhqXcHptrNPAEIVNUU983e0J/f 0KmoDwapS9jLRSEt/t44AcYzVSy/ai/iXQJgng7HtLlp+4d5yiOHFpGB54L6O3dBpou3h7caNhhL jjFv+2NQ8/vJ/xJXwO5fh2Ph6YYguOVQ53PyR/4efc4uuMmB69VXQ320viKRtmBbQCmyLZzeWtFu D4qzTizu+7+B9LccVDGFdS5MPG9ajzsWHD/tFElptKJXuLi1qfJlX0wCtTtXoY+3nkHdj+d8GtPf YHFzKsVl3XUte66S5MbnjiWHmaZaMtS1k7u0qg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 4MafVQvjuuBxvIjR+OYUlKEesGBWmyoKTpW4+3dmDKYdKobe8ekpI4KwM+KYTh1JKxG3Qgsr94sv sXNAR2TjWeHLAvJhva65Oh3N+FSqhrH0zjkmu9XvgIV/UwkRDNwOx9c4++PMmrK6Sc3dNZpoycaC lN9AukRoCBpCWkU/kGY= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Oe9rX9bCQUY9pDwkxKbbIf2ys0cqImU27qEFK2Dw17YylEZy1DE0fAY/RnVb+EPxtWACfGlXlONl m+j1F3QtQOlCfFGG+seFfsBQSPHUmFsJmINuxeAGpMhxfKpsTFjDqKjDpQa8VcnDwKWm4aO3goL8 ohfQk4XoUdGZKXOs6aDCwCjQ3NSG6AcZNW0ORDZyS9Kio2rZOPAl2Iatk0VLalSOSKS8f5tT86ig hcckTERcoJMSnJHpKMG0Uf46p6lF1NxyM72QA47lZHQTdUAqzyv8wPWp/x+9NpDScFU+0BwCqNgR Wwy5LWtdGsu9PzUszKuMs6YlHHcqBdvP6pV04w== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008) `protect data_block ugPchIic85pVoazhFaH2TWuQjqsMIDhfmCLDBUOtUS/RF04DCSHl4KkxPTtW6P+RbyiD3T+m3kTR N0N334mL4z3weuQnltN6rjwv5421Of+ebjf9jNPWmR9lf0e4KC1P2a+RqcNXNDLyWLeUSh5xhG/Z 78Dc0xYUHiF3d+hrOZnBHDBSzBMBxH85jBmUl3hJ6N8TJlBFLvzDJLAwx9rMqd+/ukKUbS92XXmq GUfEtXOD/kOjfUAMdbSYK383ZTVeO8P00Ys+990ShfmBjW11X5zfC8a6pcCnYMWovhs5zhxlg5VY 5qaNHLAk3jG98jGzfgSX7h68H0TVRR7JEDFOWoBp6nHeaNm3GUeQnBHvRRf9iGTHwtNoBo20CT3s B+8CdJKTLLUzk6qAj2GsiBGHS8LnYKmNkY/fLp6AmB2/qs4DlNFJIF8WLDrSqDSxN7vLmxfW02dn 97TZdyIIRU0sSDWmckU00Bj4DR6lVWvrorzqz+TKptQht1fc7GrTmUsh2hItQeA59cOw1AOmZDS9 1wq0ZKLVSXAjdB+CY84byFDq/ggnql+ym9df++F4CndyzeHn/77aqPKlsW1vloWWAkuV+/oxdhDW p20TyTT2O/VPp3m+EzlmnnWV4xK70h3N6PHM98xVk6mnffhh/Vgh2FPYUMBhFoA1R5ZkVo2hBFx+ BdBPaixrD1Bh0/1sYSrIxRoyOp3yESYfh6j5q6cxlNTa1qH+ifL4xeUh7yFpIAKcpGKV/BHZ4BXZ dzcowFS0zr5D1j59GJ2fBtclaFagM874kSHoT7saPkMwJZzu0a9Suyo2oyHeDY5u0tqwoOjIxSPD LgfMjS5eI/7kq2LRK6vuUkw4NPeUXfLEpGv5FCJ6L5qj3kBW2g6KAhG87smejtyOyPsvsfynrIc2 3VnDVEHbU7JdT+65asCO43n+F2twwXTbRz3siKaGFW/pSUKMJST4WLbItR8/WK8o1ze8PIiuzlcV 2q4JbKB8FDK4mLtzmIeYo7UTwNP6U9iXbLmMvu0dzyoUw3NDGJK4KUCMCVvDKN1R/+YL7Uwr/kfr H2I7nTHDRk6JDcgnN9lfHUT2S8C2BMkKRraWkqRs0K6NTq153MMgQ0I68tioSH/TpTwOz9oXVKBC IPIOjB4kXex4kXwRz23kXOxBtWL2ufKqg40K9aFi7BK+LFkdT9TJGBCwlY11kGcbWle5fHFUxBgl D7qMX2r59mWmGBSSP9gWsTMEGB58WJb0FCVJzJGA6OZLDvK1GTVkE3XRxGSmgNPHSS7w3jMJyMM1 LUnr75CCm+QeHuKzLZmM4W96dN4nPXd6yqiYEO85iAqDcN94rfIuZjKzOQpcTx9Oi4DIbX9uESmY tjGl70Xxr/adCaR8ilSvqqc+b4MBKqY7ELJDs0L3vXhscTGf4aQPSq6GF+yybBqE/m0z770fLOgC kzFPyfhoCNMoGzjgznhNFl/K2SBBjlumjwB4VoL4kPAv9g27PQzII7LCyKyJowsuyed1QFyLx6e0 zPEPygamJ5b2aKJfHjhq6Imar4DfdI9b/lJ2m3mKH5VW2TviID8sew7r/S+Cqsd1khcH0dn+JSpQ Cz5CskuqoPSTdJzTOv3pTxDL59oUgopc8EhlWAJY+mQaF0YTUq6eOMJWIqiTRPuWQs6VbYgRaUWq gGyiyprJEh8tjGjzF1g0t47LQBCmfF+ET+Qos0n0Wh5P3AuYe2d26zA4VHkOum3I/l6rLBKqZWgw 80FOjGL5rFavkxULg1QQ4CE5oihzlPEto13KkUan3UDd4FbgJCBwxe8aBRFgid7TZjfFiKmhUFt5 VQdmXePim15/U9KY4mMIYrnEKT0toYoS7SwJCXalf9S/2xU0+tvNWpw1X6qO/7v3BrnHauRDb8p7 DXnByUOEvR5Iwn7KTkPdDsC19IFFE44KJQW/TLM47NkLTnUgjtpw8GJXRgECeGgmVvN4zDWAz4kH JoZvUApvZD/k60yS9lZdKVETDuGnJLMPWqaE9URGx1F68zV/t6gNNzi4Vbw84HrncqaVQ9wkyUgz NG85xmeRL3PM9bycBzo2/5tEUhya/xB50ZheKo/wFA+vGxItbWD3A/cZCrWTA58Qp5cdb0eH8meI wFkrjyP9iCxkcXPvTVMY8oL8o5pJxxGdMvGwC7jjkK1ms7Vqxk+flNpQwFOxc8Bhi0iZ0/TmPVEf F+ZGV5tPUjYRSTzxofFD0jffamlYZQpqwKkMAfWbYnog1yK+fbQm41jBZ/ovWhcEWoIbKWZIjFSA OD5IG/kjBWkEXyU9LTohftglq69r0maNKbr7EKYPsDpvo8izUbasMLapY/Ny14fG6BWgAYo5xI4s djD2qS4vNfqRKU4rAsx+aRpvVQxZ6OeKvHYxiqiIPhOi8yi5g6zUu2EdUUni0ErRMnKL38mmI4KK 4xPf2PcduRPfhljJVhFLQAL/Vx9rs8TI2ixHSpthP0bZl7TycX1Ef3z74wUQ6nP/jp9Yi9pNL4Es OrsoIJiJrNwmzskoRB+FpS0XmnGK+WXeWg8mUkqP5uDqsrTxbhy1nUF9+bxAHJTjfax7I9UPhkOO g0Ms31UeKJczoUQXY4xQ2756Cr+BoXCCgUE63OOGha4EZNIFVDjshALTXX/K1Zamfq3M4naQOWi7 h36LS6E/7kjsvKD0qig3B+bw4eYn9D7xp9W/b/xnQX1Y6b+KJI1mq3ewFW6FWhzfiushu/g1D3BH IVDnqB2RNE5KByrzrzTWfPXtAzqwVypuv0uPzMYjP/HUWBWWxaM0698XRYq6tEjyEZmrbmcmdddB F+978ctayhLeGND3gjJzMD9GVyWbsp22+eKzIrPfgf+zir8BuPgUT2EfbWNhBLNuDCTbpqX3h5p5 UQgkeDx9fuGyyfEwSY01Gj+b0y0ZfFaPQ8GsQKQ544ltOq5D2c2hxCm8+bT33Xox9Byh0dE54yji mtCKhyFgjWGN+nc8kZemzz58Qc+tFgq33sNTvW+u613NDE6weCWYbSHGw+zKAAKUT3bn5wnjKlNP Za0+LvGGrSLhqhB1E+mDbzQz9WPa7pk2U5Yx8hXeWw49WqeFimySWFNJyPEM3fxsATP6UzAn8oSB gaeOEqF9ZAokKdVC3hxFEdR4hES9AH5L8QlOcAwytA0XEPo7+VJ1dvQy+CUJFMSViL4UyQ/1d3w3 /JflFzwiR+Pqp+4cC7R1OcxV41N/Xis6AjZZ+L7AUqsfgANI6OaDHJs7hPXGw7n3rtuNAlK2NiwM bWvK56olPYG7yuoHmsKWkg4wJLoG/MjMFjZEijGpYHYAri6CzgPrNOGFw45dmw2Adhf7PPKe3wyy LOw0Ka9N83vjMWPcpVP+2ScLxhfRWLsSQwqGhh8AaitW2OiTx7ekbXijvvIy/TeTns9LEnf2mN7s IBe+4wzrMc5PmHPVAy16ju/wQ6j1XAbp9cyi6gY0S6FWOq1l8lKsx96z6qBwWwgxdynUzi7lARod UBJaDyt9i7nIhqjp79HJziAlaRo1Xrnt+LN/sCHD7PBmqF50pCSW6YzEuP164twgaiGlAi/yYTc3 kt2l9rDpHVSNaJM0oz662UavJO7BxnuoM2PoAzBcoBY78upERvNQBQFzOo9XtFM6zaeXPNJPSIJz H8F3j7maBdtYWMjy4sDalZ7Fyxlo/lRm19Ds8/86OjGDBNR9PMmPiZAwnLvtNG3yp5gmgsW1sskF +jyaMoW9SFHOaU0dQ9hPXG6sflnNACAOh4LqrSjDxOdDGXJIBbCV85aakvibPiTbvRihxfcymks/ F3Vg2mB0MLQN1C41ypwTN41Z7iy6mmfowNrVB6suL0B4C23X5uXmksOWaa7Fqhue8voYHNYz87AX 1CmUnsx+ESMgq+Cnk/6CljrQ65N4INHD44SXvqqsH7KGdCK/VJXrSrd2MBqWddVIeoLXCuqYwOxj ezDRKd9jCIrgi/Tp6uGj5vAaqWNO0i6KQ+V1odyjNq7xhDwfSyL15I44zNRkGVJd7ttEs2zo+e9M tTkR1igHWulM5TMUdbMdej0p4q9rY2Vpez9BWoTMI+NMTosN/VBa1uoXg3e1i5Mey6pH68hXSc/y OOl6NP0lAsF6r0vso9xG+KIJcJZ1ldonn048etdsDOsRodP/ZiitgPAjFW8b3r38t2L5uZfsEwWr WnyK9Yy27tLFMgyfeBmKMin/bqqg+xVK4GGjb8oravkTjBVW9VCYc8nzEU0RlL3Kpd4DNscR6Chn fBK2UambbZE0jsrc/gF32wOzEjsRYq2t/NxyOzmZ6TBogtMcqTuJUWvDPcmPB7KFI1xve5KpTnFH b+AGLQebcHUjlzNAfV1aH3VZWNbetP9Op++JhuKwV84xkXVR7HuIdr3CIedCHKzWW9k6bDKi27rn MpImtyw+Jhjrdjb6GpTy/V9Mt35CVz0ilaAlzYnQJBMH+HbaZ2u8yveI4vSTZwSZ51DlN6u2fdtZ OHLA4WhhHPzW93UgL+Z3Yn1ZfGH8L0XL0rG0Wmi5mZuQTP2nfGHnKvEpiUV4uhQnQoO4ovh+VRRa UdTp3aYvOwcLa1Tbfxs0zG8896q6sLndM++95zagL7jOyZnFmQddlKEtNZvqtBxvKiZzUa4mudH8 2QAR8ewUfAWLEQ3FDWqtbRklVLgvxrbFK8SrAIE3lwO5YHXnIYHasG7Q8kSregntWeOmW9T414pQ js7uEMYE6soIZDftkj7r2aw7chVXBS+0VcsvZ/buAIoIiNyiZISKmnQvXIqWI/07V/7ZcJb1Mul7 iyxId91udFo7+4FtchFIwNV+RHeV4jxN6vLH4C160myH5id0QWN9saHX31nAzxNCLbI/8NdaMApz Pe14SASWdOWHeESkoxp32P0cnYi2VaV9dE8aaiiuHcNyfSbIndQdMiAHZADN8h5t9ZH+FUd3QsyF Sqpl5mKnkQ4Iee+gH/GeM4GoWyqumkfLSfvgpjCP+glKrnG8oarvPatTNQyzZxLcT3qc3gw+2qD3 w8EFzIZpIIllJuwyHGtnzdAofwWQ2t2QhS2nw4dvDoLydqXqtl22O0UF8tdDfG0ePnfvBF1OJ6tX 27vnuoiD7/sNn1iXhX00lrc+/ZM5JU80RRA1t6eEcOzVORKNgDQJFnuujNJH7wLQ7EHTUmeR+sAt Cv1KJNSHlVz/cK7/iUC0r6axtv8mKAVntAgTy/SGFP6roiqTVFExrldW4nVtzASpqjulJ4OusT++ eOEove+a0qg2KM7bTk0Bn45YeIrsgjan3/mlE07UhfoZ4SSfMl7EtZvaRR3ipwx6e71+8ku0ngoS qy8nRgtaRqRY7Jk1nDpdNe2iqhTgF6b7cG3phYYw/NBlzKtuyfmjvBqZyBwCH9LpIGKRL75azkK3 lLHg6yhSIhU+EORJ2y1YtfqGUmiG9Niiw6+HG4pf6osSsJn2bE5IAMUdFnPsLXbLZGp7eSXJQyFq 8hpiZMpF1xQkxYpxz/wk5LDqfQjjU8223MNGUH4fNxNkw+ADIhqqCZqHIOIpsfQzG71AfZu814ak jBTWPgeR/JYYF+PVJCvoxDhcgNL8XkOo2SzCjPaxCZFctxOkd/vDMvfhEwUgLbji10FGbOWGlVBq NZCJSflITRjCxkEaeIs4knmuyTIB7itLSpYbJz2ASoRzfyhtxl7lRvRhoI3I8JWSjaE0gzCDLYgi RDsCb2RiJ8XohoAuLRZKRVerVZcZf3rUI+0/K6zcdFL0klSPqnlt5vcgh5NgguKaJ9GabPGAD2NP 9fbfs1buAvi4uv69L1MqWzQSAvacBFAa4P9AT8u+t+aH0rU9nbdivFCa4QBcrbu4dIurpEOTlz6v Q4y+hklWTfxSNJo3P03O2zVvqDbYdlUSMVa47POuEwZqhOYuMHlll8NMSrwLAgOBiQ0GMCj71pVW mThWwktWKUqfgfmCpBcf1vO3YgSc0eGbNhSvwHYOyVLBPc7ySaMgxTOBJYVsnEQHWtVqoSnTAk3G QvSI8/SSOhE95/e4PurKfyZRuJflbeXE//Tnmh5ucLit5o7PbNAx+7Vgzx7QWY2EmPlpS1vNTfXL E8YrX+xRsIaJTA8fEBWnr/2c6i8iEenn++STYpXoY5RK8zeq8W+hGwmkOPtbQzLKXWJlpFkYVR4o nSLEIJnCAjsqDoVa8M9WHzmMxduRz+5JHd+ulXyw6HuVbSfxGl7+1vmiwX98jOJV/B2rnUnZ1WzQ frG/pjNNX8cyOnWkREdG+pBC3KYfZH9J7OP2KLdC7ZPxSR9hYJYqhq0xq0pyolbbeIXSnahGLH2A zQklbExh0qDnU0yp1f5U2TmWZDcf3jcHCvmJAm+cSplprSIUCHpP9yfCr087fRyet37UlxQTirZ2 Cu275t1hYOJ0EpvJYJ1S6sdM1QsbzskwSDC8Y0xP98UWE6/+AMHdv3GnE6SvwNZMvTGJkn96ab2o 5znQmV8122xq0E6e+2wD/XdQve42BvedJmozWGevKv7/RLHlK2YbqQsVKlDxeFIBunkkGOBmRsbL aBqwLRvIuO95OqqPOiRjf3RRcpxxM7y2a/uM3IuxuvLPfmYxV99uAcrvlwJkoiAnFLTlQKD7L8v8 0aeXoVkGq8/cq0354bbX7VSOJvu4cu5VUhtCS1YI7frRP2oJmWAeQRekteggVCoDflkDUqzUsZLQ tS+fjwPiGPLI1b4K4HZvtGwp+EUT7UUzfFeEJNhEPPa+GT1sHRDq43kuHJUO2l6pG02DdQwejKvE BgHQyX4JsLUlFp54yHA03+7z/+1+hVbZf1gG19WdyGmqON33qKq4fecMxXgb08hJbkLI/bzfiPJo GIIUI4ZgP80hbq3wJt3KVfhyMfbQNTfFTs1DiS/ZtB2YMSgErGn+A8gpB2VHPyovp1MWHUhPfsGl Cicec2BTQreiNhgJSU3tuYBD8HFEOkNuG8HxwffyjMrTOQUDf5/DcRSh8/QZN9aRP7vqMB5+ouLB BM3Cm3zzlWfS/lNhRsCrewOzfzFINfPGZqgmtF/1UyksiLB0VrU1KzHhWCMK6qwQepPPMmH1Ww+H dhP/5e4gNAw7t33+ciyoMyKCb/1I3sCedU6yjgejvKIdLhu4OloBAgbaBVAYhb2QP5GixZZruar8 K5r644IqRnPKDjNB2MY1tUwguYv2cPh3zYwZvI+maiWwHhQAHwjXFwx1y/zRxF9+OnpAHpeqga7K cmvuqKPjBhbGo0Vk/Dw7A1CQ4CG6b6M1AdZYpimNvVrzA7NKArpavLkGw2GCxuoWS2GCBqcumTKP MVGztQTL4F7W5ufN9sjaCh1Lh6LHjWq3ufgoEP3DK6R2KPwPrRnfEsTQLbdQS9SGjcpVRNcpQfAV i3OBYmpj60typMrGJyAP9EqSaOwlG6sWtz/p1e7AG72uyH2OT5PMSlQ7z3WCFYKRc/eI7/svcCLw TV3v7TH8B/1z+usu9X3y5Ad4fnvZ1jaSCKRO6KEjdKoIKJRsV9UnmMm8XyrUZtRcQpdWogyhqTKZ 3hODX4nK2UKq0ZPcoq4unvTXSvUW31Esqd5c3IcGDTMPHGceQHYmNfhkha6dJvTce7iJ/Dx4eMzW k5DDQml26ol8E9GGKeVa/awQmyAqtlmpvtHU/sBtxfrCTFmD2TcUGW6FdwFXMTu1MPwHJCE+Uwe0 VOmcC+/Mgaron1eLzMWV8XyW0ACztshoHbJfD9d9JsU1cJbGyOYQXu5pydYlv0r7f6HmDVxM7O1S rCuOYx2DZtSqmHzS1d8qCYlF2TkW0CVBcb8FCABSIM6caQ2aR+2MnCP+f/2uXHkH5acFGclk0M3n xc2A7ebD6mzZEOYWWxJBDElzxDKstwuB0ok5v2gwisV8CeuWAs8bjHOs5An7XdyM5g/9hyxXZivj fr0OMVLnw6u/Q+8rJV8/MoRSJ6wjs2qI8Z5MJSh4pBnHrwZbv2MWl+AIAMlq94qF4weEhBVNaHGH CfVPrMuRFwHVRkRhdFZAcsjaQBs+s+E3oenDYAe7Ko4bHmAA1sKKYLiatMXxmmwXSSCz6FewD4PM EFO9Gv7SsiECezHUmJxNcolWOsuk0RE9MakoNlaBgzKEkiDTqa13GwLnNg9Ck+cLCcHgnzIO1Njk L4b7LBFITgmMMm5B6INns4IdMbmaNO6KziwlBDOx22CmDUoV38m699UmEYCaUoDauHrMWbFAX2Nh 99QDJ0gI/4echrXMMbmcWyrizwN+QOYXN7WcSBMBW3iyy3ttsbDzaeq9/oPU18zzPAM+D+zFmeR2 zdbBrzQa9sESX1LphCo2CrKvbqZOJ65K3Sd+BlGnzi2uADnDnEqjwGRXXAnPihzVAbwbYxSLMvk6 bz6SW+eG9w6sZkC8M6DnGvKjF+Qm5tm241A6vyreUHmwA24lFL2F4DQ/wcOaGIxI1V/cxiaxxG24 bhp4Q3ZDgkwS12sHr+j/380mxAtPIeOyNv5Jc15jyBWwkCJ+pKuzrwu2la3lwDcbZaIRB3QwG7Jf +b1aBgR3kCCQkyUMFk+7nJuGWWpI26G89k9mbt7RGBKNhowreUdEkunfV3Ce6DswgpB0DHe7dO+x tYunTbfkcJvJCaDIg7MmBnaK7vEHSDIQ3vk1/JqRqFQj88Qiw5BwFV10oPymHswGDs5Y6PIHtWvN 0OdG7RqnNFk0sFTQkgR5IsxR6CcQIL7TUw/dBEwMvmQ8tO+jtpxMwOPKu5I1RjaTOYHWhHWp5c7V u016PT3exfxVU6/P2PRvvG5ppHbkirnTGwfDZ+0Z1HnVvBLbIeYkU9VlfXZdMcm7gBcbme7Lo2Ie NpSu2PZffaAlMGWZjninpfmmeGrjGRquaDcN3kbZA+M0d4d4v6QtTLCCZDKC5n/KD0pphYQ1yEwT 0e8gU+Q2n+LvWiAji6Ij6kRFmwkk/Ym2MuKGSakMztcBzZdTqCc22uHIwNPqU9lNGV64pnT+6O8s g7U9zg4/JzFhnIO8EtTmid/2CZhfhXsyAB3ze0Ak+sHyY9ad9eZNwnQkJ2UzOsaKXYa/8t+ZvTAS btPANzI6CtZktmDemOgTWKfrwG4Z77GYcEk4VOzTFeQfsVSqJ1SyAIMGgqQUF+pGk22sT6h/6xmx zv6T41noCLQD/2wf31d6iEkF+z5HA86qxKIduLnahwesrHJnZoQHLtO/hg6W9q4tpmy8dchOt3vR 7NcdOx9P1A9EUI3iNDQCD4ppzR08rxLqrO1f7wdD8FtZuyLGgcRceKh/9iBM5MYtFphzbai+Y/NT +30bD8xPgfqjtCtbeuAjR0Sh8WeIy9gDKwc52WwOe7ljeiABuBxt0WpaYOMY9vxWP9J/IyaUWi54 4bH72orR/xMzYfnJjD0qjxak7K+1Ebo1ieyrkJFUoqTJsM2nNolYkf281GAO7pp+BkzZyvUxT6c7 bJlMXA7bUFfEtIEw+Osw0rZ1RASz2N0aFrVISS0O9xN/TFlWN9N5ukA4cn2rjzxCAVg+qTkacZGj rCP9graLLlQOkF+pC5atmThyzkSWPYf+2oYU84nB5w1RwUxI4otUS9wKKkMgjXtp7d5S/fKAFVfG ysAivsHGSG5R4bKNY5QwjJ/6968hMuVya9rih0BjYQPX9VC4yTuyUtsn7qW89ivRqrKy1qYT/xQ7 bY+dA/ciLOIdM2mEWvwZgfCynEcS+Pzqx0w/WR2HUSB1r7hKIgyrXjOC7egRl+cM9BOFaQmJBL2F kJcdNUzEO7hPsyDvlbZ6G8pdkEZDeQXn5MtHpFw/KMAmLXuBxBoPMTDD7XjsZTR171GOdb1mcll9 19pbVmD2rH4l0dKbw2J8qX6swvH7+/eF/l7k40+b4jZQMmHSkbbxrHTbTTSqHrVlk6eWZ0CuujCm 9PrZ3s983CBMJnA3GlCkvwK50OoQFFweh/2Hd5bBoXZUg+SshWddUSlOoq5nZlfeB0hcXfpYkOwt C/TfGMV56JMsRwITN/SkKO04Hgc6fQc6qkEpag40qHmTNgDSWOfHuskqDoVpHBGBPqAE+saW6FMp YmcxpAKVJKxfvvyIEUBAlomVPep1FH1wK0Q6punWKQasWvG0qdmdjmDh01QIff56cAN1sefxkwYH k51x7eB6p2FZ/DN6fSB2fYfP7Yg9HFTKcj8ef1Bym7/QJRHw5PbTw1A+RX8sNM4dbuzQFX1WsaXN J/F26uB4ePpD5ukYZ6C/Fenm0EsDQ4ztrXPvoGT1UzkkHNNGS8EGXQvW5SYsScQWcO2l4JI3V9lr ayfyEkpYTAY/goJCjCLUTpecHTO+LW5xQMPp93TqgereowbY0WIDoU1978EVVQlcZr2XjnsoyO8u Tj9ddSY/bj52JU/ncZVEX+pcvAqiuo8L4jeeM2zQc8hBW2zvvlUFYSSqrukjrKIcx26CC3t92CyU 3344G28F5g8PpzlcvW/zQevzj8wXNI+0XkSEDZp9db6eJ0bCv3oCDxdwv0CA9wIAYq9XYqvn64RM lvol0JsLKJNQ+10znu/ocWJpvhlWYvvn2tt4Nb+V4NIZGmOZ4p9dpD0L/wBawvlgvT5bDKjEFIP8 1OBK3j3ho7+ai9XZqauvpF+aIBvqrzPZ7wj/fiyKCZpWcstSDSvXfcRhBBRkI+o86RC7vs0SOSqd T5rhbnqyil3D/1goL5PMVEoW00401lLrCd+zkkejZqK0Al6+zkepngWwOyEQAlM19owEMIaNM2cL dwEfWOcPpfx4Nxzpp36wUaaF/yAz1VMl6a+ovf/lIeFeFk4IceDOA0PapHAUjnWnInce8cgOdr2B p134X8lSBSmziEVvJW9sW9FP3M9Xou8+TaWQgkT8RkhzP5gzLkRbfz/kxE1m6V8e8n77J7JHmnK8 T3XM4sxf+sdEpaE6oOSzIRDT1NL7d5KC4r6bI9icoLS6Ug9fJL8HMLvOwFtrj+K78q8mqb0ut1bY fTCEyh39fot4pOBGhSJgBXjXEnDKOXvzM08S0rBwFVZhHHbtXf5wHNuPnWYFNXwArkCBPZLkrB8G azj++KGft7tP7KD2c4asdVZuzSKiI0UCRThyqY68yeLdJ4I5raRtfygrShHo5hnhUuZ+vcK4mZig MN9d5f2ncdrtDmQWQWCcJXsWoVUbD73fz9KCFSv+bJSVWtvGCotvRZQJkGCXGX4GywfgzwJL7Ia8 hdL+E8NMKcQ0Xyjqe8sF45B80bSzv/nILgAZezqqVHjgL8XfTvWDugeSMEZtd+XYVNcQ2r4hh1fV rfqgBcK7Lqhqik31Fcv6plYuZwlSdS6QLmFbGJmrM3aeRuCSITKzKv8b2vrPeSeQRnn0NYvjwN30 WdBH96SMxryYnzbcNbwt2cwyb47TC1ABhh4VSr8+dSAi5IpcfVH0lirSnmJn7iqlDNXk6nvEsXxA WMiUtohOXx3BXSU/ZPIHO74Vu9Goo9wm9l7aCiAcXXzF0Ke8GthcuJ8vHve0eeAu0XqxqgpwXLi1 Bs7OfGoNoC36vJNAqzCLaPXl5CJSSWuOTWHKPsy617fPHbicLO1I6pdea9nntSSamFVfisjxI3MW DfLj0R3udqh6X7qPxEX0Tzzlt+XyU20zKZgt1cDXGqKFDTmpJzQA4ko22drmws26lRXIA91KuoFZ p+BZ7czB8HyiwOzzWrBGA0ReUAV27py85PBMPJlh+gFMcG03zPXrNqGch9z8tFh/1VAls62/6Ddy 8GfAkltZyl8q/d8MRiDM5R2RonoC67YJl4an18W+qwN71gXOA5o8XbCa+7iBuJz92/d7GpMkDIHJ j/fOmyetG9ZdKfNEfWtcGTZ1vz9G+5odQjEgYSVC3RErKMREr5K1kR1mUdZiyHiJncWlvIAum26C G3+Hlwq9bIyE1ECmS6ZIm1VeE2VgycYhQTADzIYxLBKT+KjJiMaB32C7+w5VqoeFlPKK/DXXuH// r44w51JR7mvybF594ZYYds2yqXdrItNspSz1uU5f8DQ39F83vW/JBmQ1zv/lcuAkZdv8Uji2OxLL obq1EFFvP3+STnuRi4JZjmoxVCIBnidcHN0hq6lNDdEbrv1BJ9HxN6ppWUJHRsydw4RZT3ZXpXj7 5M235BkgZUyU0XUqfv0mjBIx5dd0p6NHmkQ2xo+op1W7dJRzfcRw0+sZWEwFC6mwPc13v2alCppr yml4wNPJ4rT+lfKt7vZrKM3d4zPFLqxUTAnP2f3BSm+j2aItYzm+Vybw73ITBU1IaLS/zgJ5nIm2 rbIUyJHdfedhzJ46x+Xv3jcs5Nu+oXZ4I8Qy0Myoyh7G6gAvU5rA2WwB7cR7uG+4Ib/quG/oAc+b E341x8TpKcVUIq0bVEf+I9q3+pvJ7dCRHunigoZzeQUfmqePNfN0LKuEn1+MVb8wrYwrty/3fpRp kC64tuZlmzVkdePyIIX69uw4IDqrdAjvPNRMLB0pxG5nrjf5iIP7qC60L09XpQdOIKNcuTgPDRw6 uVNwVaaftCIzLTmvK1qcubxea2lec3W63wzyCJ8pHO3j61l2uUr98GyqP0IbjhMe6sUihs0YB1Mf HFCnS71UcLFrQqjYs91ZHbNNBZSYfWxxCChRHflqqR3ZEpLyN6LUHXB99z1S71vcsWuWy1osz932 RGY+k2K6NVBTflCNylerKecDr4tjkw81N8j/7oxzC3rNGivhkTIewJtyCZV7SRaeCJzODXfTIFGh z68mTx3f2tuhGA+k9UU1OYLLl/f1MSQLXzEiyd+ydFsc6yTAYRtXkvLjnwFh3yA0V9H7rLx/P8nC iunAKO593zELp4AKBBPKMY0saoxvpZtddejn+YC7dLQXLavFrIeS4OUXVnkpoQU1aUKHLaiiOZLp lt+0O3aie7aWtihUXFQnvZD4194rsZE/v2w7SdUyrYWelW7s0IJ8OychbrGT3SwvSAkcXWsSDwLw X13XM/qkwIzky2FoovpDQDBNbaLNFTeV/oTLoNp/EZoxCm5kkqfadB4uMDGvU28Ut0xXOz/3wLCu iFeSrlo+Drn5Yu7NZnVKYy4KOT21lSo+0+VuazH96fB3wq35PG9puYjeih8Gbj1iHPg/XUJhuOZt ehsJc/SAhN/Z0QK+kXYLDH/k5eEPyMEADNfTZmXMvuDLpbqHwU/jIDpikOYhghTtcbRvpDRDdRSS U4pC+9FXZ9ACizUPzH1lFGlQs0buk1jzRSYnp+wPWeNE635Zo9zXG2nuLXwYo6sWmufeHpJLBGC/ rS4pL3zLnffVbMQc25hG12sGq6Gpxw/LLxZNMCBg0JievUQ3TcQ5JK6n6a57jb7/WfHUtzUtvaYf Qh728Q639I0tOVxvPe1wtwtkoOBA+ouVDElxhqy9Tn/FhNSyBHnQIAfrLC1lxpp/2KYvK9halNgU +KPe69LEGjFGxNeIMGMcJXBOVsUW4Wo09WHQCqA5fMckLi91kZEy3r7WsEuVouiF+2NpnXl5gcZY yBgv/9EnfOJUEHcC/kSIcMKUR64NdyYVNmOgHthLVHPMhcIrk3XPPxzKDj4FKJY7mhi1pLqOUiGM 1/L/4XjdtmAM4cG+wClRetoPHCwV1PuobCAxSdyRCcsDrcbItMiLtnc5DK6B4hK1Xj9tGKjpME18 M1KTAH0xP70UpEDGPb14A/Ecldf3q6K7GX6vHn/aio25Fqs9+1mgmABQ1C1rg7D3mJ0ckNRiexdd KCG3JuJYpB0lJPhd9zVxyNVwriqGxVBudweNf8IrAHzscfMvDi+3A7xohLJJWK7HRNC/ndxHMvxq 8PZkrDQVovaQbf+EBZqBe1thSH6N2KbKKE8kABhNrFHltnt8vMhNcz/9RqQYRmmRLhayTs/Lakhx XIfXj6jJndmo83miUReEFVlxwxCsjNsckDkX4MbQVsfTBHMyPXU8F75pAeP2CLkA0bKlWbbVc4L5 YxYBLNQFbJM3jCfdKlYh01q9CKWjxtoQZeO3SzfHVUiITFxnc8fxj2kIUKryilqTXBSurXTjjXvk mACBBoko4KGanV7DTBqmS62mKPs/J2kIQJ/JbRSQyZTzV+DUsfB0uV0KW6ajQaQ6yoFCCoVIDqeD +r9E1WeKGKvrFjzy/Lz7BEo2ymbE0xgBOE7XYdKXe2nUY71+K5p/IkubjPq2fZiwceowlRDSdyUt cZbvpRZc/vaYm+hsw2YxrivJr3ez7Be/3+3OMEZeQs5GrSitXbJLXRtMUoKjU3fK2sE0mc3aVTc3 QrFi15AtNyL7Wy6lzMbROkYxwMl+UrJ0iPAfDMpsF6bYr/sV+SA3mYB+1MREVLo/XJDqbyYVT0Yc 6w7i5vG8uFjKi/hr1Jie5vp8UuPQdpawPoxWbLQz2pEpeG9Z/vlNtvAwq0FflZR9Hiy0R2PfjGMm uBfjOwNzByOi6kKXfgMxPTgMwCLncOjGng9DZYG98a1paYiI8bf/Z+KqpgMKGkYg0dpJzj/m0WCY rqTsZM0lRsXBpo1jaOQYAxfUIvFKYztuAA68gm0a/YrJIBqqDocTZJVkp3pZ4r7ZZ6AzeHoaZf7E 74SUIlp9ow5Rx0FJhLyodHgP0JlvJtsPeYx6b0W3dqPDj/RqHVBeW8QKqSJjCcgEAtyTWmNebl2f e6LlunmSYqm3moX0NqLP/wEeYBDghM1R3+PSNfFTmiaqjwogHcnXNMdM72B9nx+Y+oT+fDRHxax0 HCYv4vgTs807cZVf85JuQl+WatT7YYXP+KiqX90qDM57qrzwLtcOf/hRig5qnj9+ksKikNdITAmf i0SVFXQHC+/dJ9Uygh1acgIHUfGVIhTupF09LChEIy0bmwWRSY9swIe/wccFl9bZRfNpC4eF1XxZ DOEOY9NhlJANvfh3PnZL7qXRa2PozfDYHgrHUYk6MI0KsXaN03CNGkPEUxc80g9ytkpsAd+TzTD1 WfcYV2qUCkST49D6Wd0mMJ42fAakqB4+drDuhXzR+bHvGrm9fw3/ZBI5HGZzc5PGCOSqUWCuvG7T fuYHUMdFwwEtFoy0ySgH9gTfsaLll1ZKSqD78tdEAVTBXGJj1n+diirnUgKAFH2ubr3QP03dK0IJ xZ4LBQ9PLah94xYFHVN43uypBCJOBxKbY3m6kLLCtyJOW2YCt/tbu0YOzKKHGIIR8WcfaVzP7c1P FezRlWgn4ntbt3F3GVWZYqN6FhQmd+ym6BUYR4BiGMs+/0Rn7YnqbkZVe8IwvYSRmaEO9z8E9I1Z 7bnpJpCUXucDF4p+Ohqw155sf2eUrevX4rxBj6WkV260495kjKZSKNlH0wdPt9mdTA5H5WeU6V4f NxcjdbqP7C6+KqnHa2dGePxZ8Lyhd09Hj9YzfCvyzCHRlGX8ROGRHpxaE9x6Jf/RNJz+zYlzhbzs /LlDnpN9JFFTsAQeMF6MfY3F7RGiBPqebWwFR8CsMQ4W8XPIOXuaKYyylOYb++Drw4CK3Vv9LFzl +A/fk4eZOHQ9IhX+EHwGNm4GWWESQNg9Fc9yUpyj+xXbQDqttvFID3u4MWNV31VQ2brn98h5F6NE 1QsfY6Dzcjey9H1CXFLdllcrBnF6mEar9xYpEyRNXLsOsNTrckLqzP2dnj4ACRICh4bDxoPZzcNW xXsvW0W8rOJId0P0vUoVruR0GUjpGX6rFxD1S3WssAnqpQecSJ4HE9ZbrntAw7zXL6aDxePQmjS7 +S5YTXFS4nKMOiGj3n0hx/yo6Lre2tDh0S8R+b5mb9Wa4NMTuAtGA9hAttlu++H1VYQf1Pj9TC0J 4/zNyetpYD2mAGW7UCWjwVesT2Yu8VIzLRmU4bttf2kf3/VE0YwCXDS5oAHkH85ufacusLmu17Kj vN9gqSnhIZxHH1nbUup2fz0rzfgpN9P1p4oAkjK0/NSDw8bZOSIqetArZSAVpg/SktGqowyg+O94 Xd70Q8ASaC+hTa+M055K6w/oAHSk/Pxu2nvrvmkqQ+bLKAMKp484IGjHSNVD///69jkgI+4IFnwA nu6lGc1Bd9ESQz02JDsXIwVvm3mTtwIgmlm+xgASGaEE36LNHKijHNNeZjPYGS4ruUE836OFzz4Z tTWapLGklaz34QdaIFpfombdnV1rQEvllFqeJ6DVo/qvaS7WzKqWXyKfPF62Y4oeXYXQPPe6sXtC xDwvU+s9nroMCX6VfJXipzRmNYPEycByt+Zc4VlwG3RUyGJRFSXpYwPHm7GTV5nRVvbFpFdtqOtU WlxA15+gcXG1fndKEZdwq6n0zzqpjP0mSSmB/QJIVeMpLmF7NJo+Oe/xOLdpZXf1jI7lccmihQVE 1tpqKZuPZm3DojCoSc5nbQ1ka7MXmUIwVE/Hoz6SlyjuNvkUZm8GufiIGf+Nzp6hSmY1+2IkgGWa l0DbdT3Cgh/JtPLA01D8dQoxkb9Ztx4NH3c4+3vBZ0Wu7N34W/E0GaRjgVbie2D/Tpz9yNjlGBpQ ZZBA8yrD3smw2NrGLmuG+ETQHQcoCKDO/sM4AAiYNvQXEXN+uuZuru3Ndh/ppWDwh/1qOP1kfvgf QI1QSY4EjEPwgV9EJ59Q0P+RpiiDzxa5D3/SF4vXfJ9iuY1Mt3V19DMchnLnQ592OqOEp3s6Exr7 th/cnhytGnZArdqtl/GU26TrvSuHH6QQ1gY1w3RQQRS2fuNZUtJPV+ImLzvTeYMtQoLUrBk8EU9f 20UDRCnAruVNLpM0YqoqxO0uUPCCCYM1RmAfbGf4+foDDRE143uk8lYfQVSSlfTy1SOZTY6AyByY udyCsxlRRG/2aAYbe0F1LMP8Bo7t+81Lyad4mgf27kxzDb6O4MMFm8rJRSYW4Z0x6WoAwK5HCuwB XSgRbXzA7R/tjyH1seP6xH5asIXCu3OklsXNmycZYjlRqoL5sABGu7HVm2OLpgEhaHLAEx6wbfcB bn0bzkudXZVhswT8f4/rX/wSGPLiGux9nGJGdl3g3HocR9IRmFqwwo7zwREhVaXtyVBfQqFYWKUA 8KXjyH0sTYlpr5/rg7OBSjjUAe4GwKPB5489Flm5YbnTqLnhnDJZf2psbRvaYcM7upugJbs4Fvcz RxGyzuOF1WoFQLSTm54TQiduwY6awsD197ugIKWQiYt3jkY+UWh2mUUpYlGNTN9aQobtH76RZdjj klFnCvKyzEjDPzkukgEunqFTXPM2zMxPvcZ1LSzKGwwcSkLppjjfVeAQKu4zX2m397JudSPLKH6j VZMuz4dqqTcZFB3krSCsQ3kos90MeESuIAjO7wAdXO2Gyp9Whfmar6v6JI4gvS8ON5RTa6Niegmv I8+RzgWl957LmvGefGfrj6p5B2hEZ7SUNW0O09Z11sdHa/sCsEBUyCiXgUDwmqZe6mM/PvDR9AS9 yfNP8OseoF3PEoH5 `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block pBqd8SbxnErWrX3lyBBDaDLKX8hSp/j5Yr+Qm9jRb/9JUTybH1McKspWz+db0YzfLoM8Rsbks3xZ F0QO+ZZlvg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block H9nfu/oUf72/R62OBj/4D944lb73dgO7fFOuMJCE4aenI7iF3utXSTO4hpgrQ8McaV+063uC1I2p SowtO/PmhlxRipVo5KEq7Hhzbtvt5amDIBC05YVti4pxjbEI/kmWeW6ApomatkIzigzghecNWi3O dw5/lv3XsuSXKGnf8V0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block LHYKr83oHemqUyK1Wezwr1z3qiqaCVVbCTepzFi2rZrXgOFTcCRhqXcHptrNPAEIVNUU983e0J/f 0KmoDwapS9jLRSEt/t44AcYzVSy/ai/iXQJgng7HtLlp+4d5yiOHFpGB54L6O3dBpou3h7caNhhL jjFv+2NQ8/vJ/xJXwO5fh2Ph6YYguOVQ53PyR/4efc4uuMmB69VXQ320viKRtmBbQCmyLZzeWtFu D4qzTizu+7+B9LccVDGFdS5MPG9ajzsWHD/tFElptKJXuLi1qfJlX0wCtTtXoY+3nkHdj+d8GtPf YHFzKsVl3XUte66S5MbnjiWHmaZaMtS1k7u0qg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 4MafVQvjuuBxvIjR+OYUlKEesGBWmyoKTpW4+3dmDKYdKobe8ekpI4KwM+KYTh1JKxG3Qgsr94sv sXNAR2TjWeHLAvJhva65Oh3N+FSqhrH0zjkmu9XvgIV/UwkRDNwOx9c4++PMmrK6Sc3dNZpoycaC lN9AukRoCBpCWkU/kGY= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Oe9rX9bCQUY9pDwkxKbbIf2ys0cqImU27qEFK2Dw17YylEZy1DE0fAY/RnVb+EPxtWACfGlXlONl m+j1F3QtQOlCfFGG+seFfsBQSPHUmFsJmINuxeAGpMhxfKpsTFjDqKjDpQa8VcnDwKWm4aO3goL8 ohfQk4XoUdGZKXOs6aDCwCjQ3NSG6AcZNW0ORDZyS9Kio2rZOPAl2Iatk0VLalSOSKS8f5tT86ig hcckTERcoJMSnJHpKMG0Uf46p6lF1NxyM72QA47lZHQTdUAqzyv8wPWp/x+9NpDScFU+0BwCqNgR Wwy5LWtdGsu9PzUszKuMs6YlHHcqBdvP6pV04w== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008) `protect data_block ugPchIic85pVoazhFaH2TWuQjqsMIDhfmCLDBUOtUS/RF04DCSHl4KkxPTtW6P+RbyiD3T+m3kTR N0N334mL4z3weuQnltN6rjwv5421Of+ebjf9jNPWmR9lf0e4KC1P2a+RqcNXNDLyWLeUSh5xhG/Z 78Dc0xYUHiF3d+hrOZnBHDBSzBMBxH85jBmUl3hJ6N8TJlBFLvzDJLAwx9rMqd+/ukKUbS92XXmq GUfEtXOD/kOjfUAMdbSYK383ZTVeO8P00Ys+990ShfmBjW11X5zfC8a6pcCnYMWovhs5zhxlg5VY 5qaNHLAk3jG98jGzfgSX7h68H0TVRR7JEDFOWoBp6nHeaNm3GUeQnBHvRRf9iGTHwtNoBo20CT3s B+8CdJKTLLUzk6qAj2GsiBGHS8LnYKmNkY/fLp6AmB2/qs4DlNFJIF8WLDrSqDSxN7vLmxfW02dn 97TZdyIIRU0sSDWmckU00Bj4DR6lVWvrorzqz+TKptQht1fc7GrTmUsh2hItQeA59cOw1AOmZDS9 1wq0ZKLVSXAjdB+CY84byFDq/ggnql+ym9df++F4CndyzeHn/77aqPKlsW1vloWWAkuV+/oxdhDW p20TyTT2O/VPp3m+EzlmnnWV4xK70h3N6PHM98xVk6mnffhh/Vgh2FPYUMBhFoA1R5ZkVo2hBFx+ BdBPaixrD1Bh0/1sYSrIxRoyOp3yESYfh6j5q6cxlNTa1qH+ifL4xeUh7yFpIAKcpGKV/BHZ4BXZ dzcowFS0zr5D1j59GJ2fBtclaFagM874kSHoT7saPkMwJZzu0a9Suyo2oyHeDY5u0tqwoOjIxSPD LgfMjS5eI/7kq2LRK6vuUkw4NPeUXfLEpGv5FCJ6L5qj3kBW2g6KAhG87smejtyOyPsvsfynrIc2 3VnDVEHbU7JdT+65asCO43n+F2twwXTbRz3siKaGFW/pSUKMJST4WLbItR8/WK8o1ze8PIiuzlcV 2q4JbKB8FDK4mLtzmIeYo7UTwNP6U9iXbLmMvu0dzyoUw3NDGJK4KUCMCVvDKN1R/+YL7Uwr/kfr H2I7nTHDRk6JDcgnN9lfHUT2S8C2BMkKRraWkqRs0K6NTq153MMgQ0I68tioSH/TpTwOz9oXVKBC IPIOjB4kXex4kXwRz23kXOxBtWL2ufKqg40K9aFi7BK+LFkdT9TJGBCwlY11kGcbWle5fHFUxBgl D7qMX2r59mWmGBSSP9gWsTMEGB58WJb0FCVJzJGA6OZLDvK1GTVkE3XRxGSmgNPHSS7w3jMJyMM1 LUnr75CCm+QeHuKzLZmM4W96dN4nPXd6yqiYEO85iAqDcN94rfIuZjKzOQpcTx9Oi4DIbX9uESmY tjGl70Xxr/adCaR8ilSvqqc+b4MBKqY7ELJDs0L3vXhscTGf4aQPSq6GF+yybBqE/m0z770fLOgC kzFPyfhoCNMoGzjgznhNFl/K2SBBjlumjwB4VoL4kPAv9g27PQzII7LCyKyJowsuyed1QFyLx6e0 zPEPygamJ5b2aKJfHjhq6Imar4DfdI9b/lJ2m3mKH5VW2TviID8sew7r/S+Cqsd1khcH0dn+JSpQ Cz5CskuqoPSTdJzTOv3pTxDL59oUgopc8EhlWAJY+mQaF0YTUq6eOMJWIqiTRPuWQs6VbYgRaUWq gGyiyprJEh8tjGjzF1g0t47LQBCmfF+ET+Qos0n0Wh5P3AuYe2d26zA4VHkOum3I/l6rLBKqZWgw 80FOjGL5rFavkxULg1QQ4CE5oihzlPEto13KkUan3UDd4FbgJCBwxe8aBRFgid7TZjfFiKmhUFt5 VQdmXePim15/U9KY4mMIYrnEKT0toYoS7SwJCXalf9S/2xU0+tvNWpw1X6qO/7v3BrnHauRDb8p7 DXnByUOEvR5Iwn7KTkPdDsC19IFFE44KJQW/TLM47NkLTnUgjtpw8GJXRgECeGgmVvN4zDWAz4kH JoZvUApvZD/k60yS9lZdKVETDuGnJLMPWqaE9URGx1F68zV/t6gNNzi4Vbw84HrncqaVQ9wkyUgz NG85xmeRL3PM9bycBzo2/5tEUhya/xB50ZheKo/wFA+vGxItbWD3A/cZCrWTA58Qp5cdb0eH8meI wFkrjyP9iCxkcXPvTVMY8oL8o5pJxxGdMvGwC7jjkK1ms7Vqxk+flNpQwFOxc8Bhi0iZ0/TmPVEf F+ZGV5tPUjYRSTzxofFD0jffamlYZQpqwKkMAfWbYnog1yK+fbQm41jBZ/ovWhcEWoIbKWZIjFSA OD5IG/kjBWkEXyU9LTohftglq69r0maNKbr7EKYPsDpvo8izUbasMLapY/Ny14fG6BWgAYo5xI4s djD2qS4vNfqRKU4rAsx+aRpvVQxZ6OeKvHYxiqiIPhOi8yi5g6zUu2EdUUni0ErRMnKL38mmI4KK 4xPf2PcduRPfhljJVhFLQAL/Vx9rs8TI2ixHSpthP0bZl7TycX1Ef3z74wUQ6nP/jp9Yi9pNL4Es OrsoIJiJrNwmzskoRB+FpS0XmnGK+WXeWg8mUkqP5uDqsrTxbhy1nUF9+bxAHJTjfax7I9UPhkOO g0Ms31UeKJczoUQXY4xQ2756Cr+BoXCCgUE63OOGha4EZNIFVDjshALTXX/K1Zamfq3M4naQOWi7 h36LS6E/7kjsvKD0qig3B+bw4eYn9D7xp9W/b/xnQX1Y6b+KJI1mq3ewFW6FWhzfiushu/g1D3BH IVDnqB2RNE5KByrzrzTWfPXtAzqwVypuv0uPzMYjP/HUWBWWxaM0698XRYq6tEjyEZmrbmcmdddB F+978ctayhLeGND3gjJzMD9GVyWbsp22+eKzIrPfgf+zir8BuPgUT2EfbWNhBLNuDCTbpqX3h5p5 UQgkeDx9fuGyyfEwSY01Gj+b0y0ZfFaPQ8GsQKQ544ltOq5D2c2hxCm8+bT33Xox9Byh0dE54yji mtCKhyFgjWGN+nc8kZemzz58Qc+tFgq33sNTvW+u613NDE6weCWYbSHGw+zKAAKUT3bn5wnjKlNP Za0+LvGGrSLhqhB1E+mDbzQz9WPa7pk2U5Yx8hXeWw49WqeFimySWFNJyPEM3fxsATP6UzAn8oSB gaeOEqF9ZAokKdVC3hxFEdR4hES9AH5L8QlOcAwytA0XEPo7+VJ1dvQy+CUJFMSViL4UyQ/1d3w3 /JflFzwiR+Pqp+4cC7R1OcxV41N/Xis6AjZZ+L7AUqsfgANI6OaDHJs7hPXGw7n3rtuNAlK2NiwM bWvK56olPYG7yuoHmsKWkg4wJLoG/MjMFjZEijGpYHYAri6CzgPrNOGFw45dmw2Adhf7PPKe3wyy LOw0Ka9N83vjMWPcpVP+2ScLxhfRWLsSQwqGhh8AaitW2OiTx7ekbXijvvIy/TeTns9LEnf2mN7s IBe+4wzrMc5PmHPVAy16ju/wQ6j1XAbp9cyi6gY0S6FWOq1l8lKsx96z6qBwWwgxdynUzi7lARod UBJaDyt9i7nIhqjp79HJziAlaRo1Xrnt+LN/sCHD7PBmqF50pCSW6YzEuP164twgaiGlAi/yYTc3 kt2l9rDpHVSNaJM0oz662UavJO7BxnuoM2PoAzBcoBY78upERvNQBQFzOo9XtFM6zaeXPNJPSIJz H8F3j7maBdtYWMjy4sDalZ7Fyxlo/lRm19Ds8/86OjGDBNR9PMmPiZAwnLvtNG3yp5gmgsW1sskF +jyaMoW9SFHOaU0dQ9hPXG6sflnNACAOh4LqrSjDxOdDGXJIBbCV85aakvibPiTbvRihxfcymks/ F3Vg2mB0MLQN1C41ypwTN41Z7iy6mmfowNrVB6suL0B4C23X5uXmksOWaa7Fqhue8voYHNYz87AX 1CmUnsx+ESMgq+Cnk/6CljrQ65N4INHD44SXvqqsH7KGdCK/VJXrSrd2MBqWddVIeoLXCuqYwOxj ezDRKd9jCIrgi/Tp6uGj5vAaqWNO0i6KQ+V1odyjNq7xhDwfSyL15I44zNRkGVJd7ttEs2zo+e9M tTkR1igHWulM5TMUdbMdej0p4q9rY2Vpez9BWoTMI+NMTosN/VBa1uoXg3e1i5Mey6pH68hXSc/y OOl6NP0lAsF6r0vso9xG+KIJcJZ1ldonn048etdsDOsRodP/ZiitgPAjFW8b3r38t2L5uZfsEwWr WnyK9Yy27tLFMgyfeBmKMin/bqqg+xVK4GGjb8oravkTjBVW9VCYc8nzEU0RlL3Kpd4DNscR6Chn fBK2UambbZE0jsrc/gF32wOzEjsRYq2t/NxyOzmZ6TBogtMcqTuJUWvDPcmPB7KFI1xve5KpTnFH b+AGLQebcHUjlzNAfV1aH3VZWNbetP9Op++JhuKwV84xkXVR7HuIdr3CIedCHKzWW9k6bDKi27rn MpImtyw+Jhjrdjb6GpTy/V9Mt35CVz0ilaAlzYnQJBMH+HbaZ2u8yveI4vSTZwSZ51DlN6u2fdtZ OHLA4WhhHPzW93UgL+Z3Yn1ZfGH8L0XL0rG0Wmi5mZuQTP2nfGHnKvEpiUV4uhQnQoO4ovh+VRRa UdTp3aYvOwcLa1Tbfxs0zG8896q6sLndM++95zagL7jOyZnFmQddlKEtNZvqtBxvKiZzUa4mudH8 2QAR8ewUfAWLEQ3FDWqtbRklVLgvxrbFK8SrAIE3lwO5YHXnIYHasG7Q8kSregntWeOmW9T414pQ js7uEMYE6soIZDftkj7r2aw7chVXBS+0VcsvZ/buAIoIiNyiZISKmnQvXIqWI/07V/7ZcJb1Mul7 iyxId91udFo7+4FtchFIwNV+RHeV4jxN6vLH4C160myH5id0QWN9saHX31nAzxNCLbI/8NdaMApz Pe14SASWdOWHeESkoxp32P0cnYi2VaV9dE8aaiiuHcNyfSbIndQdMiAHZADN8h5t9ZH+FUd3QsyF Sqpl5mKnkQ4Iee+gH/GeM4GoWyqumkfLSfvgpjCP+glKrnG8oarvPatTNQyzZxLcT3qc3gw+2qD3 w8EFzIZpIIllJuwyHGtnzdAofwWQ2t2QhS2nw4dvDoLydqXqtl22O0UF8tdDfG0ePnfvBF1OJ6tX 27vnuoiD7/sNn1iXhX00lrc+/ZM5JU80RRA1t6eEcOzVORKNgDQJFnuujNJH7wLQ7EHTUmeR+sAt Cv1KJNSHlVz/cK7/iUC0r6axtv8mKAVntAgTy/SGFP6roiqTVFExrldW4nVtzASpqjulJ4OusT++ eOEove+a0qg2KM7bTk0Bn45YeIrsgjan3/mlE07UhfoZ4SSfMl7EtZvaRR3ipwx6e71+8ku0ngoS qy8nRgtaRqRY7Jk1nDpdNe2iqhTgF6b7cG3phYYw/NBlzKtuyfmjvBqZyBwCH9LpIGKRL75azkK3 lLHg6yhSIhU+EORJ2y1YtfqGUmiG9Niiw6+HG4pf6osSsJn2bE5IAMUdFnPsLXbLZGp7eSXJQyFq 8hpiZMpF1xQkxYpxz/wk5LDqfQjjU8223MNGUH4fNxNkw+ADIhqqCZqHIOIpsfQzG71AfZu814ak jBTWPgeR/JYYF+PVJCvoxDhcgNL8XkOo2SzCjPaxCZFctxOkd/vDMvfhEwUgLbji10FGbOWGlVBq NZCJSflITRjCxkEaeIs4knmuyTIB7itLSpYbJz2ASoRzfyhtxl7lRvRhoI3I8JWSjaE0gzCDLYgi RDsCb2RiJ8XohoAuLRZKRVerVZcZf3rUI+0/K6zcdFL0klSPqnlt5vcgh5NgguKaJ9GabPGAD2NP 9fbfs1buAvi4uv69L1MqWzQSAvacBFAa4P9AT8u+t+aH0rU9nbdivFCa4QBcrbu4dIurpEOTlz6v Q4y+hklWTfxSNJo3P03O2zVvqDbYdlUSMVa47POuEwZqhOYuMHlll8NMSrwLAgOBiQ0GMCj71pVW mThWwktWKUqfgfmCpBcf1vO3YgSc0eGbNhSvwHYOyVLBPc7ySaMgxTOBJYVsnEQHWtVqoSnTAk3G QvSI8/SSOhE95/e4PurKfyZRuJflbeXE//Tnmh5ucLit5o7PbNAx+7Vgzx7QWY2EmPlpS1vNTfXL E8YrX+xRsIaJTA8fEBWnr/2c6i8iEenn++STYpXoY5RK8zeq8W+hGwmkOPtbQzLKXWJlpFkYVR4o nSLEIJnCAjsqDoVa8M9WHzmMxduRz+5JHd+ulXyw6HuVbSfxGl7+1vmiwX98jOJV/B2rnUnZ1WzQ frG/pjNNX8cyOnWkREdG+pBC3KYfZH9J7OP2KLdC7ZPxSR9hYJYqhq0xq0pyolbbeIXSnahGLH2A zQklbExh0qDnU0yp1f5U2TmWZDcf3jcHCvmJAm+cSplprSIUCHpP9yfCr087fRyet37UlxQTirZ2 Cu275t1hYOJ0EpvJYJ1S6sdM1QsbzskwSDC8Y0xP98UWE6/+AMHdv3GnE6SvwNZMvTGJkn96ab2o 5znQmV8122xq0E6e+2wD/XdQve42BvedJmozWGevKv7/RLHlK2YbqQsVKlDxeFIBunkkGOBmRsbL aBqwLRvIuO95OqqPOiRjf3RRcpxxM7y2a/uM3IuxuvLPfmYxV99uAcrvlwJkoiAnFLTlQKD7L8v8 0aeXoVkGq8/cq0354bbX7VSOJvu4cu5VUhtCS1YI7frRP2oJmWAeQRekteggVCoDflkDUqzUsZLQ tS+fjwPiGPLI1b4K4HZvtGwp+EUT7UUzfFeEJNhEPPa+GT1sHRDq43kuHJUO2l6pG02DdQwejKvE BgHQyX4JsLUlFp54yHA03+7z/+1+hVbZf1gG19WdyGmqON33qKq4fecMxXgb08hJbkLI/bzfiPJo GIIUI4ZgP80hbq3wJt3KVfhyMfbQNTfFTs1DiS/ZtB2YMSgErGn+A8gpB2VHPyovp1MWHUhPfsGl Cicec2BTQreiNhgJSU3tuYBD8HFEOkNuG8HxwffyjMrTOQUDf5/DcRSh8/QZN9aRP7vqMB5+ouLB BM3Cm3zzlWfS/lNhRsCrewOzfzFINfPGZqgmtF/1UyksiLB0VrU1KzHhWCMK6qwQepPPMmH1Ww+H dhP/5e4gNAw7t33+ciyoMyKCb/1I3sCedU6yjgejvKIdLhu4OloBAgbaBVAYhb2QP5GixZZruar8 K5r644IqRnPKDjNB2MY1tUwguYv2cPh3zYwZvI+maiWwHhQAHwjXFwx1y/zRxF9+OnpAHpeqga7K cmvuqKPjBhbGo0Vk/Dw7A1CQ4CG6b6M1AdZYpimNvVrzA7NKArpavLkGw2GCxuoWS2GCBqcumTKP MVGztQTL4F7W5ufN9sjaCh1Lh6LHjWq3ufgoEP3DK6R2KPwPrRnfEsTQLbdQS9SGjcpVRNcpQfAV i3OBYmpj60typMrGJyAP9EqSaOwlG6sWtz/p1e7AG72uyH2OT5PMSlQ7z3WCFYKRc/eI7/svcCLw TV3v7TH8B/1z+usu9X3y5Ad4fnvZ1jaSCKRO6KEjdKoIKJRsV9UnmMm8XyrUZtRcQpdWogyhqTKZ 3hODX4nK2UKq0ZPcoq4unvTXSvUW31Esqd5c3IcGDTMPHGceQHYmNfhkha6dJvTce7iJ/Dx4eMzW k5DDQml26ol8E9GGKeVa/awQmyAqtlmpvtHU/sBtxfrCTFmD2TcUGW6FdwFXMTu1MPwHJCE+Uwe0 VOmcC+/Mgaron1eLzMWV8XyW0ACztshoHbJfD9d9JsU1cJbGyOYQXu5pydYlv0r7f6HmDVxM7O1S rCuOYx2DZtSqmHzS1d8qCYlF2TkW0CVBcb8FCABSIM6caQ2aR+2MnCP+f/2uXHkH5acFGclk0M3n xc2A7ebD6mzZEOYWWxJBDElzxDKstwuB0ok5v2gwisV8CeuWAs8bjHOs5An7XdyM5g/9hyxXZivj fr0OMVLnw6u/Q+8rJV8/MoRSJ6wjs2qI8Z5MJSh4pBnHrwZbv2MWl+AIAMlq94qF4weEhBVNaHGH CfVPrMuRFwHVRkRhdFZAcsjaQBs+s+E3oenDYAe7Ko4bHmAA1sKKYLiatMXxmmwXSSCz6FewD4PM EFO9Gv7SsiECezHUmJxNcolWOsuk0RE9MakoNlaBgzKEkiDTqa13GwLnNg9Ck+cLCcHgnzIO1Njk L4b7LBFITgmMMm5B6INns4IdMbmaNO6KziwlBDOx22CmDUoV38m699UmEYCaUoDauHrMWbFAX2Nh 99QDJ0gI/4echrXMMbmcWyrizwN+QOYXN7WcSBMBW3iyy3ttsbDzaeq9/oPU18zzPAM+D+zFmeR2 zdbBrzQa9sESX1LphCo2CrKvbqZOJ65K3Sd+BlGnzi2uADnDnEqjwGRXXAnPihzVAbwbYxSLMvk6 bz6SW+eG9w6sZkC8M6DnGvKjF+Qm5tm241A6vyreUHmwA24lFL2F4DQ/wcOaGIxI1V/cxiaxxG24 bhp4Q3ZDgkwS12sHr+j/380mxAtPIeOyNv5Jc15jyBWwkCJ+pKuzrwu2la3lwDcbZaIRB3QwG7Jf +b1aBgR3kCCQkyUMFk+7nJuGWWpI26G89k9mbt7RGBKNhowreUdEkunfV3Ce6DswgpB0DHe7dO+x tYunTbfkcJvJCaDIg7MmBnaK7vEHSDIQ3vk1/JqRqFQj88Qiw5BwFV10oPymHswGDs5Y6PIHtWvN 0OdG7RqnNFk0sFTQkgR5IsxR6CcQIL7TUw/dBEwMvmQ8tO+jtpxMwOPKu5I1RjaTOYHWhHWp5c7V u016PT3exfxVU6/P2PRvvG5ppHbkirnTGwfDZ+0Z1HnVvBLbIeYkU9VlfXZdMcm7gBcbme7Lo2Ie NpSu2PZffaAlMGWZjninpfmmeGrjGRquaDcN3kbZA+M0d4d4v6QtTLCCZDKC5n/KD0pphYQ1yEwT 0e8gU+Q2n+LvWiAji6Ij6kRFmwkk/Ym2MuKGSakMztcBzZdTqCc22uHIwNPqU9lNGV64pnT+6O8s g7U9zg4/JzFhnIO8EtTmid/2CZhfhXsyAB3ze0Ak+sHyY9ad9eZNwnQkJ2UzOsaKXYa/8t+ZvTAS btPANzI6CtZktmDemOgTWKfrwG4Z77GYcEk4VOzTFeQfsVSqJ1SyAIMGgqQUF+pGk22sT6h/6xmx zv6T41noCLQD/2wf31d6iEkF+z5HA86qxKIduLnahwesrHJnZoQHLtO/hg6W9q4tpmy8dchOt3vR 7NcdOx9P1A9EUI3iNDQCD4ppzR08rxLqrO1f7wdD8FtZuyLGgcRceKh/9iBM5MYtFphzbai+Y/NT +30bD8xPgfqjtCtbeuAjR0Sh8WeIy9gDKwc52WwOe7ljeiABuBxt0WpaYOMY9vxWP9J/IyaUWi54 4bH72orR/xMzYfnJjD0qjxak7K+1Ebo1ieyrkJFUoqTJsM2nNolYkf281GAO7pp+BkzZyvUxT6c7 bJlMXA7bUFfEtIEw+Osw0rZ1RASz2N0aFrVISS0O9xN/TFlWN9N5ukA4cn2rjzxCAVg+qTkacZGj rCP9graLLlQOkF+pC5atmThyzkSWPYf+2oYU84nB5w1RwUxI4otUS9wKKkMgjXtp7d5S/fKAFVfG ysAivsHGSG5R4bKNY5QwjJ/6968hMuVya9rih0BjYQPX9VC4yTuyUtsn7qW89ivRqrKy1qYT/xQ7 bY+dA/ciLOIdM2mEWvwZgfCynEcS+Pzqx0w/WR2HUSB1r7hKIgyrXjOC7egRl+cM9BOFaQmJBL2F kJcdNUzEO7hPsyDvlbZ6G8pdkEZDeQXn5MtHpFw/KMAmLXuBxBoPMTDD7XjsZTR171GOdb1mcll9 19pbVmD2rH4l0dKbw2J8qX6swvH7+/eF/l7k40+b4jZQMmHSkbbxrHTbTTSqHrVlk6eWZ0CuujCm 9PrZ3s983CBMJnA3GlCkvwK50OoQFFweh/2Hd5bBoXZUg+SshWddUSlOoq5nZlfeB0hcXfpYkOwt C/TfGMV56JMsRwITN/SkKO04Hgc6fQc6qkEpag40qHmTNgDSWOfHuskqDoVpHBGBPqAE+saW6FMp YmcxpAKVJKxfvvyIEUBAlomVPep1FH1wK0Q6punWKQasWvG0qdmdjmDh01QIff56cAN1sefxkwYH k51x7eB6p2FZ/DN6fSB2fYfP7Yg9HFTKcj8ef1Bym7/QJRHw5PbTw1A+RX8sNM4dbuzQFX1WsaXN J/F26uB4ePpD5ukYZ6C/Fenm0EsDQ4ztrXPvoGT1UzkkHNNGS8EGXQvW5SYsScQWcO2l4JI3V9lr ayfyEkpYTAY/goJCjCLUTpecHTO+LW5xQMPp93TqgereowbY0WIDoU1978EVVQlcZr2XjnsoyO8u Tj9ddSY/bj52JU/ncZVEX+pcvAqiuo8L4jeeM2zQc8hBW2zvvlUFYSSqrukjrKIcx26CC3t92CyU 3344G28F5g8PpzlcvW/zQevzj8wXNI+0XkSEDZp9db6eJ0bCv3oCDxdwv0CA9wIAYq9XYqvn64RM lvol0JsLKJNQ+10znu/ocWJpvhlWYvvn2tt4Nb+V4NIZGmOZ4p9dpD0L/wBawvlgvT5bDKjEFIP8 1OBK3j3ho7+ai9XZqauvpF+aIBvqrzPZ7wj/fiyKCZpWcstSDSvXfcRhBBRkI+o86RC7vs0SOSqd T5rhbnqyil3D/1goL5PMVEoW00401lLrCd+zkkejZqK0Al6+zkepngWwOyEQAlM19owEMIaNM2cL dwEfWOcPpfx4Nxzpp36wUaaF/yAz1VMl6a+ovf/lIeFeFk4IceDOA0PapHAUjnWnInce8cgOdr2B p134X8lSBSmziEVvJW9sW9FP3M9Xou8+TaWQgkT8RkhzP5gzLkRbfz/kxE1m6V8e8n77J7JHmnK8 T3XM4sxf+sdEpaE6oOSzIRDT1NL7d5KC4r6bI9icoLS6Ug9fJL8HMLvOwFtrj+K78q8mqb0ut1bY fTCEyh39fot4pOBGhSJgBXjXEnDKOXvzM08S0rBwFVZhHHbtXf5wHNuPnWYFNXwArkCBPZLkrB8G azj++KGft7tP7KD2c4asdVZuzSKiI0UCRThyqY68yeLdJ4I5raRtfygrShHo5hnhUuZ+vcK4mZig MN9d5f2ncdrtDmQWQWCcJXsWoVUbD73fz9KCFSv+bJSVWtvGCotvRZQJkGCXGX4GywfgzwJL7Ia8 hdL+E8NMKcQ0Xyjqe8sF45B80bSzv/nILgAZezqqVHjgL8XfTvWDugeSMEZtd+XYVNcQ2r4hh1fV rfqgBcK7Lqhqik31Fcv6plYuZwlSdS6QLmFbGJmrM3aeRuCSITKzKv8b2vrPeSeQRnn0NYvjwN30 WdBH96SMxryYnzbcNbwt2cwyb47TC1ABhh4VSr8+dSAi5IpcfVH0lirSnmJn7iqlDNXk6nvEsXxA WMiUtohOXx3BXSU/ZPIHO74Vu9Goo9wm9l7aCiAcXXzF0Ke8GthcuJ8vHve0eeAu0XqxqgpwXLi1 Bs7OfGoNoC36vJNAqzCLaPXl5CJSSWuOTWHKPsy617fPHbicLO1I6pdea9nntSSamFVfisjxI3MW DfLj0R3udqh6X7qPxEX0Tzzlt+XyU20zKZgt1cDXGqKFDTmpJzQA4ko22drmws26lRXIA91KuoFZ p+BZ7czB8HyiwOzzWrBGA0ReUAV27py85PBMPJlh+gFMcG03zPXrNqGch9z8tFh/1VAls62/6Ddy 8GfAkltZyl8q/d8MRiDM5R2RonoC67YJl4an18W+qwN71gXOA5o8XbCa+7iBuJz92/d7GpMkDIHJ j/fOmyetG9ZdKfNEfWtcGTZ1vz9G+5odQjEgYSVC3RErKMREr5K1kR1mUdZiyHiJncWlvIAum26C G3+Hlwq9bIyE1ECmS6ZIm1VeE2VgycYhQTADzIYxLBKT+KjJiMaB32C7+w5VqoeFlPKK/DXXuH// r44w51JR7mvybF594ZYYds2yqXdrItNspSz1uU5f8DQ39F83vW/JBmQ1zv/lcuAkZdv8Uji2OxLL obq1EFFvP3+STnuRi4JZjmoxVCIBnidcHN0hq6lNDdEbrv1BJ9HxN6ppWUJHRsydw4RZT3ZXpXj7 5M235BkgZUyU0XUqfv0mjBIx5dd0p6NHmkQ2xo+op1W7dJRzfcRw0+sZWEwFC6mwPc13v2alCppr yml4wNPJ4rT+lfKt7vZrKM3d4zPFLqxUTAnP2f3BSm+j2aItYzm+Vybw73ITBU1IaLS/zgJ5nIm2 rbIUyJHdfedhzJ46x+Xv3jcs5Nu+oXZ4I8Qy0Myoyh7G6gAvU5rA2WwB7cR7uG+4Ib/quG/oAc+b E341x8TpKcVUIq0bVEf+I9q3+pvJ7dCRHunigoZzeQUfmqePNfN0LKuEn1+MVb8wrYwrty/3fpRp kC64tuZlmzVkdePyIIX69uw4IDqrdAjvPNRMLB0pxG5nrjf5iIP7qC60L09XpQdOIKNcuTgPDRw6 uVNwVaaftCIzLTmvK1qcubxea2lec3W63wzyCJ8pHO3j61l2uUr98GyqP0IbjhMe6sUihs0YB1Mf HFCnS71UcLFrQqjYs91ZHbNNBZSYfWxxCChRHflqqR3ZEpLyN6LUHXB99z1S71vcsWuWy1osz932 RGY+k2K6NVBTflCNylerKecDr4tjkw81N8j/7oxzC3rNGivhkTIewJtyCZV7SRaeCJzODXfTIFGh z68mTx3f2tuhGA+k9UU1OYLLl/f1MSQLXzEiyd+ydFsc6yTAYRtXkvLjnwFh3yA0V9H7rLx/P8nC iunAKO593zELp4AKBBPKMY0saoxvpZtddejn+YC7dLQXLavFrIeS4OUXVnkpoQU1aUKHLaiiOZLp lt+0O3aie7aWtihUXFQnvZD4194rsZE/v2w7SdUyrYWelW7s0IJ8OychbrGT3SwvSAkcXWsSDwLw X13XM/qkwIzky2FoovpDQDBNbaLNFTeV/oTLoNp/EZoxCm5kkqfadB4uMDGvU28Ut0xXOz/3wLCu iFeSrlo+Drn5Yu7NZnVKYy4KOT21lSo+0+VuazH96fB3wq35PG9puYjeih8Gbj1iHPg/XUJhuOZt ehsJc/SAhN/Z0QK+kXYLDH/k5eEPyMEADNfTZmXMvuDLpbqHwU/jIDpikOYhghTtcbRvpDRDdRSS U4pC+9FXZ9ACizUPzH1lFGlQs0buk1jzRSYnp+wPWeNE635Zo9zXG2nuLXwYo6sWmufeHpJLBGC/ rS4pL3zLnffVbMQc25hG12sGq6Gpxw/LLxZNMCBg0JievUQ3TcQ5JK6n6a57jb7/WfHUtzUtvaYf Qh728Q639I0tOVxvPe1wtwtkoOBA+ouVDElxhqy9Tn/FhNSyBHnQIAfrLC1lxpp/2KYvK9halNgU +KPe69LEGjFGxNeIMGMcJXBOVsUW4Wo09WHQCqA5fMckLi91kZEy3r7WsEuVouiF+2NpnXl5gcZY yBgv/9EnfOJUEHcC/kSIcMKUR64NdyYVNmOgHthLVHPMhcIrk3XPPxzKDj4FKJY7mhi1pLqOUiGM 1/L/4XjdtmAM4cG+wClRetoPHCwV1PuobCAxSdyRCcsDrcbItMiLtnc5DK6B4hK1Xj9tGKjpME18 M1KTAH0xP70UpEDGPb14A/Ecldf3q6K7GX6vHn/aio25Fqs9+1mgmABQ1C1rg7D3mJ0ckNRiexdd KCG3JuJYpB0lJPhd9zVxyNVwriqGxVBudweNf8IrAHzscfMvDi+3A7xohLJJWK7HRNC/ndxHMvxq 8PZkrDQVovaQbf+EBZqBe1thSH6N2KbKKE8kABhNrFHltnt8vMhNcz/9RqQYRmmRLhayTs/Lakhx XIfXj6jJndmo83miUReEFVlxwxCsjNsckDkX4MbQVsfTBHMyPXU8F75pAeP2CLkA0bKlWbbVc4L5 YxYBLNQFbJM3jCfdKlYh01q9CKWjxtoQZeO3SzfHVUiITFxnc8fxj2kIUKryilqTXBSurXTjjXvk mACBBoko4KGanV7DTBqmS62mKPs/J2kIQJ/JbRSQyZTzV+DUsfB0uV0KW6ajQaQ6yoFCCoVIDqeD +r9E1WeKGKvrFjzy/Lz7BEo2ymbE0xgBOE7XYdKXe2nUY71+K5p/IkubjPq2fZiwceowlRDSdyUt cZbvpRZc/vaYm+hsw2YxrivJr3ez7Be/3+3OMEZeQs5GrSitXbJLXRtMUoKjU3fK2sE0mc3aVTc3 QrFi15AtNyL7Wy6lzMbROkYxwMl+UrJ0iPAfDMpsF6bYr/sV+SA3mYB+1MREVLo/XJDqbyYVT0Yc 6w7i5vG8uFjKi/hr1Jie5vp8UuPQdpawPoxWbLQz2pEpeG9Z/vlNtvAwq0FflZR9Hiy0R2PfjGMm uBfjOwNzByOi6kKXfgMxPTgMwCLncOjGng9DZYG98a1paYiI8bf/Z+KqpgMKGkYg0dpJzj/m0WCY rqTsZM0lRsXBpo1jaOQYAxfUIvFKYztuAA68gm0a/YrJIBqqDocTZJVkp3pZ4r7ZZ6AzeHoaZf7E 74SUIlp9ow5Rx0FJhLyodHgP0JlvJtsPeYx6b0W3dqPDj/RqHVBeW8QKqSJjCcgEAtyTWmNebl2f e6LlunmSYqm3moX0NqLP/wEeYBDghM1R3+PSNfFTmiaqjwogHcnXNMdM72B9nx+Y+oT+fDRHxax0 HCYv4vgTs807cZVf85JuQl+WatT7YYXP+KiqX90qDM57qrzwLtcOf/hRig5qnj9+ksKikNdITAmf i0SVFXQHC+/dJ9Uygh1acgIHUfGVIhTupF09LChEIy0bmwWRSY9swIe/wccFl9bZRfNpC4eF1XxZ DOEOY9NhlJANvfh3PnZL7qXRa2PozfDYHgrHUYk6MI0KsXaN03CNGkPEUxc80g9ytkpsAd+TzTD1 WfcYV2qUCkST49D6Wd0mMJ42fAakqB4+drDuhXzR+bHvGrm9fw3/ZBI5HGZzc5PGCOSqUWCuvG7T fuYHUMdFwwEtFoy0ySgH9gTfsaLll1ZKSqD78tdEAVTBXGJj1n+diirnUgKAFH2ubr3QP03dK0IJ xZ4LBQ9PLah94xYFHVN43uypBCJOBxKbY3m6kLLCtyJOW2YCt/tbu0YOzKKHGIIR8WcfaVzP7c1P FezRlWgn4ntbt3F3GVWZYqN6FhQmd+ym6BUYR4BiGMs+/0Rn7YnqbkZVe8IwvYSRmaEO9z8E9I1Z 7bnpJpCUXucDF4p+Ohqw155sf2eUrevX4rxBj6WkV260495kjKZSKNlH0wdPt9mdTA5H5WeU6V4f NxcjdbqP7C6+KqnHa2dGePxZ8Lyhd09Hj9YzfCvyzCHRlGX8ROGRHpxaE9x6Jf/RNJz+zYlzhbzs /LlDnpN9JFFTsAQeMF6MfY3F7RGiBPqebWwFR8CsMQ4W8XPIOXuaKYyylOYb++Drw4CK3Vv9LFzl +A/fk4eZOHQ9IhX+EHwGNm4GWWESQNg9Fc9yUpyj+xXbQDqttvFID3u4MWNV31VQ2brn98h5F6NE 1QsfY6Dzcjey9H1CXFLdllcrBnF6mEar9xYpEyRNXLsOsNTrckLqzP2dnj4ACRICh4bDxoPZzcNW xXsvW0W8rOJId0P0vUoVruR0GUjpGX6rFxD1S3WssAnqpQecSJ4HE9ZbrntAw7zXL6aDxePQmjS7 +S5YTXFS4nKMOiGj3n0hx/yo6Lre2tDh0S8R+b5mb9Wa4NMTuAtGA9hAttlu++H1VYQf1Pj9TC0J 4/zNyetpYD2mAGW7UCWjwVesT2Yu8VIzLRmU4bttf2kf3/VE0YwCXDS5oAHkH85ufacusLmu17Kj vN9gqSnhIZxHH1nbUup2fz0rzfgpN9P1p4oAkjK0/NSDw8bZOSIqetArZSAVpg/SktGqowyg+O94 Xd70Q8ASaC+hTa+M055K6w/oAHSk/Pxu2nvrvmkqQ+bLKAMKp484IGjHSNVD///69jkgI+4IFnwA nu6lGc1Bd9ESQz02JDsXIwVvm3mTtwIgmlm+xgASGaEE36LNHKijHNNeZjPYGS4ruUE836OFzz4Z tTWapLGklaz34QdaIFpfombdnV1rQEvllFqeJ6DVo/qvaS7WzKqWXyKfPF62Y4oeXYXQPPe6sXtC xDwvU+s9nroMCX6VfJXipzRmNYPEycByt+Zc4VlwG3RUyGJRFSXpYwPHm7GTV5nRVvbFpFdtqOtU WlxA15+gcXG1fndKEZdwq6n0zzqpjP0mSSmB/QJIVeMpLmF7NJo+Oe/xOLdpZXf1jI7lccmihQVE 1tpqKZuPZm3DojCoSc5nbQ1ka7MXmUIwVE/Hoz6SlyjuNvkUZm8GufiIGf+Nzp6hSmY1+2IkgGWa l0DbdT3Cgh/JtPLA01D8dQoxkb9Ztx4NH3c4+3vBZ0Wu7N34W/E0GaRjgVbie2D/Tpz9yNjlGBpQ ZZBA8yrD3smw2NrGLmuG+ETQHQcoCKDO/sM4AAiYNvQXEXN+uuZuru3Ndh/ppWDwh/1qOP1kfvgf QI1QSY4EjEPwgV9EJ59Q0P+RpiiDzxa5D3/SF4vXfJ9iuY1Mt3V19DMchnLnQ592OqOEp3s6Exr7 th/cnhytGnZArdqtl/GU26TrvSuHH6QQ1gY1w3RQQRS2fuNZUtJPV+ImLzvTeYMtQoLUrBk8EU9f 20UDRCnAruVNLpM0YqoqxO0uUPCCCYM1RmAfbGf4+foDDRE143uk8lYfQVSSlfTy1SOZTY6AyByY udyCsxlRRG/2aAYbe0F1LMP8Bo7t+81Lyad4mgf27kxzDb6O4MMFm8rJRSYW4Z0x6WoAwK5HCuwB XSgRbXzA7R/tjyH1seP6xH5asIXCu3OklsXNmycZYjlRqoL5sABGu7HVm2OLpgEhaHLAEx6wbfcB bn0bzkudXZVhswT8f4/rX/wSGPLiGux9nGJGdl3g3HocR9IRmFqwwo7zwREhVaXtyVBfQqFYWKUA 8KXjyH0sTYlpr5/rg7OBSjjUAe4GwKPB5489Flm5YbnTqLnhnDJZf2psbRvaYcM7upugJbs4Fvcz RxGyzuOF1WoFQLSTm54TQiduwY6awsD197ugIKWQiYt3jkY+UWh2mUUpYlGNTN9aQobtH76RZdjj klFnCvKyzEjDPzkukgEunqFTXPM2zMxPvcZ1LSzKGwwcSkLppjjfVeAQKu4zX2m397JudSPLKH6j VZMuz4dqqTcZFB3krSCsQ3kos90MeESuIAjO7wAdXO2Gyp9Whfmar6v6JI4gvS8ON5RTa6Niegmv I8+RzgWl957LmvGefGfrj6p5B2hEZ7SUNW0O09Z11sdHa/sCsEBUyCiXgUDwmqZe6mM/PvDR9AS9 yfNP8OseoF3PEoH5 `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block pBqd8SbxnErWrX3lyBBDaDLKX8hSp/j5Yr+Qm9jRb/9JUTybH1McKspWz+db0YzfLoM8Rsbks3xZ F0QO+ZZlvg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block H9nfu/oUf72/R62OBj/4D944lb73dgO7fFOuMJCE4aenI7iF3utXSTO4hpgrQ8McaV+063uC1I2p SowtO/PmhlxRipVo5KEq7Hhzbtvt5amDIBC05YVti4pxjbEI/kmWeW6ApomatkIzigzghecNWi3O dw5/lv3XsuSXKGnf8V0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block LHYKr83oHemqUyK1Wezwr1z3qiqaCVVbCTepzFi2rZrXgOFTcCRhqXcHptrNPAEIVNUU983e0J/f 0KmoDwapS9jLRSEt/t44AcYzVSy/ai/iXQJgng7HtLlp+4d5yiOHFpGB54L6O3dBpou3h7caNhhL jjFv+2NQ8/vJ/xJXwO5fh2Ph6YYguOVQ53PyR/4efc4uuMmB69VXQ320viKRtmBbQCmyLZzeWtFu D4qzTizu+7+B9LccVDGFdS5MPG9ajzsWHD/tFElptKJXuLi1qfJlX0wCtTtXoY+3nkHdj+d8GtPf YHFzKsVl3XUte66S5MbnjiWHmaZaMtS1k7u0qg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 4MafVQvjuuBxvIjR+OYUlKEesGBWmyoKTpW4+3dmDKYdKobe8ekpI4KwM+KYTh1JKxG3Qgsr94sv sXNAR2TjWeHLAvJhva65Oh3N+FSqhrH0zjkmu9XvgIV/UwkRDNwOx9c4++PMmrK6Sc3dNZpoycaC lN9AukRoCBpCWkU/kGY= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Oe9rX9bCQUY9pDwkxKbbIf2ys0cqImU27qEFK2Dw17YylEZy1DE0fAY/RnVb+EPxtWACfGlXlONl m+j1F3QtQOlCfFGG+seFfsBQSPHUmFsJmINuxeAGpMhxfKpsTFjDqKjDpQa8VcnDwKWm4aO3goL8 ohfQk4XoUdGZKXOs6aDCwCjQ3NSG6AcZNW0ORDZyS9Kio2rZOPAl2Iatk0VLalSOSKS8f5tT86ig hcckTERcoJMSnJHpKMG0Uf46p6lF1NxyM72QA47lZHQTdUAqzyv8wPWp/x+9NpDScFU+0BwCqNgR Wwy5LWtdGsu9PzUszKuMs6YlHHcqBdvP6pV04w== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008) `protect data_block ugPchIic85pVoazhFaH2TWuQjqsMIDhfmCLDBUOtUS/RF04DCSHl4KkxPTtW6P+RbyiD3T+m3kTR N0N334mL4z3weuQnltN6rjwv5421Of+ebjf9jNPWmR9lf0e4KC1P2a+RqcNXNDLyWLeUSh5xhG/Z 78Dc0xYUHiF3d+hrOZnBHDBSzBMBxH85jBmUl3hJ6N8TJlBFLvzDJLAwx9rMqd+/ukKUbS92XXmq GUfEtXOD/kOjfUAMdbSYK383ZTVeO8P00Ys+990ShfmBjW11X5zfC8a6pcCnYMWovhs5zhxlg5VY 5qaNHLAk3jG98jGzfgSX7h68H0TVRR7JEDFOWoBp6nHeaNm3GUeQnBHvRRf9iGTHwtNoBo20CT3s B+8CdJKTLLUzk6qAj2GsiBGHS8LnYKmNkY/fLp6AmB2/qs4DlNFJIF8WLDrSqDSxN7vLmxfW02dn 97TZdyIIRU0sSDWmckU00Bj4DR6lVWvrorzqz+TKptQht1fc7GrTmUsh2hItQeA59cOw1AOmZDS9 1wq0ZKLVSXAjdB+CY84byFDq/ggnql+ym9df++F4CndyzeHn/77aqPKlsW1vloWWAkuV+/oxdhDW p20TyTT2O/VPp3m+EzlmnnWV4xK70h3N6PHM98xVk6mnffhh/Vgh2FPYUMBhFoA1R5ZkVo2hBFx+ BdBPaixrD1Bh0/1sYSrIxRoyOp3yESYfh6j5q6cxlNTa1qH+ifL4xeUh7yFpIAKcpGKV/BHZ4BXZ dzcowFS0zr5D1j59GJ2fBtclaFagM874kSHoT7saPkMwJZzu0a9Suyo2oyHeDY5u0tqwoOjIxSPD LgfMjS5eI/7kq2LRK6vuUkw4NPeUXfLEpGv5FCJ6L5qj3kBW2g6KAhG87smejtyOyPsvsfynrIc2 3VnDVEHbU7JdT+65asCO43n+F2twwXTbRz3siKaGFW/pSUKMJST4WLbItR8/WK8o1ze8PIiuzlcV 2q4JbKB8FDK4mLtzmIeYo7UTwNP6U9iXbLmMvu0dzyoUw3NDGJK4KUCMCVvDKN1R/+YL7Uwr/kfr H2I7nTHDRk6JDcgnN9lfHUT2S8C2BMkKRraWkqRs0K6NTq153MMgQ0I68tioSH/TpTwOz9oXVKBC IPIOjB4kXex4kXwRz23kXOxBtWL2ufKqg40K9aFi7BK+LFkdT9TJGBCwlY11kGcbWle5fHFUxBgl D7qMX2r59mWmGBSSP9gWsTMEGB58WJb0FCVJzJGA6OZLDvK1GTVkE3XRxGSmgNPHSS7w3jMJyMM1 LUnr75CCm+QeHuKzLZmM4W96dN4nPXd6yqiYEO85iAqDcN94rfIuZjKzOQpcTx9Oi4DIbX9uESmY tjGl70Xxr/adCaR8ilSvqqc+b4MBKqY7ELJDs0L3vXhscTGf4aQPSq6GF+yybBqE/m0z770fLOgC kzFPyfhoCNMoGzjgznhNFl/K2SBBjlumjwB4VoL4kPAv9g27PQzII7LCyKyJowsuyed1QFyLx6e0 zPEPygamJ5b2aKJfHjhq6Imar4DfdI9b/lJ2m3mKH5VW2TviID8sew7r/S+Cqsd1khcH0dn+JSpQ Cz5CskuqoPSTdJzTOv3pTxDL59oUgopc8EhlWAJY+mQaF0YTUq6eOMJWIqiTRPuWQs6VbYgRaUWq gGyiyprJEh8tjGjzF1g0t47LQBCmfF+ET+Qos0n0Wh5P3AuYe2d26zA4VHkOum3I/l6rLBKqZWgw 80FOjGL5rFavkxULg1QQ4CE5oihzlPEto13KkUan3UDd4FbgJCBwxe8aBRFgid7TZjfFiKmhUFt5 VQdmXePim15/U9KY4mMIYrnEKT0toYoS7SwJCXalf9S/2xU0+tvNWpw1X6qO/7v3BrnHauRDb8p7 DXnByUOEvR5Iwn7KTkPdDsC19IFFE44KJQW/TLM47NkLTnUgjtpw8GJXRgECeGgmVvN4zDWAz4kH JoZvUApvZD/k60yS9lZdKVETDuGnJLMPWqaE9URGx1F68zV/t6gNNzi4Vbw84HrncqaVQ9wkyUgz NG85xmeRL3PM9bycBzo2/5tEUhya/xB50ZheKo/wFA+vGxItbWD3A/cZCrWTA58Qp5cdb0eH8meI wFkrjyP9iCxkcXPvTVMY8oL8o5pJxxGdMvGwC7jjkK1ms7Vqxk+flNpQwFOxc8Bhi0iZ0/TmPVEf F+ZGV5tPUjYRSTzxofFD0jffamlYZQpqwKkMAfWbYnog1yK+fbQm41jBZ/ovWhcEWoIbKWZIjFSA OD5IG/kjBWkEXyU9LTohftglq69r0maNKbr7EKYPsDpvo8izUbasMLapY/Ny14fG6BWgAYo5xI4s djD2qS4vNfqRKU4rAsx+aRpvVQxZ6OeKvHYxiqiIPhOi8yi5g6zUu2EdUUni0ErRMnKL38mmI4KK 4xPf2PcduRPfhljJVhFLQAL/Vx9rs8TI2ixHSpthP0bZl7TycX1Ef3z74wUQ6nP/jp9Yi9pNL4Es OrsoIJiJrNwmzskoRB+FpS0XmnGK+WXeWg8mUkqP5uDqsrTxbhy1nUF9+bxAHJTjfax7I9UPhkOO g0Ms31UeKJczoUQXY4xQ2756Cr+BoXCCgUE63OOGha4EZNIFVDjshALTXX/K1Zamfq3M4naQOWi7 h36LS6E/7kjsvKD0qig3B+bw4eYn9D7xp9W/b/xnQX1Y6b+KJI1mq3ewFW6FWhzfiushu/g1D3BH IVDnqB2RNE5KByrzrzTWfPXtAzqwVypuv0uPzMYjP/HUWBWWxaM0698XRYq6tEjyEZmrbmcmdddB F+978ctayhLeGND3gjJzMD9GVyWbsp22+eKzIrPfgf+zir8BuPgUT2EfbWNhBLNuDCTbpqX3h5p5 UQgkeDx9fuGyyfEwSY01Gj+b0y0ZfFaPQ8GsQKQ544ltOq5D2c2hxCm8+bT33Xox9Byh0dE54yji mtCKhyFgjWGN+nc8kZemzz58Qc+tFgq33sNTvW+u613NDE6weCWYbSHGw+zKAAKUT3bn5wnjKlNP Za0+LvGGrSLhqhB1E+mDbzQz9WPa7pk2U5Yx8hXeWw49WqeFimySWFNJyPEM3fxsATP6UzAn8oSB gaeOEqF9ZAokKdVC3hxFEdR4hES9AH5L8QlOcAwytA0XEPo7+VJ1dvQy+CUJFMSViL4UyQ/1d3w3 /JflFzwiR+Pqp+4cC7R1OcxV41N/Xis6AjZZ+L7AUqsfgANI6OaDHJs7hPXGw7n3rtuNAlK2NiwM bWvK56olPYG7yuoHmsKWkg4wJLoG/MjMFjZEijGpYHYAri6CzgPrNOGFw45dmw2Adhf7PPKe3wyy LOw0Ka9N83vjMWPcpVP+2ScLxhfRWLsSQwqGhh8AaitW2OiTx7ekbXijvvIy/TeTns9LEnf2mN7s IBe+4wzrMc5PmHPVAy16ju/wQ6j1XAbp9cyi6gY0S6FWOq1l8lKsx96z6qBwWwgxdynUzi7lARod UBJaDyt9i7nIhqjp79HJziAlaRo1Xrnt+LN/sCHD7PBmqF50pCSW6YzEuP164twgaiGlAi/yYTc3 kt2l9rDpHVSNaJM0oz662UavJO7BxnuoM2PoAzBcoBY78upERvNQBQFzOo9XtFM6zaeXPNJPSIJz H8F3j7maBdtYWMjy4sDalZ7Fyxlo/lRm19Ds8/86OjGDBNR9PMmPiZAwnLvtNG3yp5gmgsW1sskF +jyaMoW9SFHOaU0dQ9hPXG6sflnNACAOh4LqrSjDxOdDGXJIBbCV85aakvibPiTbvRihxfcymks/ F3Vg2mB0MLQN1C41ypwTN41Z7iy6mmfowNrVB6suL0B4C23X5uXmksOWaa7Fqhue8voYHNYz87AX 1CmUnsx+ESMgq+Cnk/6CljrQ65N4INHD44SXvqqsH7KGdCK/VJXrSrd2MBqWddVIeoLXCuqYwOxj ezDRKd9jCIrgi/Tp6uGj5vAaqWNO0i6KQ+V1odyjNq7xhDwfSyL15I44zNRkGVJd7ttEs2zo+e9M tTkR1igHWulM5TMUdbMdej0p4q9rY2Vpez9BWoTMI+NMTosN/VBa1uoXg3e1i5Mey6pH68hXSc/y OOl6NP0lAsF6r0vso9xG+KIJcJZ1ldonn048etdsDOsRodP/ZiitgPAjFW8b3r38t2L5uZfsEwWr WnyK9Yy27tLFMgyfeBmKMin/bqqg+xVK4GGjb8oravkTjBVW9VCYc8nzEU0RlL3Kpd4DNscR6Chn fBK2UambbZE0jsrc/gF32wOzEjsRYq2t/NxyOzmZ6TBogtMcqTuJUWvDPcmPB7KFI1xve5KpTnFH b+AGLQebcHUjlzNAfV1aH3VZWNbetP9Op++JhuKwV84xkXVR7HuIdr3CIedCHKzWW9k6bDKi27rn MpImtyw+Jhjrdjb6GpTy/V9Mt35CVz0ilaAlzYnQJBMH+HbaZ2u8yveI4vSTZwSZ51DlN6u2fdtZ OHLA4WhhHPzW93UgL+Z3Yn1ZfGH8L0XL0rG0Wmi5mZuQTP2nfGHnKvEpiUV4uhQnQoO4ovh+VRRa UdTp3aYvOwcLa1Tbfxs0zG8896q6sLndM++95zagL7jOyZnFmQddlKEtNZvqtBxvKiZzUa4mudH8 2QAR8ewUfAWLEQ3FDWqtbRklVLgvxrbFK8SrAIE3lwO5YHXnIYHasG7Q8kSregntWeOmW9T414pQ js7uEMYE6soIZDftkj7r2aw7chVXBS+0VcsvZ/buAIoIiNyiZISKmnQvXIqWI/07V/7ZcJb1Mul7 iyxId91udFo7+4FtchFIwNV+RHeV4jxN6vLH4C160myH5id0QWN9saHX31nAzxNCLbI/8NdaMApz Pe14SASWdOWHeESkoxp32P0cnYi2VaV9dE8aaiiuHcNyfSbIndQdMiAHZADN8h5t9ZH+FUd3QsyF Sqpl5mKnkQ4Iee+gH/GeM4GoWyqumkfLSfvgpjCP+glKrnG8oarvPatTNQyzZxLcT3qc3gw+2qD3 w8EFzIZpIIllJuwyHGtnzdAofwWQ2t2QhS2nw4dvDoLydqXqtl22O0UF8tdDfG0ePnfvBF1OJ6tX 27vnuoiD7/sNn1iXhX00lrc+/ZM5JU80RRA1t6eEcOzVORKNgDQJFnuujNJH7wLQ7EHTUmeR+sAt Cv1KJNSHlVz/cK7/iUC0r6axtv8mKAVntAgTy/SGFP6roiqTVFExrldW4nVtzASpqjulJ4OusT++ eOEove+a0qg2KM7bTk0Bn45YeIrsgjan3/mlE07UhfoZ4SSfMl7EtZvaRR3ipwx6e71+8ku0ngoS qy8nRgtaRqRY7Jk1nDpdNe2iqhTgF6b7cG3phYYw/NBlzKtuyfmjvBqZyBwCH9LpIGKRL75azkK3 lLHg6yhSIhU+EORJ2y1YtfqGUmiG9Niiw6+HG4pf6osSsJn2bE5IAMUdFnPsLXbLZGp7eSXJQyFq 8hpiZMpF1xQkxYpxz/wk5LDqfQjjU8223MNGUH4fNxNkw+ADIhqqCZqHIOIpsfQzG71AfZu814ak jBTWPgeR/JYYF+PVJCvoxDhcgNL8XkOo2SzCjPaxCZFctxOkd/vDMvfhEwUgLbji10FGbOWGlVBq NZCJSflITRjCxkEaeIs4knmuyTIB7itLSpYbJz2ASoRzfyhtxl7lRvRhoI3I8JWSjaE0gzCDLYgi RDsCb2RiJ8XohoAuLRZKRVerVZcZf3rUI+0/K6zcdFL0klSPqnlt5vcgh5NgguKaJ9GabPGAD2NP 9fbfs1buAvi4uv69L1MqWzQSAvacBFAa4P9AT8u+t+aH0rU9nbdivFCa4QBcrbu4dIurpEOTlz6v Q4y+hklWTfxSNJo3P03O2zVvqDbYdlUSMVa47POuEwZqhOYuMHlll8NMSrwLAgOBiQ0GMCj71pVW mThWwktWKUqfgfmCpBcf1vO3YgSc0eGbNhSvwHYOyVLBPc7ySaMgxTOBJYVsnEQHWtVqoSnTAk3G QvSI8/SSOhE95/e4PurKfyZRuJflbeXE//Tnmh5ucLit5o7PbNAx+7Vgzx7QWY2EmPlpS1vNTfXL E8YrX+xRsIaJTA8fEBWnr/2c6i8iEenn++STYpXoY5RK8zeq8W+hGwmkOPtbQzLKXWJlpFkYVR4o nSLEIJnCAjsqDoVa8M9WHzmMxduRz+5JHd+ulXyw6HuVbSfxGl7+1vmiwX98jOJV/B2rnUnZ1WzQ frG/pjNNX8cyOnWkREdG+pBC3KYfZH9J7OP2KLdC7ZPxSR9hYJYqhq0xq0pyolbbeIXSnahGLH2A zQklbExh0qDnU0yp1f5U2TmWZDcf3jcHCvmJAm+cSplprSIUCHpP9yfCr087fRyet37UlxQTirZ2 Cu275t1hYOJ0EpvJYJ1S6sdM1QsbzskwSDC8Y0xP98UWE6/+AMHdv3GnE6SvwNZMvTGJkn96ab2o 5znQmV8122xq0E6e+2wD/XdQve42BvedJmozWGevKv7/RLHlK2YbqQsVKlDxeFIBunkkGOBmRsbL aBqwLRvIuO95OqqPOiRjf3RRcpxxM7y2a/uM3IuxuvLPfmYxV99uAcrvlwJkoiAnFLTlQKD7L8v8 0aeXoVkGq8/cq0354bbX7VSOJvu4cu5VUhtCS1YI7frRP2oJmWAeQRekteggVCoDflkDUqzUsZLQ tS+fjwPiGPLI1b4K4HZvtGwp+EUT7UUzfFeEJNhEPPa+GT1sHRDq43kuHJUO2l6pG02DdQwejKvE BgHQyX4JsLUlFp54yHA03+7z/+1+hVbZf1gG19WdyGmqON33qKq4fecMxXgb08hJbkLI/bzfiPJo GIIUI4ZgP80hbq3wJt3KVfhyMfbQNTfFTs1DiS/ZtB2YMSgErGn+A8gpB2VHPyovp1MWHUhPfsGl Cicec2BTQreiNhgJSU3tuYBD8HFEOkNuG8HxwffyjMrTOQUDf5/DcRSh8/QZN9aRP7vqMB5+ouLB BM3Cm3zzlWfS/lNhRsCrewOzfzFINfPGZqgmtF/1UyksiLB0VrU1KzHhWCMK6qwQepPPMmH1Ww+H dhP/5e4gNAw7t33+ciyoMyKCb/1I3sCedU6yjgejvKIdLhu4OloBAgbaBVAYhb2QP5GixZZruar8 K5r644IqRnPKDjNB2MY1tUwguYv2cPh3zYwZvI+maiWwHhQAHwjXFwx1y/zRxF9+OnpAHpeqga7K cmvuqKPjBhbGo0Vk/Dw7A1CQ4CG6b6M1AdZYpimNvVrzA7NKArpavLkGw2GCxuoWS2GCBqcumTKP MVGztQTL4F7W5ufN9sjaCh1Lh6LHjWq3ufgoEP3DK6R2KPwPrRnfEsTQLbdQS9SGjcpVRNcpQfAV i3OBYmpj60typMrGJyAP9EqSaOwlG6sWtz/p1e7AG72uyH2OT5PMSlQ7z3WCFYKRc/eI7/svcCLw TV3v7TH8B/1z+usu9X3y5Ad4fnvZ1jaSCKRO6KEjdKoIKJRsV9UnmMm8XyrUZtRcQpdWogyhqTKZ 3hODX4nK2UKq0ZPcoq4unvTXSvUW31Esqd5c3IcGDTMPHGceQHYmNfhkha6dJvTce7iJ/Dx4eMzW k5DDQml26ol8E9GGKeVa/awQmyAqtlmpvtHU/sBtxfrCTFmD2TcUGW6FdwFXMTu1MPwHJCE+Uwe0 VOmcC+/Mgaron1eLzMWV8XyW0ACztshoHbJfD9d9JsU1cJbGyOYQXu5pydYlv0r7f6HmDVxM7O1S rCuOYx2DZtSqmHzS1d8qCYlF2TkW0CVBcb8FCABSIM6caQ2aR+2MnCP+f/2uXHkH5acFGclk0M3n xc2A7ebD6mzZEOYWWxJBDElzxDKstwuB0ok5v2gwisV8CeuWAs8bjHOs5An7XdyM5g/9hyxXZivj fr0OMVLnw6u/Q+8rJV8/MoRSJ6wjs2qI8Z5MJSh4pBnHrwZbv2MWl+AIAMlq94qF4weEhBVNaHGH CfVPrMuRFwHVRkRhdFZAcsjaQBs+s+E3oenDYAe7Ko4bHmAA1sKKYLiatMXxmmwXSSCz6FewD4PM EFO9Gv7SsiECezHUmJxNcolWOsuk0RE9MakoNlaBgzKEkiDTqa13GwLnNg9Ck+cLCcHgnzIO1Njk L4b7LBFITgmMMm5B6INns4IdMbmaNO6KziwlBDOx22CmDUoV38m699UmEYCaUoDauHrMWbFAX2Nh 99QDJ0gI/4echrXMMbmcWyrizwN+QOYXN7WcSBMBW3iyy3ttsbDzaeq9/oPU18zzPAM+D+zFmeR2 zdbBrzQa9sESX1LphCo2CrKvbqZOJ65K3Sd+BlGnzi2uADnDnEqjwGRXXAnPihzVAbwbYxSLMvk6 bz6SW+eG9w6sZkC8M6DnGvKjF+Qm5tm241A6vyreUHmwA24lFL2F4DQ/wcOaGIxI1V/cxiaxxG24 bhp4Q3ZDgkwS12sHr+j/380mxAtPIeOyNv5Jc15jyBWwkCJ+pKuzrwu2la3lwDcbZaIRB3QwG7Jf +b1aBgR3kCCQkyUMFk+7nJuGWWpI26G89k9mbt7RGBKNhowreUdEkunfV3Ce6DswgpB0DHe7dO+x tYunTbfkcJvJCaDIg7MmBnaK7vEHSDIQ3vk1/JqRqFQj88Qiw5BwFV10oPymHswGDs5Y6PIHtWvN 0OdG7RqnNFk0sFTQkgR5IsxR6CcQIL7TUw/dBEwMvmQ8tO+jtpxMwOPKu5I1RjaTOYHWhHWp5c7V u016PT3exfxVU6/P2PRvvG5ppHbkirnTGwfDZ+0Z1HnVvBLbIeYkU9VlfXZdMcm7gBcbme7Lo2Ie NpSu2PZffaAlMGWZjninpfmmeGrjGRquaDcN3kbZA+M0d4d4v6QtTLCCZDKC5n/KD0pphYQ1yEwT 0e8gU+Q2n+LvWiAji6Ij6kRFmwkk/Ym2MuKGSakMztcBzZdTqCc22uHIwNPqU9lNGV64pnT+6O8s g7U9zg4/JzFhnIO8EtTmid/2CZhfhXsyAB3ze0Ak+sHyY9ad9eZNwnQkJ2UzOsaKXYa/8t+ZvTAS btPANzI6CtZktmDemOgTWKfrwG4Z77GYcEk4VOzTFeQfsVSqJ1SyAIMGgqQUF+pGk22sT6h/6xmx zv6T41noCLQD/2wf31d6iEkF+z5HA86qxKIduLnahwesrHJnZoQHLtO/hg6W9q4tpmy8dchOt3vR 7NcdOx9P1A9EUI3iNDQCD4ppzR08rxLqrO1f7wdD8FtZuyLGgcRceKh/9iBM5MYtFphzbai+Y/NT +30bD8xPgfqjtCtbeuAjR0Sh8WeIy9gDKwc52WwOe7ljeiABuBxt0WpaYOMY9vxWP9J/IyaUWi54 4bH72orR/xMzYfnJjD0qjxak7K+1Ebo1ieyrkJFUoqTJsM2nNolYkf281GAO7pp+BkzZyvUxT6c7 bJlMXA7bUFfEtIEw+Osw0rZ1RASz2N0aFrVISS0O9xN/TFlWN9N5ukA4cn2rjzxCAVg+qTkacZGj rCP9graLLlQOkF+pC5atmThyzkSWPYf+2oYU84nB5w1RwUxI4otUS9wKKkMgjXtp7d5S/fKAFVfG ysAivsHGSG5R4bKNY5QwjJ/6968hMuVya9rih0BjYQPX9VC4yTuyUtsn7qW89ivRqrKy1qYT/xQ7 bY+dA/ciLOIdM2mEWvwZgfCynEcS+Pzqx0w/WR2HUSB1r7hKIgyrXjOC7egRl+cM9BOFaQmJBL2F kJcdNUzEO7hPsyDvlbZ6G8pdkEZDeQXn5MtHpFw/KMAmLXuBxBoPMTDD7XjsZTR171GOdb1mcll9 19pbVmD2rH4l0dKbw2J8qX6swvH7+/eF/l7k40+b4jZQMmHSkbbxrHTbTTSqHrVlk6eWZ0CuujCm 9PrZ3s983CBMJnA3GlCkvwK50OoQFFweh/2Hd5bBoXZUg+SshWddUSlOoq5nZlfeB0hcXfpYkOwt C/TfGMV56JMsRwITN/SkKO04Hgc6fQc6qkEpag40qHmTNgDSWOfHuskqDoVpHBGBPqAE+saW6FMp YmcxpAKVJKxfvvyIEUBAlomVPep1FH1wK0Q6punWKQasWvG0qdmdjmDh01QIff56cAN1sefxkwYH k51x7eB6p2FZ/DN6fSB2fYfP7Yg9HFTKcj8ef1Bym7/QJRHw5PbTw1A+RX8sNM4dbuzQFX1WsaXN J/F26uB4ePpD5ukYZ6C/Fenm0EsDQ4ztrXPvoGT1UzkkHNNGS8EGXQvW5SYsScQWcO2l4JI3V9lr ayfyEkpYTAY/goJCjCLUTpecHTO+LW5xQMPp93TqgereowbY0WIDoU1978EVVQlcZr2XjnsoyO8u Tj9ddSY/bj52JU/ncZVEX+pcvAqiuo8L4jeeM2zQc8hBW2zvvlUFYSSqrukjrKIcx26CC3t92CyU 3344G28F5g8PpzlcvW/zQevzj8wXNI+0XkSEDZp9db6eJ0bCv3oCDxdwv0CA9wIAYq9XYqvn64RM lvol0JsLKJNQ+10znu/ocWJpvhlWYvvn2tt4Nb+V4NIZGmOZ4p9dpD0L/wBawvlgvT5bDKjEFIP8 1OBK3j3ho7+ai9XZqauvpF+aIBvqrzPZ7wj/fiyKCZpWcstSDSvXfcRhBBRkI+o86RC7vs0SOSqd T5rhbnqyil3D/1goL5PMVEoW00401lLrCd+zkkejZqK0Al6+zkepngWwOyEQAlM19owEMIaNM2cL dwEfWOcPpfx4Nxzpp36wUaaF/yAz1VMl6a+ovf/lIeFeFk4IceDOA0PapHAUjnWnInce8cgOdr2B p134X8lSBSmziEVvJW9sW9FP3M9Xou8+TaWQgkT8RkhzP5gzLkRbfz/kxE1m6V8e8n77J7JHmnK8 T3XM4sxf+sdEpaE6oOSzIRDT1NL7d5KC4r6bI9icoLS6Ug9fJL8HMLvOwFtrj+K78q8mqb0ut1bY fTCEyh39fot4pOBGhSJgBXjXEnDKOXvzM08S0rBwFVZhHHbtXf5wHNuPnWYFNXwArkCBPZLkrB8G azj++KGft7tP7KD2c4asdVZuzSKiI0UCRThyqY68yeLdJ4I5raRtfygrShHo5hnhUuZ+vcK4mZig MN9d5f2ncdrtDmQWQWCcJXsWoVUbD73fz9KCFSv+bJSVWtvGCotvRZQJkGCXGX4GywfgzwJL7Ia8 hdL+E8NMKcQ0Xyjqe8sF45B80bSzv/nILgAZezqqVHjgL8XfTvWDugeSMEZtd+XYVNcQ2r4hh1fV rfqgBcK7Lqhqik31Fcv6plYuZwlSdS6QLmFbGJmrM3aeRuCSITKzKv8b2vrPeSeQRnn0NYvjwN30 WdBH96SMxryYnzbcNbwt2cwyb47TC1ABhh4VSr8+dSAi5IpcfVH0lirSnmJn7iqlDNXk6nvEsXxA WMiUtohOXx3BXSU/ZPIHO74Vu9Goo9wm9l7aCiAcXXzF0Ke8GthcuJ8vHve0eeAu0XqxqgpwXLi1 Bs7OfGoNoC36vJNAqzCLaPXl5CJSSWuOTWHKPsy617fPHbicLO1I6pdea9nntSSamFVfisjxI3MW DfLj0R3udqh6X7qPxEX0Tzzlt+XyU20zKZgt1cDXGqKFDTmpJzQA4ko22drmws26lRXIA91KuoFZ p+BZ7czB8HyiwOzzWrBGA0ReUAV27py85PBMPJlh+gFMcG03zPXrNqGch9z8tFh/1VAls62/6Ddy 8GfAkltZyl8q/d8MRiDM5R2RonoC67YJl4an18W+qwN71gXOA5o8XbCa+7iBuJz92/d7GpMkDIHJ j/fOmyetG9ZdKfNEfWtcGTZ1vz9G+5odQjEgYSVC3RErKMREr5K1kR1mUdZiyHiJncWlvIAum26C G3+Hlwq9bIyE1ECmS6ZIm1VeE2VgycYhQTADzIYxLBKT+KjJiMaB32C7+w5VqoeFlPKK/DXXuH// r44w51JR7mvybF594ZYYds2yqXdrItNspSz1uU5f8DQ39F83vW/JBmQ1zv/lcuAkZdv8Uji2OxLL obq1EFFvP3+STnuRi4JZjmoxVCIBnidcHN0hq6lNDdEbrv1BJ9HxN6ppWUJHRsydw4RZT3ZXpXj7 5M235BkgZUyU0XUqfv0mjBIx5dd0p6NHmkQ2xo+op1W7dJRzfcRw0+sZWEwFC6mwPc13v2alCppr yml4wNPJ4rT+lfKt7vZrKM3d4zPFLqxUTAnP2f3BSm+j2aItYzm+Vybw73ITBU1IaLS/zgJ5nIm2 rbIUyJHdfedhzJ46x+Xv3jcs5Nu+oXZ4I8Qy0Myoyh7G6gAvU5rA2WwB7cR7uG+4Ib/quG/oAc+b E341x8TpKcVUIq0bVEf+I9q3+pvJ7dCRHunigoZzeQUfmqePNfN0LKuEn1+MVb8wrYwrty/3fpRp kC64tuZlmzVkdePyIIX69uw4IDqrdAjvPNRMLB0pxG5nrjf5iIP7qC60L09XpQdOIKNcuTgPDRw6 uVNwVaaftCIzLTmvK1qcubxea2lec3W63wzyCJ8pHO3j61l2uUr98GyqP0IbjhMe6sUihs0YB1Mf HFCnS71UcLFrQqjYs91ZHbNNBZSYfWxxCChRHflqqR3ZEpLyN6LUHXB99z1S71vcsWuWy1osz932 RGY+k2K6NVBTflCNylerKecDr4tjkw81N8j/7oxzC3rNGivhkTIewJtyCZV7SRaeCJzODXfTIFGh z68mTx3f2tuhGA+k9UU1OYLLl/f1MSQLXzEiyd+ydFsc6yTAYRtXkvLjnwFh3yA0V9H7rLx/P8nC iunAKO593zELp4AKBBPKMY0saoxvpZtddejn+YC7dLQXLavFrIeS4OUXVnkpoQU1aUKHLaiiOZLp lt+0O3aie7aWtihUXFQnvZD4194rsZE/v2w7SdUyrYWelW7s0IJ8OychbrGT3SwvSAkcXWsSDwLw X13XM/qkwIzky2FoovpDQDBNbaLNFTeV/oTLoNp/EZoxCm5kkqfadB4uMDGvU28Ut0xXOz/3wLCu iFeSrlo+Drn5Yu7NZnVKYy4KOT21lSo+0+VuazH96fB3wq35PG9puYjeih8Gbj1iHPg/XUJhuOZt ehsJc/SAhN/Z0QK+kXYLDH/k5eEPyMEADNfTZmXMvuDLpbqHwU/jIDpikOYhghTtcbRvpDRDdRSS U4pC+9FXZ9ACizUPzH1lFGlQs0buk1jzRSYnp+wPWeNE635Zo9zXG2nuLXwYo6sWmufeHpJLBGC/ rS4pL3zLnffVbMQc25hG12sGq6Gpxw/LLxZNMCBg0JievUQ3TcQ5JK6n6a57jb7/WfHUtzUtvaYf Qh728Q639I0tOVxvPe1wtwtkoOBA+ouVDElxhqy9Tn/FhNSyBHnQIAfrLC1lxpp/2KYvK9halNgU +KPe69LEGjFGxNeIMGMcJXBOVsUW4Wo09WHQCqA5fMckLi91kZEy3r7WsEuVouiF+2NpnXl5gcZY yBgv/9EnfOJUEHcC/kSIcMKUR64NdyYVNmOgHthLVHPMhcIrk3XPPxzKDj4FKJY7mhi1pLqOUiGM 1/L/4XjdtmAM4cG+wClRetoPHCwV1PuobCAxSdyRCcsDrcbItMiLtnc5DK6B4hK1Xj9tGKjpME18 M1KTAH0xP70UpEDGPb14A/Ecldf3q6K7GX6vHn/aio25Fqs9+1mgmABQ1C1rg7D3mJ0ckNRiexdd KCG3JuJYpB0lJPhd9zVxyNVwriqGxVBudweNf8IrAHzscfMvDi+3A7xohLJJWK7HRNC/ndxHMvxq 8PZkrDQVovaQbf+EBZqBe1thSH6N2KbKKE8kABhNrFHltnt8vMhNcz/9RqQYRmmRLhayTs/Lakhx XIfXj6jJndmo83miUReEFVlxwxCsjNsckDkX4MbQVsfTBHMyPXU8F75pAeP2CLkA0bKlWbbVc4L5 YxYBLNQFbJM3jCfdKlYh01q9CKWjxtoQZeO3SzfHVUiITFxnc8fxj2kIUKryilqTXBSurXTjjXvk mACBBoko4KGanV7DTBqmS62mKPs/J2kIQJ/JbRSQyZTzV+DUsfB0uV0KW6ajQaQ6yoFCCoVIDqeD +r9E1WeKGKvrFjzy/Lz7BEo2ymbE0xgBOE7XYdKXe2nUY71+K5p/IkubjPq2fZiwceowlRDSdyUt cZbvpRZc/vaYm+hsw2YxrivJr3ez7Be/3+3OMEZeQs5GrSitXbJLXRtMUoKjU3fK2sE0mc3aVTc3 QrFi15AtNyL7Wy6lzMbROkYxwMl+UrJ0iPAfDMpsF6bYr/sV+SA3mYB+1MREVLo/XJDqbyYVT0Yc 6w7i5vG8uFjKi/hr1Jie5vp8UuPQdpawPoxWbLQz2pEpeG9Z/vlNtvAwq0FflZR9Hiy0R2PfjGMm uBfjOwNzByOi6kKXfgMxPTgMwCLncOjGng9DZYG98a1paYiI8bf/Z+KqpgMKGkYg0dpJzj/m0WCY rqTsZM0lRsXBpo1jaOQYAxfUIvFKYztuAA68gm0a/YrJIBqqDocTZJVkp3pZ4r7ZZ6AzeHoaZf7E 74SUIlp9ow5Rx0FJhLyodHgP0JlvJtsPeYx6b0W3dqPDj/RqHVBeW8QKqSJjCcgEAtyTWmNebl2f e6LlunmSYqm3moX0NqLP/wEeYBDghM1R3+PSNfFTmiaqjwogHcnXNMdM72B9nx+Y+oT+fDRHxax0 HCYv4vgTs807cZVf85JuQl+WatT7YYXP+KiqX90qDM57qrzwLtcOf/hRig5qnj9+ksKikNdITAmf i0SVFXQHC+/dJ9Uygh1acgIHUfGVIhTupF09LChEIy0bmwWRSY9swIe/wccFl9bZRfNpC4eF1XxZ DOEOY9NhlJANvfh3PnZL7qXRa2PozfDYHgrHUYk6MI0KsXaN03CNGkPEUxc80g9ytkpsAd+TzTD1 WfcYV2qUCkST49D6Wd0mMJ42fAakqB4+drDuhXzR+bHvGrm9fw3/ZBI5HGZzc5PGCOSqUWCuvG7T fuYHUMdFwwEtFoy0ySgH9gTfsaLll1ZKSqD78tdEAVTBXGJj1n+diirnUgKAFH2ubr3QP03dK0IJ xZ4LBQ9PLah94xYFHVN43uypBCJOBxKbY3m6kLLCtyJOW2YCt/tbu0YOzKKHGIIR8WcfaVzP7c1P FezRlWgn4ntbt3F3GVWZYqN6FhQmd+ym6BUYR4BiGMs+/0Rn7YnqbkZVe8IwvYSRmaEO9z8E9I1Z 7bnpJpCUXucDF4p+Ohqw155sf2eUrevX4rxBj6WkV260495kjKZSKNlH0wdPt9mdTA5H5WeU6V4f NxcjdbqP7C6+KqnHa2dGePxZ8Lyhd09Hj9YzfCvyzCHRlGX8ROGRHpxaE9x6Jf/RNJz+zYlzhbzs /LlDnpN9JFFTsAQeMF6MfY3F7RGiBPqebWwFR8CsMQ4W8XPIOXuaKYyylOYb++Drw4CK3Vv9LFzl +A/fk4eZOHQ9IhX+EHwGNm4GWWESQNg9Fc9yUpyj+xXbQDqttvFID3u4MWNV31VQ2brn98h5F6NE 1QsfY6Dzcjey9H1CXFLdllcrBnF6mEar9xYpEyRNXLsOsNTrckLqzP2dnj4ACRICh4bDxoPZzcNW xXsvW0W8rOJId0P0vUoVruR0GUjpGX6rFxD1S3WssAnqpQecSJ4HE9ZbrntAw7zXL6aDxePQmjS7 +S5YTXFS4nKMOiGj3n0hx/yo6Lre2tDh0S8R+b5mb9Wa4NMTuAtGA9hAttlu++H1VYQf1Pj9TC0J 4/zNyetpYD2mAGW7UCWjwVesT2Yu8VIzLRmU4bttf2kf3/VE0YwCXDS5oAHkH85ufacusLmu17Kj vN9gqSnhIZxHH1nbUup2fz0rzfgpN9P1p4oAkjK0/NSDw8bZOSIqetArZSAVpg/SktGqowyg+O94 Xd70Q8ASaC+hTa+M055K6w/oAHSk/Pxu2nvrvmkqQ+bLKAMKp484IGjHSNVD///69jkgI+4IFnwA nu6lGc1Bd9ESQz02JDsXIwVvm3mTtwIgmlm+xgASGaEE36LNHKijHNNeZjPYGS4ruUE836OFzz4Z tTWapLGklaz34QdaIFpfombdnV1rQEvllFqeJ6DVo/qvaS7WzKqWXyKfPF62Y4oeXYXQPPe6sXtC xDwvU+s9nroMCX6VfJXipzRmNYPEycByt+Zc4VlwG3RUyGJRFSXpYwPHm7GTV5nRVvbFpFdtqOtU WlxA15+gcXG1fndKEZdwq6n0zzqpjP0mSSmB/QJIVeMpLmF7NJo+Oe/xOLdpZXf1jI7lccmihQVE 1tpqKZuPZm3DojCoSc5nbQ1ka7MXmUIwVE/Hoz6SlyjuNvkUZm8GufiIGf+Nzp6hSmY1+2IkgGWa l0DbdT3Cgh/JtPLA01D8dQoxkb9Ztx4NH3c4+3vBZ0Wu7N34W/E0GaRjgVbie2D/Tpz9yNjlGBpQ ZZBA8yrD3smw2NrGLmuG+ETQHQcoCKDO/sM4AAiYNvQXEXN+uuZuru3Ndh/ppWDwh/1qOP1kfvgf QI1QSY4EjEPwgV9EJ59Q0P+RpiiDzxa5D3/SF4vXfJ9iuY1Mt3V19DMchnLnQ592OqOEp3s6Exr7 th/cnhytGnZArdqtl/GU26TrvSuHH6QQ1gY1w3RQQRS2fuNZUtJPV+ImLzvTeYMtQoLUrBk8EU9f 20UDRCnAruVNLpM0YqoqxO0uUPCCCYM1RmAfbGf4+foDDRE143uk8lYfQVSSlfTy1SOZTY6AyByY udyCsxlRRG/2aAYbe0F1LMP8Bo7t+81Lyad4mgf27kxzDb6O4MMFm8rJRSYW4Z0x6WoAwK5HCuwB XSgRbXzA7R/tjyH1seP6xH5asIXCu3OklsXNmycZYjlRqoL5sABGu7HVm2OLpgEhaHLAEx6wbfcB bn0bzkudXZVhswT8f4/rX/wSGPLiGux9nGJGdl3g3HocR9IRmFqwwo7zwREhVaXtyVBfQqFYWKUA 8KXjyH0sTYlpr5/rg7OBSjjUAe4GwKPB5489Flm5YbnTqLnhnDJZf2psbRvaYcM7upugJbs4Fvcz RxGyzuOF1WoFQLSTm54TQiduwY6awsD197ugIKWQiYt3jkY+UWh2mUUpYlGNTN9aQobtH76RZdjj klFnCvKyzEjDPzkukgEunqFTXPM2zMxPvcZ1LSzKGwwcSkLppjjfVeAQKu4zX2m397JudSPLKH6j VZMuz4dqqTcZFB3krSCsQ3kos90MeESuIAjO7wAdXO2Gyp9Whfmar6v6JI4gvS8ON5RTa6Niegmv I8+RzgWl957LmvGefGfrj6p5B2hEZ7SUNW0O09Z11sdHa/sCsEBUyCiXgUDwmqZe6mM/PvDR9AS9 yfNP8OseoF3PEoH5 `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block pBqd8SbxnErWrX3lyBBDaDLKX8hSp/j5Yr+Qm9jRb/9JUTybH1McKspWz+db0YzfLoM8Rsbks3xZ F0QO+ZZlvg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block H9nfu/oUf72/R62OBj/4D944lb73dgO7fFOuMJCE4aenI7iF3utXSTO4hpgrQ8McaV+063uC1I2p SowtO/PmhlxRipVo5KEq7Hhzbtvt5amDIBC05YVti4pxjbEI/kmWeW6ApomatkIzigzghecNWi3O dw5/lv3XsuSXKGnf8V0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block LHYKr83oHemqUyK1Wezwr1z3qiqaCVVbCTepzFi2rZrXgOFTcCRhqXcHptrNPAEIVNUU983e0J/f 0KmoDwapS9jLRSEt/t44AcYzVSy/ai/iXQJgng7HtLlp+4d5yiOHFpGB54L6O3dBpou3h7caNhhL jjFv+2NQ8/vJ/xJXwO5fh2Ph6YYguOVQ53PyR/4efc4uuMmB69VXQ320viKRtmBbQCmyLZzeWtFu D4qzTizu+7+B9LccVDGFdS5MPG9ajzsWHD/tFElptKJXuLi1qfJlX0wCtTtXoY+3nkHdj+d8GtPf YHFzKsVl3XUte66S5MbnjiWHmaZaMtS1k7u0qg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 4MafVQvjuuBxvIjR+OYUlKEesGBWmyoKTpW4+3dmDKYdKobe8ekpI4KwM+KYTh1JKxG3Qgsr94sv sXNAR2TjWeHLAvJhva65Oh3N+FSqhrH0zjkmu9XvgIV/UwkRDNwOx9c4++PMmrK6Sc3dNZpoycaC lN9AukRoCBpCWkU/kGY= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Oe9rX9bCQUY9pDwkxKbbIf2ys0cqImU27qEFK2Dw17YylEZy1DE0fAY/RnVb+EPxtWACfGlXlONl m+j1F3QtQOlCfFGG+seFfsBQSPHUmFsJmINuxeAGpMhxfKpsTFjDqKjDpQa8VcnDwKWm4aO3goL8 ohfQk4XoUdGZKXOs6aDCwCjQ3NSG6AcZNW0ORDZyS9Kio2rZOPAl2Iatk0VLalSOSKS8f5tT86ig hcckTERcoJMSnJHpKMG0Uf46p6lF1NxyM72QA47lZHQTdUAqzyv8wPWp/x+9NpDScFU+0BwCqNgR Wwy5LWtdGsu9PzUszKuMs6YlHHcqBdvP6pV04w== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008) `protect data_block ugPchIic85pVoazhFaH2TWuQjqsMIDhfmCLDBUOtUS/RF04DCSHl4KkxPTtW6P+RbyiD3T+m3kTR N0N334mL4z3weuQnltN6rjwv5421Of+ebjf9jNPWmR9lf0e4KC1P2a+RqcNXNDLyWLeUSh5xhG/Z 78Dc0xYUHiF3d+hrOZnBHDBSzBMBxH85jBmUl3hJ6N8TJlBFLvzDJLAwx9rMqd+/ukKUbS92XXmq GUfEtXOD/kOjfUAMdbSYK383ZTVeO8P00Ys+990ShfmBjW11X5zfC8a6pcCnYMWovhs5zhxlg5VY 5qaNHLAk3jG98jGzfgSX7h68H0TVRR7JEDFOWoBp6nHeaNm3GUeQnBHvRRf9iGTHwtNoBo20CT3s B+8CdJKTLLUzk6qAj2GsiBGHS8LnYKmNkY/fLp6AmB2/qs4DlNFJIF8WLDrSqDSxN7vLmxfW02dn 97TZdyIIRU0sSDWmckU00Bj4DR6lVWvrorzqz+TKptQht1fc7GrTmUsh2hItQeA59cOw1AOmZDS9 1wq0ZKLVSXAjdB+CY84byFDq/ggnql+ym9df++F4CndyzeHn/77aqPKlsW1vloWWAkuV+/oxdhDW p20TyTT2O/VPp3m+EzlmnnWV4xK70h3N6PHM98xVk6mnffhh/Vgh2FPYUMBhFoA1R5ZkVo2hBFx+ BdBPaixrD1Bh0/1sYSrIxRoyOp3yESYfh6j5q6cxlNTa1qH+ifL4xeUh7yFpIAKcpGKV/BHZ4BXZ dzcowFS0zr5D1j59GJ2fBtclaFagM874kSHoT7saPkMwJZzu0a9Suyo2oyHeDY5u0tqwoOjIxSPD LgfMjS5eI/7kq2LRK6vuUkw4NPeUXfLEpGv5FCJ6L5qj3kBW2g6KAhG87smejtyOyPsvsfynrIc2 3VnDVEHbU7JdT+65asCO43n+F2twwXTbRz3siKaGFW/pSUKMJST4WLbItR8/WK8o1ze8PIiuzlcV 2q4JbKB8FDK4mLtzmIeYo7UTwNP6U9iXbLmMvu0dzyoUw3NDGJK4KUCMCVvDKN1R/+YL7Uwr/kfr H2I7nTHDRk6JDcgnN9lfHUT2S8C2BMkKRraWkqRs0K6NTq153MMgQ0I68tioSH/TpTwOz9oXVKBC IPIOjB4kXex4kXwRz23kXOxBtWL2ufKqg40K9aFi7BK+LFkdT9TJGBCwlY11kGcbWle5fHFUxBgl D7qMX2r59mWmGBSSP9gWsTMEGB58WJb0FCVJzJGA6OZLDvK1GTVkE3XRxGSmgNPHSS7w3jMJyMM1 LUnr75CCm+QeHuKzLZmM4W96dN4nPXd6yqiYEO85iAqDcN94rfIuZjKzOQpcTx9Oi4DIbX9uESmY tjGl70Xxr/adCaR8ilSvqqc+b4MBKqY7ELJDs0L3vXhscTGf4aQPSq6GF+yybBqE/m0z770fLOgC kzFPyfhoCNMoGzjgznhNFl/K2SBBjlumjwB4VoL4kPAv9g27PQzII7LCyKyJowsuyed1QFyLx6e0 zPEPygamJ5b2aKJfHjhq6Imar4DfdI9b/lJ2m3mKH5VW2TviID8sew7r/S+Cqsd1khcH0dn+JSpQ Cz5CskuqoPSTdJzTOv3pTxDL59oUgopc8EhlWAJY+mQaF0YTUq6eOMJWIqiTRPuWQs6VbYgRaUWq gGyiyprJEh8tjGjzF1g0t47LQBCmfF+ET+Qos0n0Wh5P3AuYe2d26zA4VHkOum3I/l6rLBKqZWgw 80FOjGL5rFavkxULg1QQ4CE5oihzlPEto13KkUan3UDd4FbgJCBwxe8aBRFgid7TZjfFiKmhUFt5 VQdmXePim15/U9KY4mMIYrnEKT0toYoS7SwJCXalf9S/2xU0+tvNWpw1X6qO/7v3BrnHauRDb8p7 DXnByUOEvR5Iwn7KTkPdDsC19IFFE44KJQW/TLM47NkLTnUgjtpw8GJXRgECeGgmVvN4zDWAz4kH JoZvUApvZD/k60yS9lZdKVETDuGnJLMPWqaE9URGx1F68zV/t6gNNzi4Vbw84HrncqaVQ9wkyUgz NG85xmeRL3PM9bycBzo2/5tEUhya/xB50ZheKo/wFA+vGxItbWD3A/cZCrWTA58Qp5cdb0eH8meI wFkrjyP9iCxkcXPvTVMY8oL8o5pJxxGdMvGwC7jjkK1ms7Vqxk+flNpQwFOxc8Bhi0iZ0/TmPVEf F+ZGV5tPUjYRSTzxofFD0jffamlYZQpqwKkMAfWbYnog1yK+fbQm41jBZ/ovWhcEWoIbKWZIjFSA OD5IG/kjBWkEXyU9LTohftglq69r0maNKbr7EKYPsDpvo8izUbasMLapY/Ny14fG6BWgAYo5xI4s djD2qS4vNfqRKU4rAsx+aRpvVQxZ6OeKvHYxiqiIPhOi8yi5g6zUu2EdUUni0ErRMnKL38mmI4KK 4xPf2PcduRPfhljJVhFLQAL/Vx9rs8TI2ixHSpthP0bZl7TycX1Ef3z74wUQ6nP/jp9Yi9pNL4Es OrsoIJiJrNwmzskoRB+FpS0XmnGK+WXeWg8mUkqP5uDqsrTxbhy1nUF9+bxAHJTjfax7I9UPhkOO g0Ms31UeKJczoUQXY4xQ2756Cr+BoXCCgUE63OOGha4EZNIFVDjshALTXX/K1Zamfq3M4naQOWi7 h36LS6E/7kjsvKD0qig3B+bw4eYn9D7xp9W/b/xnQX1Y6b+KJI1mq3ewFW6FWhzfiushu/g1D3BH IVDnqB2RNE5KByrzrzTWfPXtAzqwVypuv0uPzMYjP/HUWBWWxaM0698XRYq6tEjyEZmrbmcmdddB F+978ctayhLeGND3gjJzMD9GVyWbsp22+eKzIrPfgf+zir8BuPgUT2EfbWNhBLNuDCTbpqX3h5p5 UQgkeDx9fuGyyfEwSY01Gj+b0y0ZfFaPQ8GsQKQ544ltOq5D2c2hxCm8+bT33Xox9Byh0dE54yji mtCKhyFgjWGN+nc8kZemzz58Qc+tFgq33sNTvW+u613NDE6weCWYbSHGw+zKAAKUT3bn5wnjKlNP Za0+LvGGrSLhqhB1E+mDbzQz9WPa7pk2U5Yx8hXeWw49WqeFimySWFNJyPEM3fxsATP6UzAn8oSB gaeOEqF9ZAokKdVC3hxFEdR4hES9AH5L8QlOcAwytA0XEPo7+VJ1dvQy+CUJFMSViL4UyQ/1d3w3 /JflFzwiR+Pqp+4cC7R1OcxV41N/Xis6AjZZ+L7AUqsfgANI6OaDHJs7hPXGw7n3rtuNAlK2NiwM bWvK56olPYG7yuoHmsKWkg4wJLoG/MjMFjZEijGpYHYAri6CzgPrNOGFw45dmw2Adhf7PPKe3wyy LOw0Ka9N83vjMWPcpVP+2ScLxhfRWLsSQwqGhh8AaitW2OiTx7ekbXijvvIy/TeTns9LEnf2mN7s IBe+4wzrMc5PmHPVAy16ju/wQ6j1XAbp9cyi6gY0S6FWOq1l8lKsx96z6qBwWwgxdynUzi7lARod UBJaDyt9i7nIhqjp79HJziAlaRo1Xrnt+LN/sCHD7PBmqF50pCSW6YzEuP164twgaiGlAi/yYTc3 kt2l9rDpHVSNaJM0oz662UavJO7BxnuoM2PoAzBcoBY78upERvNQBQFzOo9XtFM6zaeXPNJPSIJz H8F3j7maBdtYWMjy4sDalZ7Fyxlo/lRm19Ds8/86OjGDBNR9PMmPiZAwnLvtNG3yp5gmgsW1sskF +jyaMoW9SFHOaU0dQ9hPXG6sflnNACAOh4LqrSjDxOdDGXJIBbCV85aakvibPiTbvRihxfcymks/ F3Vg2mB0MLQN1C41ypwTN41Z7iy6mmfowNrVB6suL0B4C23X5uXmksOWaa7Fqhue8voYHNYz87AX 1CmUnsx+ESMgq+Cnk/6CljrQ65N4INHD44SXvqqsH7KGdCK/VJXrSrd2MBqWddVIeoLXCuqYwOxj ezDRKd9jCIrgi/Tp6uGj5vAaqWNO0i6KQ+V1odyjNq7xhDwfSyL15I44zNRkGVJd7ttEs2zo+e9M tTkR1igHWulM5TMUdbMdej0p4q9rY2Vpez9BWoTMI+NMTosN/VBa1uoXg3e1i5Mey6pH68hXSc/y OOl6NP0lAsF6r0vso9xG+KIJcJZ1ldonn048etdsDOsRodP/ZiitgPAjFW8b3r38t2L5uZfsEwWr WnyK9Yy27tLFMgyfeBmKMin/bqqg+xVK4GGjb8oravkTjBVW9VCYc8nzEU0RlL3Kpd4DNscR6Chn fBK2UambbZE0jsrc/gF32wOzEjsRYq2t/NxyOzmZ6TBogtMcqTuJUWvDPcmPB7KFI1xve5KpTnFH b+AGLQebcHUjlzNAfV1aH3VZWNbetP9Op++JhuKwV84xkXVR7HuIdr3CIedCHKzWW9k6bDKi27rn MpImtyw+Jhjrdjb6GpTy/V9Mt35CVz0ilaAlzYnQJBMH+HbaZ2u8yveI4vSTZwSZ51DlN6u2fdtZ OHLA4WhhHPzW93UgL+Z3Yn1ZfGH8L0XL0rG0Wmi5mZuQTP2nfGHnKvEpiUV4uhQnQoO4ovh+VRRa UdTp3aYvOwcLa1Tbfxs0zG8896q6sLndM++95zagL7jOyZnFmQddlKEtNZvqtBxvKiZzUa4mudH8 2QAR8ewUfAWLEQ3FDWqtbRklVLgvxrbFK8SrAIE3lwO5YHXnIYHasG7Q8kSregntWeOmW9T414pQ js7uEMYE6soIZDftkj7r2aw7chVXBS+0VcsvZ/buAIoIiNyiZISKmnQvXIqWI/07V/7ZcJb1Mul7 iyxId91udFo7+4FtchFIwNV+RHeV4jxN6vLH4C160myH5id0QWN9saHX31nAzxNCLbI/8NdaMApz Pe14SASWdOWHeESkoxp32P0cnYi2VaV9dE8aaiiuHcNyfSbIndQdMiAHZADN8h5t9ZH+FUd3QsyF Sqpl5mKnkQ4Iee+gH/GeM4GoWyqumkfLSfvgpjCP+glKrnG8oarvPatTNQyzZxLcT3qc3gw+2qD3 w8EFzIZpIIllJuwyHGtnzdAofwWQ2t2QhS2nw4dvDoLydqXqtl22O0UF8tdDfG0ePnfvBF1OJ6tX 27vnuoiD7/sNn1iXhX00lrc+/ZM5JU80RRA1t6eEcOzVORKNgDQJFnuujNJH7wLQ7EHTUmeR+sAt Cv1KJNSHlVz/cK7/iUC0r6axtv8mKAVntAgTy/SGFP6roiqTVFExrldW4nVtzASpqjulJ4OusT++ eOEove+a0qg2KM7bTk0Bn45YeIrsgjan3/mlE07UhfoZ4SSfMl7EtZvaRR3ipwx6e71+8ku0ngoS qy8nRgtaRqRY7Jk1nDpdNe2iqhTgF6b7cG3phYYw/NBlzKtuyfmjvBqZyBwCH9LpIGKRL75azkK3 lLHg6yhSIhU+EORJ2y1YtfqGUmiG9Niiw6+HG4pf6osSsJn2bE5IAMUdFnPsLXbLZGp7eSXJQyFq 8hpiZMpF1xQkxYpxz/wk5LDqfQjjU8223MNGUH4fNxNkw+ADIhqqCZqHIOIpsfQzG71AfZu814ak jBTWPgeR/JYYF+PVJCvoxDhcgNL8XkOo2SzCjPaxCZFctxOkd/vDMvfhEwUgLbji10FGbOWGlVBq NZCJSflITRjCxkEaeIs4knmuyTIB7itLSpYbJz2ASoRzfyhtxl7lRvRhoI3I8JWSjaE0gzCDLYgi RDsCb2RiJ8XohoAuLRZKRVerVZcZf3rUI+0/K6zcdFL0klSPqnlt5vcgh5NgguKaJ9GabPGAD2NP 9fbfs1buAvi4uv69L1MqWzQSAvacBFAa4P9AT8u+t+aH0rU9nbdivFCa4QBcrbu4dIurpEOTlz6v Q4y+hklWTfxSNJo3P03O2zVvqDbYdlUSMVa47POuEwZqhOYuMHlll8NMSrwLAgOBiQ0GMCj71pVW mThWwktWKUqfgfmCpBcf1vO3YgSc0eGbNhSvwHYOyVLBPc7ySaMgxTOBJYVsnEQHWtVqoSnTAk3G QvSI8/SSOhE95/e4PurKfyZRuJflbeXE//Tnmh5ucLit5o7PbNAx+7Vgzx7QWY2EmPlpS1vNTfXL E8YrX+xRsIaJTA8fEBWnr/2c6i8iEenn++STYpXoY5RK8zeq8W+hGwmkOPtbQzLKXWJlpFkYVR4o nSLEIJnCAjsqDoVa8M9WHzmMxduRz+5JHd+ulXyw6HuVbSfxGl7+1vmiwX98jOJV/B2rnUnZ1WzQ frG/pjNNX8cyOnWkREdG+pBC3KYfZH9J7OP2KLdC7ZPxSR9hYJYqhq0xq0pyolbbeIXSnahGLH2A zQklbExh0qDnU0yp1f5U2TmWZDcf3jcHCvmJAm+cSplprSIUCHpP9yfCr087fRyet37UlxQTirZ2 Cu275t1hYOJ0EpvJYJ1S6sdM1QsbzskwSDC8Y0xP98UWE6/+AMHdv3GnE6SvwNZMvTGJkn96ab2o 5znQmV8122xq0E6e+2wD/XdQve42BvedJmozWGevKv7/RLHlK2YbqQsVKlDxeFIBunkkGOBmRsbL aBqwLRvIuO95OqqPOiRjf3RRcpxxM7y2a/uM3IuxuvLPfmYxV99uAcrvlwJkoiAnFLTlQKD7L8v8 0aeXoVkGq8/cq0354bbX7VSOJvu4cu5VUhtCS1YI7frRP2oJmWAeQRekteggVCoDflkDUqzUsZLQ tS+fjwPiGPLI1b4K4HZvtGwp+EUT7UUzfFeEJNhEPPa+GT1sHRDq43kuHJUO2l6pG02DdQwejKvE BgHQyX4JsLUlFp54yHA03+7z/+1+hVbZf1gG19WdyGmqON33qKq4fecMxXgb08hJbkLI/bzfiPJo GIIUI4ZgP80hbq3wJt3KVfhyMfbQNTfFTs1DiS/ZtB2YMSgErGn+A8gpB2VHPyovp1MWHUhPfsGl Cicec2BTQreiNhgJSU3tuYBD8HFEOkNuG8HxwffyjMrTOQUDf5/DcRSh8/QZN9aRP7vqMB5+ouLB BM3Cm3zzlWfS/lNhRsCrewOzfzFINfPGZqgmtF/1UyksiLB0VrU1KzHhWCMK6qwQepPPMmH1Ww+H dhP/5e4gNAw7t33+ciyoMyKCb/1I3sCedU6yjgejvKIdLhu4OloBAgbaBVAYhb2QP5GixZZruar8 K5r644IqRnPKDjNB2MY1tUwguYv2cPh3zYwZvI+maiWwHhQAHwjXFwx1y/zRxF9+OnpAHpeqga7K cmvuqKPjBhbGo0Vk/Dw7A1CQ4CG6b6M1AdZYpimNvVrzA7NKArpavLkGw2GCxuoWS2GCBqcumTKP MVGztQTL4F7W5ufN9sjaCh1Lh6LHjWq3ufgoEP3DK6R2KPwPrRnfEsTQLbdQS9SGjcpVRNcpQfAV i3OBYmpj60typMrGJyAP9EqSaOwlG6sWtz/p1e7AG72uyH2OT5PMSlQ7z3WCFYKRc/eI7/svcCLw TV3v7TH8B/1z+usu9X3y5Ad4fnvZ1jaSCKRO6KEjdKoIKJRsV9UnmMm8XyrUZtRcQpdWogyhqTKZ 3hODX4nK2UKq0ZPcoq4unvTXSvUW31Esqd5c3IcGDTMPHGceQHYmNfhkha6dJvTce7iJ/Dx4eMzW k5DDQml26ol8E9GGKeVa/awQmyAqtlmpvtHU/sBtxfrCTFmD2TcUGW6FdwFXMTu1MPwHJCE+Uwe0 VOmcC+/Mgaron1eLzMWV8XyW0ACztshoHbJfD9d9JsU1cJbGyOYQXu5pydYlv0r7f6HmDVxM7O1S rCuOYx2DZtSqmHzS1d8qCYlF2TkW0CVBcb8FCABSIM6caQ2aR+2MnCP+f/2uXHkH5acFGclk0M3n xc2A7ebD6mzZEOYWWxJBDElzxDKstwuB0ok5v2gwisV8CeuWAs8bjHOs5An7XdyM5g/9hyxXZivj fr0OMVLnw6u/Q+8rJV8/MoRSJ6wjs2qI8Z5MJSh4pBnHrwZbv2MWl+AIAMlq94qF4weEhBVNaHGH CfVPrMuRFwHVRkRhdFZAcsjaQBs+s+E3oenDYAe7Ko4bHmAA1sKKYLiatMXxmmwXSSCz6FewD4PM EFO9Gv7SsiECezHUmJxNcolWOsuk0RE9MakoNlaBgzKEkiDTqa13GwLnNg9Ck+cLCcHgnzIO1Njk L4b7LBFITgmMMm5B6INns4IdMbmaNO6KziwlBDOx22CmDUoV38m699UmEYCaUoDauHrMWbFAX2Nh 99QDJ0gI/4echrXMMbmcWyrizwN+QOYXN7WcSBMBW3iyy3ttsbDzaeq9/oPU18zzPAM+D+zFmeR2 zdbBrzQa9sESX1LphCo2CrKvbqZOJ65K3Sd+BlGnzi2uADnDnEqjwGRXXAnPihzVAbwbYxSLMvk6 bz6SW+eG9w6sZkC8M6DnGvKjF+Qm5tm241A6vyreUHmwA24lFL2F4DQ/wcOaGIxI1V/cxiaxxG24 bhp4Q3ZDgkwS12sHr+j/380mxAtPIeOyNv5Jc15jyBWwkCJ+pKuzrwu2la3lwDcbZaIRB3QwG7Jf +b1aBgR3kCCQkyUMFk+7nJuGWWpI26G89k9mbt7RGBKNhowreUdEkunfV3Ce6DswgpB0DHe7dO+x tYunTbfkcJvJCaDIg7MmBnaK7vEHSDIQ3vk1/JqRqFQj88Qiw5BwFV10oPymHswGDs5Y6PIHtWvN 0OdG7RqnNFk0sFTQkgR5IsxR6CcQIL7TUw/dBEwMvmQ8tO+jtpxMwOPKu5I1RjaTOYHWhHWp5c7V u016PT3exfxVU6/P2PRvvG5ppHbkirnTGwfDZ+0Z1HnVvBLbIeYkU9VlfXZdMcm7gBcbme7Lo2Ie NpSu2PZffaAlMGWZjninpfmmeGrjGRquaDcN3kbZA+M0d4d4v6QtTLCCZDKC5n/KD0pphYQ1yEwT 0e8gU+Q2n+LvWiAji6Ij6kRFmwkk/Ym2MuKGSakMztcBzZdTqCc22uHIwNPqU9lNGV64pnT+6O8s g7U9zg4/JzFhnIO8EtTmid/2CZhfhXsyAB3ze0Ak+sHyY9ad9eZNwnQkJ2UzOsaKXYa/8t+ZvTAS btPANzI6CtZktmDemOgTWKfrwG4Z77GYcEk4VOzTFeQfsVSqJ1SyAIMGgqQUF+pGk22sT6h/6xmx zv6T41noCLQD/2wf31d6iEkF+z5HA86qxKIduLnahwesrHJnZoQHLtO/hg6W9q4tpmy8dchOt3vR 7NcdOx9P1A9EUI3iNDQCD4ppzR08rxLqrO1f7wdD8FtZuyLGgcRceKh/9iBM5MYtFphzbai+Y/NT +30bD8xPgfqjtCtbeuAjR0Sh8WeIy9gDKwc52WwOe7ljeiABuBxt0WpaYOMY9vxWP9J/IyaUWi54 4bH72orR/xMzYfnJjD0qjxak7K+1Ebo1ieyrkJFUoqTJsM2nNolYkf281GAO7pp+BkzZyvUxT6c7 bJlMXA7bUFfEtIEw+Osw0rZ1RASz2N0aFrVISS0O9xN/TFlWN9N5ukA4cn2rjzxCAVg+qTkacZGj rCP9graLLlQOkF+pC5atmThyzkSWPYf+2oYU84nB5w1RwUxI4otUS9wKKkMgjXtp7d5S/fKAFVfG ysAivsHGSG5R4bKNY5QwjJ/6968hMuVya9rih0BjYQPX9VC4yTuyUtsn7qW89ivRqrKy1qYT/xQ7 bY+dA/ciLOIdM2mEWvwZgfCynEcS+Pzqx0w/WR2HUSB1r7hKIgyrXjOC7egRl+cM9BOFaQmJBL2F kJcdNUzEO7hPsyDvlbZ6G8pdkEZDeQXn5MtHpFw/KMAmLXuBxBoPMTDD7XjsZTR171GOdb1mcll9 19pbVmD2rH4l0dKbw2J8qX6swvH7+/eF/l7k40+b4jZQMmHSkbbxrHTbTTSqHrVlk6eWZ0CuujCm 9PrZ3s983CBMJnA3GlCkvwK50OoQFFweh/2Hd5bBoXZUg+SshWddUSlOoq5nZlfeB0hcXfpYkOwt C/TfGMV56JMsRwITN/SkKO04Hgc6fQc6qkEpag40qHmTNgDSWOfHuskqDoVpHBGBPqAE+saW6FMp YmcxpAKVJKxfvvyIEUBAlomVPep1FH1wK0Q6punWKQasWvG0qdmdjmDh01QIff56cAN1sefxkwYH k51x7eB6p2FZ/DN6fSB2fYfP7Yg9HFTKcj8ef1Bym7/QJRHw5PbTw1A+RX8sNM4dbuzQFX1WsaXN J/F26uB4ePpD5ukYZ6C/Fenm0EsDQ4ztrXPvoGT1UzkkHNNGS8EGXQvW5SYsScQWcO2l4JI3V9lr ayfyEkpYTAY/goJCjCLUTpecHTO+LW5xQMPp93TqgereowbY0WIDoU1978EVVQlcZr2XjnsoyO8u Tj9ddSY/bj52JU/ncZVEX+pcvAqiuo8L4jeeM2zQc8hBW2zvvlUFYSSqrukjrKIcx26CC3t92CyU 3344G28F5g8PpzlcvW/zQevzj8wXNI+0XkSEDZp9db6eJ0bCv3oCDxdwv0CA9wIAYq9XYqvn64RM lvol0JsLKJNQ+10znu/ocWJpvhlWYvvn2tt4Nb+V4NIZGmOZ4p9dpD0L/wBawvlgvT5bDKjEFIP8 1OBK3j3ho7+ai9XZqauvpF+aIBvqrzPZ7wj/fiyKCZpWcstSDSvXfcRhBBRkI+o86RC7vs0SOSqd T5rhbnqyil3D/1goL5PMVEoW00401lLrCd+zkkejZqK0Al6+zkepngWwOyEQAlM19owEMIaNM2cL dwEfWOcPpfx4Nxzpp36wUaaF/yAz1VMl6a+ovf/lIeFeFk4IceDOA0PapHAUjnWnInce8cgOdr2B p134X8lSBSmziEVvJW9sW9FP3M9Xou8+TaWQgkT8RkhzP5gzLkRbfz/kxE1m6V8e8n77J7JHmnK8 T3XM4sxf+sdEpaE6oOSzIRDT1NL7d5KC4r6bI9icoLS6Ug9fJL8HMLvOwFtrj+K78q8mqb0ut1bY fTCEyh39fot4pOBGhSJgBXjXEnDKOXvzM08S0rBwFVZhHHbtXf5wHNuPnWYFNXwArkCBPZLkrB8G azj++KGft7tP7KD2c4asdVZuzSKiI0UCRThyqY68yeLdJ4I5raRtfygrShHo5hnhUuZ+vcK4mZig MN9d5f2ncdrtDmQWQWCcJXsWoVUbD73fz9KCFSv+bJSVWtvGCotvRZQJkGCXGX4GywfgzwJL7Ia8 hdL+E8NMKcQ0Xyjqe8sF45B80bSzv/nILgAZezqqVHjgL8XfTvWDugeSMEZtd+XYVNcQ2r4hh1fV rfqgBcK7Lqhqik31Fcv6plYuZwlSdS6QLmFbGJmrM3aeRuCSITKzKv8b2vrPeSeQRnn0NYvjwN30 WdBH96SMxryYnzbcNbwt2cwyb47TC1ABhh4VSr8+dSAi5IpcfVH0lirSnmJn7iqlDNXk6nvEsXxA WMiUtohOXx3BXSU/ZPIHO74Vu9Goo9wm9l7aCiAcXXzF0Ke8GthcuJ8vHve0eeAu0XqxqgpwXLi1 Bs7OfGoNoC36vJNAqzCLaPXl5CJSSWuOTWHKPsy617fPHbicLO1I6pdea9nntSSamFVfisjxI3MW DfLj0R3udqh6X7qPxEX0Tzzlt+XyU20zKZgt1cDXGqKFDTmpJzQA4ko22drmws26lRXIA91KuoFZ p+BZ7czB8HyiwOzzWrBGA0ReUAV27py85PBMPJlh+gFMcG03zPXrNqGch9z8tFh/1VAls62/6Ddy 8GfAkltZyl8q/d8MRiDM5R2RonoC67YJl4an18W+qwN71gXOA5o8XbCa+7iBuJz92/d7GpMkDIHJ j/fOmyetG9ZdKfNEfWtcGTZ1vz9G+5odQjEgYSVC3RErKMREr5K1kR1mUdZiyHiJncWlvIAum26C G3+Hlwq9bIyE1ECmS6ZIm1VeE2VgycYhQTADzIYxLBKT+KjJiMaB32C7+w5VqoeFlPKK/DXXuH// r44w51JR7mvybF594ZYYds2yqXdrItNspSz1uU5f8DQ39F83vW/JBmQ1zv/lcuAkZdv8Uji2OxLL obq1EFFvP3+STnuRi4JZjmoxVCIBnidcHN0hq6lNDdEbrv1BJ9HxN6ppWUJHRsydw4RZT3ZXpXj7 5M235BkgZUyU0XUqfv0mjBIx5dd0p6NHmkQ2xo+op1W7dJRzfcRw0+sZWEwFC6mwPc13v2alCppr yml4wNPJ4rT+lfKt7vZrKM3d4zPFLqxUTAnP2f3BSm+j2aItYzm+Vybw73ITBU1IaLS/zgJ5nIm2 rbIUyJHdfedhzJ46x+Xv3jcs5Nu+oXZ4I8Qy0Myoyh7G6gAvU5rA2WwB7cR7uG+4Ib/quG/oAc+b E341x8TpKcVUIq0bVEf+I9q3+pvJ7dCRHunigoZzeQUfmqePNfN0LKuEn1+MVb8wrYwrty/3fpRp kC64tuZlmzVkdePyIIX69uw4IDqrdAjvPNRMLB0pxG5nrjf5iIP7qC60L09XpQdOIKNcuTgPDRw6 uVNwVaaftCIzLTmvK1qcubxea2lec3W63wzyCJ8pHO3j61l2uUr98GyqP0IbjhMe6sUihs0YB1Mf HFCnS71UcLFrQqjYs91ZHbNNBZSYfWxxCChRHflqqR3ZEpLyN6LUHXB99z1S71vcsWuWy1osz932 RGY+k2K6NVBTflCNylerKecDr4tjkw81N8j/7oxzC3rNGivhkTIewJtyCZV7SRaeCJzODXfTIFGh z68mTx3f2tuhGA+k9UU1OYLLl/f1MSQLXzEiyd+ydFsc6yTAYRtXkvLjnwFh3yA0V9H7rLx/P8nC iunAKO593zELp4AKBBPKMY0saoxvpZtddejn+YC7dLQXLavFrIeS4OUXVnkpoQU1aUKHLaiiOZLp lt+0O3aie7aWtihUXFQnvZD4194rsZE/v2w7SdUyrYWelW7s0IJ8OychbrGT3SwvSAkcXWsSDwLw X13XM/qkwIzky2FoovpDQDBNbaLNFTeV/oTLoNp/EZoxCm5kkqfadB4uMDGvU28Ut0xXOz/3wLCu iFeSrlo+Drn5Yu7NZnVKYy4KOT21lSo+0+VuazH96fB3wq35PG9puYjeih8Gbj1iHPg/XUJhuOZt ehsJc/SAhN/Z0QK+kXYLDH/k5eEPyMEADNfTZmXMvuDLpbqHwU/jIDpikOYhghTtcbRvpDRDdRSS U4pC+9FXZ9ACizUPzH1lFGlQs0buk1jzRSYnp+wPWeNE635Zo9zXG2nuLXwYo6sWmufeHpJLBGC/ rS4pL3zLnffVbMQc25hG12sGq6Gpxw/LLxZNMCBg0JievUQ3TcQ5JK6n6a57jb7/WfHUtzUtvaYf Qh728Q639I0tOVxvPe1wtwtkoOBA+ouVDElxhqy9Tn/FhNSyBHnQIAfrLC1lxpp/2KYvK9halNgU +KPe69LEGjFGxNeIMGMcJXBOVsUW4Wo09WHQCqA5fMckLi91kZEy3r7WsEuVouiF+2NpnXl5gcZY yBgv/9EnfOJUEHcC/kSIcMKUR64NdyYVNmOgHthLVHPMhcIrk3XPPxzKDj4FKJY7mhi1pLqOUiGM 1/L/4XjdtmAM4cG+wClRetoPHCwV1PuobCAxSdyRCcsDrcbItMiLtnc5DK6B4hK1Xj9tGKjpME18 M1KTAH0xP70UpEDGPb14A/Ecldf3q6K7GX6vHn/aio25Fqs9+1mgmABQ1C1rg7D3mJ0ckNRiexdd KCG3JuJYpB0lJPhd9zVxyNVwriqGxVBudweNf8IrAHzscfMvDi+3A7xohLJJWK7HRNC/ndxHMvxq 8PZkrDQVovaQbf+EBZqBe1thSH6N2KbKKE8kABhNrFHltnt8vMhNcz/9RqQYRmmRLhayTs/Lakhx XIfXj6jJndmo83miUReEFVlxwxCsjNsckDkX4MbQVsfTBHMyPXU8F75pAeP2CLkA0bKlWbbVc4L5 YxYBLNQFbJM3jCfdKlYh01q9CKWjxtoQZeO3SzfHVUiITFxnc8fxj2kIUKryilqTXBSurXTjjXvk mACBBoko4KGanV7DTBqmS62mKPs/J2kIQJ/JbRSQyZTzV+DUsfB0uV0KW6ajQaQ6yoFCCoVIDqeD +r9E1WeKGKvrFjzy/Lz7BEo2ymbE0xgBOE7XYdKXe2nUY71+K5p/IkubjPq2fZiwceowlRDSdyUt cZbvpRZc/vaYm+hsw2YxrivJr3ez7Be/3+3OMEZeQs5GrSitXbJLXRtMUoKjU3fK2sE0mc3aVTc3 QrFi15AtNyL7Wy6lzMbROkYxwMl+UrJ0iPAfDMpsF6bYr/sV+SA3mYB+1MREVLo/XJDqbyYVT0Yc 6w7i5vG8uFjKi/hr1Jie5vp8UuPQdpawPoxWbLQz2pEpeG9Z/vlNtvAwq0FflZR9Hiy0R2PfjGMm uBfjOwNzByOi6kKXfgMxPTgMwCLncOjGng9DZYG98a1paYiI8bf/Z+KqpgMKGkYg0dpJzj/m0WCY rqTsZM0lRsXBpo1jaOQYAxfUIvFKYztuAA68gm0a/YrJIBqqDocTZJVkp3pZ4r7ZZ6AzeHoaZf7E 74SUIlp9ow5Rx0FJhLyodHgP0JlvJtsPeYx6b0W3dqPDj/RqHVBeW8QKqSJjCcgEAtyTWmNebl2f e6LlunmSYqm3moX0NqLP/wEeYBDghM1R3+PSNfFTmiaqjwogHcnXNMdM72B9nx+Y+oT+fDRHxax0 HCYv4vgTs807cZVf85JuQl+WatT7YYXP+KiqX90qDM57qrzwLtcOf/hRig5qnj9+ksKikNdITAmf i0SVFXQHC+/dJ9Uygh1acgIHUfGVIhTupF09LChEIy0bmwWRSY9swIe/wccFl9bZRfNpC4eF1XxZ DOEOY9NhlJANvfh3PnZL7qXRa2PozfDYHgrHUYk6MI0KsXaN03CNGkPEUxc80g9ytkpsAd+TzTD1 WfcYV2qUCkST49D6Wd0mMJ42fAakqB4+drDuhXzR+bHvGrm9fw3/ZBI5HGZzc5PGCOSqUWCuvG7T fuYHUMdFwwEtFoy0ySgH9gTfsaLll1ZKSqD78tdEAVTBXGJj1n+diirnUgKAFH2ubr3QP03dK0IJ xZ4LBQ9PLah94xYFHVN43uypBCJOBxKbY3m6kLLCtyJOW2YCt/tbu0YOzKKHGIIR8WcfaVzP7c1P FezRlWgn4ntbt3F3GVWZYqN6FhQmd+ym6BUYR4BiGMs+/0Rn7YnqbkZVe8IwvYSRmaEO9z8E9I1Z 7bnpJpCUXucDF4p+Ohqw155sf2eUrevX4rxBj6WkV260495kjKZSKNlH0wdPt9mdTA5H5WeU6V4f NxcjdbqP7C6+KqnHa2dGePxZ8Lyhd09Hj9YzfCvyzCHRlGX8ROGRHpxaE9x6Jf/RNJz+zYlzhbzs /LlDnpN9JFFTsAQeMF6MfY3F7RGiBPqebWwFR8CsMQ4W8XPIOXuaKYyylOYb++Drw4CK3Vv9LFzl +A/fk4eZOHQ9IhX+EHwGNm4GWWESQNg9Fc9yUpyj+xXbQDqttvFID3u4MWNV31VQ2brn98h5F6NE 1QsfY6Dzcjey9H1CXFLdllcrBnF6mEar9xYpEyRNXLsOsNTrckLqzP2dnj4ACRICh4bDxoPZzcNW xXsvW0W8rOJId0P0vUoVruR0GUjpGX6rFxD1S3WssAnqpQecSJ4HE9ZbrntAw7zXL6aDxePQmjS7 +S5YTXFS4nKMOiGj3n0hx/yo6Lre2tDh0S8R+b5mb9Wa4NMTuAtGA9hAttlu++H1VYQf1Pj9TC0J 4/zNyetpYD2mAGW7UCWjwVesT2Yu8VIzLRmU4bttf2kf3/VE0YwCXDS5oAHkH85ufacusLmu17Kj vN9gqSnhIZxHH1nbUup2fz0rzfgpN9P1p4oAkjK0/NSDw8bZOSIqetArZSAVpg/SktGqowyg+O94 Xd70Q8ASaC+hTa+M055K6w/oAHSk/Pxu2nvrvmkqQ+bLKAMKp484IGjHSNVD///69jkgI+4IFnwA nu6lGc1Bd9ESQz02JDsXIwVvm3mTtwIgmlm+xgASGaEE36LNHKijHNNeZjPYGS4ruUE836OFzz4Z tTWapLGklaz34QdaIFpfombdnV1rQEvllFqeJ6DVo/qvaS7WzKqWXyKfPF62Y4oeXYXQPPe6sXtC xDwvU+s9nroMCX6VfJXipzRmNYPEycByt+Zc4VlwG3RUyGJRFSXpYwPHm7GTV5nRVvbFpFdtqOtU WlxA15+gcXG1fndKEZdwq6n0zzqpjP0mSSmB/QJIVeMpLmF7NJo+Oe/xOLdpZXf1jI7lccmihQVE 1tpqKZuPZm3DojCoSc5nbQ1ka7MXmUIwVE/Hoz6SlyjuNvkUZm8GufiIGf+Nzp6hSmY1+2IkgGWa l0DbdT3Cgh/JtPLA01D8dQoxkb9Ztx4NH3c4+3vBZ0Wu7N34W/E0GaRjgVbie2D/Tpz9yNjlGBpQ ZZBA8yrD3smw2NrGLmuG+ETQHQcoCKDO/sM4AAiYNvQXEXN+uuZuru3Ndh/ppWDwh/1qOP1kfvgf QI1QSY4EjEPwgV9EJ59Q0P+RpiiDzxa5D3/SF4vXfJ9iuY1Mt3V19DMchnLnQ592OqOEp3s6Exr7 th/cnhytGnZArdqtl/GU26TrvSuHH6QQ1gY1w3RQQRS2fuNZUtJPV+ImLzvTeYMtQoLUrBk8EU9f 20UDRCnAruVNLpM0YqoqxO0uUPCCCYM1RmAfbGf4+foDDRE143uk8lYfQVSSlfTy1SOZTY6AyByY udyCsxlRRG/2aAYbe0F1LMP8Bo7t+81Lyad4mgf27kxzDb6O4MMFm8rJRSYW4Z0x6WoAwK5HCuwB XSgRbXzA7R/tjyH1seP6xH5asIXCu3OklsXNmycZYjlRqoL5sABGu7HVm2OLpgEhaHLAEx6wbfcB bn0bzkudXZVhswT8f4/rX/wSGPLiGux9nGJGdl3g3HocR9IRmFqwwo7zwREhVaXtyVBfQqFYWKUA 8KXjyH0sTYlpr5/rg7OBSjjUAe4GwKPB5489Flm5YbnTqLnhnDJZf2psbRvaYcM7upugJbs4Fvcz RxGyzuOF1WoFQLSTm54TQiduwY6awsD197ugIKWQiYt3jkY+UWh2mUUpYlGNTN9aQobtH76RZdjj klFnCvKyzEjDPzkukgEunqFTXPM2zMxPvcZ1LSzKGwwcSkLppjjfVeAQKu4zX2m397JudSPLKH6j VZMuz4dqqTcZFB3krSCsQ3kos90MeESuIAjO7wAdXO2Gyp9Whfmar6v6JI4gvS8ON5RTa6Niegmv I8+RzgWl957LmvGefGfrj6p5B2hEZ7SUNW0O09Z11sdHa/sCsEBUyCiXgUDwmqZe6mM/PvDR9AS9 yfNP8OseoF3PEoH5 `protect end_protected
component update is port ( busy : out std_logic; -- busy data_out : out std_logic_vector(28 downto 0); -- data_out param : in std_logic_vector(2 downto 0) := (others => 'X'); -- param read_param : in std_logic := 'X'; -- read_param reconfig : in std_logic := 'X'; -- reconfig reset_timer : in std_logic := 'X'; -- reset_timer read_source : in std_logic_vector(1 downto 0) := (others => 'X'); -- read_source clock : in std_logic := 'X'; -- clk reset : in std_logic := 'X' -- reset ); end component update; u0 : component update port map ( busy => CONNECTED_TO_busy, -- busy.busy data_out => CONNECTED_TO_data_out, -- data_out.data_out param => CONNECTED_TO_param, -- param.param read_param => CONNECTED_TO_read_param, -- read_param.read_param reconfig => CONNECTED_TO_reconfig, -- reconfig.reconfig reset_timer => CONNECTED_TO_reset_timer, -- reset_timer.reset_timer read_source => CONNECTED_TO_read_source, -- read_source.read_source clock => CONNECTED_TO_clock, -- clock.clk reset => CONNECTED_TO_reset -- reset.reset );
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3 -- IP Revision: 5 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY blk_mem_gen_v8_3_5; USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5; ENTITY win IS PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); END win; ARCHITECTURE win_arch OF win IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF win_arch: ARCHITECTURE IS "yes"; COMPONENT blk_mem_gen_v8_3_5 IS GENERIC ( C_FAMILY : STRING; C_XDEVICEFAMILY : STRING; C_ELABORATION_DIR : STRING; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_AXI_SLAVE_TYPE : INTEGER; C_USE_BRAM_BLOCK : INTEGER; C_ENABLE_32BIT_ADDRESS : INTEGER; C_CTRL_ECC_ALGO : STRING; C_HAS_AXI_ID : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_MEM_TYPE : INTEGER; C_BYTE_SIZE : INTEGER; C_ALGORITHM : INTEGER; C_PRIM_TYPE : INTEGER; C_LOAD_INIT_FILE : INTEGER; C_INIT_FILE_NAME : STRING; C_INIT_FILE : STRING; C_USE_DEFAULT_DATA : INTEGER; C_DEFAULT_DATA : STRING; C_HAS_RSTA : INTEGER; C_RST_PRIORITY_A : STRING; C_RSTRAM_A : INTEGER; C_INITA_VAL : STRING; C_HAS_ENA : INTEGER; C_HAS_REGCEA : INTEGER; C_USE_BYTE_WEA : INTEGER; C_WEA_WIDTH : INTEGER; C_WRITE_MODE_A : STRING; C_WRITE_WIDTH_A : INTEGER; C_READ_WIDTH_A : INTEGER; C_WRITE_DEPTH_A : INTEGER; C_READ_DEPTH_A : INTEGER; C_ADDRA_WIDTH : INTEGER; C_HAS_RSTB : INTEGER; C_RST_PRIORITY_B : STRING; C_RSTRAM_B : INTEGER; C_INITB_VAL : STRING; C_HAS_ENB : INTEGER; C_HAS_REGCEB : INTEGER; C_USE_BYTE_WEB : INTEGER; C_WEB_WIDTH : INTEGER; C_WRITE_MODE_B : STRING; C_WRITE_WIDTH_B : INTEGER; C_READ_WIDTH_B : INTEGER; C_WRITE_DEPTH_B : INTEGER; C_READ_DEPTH_B : INTEGER; C_ADDRB_WIDTH : INTEGER; C_HAS_MEM_OUTPUT_REGS_A : INTEGER; C_HAS_MEM_OUTPUT_REGS_B : INTEGER; C_HAS_MUX_OUTPUT_REGS_A : INTEGER; C_HAS_MUX_OUTPUT_REGS_B : INTEGER; C_MUX_PIPELINE_STAGES : INTEGER; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER; C_USE_SOFTECC : INTEGER; C_USE_ECC : INTEGER; C_EN_ECC_PIPE : INTEGER; C_HAS_INJECTERR : INTEGER; C_SIM_COLLISION_CHECK : STRING; C_COMMON_CLK : INTEGER; C_DISABLE_WARN_BHV_COLL : INTEGER; C_EN_SLEEP_PIN : INTEGER; C_USE_URAM : INTEGER; C_EN_RDADDRA_CHG : INTEGER; C_EN_RDADDRB_CHG : INTEGER; C_EN_DEEPSLEEP_PIN : INTEGER; C_EN_SHUTDOWN_PIN : INTEGER; C_EN_SAFETY_CKT : INTEGER; C_DISABLE_WARN_BHV_RANGE : INTEGER; C_COUNT_36K_BRAM : STRING; C_COUNT_18K_BRAM : STRING; C_EST_POWER_SUMMARY : STRING ); PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; ena : IN STD_LOGIC; regcea : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); clkb : IN STD_LOGIC; rstb : IN STD_LOGIC; enb : IN STD_LOGIC; regceb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); injectsbiterr : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; eccpipece : IN STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); sleep : IN STD_LOGIC; deepsleep : IN STD_LOGIC; shutdown : IN STD_LOGIC; rsta_busy : OUT STD_LOGIC; rstb_busy : OUT STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_injectsbiterr : IN STD_LOGIC; s_axi_injectdbiterr : IN STD_LOGIC; s_axi_sbiterr : OUT STD_LOGIC; s_axi_dbiterr : OUT STD_LOGIC; s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0) ); END COMPONENT blk_mem_gen_v8_3_5; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF win_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF win_arch : ARCHITECTURE IS "win,blk_mem_gen_v8_3_5,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF win_arch: ARCHITECTURE IS "win,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=win.mif,C_INIT_" & "FILE=win.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=15120,C_READ_DEPTH_A=15120,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=15120,C_R" & "EAD_DEPTH_B=15120,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RAN" & "GE=0,C_COUNT_36K_BRAM=5,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 6.227751 mW}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; BEGIN U0 : blk_mem_gen_v8_3_5 GENERIC MAP ( C_FAMILY => "artix7", C_XDEVICEFAMILY => "artix7", C_ELABORATION_DIR => "./", C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_AXI_SLAVE_TYPE => 0, C_USE_BRAM_BLOCK => 0, C_ENABLE_32BIT_ADDRESS => 0, C_CTRL_ECC_ALGO => "NONE", C_HAS_AXI_ID => 0, C_AXI_ID_WIDTH => 4, C_MEM_TYPE => 0, C_BYTE_SIZE => 9, C_ALGORITHM => 1, C_PRIM_TYPE => 1, C_LOAD_INIT_FILE => 1, C_INIT_FILE_NAME => "win.mif", C_INIT_FILE => "win.mem", C_USE_DEFAULT_DATA => 0, C_DEFAULT_DATA => "0", C_HAS_RSTA => 0, C_RST_PRIORITY_A => "CE", C_RSTRAM_A => 0, C_INITA_VAL => "0", C_HAS_ENA => 0, C_HAS_REGCEA => 0, C_USE_BYTE_WEA => 0, C_WEA_WIDTH => 1, C_WRITE_MODE_A => "WRITE_FIRST", C_WRITE_WIDTH_A => 12, C_READ_WIDTH_A => 12, C_WRITE_DEPTH_A => 15120, C_READ_DEPTH_A => 15120, C_ADDRA_WIDTH => 14, C_HAS_RSTB => 0, C_RST_PRIORITY_B => "CE", C_RSTRAM_B => 0, C_INITB_VAL => "0", C_HAS_ENB => 0, C_HAS_REGCEB => 0, C_USE_BYTE_WEB => 0, C_WEB_WIDTH => 1, C_WRITE_MODE_B => "WRITE_FIRST", C_WRITE_WIDTH_B => 12, C_READ_WIDTH_B => 12, C_WRITE_DEPTH_B => 15120, C_READ_DEPTH_B => 15120, C_ADDRB_WIDTH => 14, C_HAS_MEM_OUTPUT_REGS_A => 1, C_HAS_MEM_OUTPUT_REGS_B => 0, C_HAS_MUX_OUTPUT_REGS_A => 0, C_HAS_MUX_OUTPUT_REGS_B => 0, C_MUX_PIPELINE_STAGES => 0, C_HAS_SOFTECC_INPUT_REGS_A => 0, C_HAS_SOFTECC_OUTPUT_REGS_B => 0, C_USE_SOFTECC => 0, C_USE_ECC => 0, C_EN_ECC_PIPE => 0, C_HAS_INJECTERR => 0, C_SIM_COLLISION_CHECK => "ALL", C_COMMON_CLK => 0, C_DISABLE_WARN_BHV_COLL => 0, C_EN_SLEEP_PIN => 0, C_USE_URAM => 0, C_EN_RDADDRA_CHG => 0, C_EN_RDADDRB_CHG => 0, C_EN_DEEPSLEEP_PIN => 0, C_EN_SHUTDOWN_PIN => 0, C_EN_SAFETY_CKT => 0, C_DISABLE_WARN_BHV_RANGE => 0, C_COUNT_36K_BRAM => "5", C_COUNT_18K_BRAM => "1", C_EST_POWER_SUMMARY => "Estimated Power for IP : 6.227751 mW" ) PORT MAP ( clka => clka, rsta => '0', ena => '0', regcea => '0', wea => wea, addra => addra, dina => dina, douta => douta, clkb => '0', rstb => '0', enb => '0', regceb => '0', web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)), dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)), injectsbiterr => '0', injectdbiterr => '0', eccpipece => '0', sleep => '0', deepsleep => '0', shutdown => '0', s_aclk => '0', s_aresetn => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awvalid => '0', s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wlast => '0', s_axi_wvalid => '0', s_axi_bready => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arvalid => '0', s_axi_rready => '0', s_axi_injectsbiterr => '0', s_axi_injectdbiterr => '0' ); END win_arch;
library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity s1a_nov is port( clock: in std_logic; input: in std_logic_vector(7 downto 0); output: out std_logic_vector(5 downto 0) ); end s1a_nov; architecture behaviour of s1a_nov is constant st0: std_logic_vector(4 downto 0) := "10110"; constant st1: std_logic_vector(4 downto 0) := "11010"; constant st2: std_logic_vector(4 downto 0) := "10101"; constant st3: std_logic_vector(4 downto 0) := "01010"; constant st4: std_logic_vector(4 downto 0) := "11001"; constant st5: std_logic_vector(4 downto 0) := "00110"; constant st6: std_logic_vector(4 downto 0) := "00011"; constant st7: std_logic_vector(4 downto 0) := "01110"; constant st8: std_logic_vector(4 downto 0) := "00000"; constant st9: std_logic_vector(4 downto 0) := "11111"; constant st10: std_logic_vector(4 downto 0) := "00100"; constant st11: std_logic_vector(4 downto 0) := "01001"; constant st12: std_logic_vector(4 downto 0) := "00001"; constant st13: std_logic_vector(4 downto 0) := "10001"; constant st14: std_logic_vector(4 downto 0) := "10010"; constant st15: std_logic_vector(4 downto 0) := "11100"; constant st16: std_logic_vector(4 downto 0) := "11110"; constant st17: std_logic_vector(4 downto 0) := "01101"; constant st18: std_logic_vector(4 downto 0) := "00010"; constant st19: std_logic_vector(4 downto 0) := "11101"; signal current_state, next_state: std_logic_vector(4 downto 0); begin process(clock) begin if rising_edge(clock) then current_state <= next_state; end if; end process; process(input, current_state) begin next_state <= "-----"; output <= "------"; case current_state is when st0 => if std_match(input, "-1-00---") then next_state <= st0; output <= "000000"; elsif std_match(input, "00--0---") then next_state <= st0; output <= "000000"; elsif std_match(input, "-0--1---") then next_state <= st1; output <= "000000"; elsif std_match(input, "-1-01---") then next_state <= st1; output <= "000000"; elsif std_match(input, "01-10---") then next_state <= st2; output <= "000000"; elsif std_match(input, "11-10---") then next_state <= st5; output <= "000000"; elsif std_match(input, "-1-11---") then next_state <= st3; output <= "000000"; elsif std_match(input, "10--0---") then next_state <= st4; output <= "000000"; end if; when st1 => if std_match(input, "-0------") then next_state <= st6; output <= "000000"; elsif std_match(input, "-1-0----") then next_state <= st6; output <= "000000"; elsif std_match(input, "-1-1----") then next_state <= st7; output <= "000000"; end if; when st2 => if std_match(input, "0---0---") then next_state <= st2; output <= "000000"; elsif std_match(input, "----1---") then next_state <= st3; output <= "000000"; elsif std_match(input, "1---0---") then next_state <= st5; output <= "000000"; end if; when st3 => if std_match(input, "--------") then next_state <= st7; output <= "000000"; end if; when st4 => if std_match(input, "--0-----") then next_state <= st12; output <= "000000"; elsif std_match(input, "--1-----") then next_state <= st13; output <= "000000"; end if; when st5 => if std_match(input, "--------") then next_state <= st13; output <= "000000"; end if; when st6 => if std_match(input, "-0--1---") then next_state <= st6; output <= "000000"; elsif std_match(input, "-1-01---") then next_state <= st6; output <= "000000"; elsif std_match(input, "-1-11---") then next_state <= st7; output <= "000000"; elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000"; elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000"; elsif std_match(input, "11-10---") then next_state <= st11; output <= "000000"; elsif std_match(input, "10--0---") then next_state <= st15; output <= "000000"; elsif std_match(input, "01-10---") then next_state <= st9; output <= "000000"; end if; when st7 => if std_match(input, "----1---") then next_state <= st7; output <= "000000"; elsif std_match(input, "0---0---") then next_state <= st9; output <= "000000"; elsif std_match(input, "1---0---") then next_state <= st11; output <= "000000"; end if; when st8 => if std_match(input, "00--00--") then next_state <= st8; output <= "000000"; elsif std_match(input, "00---1-0") then next_state <= st8; output <= "000000"; elsif std_match(input, "-1-000--") then next_state <= st8; output <= "000000"; elsif std_match(input, "-1-0-1-0") then next_state <= st8; output <= "000000"; elsif std_match(input, "00--01-1") then next_state <= st0; output <= "000000"; elsif std_match(input, "-1-001-1") then next_state <= st0; output <= "000000"; elsif std_match(input, "-0--11-1") then next_state <= st1; output <= "000000"; elsif std_match(input, "-1-011-1") then next_state <= st1; output <= "000000"; elsif std_match(input, "10--01-1") then next_state <= st4; output <= "000000"; elsif std_match(input, "01-100--") then next_state <= st9; output <= "000000"; elsif std_match(input, "01-1-1--") then next_state <= st9; output <= "000000"; elsif std_match(input, "01-110--") then next_state <= st10; output <= "000000"; elsif std_match(input, "11-1----") then next_state <= st11; output <= "000000"; elsif std_match(input, "100-10--") then next_state <= st14; output <= "000000"; elsif std_match(input, "-1-010--") then next_state <= st14; output <= "000000"; elsif std_match(input, "101-101-") then next_state <= st14; output <= "000000"; elsif std_match(input, "00--10--") then next_state <= st14; output <= "000000"; elsif std_match(input, "10--00--") then next_state <= st15; output <= "000000"; elsif std_match(input, "10---1-0") then next_state <= st15; output <= "000000"; elsif std_match(input, "101-100-") then next_state <= st15; output <= "000000"; end if; when st9 => if std_match(input, "0---00--") then next_state <= st9; output <= "000000"; elsif std_match(input, "0----1-0") then next_state <= st9; output <= "000000"; elsif std_match(input, "0---01-1") then next_state <= st2; output <= "000000"; elsif std_match(input, "0---10--") then next_state <= st10; output <= "000000"; elsif std_match(input, "0---11-1") then next_state <= st3; output <= "000000"; elsif std_match(input, "1----0--") then next_state <= st11; output <= "000000"; elsif std_match(input, "1----1-0") then next_state <= st11; output <= "000000"; elsif std_match(input, "1----1-1") then next_state <= st5; output <= "000000"; end if; when st10 => if std_match(input, "------0-") then next_state <= st16; output <= "000000"; elsif std_match(input, "------1-") then next_state <= st7; output <= "000000"; end if; when st11 => if std_match(input, "-----1-1") then next_state <= st13; output <= "000000"; elsif std_match(input, "-----0--") then next_state <= st17; output <= "000000"; elsif std_match(input, "-----1-0") then next_state <= st17; output <= "000000"; end if; when st12 => if std_match(input, "1-0-----") then next_state <= st12; output <= "000000"; elsif std_match(input, "1-1-----") then next_state <= st13; output <= "000000"; elsif std_match(input, "0---1---") then next_state <= st1; output <= "000000"; elsif std_match(input, "0---0---") then next_state <= st0; output <= "000000"; end if; when st13 => if std_match(input, "1-------") then next_state <= st13; output <= "000000"; elsif std_match(input, "0---0---") then next_state <= st0; output <= "000000"; elsif std_match(input, "0---1---") then next_state <= st1; output <= "000000"; end if; when st14 => if std_match(input, "---0--1-") then next_state <= st6; output <= "000000"; elsif std_match(input, "---0--0-") then next_state <= st18; output <= "000000"; elsif std_match(input, "-0-1----") then next_state <= st18; output <= "000000"; elsif std_match(input, "-1-1----") then next_state <= st16; output <= "000000"; end if; when st15 => if std_match(input, "--0--0--") then next_state <= st19; output <= "000000"; elsif std_match(input, "--0--1-0") then next_state <= st19; output <= "000000"; elsif std_match(input, "--0--1-1") then next_state <= st12; output <= "000000"; elsif std_match(input, "--1-----") then next_state <= st17; output <= "000000"; end if; when st16 => if std_match(input, "----1-0-") then next_state <= st16; output <= "000000"; elsif std_match(input, "----1-1-") then next_state <= st7; output <= "000000"; elsif std_match(input, "1---0---") then next_state <= st11; output <= "000000"; elsif std_match(input, "0---0---") then next_state <= st9; output <= "000000"; end if; when st17 => if std_match(input, "1----0--") then next_state <= st17; output <= "000000"; elsif std_match(input, "1----1-0") then next_state <= st17; output <= "000000"; elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000"; elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000"; elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000000"; elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000000"; elsif std_match(input, "1----1-1") then next_state <= st13; output <= "000000"; elsif std_match(input, "0---10--") then next_state <= st14; output <= "000000"; end if; when st18 => if std_match(input, "----1-1-") then next_state <= st6; output <= "000000"; elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000"; elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000"; elsif std_match(input, "01-10---") then next_state <= st9; output <= "000000"; elsif std_match(input, "11-10---") then next_state <= st11; output <= "000000"; elsif std_match(input, "10--0---") then next_state <= st15; output <= "000000"; elsif std_match(input, "-1-11-0-") then next_state <= st16; output <= "000000"; elsif std_match(input, "-0--1-0-") then next_state <= st18; output <= "000000"; elsif std_match(input, "-1-01-0-") then next_state <= st18; output <= "000000"; end if; when st19 => if std_match(input, "1-0--0--") then next_state <= st19; output <= "000000"; elsif std_match(input, "1-0--1-0") then next_state <= st19; output <= "000000"; elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000"; elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000"; elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000000"; elsif std_match(input, "0---10--") then next_state <= st14; output <= "000000"; elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000000"; elsif std_match(input, "1-0--1-1") then next_state <= st12; output <= "000000"; elsif std_match(input, "1-1-----") then next_state <= st17; output <= "000000"; end if; when others => next_state <= "-----"; output <= "------"; end case; end process; end behaviour;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc194.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s00b00x00p11n01i00194ent IS END c03s00b00x00p11n01i00194ent; ARCHITECTURE c03s00b00x00p11n01i00194arch OF c03s00b00x00p11n01i00194ent IS type T1 is array (0 to 31) of BIT; subtype T2 is integer range 2 to 20; signal S1 : T2 ; BEGIN TESTING: PROCESS BEGIN S1 <= 15 after 10 ns; -- no_failure_here wait for 20 ns; assert NOT(S1 = 15) report "***PASSED TEST: c03s00b00x00p11n01i00194" severity NOTE; assert ( S1 = 15 ) report "***FAILED TEST: c03s00b00x00p11n01i00194 - The assignment operation to an object having a given subtype only assigns values that belong to the subtype." severity ERROR; wait; END PROCESS TESTING; END c03s00b00x00p11n01i00194arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc194.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s00b00x00p11n01i00194ent IS END c03s00b00x00p11n01i00194ent; ARCHITECTURE c03s00b00x00p11n01i00194arch OF c03s00b00x00p11n01i00194ent IS type T1 is array (0 to 31) of BIT; subtype T2 is integer range 2 to 20; signal S1 : T2 ; BEGIN TESTING: PROCESS BEGIN S1 <= 15 after 10 ns; -- no_failure_here wait for 20 ns; assert NOT(S1 = 15) report "***PASSED TEST: c03s00b00x00p11n01i00194" severity NOTE; assert ( S1 = 15 ) report "***FAILED TEST: c03s00b00x00p11n01i00194 - The assignment operation to an object having a given subtype only assigns values that belong to the subtype." severity ERROR; wait; END PROCESS TESTING; END c03s00b00x00p11n01i00194arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc194.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s00b00x00p11n01i00194ent IS END c03s00b00x00p11n01i00194ent; ARCHITECTURE c03s00b00x00p11n01i00194arch OF c03s00b00x00p11n01i00194ent IS type T1 is array (0 to 31) of BIT; subtype T2 is integer range 2 to 20; signal S1 : T2 ; BEGIN TESTING: PROCESS BEGIN S1 <= 15 after 10 ns; -- no_failure_here wait for 20 ns; assert NOT(S1 = 15) report "***PASSED TEST: c03s00b00x00p11n01i00194" severity NOTE; assert ( S1 = 15 ) report "***FAILED TEST: c03s00b00x00p11n01i00194 - The assignment operation to an object having a given subtype only assigns values that belong to the subtype." severity ERROR; wait; END PROCESS TESTING; END c03s00b00x00p11n01i00194arch;
entity tb2 is end tb2; architecture behav of tb2 is signal s : bit; signal clk : bit; begin -- psl default clock is (clk'event and clk = '1'); postponed assert always {s = '0'; s = '1'} severity failure; process begin s <= '1'; wait for 0 ns; s <= '0'; wait; end process; end behav;
entity tb2 is end tb2; architecture behav of tb2 is signal s : bit; signal clk : bit; begin -- psl default clock is (clk'event and clk = '1'); postponed assert always {s = '0'; s = '1'} severity failure; process begin s <= '1'; wait for 0 ns; s <= '0'; wait; end process; end behav;
-- ------------------------------------------------------------- -- -- Entity Declaration for inst_t_e -- -- Generated -- by: wig -- on: Mon Oct 10 12:25:03 2005 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../bitsplice.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_t_e-e.vhd,v 1.2 2005/11/30 14:20:41 wig Exp $ -- $Date: 2005/11/30 14:20:41 $ -- $Log: inst_t_e-e.vhd,v $ -- Revision 1.2 2005/11/30 14:20:41 wig -- Updated testcase references -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.59 2005/10/06 11:21:44 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.37 , wilfried.gaensheimer@micronas.com -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity inst_t_e -- entity inst_t_e is -- Generics: -- No Generated Generics for Entity inst_t_e -- Generated Port Declaration: -- No Generated Port for Entity inst_t_e end inst_t_e; -- -- End of Generated Entity inst_t_e -- -- --!End of Entity/ies -- --------------------------------------------------------------
Library IEEE; use IEEE.std_logic_1164.all; entity nxor is port( A: in std_logic_vector (2 downto 0); Q: out std_logic_vector (0 downto 0)); end entity nxor; architecture Behave of nxor is begin process (A) begin case A is when "000" => Q <= "0"; when "001" => Q <= "1"; when "010" => Q <= "1"; when "011" => Q <= "0"; when "100" => Q <= "1"; when "101" => Q <= "0"; when "110" => Q <= "0"; when "111" => Q <= "1"; when others => Q <= "0"; end case; end process; end Behave;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_03_ch_03_10.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- entity ch_03_10 is end entity ch_03_10; architecture test of ch_03_10 is type opcode_type is (nop, add, subtract); signal opcode : opcode_type := nop; begin process_3_3_a : process (opcode) is variable Acc : integer := 0; constant operand : integer := 1; begin -- code from book: case opcode is when add => Acc := Acc + operand; when subtract => Acc := Acc - operand; when nop => null; end case; -- end of code from book end process process_3_3_a; stimulus : process is begin opcode <= add after 10 ns, subtract after 20 ns, nop after 30 ns; wait; end process stimulus; end architecture test;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_03_ch_03_10.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- entity ch_03_10 is end entity ch_03_10; architecture test of ch_03_10 is type opcode_type is (nop, add, subtract); signal opcode : opcode_type := nop; begin process_3_3_a : process (opcode) is variable Acc : integer := 0; constant operand : integer := 1; begin -- code from book: case opcode is when add => Acc := Acc + operand; when subtract => Acc := Acc - operand; when nop => null; end case; -- end of code from book end process process_3_3_a; stimulus : process is begin opcode <= add after 10 ns, subtract after 20 ns, nop after 30 ns; wait; end process stimulus; end architecture test;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_03_ch_03_10.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- entity ch_03_10 is end entity ch_03_10; architecture test of ch_03_10 is type opcode_type is (nop, add, subtract); signal opcode : opcode_type := nop; begin process_3_3_a : process (opcode) is variable Acc : integer := 0; constant operand : integer := 1; begin -- code from book: case opcode is when add => Acc := Acc + operand; when subtract => Acc := Acc - operand; when nop => null; end case; -- end of code from book end process process_3_3_a; stimulus : process is begin opcode <= add after 10 ns, subtract after 20 ns, nop after 30 ns; wait; end process stimulus; end architecture test;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_textio.all; use ieee.std_logic_unsigned.all; use std.textio.all; use ieee.numeric_std.all; entity tb is generic( address_width: integer := 16; memory_file : string := "code.txt"; log_file: string := "out.txt"; uart_support : string := "no" ); end tb; architecture tb of tb is signal clock_in, reset, data, stall, stall_sig: std_logic := '0'; signal uart_read, uart_write: std_logic; signal boot_enable_n, ram_enable_n, ram_dly: std_logic; signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0); signal ext_irq: std_logic_vector(7 downto 0); signal data_we, data_w_n_ram: std_logic_vector(3 downto 0); signal periph, periph_dly, periph_wr, periph_irq: std_logic; signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0); signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(7 downto 0); signal gpio_sig: std_logic := '0'; begin process --25Mhz system clock begin clock_in <= not clock_in; wait for 20 ns; clock_in <= not clock_in; wait for 20 ns; end process; process begin wait for 4 ms; gpio_sig <= not gpio_sig; wait for 100 us; gpio_sig <= not gpio_sig; end process; gpioa_in <= "0000" & gpio_sig & "000"; process begin stall <= not stall; wait for 123 ns; stall <= not stall; wait for 123 ns; end process; reset <= '0', '1' after 5 ns, '0' after 500 ns; stall_sig <= '0'; --stall; ext_irq <= "0000000" & periph_irq; boot_enable_n <= '0' when (address(31 downto 28) = "0000" and stall_sig = '0') or reset = '1' else '1'; ram_enable_n <= '0' when (address(31 downto 28) = "0100" and stall_sig = '0') or reset = '1' else '1'; data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram; data_w_n_ram <= not data_we; process(clock_in, reset) begin if reset = '1' then ram_dly <= '0'; periph_dly <= '0'; elsif clock_in'event and clock_in = '1' then ram_dly <= not ram_enable_n; periph_dly <= periph; end if; end process; -- HF-RISCV core processor: entity work.processor port map( clk_i => clock_in, rst_i => reset, stall_i => stall_sig, addr_o => address, data_i => data_read, data_o => data_write, data_w_o => data_we, data_mode_o => open, extio_in => ext_irq, extio_out => open ); data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24); data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24); periph_wr <= '1' when data_we /= "0000" else '0'; periph <= '1' when address(31 downto 28) = x"e" else '0'; peripherals: entity work.peripherals port map( clk_i => clock_in, rst_i => reset, addr_i => address, data_i => data_write_periph, data_o => data_read_periph_s, sel_i => periph, wr_i => periph_wr, irq_o => periph_irq, gpioa_in => gpioa_in, gpioa_out => gpioa_out, gpioa_ddr => gpioa_ddr ); -- boot ROM boot0lb: entity work.boot_ram generic map ( memory_file => "boot.txt", data_width => 8, address_width => 12, bank => 0) port map( clk => clock_in, addr => address(11 downto 2), cs_n => boot_enable_n, we_n => '1', data_i => (others => '0'), data_o => data_read_boot(7 downto 0) ); boot0ub: entity work.boot_ram generic map ( memory_file => "boot.txt", data_width => 8, address_width => 12, bank => 1) port map( clk => clock_in, addr => address(11 downto 2), cs_n => boot_enable_n, we_n => '1', data_i => (others => '0'), data_o => data_read_boot(15 downto 8) ); boot1lb: entity work.boot_ram generic map ( memory_file => "boot.txt", data_width => 8, address_width => 12, bank => 2) port map( clk => clock_in, addr => address(11 downto 2), cs_n => boot_enable_n, we_n => '1', data_i => (others => '0'), data_o => data_read_boot(23 downto 16) ); boot1ub: entity work.boot_ram generic map ( memory_file => "boot.txt", data_width => 8, address_width => 12, bank => 3) port map( clk => clock_in, addr => address(11 downto 2), cs_n => boot_enable_n, we_n => '1', data_i => (others => '0'), data_o => data_read_boot(31 downto 24) ); -- RAM memory0lb: entity work.bram generic map ( memory_file => memory_file, data_width => 8, address_width => address_width, bank => 0) port map( clk => clock_in, addr => address(address_width -1 downto 2), cs_n => ram_enable_n, we_n => data_w_n_ram(0), data_i => data_write(7 downto 0), data_o => data_read_ram(7 downto 0) ); memory0ub: entity work.bram generic map ( memory_file => memory_file, data_width => 8, address_width => address_width, bank => 1) port map( clk => clock_in, addr => address(address_width -1 downto 2), cs_n => ram_enable_n, we_n => data_w_n_ram(1), data_i => data_write(15 downto 8), data_o => data_read_ram(15 downto 8) ); memory1lb: entity work.bram generic map ( memory_file => memory_file, data_width => 8, address_width => address_width, bank => 2) port map( clk => clock_in, addr => address(address_width -1 downto 2), cs_n => ram_enable_n, we_n => data_w_n_ram(2), data_i => data_write(23 downto 16), data_o => data_read_ram(23 downto 16) ); memory1ub: entity work.bram generic map ( memory_file => memory_file, data_width => 8, address_width => address_width, bank => 3) port map( clk => clock_in, addr => address(address_width -1 downto 2), cs_n => ram_enable_n, we_n => data_w_n_ram(3), data_i => data_write(31 downto 24), data_o => data_read_ram(31 downto 24) ); -- debug process debug: if uart_support = "no" generate process(clock_in, address) file store_file : text open write_mode is "debug.txt"; variable hex_file_line : line; variable c : character; variable index : natural; variable line_length : natural := 0; begin if clock_in'event and clock_in = '1' then if address = x"f00000d0" and data = '0' then data <= '1'; index := conv_integer(data_write(30 downto 24)); if index /= 10 then c := character'val(index); write(hex_file_line, c); line_length := line_length + 1; end if; if index = 10 or line_length >= 72 then writeline(store_file, hex_file_line); line_length := 0; end if; else data <= '0'; end if; end if; end process; end generate; process(clock_in, reset, address) begin if reset = '1' then elsif clock_in'event and clock_in = '0' then assert address /= x"e0000000" report "end of simulation" severity failure; assert (address < x"50000000") or (address >= x"e0000000") report "out of memory region" severity failure; assert address /= x"40000104" report "handling IRQ" severity warning; end if; end process; end tb;
library verilog; use verilog.vl_types.all; entity cw3_vlg_sample_tst is port( clk : in vl_logic; DOWN : in vl_logic; UP : in vl_logic; sampler_tx : out vl_logic ); end cw3_vlg_sample_tst;
----------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- -- -- This file is part of the DSP-Crowd project -- -- https://www.dsp-crowd.com -- -- -- -- Author(s): -- -- - Johannes Natter, office@dsp-crowd.com -- -- -- ----------------------------------------------------------------------------- -- -- -- Copyright (C) 2015 Authors and www.dsp-crowd.com -- -- -- -- This program is free software: you can redistribute it and/or modify -- -- it under the terms of the GNU General Public License as published by -- -- the Free Software Foundation, either version 3 of the License, or -- -- (at your option) any later version. -- -- -- -- This program is distributed in the hope that it will be useful, -- -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- -- GNU General Public License for more details. -- -- -- -- You should have received a copy of the GNU General Public License -- -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- -- ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package spi2rgb_pkg is --------------------------------------------------------------------- -- Constants / Types --------------------------------------------------------------------- constant SPI2RGB_NUM_DATA_BYTES : natural := 3; type SPI2RGB_DATA_TYPE is array (SPI2RGB_NUM_DATA_BYTES - 1 downto 0) of std_ulogic_vector(7 downto 0); end spi2rgb_pkg;
------------------------------------------------------------------------------- -- lmb_bram_if_funcs.vhd - Entity and architecture ------------------------------------------------------------------------------- -- -- (c) Copyright 2001-2015 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------- -- Filename: lmb_bram_if_funcs.vhd -- -- Description: Support functions for lmb_bram_if_cntlr -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- lmb_bram_if_funcs.vhd -- ------------------------------------------------------------------------------- -- Author: stefana ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; package lmb_bram_if_funcs is type TARGET_FAMILY_TYPE is ( -- pragma xilinx_rtl_off VIRTEX7, KINTEX7, ARTIX7, ZYNQ, VIRTEXU, KINTEXU, ZYNQUPLUS, VIRTEXUPLUS, KINTEXUPLUS, SPARTAN7, -- pragma xilinx_rtl_on RTL ); function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE; -- Get the maximum number of inputs to a LUT. function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer; end package lmb_bram_if_funcs; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; package body lmb_bram_if_funcs is function LowerCase_Char(char : character) return character is begin -- If char is not an upper case letter then return char if char < 'A' or char > 'Z' then return char; end if; -- Otherwise map char to its corresponding lower case character and -- return that case char is when 'A' => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd'; when 'E' => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h'; when 'I' => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l'; when 'M' => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p'; when 'Q' => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't'; when 'U' => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x'; when 'Y' => return 'y'; when 'Z' => return 'z'; when others => return char; end case; end LowerCase_Char; -- Returns true if case insensitive string comparison determines that -- str1 and str2 are equal function Equal_String( str1, str2 : STRING ) RETURN BOOLEAN IS CONSTANT len1 : INTEGER := str1'length; CONSTANT len2 : INTEGER := str2'length; VARIABLE equal : BOOLEAN := TRUE; BEGIN IF NOT (len1=len2) THEN equal := FALSE; ELSE FOR i IN str1'range LOOP IF NOT (LowerCase_Char(str1(i)) = LowerCase_Char(str2(i))) THEN equal := FALSE; END IF; END LOOP; END IF; RETURN equal; END Equal_String; function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE is begin -- function String_To_Family if ((Select_RTL) or Equal_String(S, "rtl")) then return RTL; elsif Equal_String(S, "virtex7") or Equal_String(S, "qvirtex7") then return VIRTEX7; elsif Equal_String(S, "kintex7") or Equal_String(S, "kintex7l") or Equal_String(S, "qkintex7") or Equal_String(S, "qkintex7l") then return KINTEX7; elsif Equal_String(S, "artix7") or Equal_String(S, "artix7l") or Equal_String(S, "aartix7") or Equal_String(S, "qartix7") or Equal_String(S, "qartix7l") then return ARTIX7; elsif Equal_String(S, "zynq") or Equal_String(S, "azynq") or Equal_String(S, "qzynq") then return ZYNQ; elsif Equal_String(S, "virtexu") or Equal_String(S, "qvirtexu") then return VIRTEXU; elsif Equal_String(S, "kintexu") or Equal_String(S, "kintexul") or Equal_String(S, "qkintexu") or Equal_String(S, "qkintexul") then return KINTEXU; elsif Equal_String(S, "zynquplus") then return ZYNQUPLUS; elsif Equal_String(S, "virtexuplus") then return VIRTEXUPLUS; elsif Equal_String(S, "kintexuplus") then return KINTEXUPLUS; elsif Equal_String(S, "spartan7") then return SPARTAN7; else -- assert (false) report "No known target family" severity failure; return RTL; end if; end function String_To_Family; function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer is begin return 6; end function Family_To_LUT_Size; end package body lmb_bram_if_funcs; ------------------------------------------------------------------------------- -- primitives.vhd - Entity and architecture ------------------------------------------------------------------------------- -- -- (c) Copyright 2015 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------- -- Filename: primitives.vhd -- -- Description: -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- lmb_bram_if_primitives.vhd -- ------------------------------------------------------------------------------- -- Author: rolandp -- -- History: -- rolandp 2015-01-22 First Version -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- ----- entity LUT6 ----- library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; library lmb_bram_if_cntlr_v4_0_10; use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all; entity MB_LUT6 is generic ( C_TARGET : TARGET_FAMILY_TYPE; INIT : bit_vector := X"0000000000000000" ); port ( O : out std_logic; I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; I4 : in std_logic; I5 : in std_logic ); end entity MB_LUT6; library Unisim; use Unisim.vcomponents.all; architecture IMP of MB_LUT6 is begin Using_RTL: if ( C_TARGET = RTL ) generate constant INIT_reg : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT); begin process (I0, I1, I2, I3, I4, I5) variable I_reg : std_logic_vector(5 downto 0); variable I0_v, I1_v, I2_v, I3_v, I4_v, I5_v : std_logic; begin -- Filter unknowns if I0 = '0' then I0_v := '0'; else I0_v := '1'; end if; if I1 = '0' then I1_v := '0'; else I1_v := '1'; end if; if I2 = '0' then I2_v := '0'; else I2_v := '1'; end if; if I3 = '0' then I3_v := '0'; else I3_v := '1'; end if; if I4 = '0' then I4_v := '0'; else I4_v := '1'; end if; if I5 = '0' then I5_v := '0'; else I5_v := '1'; end if; I_reg := TO_STDLOGICVECTOR(I5_v & I4_v & I3_v & I2_v & I1_v & I0_v); O <= INIT_reg(TO_INTEGER(unsigned(I_reg))); end process; end generate Using_RTL; Using_FPGA: if ( C_TARGET /= RTL ) generate begin Native: LUT6 generic map( INIT => INIT ) port map( O => O, I0 => I0, I1 => I1, I2 => I2, I3 => I3, I4 => I4, I5 => I5 ); end generate Using_FPGA; end architecture IMP; ----- entity MUXCY ----- library IEEE; use IEEE.std_logic_1164.all; library lmb_bram_if_cntlr_v4_0_10; use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all; entity MB_MUXCY is generic ( C_TARGET : TARGET_FAMILY_TYPE ); port ( LO : out std_logic; CI : in std_logic; DI : in std_logic; S : in std_logic ); end entity MB_MUXCY; library Unisim; use Unisim.vcomponents.all; architecture IMP of MB_MUXCY is begin Using_RTL: if ( C_TARGET = RTL ) generate begin LO <= DI when S = '0' else CI; end generate Using_RTL; Using_FPGA: if ( C_TARGET /= RTL ) generate begin Native: MUXCY_L port map( LO => LO, CI => CI, DI => DI, S => S ); end generate Using_FPGA; end architecture IMP; ----- entity XORCY ----- library IEEE; use IEEE.std_logic_1164.all; library lmb_bram_if_cntlr_v4_0_10; use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all; entity MB_XORCY is generic ( C_TARGET : TARGET_FAMILY_TYPE ); port ( O : out std_logic; CI : in std_logic; LI : in std_logic ); end entity MB_XORCY; library Unisim; use Unisim.vcomponents.all; architecture IMP of MB_XORCY is begin Using_RTL: if ( C_TARGET = RTL ) generate begin O <= (CI xor LI); end generate Using_RTL; Using_FPGA: if ( C_TARGET /= RTL ) generate begin Native: XORCY port map( O => O, CI => CI, LI => LI ); end generate Using_FPGA; end architecture IMP; ----- entity MUXF7 ----- library IEEE; use IEEE.std_logic_1164.all; library lmb_bram_if_cntlr_v4_0_10; use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all; entity MB_MUXF7 is generic ( C_TARGET : TARGET_FAMILY_TYPE ); port ( O : out std_logic; I0 : in std_logic; I1 : in std_logic; S : in std_logic ); end entity MB_MUXF7; library Unisim; use Unisim.vcomponents.all; architecture IMP of MB_MUXF7 is begin Using_RTL: if ( C_TARGET = RTL ) generate begin O <= I0 when S = '0' else I1; end generate Using_RTL; Using_FPGA: if ( C_TARGET /= RTL ) generate begin Native: MUXF7 port map( O => O, I0 => I0, I1 => I1, S => S ); end generate Using_FPGA; end architecture IMP; ----- entity MUXF8 ----- library IEEE; use IEEE.std_logic_1164.all; library lmb_bram_if_cntlr_v4_0_10; use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all; entity MB_MUXF8 is generic ( C_TARGET : TARGET_FAMILY_TYPE ); port ( O : out std_logic; I0 : in std_logic; I1 : in std_logic; S : in std_logic ); end entity MB_MUXF8; library Unisim; use Unisim.vcomponents.all; architecture IMP of MB_MUXF8 is begin Using_RTL: if ( C_TARGET = RTL ) generate begin O <= I0 when S = '0' else I1; end generate Using_RTL; Using_FPGA: if ( C_TARGET /= RTL ) generate begin Native: MUXF8 port map( O => O, I0 => I0, I1 => I1, S => S ); end generate Using_FPGA; end architecture IMP; ----- entity FDRE ----- library IEEE; use IEEE.std_logic_1164.all; library lmb_bram_if_cntlr_v4_0_10; use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all; entity MB_FDRE is generic ( C_TARGET : TARGET_FAMILY_TYPE; INIT : bit := '0' ); port( Q : out std_logic; C : in std_logic; CE : in std_logic; D : in std_logic; R : in std_logic ); end entity MB_FDRE; library Unisim; use Unisim.vcomponents.all; architecture IMP of MB_FDRE is begin Using_RTL: if ( C_TARGET = RTL ) generate function To_StdLogic(A : in bit ) return std_logic is begin if( A = '1' ) then return '1'; end if; return '0'; end; signal q_o : std_logic := To_StdLogic(INIT); begin Q <= q_o; process(C) begin if (rising_edge(C)) then if (R = '1') then q_o <= '0'; elsif (CE = '1') then q_o <= D; end if; end if; end process; end generate Using_RTL; Using_FPGA: if ( C_TARGET /= RTL ) generate begin Native: FDRE generic map( INIT => INIT ) port map( Q => Q, C => C, CE => CE, D => D, R => R ); end generate Using_FPGA; end architecture IMP; ------------------------------------------------------------------------------- -- xor18.vhd - Entity and architecture ------------------------------------------------------------------------------- -- -- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES -- ------------------------------------------------------------------------------ -- Filename: xor18.vhd -- -- Description: -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- xor18.vhd -- ------------------------------------------------------------------------------- -- Author: rolandp ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library lmb_bram_if_cntlr_v4_0_10; use lmb_bram_if_cntlr_v4_0_10.all; use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all; entity XOR18 is generic ( C_TARGET : TARGET_FAMILY_TYPE); port ( InA : in std_logic_vector(0 to 17); res : out std_logic); end entity XOR18; architecture IMP of XOR18 is component MB_LUT6 is generic ( C_TARGET : TARGET_FAMILY_TYPE; INIT : bit_vector := X"0000000000000000" ); port ( O : out std_logic; I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; I4 : in std_logic; I5 : in std_logic ); end component MB_LUT6; component MB_MUXCY is generic ( C_TARGET : TARGET_FAMILY_TYPE ); port ( LO : out std_logic; CI : in std_logic; DI : in std_logic; S : in std_logic ); end component MB_MUXCY; component MB_XORCY is generic ( C_TARGET : TARGET_FAMILY_TYPE ); port ( O : out std_logic; CI : in std_logic; LI : in std_logic ); end component MB_XORCY; begin -- architecture IMP Using_FPGA: if ( C_TARGET /= RTL ) generate signal xor6_1 : std_logic; signal xor6_2 : std_logic; signal xor6_3 : std_logic; signal xor18_c1 : std_logic; signal xor18_c2 : std_logic; begin -- generate Using_LUT6 XOR6_1_LUT : MB_LUT6 generic map( C_TARGET => C_TARGET, INIT => X"6996966996696996") port map( O => xor6_1, I0 => InA(17), I1 => InA(16), I2 => InA(15), I3 => InA(14), I4 => InA(13), I5 => InA(12)); XOR_1st_MUXCY : MB_MUXCY generic map( C_TARGET => C_TARGET) port map ( DI => '1', CI => '0', S => xor6_1, LO => xor18_c1); XOR6_2_LUT : MB_LUT6 generic map( C_TARGET => C_TARGET, INIT => X"6996966996696996") port map( O => xor6_2, I0 => InA(11), I1 => InA(10), I2 => InA(9), I3 => InA(8), I4 => InA(7), I5 => InA(6)); XOR_2nd_MUXCY : MB_MUXCY generic map( C_TARGET => C_TARGET) port map ( DI => xor6_1, CI => xor18_c1, S => xor6_2, LO => xor18_c2); XOR6_3_LUT : MB_LUT6 generic map( C_TARGET => C_TARGET, INIT => X"6996966996696996") port map( O => xor6_3, I0 => InA(5), I1 => InA(4), I2 => InA(3), I3 => InA(2), I4 => InA(1), I5 => InA(0)); XOR18_XORCY : MB_XORCY generic map( C_TARGET => C_TARGET) port map ( LI => xor6_3, CI => xor18_c2, O => res); end generate Using_FPGA; Using_RTL: if ( C_TARGET = RTL ) generate begin res <= InA(17) xor InA(16) xor InA(15) xor InA(14) xor InA(13) xor InA(12) xor InA(11) xor InA(10) xor InA(9) xor InA(8) xor InA(7) xor InA(6) xor InA(5) xor InA(4) xor InA(3) xor InA(2) xor InA(1) xor InA(0); end generate Using_RTL; end architecture IMP; ------------------------------------------------------------------------------- -- parity.vhd - Entity and architecture ------------------------------------------------------------------------------- -- -- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES -- ------------------------------------------------------------------------------ -- Filename: parity.vhd -- -- Description: Generate parity optimally for all target architectures -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- parity.vhd -- xor18.vhd -- parity_recursive_LUT6.vhd -- ------------------------------------------------------------------------------- -- Author: stefana ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library lmb_bram_if_cntlr_v4_0_10; use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all; entity Parity is generic ( C_TARGET : TARGET_FAMILY_TYPE; C_SIZE : integer := 6 ); port ( InA : in std_logic_vector(0 to C_SIZE - 1); Res : out std_logic ); end entity Parity; architecture IMP of Parity is component MB_LUT6 is generic ( C_TARGET : TARGET_FAMILY_TYPE; INIT : bit_vector := X"0000000000000000" ); port ( O : out std_logic; I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; I4 : in std_logic; I5 : in std_logic ); end component MB_LUT6; component MB_MUXF7 is generic ( C_TARGET : TARGET_FAMILY_TYPE ); port ( O : out std_logic; I0 : in std_logic; I1 : in std_logic; S : in std_logic ); end component MB_MUXF7; component MB_MUXF8 is generic ( C_TARGET : TARGET_FAMILY_TYPE ); port ( O : out std_logic; I0 : in std_logic; I1 : in std_logic; S : in std_logic ); end component MB_MUXF8; -- Non-recursive loop implementation function ParityGen (InA : std_logic_vector) return std_logic is variable result : std_logic; begin result := '0'; for I in InA'range loop result := result xor InA(I); end loop; return result; end function ParityGen; begin -- architecture IMP Using_FPGA : if (C_TARGET /= RTL) generate -------------------------------------------------------------------------------------------------- -- Single LUT6 -------------------------------------------------------------------------------------------------- Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate signal inA6 : std_logic_vector(0 to 5); begin Assign_InA : process (InA) is begin inA6 <= (others => '0'); inA6(0 to InA'length - 1) <= InA; end process Assign_InA; XOR6_LUT : MB_LUT6 generic map( C_TARGET => C_TARGET, INIT => X"6996966996696996") port map( O => Res, I0 => inA6(5), I1 => inA6(4), I2 => inA6(3), I3 => inA6(2), I4 => inA6(1), I5 => inA6(0)); end generate Single_LUT6; -------------------------------------------------------------------------------------------------- -- Two LUT6 and one MUXF7 -------------------------------------------------------------------------------------------------- Use_MUXF7 : if C_SIZE = 7 generate signal inA7 : std_logic_vector(0 to 6); signal result6 : std_logic; signal result6n : std_logic; begin Assign_InA : process (InA) is begin inA7 <= (others => '0'); inA7(0 to InA'length - 1) <= InA; end process Assign_InA; XOR6_LUT : MB_LUT6 generic map( C_TARGET => C_TARGET, INIT => X"6996966996696996") port map( O => result6, I0 => inA7(5), I1 => inA7(4), I2 => inA7(3), I3 => inA7(2), I4 => inA7(1), I5 => inA7(0)); XOR6_LUT_N : MB_LUT6 generic map( C_TARGET => C_TARGET, INIT => X"9669699669969669") port map( O => result6n, I0 => inA7(5), I1 => inA7(4), I2 => inA7(3), I3 => inA7(2), I4 => inA7(1), I5 => inA7(0)); MUXF7_LUT : MB_MUXF7 generic map( C_TARGET => C_TARGET) port map ( O => Res, I0 => result6, I1 => result6n, S => inA7(6)); end generate Use_MUXF7; -------------------------------------------------------------------------------------------------- -- Four LUT6, two MUXF7 and one MUXF8 -------------------------------------------------------------------------------------------------- Use_MUXF8 : if C_SIZE = 8 generate signal inA8 : std_logic_vector(0 to 7); signal result6_1 : std_logic; signal result6_1n : std_logic; signal result6_2 : std_logic; signal result6_2n : std_logic; signal result7_1 : std_logic; signal result7_1n : std_logic; begin Assign_InA : process (InA) is begin inA8 <= (others => '0'); inA8(0 to InA'length - 1) <= InA; end process Assign_InA; XOR6_LUT1 : MB_LUT6 generic map( C_TARGET => C_TARGET, INIT => X"6996966996696996") port map( O => result6_1, I0 => inA8(5), I1 => inA8(4), I2 => inA8(3), I3 => inA8(2), I4 => inA8(1), I5 => inA8(0)); XOR6_LUT2_N : MB_LUT6 generic map( C_TARGET => C_TARGET, INIT => X"9669699669969669") port map( O => result6_1n, I0 => inA8(5), I1 => inA8(4), I2 => inA8(3), I3 => inA8(2), I4 => inA8(1), I5 => inA8(0)); MUXF7_LUT1 : MB_MUXF7 generic map( C_TARGET => C_TARGET) port map ( O => result7_1, I0 => result6_1, I1 => result6_1n, S => inA8(6)); XOR6_LUT3 : MB_LUT6 generic map( C_TARGET => C_TARGET, INIT => X"6996966996696996") port map( O => result6_2, I0 => inA8(5), I1 => inA8(4), I2 => inA8(3), I3 => inA8(2), I4 => inA8(1), I5 => inA8(0)); XOR6_LUT4_N : MB_LUT6 generic map( C_TARGET => C_TARGET, INIT => X"9669699669969669") port map( O => result6_2n, I0 => inA8(5), I1 => inA8(4), I2 => inA8(3), I3 => inA8(2), I4 => inA8(1), I5 => inA8(0)); MUXF7_LUT2 : MB_MUXF7 generic map( C_TARGET => C_TARGET) port map ( O => result7_1n, I0 => result6_2n, I1 => result6_2, S => inA8(6)); MUXF8_LUT : MB_MUXF8 generic map( C_TARGET => C_TARGET) port map ( O => res, I0 => result7_1, I1 => result7_1n, S => inA8(7)); end generate Use_MUXF8; end generate Using_FPGA; Using_RTL: if ( C_TARGET = RTL ) generate begin Res <= ParityGen(InA); end generate Using_RTL; end architecture IMP; ------------------------------------------------------------------------------- -- parityenable.vhd - Entity and architecture ------------------------------------------------------------------------------- -- -- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES -- ------------------------------------------------------------------------------ -- Filename: parity.vhd -- -- Description: Generate parity optimally for all target architectures -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- parity.vhd -- xor18.vhd -- parity_recursive_LUT6.vhd -- ------------------------------------------------------------------------------- -- Author: stefana ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library lmb_bram_if_cntlr_v4_0_10; use lmb_bram_if_cntlr_v4_0_10.all; use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all; entity ParityEnable is generic ( C_TARGET : TARGET_FAMILY_TYPE; C_SIZE : integer := 4 ); port ( InA : in std_logic_vector(0 to C_SIZE - 1); Enable : in std_logic; Res : out std_logic ); end entity ParityEnable; architecture IMP of ParityEnable is -- Non-recursive loop implementation function ParityGen (InA : std_logic_vector) return std_logic is variable result : std_logic; begin result := '0'; for I in InA'range loop result := result xor InA(I); end loop; return result; end function ParityGen; component MB_LUT6 is generic ( C_TARGET : TARGET_FAMILY_TYPE; INIT : bit_vector := X"0000000000000000" ); port ( O : out std_logic; I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; I4 : in std_logic; I5 : in std_logic ); end component MB_LUT6; begin -- architecture IMP Using_FPGA: if ( C_TARGET /= RTL ) generate -------------------------------------------------------------------------------------------------- -- Single LUT6 -------------------------------------------------------------------------------------------------- Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 5 generate signal inA5 : std_logic_vector(0 to 4); begin Assign_InA : process (InA) is begin inA5 <= (others => '0'); inA5(0 to InA'length - 1) <= InA; end process Assign_InA; XOR6_LUT : MB_LUT6 generic map( C_TARGET => C_TARGET, INIT => X"9669699600000000") port map( O => Res, I0 => InA5(4), I1 => inA5(3), I2 => inA5(2), I3 => inA5(1), I4 => inA5(0), I5 => Enable); end generate Single_LUT6; end generate Using_FPGA; Using_RTL: if ( C_TARGET = RTL ) generate begin Res <= Enable and ParityGen(InA); end generate Using_RTL; end architecture IMP; ------------------------------------------------------------------------------- -- checkbit_handler.vhd - Entity and architecture ------------------------------------------------------------------------------- -- -- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES -- ------------------------------------------------------------------------------- -- Filename: gen_checkbits.vhd -- -- Description: -- -- VHDL-Standard: VHDL'93/02 ------------------------------------------------------------------------------- -- Structure: -- gen_checkbits.vhd -- ------------------------------------------------------------------------------- -- Author: goran ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library lmb_bram_if_cntlr_v4_0_10; use lmb_bram_if_cntlr_v4_0_10.all; use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all; entity checkbit_handler is generic ( C_TARGET : TARGET_FAMILY_TYPE; C_ENCODE : boolean := true); port ( DataIn : in std_logic_vector(0 to 31); CheckIn : in std_logic_vector(0 to 6); CheckOut : out std_logic_vector(0 to 6); Syndrome : out std_logic_vector(0 to 6); Enable_ECC : in std_logic; UE_Q : in std_logic; CE_Q : in std_logic; UE : out std_logic; CE : out std_logic ); end entity checkbit_handler; architecture IMP of checkbit_handler is component XOR18 is generic ( C_TARGET : TARGET_FAMILY_TYPE); port ( InA : in std_logic_vector(0 to 17); res : out std_logic); end component XOR18; component Parity is generic ( C_TARGET : TARGET_FAMILY_TYPE; C_SIZE : integer); port ( InA : in std_logic_vector(0 to C_SIZE - 1); Res : out std_logic); end component Parity; component ParityEnable generic ( C_TARGET : TARGET_FAMILY_TYPE; C_SIZE : integer); port ( InA : in std_logic_vector(0 to C_SIZE - 1); Enable : in std_logic; Res : out std_logic); end component ParityEnable; component MB_MUXF7 is generic ( C_TARGET : TARGET_FAMILY_TYPE ); port ( O : out std_logic; I0 : in std_logic; I1 : in std_logic; S : in std_logic ); end component MB_MUXF7; signal data_chk0 : std_logic_vector(0 to 17); signal data_chk1 : std_logic_vector(0 to 17); signal data_chk2 : std_logic_vector(0 to 17); signal data_chk3 : std_logic_vector(0 to 14); signal data_chk4 : std_logic_vector(0 to 14); signal data_chk5 : std_logic_vector(0 to 5); begin -- architecture IMP data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) & DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) & DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30); data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) & DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) & DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31); data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31); data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25); data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25); data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31); -- Encode bits for writing data Encode_Bits : if (C_ENCODE) generate signal data_chk3_i : std_logic_vector(0 to 17); signal data_chk4_i : std_logic_vector(0 to 17); signal data_chk6 : std_logic_vector(0 to 17); begin ------------------------------------------------------------------------------------------------ -- Checkbit 0 built up using XOR18 ------------------------------------------------------------------------------------------------ XOR18_I0 : XOR18 generic map ( C_TARGET => C_TARGET) port map ( InA => data_chk0, -- [in std_logic_vector(0 to 17)] res => CheckOut(0)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 1 built up using XOR18 ------------------------------------------------------------------------------------------------ XOR18_I1 : XOR18 generic map ( C_TARGET => C_TARGET) port map ( InA => data_chk1, -- [in std_logic_vector(0 to 17)] res => CheckOut(1)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 2 built up using XOR18 ------------------------------------------------------------------------------------------------ XOR18_I2 : XOR18 generic map ( C_TARGET => C_TARGET) port map ( InA => data_chk2, -- [in std_logic_vector(0 to 17)] res => CheckOut(2)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 3 built up using XOR18 ------------------------------------------------------------------------------------------------ data_chk3_i <= data_chk3 & "000"; XOR18_I3 : XOR18 generic map ( C_TARGET => C_TARGET) port map ( InA => data_chk3_i, -- [in std_logic_vector(0 to 17)] res => CheckOut(3)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 4 built up using XOR18 ------------------------------------------------------------------------------------------------ data_chk4_i <= data_chk4 & "000"; XOR18_I4 : XOR18 generic map ( C_TARGET => C_TARGET) port map ( InA => data_chk4_i, -- [in std_logic_vector(0 to 17)] res => CheckOut(4)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 5 built up from 1 LUT6 ------------------------------------------------------------------------------------------------ Parity_chk5_1 : Parity generic map ( C_TARGET => C_TARGET, C_SIZE => 6) port map ( InA => data_chk5, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => CheckOut(5)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 6 built up from 3 LUT7 and 4 LUT6 ------------------------------------------------------------------------------------------------ data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18) & DataIn(21) & DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29); XOR18_I6 : XOR18 generic map ( C_TARGET => C_TARGET) -- [boolean] port map ( InA => data_chk6, -- [in std_logic_vector(0 to 17)] res => CheckOut(6)); -- [out std_logic] -- Unused Syndrome <= (others => '0'); UE <= '0'; CE <= '0'; end generate Encode_Bits; -------------------------------------------------------------------------------------------------- -- Decode bits to get syndrome and UE/CE signals -------------------------------------------------------------------------------------------------- Decode_Bits : if (not C_ENCODE) generate signal syndrome_i : std_logic_vector(0 to 6); signal chk0_1 : std_logic_vector(0 to 3); signal chk1_1 : std_logic_vector(0 to 3); signal chk2_1 : std_logic_vector(0 to 3); signal data_chk3_i : std_logic_vector(0 to 15); signal chk3_1 : std_logic_vector(0 to 1); signal data_chk4_i : std_logic_vector(0 to 15); signal chk4_1 : std_logic_vector(0 to 1); signal data_chk5_i : std_logic_vector(0 to 6); signal data_chk6 : std_logic_vector(0 to 38); signal chk6_1 : std_logic_vector(0 to 5); signal syndrome_3_to_5 : std_logic_vector(3 to 5); signal syndrome_3_to_5_multi : std_logic; signal syndrome_3_to_5_zero : std_logic; signal ue_i_0 : std_logic; signal ue_i_1 : std_logic; begin ------------------------------------------------------------------------------------------------ -- Syndrome bit 0 built up from 3 LUT6 and 1 LUT4 ------------------------------------------------------------------------------------------------ chk0_1(3) <= CheckIn(0); Parity_chk0_1 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 6) port map ( InA => data_chk0(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk0_1(0)); -- [out std_logic] Parity_chk0_2 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 6) port map ( InA => data_chk0(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk0_1(1)); -- [out std_logic] Parity_chk0_3 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 6) port map ( InA => data_chk0(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk0_1(2)); -- [out std_logic] Parity_chk0_4 : ParityEnable generic map (C_TARGET => C_TARGET, C_SIZE => 4) port map ( InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Enable => Enable_ECC, -- [in std_logic] Res => syndrome_i(0)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 1 built up from 3 LUT6 and 1 LUT4 ------------------------------------------------------------------------------------------------ chk1_1(3) <= CheckIn(1); Parity_chk1_1 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 6) port map ( InA => data_chk1(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk1_1(0)); -- [out std_logic] Parity_chk1_2 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 6) port map ( InA => data_chk1(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk1_1(1)); -- [out std_logic] Parity_chk1_3 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 6) port map ( InA => data_chk1(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk1_1(2)); -- [out std_logic] Parity_chk1_4 : ParityEnable generic map (C_TARGET => C_TARGET, C_SIZE => 4) port map ( InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Enable => Enable_ECC, -- [in std_logic] Res => syndrome_i(1)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 2 built up from 3 LUT6 and 1 LUT4 ------------------------------------------------------------------------------------------------ chk2_1(3) <= CheckIn(2); Parity_chk2_1 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 6) port map ( InA => data_chk2(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk2_1(0)); -- [out std_logic] Parity_chk2_2 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 6) port map ( InA => data_chk2(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk2_1(1)); -- [out std_logic] Parity_chk2_3 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 6) port map ( InA => data_chk2(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk2_1(2)); -- [out std_logic] Parity_chk2_4 : ParityEnable generic map (C_TARGET => C_TARGET, C_SIZE => 4) port map ( InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Enable => Enable_ECC, -- [in std_logic] Res => syndrome_i(2)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 3 built up from 2 LUT8 and 1 LUT2 ------------------------------------------------------------------------------------------------ data_chk3_i <= data_chk3 & CheckIn(3); Parity_chk3_1 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 8) port map ( InA => data_chk3_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk3_1(0)); -- [out std_logic] Parity_chk3_2 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 8) port map ( InA => data_chk3_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk3_1(1)); -- [out std_logic] Parity_chk3_3 : ParityEnable generic map (C_TARGET => C_TARGET, C_SIZE => 2) port map ( InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Enable => Enable_ECC, -- [in std_logic] Res => syndrome_i(3)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 4 built up from 2 LUT8 and 1 LUT2 ------------------------------------------------------------------------------------------------ data_chk4_i <= data_chk4 & CheckIn(4); Parity_chk4_1 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 8) port map ( InA => data_chk4_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk4_1(0)); -- [out std_logic] Parity_chk4_2 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 8) port map ( InA => data_chk4_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk4_1(1)); -- [out std_logic] Parity_chk4_3 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 2) port map ( InA => chk4_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(4)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 5 built up from 1 LUT7 ------------------------------------------------------------------------------------------------ data_chk5_i <= data_chk5 & CheckIn(5); Parity_chk5_1 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 7) port map ( InA => data_chk5_i, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(5)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 6 built up from 3 LUT7 and 4 LUT6 ------------------------------------------------------------------------------------------------ data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(3) & DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31) & CheckIn(5) & CheckIn(4) & CheckIn(3) & CheckIn(2) & CheckIn(1) & CheckIn(0) & CheckIn(6); Parity_chk6_1 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 6) port map ( InA => data_chk6(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(0)); -- [out std_logic] Parity_chk6_2 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 6) port map ( InA => data_chk6(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(1)); -- [out std_logic] Parity_chk6_3 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 6) port map ( InA => data_chk6(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(2)); -- [out std_logic] Parity_chk6_4 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 7) port map ( InA => data_chk6(18 to 24), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(3)); -- [out std_logic] Parity_chk6_5 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 7) port map ( InA => data_chk6(25 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(4)); -- [out std_logic] Parity_chk6_6 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 7) port map ( InA => data_chk6(32 to 38), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(5)); -- [out std_logic] Parity_chk6_7 : Parity generic map (C_TARGET => C_TARGET, C_SIZE => 6) port map ( InA => chk6_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(6)); -- [out std_logic] Syndrome <= syndrome_i; syndrome_3_to_5 <= (chk3_1(0) xor chk3_1(1)) & (chk4_1(0) xor chk4_1(1)) & syndrome_i(5); syndrome_3_to_5_zero <= '1' when syndrome_3_to_5 = "000" else '0'; syndrome_3_to_5_multi <= '1' when (syndrome_3_to_5 = "111" or syndrome_3_to_5 = "011" or syndrome_3_to_5 = "101") else '0'; CE <= '0' when (Enable_ECC = '0') else (syndrome_i(6) or CE_Q) when (syndrome_3_to_5_multi = '0') else CE_Q; ue_i_0 <= '0' when (Enable_ECC = '0') else '1' when (syndrome_3_to_5_zero = '0') or (syndrome_i(0 to 2) /= "000") else UE_Q; ue_i_1 <= '0' when (Enable_ECC = '0') else (syndrome_3_to_5_multi or UE_Q); Use_FPGA: if (C_TARGET /= RTL) generate UE_MUXF7 : MB_MUXF7 generic map ( C_TARGET => C_TARGET) port map ( I0 => ue_i_0, I1 => ue_i_1, S => syndrome_i(6), O => UE); end generate Use_FPGA; Use_RTL: if (C_TARGET = RTL) generate UE <= ue_i_1 when syndrome_i(6) = '1' else ue_i_0; end generate Use_RTL; -- Unused CheckOut <= (others => '0'); end generate Decode_Bits; end architecture IMP; ------------------------------------------------------------------------------- -- correct_one_bit.vhd - Entity and architecture ------------------------------------------------------------------------------- -- -- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES -- ------------------------------------------------------------------------------ -- Filename: correct_one_bit.vhd -- -- Description: -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- correct_one_bit ------------------------------------------------------------------------------- -- Author: rolandp ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library lmb_bram_if_cntlr_v4_0_10; use lmb_bram_if_cntlr_v4_0_10.all; use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all; entity Correct_One_Bit is generic ( C_TARGET : TARGET_FAMILY_TYPE; Correct_Value : std_logic_vector(0 to 6)); port ( DIn : in std_logic; Syndrome : in std_logic_vector(0 to 6); DCorr : out std_logic); end entity Correct_One_Bit; architecture IMP of Correct_One_Bit is component MB_MUXCY is generic ( C_TARGET : TARGET_FAMILY_TYPE ); port ( LO : out std_logic; CI : in std_logic; DI : in std_logic; S : in std_logic ); end component MB_MUXCY; component MB_XORCY is generic ( C_TARGET : TARGET_FAMILY_TYPE ); port ( O : out std_logic; CI : in std_logic; LI : in std_logic ); end component MB_XORCY; ----------------------------------------------------------------------------- -- Find which bit that has a '1' -- There is always one bit which has a '1' ----------------------------------------------------------------------------- function find_one (Syn : std_logic_vector(0 to 6)) return natural is begin -- function find_one for I in 0 to 6 loop if (Syn(I) = '1') then return I; end if; end loop; -- I return 0; -- Should never reach this statement end function find_one; constant di_index : natural := find_one(Correct_Value); signal corr_sel : std_logic; signal corr_c : std_logic; signal lut_compare : std_logic_vector(0 to 5); signal lut_corr_val : std_logic_vector(0 to 5); begin -- architecture IMP Remove_DI_Index : process (Syndrome) is begin -- process Remove_DI_Index if (di_index = 0) then lut_compare <= Syndrome(1 to 6); lut_corr_val <= Correct_Value(1 to 6); elsif (di_index = 6) then lut_compare <= Syndrome(0 to 5); lut_corr_val <= Correct_Value(0 to 5); else lut_compare <= Syndrome(0 to di_index-1) & Syndrome(di_index+1 to 6); lut_corr_val <= Correct_Value(0 to di_index-1) & Correct_Value(di_index+1 to 6); end if; end process Remove_DI_Index; corr_sel <= '0' when lut_compare = lut_corr_val else '1'; Corr_MUXCY : MB_MUXCY generic map( C_TARGET => C_TARGET) port map ( DI => Syndrome(di_index), CI => '0', S => corr_sel, LO => corr_c); Corr_XORCY : MB_XORCY generic map( C_TARGET => C_TARGET) port map ( LI => DIn, CI => corr_c, O => DCorr); end architecture IMP; ------------------------------------------------------------------------------- -- pselect_mask.vhd - Entity and architecture ------------------------------------------------------------------------------- -- -- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES -- ------------------------------------------------------------------------------ -- Filename: pselect_mask.vhd -- -- Description: -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- pselect_mask.vhd -- ------------------------------------------------------------------------------- -- Author: goran ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity pselect_mask is generic ( C_AW : integer := 32; C_BAR : std_logic_vector(0 to 63) := X"0000000000020000"; C_MASK : std_logic_vector(0 to 63) := X"000000000007C000" ); port ( A : in std_logic_vector(0 to C_AW-1); Valid : in std_logic; CS : out std_logic ); end entity pselect_mask; architecture imp of pselect_mask is function Nr_Of_Ones (S : std_logic_vector) return natural is variable tmp : natural := 0; begin -- function Nr_Of_Ones for I in S'range loop if (S(I) = '1') then tmp := tmp + 1; end if; end loop; -- I return tmp; end function Nr_Of_Ones; function fix_AB (B : boolean; I : integer) return integer is begin -- function fix_AB if (not B) then return I + 1; else return I; end if; end function fix_AB; constant Nr : integer := Nr_Of_Ones(C_MASK(64 - C_AW to 63)); constant Use_CIN : boolean := ((Nr mod 4) = 0); constant AB : integer := fix_AB(Use_CIN, Nr); signal A_Bus : std_logic_vector(0 to AB); signal BAR : std_logic_vector(0 to AB); ------------------------------------------------------------------------------- -- Begin architecture section ------------------------------------------------------------------------------- begin -- VHDL_RTL Make_Busses : process (A,Valid) is variable tmp : natural; begin -- process Make_Busses tmp := 0; A_Bus <= (others => '0'); BAR <= (others => '0'); for I in 0 to C_AW - 1 loop if (C_MASK(64 - C_AW + I) = '1') then A_Bus(tmp) <= A(I); BAR(tmp) <= C_BAR(64 - C_AW + I); tmp := tmp + 1; end if; end loop; -- I if (not Use_CIN) then BAR(tmp) <= '1'; A_Bus(tmp) <= Valid; end if; end process Make_Busses; CS <= Valid when A_Bus=BAR else '0'; end imp; ------------------------------------------------------------------------------- -- axi_interface.vhd - Entity and architecture ------------------------------------------------------------------------------- -- -- (c) Copyright 2003-2015 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------- -- Filename: axi_interface.vhd -- -- Description: -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_interface.vhd -- ------------------------------------------------------------------------------- -- Author: rolandp ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library lmb_bram_if_cntlr_v4_0_10; use lmb_bram_if_cntlr_v4_0_10.all; use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all; entity axi_interface is generic ( C_TARGET : TARGET_FAMILY_TYPE; -- AXI4-Lite slave generics C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF"; C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000"; C_S_AXI_ADDR_WIDTH : integer := 32; C_S_AXI_DATA_WIDTH : integer := 32; C_REGADDR_WIDTH : integer := 5; -- Address bits including register offset. C_DWIDTH : integer := 32); -- Width of data bus. port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; -- AXI4-Lite SLAVE SINGLE INTERFACE S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; -- lmb_bram_if_cntlr signals RegWr : out std_logic; RegWrData : out std_logic_vector(0 to C_DWIDTH - 1); RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1); RegRdData : in std_logic_vector(0 to C_DWIDTH - 1)); end entity axi_interface; architecture IMP of axi_interface is component MB_FDRE is generic ( C_TARGET : TARGET_FAMILY_TYPE; INIT : bit := '0' ); port( Q : out std_logic; C : in std_logic; CE : in std_logic; D : in std_logic; R : in std_logic ); end component MB_FDRE; ----------------------------------------------------------------------------- -- Signal declaration ----------------------------------------------------------------------------- signal new_write_access : std_logic; signal new_read_access : std_logic; signal ongoing_write : std_logic; signal ongoing_read : std_logic; signal S_AXI_RVALID_i : std_logic; signal RegRdData_i : std_logic_vector(C_DWIDTH - 1 downto 0); begin -- architecture IMP ----------------------------------------------------------------------------- -- Handling the AXI4-Lite bus interface (AR/AW/W) ----------------------------------------------------------------------------- -- Detect new transaction. -- Only allow one access at a time new_write_access <= not (ongoing_read or ongoing_write) and S_AXI_AWVALID and S_AXI_WVALID; new_read_access <= not (ongoing_read or ongoing_write) and S_AXI_ARVALID and not new_write_access; -- Acknowledge new transaction. S_AXI_AWREADY <= new_write_access; S_AXI_WREADY <= new_write_access; S_AXI_ARREADY <= new_read_access; -- Store register address and write data Reg: process (LMB_Clk) is begin if LMB_Clk'event and LMB_Clk = '1' then if LMB_Rst = '1' then RegAddr <= (others => '0'); RegWrData <= (others => '0'); elsif new_write_access = '1' then RegAddr <= S_AXI_AWADDR(C_REGADDR_WIDTH-1+2 downto 2); RegWrData <= S_AXI_WDATA(C_DWIDTH-1 downto 0); elsif new_read_access = '1' then RegAddr <= S_AXI_ARADDR(C_REGADDR_WIDTH-1+2 downto 2); end if; end if; end process Reg; -- Handle write access. WriteAccess: process (LMB_Clk) is begin if LMB_Clk'event and LMB_Clk = '1' then if LMB_Rst = '1' then ongoing_write <= '0'; elsif new_write_access = '1' then ongoing_write <= '1'; elsif ongoing_write = '1' and S_AXI_BREADY = '1' then ongoing_write <= '0'; end if; RegWr <= new_write_access; end if; end process WriteAccess; S_AXI_BVALID <= ongoing_write; S_AXI_BRESP <= (others => '0'); -- Handle read access ReadAccess: process (LMB_Clk) is begin if LMB_Clk'event and LMB_Clk = '1' then if LMB_Rst = '1' then ongoing_read <= '0'; S_AXI_RVALID_i <= '0'; elsif new_read_access = '1' then ongoing_read <= '1'; S_AXI_RVALID_i <= '0'; elsif ongoing_read = '1' then if S_AXI_RREADY = '1' and S_AXI_RVALID_i = '1' then ongoing_read <= '0'; S_AXI_RVALID_i <= '0'; else S_AXI_RVALID_i <= '1'; -- Asserted one cycle after ongoing_read to match S_AXI_RDDATA end if; end if; end if; end process ReadAccess; S_AXI_RVALID <= S_AXI_RVALID_i; S_AXI_RRESP <= (others => '0'); Not_All_Bits_Are_Used: if (C_DWIDTH < C_S_AXI_DATA_WIDTH) generate begin S_AXI_RDATA(C_S_AXI_DATA_WIDTH-1 downto C_S_AXI_DATA_WIDTH - C_DWIDTH) <= (others=>'0'); end generate Not_All_Bits_Are_Used; RegRdData_i <= RegRdData; -- Swap to - downto S_AXI_RDATA_DFF : for I in C_DWIDTH - 1 downto 0 generate begin S_AXI_RDATA_FDRE : MB_FDRE generic map ( C_TARGET => C_TARGET) port map ( Q => S_AXI_RDATA(I), C => LMB_Clk, CE => ongoing_read, D => RegRdData_i(I), R => LMB_Rst); end generate S_AXI_RDATA_DFF; end architecture IMP; ------------------------------------------------------------------------------- -- lmb_mux.vhd - Entity and architecture ------------------------------------------------------------------------------- -- -- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES -- ------------------------------------------------------------------------------ -- Filename: lmb_mux.vhd -- -- Description: -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- lmb_mux.vhd -- pselct_mask.vhd -- ------------------------------------------------------------------------------- -- Author: rolandp ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity lmb_mux is generic ( C_BASEADDR : std_logic_vector(0 to 63) := X"FFFFFFFFFFFFFFFF"; C_MASK : std_logic_vector(0 to 63) := X"0000000000800000"; C_MASK1 : std_logic_vector(0 to 63) := X"0000000000800000"; C_MASK2 : std_logic_vector(0 to 63) := X"0000000000800000"; C_MASK3 : std_logic_vector(0 to 63) := X"0000000000800000"; C_LMB_AWIDTH : integer := 32; C_LMB_DWIDTH : integer := 32; C_NUM_LMB : integer := 1); port ( LMB_Clk : in std_logic := '0'; LMB_Rst : in std_logic := '0'; -- LMB Bus 0 LMB0_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB0_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB0_AddrStrobe : in std_logic; LMB0_ReadStrobe : in std_logic; LMB0_WriteStrobe : in std_logic; LMB0_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1)); Sl0_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl0_Ready : out std_logic; Sl0_Wait : out std_logic; Sl0_UE : out std_logic; Sl0_CE : out std_logic; -- LMB Bus 1 LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB1_AddrStrobe : in std_logic; LMB1_ReadStrobe : in std_logic; LMB1_WriteStrobe : in std_logic; LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1)); Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl1_Ready : out std_logic; Sl1_Wait : out std_logic; Sl1_UE : out std_logic; Sl1_CE : out std_logic; -- LMB Bus 2 LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB2_AddrStrobe : in std_logic; LMB2_ReadStrobe : in std_logic; LMB2_WriteStrobe : in std_logic; LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1)); Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl2_Ready : out std_logic; Sl2_Wait : out std_logic; Sl2_UE : out std_logic; Sl2_CE : out std_logic; -- LMB Bus 3 LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB3_AddrStrobe : in std_logic; LMB3_ReadStrobe : in std_logic; LMB3_WriteStrobe : in std_logic; LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1)); Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl3_Ready : out std_logic; Sl3_Wait : out std_logic; Sl3_UE : out std_logic; Sl3_CE : out std_logic; -- Muxed LMB Bus LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1); LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); LMB_AddrStrobe : out std_logic; LMB_ReadStrobe : out std_logic; LMB_WriteStrobe : out std_logic; LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1)); Sl_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); Sl_Ready : in std_logic; Sl_Wait : in std_logic; Sl_UE : in std_logic; Sl_CE : in std_logic; lmb_select : out std_logic); end entity lmb_mux; architecture imp of lmb_mux is component pselect_mask generic ( C_AW : integer := 32; C_BAR : std_logic_vector(0 to 63) := X"0000000000000000"; C_MASK : std_logic_vector(0 to 63) := X"0000000000800000"); port ( A : in std_logic_vector(0 to C_AW - 1); CS : out std_logic; Valid : in std_logic); end component; signal one : std_logic; ------------------------------------------------------------------------------- -- Begin architecture section ------------------------------------------------------------------------------- begin -- VHDL_RTL LMB1_no: if (C_NUM_LMB < 2) generate Sl1_DBus <= (others => '0'); Sl1_Ready <= '0'; Sl1_Wait <= '0'; Sl1_UE <= '0'; Sl1_CE <= '0'; end generate LMB1_no; LMB2_no: if (C_NUM_LMB < 3) generate Sl2_DBus <= (others => '0'); Sl2_Ready <= '0'; Sl2_Wait <= '0'; Sl2_UE <= '0'; Sl2_CE <= '0'; end generate LMB2_no; LMB3_no: if (C_NUM_LMB < 4) generate Sl3_DBus <= (others => '0'); Sl3_Ready <= '0'; Sl3_Wait <= '0'; Sl3_UE <= '0'; Sl3_CE <= '0'; end generate LMB3_no; one <= '1'; one_lmb: if (C_NUM_LMB = 1) generate begin ----------------------------------------------------------------------------- -- Do the LMB address decoding ----------------------------------------------------------------------------- pselect_mask_lmb : pselect_mask generic map ( C_AW => LMB_ABus'length, C_BAR => C_BASEADDR, C_MASK => C_MASK) port map ( A => LMB0_ABus, CS => lmb_select, Valid => one); LMB_ABus <= LMB0_ABus; LMB_WriteDBus <= LMB0_WriteDBus; LMB_AddrStrobe <= LMB0_AddrStrobe; LMB_ReadStrobe <= LMB0_ReadStrobe; LMB_WriteStrobe <= LMB0_WriteStrobe; LMB_BE <= LMB0_BE; Sl0_DBus <= Sl_DBus; Sl0_Ready <= Sl_Ready; Sl0_Wait <= Sl_Wait; Sl0_UE <= Sl_UE; Sl0_CE <= Sl_CE; end generate one_lmb; more_than_one_lmb: if (C_NUM_LMB > 1) generate type C_Mask_Vec_T is array (0 to 3) of std_logic_vector(0 to 63); constant C_Mask_Vec : C_MASK_Vec_T := (C_MASK, C_MASK1, C_MASK2, C_MASK3); type ABus_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_AWIDTH - 1); type DBus_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_DWIDTH - 1); type BE_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_DWIDTH/8 - 1); signal LMB_ABus_vec : ABus_vec_T; signal LMB_ABus_vec_i : ABus_vec_T; signal LMB_ABus_vec_Q : ABus_vec_T; signal LMB_WriteDBus_vec : DBus_vec_T; signal LMB_WriteDBus_vec_i : DBus_vec_T; signal LMB_WriteDBus_vec_Q : DBus_vec_T; signal LMB_AddrStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1); signal LMB_AddrStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1); signal LMB_AddrStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1); signal LMB_ReadStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1); signal LMB_ReadStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1); signal LMB_ReadStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1); signal LMB_WriteStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1); signal LMB_WriteStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1); signal LMB_WriteStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1); signal LMB_BE_vec : BE_vec_T; signal LMB_BE_vec_i : BE_vec_T; signal LMB_BE_vec_Q : BE_vec_T; signal Sl_DBus_vec : DBus_vec_T; signal Sl_Ready_vec : std_logic_vector(0 to C_NUM_LMB-1); signal Sl_Wait_vec : std_logic_vector(0 to C_NUM_LMB-1); signal Sl_UE_vec : std_logic_vector(0 to C_NUM_LMB-1); signal Sl_CE_vec : std_logic_vector(0 to C_NUM_LMB-1); signal wait_vec : std_logic_vector(0 to C_NUM_LMB-1); signal lmb_select_vec : std_logic_vector(0 to C_NUM_LMB-1); signal as_and_lmb_select_vec : std_logic_vector(0 to C_NUM_LMB-1); signal ongoing : natural range 0 to C_NUM_LMB-1; signal ongoing_new : natural range 0 to C_NUM_LMB-1; signal ongoing_Q : natural range 0 to C_NUM_LMB-1; begin LMB_ABus_vec(0) <= LMB0_ABus; LMB_WriteDBus_vec(0) <= LMB0_WriteDBus; LMB_AddrStrobe_vec(0) <= LMB0_AddrStrobe; LMB_ReadStrobe_vec(0) <= LMB0_ReadStrobe; LMB_WriteStrobe_vec(0) <= LMB0_WriteStrobe; LMB_BE_vec(0) <= LMB0_BE; Sl0_DBus <= Sl_DBus_vec(0); Sl0_Ready <= Sl_Ready_vec(0); Sl0_Wait <= Sl_Wait_vec(0); Sl0_UE <= Sl_UE_vec(0); Sl0_CE <= Sl_CE_vec(0); LMB_ABus_vec(1) <= LMB1_ABus; LMB_WriteDBus_vec(1) <= LMB1_WriteDBus; LMB_AddrStrobe_vec(1) <= LMB1_AddrStrobe; LMB_ReadStrobe_vec(1) <= LMB1_ReadStrobe; LMB_WriteStrobe_vec(1) <= LMB1_WriteStrobe; LMB_BE_vec(1) <= LMB1_BE; Sl1_DBus <= Sl_DBus_vec(1); Sl1_Ready <= Sl_Ready_vec(1); Sl1_Wait <= Sl_Wait_vec(1); Sl1_UE <= Sl_UE_vec(1); Sl1_CE <= Sl_CE_vec(1); LMB2_yes: if (C_NUM_LMB > 2) generate LMB_ABus_vec(2) <= LMB2_ABus; LMB_WriteDBus_vec(2) <= LMB2_WriteDBus; LMB_AddrStrobe_vec(2) <= LMB2_AddrStrobe; LMB_ReadStrobe_vec(2) <= LMB2_ReadStrobe; LMB_WriteStrobe_vec(2) <= LMB2_WriteStrobe; LMB_BE_vec(2) <= LMB2_BE; Sl2_DBus <= Sl_DBus_vec(2); Sl2_Ready <= Sl_Ready_vec(2); Sl2_Wait <= Sl_Wait_vec(2); Sl2_UE <= Sl_UE_vec(2); Sl2_CE <= Sl_CE_vec(2); end generate LMB2_yes; LMB3_yes: if (C_NUM_LMB > 3) generate LMB_ABus_vec(3) <= LMB3_ABus; LMB_WriteDBus_vec(3) <= LMB3_WriteDBus; LMB_AddrStrobe_vec(3) <= LMB3_AddrStrobe; LMB_ReadStrobe_vec(3) <= LMB3_ReadStrobe; LMB_WriteStrobe_vec(3) <= LMB3_WriteStrobe; LMB_BE_vec(3) <= LMB3_BE; Sl3_DBus <= Sl_DBus_vec(3); Sl3_Ready <= Sl_Ready_vec(3); Sl3_Wait <= Sl_Wait_vec(3); Sl3_UE <= Sl_UE_vec(3); Sl3_CE <= Sl_CE_vec(3); end generate LMB3_yes; lmb_mux_generate: for I in 0 to C_NUM_LMB-1 generate begin ----------------------------------------------------------------------------- -- Do the LMB address decoding ----------------------------------------------------------------------------- pselect_mask_lmb : pselect_mask generic map ( C_AW => LMB_ABus'length, C_BAR => C_BASEADDR, C_MASK => C_Mask_Vec(I)) port map ( A => LMB_ABus_vec(I), CS => lmb_select_vec(I), Valid => one); as_and_lmb_select_vec(I) <= lmb_select_vec(I) and LMB_AddrStrobe_vec(I); remember_access : process (LMB_Clk) is begin if (LMB_Clk'event and LMB_Clk = '1') then if (LMB_Rst = '1') then LMB_ABus_vec_Q(I) <= (others => '0'); LMB_WriteDBus_vec_Q(I) <= (others => '0'); LMB_AddrStrobe_vec_Q(I) <= '0'; LMB_ReadStrobe_vec_Q(I) <= '0'; LMB_WriteStrobe_vec_Q(I) <= '0'; LMB_BE_vec_Q(I) <= (others => '0'); elsif (as_and_lmb_select_vec(I) = '1' and ongoing /= I) then LMB_ABus_vec_Q(I) <= LMB_ABus_vec(I); LMB_WriteDBus_vec_Q(I) <= LMB_WriteDBus_vec(I); LMB_AddrStrobe_vec_Q(I) <= LMB_AddrStrobe_vec(I); LMB_ReadStrobe_vec_Q(I) <= LMB_ReadStrobe_vec(I); LMB_WriteStrobe_vec_Q(I) <= LMB_WriteStrobe_vec(I); LMB_BE_vec_Q(I) <= LMB_BE_vec(I); end if; end if; end process remember_access; wait_proc : process (LMB_Clk) is begin if (LMB_Clk'event and LMB_Clk = '1') then if (LMB_Rst = '1') then wait_vec(I) <= '0'; elsif (as_and_lmb_select_vec(I) = '1' and ongoing /= I) then wait_vec(I) <= '1'; elsif (wait_vec(I) = '1' and ongoing = I) then wait_vec(I) <= '0'; end if; end if; end process wait_proc; LMB_ABus_vec_i(I) <= LMB_ABus_vec_Q(I) when wait_vec(I) = '1' else LMB_ABus_vec(I); LMB_WriteDBus_vec_i(I) <= LMB_WriteDBus_vec_Q(I) when wait_vec(I) = '1' else LMB_WriteDBus_vec(I); LMB_AddrStrobe_vec_i(I) <= LMB_AddrStrobe_vec_Q(I) when wait_vec(I) = '1' else LMB_AddrStrobe_vec(I); LMB_ReadStrobe_vec_i(I) <= LMB_ReadStrobe_vec_Q(I) when wait_vec(I) = '1' else LMB_ReadStrobe_vec(I); LMB_WriteStrobe_vec_i(I) <= LMB_WriteStrobe_vec_Q(I) when wait_vec(I) = '1' else LMB_WriteStrobe_vec(I); LMB_BE_vec_i(I) <= LMB_BE_vec_Q(I) when wait_vec(I) = '1' else LMB_BE_vec(I); -- Assign selected LMB from internal signals Sl_DBus_vec(I) <= Sl_DBus; Sl_Ready_vec(I) <= Sl_Ready when ongoing_Q = I else '0'; Sl_Wait_vec(I) <= Sl_Wait when ongoing_Q = I else wait_vec(I); Sl_UE_vec(I) <= Sl_UE when ongoing_Q = I else '0'; Sl_CE_vec(I) <= Sl_CE when ongoing_Q = I else '0'; end generate lmb_mux_generate; OnGoing_Reg : process (LMB_Clk) is begin if (LMB_Clk'event and LMB_Clk = '1') then if (LMB_Rst = '1') then ongoing_Q <= 0; else ongoing_Q <= ongoing; end if; end if; end process OnGoing_Reg; Arbit : process (as_and_lmb_select_vec, wait_vec) is variable N : natural range 0 to C_NUM_LMB-1; begin ongoing_new <= 0; for N in 0 to C_NUM_LMB - 1 loop if as_and_lmb_select_vec(N) = '1' or wait_vec(N) = '1' then ongoing_new <= N; exit; end if; end loop; end process Arbit; ongoing <= ongoing_Q when Sl_Wait = '1' and Sl_Ready = '0' else ongoing_new; -- Assign selected LMB LMB_ABus <= LMB_ABus_vec_i(ongoing); LMB_WriteDBus <= LMB_WriteDBus_vec_i(ongoing); LMB_AddrStrobe <= LMB_AddrStrobe_vec_i(ongoing); LMB_ReadStrobe <= LMB_ReadStrobe_vec_i(ongoing); LMB_WriteStrobe <= LMB_WriteStrobe_vec_i(ongoing); LMB_BE <= LMB_BE_vec_i(ongoing); lmb_select <= lmb_select_vec(ongoing) or wait_vec(ongoing); end generate more_than_one_lmb; end imp; ------------------------------------------------------------------------------- -- lmb_bram_if_cntlr.vhd - Entity and architecture ------------------------------------------------------------------------------- -- -- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES -- ------------------------------------------------------------------------------ -- Filename: lmb_bram_if_cntlr.vhd -- -- Description: -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- lmb_bram_if_cntlr -- lmb_mux -- correct_one_bit -- xor18.vhd -- axi_interface ------------------------------------------------------------------------------- -- Author: rolandp ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library lmb_bram_if_cntlr_v4_0_10; use lmb_bram_if_cntlr_v4_0_10.all; entity lmb_bram_if_cntlr is generic ( C_FAMILY : string := "Virtex7"; C_HIGHADDR : std_logic_vector(0 to 63) := X"0000000000000000"; C_BASEADDR : std_logic_vector(0 to 63) := X"FFFFFFFFFFFFFFFF"; C_MASK : std_logic_vector(0 to 63) := X"0000000000800000"; C_MASK1 : std_logic_vector(0 to 63) := X"0000000000800000"; C_MASK2 : std_logic_vector(0 to 63) := X"0000000000800000"; C_MASK3 : std_logic_vector(0 to 63) := X"0000000000800000"; C_LMB_AWIDTH : integer := 32; C_LMB_DWIDTH : integer := 32; C_ECC : integer := 0; C_INTERCONNECT : integer := 1; C_FAULT_INJECT : integer := 0; C_CE_FAILING_REGISTERS : integer := 0; C_UE_FAILING_REGISTERS : integer := 0; C_ECC_STATUS_REGISTERS : integer := 0; C_ECC_ONOFF_REGISTER : integer := 0; C_ECC_ONOFF_RESET_VALUE : integer := 1; C_CE_COUNTER_WIDTH : integer := 0; C_WRITE_ACCESS : integer := 2; C_NUM_LMB : integer := 1; -- BRAM generic C_BRAM_AWIDTH : integer := 32; -- AXI generics C_S_AXI_CTRL_BASEADDR : std_logic_vector := X"FFFF_FFFF"; C_S_AXI_CTRL_HIGHADDR : std_logic_vector := X"0000_0000"; C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; C_S_AXI_CTRL_DATA_WIDTH : integer := 32); port ( LMB_Clk : in std_logic := '0'; LMB_Rst : in std_logic := '0'; -- LMB Bus LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB_AddrStrobe : in std_logic; LMB_ReadStrobe : in std_logic; LMB_WriteStrobe : in std_logic; LMB_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1)); Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl_Ready : out std_logic; Sl_Wait : out std_logic; Sl_UE : out std_logic; Sl_CE : out std_logic; -- Supplementary LMB Bus 1 LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB1_AddrStrobe : in std_logic; LMB1_ReadStrobe : in std_logic; LMB1_WriteStrobe : in std_logic; LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1)); Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl1_Ready : out std_logic; Sl1_Wait : out std_logic; Sl1_UE : out std_logic; Sl1_CE : out std_logic; -- Supplementary LMB Bus 2 LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB2_AddrStrobe : in std_logic; LMB2_ReadStrobe : in std_logic; LMB2_WriteStrobe : in std_logic; LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1)); Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl2_Ready : out std_logic; Sl2_Wait : out std_logic; Sl2_UE : out std_logic; Sl2_CE : out std_logic; -- Supplementary LMB Bus 3 LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB3_AddrStrobe : in std_logic; LMB3_ReadStrobe : in std_logic; LMB3_WriteStrobe : in std_logic; LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1)); Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl3_Ready : out std_logic; Sl3_Wait : out std_logic; Sl3_UE : out std_logic; Sl3_CE : out std_logic; -- ports to data memory block BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_Addr_A : out std_logic_vector(0 to C_BRAM_AWIDTH-1); BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to (C_LMB_DWIDTH+8*C_ECC)/8-1); BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1); BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1); -- AXI Interface S_AXI_CTRL_ACLK : in std_logic; S_AXI_CTRL_ARESETN : in std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); S_AXI_CTRL_WSTRB : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH/8)-1 downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic; -- Interrupt and error signals UE : out std_logic; CE : out std_logic; Interrupt : out std_logic); end lmb_bram_if_cntlr; library lmb_bram_if_cntlr_v4_0_10; use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all; architecture imp of lmb_bram_if_cntlr is ------------------------------------------------------------------------------ -- component declarations ------------------------------------------------------------------------------ component lmb_mux is generic ( C_BASEADDR : std_logic_vector(0 to 63) := X"FFFFFFFFFFFFFFFF"; C_MASK : std_logic_vector(0 to 63) := X"0000000000800000"; C_MASK1 : std_logic_vector(0 to 63) := X"0000000000800000"; C_MASK2 : std_logic_vector(0 to 63) := X"0000000000800000"; C_MASK3 : std_logic_vector(0 to 63) := X"0000000000800000"; C_LMB_AWIDTH : integer := 32; C_LMB_DWIDTH : integer := 32; C_NUM_LMB : integer := 1); port ( LMB_Clk : in std_logic := '0'; LMB_Rst : in std_logic := '0'; -- LMB Bus 0 LMB0_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB0_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB0_AddrStrobe : in std_logic; LMB0_ReadStrobe : in std_logic; LMB0_WriteStrobe : in std_logic; LMB0_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1)); Sl0_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl0_Ready : out std_logic; Sl0_Wait : out std_logic; Sl0_UE : out std_logic; Sl0_CE : out std_logic; -- LMB Bus 1 LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB1_AddrStrobe : in std_logic; LMB1_ReadStrobe : in std_logic; LMB1_WriteStrobe : in std_logic; LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1)); Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl1_Ready : out std_logic; Sl1_Wait : out std_logic; Sl1_UE : out std_logic; Sl1_CE : out std_logic; -- LMB Bus 2 LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB2_AddrStrobe : in std_logic; LMB2_ReadStrobe : in std_logic; LMB2_WriteStrobe : in std_logic; LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1)); Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl2_Ready : out std_logic; Sl2_Wait : out std_logic; Sl2_UE : out std_logic; Sl2_CE : out std_logic; -- LMB Bus 3 LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); LMB3_AddrStrobe : in std_logic; LMB3_ReadStrobe : in std_logic; LMB3_WriteStrobe : in std_logic; LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1)); Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); Sl3_Ready : out std_logic; Sl3_Wait : out std_logic; Sl3_UE : out std_logic; Sl3_CE : out std_logic; -- Muxed LMB Bus LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1); LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1); LMB_AddrStrobe : out std_logic; LMB_ReadStrobe : out std_logic; LMB_WriteStrobe : out std_logic; LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1)); Sl_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1); Sl_Ready : in std_logic; Sl_Wait : in std_logic; Sl_UE : in std_logic; Sl_CE : in std_logic; lmb_select : out std_logic); end component lmb_mux; component axi_interface generic ( C_TARGET : TARGET_FAMILY_TYPE; C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF"; C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000"; C_S_AXI_ADDR_WIDTH : integer := 32; C_S_AXI_DATA_WIDTH : integer := 32; C_REGADDR_WIDTH : integer := 5; -- Address bits including register offset. C_DWIDTH : integer := 32); -- Width of data bus. port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; RegWr : out std_logic; RegWrData : out std_logic_vector(0 to C_DWIDTH - 1); RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1); RegRdData : in std_logic_vector(0 to C_DWIDTH - 1)); end component; component checkbit_handler is generic ( C_TARGET : TARGET_FAMILY_TYPE; C_ENCODE : boolean); port ( DataIn : in std_logic_vector(0 to 31); CheckIn : in std_logic_vector(0 to 6); CheckOut : out std_logic_vector(0 to 6); Syndrome : out std_logic_vector(0 to 6); Enable_ECC : in std_logic; UE_Q : in std_logic; CE_Q : in std_logic; UE : out std_logic; CE : out std_logic); end component checkbit_handler; component Correct_One_Bit generic ( C_TARGET : TARGET_FAMILY_TYPE; Correct_Value : std_logic_vector(0 to 6)); port ( DIn : in std_logic; Syndrome : in std_logic_vector(0 to 6); DCorr : out std_logic); end component Correct_One_Bit; constant C_TARGET : TARGET_FAMILY_TYPE := String_To_Family(C_FAMILY, false); constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1; constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1; constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1; constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1; constant C_HAS_ECC_ONOFF_REGISTER : boolean := C_ECC_ONOFF_REGISTER = 1; constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0; constant C_BUS_NEEDED : boolean := C_HAS_FAULT_INJECT or C_HAS_CE_FAILING_REGISTERS or C_HAS_UE_FAILING_REGISTERS or C_HAS_ECC_STATUS_REGISTERS or C_HAS_ECC_ONOFF_REGISTER or C_HAS_CE_COUNTER; constant C_AXI : integer := 2; constant C_HAS_AXI : boolean := C_ECC = 1 and C_INTERCONNECT = C_AXI and C_BUS_NEEDED; constant C_ECC_WIDTH : integer := 7; -- Intermediate signals to handle multiple LMB ports signal LMB_ABus_i : std_logic_vector(0 to C_LMB_AWIDTH-1); signal LMB_WriteDBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1); signal LMB_AddrStrobe_i : std_logic; signal LMB_ReadStrobe_i : std_logic; signal LMB_WriteStrobe_i : std_logic; signal LMB_BE_i : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1)); signal Sl_DBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1); signal Sl_Ready_i : std_logic; signal Sl_Wait_i : std_logic; signal Sl_UE_i : std_logic; signal Sl_CE_i : std_logic; signal lmb_select : std_logic; signal lmb_as : std_logic; signal lmb_we : std_logic_vector(0 to 3); signal Sl_Rdy : std_logic; signal bram_din_a_i : std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1); begin assert C_LMB_AWIDTH >= C_BRAM_AWIDTH report "C_LMB_AWIDTH must be greater than or equal to C_BRAM_AWIDTH" severity failure; ----------------------------------------------------------------------------- -- Cleaning incoming data from BRAM from 'U' for simulation purpose -- This is added since simulation model for BRAM will not initialize -- undefined memory locations with zero. -- Added as a work-around until this is fixed in the simulation model. ----------------------------------------------------------------------------- Cleaning_machine: process (BRAM_Din_A) is begin -- process Cleaning_machine -- Default assignments bram_din_a_i <= BRAM_Din_A; -- pragma translate_off bram_din_a_i <= To_StdLogicVector(To_bitvector(BRAM_Din_A)); -- pragma translate_on end process Cleaning_machine; lmb_mux_I : lmb_mux generic map ( C_BASEADDR => C_BASEADDR, C_MASK => C_MASK, C_MASK1 => C_MASK1, C_MASK2 => C_MASK2, C_MASK3 => C_MASK3, C_LMB_AWIDTH => C_LMB_AWIDTH, C_LMB_DWIDTH => C_LMB_DWIDTH, C_NUM_LMB => C_NUM_LMB) port map ( LMB_Clk => LMB_Clk, LMB_Rst => LMB_Rst, LMB0_ABus => LMB_ABus, LMB0_WriteDBus => LMB_WriteDBus, LMB0_AddrStrobe => LMB_AddrStrobe, LMB0_ReadStrobe => LMB_ReadStrobe, LMB0_WriteStrobe => LMB_WriteStrobe, LMB0_BE => LMB_BE, Sl0_DBus => Sl_DBus, Sl0_Ready => Sl_Ready, Sl0_Wait => Sl_Wait, Sl0_UE => Sl_UE, Sl0_CE => Sl_CE, LMB1_ABus => LMB1_ABus, LMB1_WriteDBus => LMB1_WriteDBus, LMB1_AddrStrobe => LMB1_AddrStrobe, LMB1_ReadStrobe => LMB1_ReadStrobe, LMB1_WriteStrobe => LMB1_WriteStrobe, LMB1_BE => LMB1_BE, Sl1_DBus => Sl1_DBus, Sl1_Ready => Sl1_Ready, Sl1_Wait => Sl1_Wait, Sl1_UE => Sl1_UE, Sl1_CE => Sl1_CE, LMB2_ABus => LMB2_ABus, LMB2_WriteDBus => LMB2_WriteDBus, LMB2_AddrStrobe => LMB2_AddrStrobe, LMB2_ReadStrobe => LMB2_ReadStrobe, LMB2_WriteStrobe => LMB2_WriteStrobe, LMB2_BE => LMB2_BE, Sl2_DBus => Sl2_DBus, Sl2_Ready => Sl2_Ready, Sl2_Wait => Sl2_Wait, Sl2_UE => Sl2_UE, Sl2_CE => Sl2_CE, LMB3_ABus => LMB3_ABus, LMB3_WriteDBus => LMB3_WriteDBus, LMB3_AddrStrobe => LMB3_AddrStrobe, LMB3_ReadStrobe => LMB3_ReadStrobe, LMB3_WriteStrobe => LMB3_WriteStrobe, LMB3_BE => LMB3_BE, Sl3_DBus => Sl3_DBus, Sl3_Ready => Sl3_Ready, Sl3_Wait => Sl3_Wait, Sl3_UE => Sl3_UE, Sl3_CE => Sl3_CE, LMB_ABus => LMB_ABus_i, LMB_WriteDBus => LMB_WriteDBus_i, LMB_AddrStrobe => LMB_AddrStrobe_i, LMB_ReadStrobe => LMB_ReadStrobe_i, LMB_WriteStrobe => LMB_WriteStrobe_i, LMB_BE => LMB_BE_i, Sl_DBus => Sl_DBus_i, Sl_Ready => Sl_Ready_i, Sl_Wait => Sl_Wait_i, Sl_UE => Sl_UE_i, Sl_CE => Sl_CE_i, lmb_select => lmb_select); BRAM_Rst_A <= '0'; BRAM_Clk_A <= LMB_Clk; lmb_we(0) <= LMB_BE_i(0) and LMB_WriteStrobe_i and lmb_select; lmb_we(1) <= LMB_BE_i(1) and LMB_WriteStrobe_i and lmb_select; lmb_we(2) <= LMB_BE_i(2) and LMB_WriteStrobe_i and lmb_select; lmb_we(3) <= LMB_BE_i(3) and LMB_WriteStrobe_i and lmb_select; No_ECC : if (C_ECC = 0) generate begin BRAM_EN_A <= LMB_AddrStrobe_i; BRAM_WEN_A <= lmb_we; BRAM_Dout_A <= LMB_WriteDBus_i; Sl_DBus_i <= bram_din_a_i; BRAM_Addr_A <= LMB_ABus_i(C_LMB_AWIDTH - C_BRAM_AWIDTH to C_LMB_AWIDTH - 1); -- only used wen ECC enabled, tie to constant inactive Sl_Wait_i <= '0'; Sl_UE_i <= '0'; Sl_CE_i <= '0'; UE <= '0'; CE <= '0'; Interrupt <= '0'; ----------------------------------------------------------------------------- -- Writes are pipelined in MB with 5 stage pipeline ----------------------------------------------------------------------------- Ready_Handling : process (LMB_Clk) is begin if (LMB_Clk'event and LMB_Clk = '1') then if (LMB_Rst = '1') then Sl_Rdy <= '0'; lmb_as <= '0'; else Sl_Rdy <= lmb_select; lmb_as <= LMB_AddrStrobe_i; end if; end if; end process Ready_Handling; Sl_Ready_i <= Sl_Rdy and lmb_as; end generate No_ECC; ECC : if (C_ECC = 1) generate constant NO_WRITES : integer := 0; constant ONLY_WORD : integer := 1; constant ALL_WRITES : integer := 2; signal enable_ecc : std_logic; -- On/Off Register constant C_ECC_ONOFF : natural := 31; constant C_ECC_ONOFF_WIDTH : natural := 1; signal ECC_EnableCheckingReg : std_logic_vector(32-C_ECC_ONOFF_WIDTH to 31); -- Fault Inject Registers signal FaultInjectData : std_logic_vector(0 to C_LMB_DWIDTH-1); signal FaultInjectECC : std_logic_vector(32-C_ECC_WIDTH to 31); -- Signals for read modify write operation when byte/half-word write signal write_access : std_logic; signal full_word_write_access : std_logic; signal IsWordWrite : std_logic; signal RdModifyWr_Read : std_logic; -- Read cycle in read modify write sequence signal RdModifyWr_Modify : std_logic; -- Modify cycle in read modify write sequence signal RdModifyWr_Modify_i : std_logic; -- Modify cycle in read modify write sequence signal RdModifyWr_Write : std_logic; -- Write cycle in read modify write sequence signal LMB_ABus_Q : std_logic_vector(0 to C_LMB_AWIDTH-1); -- Read ECC signal Syndrome : std_logic_vector(0 to C_ECC_WIDTH-1); signal CorrectedRdData : std_logic_vector(0 to C_LMB_DWIDTH-1); signal CorrectedRdData_Q : std_logic_vector(0 to C_LMB_DWIDTH-1); signal CE_Q : std_logic; signal UE_Q : std_logic; -- Enable and address same for both data and ECC BRAM signal bram_en : std_logic; signal bram_addr : std_logic_vector(0 to C_LMB_AWIDTH-1); subtype syndrome_bits is std_logic_vector(0 to 6); type correct_data_table_type is array(natural range 0 to 31) of syndrome_bits; constant correct_data_table : correct_data_table_type := ( 0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001", 4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001", 8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101", 12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101", 16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101", 20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101", 24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011", 28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011" ); type bool_array is array (natural range 0 to 6) of boolean; constant inverted_bit : bool_array := (false,false,true,false,true,false,false); begin assert C_LMB_DWIDTH = 32 report "C_LMB_DWIDTH must be 32 when C_ECC = 1" severity failure; -- Enable BRAMs when access on LMB and in the second cycle in a read/modify write bram_en <= '1' when LMB_AddrStrobe_i = '1' or RdModifyWr_Write = '1' else '0'; BRAM_EN_A <= bram_en; IsWordWrite <= LMB_WriteStrobe_i when (LMB_BE_i = "1111") else '0'; -- ECC checking enable during access and when checking is turned on enable_ecc <= ECC_EnableCheckingReg(C_ECC_ONOFF) and Sl_Wait_i and not(full_word_write_access); ----------------------------------------------------------------------------- -- Writes are pipelined in MB with 5 stage pipeline ----------------------------------------------------------------------------- Ready_Handling : process (LMB_Clk) is begin if (LMB_Clk'event and LMB_Clk = '1') then if (LMB_Rst = '1') then Sl_Rdy <= '0'; lmb_as <= '0'; else -- Directly drive ready on valid read access or on valid word write access -- otherwise drive ready when we have written the new data on a -- readmodifywrite sequence Sl_Rdy <= ((LMB_AddrStrobe_i and lmb_select) and (LMB_ReadStrobe_i or IsWordWrite)) or RdModifyWr_Write; lmb_as <= LMB_AddrStrobe_i; end if; end if; end process Ready_Handling; Sl_Ready_i <= Sl_Rdy; Wait_Handling: process (LMB_Clk) is begin -- process Wait_Handling if (LMB_Clk'event and LMB_Clk = '1') then -- rising clock edge if (LMB_Rst = '1') then Sl_Wait_i <= '0'; elsif (LMB_AddrStrobe_i = '1') then Sl_Wait_i <= lmb_select; elsif (Sl_Rdy = '1') then Sl_Wait_i <= '0'; end if; end if; end process Wait_Handling; -- Generate ECC bits for checking data read from BRAM checkbit_handler_I1 : checkbit_handler generic map ( C_TARGET => C_TARGET, C_ENCODE => false) -- [boolean] port map ( DataIn => bram_din_a_i(0 to 31), -- [in std_logic_vector(0 to 31)] CheckIn => bram_din_a_i(33 to 39), -- [in std_logic_vector(0 to 6)] CheckOut => open, -- [out std_logic_vector(0 to 6)] Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)] Enable_ECC => enable_ecc, -- [in std_logic] UE_Q => UE_Q, -- [in std_logic] CE_Q => CE_Q, -- [in std_logic] UE => Sl_UE_i, -- [out std_logic] CE => Sl_CE_i); -- [out std_logic] -- Discrete error signals UE <= Sl_UE_i and Sl_Ready_i; CE <= Sl_CE_i and Sl_Ready_i; -- Correct Data Gen_Correct_Data: for I in 0 to 31 generate Correct_One_Bit_I : Correct_One_Bit generic map ( C_TARGET => C_TARGET, Correct_Value => correct_data_table(I)) port map ( DIn => bram_din_a_i(I), Syndrome => Syndrome, DCorr => CorrectedRdData(I)); end generate Gen_Correct_Data; -- Drive corrected read data on LMB Sl_DBus_i <= CorrectedRdData; -- Remember address and writestrobe AddressReg : process(LMB_Clk) is begin if (LMB_Clk'event and LMB_Clk = '1') then if LMB_Rst = '1' then LMB_ABus_Q <= (others => '0'); write_access <= '0'; full_word_write_access <= '0'; elsif LMB_AddrStrobe_i = '1' then LMB_ABus_Q <= LMB_ABus_i; write_access <= LMB_WriteStrobe_i; full_word_write_access <= LMB_BE_i(0) and LMB_BE_i(1) and LMB_BE_i(2) and LMB_BE_i(3) and LMB_WriteStrobe_i; end if; end if; end process AddressReg; bram_addr <= LMB_ABus_Q when RdModifyWr_Write = '1' else LMB_ABus_i; BRAM_Addr_A <= bram_addr(C_LMB_AWIDTH - C_BRAM_AWIDTH to C_LMB_AWIDTH - 1); Do_Writes : if (C_WRITE_ACCESS /= NO_WRITES) generate signal WrData : std_logic_vector(0 to C_LMB_DWIDTH-1); signal WrECC : std_logic_vector(0 to C_ECC_WIDTH-1); constant null7 : std_logic_vector(0 to 6) := "0000000"; begin DO_BYTE_HALFWORD_WRITES : if (C_WRITE_ACCESS = ALL_WRITES) generate signal wrdata_i : std_logic_vector(0 to C_LMB_DWIDTH-1); signal writeDBus_Q : std_logic_vector(0 to C_LMB_DWIDTH-1); signal lmb_be_q : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1)); begin -- Remember correctable/uncorrectable error from read in read modify write CorrReg : process(LMB_Clk) is begin if (LMB_Clk'event and LMB_Clk = '1') then if RdModifyWr_Modify = '1' then -- Remember error signals CE_Q <= Sl_CE_i; UE_Q <= Sl_UE_i; elsif RdModifyWr_Write = '1' then -- Keep the signals one more cycle CE_Q <= CE_Q; UE_Q <= UE_Q; else CE_Q <= '0'; UE_Q <= '0'; end if; end if; end process CorrReg; -- Remember byte write enables one clock cycle to properly mux bytes to write, -- with read data in read/modify write operation -- Write in Read/Write always 1 cycle after Read StoreLMB_WE : process(LMB_Clk) is begin if (LMB_Clk'event and LMB_Clk = '1') then RdModifyWr_Modify_i <= RdModifyWr_Read; RdModifyWr_Write <= RdModifyWr_Modify; CorrectedRdData_Q <= CorrectedRdData; end if; end process StoreLMB_WE; RdModifyWr_Modify <= RdModifyWr_Modify_i and lmb_as; RdModifyWr_Read <= '1' when lmb_we /= "1111" and lmb_we /= "0000" and (C_WRITE_ACCESS = ALL_WRITES) else '0'; -- Remember write data one cycle to be available after read has been completed in a -- read/modify write operation StoreWriteDBus : process(LMB_Clk) is begin if (LMB_Clk'event and LMB_Clk = '1') then if (LMB_Rst = '1') then WriteDBus_Q <= (others => '0'); lmb_be_q <= (others => '0'); elsif (LMB_AddrStrobe_i = '1') then WriteDBus_Q <= LMB_WriteDBus_i; lmb_be_q <= LMB_BE_i; end if; end if; end process StoreWriteDBus; wrdata_i <= WriteDBus_Q when RdModifyWr_Write = '1' else LMB_WriteDBus_i; -- Select BRAM data to write from LMB on 32-bit word access or a mix of -- read data and LMB write data for read/modify write operations WrData(0 to 7) <= wrdata_i(0 to 7) when ((RdModifyWr_Write = '0' and LMB_BE_i(0) = '1') or (RdModifyWr_Write = '1' and lmb_be_q(0) = '1')) else CorrectedRdData_Q(0 to 7); WrData(8 to 15) <= wrdata_i(8 to 15) when ((RdModifyWr_Write = '0' and LMB_BE_i(1) = '1') or (RdModifyWr_Write = '1' and lmb_be_q(1) = '1')) else CorrectedRdData_Q(8 to 15); WrData(16 to 23) <= wrdata_i(16 to 23) when ((RdModifyWr_Write = '0' and LMB_BE_i(2) = '1') or (RdModifyWr_Write = '1' and lmb_be_q(2) = '1')) else CorrectedRdData_Q(16 to 23); WrData(24 to 31) <= wrdata_i(24 to 31) when ((RdModifyWr_Write = '0' and LMB_BE_i(3) = '1') or (RdModifyWr_Write = '1' and lmb_be_q(3) = '1')) else CorrectedRdData_Q(24 to 31); end generate DO_BYTE_HALFWORD_WRITES; DO_Only_Word_Writes : if (C_WRITE_ACCESS = ONLY_WORD) generate RdModifyWr_Write <= '0'; RdModifyWr_Read <= '0'; RdModifyWr_Modify <= '0'; CorrectedRdData_Q <= (others => '0'); WrData <= LMB_WriteDBus_i; CE_Q <= '0'; UE_Q <= '0'; end generate DO_Only_Word_Writes; -- Generate BRAM WEN, which will always be all 1's due to read modify write -- for non 32-bit word access WrDataSel : process(IsWordWrite, lmb_select, RdModifyWr_Modify, RdModifyWr_Write, UE_Q) begin if (RdModifyWr_Modify = '1') then BRAM_WEN_A <= (others => '0'); elsif (RdModifyWr_Write = '1') then if (UE_Q = '0') then BRAM_WEN_A <= (others => '1'); -- byte or half word write, and not UE else BRAM_WEN_A <= (others => '0'); end if; elsif (IsWordWrite = '1') then -- word write BRAM_WEN_A <= (others => lmb_select); else BRAM_WEN_A <= (others => '0'); end if; end process WrDataSel; -- Generate ECC bits for writing into BRAM checkbit_handler_I2 : checkbit_handler generic map ( C_TARGET => C_TARGET, C_ENCODE => true) -- [boolean] port map ( DataIn => WrData, -- [in std_logic_vector(0 to 31)] CheckIn => null7, -- [in std_logic_vector(0 to 6)] CheckOut => WrECC, -- [out std_logic_vector(0 to 6)] Syndrome => open, -- [out std_logic_vector(0 to 6)] Enable_ECC => '1', -- [in std_logic] UE_Q => '0', -- [in std_logic] CE_Q => '0', -- [in std_logic] UE => open, -- [out std_logic] CE => open); -- [out std_logic] -- Drive BRAM write data and inject fault if applicable BRAM_Dout_A(0 to 31) <= WrData xor FaultInjectData; BRAM_Dout_A(32 to 39) <= ('0' & WrECC) xor ('0' & FaultInjectECC); end generate Do_Writes; No_Write_Accesses : if (C_WRITE_ACCESS = NO_WRITES) generate RdModifyWr_Write <= '0'; RdModifyWr_Read <= '0'; RdModifyWr_Modify <= '0'; CorrectedRdData_Q <= (others => '0'); FaultInjectData <= (others => '0'); FaultInjectECC <= (others => '0'); CE_Q <= '0'; UE_Q <= '0'; BRAM_WEN_A <= (others => '0'); BRAM_Dout_A <= (others => '0'); end generate No_Write_Accesses; Has_AXI : if C_HAS_AXI generate -- Register accesses -- Register addresses use word address, i.e 2 LSB don't care -- Don't decode MSB, i.e. mirroring of registers in address space of module -- Don't decode unmapped addresses -- Data registers occupy 32 words to accommodate up to 1024-bit words in other IPs -- ECC registers occupy 16 words to accomodate up to 512-bit ECC in other IPs -- Address registers occupy 2 words to accommodate 64-bit address in other IPs constant C_REGADDR_WIDTH : integer := 8; constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x000 ECC_STATUS constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x004 ECC_EN_IRQ constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x008 ECC_ONOFF constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0x00C CE_CNT constant C_CE_FailingData : std_logic_vector := "01000000"; -- 0x100 CE_FFD[31:0] constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 CE_FFE constant C_CE_FailingAddress : std_logic_vector := "01110000"; -- 0x1C0 CE_FFA[31:0] constant C_UE_FailingData : std_logic_vector := "10000000"; -- 0x200 UE_FFD[31:0] constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 UE_FFE constant C_UE_FailingAddress : std_logic_vector := "10110000"; -- 0x2C0 UE_FFA[31:0] constant C_FaultInjectData : std_logic_vector := "11000000"; -- 0x300 FI_D[31:0] constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 FI_ECC -- ECC Status register bit positions constant C_ECC_STATUS_CE : natural := 30; constant C_ECC_STATUS_UE : natural := 31; constant C_ECC_STATUS_WIDTH : natural := 2; constant C_ECC_ENABLE_IRQ_CE : natural := 30; constant C_ECC_ENABLE_IRQ_UE : natural := 31; constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2; -- Read and write data to internal registers constant C_DWIDTH : integer := 32; signal RegWrData : std_logic_vector(0 to C_DWIDTH-1); signal RegRdData : std_logic_vector(0 to C_DWIDTH-1); signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1); signal RegWr : std_logic; -- Correctable Error First Failing Register signal CE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1); signal CE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1); signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31); -- Uncorrectable Error First Failing Register signal UE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1); signal UE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1); signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31); -- ECC Status and Control register signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31); signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31); -- Correctable Error Counter signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31); signal sample_registers : std_logic; begin sample_registers <= lmb_as and not full_word_write_access; -- Implement fault injection registers Fault_Inject : if C_HAS_FAULT_INJECT and (C_WRITE_ACCESS /= NO_WRITES) generate begin FaultInjectDataReg : process(LMB_Clk) is begin if LMB_Clk'event and LMB_Clk = '1' then if LMB_Rst = '1' then FaultInjectData <= (others => '0'); FaultInjectECC <= (others => '0'); elsif RegWr = '1' and RegAddr = C_FaultInjectData then FaultInjectData <= RegWrData; elsif RegWr = '1' and RegAddr = C_FaultInjectECC then FaultInjectECC <= RegWrData(FaultInjectECC'range); elsif (Sl_Rdy = '1') and (write_access = '1') then -- One shoot, clear after first LMB write FaultInjectData <= (others => '0'); FaultInjectECC <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate Fault_Inject; No_Fault_Inject : if not C_HAS_FAULT_INJECT or (C_WRITE_ACCESS = NO_WRITES) generate begin FaultInjectData <= (others => '0'); FaultInjectECC <= (others => '0'); end generate No_Fault_Inject; -- Implement Correctable Error First Failing Register CE_Failing_Registers : if C_HAS_CE_FAILING_REGISTERS generate begin CE_FailingReg : process(LMB_Clk) is begin if LMB_Clk'event and LMB_Clk = '1' then if LMB_Rst = '1' then CE_FailingAddress <= (others => '0'); CE_FailingData <= (others => '0'); CE_FailingECC <= (others => '0'); elsif Sl_CE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0' then CE_FailingAddress <= LMB_ABus_Q; CE_FailingData <= bram_din_a_i(CE_FailingData'range); CE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1); end if; end if; end process CE_FailingReg; end generate CE_Failing_Registers; No_CE_Failing_Registers : if not C_HAS_CE_FAILING_REGISTERS generate begin CE_FailingAddress <= (others => '0'); CE_FailingData <= (others => '0'); CE_FailingECC <= (others => '0'); end generate No_CE_Failing_Registers; -- Implement Unorrectable Error First Failing Register UE_Failing_Registers : if C_HAS_UE_FAILING_REGISTERS generate begin UE_FailingReg : process(LMB_Clk) is begin if LMB_Clk'event and LMB_Clk = '1' then if LMB_Rst = '1' then UE_FailingAddress <= (others => '0'); UE_FailingData <= (others => '0'); UE_FailingECC <= (others => '0'); elsif Sl_UE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0' then UE_FailingAddress <= LMB_ABus_Q; UE_FailingData <= bram_din_a_i(UE_FailingData'range); UE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1); end if; end if; end process UE_FailingReg; end generate UE_Failing_Registers; No_UE_Failing_Registers : if not C_HAS_UE_FAILING_REGISTERS generate begin UE_FailingAddress <= (others => '0'); UE_FailingData <= (others => '0'); UE_FailingECC <= (others => '0'); end generate No_UE_Failing_Registers; ECC_Status_Registers : if C_HAS_ECC_STATUS_REGISTERS generate begin StatusReg : process(LMB_Clk) is begin if LMB_Clk'event and LMB_Clk = '1' then if LMB_Rst = '1' then ECC_StatusReg <= (others => '0'); elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then -- CE Interrupt status bit if RegWrData(C_ECC_STATUS_CE) = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1' end if; -- UE Interrupt status bit if RegWrData(C_ECC_STATUS_UE) = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1' end if; else if Sl_CE_i = '1' and sample_registers = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs end if; if Sl_UE_i = '1' and sample_registers = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs end if; end if; end if; end process StatusReg; EnableIRQReg : process(LMB_Clk) is begin if LMB_Clk'event and LMB_Clk = '1' then if LMB_Rst = '1' then ECC_EnableIRQReg <= (others => '0'); elsif RegWr = '1' and RegAddr = C_ECC_EnableIRQReg then -- CE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE); -- UE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE); end if; end if; end process EnableIRQReg; Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or (ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE)); end generate ECC_Status_Registers; No_ECC_Status_Registers : if not C_HAS_ECC_STATUS_REGISTERS generate begin ECC_EnableIRQReg <= (others => '0'); ECC_StatusReg <= (others => '0'); Interrupt <= '0'; end generate No_ECC_Status_Registers; ECC_OnOff_Register : if C_HAS_ECC_ONOFF_REGISTER generate begin OnOffReg : process(LMB_Clk) is begin if LMB_Clk'event and LMB_Clk = '1' then if LMB_Rst = '1' then if C_ECC_ONOFF_RESET_VALUE = 0 then ECC_EnableCheckingReg(C_ECC_ONOFF) <= '0'; else ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1'; end if; elsif RegWr = '1' and RegAddr = C_ECC_OnOffReg then ECC_EnableCheckingReg(C_ECC_ONOFF) <= RegWrData(C_ECC_ONOFF); end if; end if; end process OnOffReg; end generate ECC_OnOff_Register; No_ECC_OnOff_Register : if not C_HAS_ECC_ONOFF_REGISTER generate begin ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1'; end generate No_ECC_OnOff_Register; CE_Counter : if C_HAS_CE_COUNTER generate -- One extra bit compare to CE_CounterReg to handle carry bit signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31); begin CountReg : process(LMB_Clk) is begin if (LMB_Clk'event and LMB_Clk = '1') then if (LMB_Rst = '1') then CE_CounterReg <= (others => '0'); elsif RegWr = '1' and RegAddr = C_CE_CounterReg then CE_CounterReg <= RegWrData(CE_CounterReg'range); elsif Sl_CE_i = '1' and sample_registers = '1' and CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0' then CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31); end if; end if; end process CountReg; CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1); end generate CE_Counter; No_CE_Counter : if not C_HAS_CE_COUNTER generate begin CE_CounterReg <= (others => '0'); end generate No_CE_Counter; SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_EnableCheckingReg, CE_CounterReg, CE_FailingAddress, CE_FailingData, CE_FailingECC, UE_FailingAddress, UE_FailingData, UE_FailingECC) begin RegRdData <= (others => '0'); case RegAddr is when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_EnableCheckingReg'range) <= ECC_EnableCheckingReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress; when C_CE_FailingData => RegRdData(CE_FailingData'range) <= CE_FailingData; when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; when C_UE_FailingAddress => RegRdData(UE_FailingAddress'range) <= UE_FailingAddress; when C_UE_FailingData => RegRdData(UE_FailingData'range) <= UE_FailingData; when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; AXI : if C_HAS_AXI generate begin axi_I : axi_interface generic map( C_TARGET => C_TARGET, C_S_AXI_BASEADDR => C_S_AXI_CTRL_BASEADDR, C_S_AXI_HIGHADDR => C_S_AXI_CTRL_HIGHADDR, C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH, C_REGADDR_WIDTH => C_REGADDR_WIDTH, C_DWIDTH => C_DWIDTH) port map ( LMB_Clk => LMB_Clk, LMB_Rst => LMB_Rst, S_AXI_AWADDR => S_AXI_CTRL_AWADDR, S_AXI_AWVALID => S_AXI_CTRL_AWVALID, S_AXI_AWREADY => S_AXI_CTRL_AWREADY, S_AXI_WDATA => S_AXI_CTRL_WDATA, S_AXI_WSTRB => S_AXI_CTRL_WSTRB, S_AXI_WVALID => S_AXI_CTRL_WVALID, S_AXI_WREADY => S_AXI_CTRL_WREADY, S_AXI_BRESP => S_AXI_CTRL_BRESP, S_AXI_BVALID => S_AXI_CTRL_BVALID, S_AXI_BREADY => S_AXI_CTRL_BREADY, S_AXI_ARADDR => S_AXI_CTRL_ARADDR, S_AXI_ARVALID => S_AXI_CTRL_ARVALID, S_AXI_ARREADY => S_AXI_CTRL_ARREADY, S_AXI_RDATA => S_AXI_CTRL_RDATA, S_AXI_RRESP => S_AXI_CTRL_RRESP, S_AXI_RVALID => S_AXI_CTRL_RVALID, S_AXI_RREADY => S_AXI_CTRL_RREADY, RegWr => RegWr, RegWrData => RegWrData, RegAddr => RegAddr, RegRdData => RegRdData); end generate AXI; end generate Has_AXI; No_AXI : if not C_HAS_AXI generate begin FaultInjectData <= (others => '0'); FaultInjectECC <= (others => '0'); Interrupt <= '0'; ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1'; end generate No_AXI; end generate ECC; No_AXI_ECC : if not C_HAS_AXI generate begin S_AXI_CTRL_AWREADY <= '0'; S_AXI_CTRL_WREADY <= '0'; S_AXI_CTRL_BRESP <= (others => '0'); S_AXI_CTRL_BVALID <= '0'; S_AXI_CTRL_ARREADY <= '0'; S_AXI_CTRL_RDATA <= (others => '0'); S_AXI_CTRL_RRESP <= (others => '0'); S_AXI_CTRL_RVALID <= '0'; end generate No_AXI_ECC; end architecture imp;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block FuX0cSXIEXFEyJ6moxnlgdQNhvJUPZMr8vFVIQUrNLsDf2FviOIs4Jhh/CHFvNoFhP+5FF35v9LO dvh+bZPjoQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block S7tTbrlKJAdaschfwlJOPPdqEsgXhD6udlTi4wWj5WF48TMYe9G1VhIVqnCUHlUnL25oPaO2K5yW Vsk8AI8Bo0/VgZ4dmHFlK1nLKVEhAxpkFlhDaWKr/0O8btUKmCpbottVQX8Qc/QN/1xsB+cAtQVI 4p260yv1TVmYXmjx8rk= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block qEKqr1fSNjUXpQ3XWX8sKOKuocUUtDBtmTHImw8Om59DsOTw465CcJ6o2q+FcioWMvCRzAjZ+xxu AagB6t20IwVcnzoYE2NAv0kR5lDRiYhvN+Oa/s6UbWb3QTRoReqitNNjJrPzCw4XlCugY6l8lFOv e7CBsRKyMbLPzBTafQvYte4TvzLzOu+s2dZBgpeCmQ5oYGoP3d/E36DB13G2B4FF6q/prcZZNvxK 4pDBg7V2LvnQK1jZPTXaJEoulfO5Z4SIOiuAtfw9/unGEeLmG0aYcKYJgP/IxwH+qnHpwfqeRJCE /1Yj3BTLU7qGqTaWq40DGwT1+OerbG037PqDzQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block rqwqoJ665sQ20WMl02BGOPGHsf2aOUmm0G44onTO+JCu6o+spEGLBUfjMbBUcisRkELriGp+LU07 3cpKcEWYCGaCiotYyP5gLJIzW8NEENlr8yzJbZ8X/3ucAWlDn3zgCifC7D62tLYynXwV4FYxobEK 1DRAdCxmk6rU46uF9uk= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block eAiRCiDFAwDHAkcVLm985ZKYRnlElWX2c1OQg/hb7b1/zSEe2QBQQDB2N5VMdnfDWPIHLEDgULZK Pr7q9ZNUZVHE8Ke1zx1QtrmAjpCWyKYPSFSm8TXhERQqUDMjMTfRQdMhCqaeEGMDnfobIkisLS1L VRbUbeW7BucMesxRAk0lchUSd9Ot/ZA2M0IehYzxFpMFTCCVcgIcya1yjJFGhThRi34AcPtyOjSU 6Faaw0NdnB5L/vvtnpTBy747RdQ4T9ABWjubiJtZhydXYGF8KL1jkgpTE/c+t89+50pxoP6Tny27 gcEgvMCVqc/YLEqHUwQno+u+caWqhfW1W1s+QA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15840) `protect data_block OhRN996YhWA7mwFITWd/Q+Uw9orS4fv4vz7rKHTu0pokFrEx2UEFoN0Wq39LgDvAn+MIN4Rr6T2I GAu7fLsemuIj3zydI+giNzpox1NcmvNUgZ/UgA8LkI8tOJvwcdEWDb+24BA+t1B2Kwg9b1te3d64 47WI3cCm1feohS+/A9m7V7Z3yj5PLIWjow4a2O8Gms+l8fDqxSBfGm9YUyN6IMyReF8z2Ip6d1GX K2wx/VSu+UF5hNmauCRlohtxdGvPSBYpoIR/cDGWhra8MFe0tsseKi+aqz1hVxx0WjzdBqQq9MtO F8ZZEc8tl4LH4xI+ZtMCFRCv90MbMsEZeUhuqtjZP+fmfrVNwjc9DW9ILe2exiur0xdMU8ukGJjz 8/Sl3cxHJjClRpZqiHySq4b9BL6kQYWcvN2poU9UVn/hdDVVCfqAWZtYYaTfuhyg1f/3j1Ut34fT yihbVMhFp+kDljNrM536QRPBVJSGvDJd8kJroU/XJ8aVOL0trE7hQDM+a5XJBLBYe90K3vvgdJKS NNH5nKDEJKVAryH8gBhpBgz6/SsdsvEPHNdtb6c6E/eZ6B4UAr+h7FPnxvl5oQeZW/OiKSQeZ8ZB 40BHkOBO2EHHEkLU5lW/1shSi3iluRxBhxEaijhYSsdwIAAeyJ8kNWLXHAMO08qczzWn/PwBIOB3 pnNGyli3Ii9i/UDYn+tU/+WsEinoLzFsJNGMCbX3bG/APZhtK1RmTY1GWwdy0XRCoFyVFXd3xvF9 dLGj363KvQxwxgvov1CaPp7GQlhGHaXpJ0rR0kS2xdbpM4CMKavphro3yKC/9r0X8loEAwBG2wDT tbZsx7K1qEthAcXut+Cth8lxNND6uBq/i8pRVYh++O9OK3LT4smFURrCC1b8QusWbWrS7i8Jfw53 IOQze8brFD6yTxlk7zKrk+ZumqlTlJuEVZCQiGWAuj65z976TUd0iVp3UpnyHaomIlSEy10gtyEm nP7aUQc69WKN7dcVvWhE1bNg2u1iI/5kPm2khbRIj8dABcjWISdipYuLD4J2L4KKLKJvQFERuoJc 0OpFg5e4+3hay9vgQ7DcqeGYYymoxPK4RZ7erYfZyrZqFH+RLQp3Pq7QPnRSfQhNVMts3DigKXOR HUYm/YjCMxKQpMNYwNaquvApeAm2XhbX38gY47ks2/Yh2+wHThsmIrPF+lAmaeT9EaYkd003GvW5 DXjpaaUAYePvJ/7mCLGXW8CUVz/nT7ezlCsWECWAM1EcH9ijsCYaXxl/kNxlVE0rnKL19N76eRZq +90gOG7k0z6W+J03pMjJ8wGPSiCenpGdeDSqi3WSKuXUkKSOtGhIEAiK6RZjJLkaCk5bUrqI+fZZ ETTUl/UeILwwvmJB/Ofd+DlVCMrl6GAxd48mYeBFOk/E6YP7b4skwLUsskW7D3sZ4EqI34Gw1To+ QnTcF/jszqMrzgzpvLmEtRZDB2+THf2oqGhxColHrCdHz5Zr6kNSBzTi7K0NE+7aVyF1YyYY9Sh1 CtDGjU1Bo9YgOc6l/O5q3ovLc0dP7Drxl5Ls73VxQvDMTpKexFYPe3JTJzmFvcijZCA7Y+2W5O3T aVJotHB10jvHfir3i2Wal6cs7Cg8i/f5N6itAAmi9mjD4SMiWeZav7MbyKSfZsuu7mjDGuP5On2S Egurq4P9C6Wl+khiyy2TyGlGeXQqh4gpwm74ASZ4pe5z2lueGy4nyqWMyWqXOi/Jom9c14SdNatr CXivYVMaauGvOa65cyoQ4m/n5D5QNWqK7Xzy4wKKr+h9uHnmWcgyykIP/E0pvGkYSAznED88iobM jbojhboaJOaSFaHpbPf+gDFiOc9Klz2d+b5/ecJuIFRA3j/Vrk6WWTYejTXV7OHQWCeUf5DyT6h+ iW93M2NjMbqhZnMulKPWewQzXPWhfWq5rHn6J5Hz376sph2PwQhtfFbLJGg9Z2zPx+5D3vjw4Vg1 a2ZiYg4TAtKFSadcZGrYpuRWO8ShT69mJ1cVvWElmTW25DxXAcBd7c7Ws7xCNHq1AfOF0sPkX3Je m4udjbJ8svWoeoCdB56oKU1P+Mdv2gbZsAD1MP0f5It/SBsWjmYvjgrqj2hfR7rwYzZ+XRptIFi1 iPlMerBcT3ql/1kCG+1j813sfe8aeh2X3urWoT16k2Nenft5o/qClEXuzM1hIbqCeATQsA81+dqb nIfhB9K7Fz7AHzApOyanW/H+cRKu64w4lVyVVTS86gaPi1DAtx18pXA+n+IqH9/EG6kSlzb5mYd1 Zpw7n78FyhqZaIA0DhImyZxDLnsDKCnGC814wBpwFp21Ag/2arq4zUkBBlvTm81ZtgayDt5SD6vi H8sak0Q53IytEqoNNGtww9W7eHUO/JTQ/zOZT3KNEAgAV4elfLeRXkmUCNoYy8tHT3A+FU4Z7Hm3 WNH4bhjnAh0YgtQLROJw6w31QVQjs5rWWrcsf29iYxHDCsXB0uS0DAqKNEYAMaa3oF5mJAQX1Eet BkVfd6ROHGY5XNiFR+1E35do4G+uh6jtiYdMTb+XgpDXyARbesONChkC3PXC5v+wHpVT5Y2hRpWv wdhUfBWiiUag5ZaCyHkr/bcYKa61/06507JDBhtI3QaYM8U5JsZF3F+RqamUPrKpKVEaL9P/MVcq NvQ+EpbPbRTKmXgxUkCVQaHODe8J/Ec5NGR+jRbpZd2oheXeTyY2AGUFcutFCXVDFEAqIBPJfgv7 eDd5QqXyGH6BFjz3VfMmqbuforTSi5VBvQpDuDUrp9UL2m16qfv6CVHCbN2PTnLPYHjue4segyjv +mMxh6YBiGQlMdth6v54Zt0JWM8YmRVh1vhJ7P46wmxvRw0s7593OwX1TNAKB18v+QUTvdAx8HZh w0AUdYbPzVAI3fe96D7Q4jVUi/o02LsOIHMki8KGmkP+70d6AqsaqgD3PnHy9LIhmbV4l+Ksebhk LWVrLVNTBBC0bObnzh/YlARktFUJ4sqAgf97URdKLi7oWg/PG6hfbjt0gPuAqDiZ4Uo2XQhB2/zb kRi2zWE9eEbUSThLGI1u1N86rVcYAnTBraEe2J84p9kAeY1KDoEdc+Fux0VB3bJV71XONqyrkj8V 2wArDbL3w1DJYbYfnAkdx/s+SbXtSTseYlRlN/nqN6RxugPiNbBcHlF9maO++/lNfbhDz6hw28d3 oING0J4AZmhL2COMTpJmKzbPIBHxksdLfjmfUW2AtqufRNSzsInEztk25XHImgti1PNDxVP4nSHW 0xxi4jqN2o6Jxw8bUw3G/8kyHxY4+9f8wEaBV/9vAXcIxqu4dmdFo8CRXOtdxLXWOGtM43HeuKbe LGO9rX9QGwbveO6ggj40Im//nm8ILgMDbP+Uv3BDoIEzFcWe4gxPZH+MVZJVO6EILbWqTMpEPKyJ eczlmfc7YU8JkKwlzpU9pw156KJ/ZZlRlWBeKxsV4BBp+HK3E8C9ZU/cKU03idNpepPLWJo6VIsa B807lW9yzph1/XxyXoOTvt1uJasd5FdWI9TeVUgLCW1e/T+bINFWG97THU6ZSQrk4AG0rac1ifPM JqYs/zT5OXmZ+MrDU22FAGymUiRDyqSAC9c1fg/BjpHi+nRECJ583GRK+4J51wbirwoRLNp7Qhjn szoQO6DP8p4JMd0f1oQdY5eHsjxvpQQkawBw2L7X8wg/LQF180nLNcmzMfPpm1nIGldHqnLu/aAa YLmRJY2WG41R+Ur8UEUTI5e5L79VttZVoIwJgNJ3jCmRerte3zvnqQZDpMNWuJAVUFJNTxJBKwZI I/UWNezr9V3iKtkUR+DpGMUZ3j/LvrQBplthP1BEc/eoGqXXf6hU/XvIQm0FAjCA/m1XytJu34fU IDUVCr9g2INizZxi/hbLWbOxWQYGzeBQM7A8959cyr4KWo59Q6+evNlki4iDSo/CJKGhhuohxH1q wU89SlxiBICdKSCP/m9a6QCIJ7+lYPA2dOuXNTV+OgCqJ3zY+UMf2GWBC2gFMJ7O5d+yv0aTbs86 IXw676crXCLkdJmDJOyJC1PaEu/7V5mYX+mgugV7DLVbdx7S9b42b8V5nC6/a55nooUUKgqxZ56G i80YsXsnpjtClCKx7BlQvZqJspWOAn1bk6uVVODMMSyzoZ1dKs03w3c7Y1HIQoaQgd7GBv+KdLXX kOhaIJ5/VWT7gh9c2BbiNzfUDJCY8HwfkPl/Z679TAXsq+1uF/mA58PN7sWjoMk5PYhRyyVA/L5S E7OrWQipLilr2MTtupMC6dxqA5aN2z0A+BL/N2Ng4yRNb66ICU8fDZHoJ7IXj3RcQr6qoGQ/bbe2 yI1qh5wSX2sA4Mut5evK/kswmstDCRL7j0kjOuXQqkaRuTKT+wMLw9JaqpTHn20H/ww6XwS1WQDl 9ShixaUVRhlmQ0LM7/UcTirDoSJzxRxLzFYbZQmMT+FD2mkHtMJiNkUpGPOZm+EjKtfK18z67emZ /BrfE2tkOA8ltnk9b+cAeniRlsRbNSDlD0NiQ0cFZIvkUUOYynmIcm6oU9scRxuNDdy92SgOurgg 0YnI6lHl7+s2NV0gPSq/iHE9AXrN9TZ5rHURDcH9fJ14Pd28Ss9waKqYdG6V5/W1rSeH7qB0HzYW 4yM2OH/lGKyqTEzdS16aJCVMQLehE8Q5fUMAADiCgLeQq+pYglfP+DIlEBiWa/uUEEpEn2UbVdyv +SLtUeKSUjPAsRPMa149tSuenuPLofsx+QDUOLwisFFsz/LgFJwIQ84Z3UK/SjCJaDSf+Bx0TTpE xXjthejqIl4XmD2juvHpMfluc0VOjK/7iRdRJqeUKYKs6eCCjtKEN5rN7CYxwBfvYSqevf+PBb0A PCpR/Z/XYKXQmnCXJ/mjPMQrAJ2kRzBvwT33nNb+xZ9a/o6XzjLICJLVIoykWEcVbNXmatxvNKfu BquPOkXRg2FFsCZnMY64yHDuHGWeok4oWLGHY/H6hCjCqVI+g2LTnxerILpRufYTb6ovJBm/YnT5 7XO0NU+3c27jzSNaj3J0I67P5BYxXMmsTbK38eeFvwpiBAr8966LM/0IN+zDXsTFSyBik64JafoD +t2lSJ2LT/PoBzy3m3V9sqmETnJs+hsU1PV8kW4K1vLlwIFDp1/Qf+SXTpr6w1/C4gvHnIV3v8Ep mIdV41fnvtTnrPoxjkUuaKRgY85/18iXwqpYtWZvxk1s+L+zK9PqlIsY57oV0jXPT+CmMV9PZQnt qCd/acVrBeRrlLr2thKZTJonuljPc6q/2Ls1ESGQno6vjwvTSgtUodGLHxY/vVtd12IPSO3yeZPq N4/Os5SlZgX5VPCLohFEFpk9kEuuZZzAl2wac/rtgmq7whbG6kUs1ttr1ai2u/MveLtFU+18HbqJ WhrXbbuDyOpPrUt2RxQqDJ36ypn0uIHh5fcuM7w5NO7mIgBksTGMTcETa4EgfASCPV7mO+tty5vI Z93WokcBm7Lo2AkY91ocTHC8da8u7UiBX0WoMe6Ds48b7BLr2kfH0Z81XS1Y3IF2mYtjXmDHWe5o CFIpmtKPtS/qKUMKrl3MHpP3Rq+i+yYLkTuHSOKIjgidr5ISOltPTSDWiFGfPLJ9Fytl7R2y4Qdz mzUcgz9OdBwCtelmy8bhCG4IRPFLey7PTk/IfFvrKFlWwy6z8ogH4L/vJuPWveWQYJsK2AvxD07T hKnN2sTTWcDdjb4dMk3E0DJJK9/CSYssfQCy1Gs6+5iFBXvmIpVisQ6yyt6Vv568/pn30Iyx8a+v VVA43FC44qa6jc4lwdTbneaq+MCn9JhmuZrVsGELufMvKXcnanNib6BklV77FAv+RnkDiqdloBSz 1G7gO1vq1UvGChlBOVDssWA68xXUTfzuquF5swrAt3fsqWdUNk6F5Gr6BQ61ej/p6Ayj6h+9XwM4 EOPb7M+vLKBYUbcIHCCQ4qa1JvHKY2j1MFWEzjP1NKUlavuvdFETawnhJDxT3bnX72Z3SEYbB1zb 069uiOE2azHY8mJyPkg0qlbpVeHkE6lPFB79Ffu0IVHKMeZayhrrUbuvY+/KGT6o8ScXEQdQXInX NzRxnS45jzvsNxdjKD3SZLWeixsOY/KvPt96I9LvN3kzY4VWqttLMrNBDlH8cmy3lHximtWp5pMi bhJRu57ng6x0X32CERd54iqQznw7oadVGWoBb6nvNxecKPbFc2icQcXWxHF/zRj4XjNTjm0uHm0R qzJgvJeDGYdCtHGwE5/UNbA2s1PTcmyVx6uf+Ixsy6LcyXuv28pPJCwimj3MBiNOeRIx5LkqrEo9 Gx7hYv43l2p/YoUcCEumXU60VLdfzly4xQw1V4ywFZ9ZxJsXlcYnqsYWXnyLKHt/YKwkQCWZk/GH wUXJZm/uJT3+KridC+vfKWiw4mmEX1ecIfDt8qAImPKLSociRTQLi5HZGRLJoXhPkQYr0fMqyKbl KGn8OZtBIlnxrW0jZri5fbn1MfMGzNAURNJQ/I1ndPz99H2M9CsFXhm6mRUF9zhF6Q5iYuK54wyC 2Y8pqTmQTFp6TFb2hHv4ub3gftjlG+FyMe6X4Ws+tjhAt4hr/juyIjf2eWF/QKR5HAaCt6sVE6Lc OCempAc14PaZVtIOkpyxxc5WC7Gh/jVno0SkcKN5zDJfrEBJ/9JuKVLNLFIT6pKlSnogb/15rVzR il67f5tzI2yHoJCtqGUAwo50LYwToWoAqCiywXjcoN6RIUOGW8BSRe8tcO4YDV/DSs/q8GaUjbgI ZbenmqkQ0wpfjuDIzfkbaTBypmc+Rv0xUe4F1tjbv3wEXb6GzeUnua8kMQ62HeJbVVAKBX0Z3LLK fmI0Dwl046FOg39gBL7ZhIHmE07OhCTnMOFmW7tElXaAUH0PeLfgtaOQSF5U3bRqdW0IJFnOdqR2 EKWTFlSKS0aBahOt4ymYgr2lOn0pSUcUilicZng5jXv8kY7tP3zOgTHHsawZg4IED2StWnnYwyL6 6EIyAwhZS3af0YlAv8KvD6vcL41MRq3zwNDn1EI5lqc2wFg8fTRrO6LFuoh7mesRfn3qoZvPPloX Sy5rGkSKvMSaVq393JMxu3pzwOlIoESC2WXmfLNTFRfa0Efuar/WrXvtxDhheePV9JRJC1VefrLU fcd4t97wlrdnbP7P/syblbRLV/l6X/XuqeQbAe1Bma089OiQx+4LaREP2uEEfMCw71Jst7M5eUrS jbfdALJxpYFyG/Vt8Ew7SXtE5mfW36udn1CSRnR/pwWDmSuN/cgglmYIz5oQDfwDiUPQNXSoOzoZ Po8TiaZsL0Ngh4bDmYMl4/6gxBgYf1QS1VrZFCvmHt9EJVxy13PLY1tCjqHqca5SxGYOyfiNIHvU uG4G9JQNyIm9PWvRp6ANFLtVLNrNB1qBwLy7y+nJJ9PH1bIMBJ5FMX6vFrt4iE/kEA+T0WG/M4jG PgooW4kQdsc+ND+E9hvGTHqvtuYcnLMGCj0cje1KMXLRUYJ0AGoO6Z+3w/Rg2U1RrAwwoJ+h/6Yz Eip78HlbOkTbLnUWDqG2oCbyNwtDaD0sS/7E3MQHDI71fUQmDbEhGsINPLAN8dNxE5xiVyxpiqJi uiU1y93QYAijZR34Gk8gIZ+7qG0Hn4Xue1JvCNG/JF3rSZStxwtgEa+ADcxcxDY0OQtj2vohayWI VlJX0AW50EH6ziaEfTDT5VGyxygyvTkQW99h1k+FA3FvCQ24o68JvyS7xzKpqG5PcwQnBaPwSlSb nPFj9DnHCG+Xj8+rxgQCKVVVUmqPypn65R0ejbIrO5OCX7agbTMad0a6b3qAXLyLRZmFtL3R2LIg NxGFYbHufOYvgFcMpm6az1KWB6EoI52oEjc200bTTjHRKzgQgF8B/flyhCKa1gUqbAGMWdN6Zhiy 16eN6+DLyLDqyz/MwQo2bTT2IX7ziuxXAiYB0S/pWcDZWNvEBhks0vCnd39f60iFHna5MOUGNFza 18UjctssRu0JB4YFhUJIeUIwrTar/VEPjWY5iZ23NJ9R7CGUUmsjmA2a4dD7PnBc5Q2Py7sfufNa JZMQlNf/l8BWk14IvSe15D8fragfwLx6/r+tjxhfXJuzzm8de8tt5QvY4DMFVYHP3AonmgLGLKGT nFeMWZMYx9bn9Ljy2vE0mfsNPXgikOuRQ3Sn5SYwACigPJW40HeUbFGTfkovmkhAsogiROFRjFrS 9QKvDiX03d35GstBpzQuq7RrLU0VNOtpbuHuM2bdi+klXXy2cyeIkvIBlTcGdtogEvoj+dHrfs3c tzPXtFW5b22EX9P6qkpoBf8/Xf9GoRDIEg33ZPqvrZVwX2TL+3GOqUJFo8EZsEhYBTDufu8lIgD2 3xk4u8ozixqazULCUVGtYAcHW7e0KFpQz8sxVQVNEf+pC6FlR4Cpvr9q+5JCzoYRIQcGID76uo13 xeoCjEn2A+rv24BLwqxPtRUmwmcNTuMeGBfDn8ZdUgaQRhlVyDQqJkDau+2OqbL4m5pu+GG+uS0a WuxlX6BBonGlmJQw9jxwAEMhqI8ReRuj1F4UWdIYZxDX9BuHGs/f8HcFQLKRt59ZdubZsKmpbN+t 57/7Ajqf55jPVhbN/K9yG/rqEWa3ivTOC3nOpbeFlwIlsd8lN9Anrc0UUww25YltsPwcMA3dvYfl EIhuePbbUnU5KbjSIW7olfHY09bdqIQ0qZMsiqCODRzufYK3mHEhwlk44kLObPQOLbk/zBEDPH5z DGhjj2COelUd/yGBEFR1JvAMdmlvumbG/6g/lbsLVaQPN7UVOffPftHPyqPFVw7kRoDLr6Z56dkO QGAcehDKCyhz/ZGEvMKVR3IDNmOAJLzFWvw3ra09/64fXkoUg+Jlgx87IOonYAimPDCTXyAWrbTg UcM23WUZmORLQz4sK//PwCdaN4xqzmI5yWuNOd3Fcud73IOm+beYiNFLYZnJEgtib/0ARw+cd/YY 9rVprmXvNY0gPql8AS5hHVrLFUMJjQQO58Y7axORxZhGmsA4L6FcZPWDJyn514IP5bI32fSG4+3U BednwnPidVv8b1YeHtnwRYq6XG/MUfMVPZ0Zk22dAfffi1G3Nm0njyyHLw7lfhQxgdUHHTN+I//j JxBXbSgo0Nn5gmjzlio1iEOZ2qZBiToKJ4n4Xf9LgjQcHdVCASkyKraC3XwqI6hh621pqOTAAzqi G6h5sOIzU+bGTS9Gk+NcucMhsYeSIQGAgdYu2v262kK63/1cEIL4P62KvMV+WHpPTZ+w+UHioaoI Hd0R7qVrmbVcG0DLrT+n+LB54XHeGPaMAOl7WEtNbBZYadrJCWgGcLJs91d9eLrhEa/JRiySxPDv Nh3nM7KYglWGRv/vqyf1bpax8Tn/vGI4cqObJgMzG2ixWZ4vwiNWbPQbxs9tmjt8YVkElaYBgaZi CBGtGKzLHbV+Nax3o6IDVM4Pv4ukpHXIclYgBJ1i8BlgqYvW8+FfALWhUbDRNmQEauVtxFrel+St A9Azb28ku+Xot4XqwlBJ8Xw0UUbTS6wgaHbGKLCndi3ZDAcVlsa3fVOamAvFv0bxm5jMbMnbQv1/ WZfdyvIoe3cw94LbSRGvEsDk11KTng76LfLVkAxVSj3rbpp5EqT2R0vB9vbj9eRs1iMxU4KV3+zv cYGnPJf3Kat9Bi9QhVNHjMDMLT3rMiXH7hHYp8VDWzYLZZuBCexp/4qoozpoEWykcieIkuX+fAFk YMA32unn/EVGFZeGMjg0oYojdM6cjZd8Tsd0Je0Lzk4pp5DcwYMh8FE8tJ6iTWG1BaOFDSBzpglm 4XU/5p5iPV1co1CmIGGx1rgWCsANm+RrNsV0l0VnAtyxNlyyJkZ2vvOPkaGTjOhdo1Y9PIQUZzGk 87xHTftVkuEfVGWUwTMPCijqNlMkkSwPQp3yAhEtN6oruJsO2296CJYGYJy1/Zp6V6/eYgbQ6BWe S9GLX0DobgPMJkyzaIcJwXEVj8J9FrYWrs8RFiRE4l4gh3cy7QogDiRhkD7nGSBxx7ltbzOVLx0u lB+FVFv60o79idFgAcBBFTUMPGry0V3eIx0Duep0KXqdqVrPa6QT/9YRZDCD/oTAqgcrwq4eGXGE l61pR/Smqa1wQNaUKZGPNiLtzRsVm2xYZ4c+TnkhrfTYDTNGdhCQ7h3293s847Tky3lYeuUprw51 IQN8KEuQ1yOsvoi7v5XmxmBKaeqOPCZoIkeH/YQ6vcQ5i28oLhIOVTCg5Z2nukUmaXmxFWcBZgLm nQk0Ev82pfN1D5tewqDR5Vb9795fqnAu5j/TRUlM3vzS+DfIdl174E/BmNTNbe8YrlpRddeTYXUg TQTrvIgOE1rW4RtUhKlEiX0PbGQYC29wKsgUoiUBYvnkUnKnpjY0kMct+vwIiZTRznqjl1ZeNAvI wCjX1Knzw/S7PdLZmdLizqZnnyEqV+SpOrlYAQWrgRFz+Lq6fc1Fz0pVvc3La+bOP3rk6n6uH2Zp XbThibKQidpN5sTGhNJEn9P4P3Pnk8XHpfkZLNc56l5J551T/eHRMls6kPqShDtTv9ioicCGDCoN qlx9I7zKOO35wFXzhssykIz8Ro5qY51tuy3m3YTjwtAFGAsvyO97297u3RZToke0beNejh4aiu0o MpebfEIxxdqJJhiPOu/XctnOqK6EpuIIfc3p7DzvmAYQWUqLBp57/17MKD3lw64NzUz4+m4Ntmyu ilN9bZc/Hv7CngccFYRglZmtmnlThvMGG9whwAnXteg6PuZUs6CE7mRKIMfanFbcwOc3xWPkrv/Z dvj0B0QVXWrCdIxhmjAhOvCpV5qiIM7pfLhZ6BQsZ4M7z4LKPa/gGj133NR1JBDYQ3hbjHPyUI6v W4dHGefLsOlewA6WiT9xtINIho2ZB2T1H3vcQ0+01YxlKFIFljPUSr6ttALWHF94Y2cXFkPX0gRl h5QzbLfrQzUpHMBfANXPDyd6heEQCUCbE8pJqOFpFFG/RI8RL9XD7XLcAq4HPlQ/PuG8mbJ/8hVY j14Ye1iCV2/FN9InlbY1mYJvzYNWqu6Mufhx1Z6CCm25uwn4Adj6ajWC5YzSW34aQAqceOtTfBvA +fxrGlCMBZ4dbeIS0axYgCfnT7z7efnGRuOFmdKlJ93RWCx5n4XWrpgGCTjPok04sVM6HDtfmcvK BVSZZXt2c9WZ6D0shTtNSXMxm2UJddnzD3QNgwQdR+tlPvws8k4UGSVZVoOcBuQuYlrLFPFePEfQ 2SLfarbPqRCMkZtFoIpUMduOW+WADwEd66EzbJeA5QRDb1mvb1RVrGzt/9tMdidVGqDgILKpr3q2 LJLnCydj7NXzwFjsjBhbkZjRhD05/KCjzz6BV594sFo/DPf/ZL/iMx2WDbWCX4Ic7Uba/gPruR9Z EL463VQ8R++H9PTtLV7VMGB9/h84bxuFS6Im7mOMdQ5dd5XElrIwynbsmWNMlObRkMqb4TIZYoOE g3u56sKOhWQBzC9ngzBu2m/1+OgoVdLwSkHFX6tVO3JmeZlq758CY1abBoNA0TX9ic8+FRBi3Rk/ +cgYHvWLqU/D3MRHKgSJIW3lJZWjHn+06+oHk2ciQJw2/cD/XQZTZK3XguHqXUZ7rhkzti8hbFaD qlncDGzkYBUJ8sY23idxAnAwDnIWRI0ExS5TvQ7RVu/Oevjaodev953V6A3mwofdvTl/ABJKwjag wm+J5Ie0VCB9dNNMp8OsjPJfwbBWKT2kPNSGlOOPhnvVBdoPWqXAmz5ITWSxZukY0XaN+UwhU9hZ fNjAe4ewhT9F/iTEFoZlyV0FiIKgOlR1pJMay6L4zR6887yzOiXw+5bszOL4/qZ0AVsLeRS7syLV l+Z9sZ1mfdRAOtTqop7eKr4CNPGboV4BsVohkX2fJ2mkB6yBujqkD9usCM+HeJyxm/GVMYH2rKe8 TkmrSttDfRDBGge+6bohtFFrgRC6nbCqwY8D7jFjnZ9udddUr2/jFtL3RK+OX5PmD7tbjhrafZtN TWoWqgcxBD573otToLUgfHyf8DIVsKt+nzLGmVbGsOpOEOrKNnh3+VZC8fT7f9+sG/7QM63Gbl48 6LmjVK3qgMWxhCNRuWTTHTFGZlXqCGnPUGOD4LxMjkNoM914EjR8UsH2LJRmFZQY4k2mBIsw9t1O ZzvJpiwUkQmxmXmSziJvjxQpUbZLp7Wnu1gUXJfeYRw4BEP/GbpVsHLX1utVf3JwSuOKd6gVlpXy 0x9bWVdrpZk3OFy/phMY8+9+bP3TPD/7FLurRvNwXyE9dyEX2sEfC9TAP3gvop3wE9yr1WWLOv2S 6C6uClo3OnOug0RsGdaJHsU+DfgV1x+Wt+uy+/ndia8XkyXNH/YM40IlapsO1/tU7sOsnxMCbNsO D6QiJNSJwy0f2ckNKvm7uyxmKyPbcaVRwiUqpcuAk7DKz1gfu1y/ETMNN45VVJoF9wcSdvD00GUI jZyV6jwmu7m5TiUwtLcuVBhY5eqeUxOmXZpJ8vFSP7mjxBMn/4PQ6AIbOjKPpxJdyxCQKtD0Mnm5 dT16RsZqOvmfxupivJaw6cJKD6OHujVjrpeRH1Zzhjhq8enR3k/FsfolfPlYWY/cYA92+8QLnDaU Mo77ls+DkRpX/HniAarEtNS0F3bqgPxjiVzS1y5nFDH06rQhQuGNfuM7reCsEsarPeQS8yOb82Kk jrYm2vyrJJuf2elTANLG0ds/DK15L+mcVLBG29CqGgOqtqRioQxn+dv7tHKlTU7tKacwdxCswkwD 5ugXvbDI8tJ7ZJ2KQO4DwI6QCbSohcRCwbKsFCfS3bVCcOiXOGQr0DRaQCYb6lcz7fZ7rW2bRwGF PGDJge1QrKZUFMMO1KfRgUzsszHj5zDJJfYKjPVxBLLd2px9tsTor5CZuPXoXgM6tIPm0GFw5gDq iH3YcOGyNf2oUItkVndBHWvbfZ6PKYgssI30f1uLDph0X1TBB8zBQCfeqqUfUJhYLd4gCDSATyrv mFN9QwRJm1lI4qiHE8cusBBp1y/jgcwwVTILwsBZjHYS/SOv6jfwerfdNqAjiOmNWD7DycT0IS3B eb8ucTG6SY5uwQverA8dA2WChj3M9bIx4N9MfOE8g7vPtGaot0mX53SyU74KGNOOH0ubuKt5skON z5ov+DatahFqdip4K1mO6Etzyl9bLCo20P2gCKDREPOu5pDZIjJRCyO7ofWhaxPMm3gdz2OJfBPT 2J/joNyZW+eCqMLeXe0U3N9EIgLI/JHemYWyejch7QJ0zgqBHzM0S47+V2Zlj4ka8RtwItFSJOts dt6ozqPGdnlwN5e5Tc2BBJ+sUYbICztMGDyocx/inP8PaEtcTPnWgtv2HExdujYjqKLQtdlpY/GG FrScgOnO+ZnWAfB9+GjJ5IJSpERgCJlYaaMsDRDm0mqjtDzntTtkVlnmN5Oo7AC7GQRLVPDVIEtM yC15s45J45B1Flu+7St6gTFbQMq7pSCHjYJ2UL4vI5vj9/RxiReQ2br7c0JzWTvSImUpffdYIxpV HskRFU8YT7ATE95zLg8eFVvLFjKO8JUXqpcgWyKdfmlcEty7x7EbnFreENS7IhO/fKDw4jHeOg8j dRcmGShf/8nQmqIwsLueKmvDqcAIMpjh9pu0Mqh8sd6hODEjJEY0LU31ZGPnl67vQZQzrRor3nPk LjXxslpwHXnji55CAG0ClBWJ+YeM6ONiUXVYOKodZ3YAlN2lFzRWPbxtHg6iWlM9YGMqE/SpEHpi kzyaKvPf//jROm+jUoFmXSFO/wXrW2BffxBZaF+umtEWz0/Yl+suwjO14XkXmk+NtEDEW7OjM6GN PduUNUelETdTrjrJXnfgyj/UogTH9PgiljIo+63a6XVW4Ip39/hNhpUFTPVeNYhcdYt7bpNiY7HK loosl0onJKFOlO3sDJy5Q68gSfvIS2TaN69ExkQQjp02ztkVq9Xbr0onYKZonLyXhkSsvdMSTlsJ 2GEavgGLQsClAfLtApmmPnw+tMl/qhLnWljLuh+JRYyBaDbM8+kT8+5zhjiz8y0VWwhFaGLhsfZn bPJB74BKIfFvjadcuT+LbJ2MriBnNzCCgEiNvubYl2j6VnLB+8ogEoGaqQ/yZxsS5auVLwY50CsW QpOQL2xJRHw07pA5nkVow04JIioreq7HjejGbN7sS4zUoPoBn4vjfhfpzmb4oSTtqP/EfBRW+cup 4RqaLi2g2N8bWYyvQ8lTLXqAFiBEpKq2iHx3AHGihwNPpghX4LnMHQVs7l6Jl6ZQG8qqjIt0ptpW 7jnlPLBY7G/nrfHdSAGf5uWaJrzVfG9bPjKYdH+orulxTQOZQ8cHQchT/5PpF1r5HzuMmRGdXv0U cMoO6IWv//bB+17+JdEXzcTP6CroKcnbsdfSvTs46+51HYBfBSHK099B1f0rwmq7pQE2raGNaXlv rBK5ZJXhr7yF0m+tVQ0lKj0U6RVAGZoVhjD2E+IICbWJ/aDv0lGBizZNGdgJX8YUgGWYEVb73yy9 QeS9n6U0Sgj+CZLgKoebK5kjdwr84NdQU6dDr230Loi5zXj21juQqW0ccIg2+lvr1Dzup35sViER S+tGdu6DZY2Fvkdc75fJzE7JpTzaecT7sPdYIv7Kc3thmukTi/zHPcN86Lk7c5kwTccKUn+87w+L y6fhxSj9cNsoVmy0rReIiJh5iexuPHT+EYx63523+xDleUOKT+J+d//Bv/8ph+xjTviqnaMdED2b ehDASKpCW/nmHFtBDPztCLp3DAQ1acaTtcQCWdGX8vreKTTs0XPqoCMbiuvGHpuBIge4Dk5ZGiNb MPoCCqNIoY6Sn1ObzSVBqsPiNwJzSkhpPmhxKiQehiB7xQE3+akLdwDfFtdw8LSyFkuvmxIx/rcg O8aozW/bOEc0oSdYuxA6Ne9bOqRa9UMQ+oQlhJWVoIe/RvDC/MPXFVUVtP6JzT5Z15OQmJv/JWOK FN6IqkcCl226uUBn3meoXr2xwR3kVRvwaqs/POnSktsvBuHiKOfaIkquspbwos6wYDbkIUXl10hN JEp0eO4kzIXA3Ou4VdMiwkcXFp+rjgPnn2n09RhnQNS+nX8dOMUjHmT7d70R1tOHsWvY4doFibJ/ Zy8LmDNXLBvw74XvWnqmHEd+GF3Wf1cRS7Hjv9x+AXBJ7M8kwKFBs0d9BVc9JVhqjVv8JGia7fbM mOjKelbMeznSWtUfCHin8jyrIWKYfUumc8w0jMRHf9flBuxZNKrhcPiLzRJJU8bOWTC8LFcBYWwZ 1hvScAfoTpGDU53ovaz996oG4Wj5ChmU5GTKQnb46KfDkUW9adIWn2nH+f2igOxkbDBsuCJ5mTvj W7xf7eJXp4ASUDF35yZ7aF73eSqb8HL7qJzcYt/1FNniX55YYw+A4KeDLk5hhQSGYsk/cORxcPvd RsS5a3sLF3Gp919IcTW9lB0keb9VdUGr8iXJAygn4G5ms+s3yt4oL9LkJntkLBmp7nBnoj0S/QjD A4WbWOv9Mos7PHCgkmJCiMTIbvXHXCOmpBRH4+WKD6cw6AkNyV7bAG//b/SXAsdt0kho/AEVo2Q4 Iw/jHAJ9HiAIUnlp4fIBwbjSh+A98ubdJafnSxpT7bXOoUTuwgzqraXy5vhYclXdm1nw6bwpB/Pg TIEyQYN3Z8s2wQU3xrrTNdNfAnDi78Swxmotep8vOEbU4SzpKvqEf6lH2U7Ix1VodAGFiM2LmNhF JgjCqLhCosDLfy4sY0nvH2ewlDg2VD/R98FxxwjiHMbZW+l17SHRYw7DP7FOMAG1MjeU6VDvhAcc 8iJc8xe1bU6tiKPonXNOXpcDzLZn68af1+sVRPXjF3/M4u8M77JZE+sWjavO17ighpeTsgD5xN2v fu4SMPDIgJ4q24i1WXWmUKfeTPKXbTqg5pAmG+d5H1R1u47xHBzP9AXj6YdEf4cJZDRjdkgwm0FX N96q2q98bloDeHMIsuSndBHxshPqcTfjs+AUpsQ09Rd00BCd51JrVRHx15ZkpukSfRF9wXy12To7 T4e5/HS70TkLpJp4E1Cib9nCrSzL/1ZW4z/cg9J1O1KsDE9ClhOig+oWhUivoq0W3PHFAmGwBMXd xmjuUE1THU9ehI2I6VeVDaA/2/k7BMOjP7U4vBeHQytPMyxwZnwNPn4/wwwHAiJ712qSkq0sF4lh zYEnRiyy7GgvUwc8TBl2aD38mK3aq9xgBSuQnGwxxcWtkKUBCSV16uJW6nJUDYecV7DQMKowxP2w jvq41ZCS4biEwmG5McMTI4I+hqS6Bb5bJFYS7YAQVBGbiJ2VxjGjSTbv010C8S2sGy7d/glmtM7w WF3qQVvrBecDd4AKG3YT4zae4e5d+Vgg+SRuVVqK+5PH0XJvlUoF0ChgNaqU2QmRh4YTIgfXWcdz s1LU5k+hEh8zOnnhPFlY+f1kGKFNi/udkld+uP9ziwdDEbBeNP0KIVc/ujSGg5KeThQzlkv76XD5 MYITUxSgoGFLE5Ufc2LigMhgp778Q4RLEuOe2pi5zuCehdrOvsCrZxGTg8KEiNeu5Z5Nw+aeKlRe DV9F3E37bWcWR33ySqeVlqUz6okkYCiZLpkHysd9LDFnn7dvlebcCNazr6iqBFNjAoYkmmEg5Ppb saBv/4gOrFXYbH8aQF1xo7lHzGTh5W04TQD/aL9avRhS21vLPQ0asvRzcIrpRfOmuKoX5w20N9Nl BycAKX6Z9yd64HLK6zUSsrGz4pxjfQQ5jnlsvk81MqD8b1D+80Kp3TEVFnQNhC7IS8EpObR4dwrP g2G1VQiG+Dt6SAivl5BubpXzCjrXI7PNOqYtWo7suImiR4N/M5XxxtNuY2XVFKh92musBCQLoRlB TsH/kExLJhCN0xSZdIcpRJy5699ZLi2FWO2hD/V6/N4cYownOBneCWuENbb0N5ZmMUaR+oHKy0hw 5/kyAS4Wakaj02KZYrLKtVrDuB4Kmlr9PTMjOqNAlxFtA/mgxPyusU83dbRsn3Tmii1lrDewNbiq 6ABobtL1R36T2NddbYbVziil4aMXaQudShlTtJ4c3JAI0tuUVxmIDrl7U0Rrj7C9iRqiI1vIUt+1 N1nuB9tcIQBALa6b/9jEDQyGa2i2HAke11mZXtToqWBSAyQpBtUrOOjPjfhGYo3bA+UZUhbiVN+u xupU/7okziey5iKNOmNXSu5Wl2CQecWnhV2A0RcsjiD0K4IrcsIJrBflRQGvirBHXBUK3ZadTJQP Fy7Vh87AKXMqkS18WtXdrp4bLCO6gGDNkkmZsH8+JlCf9jvfJfDcd3xCRQlF1wBTCzTh0ZR1uUR2 IgF8KXddvTAbme/abv14oFGwrEevUyr0G5ieFdsUpdDo4U1QJQqbkgNtPH4vAVyDyOhVKZq5CRXI iK4OgmfPDHn6sAxz+uWHiGH9Ll8pEqF8Sir+AsGWyxcIEGPOv0nmF/8+vjDULQ1/KW9zZj0If/f3 zjvRbCEsmi22VIpwD53gQAacc/aGUuTQM/vvUo0E7Zziu7uLEkBOX4PF8ExyFAxWjhYdZ0+WxRdt mgGIsB4O9jtewzmU/01qS/jPTHvlHqTpqlGQ4OxVKDLS964zNRqRm726XohoGA0W8ebs1QxJ/AV4 u9QFAkSHvP4DcrMewBkJoEXKyzV9szwYkPxNOMraPmOLcnEa1y4uXFCrklTe/1us3BivxDDxfCgQ 6s8AP7WvhN5nl90t1unMjTMcoEizS/SnJH6ApOAYD7CYF1XnScbpvr44tyjS4X22fBohMfKTWtp8 nxAfTeOljw/g1r/V0XeHeu9y7sYJt9Fg0qeI9WncQ5FvzU1TQ/3PAe/a3/SivMhbLXoLTc1BFk76 k/zM5ydvN0rbKLtN0iKuuxriaNGvh9EFfuQYitxc1FDTpq2lCfPzaY727B2UVB19laQW+QudSBy3 shSOd4FweK+fOelfRHp9257hmD5MtEqftc38akAB/LVXVN7Gsnq8O0/O0+il4QsGuJAmgX50CJM4 UjxObLpsRNY12SMh+GGwXzIcysVlU9mz7Xve1R8T3XEEVXIWbHmIWIy9Xk16tze33aO5uBRjcNW0 wtGcCaDyGnSMnImUeQrymnjPKyQoAcBH64JjHXJP/WBbCluZxtfT74GNkKoVQztZxk+ToGY3Si2x SF826SM2iywdZoYGtJCClKWq+UQWP9RuEyFqRZzBSJpoSrv8Yr00PS4JWRSDvQVwa20MCRlq/HGe KEHvRtW2bSLLj88qKBKI7wxNUcxAmSjFLx6rbDpacMcqvmpR1pVRNvT6WuXWv3Vsh2YP1buxUBaf BH9qTHPaNkFKaO6Gl5nG/ZmXJ9SESUSdAZFbJti+fof0lo3IzlZyne5CNR7GAfRQluV+EY/kozno k3o5Y0G3Cc0c9Rkl0x7o1kt92dc2Q7eq75+5hSLxhFJHMkBXeHQb6WooTvBTYj4WM+FcLfhGwuAO woxk7ZNEPtvBKwV7ieFScF55fGtpoO2Sj4F9fdvjw6BueHydkJ/48t2ZcLMNM5AGrJVXVtDn0VfY TSKovzfw/4a8F9pndzWdwPJT++OcW/uBpxmSXqWCuUSGjPFWIJMaMcQZpr47a9qvDQVbHJJIqQ/A edGHvXRESKkwBu+G2jR6JG/es670OICFyYZ0xjixjSIH3/3n+/+QDtMoakyD/okfkK6Hbgssc9T1 yCGgVs0E+5oK4W/rO8hSLDnG+lMY78v5sBusid927aG+cNsb17avY+XQmykZEgRrNIBv/V5HPu3s MMiZSEEu0broZFGzoImlj+QbgjJ5OZjizIi8nsK5zhdMocKowwVUUmlH5GGciNRrZkJAnouuz99V FLaKd/k6taYSRDdcL2UAxi51+O2fT9UrKU6EY+oDbBfhhCSsGzU9Vw9NviRlOrxWV9vXK21d86q9 PygOSMlc5oSkaNgEtPUVYCEzElBd88QBfUPBPQZL4PgHHGwSSTehTONzMqgPe+DaYRQLQY6HNpVu TQmRV//H1HpzrpmLpipHA+sD67xzjA1jgwI9761n9oZQl2j/TGw+4LDJfKpWmkpEGKKSqQDqAd6X 6l+ITlz3SUuqy7cT/zC7sHYJekOAF92+B1B05KRJ8rtceHEo0iuDID/BgqLqUPSDqf1bPC0yvi5O 4dJCzA1MnsxIY/a45M64xyAetYaReBPRbmvMgYriNh9IXkRwvysnx3mqehIxYU7Ivbg8YSX4gaNx OT2F23qUfI3Dsb3MP6EWCMLlnCsKnPy9UHUZEGBR+5bVk+Jb2S17zQJA4LJE5j9smmYQtu8b793/ yz/8P61FF+6Gxbp/dPCWFxx0tBPAgMoKNgRi0szmFToixXRynUctWK4K86h+wLO3nawvfXLA6aEQ CV0//vjzhLleH364829VfBPHZwmHXB+IqOqiPsfO3YlJ6xOGr9+3Kcitf1b9Tr22VMKUb9GZeq1L T8J58SSe8AZVjwxqPpFu/HpJ0+EIISNwTxmBugLoMfmVT/0HPMfVqj4n5aT66FwbemWdkkPJG65Q /02KkhytTSKPkzLdEnmCsNOqIj8fJVJkQsH7++Uhd3A9Ai8sahx5/mc0vxB9NzK1DYAX2kbbHtB3 +nCXjf1R9bsShVTG9we8TdnQmM2RyseGIQ4x3coMrt2Q0Ad7/VUDdV83PhCZptNAckdC8/PMusMp McZU05iGQDEC8TYgC8chmhibR/74vfFv3X9bigQeiTsto7YYEEKntPFZkDY2uZyxyeP4PJJt0Mh1 WBVYD++NAx0kstH1VyLTCwaEqMKwj1pOHK6fC4hNBD9lZ9var8KfjhxHczuSmf1Ph1gWMRZpS1av 0898fBzE3rI+yQbxYIVMR2fndQ9dCfCz179N5KLCQ6z5CY4vr6YlVukFy2GlUUAixHXmtYW5K3qf BBYRe1iZXMjE1d/1D9GI2NF4+MoB3XrKl0nFVgMxA8dErJCsw7o40llBG8b07RpKpb8Rq8eBFIHw l14uicuA4E0VGD/A7koNiR9gnLxOPf3gFa4r4Mbly0txd86W4Of95ilIAqawunoxFTrlaAQ9tTkz 9nThHIpa8JV1hKIp/DV3oAtKEfJtaGbAWr0zpc/HEfN21XsxX5ZsUy+7TlV6CBSz9DL87lDROrJh aQlk82sd7v+LVzteZfFTfM8M5KD83zuSW9XwB0ucjUjW5DOtjDPgl1YRlgn213gty3eOKoX/mFMI 5zBMYnoV6yanjXASz+O2ZLLCPrhRqRRvYTyAuJBXDw8ES7xkllKlY1H4JpjJtYvXVaRy3TCACHrF gZs3dd75JJv9fDhl1oba8XVvQwh3yNnrN+QaCvfIKTZv6HAFXkTA5t+mgkDQEt2kgyHzXG91caDx 4520YdPKTwKm8l7LuUywm8ciHrsuqhTz1dfm5flD4lzQzLM0Svlf3Nt3qwkg2R7sooNEv1SXUM9V cfYoLcXuHOeiOQEESmnbCFl3pYibbQezppwYlie87/DQOz40Bgg1aJ4ibAln5juaPbYnKwzIxfAF 3mt+yk1eiaAuXtJ3h8BXMwJZzLvl5tTXPYT1QvPlTWq1+zN4zQc41J9QkVCl44jtLruKcd0MZCgY F5KYA3QncWM0wb5uN6Q71r3ARdVN02iAqjo68heE3b+SShsBDIxxeoSuXEOhIWe+qbYYLkXKYXRO VJS6KvZTB8A4eR0KBw6wuCx6kpt8FI5y1XhhDMgn2nIe4Qu5IJeZoqJPV5w+rqgiIZbvAbaPT1Jb s2/dVa1xEX6wTcPL4faQZy+JlfjJKRO2vZpFENJI7cVz3SE6DOjWbmhQCG9UnW1N40vvdlKHT4tW p8+AELrmVonL0cmQXfOX5Jma9ZfzQIq3urFXBJ9xu9BcrTX+SXyBWzhWMjodpVVsK6Cw/gO8d4wo Enm2O7iO6aqip6xk0RbgerUrUp1VzAU3K8NDT1N3vEGnox9rZS/uf+CRER5yjdy6ujzJhvpiPEVO a4CwP/KcE3bHXnEVAdS8ytJyZFOGx7qRERjfywqMgOBHO+xLSs4fO+kXX9XQvoX/Z/z0G4EFR9BZ wKAZzxTIR1HbVQJcAVnBb0RIFKvgwliAHCiSwphQ2e/AySivdK4iN25Bx/BnkBvu0c/l `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block FuX0cSXIEXFEyJ6moxnlgdQNhvJUPZMr8vFVIQUrNLsDf2FviOIs4Jhh/CHFvNoFhP+5FF35v9LO dvh+bZPjoQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block S7tTbrlKJAdaschfwlJOPPdqEsgXhD6udlTi4wWj5WF48TMYe9G1VhIVqnCUHlUnL25oPaO2K5yW Vsk8AI8Bo0/VgZ4dmHFlK1nLKVEhAxpkFlhDaWKr/0O8btUKmCpbottVQX8Qc/QN/1xsB+cAtQVI 4p260yv1TVmYXmjx8rk= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block qEKqr1fSNjUXpQ3XWX8sKOKuocUUtDBtmTHImw8Om59DsOTw465CcJ6o2q+FcioWMvCRzAjZ+xxu AagB6t20IwVcnzoYE2NAv0kR5lDRiYhvN+Oa/s6UbWb3QTRoReqitNNjJrPzCw4XlCugY6l8lFOv e7CBsRKyMbLPzBTafQvYte4TvzLzOu+s2dZBgpeCmQ5oYGoP3d/E36DB13G2B4FF6q/prcZZNvxK 4pDBg7V2LvnQK1jZPTXaJEoulfO5Z4SIOiuAtfw9/unGEeLmG0aYcKYJgP/IxwH+qnHpwfqeRJCE /1Yj3BTLU7qGqTaWq40DGwT1+OerbG037PqDzQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block rqwqoJ665sQ20WMl02BGOPGHsf2aOUmm0G44onTO+JCu6o+spEGLBUfjMbBUcisRkELriGp+LU07 3cpKcEWYCGaCiotYyP5gLJIzW8NEENlr8yzJbZ8X/3ucAWlDn3zgCifC7D62tLYynXwV4FYxobEK 1DRAdCxmk6rU46uF9uk= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block eAiRCiDFAwDHAkcVLm985ZKYRnlElWX2c1OQg/hb7b1/zSEe2QBQQDB2N5VMdnfDWPIHLEDgULZK Pr7q9ZNUZVHE8Ke1zx1QtrmAjpCWyKYPSFSm8TXhERQqUDMjMTfRQdMhCqaeEGMDnfobIkisLS1L VRbUbeW7BucMesxRAk0lchUSd9Ot/ZA2M0IehYzxFpMFTCCVcgIcya1yjJFGhThRi34AcPtyOjSU 6Faaw0NdnB5L/vvtnpTBy747RdQ4T9ABWjubiJtZhydXYGF8KL1jkgpTE/c+t89+50pxoP6Tny27 gcEgvMCVqc/YLEqHUwQno+u+caWqhfW1W1s+QA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15840) `protect data_block OhRN996YhWA7mwFITWd/Q+Uw9orS4fv4vz7rKHTu0pokFrEx2UEFoN0Wq39LgDvAn+MIN4Rr6T2I GAu7fLsemuIj3zydI+giNzpox1NcmvNUgZ/UgA8LkI8tOJvwcdEWDb+24BA+t1B2Kwg9b1te3d64 47WI3cCm1feohS+/A9m7V7Z3yj5PLIWjow4a2O8Gms+l8fDqxSBfGm9YUyN6IMyReF8z2Ip6d1GX K2wx/VSu+UF5hNmauCRlohtxdGvPSBYpoIR/cDGWhra8MFe0tsseKi+aqz1hVxx0WjzdBqQq9MtO F8ZZEc8tl4LH4xI+ZtMCFRCv90MbMsEZeUhuqtjZP+fmfrVNwjc9DW9ILe2exiur0xdMU8ukGJjz 8/Sl3cxHJjClRpZqiHySq4b9BL6kQYWcvN2poU9UVn/hdDVVCfqAWZtYYaTfuhyg1f/3j1Ut34fT yihbVMhFp+kDljNrM536QRPBVJSGvDJd8kJroU/XJ8aVOL0trE7hQDM+a5XJBLBYe90K3vvgdJKS NNH5nKDEJKVAryH8gBhpBgz6/SsdsvEPHNdtb6c6E/eZ6B4UAr+h7FPnxvl5oQeZW/OiKSQeZ8ZB 40BHkOBO2EHHEkLU5lW/1shSi3iluRxBhxEaijhYSsdwIAAeyJ8kNWLXHAMO08qczzWn/PwBIOB3 pnNGyli3Ii9i/UDYn+tU/+WsEinoLzFsJNGMCbX3bG/APZhtK1RmTY1GWwdy0XRCoFyVFXd3xvF9 dLGj363KvQxwxgvov1CaPp7GQlhGHaXpJ0rR0kS2xdbpM4CMKavphro3yKC/9r0X8loEAwBG2wDT tbZsx7K1qEthAcXut+Cth8lxNND6uBq/i8pRVYh++O9OK3LT4smFURrCC1b8QusWbWrS7i8Jfw53 IOQze8brFD6yTxlk7zKrk+ZumqlTlJuEVZCQiGWAuj65z976TUd0iVp3UpnyHaomIlSEy10gtyEm nP7aUQc69WKN7dcVvWhE1bNg2u1iI/5kPm2khbRIj8dABcjWISdipYuLD4J2L4KKLKJvQFERuoJc 0OpFg5e4+3hay9vgQ7DcqeGYYymoxPK4RZ7erYfZyrZqFH+RLQp3Pq7QPnRSfQhNVMts3DigKXOR HUYm/YjCMxKQpMNYwNaquvApeAm2XhbX38gY47ks2/Yh2+wHThsmIrPF+lAmaeT9EaYkd003GvW5 DXjpaaUAYePvJ/7mCLGXW8CUVz/nT7ezlCsWECWAM1EcH9ijsCYaXxl/kNxlVE0rnKL19N76eRZq +90gOG7k0z6W+J03pMjJ8wGPSiCenpGdeDSqi3WSKuXUkKSOtGhIEAiK6RZjJLkaCk5bUrqI+fZZ ETTUl/UeILwwvmJB/Ofd+DlVCMrl6GAxd48mYeBFOk/E6YP7b4skwLUsskW7D3sZ4EqI34Gw1To+ QnTcF/jszqMrzgzpvLmEtRZDB2+THf2oqGhxColHrCdHz5Zr6kNSBzTi7K0NE+7aVyF1YyYY9Sh1 CtDGjU1Bo9YgOc6l/O5q3ovLc0dP7Drxl5Ls73VxQvDMTpKexFYPe3JTJzmFvcijZCA7Y+2W5O3T aVJotHB10jvHfir3i2Wal6cs7Cg8i/f5N6itAAmi9mjD4SMiWeZav7MbyKSfZsuu7mjDGuP5On2S Egurq4P9C6Wl+khiyy2TyGlGeXQqh4gpwm74ASZ4pe5z2lueGy4nyqWMyWqXOi/Jom9c14SdNatr CXivYVMaauGvOa65cyoQ4m/n5D5QNWqK7Xzy4wKKr+h9uHnmWcgyykIP/E0pvGkYSAznED88iobM jbojhboaJOaSFaHpbPf+gDFiOc9Klz2d+b5/ecJuIFRA3j/Vrk6WWTYejTXV7OHQWCeUf5DyT6h+ iW93M2NjMbqhZnMulKPWewQzXPWhfWq5rHn6J5Hz376sph2PwQhtfFbLJGg9Z2zPx+5D3vjw4Vg1 a2ZiYg4TAtKFSadcZGrYpuRWO8ShT69mJ1cVvWElmTW25DxXAcBd7c7Ws7xCNHq1AfOF0sPkX3Je m4udjbJ8svWoeoCdB56oKU1P+Mdv2gbZsAD1MP0f5It/SBsWjmYvjgrqj2hfR7rwYzZ+XRptIFi1 iPlMerBcT3ql/1kCG+1j813sfe8aeh2X3urWoT16k2Nenft5o/qClEXuzM1hIbqCeATQsA81+dqb nIfhB9K7Fz7AHzApOyanW/H+cRKu64w4lVyVVTS86gaPi1DAtx18pXA+n+IqH9/EG6kSlzb5mYd1 Zpw7n78FyhqZaIA0DhImyZxDLnsDKCnGC814wBpwFp21Ag/2arq4zUkBBlvTm81ZtgayDt5SD6vi H8sak0Q53IytEqoNNGtww9W7eHUO/JTQ/zOZT3KNEAgAV4elfLeRXkmUCNoYy8tHT3A+FU4Z7Hm3 WNH4bhjnAh0YgtQLROJw6w31QVQjs5rWWrcsf29iYxHDCsXB0uS0DAqKNEYAMaa3oF5mJAQX1Eet BkVfd6ROHGY5XNiFR+1E35do4G+uh6jtiYdMTb+XgpDXyARbesONChkC3PXC5v+wHpVT5Y2hRpWv wdhUfBWiiUag5ZaCyHkr/bcYKa61/06507JDBhtI3QaYM8U5JsZF3F+RqamUPrKpKVEaL9P/MVcq NvQ+EpbPbRTKmXgxUkCVQaHODe8J/Ec5NGR+jRbpZd2oheXeTyY2AGUFcutFCXVDFEAqIBPJfgv7 eDd5QqXyGH6BFjz3VfMmqbuforTSi5VBvQpDuDUrp9UL2m16qfv6CVHCbN2PTnLPYHjue4segyjv +mMxh6YBiGQlMdth6v54Zt0JWM8YmRVh1vhJ7P46wmxvRw0s7593OwX1TNAKB18v+QUTvdAx8HZh w0AUdYbPzVAI3fe96D7Q4jVUi/o02LsOIHMki8KGmkP+70d6AqsaqgD3PnHy9LIhmbV4l+Ksebhk LWVrLVNTBBC0bObnzh/YlARktFUJ4sqAgf97URdKLi7oWg/PG6hfbjt0gPuAqDiZ4Uo2XQhB2/zb kRi2zWE9eEbUSThLGI1u1N86rVcYAnTBraEe2J84p9kAeY1KDoEdc+Fux0VB3bJV71XONqyrkj8V 2wArDbL3w1DJYbYfnAkdx/s+SbXtSTseYlRlN/nqN6RxugPiNbBcHlF9maO++/lNfbhDz6hw28d3 oING0J4AZmhL2COMTpJmKzbPIBHxksdLfjmfUW2AtqufRNSzsInEztk25XHImgti1PNDxVP4nSHW 0xxi4jqN2o6Jxw8bUw3G/8kyHxY4+9f8wEaBV/9vAXcIxqu4dmdFo8CRXOtdxLXWOGtM43HeuKbe LGO9rX9QGwbveO6ggj40Im//nm8ILgMDbP+Uv3BDoIEzFcWe4gxPZH+MVZJVO6EILbWqTMpEPKyJ eczlmfc7YU8JkKwlzpU9pw156KJ/ZZlRlWBeKxsV4BBp+HK3E8C9ZU/cKU03idNpepPLWJo6VIsa B807lW9yzph1/XxyXoOTvt1uJasd5FdWI9TeVUgLCW1e/T+bINFWG97THU6ZSQrk4AG0rac1ifPM JqYs/zT5OXmZ+MrDU22FAGymUiRDyqSAC9c1fg/BjpHi+nRECJ583GRK+4J51wbirwoRLNp7Qhjn szoQO6DP8p4JMd0f1oQdY5eHsjxvpQQkawBw2L7X8wg/LQF180nLNcmzMfPpm1nIGldHqnLu/aAa YLmRJY2WG41R+Ur8UEUTI5e5L79VttZVoIwJgNJ3jCmRerte3zvnqQZDpMNWuJAVUFJNTxJBKwZI I/UWNezr9V3iKtkUR+DpGMUZ3j/LvrQBplthP1BEc/eoGqXXf6hU/XvIQm0FAjCA/m1XytJu34fU IDUVCr9g2INizZxi/hbLWbOxWQYGzeBQM7A8959cyr4KWo59Q6+evNlki4iDSo/CJKGhhuohxH1q wU89SlxiBICdKSCP/m9a6QCIJ7+lYPA2dOuXNTV+OgCqJ3zY+UMf2GWBC2gFMJ7O5d+yv0aTbs86 IXw676crXCLkdJmDJOyJC1PaEu/7V5mYX+mgugV7DLVbdx7S9b42b8V5nC6/a55nooUUKgqxZ56G i80YsXsnpjtClCKx7BlQvZqJspWOAn1bk6uVVODMMSyzoZ1dKs03w3c7Y1HIQoaQgd7GBv+KdLXX kOhaIJ5/VWT7gh9c2BbiNzfUDJCY8HwfkPl/Z679TAXsq+1uF/mA58PN7sWjoMk5PYhRyyVA/L5S E7OrWQipLilr2MTtupMC6dxqA5aN2z0A+BL/N2Ng4yRNb66ICU8fDZHoJ7IXj3RcQr6qoGQ/bbe2 yI1qh5wSX2sA4Mut5evK/kswmstDCRL7j0kjOuXQqkaRuTKT+wMLw9JaqpTHn20H/ww6XwS1WQDl 9ShixaUVRhlmQ0LM7/UcTirDoSJzxRxLzFYbZQmMT+FD2mkHtMJiNkUpGPOZm+EjKtfK18z67emZ /BrfE2tkOA8ltnk9b+cAeniRlsRbNSDlD0NiQ0cFZIvkUUOYynmIcm6oU9scRxuNDdy92SgOurgg 0YnI6lHl7+s2NV0gPSq/iHE9AXrN9TZ5rHURDcH9fJ14Pd28Ss9waKqYdG6V5/W1rSeH7qB0HzYW 4yM2OH/lGKyqTEzdS16aJCVMQLehE8Q5fUMAADiCgLeQq+pYglfP+DIlEBiWa/uUEEpEn2UbVdyv +SLtUeKSUjPAsRPMa149tSuenuPLofsx+QDUOLwisFFsz/LgFJwIQ84Z3UK/SjCJaDSf+Bx0TTpE xXjthejqIl4XmD2juvHpMfluc0VOjK/7iRdRJqeUKYKs6eCCjtKEN5rN7CYxwBfvYSqevf+PBb0A PCpR/Z/XYKXQmnCXJ/mjPMQrAJ2kRzBvwT33nNb+xZ9a/o6XzjLICJLVIoykWEcVbNXmatxvNKfu BquPOkXRg2FFsCZnMY64yHDuHGWeok4oWLGHY/H6hCjCqVI+g2LTnxerILpRufYTb6ovJBm/YnT5 7XO0NU+3c27jzSNaj3J0I67P5BYxXMmsTbK38eeFvwpiBAr8966LM/0IN+zDXsTFSyBik64JafoD +t2lSJ2LT/PoBzy3m3V9sqmETnJs+hsU1PV8kW4K1vLlwIFDp1/Qf+SXTpr6w1/C4gvHnIV3v8Ep mIdV41fnvtTnrPoxjkUuaKRgY85/18iXwqpYtWZvxk1s+L+zK9PqlIsY57oV0jXPT+CmMV9PZQnt qCd/acVrBeRrlLr2thKZTJonuljPc6q/2Ls1ESGQno6vjwvTSgtUodGLHxY/vVtd12IPSO3yeZPq N4/Os5SlZgX5VPCLohFEFpk9kEuuZZzAl2wac/rtgmq7whbG6kUs1ttr1ai2u/MveLtFU+18HbqJ WhrXbbuDyOpPrUt2RxQqDJ36ypn0uIHh5fcuM7w5NO7mIgBksTGMTcETa4EgfASCPV7mO+tty5vI Z93WokcBm7Lo2AkY91ocTHC8da8u7UiBX0WoMe6Ds48b7BLr2kfH0Z81XS1Y3IF2mYtjXmDHWe5o CFIpmtKPtS/qKUMKrl3MHpP3Rq+i+yYLkTuHSOKIjgidr5ISOltPTSDWiFGfPLJ9Fytl7R2y4Qdz mzUcgz9OdBwCtelmy8bhCG4IRPFLey7PTk/IfFvrKFlWwy6z8ogH4L/vJuPWveWQYJsK2AvxD07T hKnN2sTTWcDdjb4dMk3E0DJJK9/CSYssfQCy1Gs6+5iFBXvmIpVisQ6yyt6Vv568/pn30Iyx8a+v VVA43FC44qa6jc4lwdTbneaq+MCn9JhmuZrVsGELufMvKXcnanNib6BklV77FAv+RnkDiqdloBSz 1G7gO1vq1UvGChlBOVDssWA68xXUTfzuquF5swrAt3fsqWdUNk6F5Gr6BQ61ej/p6Ayj6h+9XwM4 EOPb7M+vLKBYUbcIHCCQ4qa1JvHKY2j1MFWEzjP1NKUlavuvdFETawnhJDxT3bnX72Z3SEYbB1zb 069uiOE2azHY8mJyPkg0qlbpVeHkE6lPFB79Ffu0IVHKMeZayhrrUbuvY+/KGT6o8ScXEQdQXInX NzRxnS45jzvsNxdjKD3SZLWeixsOY/KvPt96I9LvN3kzY4VWqttLMrNBDlH8cmy3lHximtWp5pMi bhJRu57ng6x0X32CERd54iqQznw7oadVGWoBb6nvNxecKPbFc2icQcXWxHF/zRj4XjNTjm0uHm0R qzJgvJeDGYdCtHGwE5/UNbA2s1PTcmyVx6uf+Ixsy6LcyXuv28pPJCwimj3MBiNOeRIx5LkqrEo9 Gx7hYv43l2p/YoUcCEumXU60VLdfzly4xQw1V4ywFZ9ZxJsXlcYnqsYWXnyLKHt/YKwkQCWZk/GH wUXJZm/uJT3+KridC+vfKWiw4mmEX1ecIfDt8qAImPKLSociRTQLi5HZGRLJoXhPkQYr0fMqyKbl KGn8OZtBIlnxrW0jZri5fbn1MfMGzNAURNJQ/I1ndPz99H2M9CsFXhm6mRUF9zhF6Q5iYuK54wyC 2Y8pqTmQTFp6TFb2hHv4ub3gftjlG+FyMe6X4Ws+tjhAt4hr/juyIjf2eWF/QKR5HAaCt6sVE6Lc OCempAc14PaZVtIOkpyxxc5WC7Gh/jVno0SkcKN5zDJfrEBJ/9JuKVLNLFIT6pKlSnogb/15rVzR il67f5tzI2yHoJCtqGUAwo50LYwToWoAqCiywXjcoN6RIUOGW8BSRe8tcO4YDV/DSs/q8GaUjbgI ZbenmqkQ0wpfjuDIzfkbaTBypmc+Rv0xUe4F1tjbv3wEXb6GzeUnua8kMQ62HeJbVVAKBX0Z3LLK fmI0Dwl046FOg39gBL7ZhIHmE07OhCTnMOFmW7tElXaAUH0PeLfgtaOQSF5U3bRqdW0IJFnOdqR2 EKWTFlSKS0aBahOt4ymYgr2lOn0pSUcUilicZng5jXv8kY7tP3zOgTHHsawZg4IED2StWnnYwyL6 6EIyAwhZS3af0YlAv8KvD6vcL41MRq3zwNDn1EI5lqc2wFg8fTRrO6LFuoh7mesRfn3qoZvPPloX Sy5rGkSKvMSaVq393JMxu3pzwOlIoESC2WXmfLNTFRfa0Efuar/WrXvtxDhheePV9JRJC1VefrLU fcd4t97wlrdnbP7P/syblbRLV/l6X/XuqeQbAe1Bma089OiQx+4LaREP2uEEfMCw71Jst7M5eUrS jbfdALJxpYFyG/Vt8Ew7SXtE5mfW36udn1CSRnR/pwWDmSuN/cgglmYIz5oQDfwDiUPQNXSoOzoZ Po8TiaZsL0Ngh4bDmYMl4/6gxBgYf1QS1VrZFCvmHt9EJVxy13PLY1tCjqHqca5SxGYOyfiNIHvU uG4G9JQNyIm9PWvRp6ANFLtVLNrNB1qBwLy7y+nJJ9PH1bIMBJ5FMX6vFrt4iE/kEA+T0WG/M4jG PgooW4kQdsc+ND+E9hvGTHqvtuYcnLMGCj0cje1KMXLRUYJ0AGoO6Z+3w/Rg2U1RrAwwoJ+h/6Yz Eip78HlbOkTbLnUWDqG2oCbyNwtDaD0sS/7E3MQHDI71fUQmDbEhGsINPLAN8dNxE5xiVyxpiqJi uiU1y93QYAijZR34Gk8gIZ+7qG0Hn4Xue1JvCNG/JF3rSZStxwtgEa+ADcxcxDY0OQtj2vohayWI VlJX0AW50EH6ziaEfTDT5VGyxygyvTkQW99h1k+FA3FvCQ24o68JvyS7xzKpqG5PcwQnBaPwSlSb nPFj9DnHCG+Xj8+rxgQCKVVVUmqPypn65R0ejbIrO5OCX7agbTMad0a6b3qAXLyLRZmFtL3R2LIg NxGFYbHufOYvgFcMpm6az1KWB6EoI52oEjc200bTTjHRKzgQgF8B/flyhCKa1gUqbAGMWdN6Zhiy 16eN6+DLyLDqyz/MwQo2bTT2IX7ziuxXAiYB0S/pWcDZWNvEBhks0vCnd39f60iFHna5MOUGNFza 18UjctssRu0JB4YFhUJIeUIwrTar/VEPjWY5iZ23NJ9R7CGUUmsjmA2a4dD7PnBc5Q2Py7sfufNa JZMQlNf/l8BWk14IvSe15D8fragfwLx6/r+tjxhfXJuzzm8de8tt5QvY4DMFVYHP3AonmgLGLKGT nFeMWZMYx9bn9Ljy2vE0mfsNPXgikOuRQ3Sn5SYwACigPJW40HeUbFGTfkovmkhAsogiROFRjFrS 9QKvDiX03d35GstBpzQuq7RrLU0VNOtpbuHuM2bdi+klXXy2cyeIkvIBlTcGdtogEvoj+dHrfs3c tzPXtFW5b22EX9P6qkpoBf8/Xf9GoRDIEg33ZPqvrZVwX2TL+3GOqUJFo8EZsEhYBTDufu8lIgD2 3xk4u8ozixqazULCUVGtYAcHW7e0KFpQz8sxVQVNEf+pC6FlR4Cpvr9q+5JCzoYRIQcGID76uo13 xeoCjEn2A+rv24BLwqxPtRUmwmcNTuMeGBfDn8ZdUgaQRhlVyDQqJkDau+2OqbL4m5pu+GG+uS0a WuxlX6BBonGlmJQw9jxwAEMhqI8ReRuj1F4UWdIYZxDX9BuHGs/f8HcFQLKRt59ZdubZsKmpbN+t 57/7Ajqf55jPVhbN/K9yG/rqEWa3ivTOC3nOpbeFlwIlsd8lN9Anrc0UUww25YltsPwcMA3dvYfl EIhuePbbUnU5KbjSIW7olfHY09bdqIQ0qZMsiqCODRzufYK3mHEhwlk44kLObPQOLbk/zBEDPH5z DGhjj2COelUd/yGBEFR1JvAMdmlvumbG/6g/lbsLVaQPN7UVOffPftHPyqPFVw7kRoDLr6Z56dkO QGAcehDKCyhz/ZGEvMKVR3IDNmOAJLzFWvw3ra09/64fXkoUg+Jlgx87IOonYAimPDCTXyAWrbTg UcM23WUZmORLQz4sK//PwCdaN4xqzmI5yWuNOd3Fcud73IOm+beYiNFLYZnJEgtib/0ARw+cd/YY 9rVprmXvNY0gPql8AS5hHVrLFUMJjQQO58Y7axORxZhGmsA4L6FcZPWDJyn514IP5bI32fSG4+3U BednwnPidVv8b1YeHtnwRYq6XG/MUfMVPZ0Zk22dAfffi1G3Nm0njyyHLw7lfhQxgdUHHTN+I//j JxBXbSgo0Nn5gmjzlio1iEOZ2qZBiToKJ4n4Xf9LgjQcHdVCASkyKraC3XwqI6hh621pqOTAAzqi G6h5sOIzU+bGTS9Gk+NcucMhsYeSIQGAgdYu2v262kK63/1cEIL4P62KvMV+WHpPTZ+w+UHioaoI Hd0R7qVrmbVcG0DLrT+n+LB54XHeGPaMAOl7WEtNbBZYadrJCWgGcLJs91d9eLrhEa/JRiySxPDv Nh3nM7KYglWGRv/vqyf1bpax8Tn/vGI4cqObJgMzG2ixWZ4vwiNWbPQbxs9tmjt8YVkElaYBgaZi CBGtGKzLHbV+Nax3o6IDVM4Pv4ukpHXIclYgBJ1i8BlgqYvW8+FfALWhUbDRNmQEauVtxFrel+St A9Azb28ku+Xot4XqwlBJ8Xw0UUbTS6wgaHbGKLCndi3ZDAcVlsa3fVOamAvFv0bxm5jMbMnbQv1/ WZfdyvIoe3cw94LbSRGvEsDk11KTng76LfLVkAxVSj3rbpp5EqT2R0vB9vbj9eRs1iMxU4KV3+zv cYGnPJf3Kat9Bi9QhVNHjMDMLT3rMiXH7hHYp8VDWzYLZZuBCexp/4qoozpoEWykcieIkuX+fAFk YMA32unn/EVGFZeGMjg0oYojdM6cjZd8Tsd0Je0Lzk4pp5DcwYMh8FE8tJ6iTWG1BaOFDSBzpglm 4XU/5p5iPV1co1CmIGGx1rgWCsANm+RrNsV0l0VnAtyxNlyyJkZ2vvOPkaGTjOhdo1Y9PIQUZzGk 87xHTftVkuEfVGWUwTMPCijqNlMkkSwPQp3yAhEtN6oruJsO2296CJYGYJy1/Zp6V6/eYgbQ6BWe S9GLX0DobgPMJkyzaIcJwXEVj8J9FrYWrs8RFiRE4l4gh3cy7QogDiRhkD7nGSBxx7ltbzOVLx0u lB+FVFv60o79idFgAcBBFTUMPGry0V3eIx0Duep0KXqdqVrPa6QT/9YRZDCD/oTAqgcrwq4eGXGE l61pR/Smqa1wQNaUKZGPNiLtzRsVm2xYZ4c+TnkhrfTYDTNGdhCQ7h3293s847Tky3lYeuUprw51 IQN8KEuQ1yOsvoi7v5XmxmBKaeqOPCZoIkeH/YQ6vcQ5i28oLhIOVTCg5Z2nukUmaXmxFWcBZgLm nQk0Ev82pfN1D5tewqDR5Vb9795fqnAu5j/TRUlM3vzS+DfIdl174E/BmNTNbe8YrlpRddeTYXUg TQTrvIgOE1rW4RtUhKlEiX0PbGQYC29wKsgUoiUBYvnkUnKnpjY0kMct+vwIiZTRznqjl1ZeNAvI wCjX1Knzw/S7PdLZmdLizqZnnyEqV+SpOrlYAQWrgRFz+Lq6fc1Fz0pVvc3La+bOP3rk6n6uH2Zp XbThibKQidpN5sTGhNJEn9P4P3Pnk8XHpfkZLNc56l5J551T/eHRMls6kPqShDtTv9ioicCGDCoN qlx9I7zKOO35wFXzhssykIz8Ro5qY51tuy3m3YTjwtAFGAsvyO97297u3RZToke0beNejh4aiu0o MpebfEIxxdqJJhiPOu/XctnOqK6EpuIIfc3p7DzvmAYQWUqLBp57/17MKD3lw64NzUz4+m4Ntmyu ilN9bZc/Hv7CngccFYRglZmtmnlThvMGG9whwAnXteg6PuZUs6CE7mRKIMfanFbcwOc3xWPkrv/Z dvj0B0QVXWrCdIxhmjAhOvCpV5qiIM7pfLhZ6BQsZ4M7z4LKPa/gGj133NR1JBDYQ3hbjHPyUI6v W4dHGefLsOlewA6WiT9xtINIho2ZB2T1H3vcQ0+01YxlKFIFljPUSr6ttALWHF94Y2cXFkPX0gRl h5QzbLfrQzUpHMBfANXPDyd6heEQCUCbE8pJqOFpFFG/RI8RL9XD7XLcAq4HPlQ/PuG8mbJ/8hVY j14Ye1iCV2/FN9InlbY1mYJvzYNWqu6Mufhx1Z6CCm25uwn4Adj6ajWC5YzSW34aQAqceOtTfBvA +fxrGlCMBZ4dbeIS0axYgCfnT7z7efnGRuOFmdKlJ93RWCx5n4XWrpgGCTjPok04sVM6HDtfmcvK BVSZZXt2c9WZ6D0shTtNSXMxm2UJddnzD3QNgwQdR+tlPvws8k4UGSVZVoOcBuQuYlrLFPFePEfQ 2SLfarbPqRCMkZtFoIpUMduOW+WADwEd66EzbJeA5QRDb1mvb1RVrGzt/9tMdidVGqDgILKpr3q2 LJLnCydj7NXzwFjsjBhbkZjRhD05/KCjzz6BV594sFo/DPf/ZL/iMx2WDbWCX4Ic7Uba/gPruR9Z EL463VQ8R++H9PTtLV7VMGB9/h84bxuFS6Im7mOMdQ5dd5XElrIwynbsmWNMlObRkMqb4TIZYoOE g3u56sKOhWQBzC9ngzBu2m/1+OgoVdLwSkHFX6tVO3JmeZlq758CY1abBoNA0TX9ic8+FRBi3Rk/ +cgYHvWLqU/D3MRHKgSJIW3lJZWjHn+06+oHk2ciQJw2/cD/XQZTZK3XguHqXUZ7rhkzti8hbFaD qlncDGzkYBUJ8sY23idxAnAwDnIWRI0ExS5TvQ7RVu/Oevjaodev953V6A3mwofdvTl/ABJKwjag wm+J5Ie0VCB9dNNMp8OsjPJfwbBWKT2kPNSGlOOPhnvVBdoPWqXAmz5ITWSxZukY0XaN+UwhU9hZ fNjAe4ewhT9F/iTEFoZlyV0FiIKgOlR1pJMay6L4zR6887yzOiXw+5bszOL4/qZ0AVsLeRS7syLV l+Z9sZ1mfdRAOtTqop7eKr4CNPGboV4BsVohkX2fJ2mkB6yBujqkD9usCM+HeJyxm/GVMYH2rKe8 TkmrSttDfRDBGge+6bohtFFrgRC6nbCqwY8D7jFjnZ9udddUr2/jFtL3RK+OX5PmD7tbjhrafZtN TWoWqgcxBD573otToLUgfHyf8DIVsKt+nzLGmVbGsOpOEOrKNnh3+VZC8fT7f9+sG/7QM63Gbl48 6LmjVK3qgMWxhCNRuWTTHTFGZlXqCGnPUGOD4LxMjkNoM914EjR8UsH2LJRmFZQY4k2mBIsw9t1O ZzvJpiwUkQmxmXmSziJvjxQpUbZLp7Wnu1gUXJfeYRw4BEP/GbpVsHLX1utVf3JwSuOKd6gVlpXy 0x9bWVdrpZk3OFy/phMY8+9+bP3TPD/7FLurRvNwXyE9dyEX2sEfC9TAP3gvop3wE9yr1WWLOv2S 6C6uClo3OnOug0RsGdaJHsU+DfgV1x+Wt+uy+/ndia8XkyXNH/YM40IlapsO1/tU7sOsnxMCbNsO D6QiJNSJwy0f2ckNKvm7uyxmKyPbcaVRwiUqpcuAk7DKz1gfu1y/ETMNN45VVJoF9wcSdvD00GUI jZyV6jwmu7m5TiUwtLcuVBhY5eqeUxOmXZpJ8vFSP7mjxBMn/4PQ6AIbOjKPpxJdyxCQKtD0Mnm5 dT16RsZqOvmfxupivJaw6cJKD6OHujVjrpeRH1Zzhjhq8enR3k/FsfolfPlYWY/cYA92+8QLnDaU Mo77ls+DkRpX/HniAarEtNS0F3bqgPxjiVzS1y5nFDH06rQhQuGNfuM7reCsEsarPeQS8yOb82Kk jrYm2vyrJJuf2elTANLG0ds/DK15L+mcVLBG29CqGgOqtqRioQxn+dv7tHKlTU7tKacwdxCswkwD 5ugXvbDI8tJ7ZJ2KQO4DwI6QCbSohcRCwbKsFCfS3bVCcOiXOGQr0DRaQCYb6lcz7fZ7rW2bRwGF PGDJge1QrKZUFMMO1KfRgUzsszHj5zDJJfYKjPVxBLLd2px9tsTor5CZuPXoXgM6tIPm0GFw5gDq iH3YcOGyNf2oUItkVndBHWvbfZ6PKYgssI30f1uLDph0X1TBB8zBQCfeqqUfUJhYLd4gCDSATyrv mFN9QwRJm1lI4qiHE8cusBBp1y/jgcwwVTILwsBZjHYS/SOv6jfwerfdNqAjiOmNWD7DycT0IS3B eb8ucTG6SY5uwQverA8dA2WChj3M9bIx4N9MfOE8g7vPtGaot0mX53SyU74KGNOOH0ubuKt5skON z5ov+DatahFqdip4K1mO6Etzyl9bLCo20P2gCKDREPOu5pDZIjJRCyO7ofWhaxPMm3gdz2OJfBPT 2J/joNyZW+eCqMLeXe0U3N9EIgLI/JHemYWyejch7QJ0zgqBHzM0S47+V2Zlj4ka8RtwItFSJOts dt6ozqPGdnlwN5e5Tc2BBJ+sUYbICztMGDyocx/inP8PaEtcTPnWgtv2HExdujYjqKLQtdlpY/GG FrScgOnO+ZnWAfB9+GjJ5IJSpERgCJlYaaMsDRDm0mqjtDzntTtkVlnmN5Oo7AC7GQRLVPDVIEtM yC15s45J45B1Flu+7St6gTFbQMq7pSCHjYJ2UL4vI5vj9/RxiReQ2br7c0JzWTvSImUpffdYIxpV HskRFU8YT7ATE95zLg8eFVvLFjKO8JUXqpcgWyKdfmlcEty7x7EbnFreENS7IhO/fKDw4jHeOg8j dRcmGShf/8nQmqIwsLueKmvDqcAIMpjh9pu0Mqh8sd6hODEjJEY0LU31ZGPnl67vQZQzrRor3nPk LjXxslpwHXnji55CAG0ClBWJ+YeM6ONiUXVYOKodZ3YAlN2lFzRWPbxtHg6iWlM9YGMqE/SpEHpi kzyaKvPf//jROm+jUoFmXSFO/wXrW2BffxBZaF+umtEWz0/Yl+suwjO14XkXmk+NtEDEW7OjM6GN PduUNUelETdTrjrJXnfgyj/UogTH9PgiljIo+63a6XVW4Ip39/hNhpUFTPVeNYhcdYt7bpNiY7HK loosl0onJKFOlO3sDJy5Q68gSfvIS2TaN69ExkQQjp02ztkVq9Xbr0onYKZonLyXhkSsvdMSTlsJ 2GEavgGLQsClAfLtApmmPnw+tMl/qhLnWljLuh+JRYyBaDbM8+kT8+5zhjiz8y0VWwhFaGLhsfZn bPJB74BKIfFvjadcuT+LbJ2MriBnNzCCgEiNvubYl2j6VnLB+8ogEoGaqQ/yZxsS5auVLwY50CsW QpOQL2xJRHw07pA5nkVow04JIioreq7HjejGbN7sS4zUoPoBn4vjfhfpzmb4oSTtqP/EfBRW+cup 4RqaLi2g2N8bWYyvQ8lTLXqAFiBEpKq2iHx3AHGihwNPpghX4LnMHQVs7l6Jl6ZQG8qqjIt0ptpW 7jnlPLBY7G/nrfHdSAGf5uWaJrzVfG9bPjKYdH+orulxTQOZQ8cHQchT/5PpF1r5HzuMmRGdXv0U cMoO6IWv//bB+17+JdEXzcTP6CroKcnbsdfSvTs46+51HYBfBSHK099B1f0rwmq7pQE2raGNaXlv rBK5ZJXhr7yF0m+tVQ0lKj0U6RVAGZoVhjD2E+IICbWJ/aDv0lGBizZNGdgJX8YUgGWYEVb73yy9 QeS9n6U0Sgj+CZLgKoebK5kjdwr84NdQU6dDr230Loi5zXj21juQqW0ccIg2+lvr1Dzup35sViER S+tGdu6DZY2Fvkdc75fJzE7JpTzaecT7sPdYIv7Kc3thmukTi/zHPcN86Lk7c5kwTccKUn+87w+L y6fhxSj9cNsoVmy0rReIiJh5iexuPHT+EYx63523+xDleUOKT+J+d//Bv/8ph+xjTviqnaMdED2b ehDASKpCW/nmHFtBDPztCLp3DAQ1acaTtcQCWdGX8vreKTTs0XPqoCMbiuvGHpuBIge4Dk5ZGiNb MPoCCqNIoY6Sn1ObzSVBqsPiNwJzSkhpPmhxKiQehiB7xQE3+akLdwDfFtdw8LSyFkuvmxIx/rcg O8aozW/bOEc0oSdYuxA6Ne9bOqRa9UMQ+oQlhJWVoIe/RvDC/MPXFVUVtP6JzT5Z15OQmJv/JWOK FN6IqkcCl226uUBn3meoXr2xwR3kVRvwaqs/POnSktsvBuHiKOfaIkquspbwos6wYDbkIUXl10hN JEp0eO4kzIXA3Ou4VdMiwkcXFp+rjgPnn2n09RhnQNS+nX8dOMUjHmT7d70R1tOHsWvY4doFibJ/ Zy8LmDNXLBvw74XvWnqmHEd+GF3Wf1cRS7Hjv9x+AXBJ7M8kwKFBs0d9BVc9JVhqjVv8JGia7fbM mOjKelbMeznSWtUfCHin8jyrIWKYfUumc8w0jMRHf9flBuxZNKrhcPiLzRJJU8bOWTC8LFcBYWwZ 1hvScAfoTpGDU53ovaz996oG4Wj5ChmU5GTKQnb46KfDkUW9adIWn2nH+f2igOxkbDBsuCJ5mTvj W7xf7eJXp4ASUDF35yZ7aF73eSqb8HL7qJzcYt/1FNniX55YYw+A4KeDLk5hhQSGYsk/cORxcPvd RsS5a3sLF3Gp919IcTW9lB0keb9VdUGr8iXJAygn4G5ms+s3yt4oL9LkJntkLBmp7nBnoj0S/QjD A4WbWOv9Mos7PHCgkmJCiMTIbvXHXCOmpBRH4+WKD6cw6AkNyV7bAG//b/SXAsdt0kho/AEVo2Q4 Iw/jHAJ9HiAIUnlp4fIBwbjSh+A98ubdJafnSxpT7bXOoUTuwgzqraXy5vhYclXdm1nw6bwpB/Pg TIEyQYN3Z8s2wQU3xrrTNdNfAnDi78Swxmotep8vOEbU4SzpKvqEf6lH2U7Ix1VodAGFiM2LmNhF JgjCqLhCosDLfy4sY0nvH2ewlDg2VD/R98FxxwjiHMbZW+l17SHRYw7DP7FOMAG1MjeU6VDvhAcc 8iJc8xe1bU6tiKPonXNOXpcDzLZn68af1+sVRPXjF3/M4u8M77JZE+sWjavO17ighpeTsgD5xN2v fu4SMPDIgJ4q24i1WXWmUKfeTPKXbTqg5pAmG+d5H1R1u47xHBzP9AXj6YdEf4cJZDRjdkgwm0FX N96q2q98bloDeHMIsuSndBHxshPqcTfjs+AUpsQ09Rd00BCd51JrVRHx15ZkpukSfRF9wXy12To7 T4e5/HS70TkLpJp4E1Cib9nCrSzL/1ZW4z/cg9J1O1KsDE9ClhOig+oWhUivoq0W3PHFAmGwBMXd xmjuUE1THU9ehI2I6VeVDaA/2/k7BMOjP7U4vBeHQytPMyxwZnwNPn4/wwwHAiJ712qSkq0sF4lh zYEnRiyy7GgvUwc8TBl2aD38mK3aq9xgBSuQnGwxxcWtkKUBCSV16uJW6nJUDYecV7DQMKowxP2w jvq41ZCS4biEwmG5McMTI4I+hqS6Bb5bJFYS7YAQVBGbiJ2VxjGjSTbv010C8S2sGy7d/glmtM7w WF3qQVvrBecDd4AKG3YT4zae4e5d+Vgg+SRuVVqK+5PH0XJvlUoF0ChgNaqU2QmRh4YTIgfXWcdz s1LU5k+hEh8zOnnhPFlY+f1kGKFNi/udkld+uP9ziwdDEbBeNP0KIVc/ujSGg5KeThQzlkv76XD5 MYITUxSgoGFLE5Ufc2LigMhgp778Q4RLEuOe2pi5zuCehdrOvsCrZxGTg8KEiNeu5Z5Nw+aeKlRe DV9F3E37bWcWR33ySqeVlqUz6okkYCiZLpkHysd9LDFnn7dvlebcCNazr6iqBFNjAoYkmmEg5Ppb saBv/4gOrFXYbH8aQF1xo7lHzGTh5W04TQD/aL9avRhS21vLPQ0asvRzcIrpRfOmuKoX5w20N9Nl BycAKX6Z9yd64HLK6zUSsrGz4pxjfQQ5jnlsvk81MqD8b1D+80Kp3TEVFnQNhC7IS8EpObR4dwrP g2G1VQiG+Dt6SAivl5BubpXzCjrXI7PNOqYtWo7suImiR4N/M5XxxtNuY2XVFKh92musBCQLoRlB TsH/kExLJhCN0xSZdIcpRJy5699ZLi2FWO2hD/V6/N4cYownOBneCWuENbb0N5ZmMUaR+oHKy0hw 5/kyAS4Wakaj02KZYrLKtVrDuB4Kmlr9PTMjOqNAlxFtA/mgxPyusU83dbRsn3Tmii1lrDewNbiq 6ABobtL1R36T2NddbYbVziil4aMXaQudShlTtJ4c3JAI0tuUVxmIDrl7U0Rrj7C9iRqiI1vIUt+1 N1nuB9tcIQBALa6b/9jEDQyGa2i2HAke11mZXtToqWBSAyQpBtUrOOjPjfhGYo3bA+UZUhbiVN+u xupU/7okziey5iKNOmNXSu5Wl2CQecWnhV2A0RcsjiD0K4IrcsIJrBflRQGvirBHXBUK3ZadTJQP Fy7Vh87AKXMqkS18WtXdrp4bLCO6gGDNkkmZsH8+JlCf9jvfJfDcd3xCRQlF1wBTCzTh0ZR1uUR2 IgF8KXddvTAbme/abv14oFGwrEevUyr0G5ieFdsUpdDo4U1QJQqbkgNtPH4vAVyDyOhVKZq5CRXI iK4OgmfPDHn6sAxz+uWHiGH9Ll8pEqF8Sir+AsGWyxcIEGPOv0nmF/8+vjDULQ1/KW9zZj0If/f3 zjvRbCEsmi22VIpwD53gQAacc/aGUuTQM/vvUo0E7Zziu7uLEkBOX4PF8ExyFAxWjhYdZ0+WxRdt mgGIsB4O9jtewzmU/01qS/jPTHvlHqTpqlGQ4OxVKDLS964zNRqRm726XohoGA0W8ebs1QxJ/AV4 u9QFAkSHvP4DcrMewBkJoEXKyzV9szwYkPxNOMraPmOLcnEa1y4uXFCrklTe/1us3BivxDDxfCgQ 6s8AP7WvhN5nl90t1unMjTMcoEizS/SnJH6ApOAYD7CYF1XnScbpvr44tyjS4X22fBohMfKTWtp8 nxAfTeOljw/g1r/V0XeHeu9y7sYJt9Fg0qeI9WncQ5FvzU1TQ/3PAe/a3/SivMhbLXoLTc1BFk76 k/zM5ydvN0rbKLtN0iKuuxriaNGvh9EFfuQYitxc1FDTpq2lCfPzaY727B2UVB19laQW+QudSBy3 shSOd4FweK+fOelfRHp9257hmD5MtEqftc38akAB/LVXVN7Gsnq8O0/O0+il4QsGuJAmgX50CJM4 UjxObLpsRNY12SMh+GGwXzIcysVlU9mz7Xve1R8T3XEEVXIWbHmIWIy9Xk16tze33aO5uBRjcNW0 wtGcCaDyGnSMnImUeQrymnjPKyQoAcBH64JjHXJP/WBbCluZxtfT74GNkKoVQztZxk+ToGY3Si2x SF826SM2iywdZoYGtJCClKWq+UQWP9RuEyFqRZzBSJpoSrv8Yr00PS4JWRSDvQVwa20MCRlq/HGe KEHvRtW2bSLLj88qKBKI7wxNUcxAmSjFLx6rbDpacMcqvmpR1pVRNvT6WuXWv3Vsh2YP1buxUBaf BH9qTHPaNkFKaO6Gl5nG/ZmXJ9SESUSdAZFbJti+fof0lo3IzlZyne5CNR7GAfRQluV+EY/kozno k3o5Y0G3Cc0c9Rkl0x7o1kt92dc2Q7eq75+5hSLxhFJHMkBXeHQb6WooTvBTYj4WM+FcLfhGwuAO woxk7ZNEPtvBKwV7ieFScF55fGtpoO2Sj4F9fdvjw6BueHydkJ/48t2ZcLMNM5AGrJVXVtDn0VfY TSKovzfw/4a8F9pndzWdwPJT++OcW/uBpxmSXqWCuUSGjPFWIJMaMcQZpr47a9qvDQVbHJJIqQ/A edGHvXRESKkwBu+G2jR6JG/es670OICFyYZ0xjixjSIH3/3n+/+QDtMoakyD/okfkK6Hbgssc9T1 yCGgVs0E+5oK4W/rO8hSLDnG+lMY78v5sBusid927aG+cNsb17avY+XQmykZEgRrNIBv/V5HPu3s MMiZSEEu0broZFGzoImlj+QbgjJ5OZjizIi8nsK5zhdMocKowwVUUmlH5GGciNRrZkJAnouuz99V FLaKd/k6taYSRDdcL2UAxi51+O2fT9UrKU6EY+oDbBfhhCSsGzU9Vw9NviRlOrxWV9vXK21d86q9 PygOSMlc5oSkaNgEtPUVYCEzElBd88QBfUPBPQZL4PgHHGwSSTehTONzMqgPe+DaYRQLQY6HNpVu TQmRV//H1HpzrpmLpipHA+sD67xzjA1jgwI9761n9oZQl2j/TGw+4LDJfKpWmkpEGKKSqQDqAd6X 6l+ITlz3SUuqy7cT/zC7sHYJekOAF92+B1B05KRJ8rtceHEo0iuDID/BgqLqUPSDqf1bPC0yvi5O 4dJCzA1MnsxIY/a45M64xyAetYaReBPRbmvMgYriNh9IXkRwvysnx3mqehIxYU7Ivbg8YSX4gaNx OT2F23qUfI3Dsb3MP6EWCMLlnCsKnPy9UHUZEGBR+5bVk+Jb2S17zQJA4LJE5j9smmYQtu8b793/ yz/8P61FF+6Gxbp/dPCWFxx0tBPAgMoKNgRi0szmFToixXRynUctWK4K86h+wLO3nawvfXLA6aEQ CV0//vjzhLleH364829VfBPHZwmHXB+IqOqiPsfO3YlJ6xOGr9+3Kcitf1b9Tr22VMKUb9GZeq1L T8J58SSe8AZVjwxqPpFu/HpJ0+EIISNwTxmBugLoMfmVT/0HPMfVqj4n5aT66FwbemWdkkPJG65Q /02KkhytTSKPkzLdEnmCsNOqIj8fJVJkQsH7++Uhd3A9Ai8sahx5/mc0vxB9NzK1DYAX2kbbHtB3 +nCXjf1R9bsShVTG9we8TdnQmM2RyseGIQ4x3coMrt2Q0Ad7/VUDdV83PhCZptNAckdC8/PMusMp McZU05iGQDEC8TYgC8chmhibR/74vfFv3X9bigQeiTsto7YYEEKntPFZkDY2uZyxyeP4PJJt0Mh1 WBVYD++NAx0kstH1VyLTCwaEqMKwj1pOHK6fC4hNBD9lZ9var8KfjhxHczuSmf1Ph1gWMRZpS1av 0898fBzE3rI+yQbxYIVMR2fndQ9dCfCz179N5KLCQ6z5CY4vr6YlVukFy2GlUUAixHXmtYW5K3qf BBYRe1iZXMjE1d/1D9GI2NF4+MoB3XrKl0nFVgMxA8dErJCsw7o40llBG8b07RpKpb8Rq8eBFIHw l14uicuA4E0VGD/A7koNiR9gnLxOPf3gFa4r4Mbly0txd86W4Of95ilIAqawunoxFTrlaAQ9tTkz 9nThHIpa8JV1hKIp/DV3oAtKEfJtaGbAWr0zpc/HEfN21XsxX5ZsUy+7TlV6CBSz9DL87lDROrJh aQlk82sd7v+LVzteZfFTfM8M5KD83zuSW9XwB0ucjUjW5DOtjDPgl1YRlgn213gty3eOKoX/mFMI 5zBMYnoV6yanjXASz+O2ZLLCPrhRqRRvYTyAuJBXDw8ES7xkllKlY1H4JpjJtYvXVaRy3TCACHrF gZs3dd75JJv9fDhl1oba8XVvQwh3yNnrN+QaCvfIKTZv6HAFXkTA5t+mgkDQEt2kgyHzXG91caDx 4520YdPKTwKm8l7LuUywm8ciHrsuqhTz1dfm5flD4lzQzLM0Svlf3Nt3qwkg2R7sooNEv1SXUM9V cfYoLcXuHOeiOQEESmnbCFl3pYibbQezppwYlie87/DQOz40Bgg1aJ4ibAln5juaPbYnKwzIxfAF 3mt+yk1eiaAuXtJ3h8BXMwJZzLvl5tTXPYT1QvPlTWq1+zN4zQc41J9QkVCl44jtLruKcd0MZCgY F5KYA3QncWM0wb5uN6Q71r3ARdVN02iAqjo68heE3b+SShsBDIxxeoSuXEOhIWe+qbYYLkXKYXRO VJS6KvZTB8A4eR0KBw6wuCx6kpt8FI5y1XhhDMgn2nIe4Qu5IJeZoqJPV5w+rqgiIZbvAbaPT1Jb s2/dVa1xEX6wTcPL4faQZy+JlfjJKRO2vZpFENJI7cVz3SE6DOjWbmhQCG9UnW1N40vvdlKHT4tW p8+AELrmVonL0cmQXfOX5Jma9ZfzQIq3urFXBJ9xu9BcrTX+SXyBWzhWMjodpVVsK6Cw/gO8d4wo Enm2O7iO6aqip6xk0RbgerUrUp1VzAU3K8NDT1N3vEGnox9rZS/uf+CRER5yjdy6ujzJhvpiPEVO a4CwP/KcE3bHXnEVAdS8ytJyZFOGx7qRERjfywqMgOBHO+xLSs4fO+kXX9XQvoX/Z/z0G4EFR9BZ wKAZzxTIR1HbVQJcAVnBb0RIFKvgwliAHCiSwphQ2e/AySivdK4iN25Bx/BnkBvu0c/l `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block FuX0cSXIEXFEyJ6moxnlgdQNhvJUPZMr8vFVIQUrNLsDf2FviOIs4Jhh/CHFvNoFhP+5FF35v9LO dvh+bZPjoQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block S7tTbrlKJAdaschfwlJOPPdqEsgXhD6udlTi4wWj5WF48TMYe9G1VhIVqnCUHlUnL25oPaO2K5yW Vsk8AI8Bo0/VgZ4dmHFlK1nLKVEhAxpkFlhDaWKr/0O8btUKmCpbottVQX8Qc/QN/1xsB+cAtQVI 4p260yv1TVmYXmjx8rk= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block qEKqr1fSNjUXpQ3XWX8sKOKuocUUtDBtmTHImw8Om59DsOTw465CcJ6o2q+FcioWMvCRzAjZ+xxu AagB6t20IwVcnzoYE2NAv0kR5lDRiYhvN+Oa/s6UbWb3QTRoReqitNNjJrPzCw4XlCugY6l8lFOv e7CBsRKyMbLPzBTafQvYte4TvzLzOu+s2dZBgpeCmQ5oYGoP3d/E36DB13G2B4FF6q/prcZZNvxK 4pDBg7V2LvnQK1jZPTXaJEoulfO5Z4SIOiuAtfw9/unGEeLmG0aYcKYJgP/IxwH+qnHpwfqeRJCE /1Yj3BTLU7qGqTaWq40DGwT1+OerbG037PqDzQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block rqwqoJ665sQ20WMl02BGOPGHsf2aOUmm0G44onTO+JCu6o+spEGLBUfjMbBUcisRkELriGp+LU07 3cpKcEWYCGaCiotYyP5gLJIzW8NEENlr8yzJbZ8X/3ucAWlDn3zgCifC7D62tLYynXwV4FYxobEK 1DRAdCxmk6rU46uF9uk= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block eAiRCiDFAwDHAkcVLm985ZKYRnlElWX2c1OQg/hb7b1/zSEe2QBQQDB2N5VMdnfDWPIHLEDgULZK Pr7q9ZNUZVHE8Ke1zx1QtrmAjpCWyKYPSFSm8TXhERQqUDMjMTfRQdMhCqaeEGMDnfobIkisLS1L VRbUbeW7BucMesxRAk0lchUSd9Ot/ZA2M0IehYzxFpMFTCCVcgIcya1yjJFGhThRi34AcPtyOjSU 6Faaw0NdnB5L/vvtnpTBy747RdQ4T9ABWjubiJtZhydXYGF8KL1jkgpTE/c+t89+50pxoP6Tny27 gcEgvMCVqc/YLEqHUwQno+u+caWqhfW1W1s+QA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15840) `protect data_block OhRN996YhWA7mwFITWd/Q+Uw9orS4fv4vz7rKHTu0pokFrEx2UEFoN0Wq39LgDvAn+MIN4Rr6T2I GAu7fLsemuIj3zydI+giNzpox1NcmvNUgZ/UgA8LkI8tOJvwcdEWDb+24BA+t1B2Kwg9b1te3d64 47WI3cCm1feohS+/A9m7V7Z3yj5PLIWjow4a2O8Gms+l8fDqxSBfGm9YUyN6IMyReF8z2Ip6d1GX K2wx/VSu+UF5hNmauCRlohtxdGvPSBYpoIR/cDGWhra8MFe0tsseKi+aqz1hVxx0WjzdBqQq9MtO F8ZZEc8tl4LH4xI+ZtMCFRCv90MbMsEZeUhuqtjZP+fmfrVNwjc9DW9ILe2exiur0xdMU8ukGJjz 8/Sl3cxHJjClRpZqiHySq4b9BL6kQYWcvN2poU9UVn/hdDVVCfqAWZtYYaTfuhyg1f/3j1Ut34fT yihbVMhFp+kDljNrM536QRPBVJSGvDJd8kJroU/XJ8aVOL0trE7hQDM+a5XJBLBYe90K3vvgdJKS NNH5nKDEJKVAryH8gBhpBgz6/SsdsvEPHNdtb6c6E/eZ6B4UAr+h7FPnxvl5oQeZW/OiKSQeZ8ZB 40BHkOBO2EHHEkLU5lW/1shSi3iluRxBhxEaijhYSsdwIAAeyJ8kNWLXHAMO08qczzWn/PwBIOB3 pnNGyli3Ii9i/UDYn+tU/+WsEinoLzFsJNGMCbX3bG/APZhtK1RmTY1GWwdy0XRCoFyVFXd3xvF9 dLGj363KvQxwxgvov1CaPp7GQlhGHaXpJ0rR0kS2xdbpM4CMKavphro3yKC/9r0X8loEAwBG2wDT tbZsx7K1qEthAcXut+Cth8lxNND6uBq/i8pRVYh++O9OK3LT4smFURrCC1b8QusWbWrS7i8Jfw53 IOQze8brFD6yTxlk7zKrk+ZumqlTlJuEVZCQiGWAuj65z976TUd0iVp3UpnyHaomIlSEy10gtyEm nP7aUQc69WKN7dcVvWhE1bNg2u1iI/5kPm2khbRIj8dABcjWISdipYuLD4J2L4KKLKJvQFERuoJc 0OpFg5e4+3hay9vgQ7DcqeGYYymoxPK4RZ7erYfZyrZqFH+RLQp3Pq7QPnRSfQhNVMts3DigKXOR HUYm/YjCMxKQpMNYwNaquvApeAm2XhbX38gY47ks2/Yh2+wHThsmIrPF+lAmaeT9EaYkd003GvW5 DXjpaaUAYePvJ/7mCLGXW8CUVz/nT7ezlCsWECWAM1EcH9ijsCYaXxl/kNxlVE0rnKL19N76eRZq +90gOG7k0z6W+J03pMjJ8wGPSiCenpGdeDSqi3WSKuXUkKSOtGhIEAiK6RZjJLkaCk5bUrqI+fZZ ETTUl/UeILwwvmJB/Ofd+DlVCMrl6GAxd48mYeBFOk/E6YP7b4skwLUsskW7D3sZ4EqI34Gw1To+ QnTcF/jszqMrzgzpvLmEtRZDB2+THf2oqGhxColHrCdHz5Zr6kNSBzTi7K0NE+7aVyF1YyYY9Sh1 CtDGjU1Bo9YgOc6l/O5q3ovLc0dP7Drxl5Ls73VxQvDMTpKexFYPe3JTJzmFvcijZCA7Y+2W5O3T aVJotHB10jvHfir3i2Wal6cs7Cg8i/f5N6itAAmi9mjD4SMiWeZav7MbyKSfZsuu7mjDGuP5On2S Egurq4P9C6Wl+khiyy2TyGlGeXQqh4gpwm74ASZ4pe5z2lueGy4nyqWMyWqXOi/Jom9c14SdNatr CXivYVMaauGvOa65cyoQ4m/n5D5QNWqK7Xzy4wKKr+h9uHnmWcgyykIP/E0pvGkYSAznED88iobM jbojhboaJOaSFaHpbPf+gDFiOc9Klz2d+b5/ecJuIFRA3j/Vrk6WWTYejTXV7OHQWCeUf5DyT6h+ iW93M2NjMbqhZnMulKPWewQzXPWhfWq5rHn6J5Hz376sph2PwQhtfFbLJGg9Z2zPx+5D3vjw4Vg1 a2ZiYg4TAtKFSadcZGrYpuRWO8ShT69mJ1cVvWElmTW25DxXAcBd7c7Ws7xCNHq1AfOF0sPkX3Je m4udjbJ8svWoeoCdB56oKU1P+Mdv2gbZsAD1MP0f5It/SBsWjmYvjgrqj2hfR7rwYzZ+XRptIFi1 iPlMerBcT3ql/1kCG+1j813sfe8aeh2X3urWoT16k2Nenft5o/qClEXuzM1hIbqCeATQsA81+dqb nIfhB9K7Fz7AHzApOyanW/H+cRKu64w4lVyVVTS86gaPi1DAtx18pXA+n+IqH9/EG6kSlzb5mYd1 Zpw7n78FyhqZaIA0DhImyZxDLnsDKCnGC814wBpwFp21Ag/2arq4zUkBBlvTm81ZtgayDt5SD6vi H8sak0Q53IytEqoNNGtww9W7eHUO/JTQ/zOZT3KNEAgAV4elfLeRXkmUCNoYy8tHT3A+FU4Z7Hm3 WNH4bhjnAh0YgtQLROJw6w31QVQjs5rWWrcsf29iYxHDCsXB0uS0DAqKNEYAMaa3oF5mJAQX1Eet BkVfd6ROHGY5XNiFR+1E35do4G+uh6jtiYdMTb+XgpDXyARbesONChkC3PXC5v+wHpVT5Y2hRpWv wdhUfBWiiUag5ZaCyHkr/bcYKa61/06507JDBhtI3QaYM8U5JsZF3F+RqamUPrKpKVEaL9P/MVcq NvQ+EpbPbRTKmXgxUkCVQaHODe8J/Ec5NGR+jRbpZd2oheXeTyY2AGUFcutFCXVDFEAqIBPJfgv7 eDd5QqXyGH6BFjz3VfMmqbuforTSi5VBvQpDuDUrp9UL2m16qfv6CVHCbN2PTnLPYHjue4segyjv +mMxh6YBiGQlMdth6v54Zt0JWM8YmRVh1vhJ7P46wmxvRw0s7593OwX1TNAKB18v+QUTvdAx8HZh w0AUdYbPzVAI3fe96D7Q4jVUi/o02LsOIHMki8KGmkP+70d6AqsaqgD3PnHy9LIhmbV4l+Ksebhk LWVrLVNTBBC0bObnzh/YlARktFUJ4sqAgf97URdKLi7oWg/PG6hfbjt0gPuAqDiZ4Uo2XQhB2/zb kRi2zWE9eEbUSThLGI1u1N86rVcYAnTBraEe2J84p9kAeY1KDoEdc+Fux0VB3bJV71XONqyrkj8V 2wArDbL3w1DJYbYfnAkdx/s+SbXtSTseYlRlN/nqN6RxugPiNbBcHlF9maO++/lNfbhDz6hw28d3 oING0J4AZmhL2COMTpJmKzbPIBHxksdLfjmfUW2AtqufRNSzsInEztk25XHImgti1PNDxVP4nSHW 0xxi4jqN2o6Jxw8bUw3G/8kyHxY4+9f8wEaBV/9vAXcIxqu4dmdFo8CRXOtdxLXWOGtM43HeuKbe LGO9rX9QGwbveO6ggj40Im//nm8ILgMDbP+Uv3BDoIEzFcWe4gxPZH+MVZJVO6EILbWqTMpEPKyJ eczlmfc7YU8JkKwlzpU9pw156KJ/ZZlRlWBeKxsV4BBp+HK3E8C9ZU/cKU03idNpepPLWJo6VIsa B807lW9yzph1/XxyXoOTvt1uJasd5FdWI9TeVUgLCW1e/T+bINFWG97THU6ZSQrk4AG0rac1ifPM JqYs/zT5OXmZ+MrDU22FAGymUiRDyqSAC9c1fg/BjpHi+nRECJ583GRK+4J51wbirwoRLNp7Qhjn szoQO6DP8p4JMd0f1oQdY5eHsjxvpQQkawBw2L7X8wg/LQF180nLNcmzMfPpm1nIGldHqnLu/aAa YLmRJY2WG41R+Ur8UEUTI5e5L79VttZVoIwJgNJ3jCmRerte3zvnqQZDpMNWuJAVUFJNTxJBKwZI I/UWNezr9V3iKtkUR+DpGMUZ3j/LvrQBplthP1BEc/eoGqXXf6hU/XvIQm0FAjCA/m1XytJu34fU IDUVCr9g2INizZxi/hbLWbOxWQYGzeBQM7A8959cyr4KWo59Q6+evNlki4iDSo/CJKGhhuohxH1q wU89SlxiBICdKSCP/m9a6QCIJ7+lYPA2dOuXNTV+OgCqJ3zY+UMf2GWBC2gFMJ7O5d+yv0aTbs86 IXw676crXCLkdJmDJOyJC1PaEu/7V5mYX+mgugV7DLVbdx7S9b42b8V5nC6/a55nooUUKgqxZ56G i80YsXsnpjtClCKx7BlQvZqJspWOAn1bk6uVVODMMSyzoZ1dKs03w3c7Y1HIQoaQgd7GBv+KdLXX kOhaIJ5/VWT7gh9c2BbiNzfUDJCY8HwfkPl/Z679TAXsq+1uF/mA58PN7sWjoMk5PYhRyyVA/L5S E7OrWQipLilr2MTtupMC6dxqA5aN2z0A+BL/N2Ng4yRNb66ICU8fDZHoJ7IXj3RcQr6qoGQ/bbe2 yI1qh5wSX2sA4Mut5evK/kswmstDCRL7j0kjOuXQqkaRuTKT+wMLw9JaqpTHn20H/ww6XwS1WQDl 9ShixaUVRhlmQ0LM7/UcTirDoSJzxRxLzFYbZQmMT+FD2mkHtMJiNkUpGPOZm+EjKtfK18z67emZ /BrfE2tkOA8ltnk9b+cAeniRlsRbNSDlD0NiQ0cFZIvkUUOYynmIcm6oU9scRxuNDdy92SgOurgg 0YnI6lHl7+s2NV0gPSq/iHE9AXrN9TZ5rHURDcH9fJ14Pd28Ss9waKqYdG6V5/W1rSeH7qB0HzYW 4yM2OH/lGKyqTEzdS16aJCVMQLehE8Q5fUMAADiCgLeQq+pYglfP+DIlEBiWa/uUEEpEn2UbVdyv +SLtUeKSUjPAsRPMa149tSuenuPLofsx+QDUOLwisFFsz/LgFJwIQ84Z3UK/SjCJaDSf+Bx0TTpE xXjthejqIl4XmD2juvHpMfluc0VOjK/7iRdRJqeUKYKs6eCCjtKEN5rN7CYxwBfvYSqevf+PBb0A PCpR/Z/XYKXQmnCXJ/mjPMQrAJ2kRzBvwT33nNb+xZ9a/o6XzjLICJLVIoykWEcVbNXmatxvNKfu BquPOkXRg2FFsCZnMY64yHDuHGWeok4oWLGHY/H6hCjCqVI+g2LTnxerILpRufYTb6ovJBm/YnT5 7XO0NU+3c27jzSNaj3J0I67P5BYxXMmsTbK38eeFvwpiBAr8966LM/0IN+zDXsTFSyBik64JafoD +t2lSJ2LT/PoBzy3m3V9sqmETnJs+hsU1PV8kW4K1vLlwIFDp1/Qf+SXTpr6w1/C4gvHnIV3v8Ep mIdV41fnvtTnrPoxjkUuaKRgY85/18iXwqpYtWZvxk1s+L+zK9PqlIsY57oV0jXPT+CmMV9PZQnt qCd/acVrBeRrlLr2thKZTJonuljPc6q/2Ls1ESGQno6vjwvTSgtUodGLHxY/vVtd12IPSO3yeZPq N4/Os5SlZgX5VPCLohFEFpk9kEuuZZzAl2wac/rtgmq7whbG6kUs1ttr1ai2u/MveLtFU+18HbqJ WhrXbbuDyOpPrUt2RxQqDJ36ypn0uIHh5fcuM7w5NO7mIgBksTGMTcETa4EgfASCPV7mO+tty5vI Z93WokcBm7Lo2AkY91ocTHC8da8u7UiBX0WoMe6Ds48b7BLr2kfH0Z81XS1Y3IF2mYtjXmDHWe5o CFIpmtKPtS/qKUMKrl3MHpP3Rq+i+yYLkTuHSOKIjgidr5ISOltPTSDWiFGfPLJ9Fytl7R2y4Qdz mzUcgz9OdBwCtelmy8bhCG4IRPFLey7PTk/IfFvrKFlWwy6z8ogH4L/vJuPWveWQYJsK2AvxD07T hKnN2sTTWcDdjb4dMk3E0DJJK9/CSYssfQCy1Gs6+5iFBXvmIpVisQ6yyt6Vv568/pn30Iyx8a+v VVA43FC44qa6jc4lwdTbneaq+MCn9JhmuZrVsGELufMvKXcnanNib6BklV77FAv+RnkDiqdloBSz 1G7gO1vq1UvGChlBOVDssWA68xXUTfzuquF5swrAt3fsqWdUNk6F5Gr6BQ61ej/p6Ayj6h+9XwM4 EOPb7M+vLKBYUbcIHCCQ4qa1JvHKY2j1MFWEzjP1NKUlavuvdFETawnhJDxT3bnX72Z3SEYbB1zb 069uiOE2azHY8mJyPkg0qlbpVeHkE6lPFB79Ffu0IVHKMeZayhrrUbuvY+/KGT6o8ScXEQdQXInX NzRxnS45jzvsNxdjKD3SZLWeixsOY/KvPt96I9LvN3kzY4VWqttLMrNBDlH8cmy3lHximtWp5pMi bhJRu57ng6x0X32CERd54iqQznw7oadVGWoBb6nvNxecKPbFc2icQcXWxHF/zRj4XjNTjm0uHm0R qzJgvJeDGYdCtHGwE5/UNbA2s1PTcmyVx6uf+Ixsy6LcyXuv28pPJCwimj3MBiNOeRIx5LkqrEo9 Gx7hYv43l2p/YoUcCEumXU60VLdfzly4xQw1V4ywFZ9ZxJsXlcYnqsYWXnyLKHt/YKwkQCWZk/GH wUXJZm/uJT3+KridC+vfKWiw4mmEX1ecIfDt8qAImPKLSociRTQLi5HZGRLJoXhPkQYr0fMqyKbl KGn8OZtBIlnxrW0jZri5fbn1MfMGzNAURNJQ/I1ndPz99H2M9CsFXhm6mRUF9zhF6Q5iYuK54wyC 2Y8pqTmQTFp6TFb2hHv4ub3gftjlG+FyMe6X4Ws+tjhAt4hr/juyIjf2eWF/QKR5HAaCt6sVE6Lc OCempAc14PaZVtIOkpyxxc5WC7Gh/jVno0SkcKN5zDJfrEBJ/9JuKVLNLFIT6pKlSnogb/15rVzR il67f5tzI2yHoJCtqGUAwo50LYwToWoAqCiywXjcoN6RIUOGW8BSRe8tcO4YDV/DSs/q8GaUjbgI ZbenmqkQ0wpfjuDIzfkbaTBypmc+Rv0xUe4F1tjbv3wEXb6GzeUnua8kMQ62HeJbVVAKBX0Z3LLK fmI0Dwl046FOg39gBL7ZhIHmE07OhCTnMOFmW7tElXaAUH0PeLfgtaOQSF5U3bRqdW0IJFnOdqR2 EKWTFlSKS0aBahOt4ymYgr2lOn0pSUcUilicZng5jXv8kY7tP3zOgTHHsawZg4IED2StWnnYwyL6 6EIyAwhZS3af0YlAv8KvD6vcL41MRq3zwNDn1EI5lqc2wFg8fTRrO6LFuoh7mesRfn3qoZvPPloX Sy5rGkSKvMSaVq393JMxu3pzwOlIoESC2WXmfLNTFRfa0Efuar/WrXvtxDhheePV9JRJC1VefrLU fcd4t97wlrdnbP7P/syblbRLV/l6X/XuqeQbAe1Bma089OiQx+4LaREP2uEEfMCw71Jst7M5eUrS jbfdALJxpYFyG/Vt8Ew7SXtE5mfW36udn1CSRnR/pwWDmSuN/cgglmYIz5oQDfwDiUPQNXSoOzoZ Po8TiaZsL0Ngh4bDmYMl4/6gxBgYf1QS1VrZFCvmHt9EJVxy13PLY1tCjqHqca5SxGYOyfiNIHvU uG4G9JQNyIm9PWvRp6ANFLtVLNrNB1qBwLy7y+nJJ9PH1bIMBJ5FMX6vFrt4iE/kEA+T0WG/M4jG PgooW4kQdsc+ND+E9hvGTHqvtuYcnLMGCj0cje1KMXLRUYJ0AGoO6Z+3w/Rg2U1RrAwwoJ+h/6Yz Eip78HlbOkTbLnUWDqG2oCbyNwtDaD0sS/7E3MQHDI71fUQmDbEhGsINPLAN8dNxE5xiVyxpiqJi uiU1y93QYAijZR34Gk8gIZ+7qG0Hn4Xue1JvCNG/JF3rSZStxwtgEa+ADcxcxDY0OQtj2vohayWI VlJX0AW50EH6ziaEfTDT5VGyxygyvTkQW99h1k+FA3FvCQ24o68JvyS7xzKpqG5PcwQnBaPwSlSb nPFj9DnHCG+Xj8+rxgQCKVVVUmqPypn65R0ejbIrO5OCX7agbTMad0a6b3qAXLyLRZmFtL3R2LIg NxGFYbHufOYvgFcMpm6az1KWB6EoI52oEjc200bTTjHRKzgQgF8B/flyhCKa1gUqbAGMWdN6Zhiy 16eN6+DLyLDqyz/MwQo2bTT2IX7ziuxXAiYB0S/pWcDZWNvEBhks0vCnd39f60iFHna5MOUGNFza 18UjctssRu0JB4YFhUJIeUIwrTar/VEPjWY5iZ23NJ9R7CGUUmsjmA2a4dD7PnBc5Q2Py7sfufNa JZMQlNf/l8BWk14IvSe15D8fragfwLx6/r+tjxhfXJuzzm8de8tt5QvY4DMFVYHP3AonmgLGLKGT nFeMWZMYx9bn9Ljy2vE0mfsNPXgikOuRQ3Sn5SYwACigPJW40HeUbFGTfkovmkhAsogiROFRjFrS 9QKvDiX03d35GstBpzQuq7RrLU0VNOtpbuHuM2bdi+klXXy2cyeIkvIBlTcGdtogEvoj+dHrfs3c tzPXtFW5b22EX9P6qkpoBf8/Xf9GoRDIEg33ZPqvrZVwX2TL+3GOqUJFo8EZsEhYBTDufu8lIgD2 3xk4u8ozixqazULCUVGtYAcHW7e0KFpQz8sxVQVNEf+pC6FlR4Cpvr9q+5JCzoYRIQcGID76uo13 xeoCjEn2A+rv24BLwqxPtRUmwmcNTuMeGBfDn8ZdUgaQRhlVyDQqJkDau+2OqbL4m5pu+GG+uS0a WuxlX6BBonGlmJQw9jxwAEMhqI8ReRuj1F4UWdIYZxDX9BuHGs/f8HcFQLKRt59ZdubZsKmpbN+t 57/7Ajqf55jPVhbN/K9yG/rqEWa3ivTOC3nOpbeFlwIlsd8lN9Anrc0UUww25YltsPwcMA3dvYfl EIhuePbbUnU5KbjSIW7olfHY09bdqIQ0qZMsiqCODRzufYK3mHEhwlk44kLObPQOLbk/zBEDPH5z DGhjj2COelUd/yGBEFR1JvAMdmlvumbG/6g/lbsLVaQPN7UVOffPftHPyqPFVw7kRoDLr6Z56dkO QGAcehDKCyhz/ZGEvMKVR3IDNmOAJLzFWvw3ra09/64fXkoUg+Jlgx87IOonYAimPDCTXyAWrbTg UcM23WUZmORLQz4sK//PwCdaN4xqzmI5yWuNOd3Fcud73IOm+beYiNFLYZnJEgtib/0ARw+cd/YY 9rVprmXvNY0gPql8AS5hHVrLFUMJjQQO58Y7axORxZhGmsA4L6FcZPWDJyn514IP5bI32fSG4+3U BednwnPidVv8b1YeHtnwRYq6XG/MUfMVPZ0Zk22dAfffi1G3Nm0njyyHLw7lfhQxgdUHHTN+I//j JxBXbSgo0Nn5gmjzlio1iEOZ2qZBiToKJ4n4Xf9LgjQcHdVCASkyKraC3XwqI6hh621pqOTAAzqi G6h5sOIzU+bGTS9Gk+NcucMhsYeSIQGAgdYu2v262kK63/1cEIL4P62KvMV+WHpPTZ+w+UHioaoI Hd0R7qVrmbVcG0DLrT+n+LB54XHeGPaMAOl7WEtNbBZYadrJCWgGcLJs91d9eLrhEa/JRiySxPDv Nh3nM7KYglWGRv/vqyf1bpax8Tn/vGI4cqObJgMzG2ixWZ4vwiNWbPQbxs9tmjt8YVkElaYBgaZi CBGtGKzLHbV+Nax3o6IDVM4Pv4ukpHXIclYgBJ1i8BlgqYvW8+FfALWhUbDRNmQEauVtxFrel+St A9Azb28ku+Xot4XqwlBJ8Xw0UUbTS6wgaHbGKLCndi3ZDAcVlsa3fVOamAvFv0bxm5jMbMnbQv1/ WZfdyvIoe3cw94LbSRGvEsDk11KTng76LfLVkAxVSj3rbpp5EqT2R0vB9vbj9eRs1iMxU4KV3+zv cYGnPJf3Kat9Bi9QhVNHjMDMLT3rMiXH7hHYp8VDWzYLZZuBCexp/4qoozpoEWykcieIkuX+fAFk YMA32unn/EVGFZeGMjg0oYojdM6cjZd8Tsd0Je0Lzk4pp5DcwYMh8FE8tJ6iTWG1BaOFDSBzpglm 4XU/5p5iPV1co1CmIGGx1rgWCsANm+RrNsV0l0VnAtyxNlyyJkZ2vvOPkaGTjOhdo1Y9PIQUZzGk 87xHTftVkuEfVGWUwTMPCijqNlMkkSwPQp3yAhEtN6oruJsO2296CJYGYJy1/Zp6V6/eYgbQ6BWe S9GLX0DobgPMJkyzaIcJwXEVj8J9FrYWrs8RFiRE4l4gh3cy7QogDiRhkD7nGSBxx7ltbzOVLx0u lB+FVFv60o79idFgAcBBFTUMPGry0V3eIx0Duep0KXqdqVrPa6QT/9YRZDCD/oTAqgcrwq4eGXGE l61pR/Smqa1wQNaUKZGPNiLtzRsVm2xYZ4c+TnkhrfTYDTNGdhCQ7h3293s847Tky3lYeuUprw51 IQN8KEuQ1yOsvoi7v5XmxmBKaeqOPCZoIkeH/YQ6vcQ5i28oLhIOVTCg5Z2nukUmaXmxFWcBZgLm nQk0Ev82pfN1D5tewqDR5Vb9795fqnAu5j/TRUlM3vzS+DfIdl174E/BmNTNbe8YrlpRddeTYXUg TQTrvIgOE1rW4RtUhKlEiX0PbGQYC29wKsgUoiUBYvnkUnKnpjY0kMct+vwIiZTRznqjl1ZeNAvI wCjX1Knzw/S7PdLZmdLizqZnnyEqV+SpOrlYAQWrgRFz+Lq6fc1Fz0pVvc3La+bOP3rk6n6uH2Zp XbThibKQidpN5sTGhNJEn9P4P3Pnk8XHpfkZLNc56l5J551T/eHRMls6kPqShDtTv9ioicCGDCoN qlx9I7zKOO35wFXzhssykIz8Ro5qY51tuy3m3YTjwtAFGAsvyO97297u3RZToke0beNejh4aiu0o MpebfEIxxdqJJhiPOu/XctnOqK6EpuIIfc3p7DzvmAYQWUqLBp57/17MKD3lw64NzUz4+m4Ntmyu ilN9bZc/Hv7CngccFYRglZmtmnlThvMGG9whwAnXteg6PuZUs6CE7mRKIMfanFbcwOc3xWPkrv/Z dvj0B0QVXWrCdIxhmjAhOvCpV5qiIM7pfLhZ6BQsZ4M7z4LKPa/gGj133NR1JBDYQ3hbjHPyUI6v W4dHGefLsOlewA6WiT9xtINIho2ZB2T1H3vcQ0+01YxlKFIFljPUSr6ttALWHF94Y2cXFkPX0gRl h5QzbLfrQzUpHMBfANXPDyd6heEQCUCbE8pJqOFpFFG/RI8RL9XD7XLcAq4HPlQ/PuG8mbJ/8hVY j14Ye1iCV2/FN9InlbY1mYJvzYNWqu6Mufhx1Z6CCm25uwn4Adj6ajWC5YzSW34aQAqceOtTfBvA +fxrGlCMBZ4dbeIS0axYgCfnT7z7efnGRuOFmdKlJ93RWCx5n4XWrpgGCTjPok04sVM6HDtfmcvK BVSZZXt2c9WZ6D0shTtNSXMxm2UJddnzD3QNgwQdR+tlPvws8k4UGSVZVoOcBuQuYlrLFPFePEfQ 2SLfarbPqRCMkZtFoIpUMduOW+WADwEd66EzbJeA5QRDb1mvb1RVrGzt/9tMdidVGqDgILKpr3q2 LJLnCydj7NXzwFjsjBhbkZjRhD05/KCjzz6BV594sFo/DPf/ZL/iMx2WDbWCX4Ic7Uba/gPruR9Z EL463VQ8R++H9PTtLV7VMGB9/h84bxuFS6Im7mOMdQ5dd5XElrIwynbsmWNMlObRkMqb4TIZYoOE g3u56sKOhWQBzC9ngzBu2m/1+OgoVdLwSkHFX6tVO3JmeZlq758CY1abBoNA0TX9ic8+FRBi3Rk/ +cgYHvWLqU/D3MRHKgSJIW3lJZWjHn+06+oHk2ciQJw2/cD/XQZTZK3XguHqXUZ7rhkzti8hbFaD qlncDGzkYBUJ8sY23idxAnAwDnIWRI0ExS5TvQ7RVu/Oevjaodev953V6A3mwofdvTl/ABJKwjag wm+J5Ie0VCB9dNNMp8OsjPJfwbBWKT2kPNSGlOOPhnvVBdoPWqXAmz5ITWSxZukY0XaN+UwhU9hZ fNjAe4ewhT9F/iTEFoZlyV0FiIKgOlR1pJMay6L4zR6887yzOiXw+5bszOL4/qZ0AVsLeRS7syLV l+Z9sZ1mfdRAOtTqop7eKr4CNPGboV4BsVohkX2fJ2mkB6yBujqkD9usCM+HeJyxm/GVMYH2rKe8 TkmrSttDfRDBGge+6bohtFFrgRC6nbCqwY8D7jFjnZ9udddUr2/jFtL3RK+OX5PmD7tbjhrafZtN TWoWqgcxBD573otToLUgfHyf8DIVsKt+nzLGmVbGsOpOEOrKNnh3+VZC8fT7f9+sG/7QM63Gbl48 6LmjVK3qgMWxhCNRuWTTHTFGZlXqCGnPUGOD4LxMjkNoM914EjR8UsH2LJRmFZQY4k2mBIsw9t1O ZzvJpiwUkQmxmXmSziJvjxQpUbZLp7Wnu1gUXJfeYRw4BEP/GbpVsHLX1utVf3JwSuOKd6gVlpXy 0x9bWVdrpZk3OFy/phMY8+9+bP3TPD/7FLurRvNwXyE9dyEX2sEfC9TAP3gvop3wE9yr1WWLOv2S 6C6uClo3OnOug0RsGdaJHsU+DfgV1x+Wt+uy+/ndia8XkyXNH/YM40IlapsO1/tU7sOsnxMCbNsO D6QiJNSJwy0f2ckNKvm7uyxmKyPbcaVRwiUqpcuAk7DKz1gfu1y/ETMNN45VVJoF9wcSdvD00GUI jZyV6jwmu7m5TiUwtLcuVBhY5eqeUxOmXZpJ8vFSP7mjxBMn/4PQ6AIbOjKPpxJdyxCQKtD0Mnm5 dT16RsZqOvmfxupivJaw6cJKD6OHujVjrpeRH1Zzhjhq8enR3k/FsfolfPlYWY/cYA92+8QLnDaU Mo77ls+DkRpX/HniAarEtNS0F3bqgPxjiVzS1y5nFDH06rQhQuGNfuM7reCsEsarPeQS8yOb82Kk jrYm2vyrJJuf2elTANLG0ds/DK15L+mcVLBG29CqGgOqtqRioQxn+dv7tHKlTU7tKacwdxCswkwD 5ugXvbDI8tJ7ZJ2KQO4DwI6QCbSohcRCwbKsFCfS3bVCcOiXOGQr0DRaQCYb6lcz7fZ7rW2bRwGF PGDJge1QrKZUFMMO1KfRgUzsszHj5zDJJfYKjPVxBLLd2px9tsTor5CZuPXoXgM6tIPm0GFw5gDq iH3YcOGyNf2oUItkVndBHWvbfZ6PKYgssI30f1uLDph0X1TBB8zBQCfeqqUfUJhYLd4gCDSATyrv mFN9QwRJm1lI4qiHE8cusBBp1y/jgcwwVTILwsBZjHYS/SOv6jfwerfdNqAjiOmNWD7DycT0IS3B eb8ucTG6SY5uwQverA8dA2WChj3M9bIx4N9MfOE8g7vPtGaot0mX53SyU74KGNOOH0ubuKt5skON z5ov+DatahFqdip4K1mO6Etzyl9bLCo20P2gCKDREPOu5pDZIjJRCyO7ofWhaxPMm3gdz2OJfBPT 2J/joNyZW+eCqMLeXe0U3N9EIgLI/JHemYWyejch7QJ0zgqBHzM0S47+V2Zlj4ka8RtwItFSJOts dt6ozqPGdnlwN5e5Tc2BBJ+sUYbICztMGDyocx/inP8PaEtcTPnWgtv2HExdujYjqKLQtdlpY/GG FrScgOnO+ZnWAfB9+GjJ5IJSpERgCJlYaaMsDRDm0mqjtDzntTtkVlnmN5Oo7AC7GQRLVPDVIEtM yC15s45J45B1Flu+7St6gTFbQMq7pSCHjYJ2UL4vI5vj9/RxiReQ2br7c0JzWTvSImUpffdYIxpV HskRFU8YT7ATE95zLg8eFVvLFjKO8JUXqpcgWyKdfmlcEty7x7EbnFreENS7IhO/fKDw4jHeOg8j dRcmGShf/8nQmqIwsLueKmvDqcAIMpjh9pu0Mqh8sd6hODEjJEY0LU31ZGPnl67vQZQzrRor3nPk LjXxslpwHXnji55CAG0ClBWJ+YeM6ONiUXVYOKodZ3YAlN2lFzRWPbxtHg6iWlM9YGMqE/SpEHpi kzyaKvPf//jROm+jUoFmXSFO/wXrW2BffxBZaF+umtEWz0/Yl+suwjO14XkXmk+NtEDEW7OjM6GN PduUNUelETdTrjrJXnfgyj/UogTH9PgiljIo+63a6XVW4Ip39/hNhpUFTPVeNYhcdYt7bpNiY7HK loosl0onJKFOlO3sDJy5Q68gSfvIS2TaN69ExkQQjp02ztkVq9Xbr0onYKZonLyXhkSsvdMSTlsJ 2GEavgGLQsClAfLtApmmPnw+tMl/qhLnWljLuh+JRYyBaDbM8+kT8+5zhjiz8y0VWwhFaGLhsfZn bPJB74BKIfFvjadcuT+LbJ2MriBnNzCCgEiNvubYl2j6VnLB+8ogEoGaqQ/yZxsS5auVLwY50CsW QpOQL2xJRHw07pA5nkVow04JIioreq7HjejGbN7sS4zUoPoBn4vjfhfpzmb4oSTtqP/EfBRW+cup 4RqaLi2g2N8bWYyvQ8lTLXqAFiBEpKq2iHx3AHGihwNPpghX4LnMHQVs7l6Jl6ZQG8qqjIt0ptpW 7jnlPLBY7G/nrfHdSAGf5uWaJrzVfG9bPjKYdH+orulxTQOZQ8cHQchT/5PpF1r5HzuMmRGdXv0U cMoO6IWv//bB+17+JdEXzcTP6CroKcnbsdfSvTs46+51HYBfBSHK099B1f0rwmq7pQE2raGNaXlv rBK5ZJXhr7yF0m+tVQ0lKj0U6RVAGZoVhjD2E+IICbWJ/aDv0lGBizZNGdgJX8YUgGWYEVb73yy9 QeS9n6U0Sgj+CZLgKoebK5kjdwr84NdQU6dDr230Loi5zXj21juQqW0ccIg2+lvr1Dzup35sViER S+tGdu6DZY2Fvkdc75fJzE7JpTzaecT7sPdYIv7Kc3thmukTi/zHPcN86Lk7c5kwTccKUn+87w+L y6fhxSj9cNsoVmy0rReIiJh5iexuPHT+EYx63523+xDleUOKT+J+d//Bv/8ph+xjTviqnaMdED2b ehDASKpCW/nmHFtBDPztCLp3DAQ1acaTtcQCWdGX8vreKTTs0XPqoCMbiuvGHpuBIge4Dk5ZGiNb MPoCCqNIoY6Sn1ObzSVBqsPiNwJzSkhpPmhxKiQehiB7xQE3+akLdwDfFtdw8LSyFkuvmxIx/rcg O8aozW/bOEc0oSdYuxA6Ne9bOqRa9UMQ+oQlhJWVoIe/RvDC/MPXFVUVtP6JzT5Z15OQmJv/JWOK FN6IqkcCl226uUBn3meoXr2xwR3kVRvwaqs/POnSktsvBuHiKOfaIkquspbwos6wYDbkIUXl10hN JEp0eO4kzIXA3Ou4VdMiwkcXFp+rjgPnn2n09RhnQNS+nX8dOMUjHmT7d70R1tOHsWvY4doFibJ/ Zy8LmDNXLBvw74XvWnqmHEd+GF3Wf1cRS7Hjv9x+AXBJ7M8kwKFBs0d9BVc9JVhqjVv8JGia7fbM mOjKelbMeznSWtUfCHin8jyrIWKYfUumc8w0jMRHf9flBuxZNKrhcPiLzRJJU8bOWTC8LFcBYWwZ 1hvScAfoTpGDU53ovaz996oG4Wj5ChmU5GTKQnb46KfDkUW9adIWn2nH+f2igOxkbDBsuCJ5mTvj W7xf7eJXp4ASUDF35yZ7aF73eSqb8HL7qJzcYt/1FNniX55YYw+A4KeDLk5hhQSGYsk/cORxcPvd RsS5a3sLF3Gp919IcTW9lB0keb9VdUGr8iXJAygn4G5ms+s3yt4oL9LkJntkLBmp7nBnoj0S/QjD A4WbWOv9Mos7PHCgkmJCiMTIbvXHXCOmpBRH4+WKD6cw6AkNyV7bAG//b/SXAsdt0kho/AEVo2Q4 Iw/jHAJ9HiAIUnlp4fIBwbjSh+A98ubdJafnSxpT7bXOoUTuwgzqraXy5vhYclXdm1nw6bwpB/Pg TIEyQYN3Z8s2wQU3xrrTNdNfAnDi78Swxmotep8vOEbU4SzpKvqEf6lH2U7Ix1VodAGFiM2LmNhF JgjCqLhCosDLfy4sY0nvH2ewlDg2VD/R98FxxwjiHMbZW+l17SHRYw7DP7FOMAG1MjeU6VDvhAcc 8iJc8xe1bU6tiKPonXNOXpcDzLZn68af1+sVRPXjF3/M4u8M77JZE+sWjavO17ighpeTsgD5xN2v fu4SMPDIgJ4q24i1WXWmUKfeTPKXbTqg5pAmG+d5H1R1u47xHBzP9AXj6YdEf4cJZDRjdkgwm0FX N96q2q98bloDeHMIsuSndBHxshPqcTfjs+AUpsQ09Rd00BCd51JrVRHx15ZkpukSfRF9wXy12To7 T4e5/HS70TkLpJp4E1Cib9nCrSzL/1ZW4z/cg9J1O1KsDE9ClhOig+oWhUivoq0W3PHFAmGwBMXd xmjuUE1THU9ehI2I6VeVDaA/2/k7BMOjP7U4vBeHQytPMyxwZnwNPn4/wwwHAiJ712qSkq0sF4lh zYEnRiyy7GgvUwc8TBl2aD38mK3aq9xgBSuQnGwxxcWtkKUBCSV16uJW6nJUDYecV7DQMKowxP2w jvq41ZCS4biEwmG5McMTI4I+hqS6Bb5bJFYS7YAQVBGbiJ2VxjGjSTbv010C8S2sGy7d/glmtM7w WF3qQVvrBecDd4AKG3YT4zae4e5d+Vgg+SRuVVqK+5PH0XJvlUoF0ChgNaqU2QmRh4YTIgfXWcdz s1LU5k+hEh8zOnnhPFlY+f1kGKFNi/udkld+uP9ziwdDEbBeNP0KIVc/ujSGg5KeThQzlkv76XD5 MYITUxSgoGFLE5Ufc2LigMhgp778Q4RLEuOe2pi5zuCehdrOvsCrZxGTg8KEiNeu5Z5Nw+aeKlRe DV9F3E37bWcWR33ySqeVlqUz6okkYCiZLpkHysd9LDFnn7dvlebcCNazr6iqBFNjAoYkmmEg5Ppb saBv/4gOrFXYbH8aQF1xo7lHzGTh5W04TQD/aL9avRhS21vLPQ0asvRzcIrpRfOmuKoX5w20N9Nl BycAKX6Z9yd64HLK6zUSsrGz4pxjfQQ5jnlsvk81MqD8b1D+80Kp3TEVFnQNhC7IS8EpObR4dwrP g2G1VQiG+Dt6SAivl5BubpXzCjrXI7PNOqYtWo7suImiR4N/M5XxxtNuY2XVFKh92musBCQLoRlB TsH/kExLJhCN0xSZdIcpRJy5699ZLi2FWO2hD/V6/N4cYownOBneCWuENbb0N5ZmMUaR+oHKy0hw 5/kyAS4Wakaj02KZYrLKtVrDuB4Kmlr9PTMjOqNAlxFtA/mgxPyusU83dbRsn3Tmii1lrDewNbiq 6ABobtL1R36T2NddbYbVziil4aMXaQudShlTtJ4c3JAI0tuUVxmIDrl7U0Rrj7C9iRqiI1vIUt+1 N1nuB9tcIQBALa6b/9jEDQyGa2i2HAke11mZXtToqWBSAyQpBtUrOOjPjfhGYo3bA+UZUhbiVN+u xupU/7okziey5iKNOmNXSu5Wl2CQecWnhV2A0RcsjiD0K4IrcsIJrBflRQGvirBHXBUK3ZadTJQP Fy7Vh87AKXMqkS18WtXdrp4bLCO6gGDNkkmZsH8+JlCf9jvfJfDcd3xCRQlF1wBTCzTh0ZR1uUR2 IgF8KXddvTAbme/abv14oFGwrEevUyr0G5ieFdsUpdDo4U1QJQqbkgNtPH4vAVyDyOhVKZq5CRXI iK4OgmfPDHn6sAxz+uWHiGH9Ll8pEqF8Sir+AsGWyxcIEGPOv0nmF/8+vjDULQ1/KW9zZj0If/f3 zjvRbCEsmi22VIpwD53gQAacc/aGUuTQM/vvUo0E7Zziu7uLEkBOX4PF8ExyFAxWjhYdZ0+WxRdt mgGIsB4O9jtewzmU/01qS/jPTHvlHqTpqlGQ4OxVKDLS964zNRqRm726XohoGA0W8ebs1QxJ/AV4 u9QFAkSHvP4DcrMewBkJoEXKyzV9szwYkPxNOMraPmOLcnEa1y4uXFCrklTe/1us3BivxDDxfCgQ 6s8AP7WvhN5nl90t1unMjTMcoEizS/SnJH6ApOAYD7CYF1XnScbpvr44tyjS4X22fBohMfKTWtp8 nxAfTeOljw/g1r/V0XeHeu9y7sYJt9Fg0qeI9WncQ5FvzU1TQ/3PAe/a3/SivMhbLXoLTc1BFk76 k/zM5ydvN0rbKLtN0iKuuxriaNGvh9EFfuQYitxc1FDTpq2lCfPzaY727B2UVB19laQW+QudSBy3 shSOd4FweK+fOelfRHp9257hmD5MtEqftc38akAB/LVXVN7Gsnq8O0/O0+il4QsGuJAmgX50CJM4 UjxObLpsRNY12SMh+GGwXzIcysVlU9mz7Xve1R8T3XEEVXIWbHmIWIy9Xk16tze33aO5uBRjcNW0 wtGcCaDyGnSMnImUeQrymnjPKyQoAcBH64JjHXJP/WBbCluZxtfT74GNkKoVQztZxk+ToGY3Si2x SF826SM2iywdZoYGtJCClKWq+UQWP9RuEyFqRZzBSJpoSrv8Yr00PS4JWRSDvQVwa20MCRlq/HGe KEHvRtW2bSLLj88qKBKI7wxNUcxAmSjFLx6rbDpacMcqvmpR1pVRNvT6WuXWv3Vsh2YP1buxUBaf BH9qTHPaNkFKaO6Gl5nG/ZmXJ9SESUSdAZFbJti+fof0lo3IzlZyne5CNR7GAfRQluV+EY/kozno k3o5Y0G3Cc0c9Rkl0x7o1kt92dc2Q7eq75+5hSLxhFJHMkBXeHQb6WooTvBTYj4WM+FcLfhGwuAO woxk7ZNEPtvBKwV7ieFScF55fGtpoO2Sj4F9fdvjw6BueHydkJ/48t2ZcLMNM5AGrJVXVtDn0VfY TSKovzfw/4a8F9pndzWdwPJT++OcW/uBpxmSXqWCuUSGjPFWIJMaMcQZpr47a9qvDQVbHJJIqQ/A edGHvXRESKkwBu+G2jR6JG/es670OICFyYZ0xjixjSIH3/3n+/+QDtMoakyD/okfkK6Hbgssc9T1 yCGgVs0E+5oK4W/rO8hSLDnG+lMY78v5sBusid927aG+cNsb17avY+XQmykZEgRrNIBv/V5HPu3s MMiZSEEu0broZFGzoImlj+QbgjJ5OZjizIi8nsK5zhdMocKowwVUUmlH5GGciNRrZkJAnouuz99V FLaKd/k6taYSRDdcL2UAxi51+O2fT9UrKU6EY+oDbBfhhCSsGzU9Vw9NviRlOrxWV9vXK21d86q9 PygOSMlc5oSkaNgEtPUVYCEzElBd88QBfUPBPQZL4PgHHGwSSTehTONzMqgPe+DaYRQLQY6HNpVu TQmRV//H1HpzrpmLpipHA+sD67xzjA1jgwI9761n9oZQl2j/TGw+4LDJfKpWmkpEGKKSqQDqAd6X 6l+ITlz3SUuqy7cT/zC7sHYJekOAF92+B1B05KRJ8rtceHEo0iuDID/BgqLqUPSDqf1bPC0yvi5O 4dJCzA1MnsxIY/a45M64xyAetYaReBPRbmvMgYriNh9IXkRwvysnx3mqehIxYU7Ivbg8YSX4gaNx OT2F23qUfI3Dsb3MP6EWCMLlnCsKnPy9UHUZEGBR+5bVk+Jb2S17zQJA4LJE5j9smmYQtu8b793/ yz/8P61FF+6Gxbp/dPCWFxx0tBPAgMoKNgRi0szmFToixXRynUctWK4K86h+wLO3nawvfXLA6aEQ CV0//vjzhLleH364829VfBPHZwmHXB+IqOqiPsfO3YlJ6xOGr9+3Kcitf1b9Tr22VMKUb9GZeq1L T8J58SSe8AZVjwxqPpFu/HpJ0+EIISNwTxmBugLoMfmVT/0HPMfVqj4n5aT66FwbemWdkkPJG65Q /02KkhytTSKPkzLdEnmCsNOqIj8fJVJkQsH7++Uhd3A9Ai8sahx5/mc0vxB9NzK1DYAX2kbbHtB3 +nCXjf1R9bsShVTG9we8TdnQmM2RyseGIQ4x3coMrt2Q0Ad7/VUDdV83PhCZptNAckdC8/PMusMp McZU05iGQDEC8TYgC8chmhibR/74vfFv3X9bigQeiTsto7YYEEKntPFZkDY2uZyxyeP4PJJt0Mh1 WBVYD++NAx0kstH1VyLTCwaEqMKwj1pOHK6fC4hNBD9lZ9var8KfjhxHczuSmf1Ph1gWMRZpS1av 0898fBzE3rI+yQbxYIVMR2fndQ9dCfCz179N5KLCQ6z5CY4vr6YlVukFy2GlUUAixHXmtYW5K3qf BBYRe1iZXMjE1d/1D9GI2NF4+MoB3XrKl0nFVgMxA8dErJCsw7o40llBG8b07RpKpb8Rq8eBFIHw l14uicuA4E0VGD/A7koNiR9gnLxOPf3gFa4r4Mbly0txd86W4Of95ilIAqawunoxFTrlaAQ9tTkz 9nThHIpa8JV1hKIp/DV3oAtKEfJtaGbAWr0zpc/HEfN21XsxX5ZsUy+7TlV6CBSz9DL87lDROrJh aQlk82sd7v+LVzteZfFTfM8M5KD83zuSW9XwB0ucjUjW5DOtjDPgl1YRlgn213gty3eOKoX/mFMI 5zBMYnoV6yanjXASz+O2ZLLCPrhRqRRvYTyAuJBXDw8ES7xkllKlY1H4JpjJtYvXVaRy3TCACHrF gZs3dd75JJv9fDhl1oba8XVvQwh3yNnrN+QaCvfIKTZv6HAFXkTA5t+mgkDQEt2kgyHzXG91caDx 4520YdPKTwKm8l7LuUywm8ciHrsuqhTz1dfm5flD4lzQzLM0Svlf3Nt3qwkg2R7sooNEv1SXUM9V cfYoLcXuHOeiOQEESmnbCFl3pYibbQezppwYlie87/DQOz40Bgg1aJ4ibAln5juaPbYnKwzIxfAF 3mt+yk1eiaAuXtJ3h8BXMwJZzLvl5tTXPYT1QvPlTWq1+zN4zQc41J9QkVCl44jtLruKcd0MZCgY F5KYA3QncWM0wb5uN6Q71r3ARdVN02iAqjo68heE3b+SShsBDIxxeoSuXEOhIWe+qbYYLkXKYXRO VJS6KvZTB8A4eR0KBw6wuCx6kpt8FI5y1XhhDMgn2nIe4Qu5IJeZoqJPV5w+rqgiIZbvAbaPT1Jb s2/dVa1xEX6wTcPL4faQZy+JlfjJKRO2vZpFENJI7cVz3SE6DOjWbmhQCG9UnW1N40vvdlKHT4tW p8+AELrmVonL0cmQXfOX5Jma9ZfzQIq3urFXBJ9xu9BcrTX+SXyBWzhWMjodpVVsK6Cw/gO8d4wo Enm2O7iO6aqip6xk0RbgerUrUp1VzAU3K8NDT1N3vEGnox9rZS/uf+CRER5yjdy6ujzJhvpiPEVO a4CwP/KcE3bHXnEVAdS8ytJyZFOGx7qRERjfywqMgOBHO+xLSs4fO+kXX9XQvoX/Z/z0G4EFR9BZ wKAZzxTIR1HbVQJcAVnBb0RIFKvgwliAHCiSwphQ2e/AySivdK4iN25Bx/BnkBvu0c/l `protect end_protected
entity tb_uns01 is end tb_uns01; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_uns01 is signal r : boolean; begin cmp01_1: entity work.uns01 port map (r); process begin wait for 1 ns; assert r severity failure; wait; end process; end behav;
architecture rtl of fifo is begin process begin REPORT_LABEL : report "hello"; report "hello"; end process; end architecture rtl;
-- ------------------------------------------------------------- -- -- Generated Architecture Declaration for rtl of inst_a_e -- -- Generated -- by: wig -- on: Wed Jul 19 05:33:58 2006 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../udc.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_a_e-rtl-a.vhd,v 1.4 2006/07/19 07:35:16 wig Exp $ -- $Date: 2006/07/19 07:35:16 $ -- $Log: inst_a_e-rtl-a.vhd,v $ -- Revision 1.4 2006/07/19 07:35:16 wig -- Updated testcases. -- -- -- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp -- -- Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/arch HOOK: global text to add to head of architecture, here is %::inst% -- -- -- Start of Generated Architecture rtl of inst_a_e -- architecture rtl of inst_a_e is -- -- Generated Constant Declarations -- -- -- Generated Components -- component inst_xa_e -- mulitple instantiated -- No Generated Generics port ( -- Generated Port for Entity inst_xa_e port_xa_i : in std_ulogic; -- signal test aa to ba port_xa_o : out std_ulogic -- open signal to create port -- End of Generated Port for Entity inst_xa_e ); end component; -- --------- component inst_ab_e -- ab instance -- No Generated Generics port ( -- Generated Port for Entity inst_ab_e port_ab_i : in std_ulogic_vector(7 downto 0) -- vector test bb to ab -- End of Generated Port for Entity inst_ab_e ); end component; -- --------- -- -- Generated Signal List -- signal mix_logic0_0 : std_ulogic; signal signal_aa_ba : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ signal signal_bb_ab : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ -- -- End of Generated Signal List -- begin udc: THIS GOES TO BODY of inst_a_i; -- -- Generated Concurrent Statements -- -- -- Generated Signal Assignments -- mix_logic0_0 <= '0'; p_mix_signal_aa_ba_go <= signal_aa_ba; -- __I_O_BIT_PORT signal_bb_ab <= p_mix_signal_bb_ab_gi; -- __I_I_BUS_PORT -- -- Generated Instances and Port Mappings -- -- Generated Instance Port Map for inst_aa_i inst_aa_i: inst_xa_e -- mulitple instantiated port map ( port_xa_i => mix_logic0_0, -- tie to low to create port port_xa_o => signal_aa_ba -- signal test aa to ba ); -- End of Generated Instance Port Map for inst_aa_i -- Generated Instance Port Map for inst_ab_i inst_ab_i: inst_ab_e -- ab instance port map ( port_ab_i => signal_bb_ab -- vector test bb to ab ); -- End of Generated Instance Port Map for inst_ab_i end rtl; -- --!End of Architecture/s -- --------------------------------------------------------------
-- fulladder -- A 1-bit full adder. library ieee; use ieee.std_logic_1164.all; library work; entity fulladder is port( x, y, cin: in std_logic; cout, sum: out std_logic ); end fulladder; architecture rtl of fulladder is begin sum <= x xor y xor cin after 15 ps; cout <= (x and y) or (cin and x) or (cin and y) after 10 ps; end rtl;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity osc03 is port( osc_dis: in std_logic ; tmr_rst: in std_logic ; osc_out: out std_logic ; tmr_out: out std_logic ); end; architecture osc0 of osc03 is component OSCTIMER generic (TIMER_DIV : string); port( DYNOSCDIS : in STD_ULOGIC; TIMERRES : in STD_ULOGIC; OSCOUT : out STD_ULOGIC; TIMEROUT : out STD_ULOGIC); end component; begin inst11: OSCTIMER generic map (TIMER_DIV => "1048576") port map ( DYNOSCDIS => osc_dis, TIMERRES => tmr_rst, OSCOUT => osc_out, TIMEROUT => tmr_out); end osc0;
------------------------------------------------------------------------------- -- system_ac0_plb_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library plb_v46_v1_05_a; use plb_v46_v1_05_a.all; entity system_ac0_plb_wrapper is port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to 0); MPLB_Rst : out std_logic_vector(0 to 14); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to 31); DCR_ABus : in std_logic_vector(0 to 9); DCR_DBus : in std_logic_vector(0 to 31); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to 479); M_UABus : in std_logic_vector(0 to 479); M_BE : in std_logic_vector(0 to 119); M_RNW : in std_logic_vector(0 to 14); M_abort : in std_logic_vector(0 to 14); M_busLock : in std_logic_vector(0 to 14); M_TAttribute : in std_logic_vector(0 to 239); M_lockErr : in std_logic_vector(0 to 14); M_MSize : in std_logic_vector(0 to 29); M_priority : in std_logic_vector(0 to 29); M_rdBurst : in std_logic_vector(0 to 14); M_request : in std_logic_vector(0 to 14); M_size : in std_logic_vector(0 to 59); M_type : in std_logic_vector(0 to 44); M_wrBurst : in std_logic_vector(0 to 14); M_wrDBus : in std_logic_vector(0 to 959); Sl_addrAck : in std_logic_vector(0 to 0); Sl_MRdErr : in std_logic_vector(0 to 14); Sl_MWrErr : in std_logic_vector(0 to 14); Sl_MBusy : in std_logic_vector(0 to 14); Sl_rdBTerm : in std_logic_vector(0 to 0); Sl_rdComp : in std_logic_vector(0 to 0); Sl_rdDAck : in std_logic_vector(0 to 0); Sl_rdDBus : in std_logic_vector(0 to 63); Sl_rdWdAddr : in std_logic_vector(0 to 3); Sl_rearbitrate : in std_logic_vector(0 to 0); Sl_SSize : in std_logic_vector(0 to 1); Sl_wait : in std_logic_vector(0 to 0); Sl_wrBTerm : in std_logic_vector(0 to 0); Sl_wrComp : in std_logic_vector(0 to 0); Sl_wrDAck : in std_logic_vector(0 to 0); Sl_MIRQ : in std_logic_vector(0 to 14); PLB_MIRQ : out std_logic_vector(0 to 14); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to 7); PLB_MAddrAck : out std_logic_vector(0 to 14); PLB_MTimeout : out std_logic_vector(0 to 14); PLB_MBusy : out std_logic_vector(0 to 14); PLB_MRdErr : out std_logic_vector(0 to 14); PLB_MWrErr : out std_logic_vector(0 to 14); PLB_MRdBTerm : out std_logic_vector(0 to 14); PLB_MRdDAck : out std_logic_vector(0 to 14); PLB_MRdDBus : out std_logic_vector(0 to 959); PLB_MRdWdAddr : out std_logic_vector(0 to 59); PLB_MRearbitrate : out std_logic_vector(0 to 14); PLB_MWrBTerm : out std_logic_vector(0 to 14); PLB_MWrDAck : out std_logic_vector(0 to 14); PLB_MSSize : out std_logic_vector(0 to 29); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to 3); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to 0); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to 63); PLB_wrPrim : out std_logic_vector(0 to 0); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to 14); PLB_SMWrErr : out std_logic_vector(0 to 14); PLB_SMBusy : out std_logic_vector(0 to 14); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to 63); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); attribute x_core_info : STRING; attribute x_core_info of system_ac0_plb_wrapper : entity is "plb_v46_v1_05_a"; end system_ac0_plb_wrapper; architecture STRUCTURE of system_ac0_plb_wrapper is component plb_v46 is generic ( C_PLBV46_NUM_MASTERS : integer; C_PLBV46_NUM_SLAVES : integer; C_PLBV46_MID_WIDTH : integer; C_PLBV46_AWIDTH : integer; C_PLBV46_DWIDTH : integer; C_DCR_INTFCE : integer; C_BASEADDR : std_logic_vector; C_HIGHADDR : std_logic_vector; C_DCR_AWIDTH : integer; C_DCR_DWIDTH : integer; C_EXT_RESET_HIGH : integer; C_IRQ_ACTIVE : std_logic; C_ADDR_PIPELINING_TYPE : integer; C_FAMILY : string; C_P2P : integer; C_ARB_TYPE : integer ); port ( PLB_Clk : in std_logic; SYS_Rst : in std_logic; PLB_Rst : out std_logic; SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_dcrAck : out std_logic; PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1); DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1); DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1); DCR_Read : in std_logic; DCR_Write : in std_logic; M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1); M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1); M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1); M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1); M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1); M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1); M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1); M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1); M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1); Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1); Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1); Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 ); Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1); Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1); Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1); Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1); PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_ABus : out std_logic_vector(0 to 31); PLB_UABus : out std_logic_vector(0 to 31); PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1); PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1); PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1); PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1); PLB_PAValid : out std_logic; PLB_RNW : out std_logic; PLB_SAValid : out std_logic; PLB_abort : out std_logic; PLB_busLock : out std_logic; PLB_TAttribute : out std_logic_vector(0 to 15); PLB_lockErr : out std_logic; PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1); PLB_MSize : out std_logic_vector(0 to 1); PLB_rdPendPri : out std_logic_vector(0 to 1); PLB_wrPendPri : out std_logic_vector(0 to 1); PLB_rdPendReq : out std_logic; PLB_wrPendReq : out std_logic; PLB_rdBurst : out std_logic; PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); PLB_reqPri : out std_logic_vector(0 to 1); PLB_size : out std_logic_vector(0 to 3); PLB_type : out std_logic_vector(0 to 2); PLB_wrBurst : out std_logic; PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1); PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1); PLB_SaddrAck : out std_logic; PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1); PLB_SrdBTerm : out std_logic; PLB_SrdComp : out std_logic; PLB_SrdDAck : out std_logic; PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1); PLB_SrdWdAddr : out std_logic_vector(0 to 3); PLB_Srearbitrate : out std_logic; PLB_Sssize : out std_logic_vector(0 to 1); PLB_Swait : out std_logic; PLB_SwrBTerm : out std_logic; PLB_SwrComp : out std_logic; PLB_SwrDAck : out std_logic; Bus_Error_Det : out std_logic ); end component; begin ac0_plb : plb_v46 generic map ( C_PLBV46_NUM_MASTERS => 15, C_PLBV46_NUM_SLAVES => 1, C_PLBV46_MID_WIDTH => 4, C_PLBV46_AWIDTH => 32, C_PLBV46_DWIDTH => 64, C_DCR_INTFCE => 0, C_BASEADDR => B"1111111111", C_HIGHADDR => B"0000000000", C_DCR_AWIDTH => 10, C_DCR_DWIDTH => 32, C_EXT_RESET_HIGH => 1, C_IRQ_ACTIVE => '1', C_ADDR_PIPELINING_TYPE => 1, C_FAMILY => "virtex5", C_P2P => 0, C_ARB_TYPE => 0 ) port map ( PLB_Clk => PLB_Clk, SYS_Rst => SYS_Rst, PLB_Rst => PLB_Rst, SPLB_Rst => SPLB_Rst, MPLB_Rst => MPLB_Rst, PLB_dcrAck => PLB_dcrAck, PLB_dcrDBus => PLB_dcrDBus, DCR_ABus => DCR_ABus, DCR_DBus => DCR_DBus, DCR_Read => DCR_Read, DCR_Write => DCR_Write, M_ABus => M_ABus, M_UABus => M_UABus, M_BE => M_BE, M_RNW => M_RNW, M_abort => M_abort, M_busLock => M_busLock, M_TAttribute => M_TAttribute, M_lockErr => M_lockErr, M_MSize => M_MSize, M_priority => M_priority, M_rdBurst => M_rdBurst, M_request => M_request, M_size => M_size, M_type => M_type, M_wrBurst => M_wrBurst, M_wrDBus => M_wrDBus, Sl_addrAck => Sl_addrAck, Sl_MRdErr => Sl_MRdErr, Sl_MWrErr => Sl_MWrErr, Sl_MBusy => Sl_MBusy, Sl_rdBTerm => Sl_rdBTerm, Sl_rdComp => Sl_rdComp, Sl_rdDAck => Sl_rdDAck, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rearbitrate => Sl_rearbitrate, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_wrBTerm => Sl_wrBTerm, Sl_wrComp => Sl_wrComp, Sl_wrDAck => Sl_wrDAck, Sl_MIRQ => Sl_MIRQ, PLB_MIRQ => PLB_MIRQ, PLB_ABus => PLB_ABus, PLB_UABus => PLB_UABus, PLB_BE => PLB_BE, PLB_MAddrAck => PLB_MAddrAck, PLB_MTimeout => PLB_MTimeout, PLB_MBusy => PLB_MBusy, PLB_MRdErr => PLB_MRdErr, PLB_MWrErr => PLB_MWrErr, PLB_MRdBTerm => PLB_MRdBTerm, PLB_MRdDAck => PLB_MRdDAck, PLB_MRdDBus => PLB_MRdDBus, PLB_MRdWdAddr => PLB_MRdWdAddr, PLB_MRearbitrate => PLB_MRearbitrate, PLB_MWrBTerm => PLB_MWrBTerm, PLB_MWrDAck => PLB_MWrDAck, PLB_MSSize => PLB_MSSize, PLB_PAValid => PLB_PAValid, PLB_RNW => PLB_RNW, PLB_SAValid => PLB_SAValid, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_TAttribute => PLB_TAttribute, PLB_lockErr => PLB_lockErr, PLB_masterID => PLB_masterID, PLB_MSize => PLB_MSize, PLB_rdPendPri => PLB_rdPendPri, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendReq => PLB_wrPendReq, PLB_rdBurst => PLB_rdBurst, PLB_rdPrim => PLB_rdPrim, PLB_reqPri => PLB_reqPri, PLB_size => PLB_size, PLB_type => PLB_type, PLB_wrBurst => PLB_wrBurst, PLB_wrDBus => PLB_wrDBus, PLB_wrPrim => PLB_wrPrim, PLB_SaddrAck => PLB_SaddrAck, PLB_SMRdErr => PLB_SMRdErr, PLB_SMWrErr => PLB_SMWrErr, PLB_SMBusy => PLB_SMBusy, PLB_SrdBTerm => PLB_SrdBTerm, PLB_SrdComp => PLB_SrdComp, PLB_SrdDAck => PLB_SrdDAck, PLB_SrdDBus => PLB_SrdDBus, PLB_SrdWdAddr => PLB_SrdWdAddr, PLB_Srearbitrate => PLB_Srearbitrate, PLB_Sssize => PLB_Sssize, PLB_Swait => PLB_Swait, PLB_SwrBTerm => PLB_SwrBTerm, PLB_SwrComp => PLB_SwrComp, PLB_SwrDAck => PLB_SwrDAck, Bus_Error_Det => Bus_Error_Det ); end architecture STRUCTURE;
-- ------------------------------------------------------------------------------------------- -- Copyright © 2010-2011, Xilinx, Inc. -- This file contains confidential and proprietary information of Xilinx, Inc. and is -- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------- -- -- Disclaimer: -- This disclaimer is not a license and does not grant any rights to the materials -- distributed herewith. Except as otherwise provided in a valid license issued to -- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE -- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY -- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, -- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, -- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable -- (whether in contract or tort, including negligence, or under any other theory -- of liability) for any loss or damage of any kind or nature related to, arising -- under or in connection with these materials, including for any direct, or any -- indirect, special, incidental, or consequential loss or damage (including loss -- of data, profits, goodwill, or any type of loss or damage suffered as a result -- of any action brought by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail-safe, or for use in any -- application requiring fail-safe performance, such as life-support or safety -- devices or systems, Class III medical devices, nuclear facilities, applications -- related to the deployment of airbags, or any other applications that could lead -- to death, personal injury, or severe property or environmental damage -- (individually and collectively, "Critical Applications"). Customer assumes the -- sole risk and liability of any use of Xilinx products in Critical Applications, -- subject only to applicable laws and regulations governing limitations on product -- liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------------------- -- ROM_form.vhd Template for a KCPSM6 program memory. This template is primarily for use during code development including generic parameters for the convenient selection of device family, program memory size and the ability to include the JTAG Loader hardware for rapid software development. Kris Chaplin and Ken Chapman (Xilinx Ltd) 17th September 2010 - First Release 4th February 2011 - Correction to definition of 'we_b' in V6/1K/JTAG instance. 3rd March 2011 - Minor adjustments to comments only. This is a VHDL template file for the KCPSM6 assembler. This VHDL file is not valid as input directly into a synthesis or a simulation tool. The assembler will read this template and insert the information required to complete the definition of program ROM and write it out to a new '.vhd' file that is ready for synthesis and simulation. This template can be modified to define alternative memory definitions. However, you are responsible for ensuring the template is correct as the assembler does not perform any checking of the VHDL. The assembler identifies all text enclosed by {} characters, and replaces these character strings. All templates should include these {} character strings for the assembler to work correctly. The next line is used to determine where the template actually starts. {begin template} -- ------------------------------------------------------------------------------------------- -- Copyright © 2010-2011, Xilinx, Inc. -- This file contains confidential and proprietary information of Xilinx, Inc. and is -- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------- -- -- Disclaimer: -- This disclaimer is not a license and does not grant any rights to the materials -- distributed herewith. Except as otherwise provided in a valid license issued to -- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE -- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY -- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, -- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, -- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable -- (whether in contract or tort, including negligence, or under any other theory -- of liability) for any loss or damage of any kind or nature related to, arising -- under or in connection with these materials, including for any direct, or any -- indirect, special, incidental, or consequential loss or damage (including loss -- of data, profits, goodwill, or any type of loss or damage suffered as a result -- of any action brought by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail-safe, or for use in any -- application requiring fail-safe performance, such as life-support or safety -- devices or systems, Class III medical devices, nuclear facilities, applications -- related to the deployment of airbags, or any other applications that could lead -- to death, personal injury, or severe property or environmental damage -- (individually and collectively, "Critical Applications"). Customer assumes the -- sole risk and liability of any use of Xilinx products in Critical Applications, -- subject only to applicable laws and regulations governing limitations on product -- liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------------------- -- -- -- Definition of a program memory for KCPSM6 including generic parameters for the -- convenient selection of device family, program memory size and the ability to include -- the JTAG Loader hardware for rapid software development. -- -- This file is primarily for use during code development and it is recommended that the -- appropriate simplified program memory definition be used in a final production design. -- -- Generic Values Comments -- Parameter Supported -- -- C_FAMILY "S6" or "V6" Specify Spartan-6 or Virtex-6 device -- C_RAM_SIZE_KWORDS 1, 2 or 4 Size of program memory in K-instructions -- '4' is only supported with 'V6'. -- C_JTAG_LOADER_ENABLE 0 or 1 Set to '1' to include JTAG Loader -- -- Notes -- -- If your design contains MULTIPLE KCPSM6 instances then only one should have the -- JTAG Loader enabled at a time (i.e. make sure that C_JTAG_LOADER_ENABLE is only set to -- '1' on one instance of the program memory). Advanced users may be interested to know -- that it is possible to connect JTAG Loader to multiple memories and then to use the -- JTAG Loader utility to specify which memory contents are to be modified. However, -- this scheme does require some effort to set up and the additional connectivity of the -- multiple BRAMs can impact the placement, routing and performance of the complete -- design. Please contact the author at Xilinx for more detailed information. -- -- Regardless of the size of program memory specified by C_RAM_SIZE_KWORDS, the complete -- 12-bit address bus is connected to KCPSM6. This enables the generic to be modified -- without requiring changes to the fundamental hardware definition. However, when the -- program memory is 1K then only the lower 10-bits of the address are actually used and -- the valid address range is 000 to 3FF hex. Likewise, for a 2K program only the lower -- 11-bits of the address are actually used and the valid address range is 000 to 7FF hex. -- -- Programs are stored in Block Memory (BRAM) and the number of BRAM used depends on the -- size of the program and the device family. -- -- In a Spartan-6 device a BRAM is capable of holding 1K instructions. Hence a 2K program -- will require 2 BRAMs to be used. Whilst it is possible to implement a 4K program in a -- Spartan-6 device this is a less natural fit within the architecture and either requires -- 4 BRAMs and a small amount of logic resulting in a lower performance or 5 BRAMs when -- performance is a critical factor. Due to these additional considerations this file -- does not support the selection of 4K when using Spartan-6. It is also possible to -- divide a BRAM into 2 smaller memories and therefore support a program up to only 512 -- instructions. If one of these special cases is required then please contact the authors -- at Xilinx to discuss and request a specific 'ROM_form' template that will meet your -- requirements. -- -- In a Virtex-6 device a BRAM is capable of holding 2K instructions so obviously a 2K -- program requires only a single BRAM. Each BRAM can also be divided into 2 smaller -- memories supporting programs of 1K in half of a 36k-bit BRAM (generally reported -- as being an 18k-bit BRAM). For a program of 4K instructions 2 BRAMs are required. -- -- -- Program defined by '{psmname}.psm'. -- -- Generated by KCPSM6 Assembler: {timestamp}. -- -- Assembler used ROM_form template: 3rd March 2011 -- -- Standard IEEE libraries -- -- package jtag_loader_pkg is function addr_width_calc (size_in_k: integer) return integer; end jtag_loader_pkg; -- package body jtag_loader_pkg is function addr_width_calc (size_in_k: integer) return integer is begin if (size_in_k = 1) then return 10; elsif (size_in_k = 2) then return 11; elsif (size_in_k = 4) then return 12; else report "Invalid BlockRAM size. Please set to 1, 2 or 4 K words." severity FAILURE; end if; return 0; end function addr_width_calc; end package body; -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.jtag_loader_pkg.ALL; -- -- The Unisim Library is used to define Xilinx primitives. It is also used during -- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd -- library unisim; use unisim.vcomponents.all; -- -- entity {name} is generic( C_FAMILY : string := "S6"; C_RAM_SIZE_KWORDS : integer := 1; C_JTAG_LOADER_ENABLE : integer := 0); Port ( address : in std_logic_vector(11 downto 0); instruction : out std_logic_vector(17 downto 0); enable : in std_logic; rdl : out std_logic; clk : in std_logic); end {name}; -- architecture low_level_definition of {name} is -- signal address_a : std_logic_vector(15 downto 0); signal data_in_a : std_logic_vector(35 downto 0); signal data_out_a : std_logic_vector(35 downto 0); signal data_out_a_l : std_logic_vector(35 downto 0); signal data_out_a_h : std_logic_vector(35 downto 0); signal address_b : std_logic_vector(15 downto 0); signal data_in_b : std_logic_vector(35 downto 0); signal data_in_b_l : std_logic_vector(35 downto 0); signal data_out_b : std_logic_vector(35 downto 0); signal data_out_b_l : std_logic_vector(35 downto 0); signal data_in_b_h : std_logic_vector(35 downto 0); signal data_out_b_h : std_logic_vector(35 downto 0); signal enable_b : std_logic; signal clk_b : std_logic; signal we_b : std_logic_vector(7 downto 0); -- signal jtag_addr : std_logic_vector(11 downto 0); signal jtag_we : std_logic; signal jtag_clk : std_logic; signal jtag_din : std_logic_vector(17 downto 0); signal jtag_dout : std_logic_vector(17 downto 0); signal jtag_dout_1 : std_logic_vector(17 downto 0); signal jtag_en : std_logic_vector(0 downto 0); -- signal picoblaze_reset : std_logic_vector(0 downto 0); signal rdl_bus : std_logic_vector(0 downto 0); -- constant BRAM_ADDRESS_WIDTH : integer := addr_width_calc(C_RAM_SIZE_KWORDS); -- -- component jtag_loader_6 generic( C_JTAG_LOADER_ENABLE : integer := 1; C_FAMILY : string := "V6"; C_NUM_PICOBLAZE : integer := 1; C_BRAM_MAX_ADDR_WIDTH : integer := 10; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18; C_JTAG_CHAIN : integer := 2; C_ADDR_WIDTH_0 : integer := 10; C_ADDR_WIDTH_1 : integer := 10; C_ADDR_WIDTH_2 : integer := 10; C_ADDR_WIDTH_3 : integer := 10; C_ADDR_WIDTH_4 : integer := 10; C_ADDR_WIDTH_5 : integer := 10; C_ADDR_WIDTH_6 : integer := 10; C_ADDR_WIDTH_7 : integer := 10); port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); jtag_din : out STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_addr : out STD_LOGIC_VECTOR(C_BRAM_MAX_ADDR_WIDTH-1 downto 0); jtag_clk : out std_logic; jtag_we : out std_logic; jtag_dout_0 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_1 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_2 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_3 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_4 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_5 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_6 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_7 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0)); end component; -- begin -- -- ram_1k_generate : if (C_RAM_SIZE_KWORDS = 1) generate s6: if (C_FAMILY = "S6") generate -- address_a(13 downto 0) <= address(9 downto 0) & "0000"; instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0); data_in_a <= "0000000000000000000000000000000000" & address(11 downto 10); jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0); address_b(13 downto 0) <= "00000000000000"; we_b(3 downto 0) <= "0000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0); address_b(13 downto 0) <= jtag_addr(9 downto 0) & "0000"; we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom: RAMB16BWER generic map ( DATA_WIDTH_A => 18, DOA_REG => 0, EN_RSTRAM_A => FALSE, INIT_A => X"000000000", RST_PRIORITY_A => "CE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", DATA_WIDTH_B => 18, DOB_REG => 0, EN_RSTRAM_B => FALSE, INIT_B => X"000000000", RST_PRIORITY_B => "CE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", RSTTYPE => "SYNC", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "SPARTAN6", INIT_00 => X"{INIT_00}", INIT_01 => X"{INIT_01}", INIT_02 => X"{INIT_02}", INIT_03 => X"{INIT_03}", INIT_04 => X"{INIT_04}", INIT_05 => X"{INIT_05}", INIT_06 => X"{INIT_06}", INIT_07 => X"{INIT_07}", INIT_08 => X"{INIT_08}", INIT_09 => X"{INIT_09}", INIT_0A => X"{INIT_0A}", INIT_0B => X"{INIT_0B}", INIT_0C => X"{INIT_0C}", INIT_0D => X"{INIT_0D}", INIT_0E => X"{INIT_0E}", INIT_0F => X"{INIT_0F}", INIT_10 => X"{INIT_10}", INIT_11 => X"{INIT_11}", INIT_12 => X"{INIT_12}", INIT_13 => X"{INIT_13}", INIT_14 => X"{INIT_14}", INIT_15 => X"{INIT_15}", INIT_16 => X"{INIT_16}", INIT_17 => X"{INIT_17}", INIT_18 => X"{INIT_18}", INIT_19 => X"{INIT_19}", INIT_1A => X"{INIT_1A}", INIT_1B => X"{INIT_1B}", INIT_1C => X"{INIT_1C}", INIT_1D => X"{INIT_1D}", INIT_1E => X"{INIT_1E}", INIT_1F => X"{INIT_1F}", INIT_20 => X"{INIT_20}", INIT_21 => X"{INIT_21}", INIT_22 => X"{INIT_22}", INIT_23 => X"{INIT_23}", INIT_24 => X"{INIT_24}", INIT_25 => X"{INIT_25}", INIT_26 => X"{INIT_26}", INIT_27 => X"{INIT_27}", INIT_28 => X"{INIT_28}", INIT_29 => X"{INIT_29}", INIT_2A => X"{INIT_2A}", INIT_2B => X"{INIT_2B}", INIT_2C => X"{INIT_2C}", INIT_2D => X"{INIT_2D}", INIT_2E => X"{INIT_2E}", INIT_2F => X"{INIT_2F}", INIT_30 => X"{INIT_30}", INIT_31 => X"{INIT_31}", INIT_32 => X"{INIT_32}", INIT_33 => X"{INIT_33}", INIT_34 => X"{INIT_34}", INIT_35 => X"{INIT_35}", INIT_36 => X"{INIT_36}", INIT_37 => X"{INIT_37}", INIT_38 => X"{INIT_38}", INIT_39 => X"{INIT_39}", INIT_3A => X"{INIT_3A}", INIT_3B => X"{INIT_3B}", INIT_3C => X"{INIT_3C}", INIT_3D => X"{INIT_3D}", INIT_3E => X"{INIT_3E}", INIT_3F => X"{INIT_3F}", INITP_00 => X"{INITP_00}", INITP_01 => X"{INITP_01}", INITP_02 => X"{INITP_02}", INITP_03 => X"{INITP_03}", INITP_04 => X"{INITP_04}", INITP_05 => X"{INITP_05}", INITP_06 => X"{INITP_06}", INITP_07 => X"{INITP_07}") port map( ADDRA => address_a(13 downto 0), ENA => enable, CLKA => clk, DOA => data_out_a(31 downto 0), DOPA => data_out_a(35 downto 32), DIA => data_in_a(31 downto 0), DIPA => data_in_a(35 downto 32), WEA => "0000", REGCEA => '0', RSTA => '0', ADDRB => address_b(13 downto 0), ENB => enable_b, CLKB => clk_b, DOB => data_out_b(31 downto 0), DOPB => data_out_b(35 downto 32), DIB => data_in_b(31 downto 0), DIPB => data_in_b(35 downto 32), WEB => we_b(3 downto 0), REGCEB => '0', RSTB => '0'); -- end generate s6; -- -- v6 : if (C_FAMILY = "V6") generate -- address_a(13 downto 0) <= address(9 downto 0) & "0000"; instruction <= data_out_a(17 downto 0); data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10); jtag_dout <= data_out_b(17 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b(17 downto 0) <= data_out_b(17 downto 0); address_b(13 downto 0) <= "00000000000000"; we_b(3 downto 0) <= "0000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b(17 downto 0) <= jtag_din(17 downto 0); address_b(13 downto 0) <= jtag_addr(9 downto 0) & "0000"; we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom: RAMB18E1 generic map ( READ_WIDTH_A => 18, WRITE_WIDTH_A => 18, DOA_REG => 0, INIT_A => "000000000000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 18, WRITE_WIDTH_B => 18, DOB_REG => 0, INIT_B => X"000000000000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", INIT_00 => X"{INIT_00}", INIT_01 => X"{INIT_01}", INIT_02 => X"{INIT_02}", INIT_03 => X"{INIT_03}", INIT_04 => X"{INIT_04}", INIT_05 => X"{INIT_05}", INIT_06 => X"{INIT_06}", INIT_07 => X"{INIT_07}", INIT_08 => X"{INIT_08}", INIT_09 => X"{INIT_09}", INIT_0A => X"{INIT_0A}", INIT_0B => X"{INIT_0B}", INIT_0C => X"{INIT_0C}", INIT_0D => X"{INIT_0D}", INIT_0E => X"{INIT_0E}", INIT_0F => X"{INIT_0F}", INIT_10 => X"{INIT_10}", INIT_11 => X"{INIT_11}", INIT_12 => X"{INIT_12}", INIT_13 => X"{INIT_13}", INIT_14 => X"{INIT_14}", INIT_15 => X"{INIT_15}", INIT_16 => X"{INIT_16}", INIT_17 => X"{INIT_17}", INIT_18 => X"{INIT_18}", INIT_19 => X"{INIT_19}", INIT_1A => X"{INIT_1A}", INIT_1B => X"{INIT_1B}", INIT_1C => X"{INIT_1C}", INIT_1D => X"{INIT_1D}", INIT_1E => X"{INIT_1E}", INIT_1F => X"{INIT_1F}", INIT_20 => X"{INIT_20}", INIT_21 => X"{INIT_21}", INIT_22 => X"{INIT_22}", INIT_23 => X"{INIT_23}", INIT_24 => X"{INIT_24}", INIT_25 => X"{INIT_25}", INIT_26 => X"{INIT_26}", INIT_27 => X"{INIT_27}", INIT_28 => X"{INIT_28}", INIT_29 => X"{INIT_29}", INIT_2A => X"{INIT_2A}", INIT_2B => X"{INIT_2B}", INIT_2C => X"{INIT_2C}", INIT_2D => X"{INIT_2D}", INIT_2E => X"{INIT_2E}", INIT_2F => X"{INIT_2F}", INIT_30 => X"{INIT_30}", INIT_31 => X"{INIT_31}", INIT_32 => X"{INIT_32}", INIT_33 => X"{INIT_33}", INIT_34 => X"{INIT_34}", INIT_35 => X"{INIT_35}", INIT_36 => X"{INIT_36}", INIT_37 => X"{INIT_37}", INIT_38 => X"{INIT_38}", INIT_39 => X"{INIT_39}", INIT_3A => X"{INIT_3A}", INIT_3B => X"{INIT_3B}", INIT_3C => X"{INIT_3C}", INIT_3D => X"{INIT_3D}", INIT_3E => X"{INIT_3E}", INIT_3F => X"{INIT_3F}", INITP_00 => X"{INITP_00}", INITP_01 => X"{INITP_01}", INITP_02 => X"{INITP_02}", INITP_03 => X"{INITP_03}", INITP_04 => X"{INITP_04}", INITP_05 => X"{INITP_05}", INITP_06 => X"{INITP_06}", INITP_07 => X"{INITP_07}") port map( ADDRARDADDR => address_a(13 downto 0), ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a(15 downto 0), DOPADOP => data_out_a(17 downto 16), DIADI => data_in_a(15 downto 0), DIPADIP => data_in_a(17 downto 16), WEA => "00", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b(13 downto 0), ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b(15 downto 0), DOPBDOP => data_out_b(17 downto 16), DIBDI => data_in_b(15 downto 0), DIPBDIP => data_in_b(17 downto 16), WEBWE => we_b(3 downto 0), REGCEB => '0', RSTRAMB => '0', RSTREGB => '0'); -- end generate v6; -- end generate ram_1k_generate; -- -- -- ram_2k_generate : if (C_RAM_SIZE_KWORDS = 2) generate -- -- s6: if (C_FAMILY = "S6") generate -- address_a(13 downto 0) <= address(10 downto 0) & "000"; instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0); data_in_a <= "00000000000000000000000000000000000" & address(11); jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0); data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0); address_b(13 downto 0) <= "00000000000000"; we_b(3 downto 0) <= "0000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9); data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0); address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000"; we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom_l: RAMB16BWER generic map ( DATA_WIDTH_A => 9, DOA_REG => 0, EN_RSTRAM_A => FALSE, INIT_A => X"000000000", RST_PRIORITY_A => "CE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", DATA_WIDTH_B => 9, DOB_REG => 0, EN_RSTRAM_B => FALSE, INIT_B => X"000000000", RST_PRIORITY_B => "CE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", RSTTYPE => "SYNC", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "SPARTAN6", INIT_00 => X"{[8:0]_INIT_00}", INIT_01 => X"{[8:0]_INIT_01}", INIT_02 => X"{[8:0]_INIT_02}", INIT_03 => X"{[8:0]_INIT_03}", INIT_04 => X"{[8:0]_INIT_04}", INIT_05 => X"{[8:0]_INIT_05}", INIT_06 => X"{[8:0]_INIT_06}", INIT_07 => X"{[8:0]_INIT_07}", INIT_08 => X"{[8:0]_INIT_08}", INIT_09 => X"{[8:0]_INIT_09}", INIT_0A => X"{[8:0]_INIT_0A}", INIT_0B => X"{[8:0]_INIT_0B}", INIT_0C => X"{[8:0]_INIT_0C}", INIT_0D => X"{[8:0]_INIT_0D}", INIT_0E => X"{[8:0]_INIT_0E}", INIT_0F => X"{[8:0]_INIT_0F}", INIT_10 => X"{[8:0]_INIT_10}", INIT_11 => X"{[8:0]_INIT_11}", INIT_12 => X"{[8:0]_INIT_12}", INIT_13 => X"{[8:0]_INIT_13}", INIT_14 => X"{[8:0]_INIT_14}", INIT_15 => X"{[8:0]_INIT_15}", INIT_16 => X"{[8:0]_INIT_16}", INIT_17 => X"{[8:0]_INIT_17}", INIT_18 => X"{[8:0]_INIT_18}", INIT_19 => X"{[8:0]_INIT_19}", INIT_1A => X"{[8:0]_INIT_1A}", INIT_1B => X"{[8:0]_INIT_1B}", INIT_1C => X"{[8:0]_INIT_1C}", INIT_1D => X"{[8:0]_INIT_1D}", INIT_1E => X"{[8:0]_INIT_1E}", INIT_1F => X"{[8:0]_INIT_1F}", INIT_20 => X"{[8:0]_INIT_20}", INIT_21 => X"{[8:0]_INIT_21}", INIT_22 => X"{[8:0]_INIT_22}", INIT_23 => X"{[8:0]_INIT_23}", INIT_24 => X"{[8:0]_INIT_24}", INIT_25 => X"{[8:0]_INIT_25}", INIT_26 => X"{[8:0]_INIT_26}", INIT_27 => X"{[8:0]_INIT_27}", INIT_28 => X"{[8:0]_INIT_28}", INIT_29 => X"{[8:0]_INIT_29}", INIT_2A => X"{[8:0]_INIT_2A}", INIT_2B => X"{[8:0]_INIT_2B}", INIT_2C => X"{[8:0]_INIT_2C}", INIT_2D => X"{[8:0]_INIT_2D}", INIT_2E => X"{[8:0]_INIT_2E}", INIT_2F => X"{[8:0]_INIT_2F}", INIT_30 => X"{[8:0]_INIT_30}", INIT_31 => X"{[8:0]_INIT_31}", INIT_32 => X"{[8:0]_INIT_32}", INIT_33 => X"{[8:0]_INIT_33}", INIT_34 => X"{[8:0]_INIT_34}", INIT_35 => X"{[8:0]_INIT_35}", INIT_36 => X"{[8:0]_INIT_36}", INIT_37 => X"{[8:0]_INIT_37}", INIT_38 => X"{[8:0]_INIT_38}", INIT_39 => X"{[8:0]_INIT_39}", INIT_3A => X"{[8:0]_INIT_3A}", INIT_3B => X"{[8:0]_INIT_3B}", INIT_3C => X"{[8:0]_INIT_3C}", INIT_3D => X"{[8:0]_INIT_3D}", INIT_3E => X"{[8:0]_INIT_3E}", INIT_3F => X"{[8:0]_INIT_3F}", INITP_00 => X"{[8:0]_INITP_00}", INITP_01 => X"{[8:0]_INITP_01}", INITP_02 => X"{[8:0]_INITP_02}", INITP_03 => X"{[8:0]_INITP_03}", INITP_04 => X"{[8:0]_INITP_04}", INITP_05 => X"{[8:0]_INITP_05}", INITP_06 => X"{[8:0]_INITP_06}", INITP_07 => X"{[8:0]_INITP_07}") port map( ADDRA => address_a(13 downto 0), ENA => enable, CLKA => clk, DOA => data_out_a_l(31 downto 0), DOPA => data_out_a_l(35 downto 32), DIA => data_in_a(31 downto 0), DIPA => data_in_a(35 downto 32), WEA => "0000", REGCEA => '0', RSTA => '0', ADDRB => address_b(13 downto 0), ENB => enable_b, CLKB => clk_b, DOB => data_out_b_l(31 downto 0), DOPB => data_out_b_l(35 downto 32), DIB => data_in_b_l(31 downto 0), DIPB => data_in_b_l(35 downto 32), WEB => we_b(3 downto 0), REGCEB => '0', RSTB => '0'); -- kcpsm6_rom_h: RAMB16BWER generic map ( DATA_WIDTH_A => 9, DOA_REG => 0, EN_RSTRAM_A => FALSE, INIT_A => X"000000000", RST_PRIORITY_A => "CE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", DATA_WIDTH_B => 9, DOB_REG => 0, EN_RSTRAM_B => FALSE, INIT_B => X"000000000", RST_PRIORITY_B => "CE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", RSTTYPE => "SYNC", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "SPARTAN6", INIT_00 => X"{[17:9]_INIT_00}", INIT_01 => X"{[17:9]_INIT_01}", INIT_02 => X"{[17:9]_INIT_02}", INIT_03 => X"{[17:9]_INIT_03}", INIT_04 => X"{[17:9]_INIT_04}", INIT_05 => X"{[17:9]_INIT_05}", INIT_06 => X"{[17:9]_INIT_06}", INIT_07 => X"{[17:9]_INIT_07}", INIT_08 => X"{[17:9]_INIT_08}", INIT_09 => X"{[17:9]_INIT_09}", INIT_0A => X"{[17:9]_INIT_0A}", INIT_0B => X"{[17:9]_INIT_0B}", INIT_0C => X"{[17:9]_INIT_0C}", INIT_0D => X"{[17:9]_INIT_0D}", INIT_0E => X"{[17:9]_INIT_0E}", INIT_0F => X"{[17:9]_INIT_0F}", INIT_10 => X"{[17:9]_INIT_10}", INIT_11 => X"{[17:9]_INIT_11}", INIT_12 => X"{[17:9]_INIT_12}", INIT_13 => X"{[17:9]_INIT_13}", INIT_14 => X"{[17:9]_INIT_14}", INIT_15 => X"{[17:9]_INIT_15}", INIT_16 => X"{[17:9]_INIT_16}", INIT_17 => X"{[17:9]_INIT_17}", INIT_18 => X"{[17:9]_INIT_18}", INIT_19 => X"{[17:9]_INIT_19}", INIT_1A => X"{[17:9]_INIT_1A}", INIT_1B => X"{[17:9]_INIT_1B}", INIT_1C => X"{[17:9]_INIT_1C}", INIT_1D => X"{[17:9]_INIT_1D}", INIT_1E => X"{[17:9]_INIT_1E}", INIT_1F => X"{[17:9]_INIT_1F}", INIT_20 => X"{[17:9]_INIT_20}", INIT_21 => X"{[17:9]_INIT_21}", INIT_22 => X"{[17:9]_INIT_22}", INIT_23 => X"{[17:9]_INIT_23}", INIT_24 => X"{[17:9]_INIT_24}", INIT_25 => X"{[17:9]_INIT_25}", INIT_26 => X"{[17:9]_INIT_26}", INIT_27 => X"{[17:9]_INIT_27}", INIT_28 => X"{[17:9]_INIT_28}", INIT_29 => X"{[17:9]_INIT_29}", INIT_2A => X"{[17:9]_INIT_2A}", INIT_2B => X"{[17:9]_INIT_2B}", INIT_2C => X"{[17:9]_INIT_2C}", INIT_2D => X"{[17:9]_INIT_2D}", INIT_2E => X"{[17:9]_INIT_2E}", INIT_2F => X"{[17:9]_INIT_2F}", INIT_30 => X"{[17:9]_INIT_30}", INIT_31 => X"{[17:9]_INIT_31}", INIT_32 => X"{[17:9]_INIT_32}", INIT_33 => X"{[17:9]_INIT_33}", INIT_34 => X"{[17:9]_INIT_34}", INIT_35 => X"{[17:9]_INIT_35}", INIT_36 => X"{[17:9]_INIT_36}", INIT_37 => X"{[17:9]_INIT_37}", INIT_38 => X"{[17:9]_INIT_38}", INIT_39 => X"{[17:9]_INIT_39}", INIT_3A => X"{[17:9]_INIT_3A}", INIT_3B => X"{[17:9]_INIT_3B}", INIT_3C => X"{[17:9]_INIT_3C}", INIT_3D => X"{[17:9]_INIT_3D}", INIT_3E => X"{[17:9]_INIT_3E}", INIT_3F => X"{[17:9]_INIT_3F}", INITP_00 => X"{[17:9]_INITP_00}", INITP_01 => X"{[17:9]_INITP_01}", INITP_02 => X"{[17:9]_INITP_02}", INITP_03 => X"{[17:9]_INITP_03}", INITP_04 => X"{[17:9]_INITP_04}", INITP_05 => X"{[17:9]_INITP_05}", INITP_06 => X"{[17:9]_INITP_06}", INITP_07 => X"{[17:9]_INITP_07}") port map( ADDRA => address_a(13 downto 0), ENA => enable, CLKA => clk, DOA => data_out_a_h(31 downto 0), DOPA => data_out_a_h(35 downto 32), DIA => data_in_a(31 downto 0), DIPA => data_in_a(35 downto 32), WEA => "0000", REGCEA => '0', RSTA => '0', ADDRB => address_b(13 downto 0), ENB => enable_b, CLKB => clk_b, DOB => data_out_b_h(31 downto 0), DOPB => data_out_b_h(35 downto 32), DIB => data_in_b_h(31 downto 0), DIPB => data_in_b_h(35 downto 32), WEB => we_b(3 downto 0), REGCEB => '0', RSTB => '0'); -- end generate s6; -- -- v6 : if (C_FAMILY = "V6") generate -- address_a <= '0' & address(10 downto 0) & "0000"; instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0); data_in_a <= "00000000000000000000000000000000000" & address(11); jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0); address_b <= "0000000000000000"; we_b <= "00000000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0); address_b <= '0' & jtag_addr(10 downto 0) & "0000"; we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom: RAMB36E1 generic map ( READ_WIDTH_A => 18, WRITE_WIDTH_A => 18, DOA_REG => 0, INIT_A => X"000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 18, WRITE_WIDTH_B => 18, DOB_REG => 0, INIT_B => X"000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", EN_ECC_READ => FALSE, EN_ECC_WRITE => FALSE, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", INIT_00 => X"{INIT_00}", INIT_01 => X"{INIT_01}", INIT_02 => X"{INIT_02}", INIT_03 => X"{INIT_03}", INIT_04 => X"{INIT_04}", INIT_05 => X"{INIT_05}", INIT_06 => X"{INIT_06}", INIT_07 => X"{INIT_07}", INIT_08 => X"{INIT_08}", INIT_09 => X"{INIT_09}", INIT_0A => X"{INIT_0A}", INIT_0B => X"{INIT_0B}", INIT_0C => X"{INIT_0C}", INIT_0D => X"{INIT_0D}", INIT_0E => X"{INIT_0E}", INIT_0F => X"{INIT_0F}", INIT_10 => X"{INIT_10}", INIT_11 => X"{INIT_11}", INIT_12 => X"{INIT_12}", INIT_13 => X"{INIT_13}", INIT_14 => X"{INIT_14}", INIT_15 => X"{INIT_15}", INIT_16 => X"{INIT_16}", INIT_17 => X"{INIT_17}", INIT_18 => X"{INIT_18}", INIT_19 => X"{INIT_19}", INIT_1A => X"{INIT_1A}", INIT_1B => X"{INIT_1B}", INIT_1C => X"{INIT_1C}", INIT_1D => X"{INIT_1D}", INIT_1E => X"{INIT_1E}", INIT_1F => X"{INIT_1F}", INIT_20 => X"{INIT_20}", INIT_21 => X"{INIT_21}", INIT_22 => X"{INIT_22}", INIT_23 => X"{INIT_23}", INIT_24 => X"{INIT_24}", INIT_25 => X"{INIT_25}", INIT_26 => X"{INIT_26}", INIT_27 => X"{INIT_27}", INIT_28 => X"{INIT_28}", INIT_29 => X"{INIT_29}", INIT_2A => X"{INIT_2A}", INIT_2B => X"{INIT_2B}", INIT_2C => X"{INIT_2C}", INIT_2D => X"{INIT_2D}", INIT_2E => X"{INIT_2E}", INIT_2F => X"{INIT_2F}", INIT_30 => X"{INIT_30}", INIT_31 => X"{INIT_31}", INIT_32 => X"{INIT_32}", INIT_33 => X"{INIT_33}", INIT_34 => X"{INIT_34}", INIT_35 => X"{INIT_35}", INIT_36 => X"{INIT_36}", INIT_37 => X"{INIT_37}", INIT_38 => X"{INIT_38}", INIT_39 => X"{INIT_39}", INIT_3A => X"{INIT_3A}", INIT_3B => X"{INIT_3B}", INIT_3C => X"{INIT_3C}", INIT_3D => X"{INIT_3D}", INIT_3E => X"{INIT_3E}", INIT_3F => X"{INIT_3F}", INIT_40 => X"{INIT_40}", INIT_41 => X"{INIT_41}", INIT_42 => X"{INIT_42}", INIT_43 => X"{INIT_43}", INIT_44 => X"{INIT_44}", INIT_45 => X"{INIT_45}", INIT_46 => X"{INIT_46}", INIT_47 => X"{INIT_47}", INIT_48 => X"{INIT_48}", INIT_49 => X"{INIT_49}", INIT_4A => X"{INIT_4A}", INIT_4B => X"{INIT_4B}", INIT_4C => X"{INIT_4C}", INIT_4D => X"{INIT_4D}", INIT_4E => X"{INIT_4E}", INIT_4F => X"{INIT_4F}", INIT_50 => X"{INIT_50}", INIT_51 => X"{INIT_51}", INIT_52 => X"{INIT_52}", INIT_53 => X"{INIT_53}", INIT_54 => X"{INIT_54}", INIT_55 => X"{INIT_55}", INIT_56 => X"{INIT_56}", INIT_57 => X"{INIT_57}", INIT_58 => X"{INIT_58}", INIT_59 => X"{INIT_59}", INIT_5A => X"{INIT_5A}", INIT_5B => X"{INIT_5B}", INIT_5C => X"{INIT_5C}", INIT_5D => X"{INIT_5D}", INIT_5E => X"{INIT_5E}", INIT_5F => X"{INIT_5F}", INIT_60 => X"{INIT_60}", INIT_61 => X"{INIT_61}", INIT_62 => X"{INIT_62}", INIT_63 => X"{INIT_63}", INIT_64 => X"{INIT_64}", INIT_65 => X"{INIT_65}", INIT_66 => X"{INIT_66}", INIT_67 => X"{INIT_67}", INIT_68 => X"{INIT_68}", INIT_69 => X"{INIT_69}", INIT_6A => X"{INIT_6A}", INIT_6B => X"{INIT_6B}", INIT_6C => X"{INIT_6C}", INIT_6D => X"{INIT_6D}", INIT_6E => X"{INIT_6E}", INIT_6F => X"{INIT_6F}", INIT_70 => X"{INIT_70}", INIT_71 => X"{INIT_71}", INIT_72 => X"{INIT_72}", INIT_73 => X"{INIT_73}", INIT_74 => X"{INIT_74}", INIT_75 => X"{INIT_75}", INIT_76 => X"{INIT_76}", INIT_77 => X"{INIT_77}", INIT_78 => X"{INIT_78}", INIT_79 => X"{INIT_79}", INIT_7A => X"{INIT_7A}", INIT_7B => X"{INIT_7B}", INIT_7C => X"{INIT_7C}", INIT_7D => X"{INIT_7D}", INIT_7E => X"{INIT_7E}", INIT_7F => X"{INIT_7F}", INITP_00 => X"{INITP_00}", INITP_01 => X"{INITP_01}", INITP_02 => X"{INITP_02}", INITP_03 => X"{INITP_03}", INITP_04 => X"{INITP_04}", INITP_05 => X"{INITP_05}", INITP_06 => X"{INITP_06}", INITP_07 => X"{INITP_07}", INITP_08 => X"{INITP_08}", INITP_09 => X"{INITP_09}", INITP_0A => X"{INITP_0A}", INITP_0B => X"{INITP_0B}", INITP_0C => X"{INITP_0C}", INITP_0D => X"{INITP_0D}", INITP_0E => X"{INITP_0E}", INITP_0F => X"{INITP_0F}") port map( ADDRARDADDR => address_a, ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a(31 downto 0), DOPADOP => data_out_a(35 downto 32), DIADI => data_in_a(31 downto 0), DIPADIP => data_in_a(35 downto 32), WEA => "0000", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b, ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b(31 downto 0), DOPBDOP => data_out_b(35 downto 32), DIBDI => data_in_b(31 downto 0), DIPBDIP => data_in_b(35 downto 32), WEBWE => we_b, REGCEB => '0', RSTRAMB => '0', RSTREGB => '0', CASCADEINA => '0', CASCADEINB => '0', INJECTDBITERR => '0', INJECTSBITERR => '0'); -- end generate v6; -- end generate ram_2k_generate; -- -- ram_4k_generate : if (C_RAM_SIZE_KWORDS = 4) generate s6: if (C_FAMILY = "S6") generate assert(1=0) report "4K BRAM in Spartan-6 is a special case not supported by this template." severity FAILURE; end generate s6; -- v6 : if (C_FAMILY = "V6") generate -- address_a <= '0' & address(11 downto 0) & "000"; instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0); data_in_a <= "000000000000000000000000000000000000"; jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0); data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0); address_b <= "0000000000000000"; we_b <= "00000000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9); data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0); address_b <= '0' & jtag_addr(11 downto 0) & "000"; we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom_l: RAMB36E1 generic map ( READ_WIDTH_A => 9, WRITE_WIDTH_A => 9, DOA_REG => 0, INIT_A => X"000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 9, WRITE_WIDTH_B => 9, DOB_REG => 0, INIT_B => X"000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", EN_ECC_READ => FALSE, EN_ECC_WRITE => FALSE, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", INIT_00 => X"{[8:0]_INIT_00}", INIT_01 => X"{[8:0]_INIT_01}", INIT_02 => X"{[8:0]_INIT_02}", INIT_03 => X"{[8:0]_INIT_03}", INIT_04 => X"{[8:0]_INIT_04}", INIT_05 => X"{[8:0]_INIT_05}", INIT_06 => X"{[8:0]_INIT_06}", INIT_07 => X"{[8:0]_INIT_07}", INIT_08 => X"{[8:0]_INIT_08}", INIT_09 => X"{[8:0]_INIT_09}", INIT_0A => X"{[8:0]_INIT_0A}", INIT_0B => X"{[8:0]_INIT_0B}", INIT_0C => X"{[8:0]_INIT_0C}", INIT_0D => X"{[8:0]_INIT_0D}", INIT_0E => X"{[8:0]_INIT_0E}", INIT_0F => X"{[8:0]_INIT_0F}", INIT_10 => X"{[8:0]_INIT_10}", INIT_11 => X"{[8:0]_INIT_11}", INIT_12 => X"{[8:0]_INIT_12}", INIT_13 => X"{[8:0]_INIT_13}", INIT_14 => X"{[8:0]_INIT_14}", INIT_15 => X"{[8:0]_INIT_15}", INIT_16 => X"{[8:0]_INIT_16}", INIT_17 => X"{[8:0]_INIT_17}", INIT_18 => X"{[8:0]_INIT_18}", INIT_19 => X"{[8:0]_INIT_19}", INIT_1A => X"{[8:0]_INIT_1A}", INIT_1B => X"{[8:0]_INIT_1B}", INIT_1C => X"{[8:0]_INIT_1C}", INIT_1D => X"{[8:0]_INIT_1D}", INIT_1E => X"{[8:0]_INIT_1E}", INIT_1F => X"{[8:0]_INIT_1F}", INIT_20 => X"{[8:0]_INIT_20}", INIT_21 => X"{[8:0]_INIT_21}", INIT_22 => X"{[8:0]_INIT_22}", INIT_23 => X"{[8:0]_INIT_23}", INIT_24 => X"{[8:0]_INIT_24}", INIT_25 => X"{[8:0]_INIT_25}", INIT_26 => X"{[8:0]_INIT_26}", INIT_27 => X"{[8:0]_INIT_27}", INIT_28 => X"{[8:0]_INIT_28}", INIT_29 => X"{[8:0]_INIT_29}", INIT_2A => X"{[8:0]_INIT_2A}", INIT_2B => X"{[8:0]_INIT_2B}", INIT_2C => X"{[8:0]_INIT_2C}", INIT_2D => X"{[8:0]_INIT_2D}", INIT_2E => X"{[8:0]_INIT_2E}", INIT_2F => X"{[8:0]_INIT_2F}", INIT_30 => X"{[8:0]_INIT_30}", INIT_31 => X"{[8:0]_INIT_31}", INIT_32 => X"{[8:0]_INIT_32}", INIT_33 => X"{[8:0]_INIT_33}", INIT_34 => X"{[8:0]_INIT_34}", INIT_35 => X"{[8:0]_INIT_35}", INIT_36 => X"{[8:0]_INIT_36}", INIT_37 => X"{[8:0]_INIT_37}", INIT_38 => X"{[8:0]_INIT_38}", INIT_39 => X"{[8:0]_INIT_39}", INIT_3A => X"{[8:0]_INIT_3A}", INIT_3B => X"{[8:0]_INIT_3B}", INIT_3C => X"{[8:0]_INIT_3C}", INIT_3D => X"{[8:0]_INIT_3D}", INIT_3E => X"{[8:0]_INIT_3E}", INIT_3F => X"{[8:0]_INIT_3F}", INIT_40 => X"{[8:0]_INIT_40}", INIT_41 => X"{[8:0]_INIT_41}", INIT_42 => X"{[8:0]_INIT_42}", INIT_43 => X"{[8:0]_INIT_43}", INIT_44 => X"{[8:0]_INIT_44}", INIT_45 => X"{[8:0]_INIT_45}", INIT_46 => X"{[8:0]_INIT_46}", INIT_47 => X"{[8:0]_INIT_47}", INIT_48 => X"{[8:0]_INIT_48}", INIT_49 => X"{[8:0]_INIT_49}", INIT_4A => X"{[8:0]_INIT_4A}", INIT_4B => X"{[8:0]_INIT_4B}", INIT_4C => X"{[8:0]_INIT_4C}", INIT_4D => X"{[8:0]_INIT_4D}", INIT_4E => X"{[8:0]_INIT_4E}", INIT_4F => X"{[8:0]_INIT_4F}", INIT_50 => X"{[8:0]_INIT_50}", INIT_51 => X"{[8:0]_INIT_51}", INIT_52 => X"{[8:0]_INIT_52}", INIT_53 => X"{[8:0]_INIT_53}", INIT_54 => X"{[8:0]_INIT_54}", INIT_55 => X"{[8:0]_INIT_55}", INIT_56 => X"{[8:0]_INIT_56}", INIT_57 => X"{[8:0]_INIT_57}", INIT_58 => X"{[8:0]_INIT_58}", INIT_59 => X"{[8:0]_INIT_59}", INIT_5A => X"{[8:0]_INIT_5A}", INIT_5B => X"{[8:0]_INIT_5B}", INIT_5C => X"{[8:0]_INIT_5C}", INIT_5D => X"{[8:0]_INIT_5D}", INIT_5E => X"{[8:0]_INIT_5E}", INIT_5F => X"{[8:0]_INIT_5F}", INIT_60 => X"{[8:0]_INIT_60}", INIT_61 => X"{[8:0]_INIT_61}", INIT_62 => X"{[8:0]_INIT_62}", INIT_63 => X"{[8:0]_INIT_63}", INIT_64 => X"{[8:0]_INIT_64}", INIT_65 => X"{[8:0]_INIT_65}", INIT_66 => X"{[8:0]_INIT_66}", INIT_67 => X"{[8:0]_INIT_67}", INIT_68 => X"{[8:0]_INIT_68}", INIT_69 => X"{[8:0]_INIT_69}", INIT_6A => X"{[8:0]_INIT_6A}", INIT_6B => X"{[8:0]_INIT_6B}", INIT_6C => X"{[8:0]_INIT_6C}", INIT_6D => X"{[8:0]_INIT_6D}", INIT_6E => X"{[8:0]_INIT_6E}", INIT_6F => X"{[8:0]_INIT_6F}", INIT_70 => X"{[8:0]_INIT_70}", INIT_71 => X"{[8:0]_INIT_71}", INIT_72 => X"{[8:0]_INIT_72}", INIT_73 => X"{[8:0]_INIT_73}", INIT_74 => X"{[8:0]_INIT_74}", INIT_75 => X"{[8:0]_INIT_75}", INIT_76 => X"{[8:0]_INIT_76}", INIT_77 => X"{[8:0]_INIT_77}", INIT_78 => X"{[8:0]_INIT_78}", INIT_79 => X"{[8:0]_INIT_79}", INIT_7A => X"{[8:0]_INIT_7A}", INIT_7B => X"{[8:0]_INIT_7B}", INIT_7C => X"{[8:0]_INIT_7C}", INIT_7D => X"{[8:0]_INIT_7D}", INIT_7E => X"{[8:0]_INIT_7E}", INIT_7F => X"{[8:0]_INIT_7F}", INITP_00 => X"{[8:0]_INITP_00}", INITP_01 => X"{[8:0]_INITP_01}", INITP_02 => X"{[8:0]_INITP_02}", INITP_03 => X"{[8:0]_INITP_03}", INITP_04 => X"{[8:0]_INITP_04}", INITP_05 => X"{[8:0]_INITP_05}", INITP_06 => X"{[8:0]_INITP_06}", INITP_07 => X"{[8:0]_INITP_07}", INITP_08 => X"{[8:0]_INITP_08}", INITP_09 => X"{[8:0]_INITP_09}", INITP_0A => X"{[8:0]_INITP_0A}", INITP_0B => X"{[8:0]_INITP_0B}", INITP_0C => X"{[8:0]_INITP_0C}", INITP_0D => X"{[8:0]_INITP_0D}", INITP_0E => X"{[8:0]_INITP_0E}", INITP_0F => X"{[8:0]_INITP_0F}") port map( ADDRARDADDR => address_a, ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a_l(31 downto 0), DOPADOP => data_out_a_l(35 downto 32), DIADI => data_in_a(31 downto 0), DIPADIP => data_in_a(35 downto 32), WEA => "0000", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b, ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b_l(31 downto 0), DOPBDOP => data_out_b_l(35 downto 32), DIBDI => data_in_b_l(31 downto 0), DIPBDIP => data_in_b_l(35 downto 32), WEBWE => we_b, REGCEB => '0', RSTRAMB => '0', RSTREGB => '0', CASCADEINA => '0', CASCADEINB => '0', INJECTDBITERR => '0', INJECTSBITERR => '0'); -- kcpsm6_rom_h: RAMB36E1 generic map ( READ_WIDTH_A => 9, WRITE_WIDTH_A => 9, DOA_REG => 0, INIT_A => X"000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 9, WRITE_WIDTH_B => 9, DOB_REG => 0, INIT_B => X"000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", EN_ECC_READ => FALSE, EN_ECC_WRITE => FALSE, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", INIT_00 => X"{[17:9]_INIT_00}", INIT_01 => X"{[17:9]_INIT_01}", INIT_02 => X"{[17:9]_INIT_02}", INIT_03 => X"{[17:9]_INIT_03}", INIT_04 => X"{[17:9]_INIT_04}", INIT_05 => X"{[17:9]_INIT_05}", INIT_06 => X"{[17:9]_INIT_06}", INIT_07 => X"{[17:9]_INIT_07}", INIT_08 => X"{[17:9]_INIT_08}", INIT_09 => X"{[17:9]_INIT_09}", INIT_0A => X"{[17:9]_INIT_0A}", INIT_0B => X"{[17:9]_INIT_0B}", INIT_0C => X"{[17:9]_INIT_0C}", INIT_0D => X"{[17:9]_INIT_0D}", INIT_0E => X"{[17:9]_INIT_0E}", INIT_0F => X"{[17:9]_INIT_0F}", INIT_10 => X"{[17:9]_INIT_10}", INIT_11 => X"{[17:9]_INIT_11}", INIT_12 => X"{[17:9]_INIT_12}", INIT_13 => X"{[17:9]_INIT_13}", INIT_14 => X"{[17:9]_INIT_14}", INIT_15 => X"{[17:9]_INIT_15}", INIT_16 => X"{[17:9]_INIT_16}", INIT_17 => X"{[17:9]_INIT_17}", INIT_18 => X"{[17:9]_INIT_18}", INIT_19 => X"{[17:9]_INIT_19}", INIT_1A => X"{[17:9]_INIT_1A}", INIT_1B => X"{[17:9]_INIT_1B}", INIT_1C => X"{[17:9]_INIT_1C}", INIT_1D => X"{[17:9]_INIT_1D}", INIT_1E => X"{[17:9]_INIT_1E}", INIT_1F => X"{[17:9]_INIT_1F}", INIT_20 => X"{[17:9]_INIT_20}", INIT_21 => X"{[17:9]_INIT_21}", INIT_22 => X"{[17:9]_INIT_22}", INIT_23 => X"{[17:9]_INIT_23}", INIT_24 => X"{[17:9]_INIT_24}", INIT_25 => X"{[17:9]_INIT_25}", INIT_26 => X"{[17:9]_INIT_26}", INIT_27 => X"{[17:9]_INIT_27}", INIT_28 => X"{[17:9]_INIT_28}", INIT_29 => X"{[17:9]_INIT_29}", INIT_2A => X"{[17:9]_INIT_2A}", INIT_2B => X"{[17:9]_INIT_2B}", INIT_2C => X"{[17:9]_INIT_2C}", INIT_2D => X"{[17:9]_INIT_2D}", INIT_2E => X"{[17:9]_INIT_2E}", INIT_2F => X"{[17:9]_INIT_2F}", INIT_30 => X"{[17:9]_INIT_30}", INIT_31 => X"{[17:9]_INIT_31}", INIT_32 => X"{[17:9]_INIT_32}", INIT_33 => X"{[17:9]_INIT_33}", INIT_34 => X"{[17:9]_INIT_34}", INIT_35 => X"{[17:9]_INIT_35}", INIT_36 => X"{[17:9]_INIT_36}", INIT_37 => X"{[17:9]_INIT_37}", INIT_38 => X"{[17:9]_INIT_38}", INIT_39 => X"{[17:9]_INIT_39}", INIT_3A => X"{[17:9]_INIT_3A}", INIT_3B => X"{[17:9]_INIT_3B}", INIT_3C => X"{[17:9]_INIT_3C}", INIT_3D => X"{[17:9]_INIT_3D}", INIT_3E => X"{[17:9]_INIT_3E}", INIT_3F => X"{[17:9]_INIT_3F}", INIT_40 => X"{[17:9]_INIT_40}", INIT_41 => X"{[17:9]_INIT_41}", INIT_42 => X"{[17:9]_INIT_42}", INIT_43 => X"{[17:9]_INIT_43}", INIT_44 => X"{[17:9]_INIT_44}", INIT_45 => X"{[17:9]_INIT_45}", INIT_46 => X"{[17:9]_INIT_46}", INIT_47 => X"{[17:9]_INIT_47}", INIT_48 => X"{[17:9]_INIT_48}", INIT_49 => X"{[17:9]_INIT_49}", INIT_4A => X"{[17:9]_INIT_4A}", INIT_4B => X"{[17:9]_INIT_4B}", INIT_4C => X"{[17:9]_INIT_4C}", INIT_4D => X"{[17:9]_INIT_4D}", INIT_4E => X"{[17:9]_INIT_4E}", INIT_4F => X"{[17:9]_INIT_4F}", INIT_50 => X"{[17:9]_INIT_50}", INIT_51 => X"{[17:9]_INIT_51}", INIT_52 => X"{[17:9]_INIT_52}", INIT_53 => X"{[17:9]_INIT_53}", INIT_54 => X"{[17:9]_INIT_54}", INIT_55 => X"{[17:9]_INIT_55}", INIT_56 => X"{[17:9]_INIT_56}", INIT_57 => X"{[17:9]_INIT_57}", INIT_58 => X"{[17:9]_INIT_58}", INIT_59 => X"{[17:9]_INIT_59}", INIT_5A => X"{[17:9]_INIT_5A}", INIT_5B => X"{[17:9]_INIT_5B}", INIT_5C => X"{[17:9]_INIT_5C}", INIT_5D => X"{[17:9]_INIT_5D}", INIT_5E => X"{[17:9]_INIT_5E}", INIT_5F => X"{[17:9]_INIT_5F}", INIT_60 => X"{[17:9]_INIT_60}", INIT_61 => X"{[17:9]_INIT_61}", INIT_62 => X"{[17:9]_INIT_62}", INIT_63 => X"{[17:9]_INIT_63}", INIT_64 => X"{[17:9]_INIT_64}", INIT_65 => X"{[17:9]_INIT_65}", INIT_66 => X"{[17:9]_INIT_66}", INIT_67 => X"{[17:9]_INIT_67}", INIT_68 => X"{[17:9]_INIT_68}", INIT_69 => X"{[17:9]_INIT_69}", INIT_6A => X"{[17:9]_INIT_6A}", INIT_6B => X"{[17:9]_INIT_6B}", INIT_6C => X"{[17:9]_INIT_6C}", INIT_6D => X"{[17:9]_INIT_6D}", INIT_6E => X"{[17:9]_INIT_6E}", INIT_6F => X"{[17:9]_INIT_6F}", INIT_70 => X"{[17:9]_INIT_70}", INIT_71 => X"{[17:9]_INIT_71}", INIT_72 => X"{[17:9]_INIT_72}", INIT_73 => X"{[17:9]_INIT_73}", INIT_74 => X"{[17:9]_INIT_74}", INIT_75 => X"{[17:9]_INIT_75}", INIT_76 => X"{[17:9]_INIT_76}", INIT_77 => X"{[17:9]_INIT_77}", INIT_78 => X"{[17:9]_INIT_78}", INIT_79 => X"{[17:9]_INIT_79}", INIT_7A => X"{[17:9]_INIT_7A}", INIT_7B => X"{[17:9]_INIT_7B}", INIT_7C => X"{[17:9]_INIT_7C}", INIT_7D => X"{[17:9]_INIT_7D}", INIT_7E => X"{[17:9]_INIT_7E}", INIT_7F => X"{[17:9]_INIT_7F}", INITP_00 => X"{[17:9]_INITP_00}", INITP_01 => X"{[17:9]_INITP_01}", INITP_02 => X"{[17:9]_INITP_02}", INITP_03 => X"{[17:9]_INITP_03}", INITP_04 => X"{[17:9]_INITP_04}", INITP_05 => X"{[17:9]_INITP_05}", INITP_06 => X"{[17:9]_INITP_06}", INITP_07 => X"{[17:9]_INITP_07}", INITP_08 => X"{[17:9]_INITP_08}", INITP_09 => X"{[17:9]_INITP_09}", INITP_0A => X"{[17:9]_INITP_0A}", INITP_0B => X"{[17:9]_INITP_0B}", INITP_0C => X"{[17:9]_INITP_0C}", INITP_0D => X"{[17:9]_INITP_0D}", INITP_0E => X"{[17:9]_INITP_0E}", INITP_0F => X"{[17:9]_INITP_0F}") port map( ADDRARDADDR => address_a, ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a_h(31 downto 0), DOPADOP => data_out_a_h(35 downto 32), DIADI => data_in_a(31 downto 0), DIPADIP => data_in_a(35 downto 32), WEA => "0000", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b, ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b_h(31 downto 0), DOPBDOP => data_out_b_h(35 downto 32), DIBDI => data_in_b_h(31 downto 0), DIPBDIP => data_in_b_h(35 downto 32), WEBWE => we_b, REGCEB => '0', RSTRAMB => '0', RSTREGB => '0', CASCADEINA => '0', CASCADEINB => '0', INJECTDBITERR => '0', INJECTSBITERR => '0'); -- end generate v6; -- end generate ram_4k_generate; -- -- -- -- -- JTAG Loader -- instantiate_loader : if (C_JTAG_LOADER_ENABLE = 1) generate -- jtag_loader_6_inst : jtag_loader_6 generic map( C_FAMILY => C_FAMILY, C_NUM_PICOBLAZE => 1, C_JTAG_LOADER_ENABLE => C_JTAG_LOADER_ENABLE, C_BRAM_MAX_ADDR_WIDTH => BRAM_ADDRESS_WIDTH, C_ADDR_WIDTH_0 => BRAM_ADDRESS_WIDTH) port map( picoblaze_reset => rdl_bus, jtag_en => jtag_en, jtag_din => jtag_din, jtag_addr => jtag_addr(BRAM_ADDRESS_WIDTH-1 downto 0), jtag_clk => jtag_clk, jtag_we => jtag_we, jtag_dout_0 => jtag_dout, jtag_dout_1 => jtag_dout, -- ports 1-7 are not used jtag_dout_2 => jtag_dout, -- in a 1 device debug jtag_dout_3 => jtag_dout, -- session. However, Synplify jtag_dout_4 => jtag_dout, -- etc require all ports to jtag_dout_5 => jtag_dout, -- be connected jtag_dout_6 => jtag_dout, jtag_dout_7 => jtag_dout); -- end generate instantiate_loader; -- end low_level_definition; -- -- -- JTAG Loader 6 - Version 6.00 -- Kris Chaplin 4 February 2010 -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- library unisim; use unisim.vcomponents.all; -- entity jtag_loader_6 is generic( C_JTAG_LOADER_ENABLE : integer := 1; C_FAMILY : string := "V6"; C_NUM_PICOBLAZE : integer := 1; C_BRAM_MAX_ADDR_WIDTH : integer := 10; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18; C_JTAG_CHAIN : integer := 2; C_ADDR_WIDTH_0 : integer := 10; C_ADDR_WIDTH_1 : integer := 10; C_ADDR_WIDTH_2 : integer := 10; C_ADDR_WIDTH_3 : integer := 10; C_ADDR_WIDTH_4 : integer := 10; C_ADDR_WIDTH_5 : integer := 10; C_ADDR_WIDTH_6 : integer := 10; C_ADDR_WIDTH_7 : integer := 10); port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); jtag_din : out std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0'); jtag_addr : out std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0) := (others => '0'); jtag_clk : out std_logic := '0'; jtag_we : out std_logic := '0'; jtag_dout_0 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_1 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_2 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_3 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_4 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_5 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_6 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_7 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0)); end jtag_loader_6; -- architecture Behavioral of jtag_loader_6 is -- component bscan_logic generic( C_JTAG_CHAIN : integer := 2; C_BUFFER_SHIFT_CLOCK : boolean := TRUE; C_FAMILY : string := "S6"); port( shift_dout : in std_logic; shift_clk : out std_logic; bram_en : out std_logic; shift_din : out std_logic; bram_strobe : out std_logic; capture : out std_logic; shift : out std_logic); end component; -- component jtag_shifter generic ( C_NUM_PICOBLAZE : integer := 1; C_BRAM_MAX_ADDR_WIDTH : integer := 10; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18); port( shift_clk : in std_logic; shift_din : in std_logic; shift : in std_logic; shift_dout : out std_logic; control_reg_ce : out std_logic; bram_ce : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); bram_a : out std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0); din_load : in std_logic; din : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); bram_d : out std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); bram_we : out std_logic); end component; -- component control_registers generic ( C_NUM_PICOBLAZE : integer := 1; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18; C_ADDR_WIDTH_0 : integer := 10; C_ADDR_WIDTH_1 : integer := 10; C_ADDR_WIDTH_2 : integer := 10; C_ADDR_WIDTH_3 : integer := 10; C_ADDR_WIDTH_4 : integer := 10; C_ADDR_WIDTH_5 : integer := 10; C_ADDR_WIDTH_6 : integer := 10; C_ADDR_WIDTH_7 : integer := 10; C_BRAM_MAX_ADDR_WIDTH : integer := 10); port( en : in std_logic; ce : in std_logic; wnr : in std_logic; clk : in std_logic; a : in std_logic_vector(3 downto 0); din : in std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); dout : out std_logic_vector(7 downto 0); picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0)); end component; -- signal shift_clk : std_logic; signal shift_din : std_logic; signal shift_dout : std_logic; signal shift : std_logic; signal capture : std_logic; -- signal control_reg_ce : std_logic; signal bram_ce : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); signal bus_zero : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); signal jtag_en_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); signal jtag_en_expanded : std_logic_vector(7 downto 0) := (others => '0'); signal jtag_addr_int : std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0); signal jtag_din_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal control_din : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0'); signal control_dout : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0'); signal bram_dout_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0'); signal jtag_we_int : std_logic; signal jtag_clk_int : std_logic; signal bram_ce_valid : std_logic; signal din_load : std_logic; -- signal jtag_dout_0_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_1_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_2_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_3_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_4_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_5_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_6_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_7_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal picoblaze_reset_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); -- begin bus_zero <= (others => '0'); -- jtag_loader_gen: if (C_JTAG_LOADER_ENABLE = 1) generate -- Inst_bscan_logic: bscan_logic generic map ( C_JTAG_CHAIN => C_JTAG_CHAIN, C_BUFFER_SHIFT_CLOCK => TRUE, C_FAMILY => C_FAMILY ) port map( shift_dout => shift_dout, shift_clk => shift_clk, bram_en => bram_ce_valid, shift_din => shift_din, bram_strobe => jtag_clk_int, capture => capture, shift => shift ); -- Inst_jtag_shifter: jtag_shifter generic map( C_NUM_PICOBLAZE => C_NUM_PICOBLAZE, C_BRAM_MAX_ADDR_WIDTH => C_BRAM_MAX_ADDR_WIDTH, C_PICOBLAZE_INSTRUCTION_DATA_WIDTH => C_PICOBLAZE_INSTRUCTION_DATA_WIDTH ) port map( shift_clk => shift_clk, shift_din => shift_din, shift => shift, shift_dout => shift_dout, control_reg_ce => control_reg_ce, bram_ce => bram_ce, bram_a => jtag_addr_int, din_load => din_load, din => bram_dout_int, bram_d => jtag_din_int, bram_we => jtag_we_int ); -- process (bram_ce, din_load, capture, bus_zero, control_reg_ce) begin if ( bram_ce = bus_zero ) then din_load <= capture and control_reg_ce; else din_load <= capture; end if; end process; -- Inst_control_registers: control_registers generic map( C_NUM_PICOBLAZE => C_NUM_PICOBLAZE, C_PICOBLAZE_INSTRUCTION_DATA_WIDTH => C_PICOBLAZE_INSTRUCTION_DATA_WIDTH, C_ADDR_WIDTH_0 => C_ADDR_WIDTH_0, C_ADDR_WIDTH_1 => C_ADDR_WIDTH_1, C_ADDR_WIDTH_2 => C_ADDR_WIDTH_2, C_ADDR_WIDTH_3 => C_ADDR_WIDTH_3, C_ADDR_WIDTH_4 => C_ADDR_WIDTH_4, C_ADDR_WIDTH_5 => C_ADDR_WIDTH_5, C_ADDR_WIDTH_6 => C_ADDR_WIDTH_6, C_ADDR_WIDTH_7 => C_ADDR_WIDTH_7, C_BRAM_MAX_ADDR_WIDTH => C_BRAM_MAX_ADDR_WIDTH) port map( en => bram_ce_valid, ce => control_reg_ce, wnr => jtag_we_int, clk => jtag_clk_int, a => jtag_addr_int(3 downto 0), din => control_din(C_NUM_PICOBLAZE-1 downto 0), dout => control_dout(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-8), picoblaze_reset => picoblaze_reset_int); -- control_dout (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-9 downto 0) <= (others => '0') when (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH > 8); -- -- Qualify the blockram CS signal with bscan select output jtag_en_int <= bram_ce when bram_ce_valid = '1' else (others => '0'); -- jtag_en_expanded(C_NUM_PICOBLAZE-1 downto 0) <= jtag_en_int; jtag_en_expanded(7 downto C_NUM_PICOBLAZE) <= (others => '0') when (C_NUM_PICOBLAZE < 8); -- bram_dout_int <= control_dout or jtag_dout_0_masked or jtag_dout_1_masked or jtag_dout_2_masked or jtag_dout_3_masked or jtag_dout_4_masked or jtag_dout_5_masked or jtag_dout_6_masked or jtag_dout_7_masked; -- control_din <= jtag_din_int; -- jtag_dout_0_masked <= jtag_dout_0 when jtag_en_expanded(0) = '1' else (others => '0'); jtag_dout_1_masked <= jtag_dout_1 when jtag_en_expanded(1) = '1' else (others => '0'); jtag_dout_2_masked <= jtag_dout_2 when jtag_en_expanded(2) = '1' else (others => '0'); jtag_dout_3_masked <= jtag_dout_3 when jtag_en_expanded(3) = '1' else (others => '0'); jtag_dout_4_masked <= jtag_dout_4 when jtag_en_expanded(4) = '1' else (others => '0'); jtag_dout_5_masked <= jtag_dout_5 when jtag_en_expanded(5) = '1' else (others => '0'); jtag_dout_6_masked <= jtag_dout_6 when jtag_en_expanded(6) = '1' else (others => '0'); jtag_dout_7_masked <= jtag_dout_7 when jtag_en_expanded(7) = '1' else (others => '0'); -- end generate jtag_loader_gen; -- -- jtag_en <= jtag_en_int; jtag_din <= jtag_din_int; jtag_addr <= jtag_addr_int; jtag_clk <= jtag_clk_int; jtag_we <= jtag_we_int; picoblaze_reset <= picoblaze_reset_int; -- end Behavioral; -- -- -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- entity control_registers is generic ( C_NUM_PICOBLAZE : integer := 1; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18; C_ADDR_WIDTH_0 : integer := 10; C_ADDR_WIDTH_1 : integer := 10; C_ADDR_WIDTH_2 : integer := 10; C_ADDR_WIDTH_3 : integer := 10; C_ADDR_WIDTH_4 : integer := 10; C_ADDR_WIDTH_5 : integer := 10; C_ADDR_WIDTH_6 : integer := 10; C_ADDR_WIDTH_7 : integer := 10; C_BRAM_MAX_ADDR_WIDTH : integer := 10 ); Port ( en : in std_logic; ce : in std_logic; wnr : in std_logic; clk : in std_logic; a : in std_logic_vector (3 downto 0); din : in std_logic_vector (C_NUM_PICOBLAZE-1 downto 0); dout : out std_logic_vector (7 downto 0); picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) ); end control_registers; -- architecture Behavioral of control_registers is -- signal version : std_logic_vector(7 downto 0) := "00000001"; signal picoblaze_reset_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); signal picoblaze_wait_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); signal dout_int : std_logic_vector(7 downto 0) := (others => '0'); signal num_picoblaze : std_logic_vector(2 downto 0); signal picoblaze_instruction_data_width : std_logic_vector(4 downto 0); -- begin -- num_picoblaze <= conv_std_logic_vector(C_NUM_PICOBLAZE-1,3); picoblaze_instruction_data_width <= conv_std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1,5); -- process(clk) begin if (clk'event and clk = '1') then if (en = '1') and (wnr = '0') and (ce = '1') then case (a) is when "0000" => -- 0 = version - returns (7 downto 4) illustrating number of PB -- and (3 downto 0) picoblaze instruction data width dout_int <= num_picoblaze & picoblaze_instruction_data_width; when "0001" => -- 1 = PicoBlaze 0 reset / status if (C_NUM_PICOBLAZE >= 1) then dout_int <= picoblaze_reset_int(0) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_0-1,5) ); else dout_int <= (others => '0'); end if; when "0010" => -- 2 = PicoBlaze 1 reset / status if (C_NUM_PICOBLAZE >= 2) then dout_int <= picoblaze_reset_int(1) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_1-1,5) ); else dout_int <= (others => '0'); end if; when "0011" => -- 3 = PicoBlaze 2 reset / status if (C_NUM_PICOBLAZE >= 3) then dout_int <= picoblaze_reset_int(2) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_2-1,5) ); else dout_int <= (others => '0'); end if; when "0100" => -- 4 = PicoBlaze 3 reset / status if (C_NUM_PICOBLAZE >= 4) then dout_int <= picoblaze_reset_int(3) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_3-1,5) ); else dout_int <= (others => '0'); end if; when "0101" => -- 5 = PicoBlaze 4 reset / status if (C_NUM_PICOBLAZE >= 5) then dout_int <= picoblaze_reset_int(4) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_4-1,5) ); else dout_int <= (others => '0'); end if; when "0110" => -- 6 = PicoBlaze 5 reset / status if (C_NUM_PICOBLAZE >= 6) then dout_int <= picoblaze_reset_int(5) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_5-1,5) ); else dout_int <= (others => '0'); end if; when "0111" => -- 7 = PicoBlaze 6 reset / status if (C_NUM_PICOBLAZE >= 7) then dout_int <= picoblaze_reset_int(6) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_6-1,5) ); else dout_int <= (others => '0'); end if; when "1000" => -- 8 = PicoBlaze 7 reset / status if (C_NUM_PICOBLAZE >= 8) then dout_int <= picoblaze_reset_int(7) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_7-1,5) ); else dout_int <= (others => '0'); end if; when "1111" => dout_int <= conv_std_logic_vector(C_BRAM_MAX_ADDR_WIDTH -1,8); when others => dout_int <= (others => '1'); end case; else dout_int <= (others => '0'); end if; end if; end process; -- dout <= dout_int; -- process(clk) begin if (clk'event and clk = '1') then if (en = '1') and (wnr = '1') and (ce = '1') then picoblaze_reset_int(C_NUM_PICOBLAZE-1 downto 0) <= din(C_NUM_PICOBLAZE-1 downto 0); end if; end if; end process; -- picoblaze_reset <= picoblaze_reset_int; -- end Behavioral; -- -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- entity jtag_shifter is generic ( C_NUM_PICOBLAZE : integer := 1; C_BRAM_MAX_ADDR_WIDTH : integer := 10; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18); Port ( shift_clk : in std_logic; shift_din : in std_logic; shift : in std_logic; shift_dout : out std_logic; control_reg_ce : out std_logic; bram_ce : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); bram_a : out std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0); din_load : in std_logic; din : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); bram_d : out std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); bram_we : out std_logic ); end jtag_shifter; -- architecture Behavioral of jtag_shifter is -- signal control_reg_ce_int : std_logic; signal bram_ce_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); signal bram_a_int : std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0) := (others => '0'); signal bram_d_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0'); signal bram_we_int : std_logic := '0'; -- begin -- control_reg_ce_shift : process (shift_clk) begin if shift_clk'event and shift_clk = '1' then if (shift = '1') then control_reg_ce_int <= shift_din; end if; end if; end process; control_reg_ce <= control_reg_ce_int; -- bram_ce_shift : process (shift_clk) begin if shift_clk'event and shift_clk='1' then if (shift = '1') then if(C_NUM_PICOBLAZE > 1) then for i in 0 to C_NUM_PICOBLAZE-2 loop bram_ce_int(i+1) <= bram_ce_int(i); end loop; end if; bram_ce_int(0) <= control_reg_ce_int; end if; end if; end process; -- bram_we_shift : process (shift_clk) begin if shift_clk'event and shift_clk='1' then if (shift = '1') then bram_we_int <= bram_ce_int(C_NUM_PICOBLAZE-1); end if; end if; end process; -- bram_a_shift : process (shift_clk) begin if shift_clk'event and shift_clk='1' then if (shift = '1') then for i in 0 to C_BRAM_MAX_ADDR_WIDTH-2 loop bram_a_int(i+1) <= bram_a_int(i); end loop; bram_a_int(0) <= bram_we_int; end if; end if; end process; -- bram_d_shift : process (shift_clk) begin if shift_clk'event and shift_clk='1' then if (din_load = '1') then bram_d_int <= din; elsif (shift = '1') then for i in 0 to C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-2 loop bram_d_int(i+1) <= bram_d_int(i); end loop; bram_d_int(0) <= bram_a_int(C_BRAM_MAX_ADDR_WIDTH-1); end if; end if; end process; -- bram_ce <= bram_ce_int; bram_we <= bram_we_int; bram_d <= bram_d_int; bram_a <= bram_a_int; shift_dout <= bram_d_int(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1); -- end Behavioral; -- -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library unisim; use unisim.vcomponents.all; -- entity bscan_logic is generic( C_JTAG_CHAIN : integer :=2; C_BUFFER_SHIFT_CLOCK : boolean := TRUE; C_FAMILY : string := "S6" ); Port ( shift_dout : in std_logic; shift_clk : out std_logic; bram_en : out std_logic; shift_din : out std_logic; bram_strobe : out std_logic; capture : out std_logic; shift : out std_logic ); end bscan_logic; -- architecture low_level_definition of bscan_logic is -- signal drck : std_logic; -- begin -- BSCAN_SPARTAN6_gen: if (C_FAMILY="S6") generate begin BSCAN_BLOCK_inst : BSCAN_SPARTAN6 generic map ( JTAG_CHAIN => C_JTAG_CHAIN) port map( CAPTURE => capture, DRCK => drck, RESET => open, RUNTEST => open, SEL => bram_en, SHIFT => shift, TCK => open, TDI => shift_din, TMS => open, UPDATE => bram_strobe, TDO => shift_dout); end generate BSCAN_SPARTAN6_gen; -- BSCAN_VIRTEX6_gen: if (C_FAMILY="V6") generate begin BSCAN_BLOCK_inst : BSCAN_VIRTEX6 generic map( JTAG_CHAIN => C_JTAG_CHAIN, DISABLE_JTAG => FALSE) port map( CAPTURE => capture, DRCK => drck, RESET => open, RUNTEST => open, SEL => bram_en, SHIFT => shift, TCK => open, TDI => shift_din, TMS => open, UPDATE => bram_strobe, TDO => shift_dout); end generate BSCAN_VIRTEX6_gen; -- BUFG_SHIFT_CLOCK_gen: if (C_BUFFER_SHIFT_CLOCK = TRUE) generate begin -- upload_clock: BUFG port map( I => drck, O => shift_clk); -- end generate BUFG_SHIFT_CLOCK_gen; -- NO_BUFG_SHIFT_CLOCK_gen: if (C_BUFFER_SHIFT_CLOCK = FALSE) generate begin shift_clk <= drck; end generate NO_BUFG_SHIFT_CLOCK_gen; -- end low_level_definition; -- -- ------------------------------------------------------------------------------------ -- -- END OF FILE {name}.vhd -- ------------------------------------------------------------------------------------
-- -- Knobs Galore - a free phase distortion synthesizer -- Copyright (C) 2015 Ilmo Euro -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; use work.common.all; entity voice_allocator_test is end entity; architecture voice_allocator_test_impl of voice_allocator_test is begin end architecture;
-- -- Knobs Galore - a free phase distortion synthesizer -- Copyright (C) 2015 Ilmo Euro -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; use work.common.all; entity voice_allocator_test is end entity; architecture voice_allocator_test_impl of voice_allocator_test is begin end architecture;
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_pkg.vhd -- Description: This package contains various constants and functions for -- AXI DMA operations. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library proc_common_v4_0; use proc_common_v4_0.proc_common_pkg.clog2; package axi_dma_pkg is ------------------------------------------------------------------------------- -- Function declarations ------------------------------------------------------------------------------- -- Find minimum required btt width function required_btt_width (dwidth : integer; burst_size : integer; btt_width : integer) return integer; -- Return correct hertz paramter value function hertz_prmtr_select(included : integer; lite_frequency : integer; sg_frequency : integer) return integer; -- Return SnF enable or disable function enable_snf (sf_enabled : integer; axi_data_width : integer; axis_tdata_width : integer) return integer; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- AXI Responce Values ------------------------------------------------------------------------------- constant OKAY_RESP : std_logic_vector(1 downto 0) := "00"; constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01"; constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10"; constant DECERR_RESP : std_logic_vector(1 downto 0) := "11"; constant MTBF_STAGES : integer := 4; constant C_FIFO_MTBF : integer := 4; ------------------------------------------------------------------------------- -- Misc Constants ------------------------------------------------------------------------------- --constant NUM_REG_TOTAL : integer := 18; --constant NUM_REG_TOTAL : integer := 23; constant NUM_REG_TOTAL : integer := 143; -- To accomodate S2MM registers --constant NUM_REG_PER_CHANNEL : integer := 6; constant NUM_REG_PER_CHANNEL : integer := 12; constant NUM_REG_PER_S2MM : integer := 120; --constant REG_MSB_ADDR_BIT : integer := clog2(NUM_REG_TOTAL)-1; constant CMD_BASE_WIDTH : integer := 40; constant BUFFER_LENGTH_WIDTH : integer := 23; -- Constants Used in Desc Updates constant DESC_STS_TYPE : std_logic := '1'; constant DESC_DATA_TYPE : std_logic := '0'; constant DESC_LAST : std_logic := '1'; constant DESC_NOT_LAST : std_logic := '0'; -- Interrupt Coalescing constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0'); constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001"; constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- AXI Lite AXI DMA Register Offsets ------------------------------------------------------------------------------- constant MM2S_DMACR_INDEX : integer := 0; constant MM2S_DMASR_INDEX : integer := 1; constant MM2S_CURDESC_LSB_INDEX : integer := 2; constant MM2S_CURDESC_MSB_INDEX : integer := 3; constant MM2S_TAILDESC_LSB_INDEX : integer := 4; constant MM2S_TAILDESC_MSB_INDEX : integer := 5; constant MM2S_SA_INDEX : integer := 6; constant RESERVED_1C_INDEX : integer := 7; constant RESERVED_20_INDEX : integer := 8; constant RESERVED_24_INDEX : integer := 9; constant MM2S_LENGTH_INDEX : integer := 10; constant RESERVED_2C_INDEX : integer := 11; constant S2MM_DMACR_INDEX : integer := 12; constant S2MM_DMASR_INDEX : integer := 13; constant S2MM_CURDESC_LSB_INDEX : integer := 14; constant S2MM_CURDESC_MSB_INDEX : integer := 15; constant S2MM_TAILDESC_LSB_INDEX : integer := 16; constant S2MM_TAILDESC_MSB_INDEX : integer := 17; constant S2MM_DA_INDEX : integer := 18; constant RESERVED_4C_INDEX : integer := 19; constant RESERVED_50_INDEX : integer := 20; constant RESERVED_54_INDEX : integer := 21; --constant S2MM_LENGTH_INDEX : integer := 22; constant S2MM_LENGTH_INDEX : integer := 142; constant MM2S_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000000000"; -- 0x00 constant MM2S_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000000100"; -- 0x04 constant MM2S_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000001000"; -- 0x08 constant MM2S_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000001100"; -- 0x0C constant MM2S_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000010000"; -- 0x10 constant MM2S_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000010100"; -- 0x14 constant MM2S_SA_OFFSET : std_logic_vector(9 downto 0) := "0000011000"; -- 0x18 constant RESERVED_1C_OFFSET : std_logic_vector(9 downto 0) := "0000011100"; -- 0x1C constant RESERVED_20_OFFSET : std_logic_vector(9 downto 0) := "0000100000"; -- 0x20 constant RESERVED_24_OFFSET : std_logic_vector(9 downto 0) := "0000100100"; -- 0x24 constant MM2S_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0000101000"; -- 0x28 -- Following was reserved, now is used for SG xCache and xUser constant SGCTL_OFFSET : std_logic_vector(9 downto 0) := "0000101100"; -- 0x2C constant S2MM_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000110000"; -- 0x30 constant S2MM_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000110100"; -- 0x34 constant S2MM_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000111000"; -- 0x38 constant S2MM_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000111100"; -- 0x3C constant S2MM_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001000000"; -- 0x40 constant S2MM_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001000100"; -- 0x44 constant S2MM_DA_OFFSET : std_logic_vector(9 downto 0) := "0001001000"; -- 0x48 --CR603034 constant RESERVED_4C_OFFSET : std_logic_vector(9 downto 0) := "0001001100"; -- 0x4C constant RESERVED_50_OFFSET : std_logic_vector(9 downto 0) := "0001010000"; -- 0x50 constant RESERVED_54_OFFSET : std_logic_vector(9 downto 0) := "0001010100"; -- 0x54 constant S2MM_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0001011000"; -- 0x58 -- New registers for S2MM channels constant S2MM_CURDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001110000"; -- 0x70 constant S2MM_CURDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001110100"; -- 0x74 constant S2MM_TAILDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001111000"; -- 0x78 constant S2MM_TAILDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001111100"; -- 0x7C constant S2MM_CURDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010010000"; -- 0x90 constant S2MM_CURDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010010100"; -- 0x94 constant S2MM_TAILDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010011000"; -- 0x98 constant S2MM_TAILDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010011100"; -- 0x9C constant S2MM_CURDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010110000"; -- 0xB0 constant S2MM_CURDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010110100"; -- 0xB4 constant S2MM_TAILDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010111000"; -- 0xB8 constant S2MM_TAILDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010111100"; -- 0xBC constant S2MM_CURDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011010000"; -- 0xD0 constant S2MM_CURDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011010100"; -- 0xD4 constant S2MM_TAILDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011011000"; -- 0xD8 constant S2MM_TAILDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011011100"; -- 0xDC constant S2MM_CURDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011110000"; -- 0xF0 constant S2MM_CURDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011110100"; -- 0xF4 constant S2MM_TAILDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011111000"; -- 0xF8 constant S2MM_TAILDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011111100"; -- 0xFC constant S2MM_CURDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100010000"; -- 0x110 constant S2MM_CURDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100010100"; -- 0x114 constant S2MM_TAILDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100011000"; -- 0x118 constant S2MM_TAILDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100011100"; -- 0x11C constant S2MM_CURDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100110000"; -- 0x130 constant S2MM_CURDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100110100"; -- 0x134 constant S2MM_TAILDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100111000"; -- 0x138 constant S2MM_TAILDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100111100"; -- 0x13C constant S2MM_CURDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101010000"; -- 0x150 constant S2MM_CURDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101010100"; -- 0x154 constant S2MM_TAILDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101011000"; -- 0x158 constant S2MM_TAILDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101011100"; -- 0x15C constant S2MM_CURDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101110000"; -- 0x170 constant S2MM_CURDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101110100"; -- 0x174 constant S2MM_TAILDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101111000"; -- 0x178 constant S2MM_TAILDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101111100"; -- 0x17C constant S2MM_CURDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110010000"; -- 0x190 constant S2MM_CURDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110010100"; -- 0x194 constant S2MM_TAILDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110011000"; -- 0x198 constant S2MM_TAILDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110011100"; -- 0x19C constant S2MM_CURDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110110000"; -- 0x1B0 constant S2MM_CURDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110110100"; -- 0x1B4 constant S2MM_TAILDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110111000"; -- 0x1B8 constant S2MM_TAILDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110111100"; -- 0x1BC constant S2MM_CURDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111010000"; -- 0x1D0 constant S2MM_CURDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111010100"; -- 0x1D4 constant S2MM_TAILDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111011000"; -- 0x1D8 constant S2MM_TAILDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111011100"; -- 0x1DC constant S2MM_CURDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111110000"; -- 0x1F0 constant S2MM_CURDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111110100"; -- 0x1F4 constant S2MM_TAILDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111111000"; -- 0x1F8 constant S2MM_TAILDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111111100"; -- 0x1FC constant S2MM_CURDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000010000"; -- 0x210 constant S2MM_CURDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000010100"; -- 0x214 constant S2MM_TAILDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000011000"; -- 0x218 constant S2MM_TAILDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000011100"; -- 0x21C constant S2MM_CURDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000110000"; -- 0x230 constant S2MM_CURDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000110100"; -- 0x234 constant S2MM_TAILDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000111000"; -- 0x238 constant S2MM_TAILDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000111100"; -- 0x23C ------------------------------------------------------------------------------- -- Register Bit Constants ------------------------------------------------------------------------------- -- DMACR constant DMACR_RS_BIT : integer := 0; constant DMACR_TAILPEN_BIT : integer := 1; constant DMACR_RESET_BIT : integer := 2; constant DMACR_KH_BIT : integer := 3; constant CYCLIC_BIT : integer := 4; --constant DMACR_RESERVED3_BIT : integer := 3; --constant DMACR_RESERVED4_BIT : integer := 4; constant DMACR_RESERVED5_BIT : integer := 5; constant DMACR_RESERVED6_BIT : integer := 6; constant DMACR_RESERVED7_BIT : integer := 7; constant DMACR_RESERVED8_BIT : integer := 8; constant DMACR_RESERVED9_BIT : integer := 9; constant DMACR_RESERVED10_BIT : integer := 10; constant DMACR_RESERVED11_BIT : integer := 11; constant DMACR_IOC_IRQEN_BIT : integer := 12; constant DMACR_DLY_IRQEN_BIT : integer := 13; constant DMACR_ERR_IRQEN_BIT : integer := 14; constant DMACR_RESERVED15_BIT : integer := 15; constant DMACR_IRQTHRESH_LSB_BIT : integer := 16; constant DMACR_IRQTHRESH_MSB_BIT : integer := 23; constant DMACR_IRQDELAY_LSB_BIT : integer := 24; constant DMACR_IRQDELAY_MSB_BIT : integer := 31; -- DMASR constant DMASR_HALTED_BIT : integer := 0; constant DMASR_IDLE_BIT : integer := 1; constant DMASR_CMPLT_BIT : integer := 2; constant DMASR_ERROR_BIT : integer := 3; constant DMASR_DMAINTERR_BIT : integer := 4; constant DMASR_DMASLVERR_BIT : integer := 5; constant DMASR_DMADECERR_BIT : integer := 6; constant DMASR_RESERVED7_BIT : integer := 7; constant DMASR_SGINTERR_BIT : integer := 8; constant DMASR_SGSLVERR_BIT : integer := 9; constant DMASR_SGDECERR_BIT : integer := 10; constant DMASR_RESERVED11_BIT : integer := 11; constant DMASR_IOCIRQ_BIT : integer := 12; constant DMASR_DLYIRQ_BIT : integer := 13; constant DMASR_ERRIRQ_BIT : integer := 14; constant DMASR_RESERVED15_BIT : integer := 15; constant DMASR_IRQTHRESH_LSB_BIT : integer := 16; constant DMASR_IRQTHRESH_MSB_BIT : integer := 23; constant DMASR_IRQDELAY_LSB_BIT : integer := 24; constant DMASR_IRQDELAY_MSB_BIT : integer := 31; -- CURDESC constant CURDESC_LOWER_MSB_BIT : integer := 31; constant CURDESC_LOWER_LSB_BIT : integer := 6; constant CURDESC_RESERVED_BIT5 : integer := 5; constant CURDESC_RESERVED_BIT4 : integer := 4; constant CURDESC_RESERVED_BIT3 : integer := 3; constant CURDESC_RESERVED_BIT2 : integer := 2; constant CURDESC_RESERVED_BIT1 : integer := 1; constant CURDESC_RESERVED_BIT0 : integer := 0; -- TAILDESC constant TAILDESC_LOWER_MSB_BIT : integer := 31; constant TAILDESC_LOWER_LSB_BIT : integer := 6; constant TAILDESC_RESERVED_BIT5 : integer := 5; constant TAILDESC_RESERVED_BIT4 : integer := 4; constant TAILDESC_RESERVED_BIT3 : integer := 3; constant TAILDESC_RESERVED_BIT2 : integer := 2; constant TAILDESC_RESERVED_BIT1 : integer := 1; constant TAILDESC_RESERVED_BIT0 : integer := 0; -- DataMover Command / Status Constants constant DATAMOVER_CMDDONE_BIT : integer := 7; constant DATAMOVER_SLVERR_BIT : integer := 6; constant DATAMOVER_DECERR_BIT : integer := 5; constant DATAMOVER_INTERR_BIT : integer := 4; constant DATAMOVER_TAGMSB_BIT : integer := 3; constant DATAMOVER_TAGLSB_BIT : integer := 0; -- Descriptor Control Bits constant DESC_BLENGTH_LSB_BIT : integer := 0; constant DESC_BLENGTH_MSB_BIT : integer := 22; constant DESC_RSVD23_BIT : integer := 23; constant DESC_RSVD24_BIT : integer := 24; constant DESC_RSVD25_BIT : integer := 25; constant DESC_EOF_BIT : integer := 26; constant DESC_SOF_BIT : integer := 27; constant DESC_RSVD28_BIT : integer := 28; constant DESC_RSVD29_BIT : integer := 29; constant DESC_RSVD30_BIT : integer := 30; constant DESC_IOC_BIT : integer := 31; -- Descriptor Status Bits constant DESC_STS_CMPLTD_BIT : integer := 31; constant DESC_STS_DECERR_BIT : integer := 30; constant DESC_STS_SLVERR_BIT : integer := 29; constant DESC_STS_INTERR_BIT : integer := 28; constant DESC_STS_RXSOF_BIT : integer := 27; constant DESC_STS_RXEOF_BIT : integer := 26; constant DESC_STS_RSVD25_BIT : integer := 25; constant DESC_STS_RSVD24_BIT : integer := 24; constant DESC_STS_RSVD23_BIT : integer := 23; constant DESC_STS_XFRDBYTS_MSB_BIT : integer := 22; constant DESC_STS_XFRDBYTS_LSB_BIT : integer := 0; -- DataMover Command / Status Constants constant DATAMOVER_STS_CMDDONE_BIT : integer := 7; constant DATAMOVER_STS_SLVERR_BIT : integer := 6; constant DATAMOVER_STS_DECERR_BIT : integer := 5; constant DATAMOVER_STS_INTERR_BIT : integer := 4; constant DATAMOVER_STS_TAGMSB_BIT : integer := 3; constant DATAMOVER_STS_TAGLSB_BIT : integer := 0; constant DATAMOVER_STS_TAGEOF_BIT : integer := 1; constant DATAMOVER_STS_TLAST_BIT : integer := 31; constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0; constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22; constant DATAMOVER_CMD_TYPE_BIT : integer := 23; constant DATAMOVER_CMD_DSALSB_BIT : integer := 24; constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29; constant DATAMOVER_CMD_EOF_BIT : integer := 30; constant DATAMOVER_CMD_DRR_BIT : integer := 31; constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32; -- Note: Bit offset require adding ADDR WIDTH to get to actual bit index constant DATAMOVER_CMD_ADDRMSB_BOFST: integer := 31; constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32; constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35; constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36; constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39; end axi_dma_pkg; ------------------------------------------------------------------------------- -- PACKAGE BODY ------------------------------------------------------------------------------- package body axi_dma_pkg is ------------------------------------------------------------------------------- -- Function to determine minimum bits required for BTT_SIZE field ------------------------------------------------------------------------------- function required_btt_width ( dwidth : integer; burst_size: integer; btt_width : integer) return integer is variable min_width : integer; begin min_width := clog2((dwidth/8)*burst_size)+1; if(min_width > btt_width)then return min_width; else return btt_width; end if; end function required_btt_width; ------------------------------------------------------------------------------- -- function to return Frequency Hertz parameter based on inclusion of sg engine ------------------------------------------------------------------------------- function hertz_prmtr_select(included : integer; lite_frequency : integer; sg_frequency : integer) return integer is begin -- 1 = Scatter Gather Included -- 0 = Scatter Gather Excluded if(included = 1)then return sg_frequency; else return lite_frequency; end if; end; ------------------------------------------------------------------------------- -- function to enable store and forward based on data width mismatch -- or directly enabled ------------------------------------------------------------------------------- function enable_snf (sf_enabled : integer; axi_data_width : integer; axis_tdata_width : integer) return integer is begin -- If store and forward enable or data widths do not -- match then return 1 to enable snf if( (sf_enabled = 1) or (axi_data_width /= axis_tdata_width))then return 1; else return 0; end if; end; end package body axi_dma_pkg;
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; -- -- Only a small fragment assigned and then whole signal assigned. -- ENTITY AssignToASliceOfReg3d IS PORT( clk : IN STD_LOGIC; data_in_addr : IN STD_LOGIC_VECTOR(1 DOWNTO 0); data_in_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0); data_in_mask : IN STD_LOGIC_VECTOR(7 DOWNTO 0); data_in_rd : OUT STD_LOGIC; data_in_vld : IN STD_LOGIC; data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); rst_n : IN STD_LOGIC ); END ENTITY; ARCHITECTURE rtl OF AssignToASliceOfReg3d IS SIGNAL r : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000000"; SIGNAL r_next : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL r_next_15downto8 : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL r_next_31downto16 : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL r_next_7downto0 : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN data_in_rd <= '1'; data_out <= r; assig_process_r: PROCESS(clk) BEGIN IF RISING_EDGE(clk) THEN IF rst_n = '0' THEN r <= X"00000000"; ELSE r <= r_next; END IF; END IF; END PROCESS; r_next <= r_next_31downto16 & r_next_15downto8 & r_next_7downto0; assig_process_r_next_15downto8: PROCESS(data_in_addr, data_in_data, r) BEGIN CASE data_in_addr IS WHEN "01" => r_next_15downto8 <= data_in_data; r_next_31downto16 <= r(31 DOWNTO 16); r_next_7downto0 <= r(7 DOWNTO 0); WHEN OTHERS => r_next_7downto0 <= X"7B"; r_next_15downto8 <= X"00"; r_next_31downto16 <= X"0000"; END CASE; END PROCESS; END ARCHITECTURE;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc36.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c04s03b01x01p02n01i00036ent IS END c04s03b01x01p02n01i00036ent; ARCHITECTURE c04s03b01x01p02n01i00036arch OF c04s03b01x01p02n01i00036ent IS constant a : positive := 1; -- No_failure_here constant b : natural := 1; -- No_failure_here constant a1 : positive := a + 1; -- No_failure_here constant a2 : positive := a + a; -- No_failure_here constant a3 : positive := a * (a/a + 1); -- No_failure_here constant b1 : natural := b + 1; -- No_failure_here constant b2 : natural := b + b; -- No_failure_here constant b3 : natural := b * (b/b + 1); -- No_failure_here constant b4 : natural := b - b; -- No_failure_here BEGIN TESTING: PROCESS BEGIN assert NOT( a = 1 and b = 1 and a1 = 2 and a2 = 2 and a3 = 2 and b1 = 2 and b2 = 2 and b3 = 2 and b4 = 0 ) report "***PASSED TEST: c04s03b01x01p02n01i00036" severity NOTE; assert ( a = 1 and b = 1 and a1 = 2 and a2 = 2 and a3 = 2 and b1 = 2 and b2 = 2 and b3 = 2 and b4 = 0 ) report "***FAILED TEST: c04s03b01x01p02n01i00036 - Constant declaration syntactic format test failed." severity ERROR; wait; END PROCESS TESTING; END c04s03b01x01p02n01i00036arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc36.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c04s03b01x01p02n01i00036ent IS END c04s03b01x01p02n01i00036ent; ARCHITECTURE c04s03b01x01p02n01i00036arch OF c04s03b01x01p02n01i00036ent IS constant a : positive := 1; -- No_failure_here constant b : natural := 1; -- No_failure_here constant a1 : positive := a + 1; -- No_failure_here constant a2 : positive := a + a; -- No_failure_here constant a3 : positive := a * (a/a + 1); -- No_failure_here constant b1 : natural := b + 1; -- No_failure_here constant b2 : natural := b + b; -- No_failure_here constant b3 : natural := b * (b/b + 1); -- No_failure_here constant b4 : natural := b - b; -- No_failure_here BEGIN TESTING: PROCESS BEGIN assert NOT( a = 1 and b = 1 and a1 = 2 and a2 = 2 and a3 = 2 and b1 = 2 and b2 = 2 and b3 = 2 and b4 = 0 ) report "***PASSED TEST: c04s03b01x01p02n01i00036" severity NOTE; assert ( a = 1 and b = 1 and a1 = 2 and a2 = 2 and a3 = 2 and b1 = 2 and b2 = 2 and b3 = 2 and b4 = 0 ) report "***FAILED TEST: c04s03b01x01p02n01i00036 - Constant declaration syntactic format test failed." severity ERROR; wait; END PROCESS TESTING; END c04s03b01x01p02n01i00036arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc36.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c04s03b01x01p02n01i00036ent IS END c04s03b01x01p02n01i00036ent; ARCHITECTURE c04s03b01x01p02n01i00036arch OF c04s03b01x01p02n01i00036ent IS constant a : positive := 1; -- No_failure_here constant b : natural := 1; -- No_failure_here constant a1 : positive := a + 1; -- No_failure_here constant a2 : positive := a + a; -- No_failure_here constant a3 : positive := a * (a/a + 1); -- No_failure_here constant b1 : natural := b + 1; -- No_failure_here constant b2 : natural := b + b; -- No_failure_here constant b3 : natural := b * (b/b + 1); -- No_failure_here constant b4 : natural := b - b; -- No_failure_here BEGIN TESTING: PROCESS BEGIN assert NOT( a = 1 and b = 1 and a1 = 2 and a2 = 2 and a3 = 2 and b1 = 2 and b2 = 2 and b3 = 2 and b4 = 0 ) report "***PASSED TEST: c04s03b01x01p02n01i00036" severity NOTE; assert ( a = 1 and b = 1 and a1 = 2 and a2 = 2 and a3 = 2 and b1 = 2 and b2 = 2 and b3 = 2 and b4 = 0 ) report "***FAILED TEST: c04s03b01x01p02n01i00036 - Constant declaration syntactic format test failed." severity ERROR; wait; END PROCESS TESTING; END c04s03b01x01p02n01i00036arch;
-------------------------------------------------------------------------------- -- Company: <Mehatronika> -- Author: <Aleksandr Gudilko> -- Email: gudilkoalex@gmail.com -- -- File: Position_INT_to_BCD_decoder.vhd -- File history: -- <2.0>: <02/04/2015>: <Updates integer and fractional position automatically. Send codes to pendant> -- <Revision number>: <Date>: <Comments> -- <Revision number>: <Date>: <Comments> -- -- Description: -- -- <receive data in integer form and form BCD code for UART transmitter> -- BCD data format is commonly used to show data on LCD or 7-segment displays -- -- Targeted device: <Family::ProASIC3> <Die::M1A3P400> <Package::208 PQFP> -- -- -------------------------------------------------------------------------------- library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity Position_INT_to_BCD_decoder is GENERIC( d_width : INTEGER := 24; -- data width counter_width : INTEGER := 11 -- position update frequency ); -- 01bit counter -> 51 us period clock 19,5 kHz -- 02bit counter -> 102 us period clock 9,75 kHz -- 03bit counter -> 204 us period clock 4,8 kHz -- 04bit counter -> 409 us period clock 2,4 kHz -- 05bit counter -> 820 us period clock 1,2 kHz -- 06bit counter -> 1.6 ms period clock 610 Hz -- 07bit counter -> 3.2 ms period clock 305 Hz -- 08bit counter -> 6.5 ms period clock 152 Hz -- 09bit counter -> 13 ms period clock 76 Hz -- 10bit counter -> 26 ms period clock 38 Hz -- 11bit counter -> 52 ms period clock 19 Hz -- 12bit counter -> 104 ms period clock 9,5 Hz -- 13bit counter -> 209 ms period clock 4,75 Hz -- 14bit counter -> 419 ms period clock 2,35 Hz -- 15bit counter -> 838 ms period clock 1,2 Hz -- 16bit counter -> 1,67 s period clock 0,6 Hz port ( RESET_N : in std_logic; -- RESET. Active low. SCLK_IN : in std_logic; -- External SCLK 50 Mhz SCLK_LF_IN : in std_logic; -- External SCLK 10 Mhz SCLK_KHz_IN : in std_logic; -- External SCLK xx hz Latch_data_IN : in std_logic; -- latch new position data input Data_ready_IN : in std_logic; -- from PMAC_block. if '1' - data is ready Pos_update_request : in std_logic; -- from PMAC_block. if '1' - send new position Update_freq : in std_logic; -- from PMAC_block. X_Pos_Int_in : in std_logic_vector(d_width-1 downto 0); -- X position (int) X_pos_Fract_in : in std_logic_vector(d_width-1 downto 0); -- X position (fract) Y_Pos_Int_in : in std_logic_vector(d_width-1 downto 0); -- Y position (int) Y_pos_Fract_in : in std_logic_vector(d_width-1 downto 0); -- Y position (fract) Z_Pos_Int_in : in std_logic_vector(d_width-1 downto 0); -- Z position (int) Z_pos_Fract_in : in std_logic_vector(d_width-1 downto 0); -- Z position (fract) A4_Pos_Int_in : in std_logic_vector(d_width-1 downto 0); -- 4 position (int) A4_pos_Fract_in : in std_logic_vector(d_width-1 downto 0); -- 4 position (fract) active_axis : in std_logic_vector(3 downto 0); -- shows active axis UART_Send_Data : out std_logic; -- if '1' - send position via UART Data_ready_out : out std_logic; -- decoding finished Position_Tx_gate : out std_logic; -- gate for UART Tx registers Position_to_decode : out std_logic_vector(13 downto 0); -- position to be decoded Pos_Int_dig12_out : out std_logic_vector(7 downto 0); -- position int digits 1 & 2 Pos_Int_dig34_out : out std_logic_vector(7 downto 0); -- position int digits 3 & 4 Pos_Int_dig56_out : out std_logic_vector(7 downto 0); -- position int digits 5 & 6 Pos_Fract_dig12_out : out std_logic_vector(7 downto 0); -- position fract digits 1 & 2 Pos_Fract_dig34_out : out std_logic_vector(7 downto 0) -- position fract digits 3 & 4 ); end Position_INT_to_BCD_decoder; architecture a_Position of Position_INT_to_BCD_decoder is -- signal, component etc. declarations signal Latch_data: std_logic; -- combined inputs to decide when to latch new position data signal New_data_available : std_logic; -- if '1' - current data /= previous data signal update_count: std_logic; -- time-based position update (long signal) signal Latch_data_timer_imp: std_logic; -- time-based position update (impulse) signal clk_divider : std_logic_vector(counter_width-1 downto 0); -- clock divider signal Data_ready_out_R: std_logic; -- data is ready signal Position_Tx_gate_R: std_logic; -- latch BCD position data in UART Tx registers signal UART_Send_Data_R: std_logic; -- will be used to generate UART write impulse -- current position signal Pos_Sign_code_R: std_logic_vector(3 downto 0); -- int position sign signal Pos_Int_dig12_R : std_logic_vector(7 downto 0); -- int position digits 1&2 (sign) signal Pos_Int_dig34_R : std_logic_vector(7 downto 0); -- int position digits 3&4 signal Pos_Int_dig5_R : std_logic_vector(3 downto 0); -- int position digits 5 signal Pos_Int_dig6_R : std_logic_vector(3 downto 0); -- int position digits 6 signal Pos_Fract_dig12_R : std_logic_vector(7 downto 0); -- fract position digits 1&2 signal Pos_Fract_dig34_R : std_logic_vector(7 downto 0); -- fract position digits 3&4 --previous position signal Prev_Pos_Int_dig12_R : std_logic_vector(7 downto 0); -- int position digits 1&2 signal Prev_Pos_Int_dig34_R : std_logic_vector(7 downto 0); -- int position digits 3&4 signal Prev_Pos_Int_dig5_R : std_logic_vector(3 downto 0); -- int position digits 5 signal Prev_Pos_Fract_dig12_R : std_logic_vector(7 downto 0); -- fract position digits 1&2 signal Prev_Pos_Fract_dig34_R : std_logic_vector(7 downto 0); -- fract position digits 3&4 -- comparison results signal Comp_Pos_Int_dig12 : std_logic; -- int position digits 1 signal Comp_Pos_Int_dig34 : std_logic; -- int position digits 3&4 signal Comp_Pos_Int_dig5 : std_logic; -- int position digits 5 signal Comp_Pos_Fract_dig12 : std_logic; -- fract position digits 1&2 signal Comp_Pos_Fract_dig34 : std_logic; -- fract position digits 3&4 signal X_Pos_Int_R : std_logic_vector(d_width-1 downto 0); -- X position (int) signal X_pos_Fract_R : std_logic_vector(d_width-1 downto 0); -- X position (fract) signal Y_Pos_Int_R : std_logic_vector(d_width-1 downto 0); -- Y position (int) signal Y_pos_Fract_R : std_logic_vector(d_width-1 downto 0); -- Y position (fract) signal Z_Pos_Int_R : std_logic_vector(d_width-1 downto 0); -- Z position (int) signal Z_pos_Fract_R : std_logic_vector(d_width-1 downto 0); -- Z position (fract) signal A4_Pos_Int_R : std_logic_vector(d_width-1 downto 0); -- 4 position (int) signal A4_pos_Fract_R :std_logic_vector(d_width-1 downto 0); -- 4 position (fract) signal Position_sign_R : std_logic; -- sign of position ( 0 => "+", 1 => "-") signal Position_int_R : std_logic_vector(13 downto 0); -- input code for 5 digit BCD decoder (int part of position) signal Position_fract_R : std_logic_vector(13 downto 0); -- input code for 4 digit BCD decoder (fract part of position) --signal pos_tenthousands_R : std_logic_vector(3 downto 0); -- BCD code for "thousands" digit (int part) signal pos_thousands_R : std_logic_vector(3 downto 0); -- BCD code for "thousands" digit (int part) signal pos_hundreds_R : std_logic_vector(3 downto 0); -- BCD code for "hundreds" digit (int part) signal pos_tens_R : std_logic_vector(3 downto 0); -- BCD code for "tens" digit (int part) signal pos_ones_R : std_logic_vector(3 downto 0); -- BCD code for "ones" digit (int part) signal pos_fr_thousands_R : std_logic_vector(3 downto 0); -- BCD code for "thousands" digit (fract part) signal pos_fr_hundreds_R : std_logic_vector(3 downto 0); -- BCD code for "hundreds" digit (fract part) signal pos_fr_tens_R : std_logic_vector(3 downto 0); -- BCD code for "tens" digit (fract part) signal pos_fr_ones_R : std_logic_vector(3 downto 0); -- BCD code for "ones" digit (fract part) component impulse_gen_N_2cycle port ( RESET_N :in std_logic; -- reset IN_SIGNAL :in std_logic; -- input signal IN_CLK :in std_logic; -- input clock signal OUT_SIGNAL_P :out std_logic; -- output impluse Active High OUT_SIGNAL_N :out std_logic -- output impluse Active Low ); end component; component bcd_4dig Port ( number : in std_logic_vector (13 downto 0); thousands : out std_logic_vector (3 downto 0); hundreds : out std_logic_vector (3 downto 0); tens : out std_logic_vector (3 downto 0); ones : out std_logic_vector (3 downto 0) ); end component; component InEquality_comparator_8bit is port( DataA : in std_logic_vector(7 downto 0); DataB : in std_logic_vector(7 downto 0); ANEB : out std_logic ); end component; component InEquality_comparator_4bit is port( DataA : in std_logic_vector(3 downto 0); DataB : in std_logic_vector(3 downto 0); ANEB : out std_logic ); end component; begin -- wiring outputs; Data_ready_out <= Data_ready_out_R; Position_Tx_gate <= Position_Tx_gate_R; UART_Send_Data <= UART_Send_Data_R; Pos_Int_dig12_out <= Pos_Int_dig12_R; Pos_Int_dig34_out <= Pos_Int_dig34_R; Pos_Int_dig56_out(7 downto 4) <= Pos_Int_dig5_R; Pos_Int_dig56_out(3 downto 0) <= Pos_Int_dig6_R; Pos_Fract_dig12_out <= Pos_Fract_dig12_R; Pos_Fract_dig34_out <= Pos_Fract_dig34_R; Position_to_decode <= Position_int_R; -- assigning signals Latch_data <= Latch_data_IN or Latch_data_timer_imp; -- may insert additional signals to start position decoding and transmission New_data_available <= Comp_Pos_Int_dig12 or Comp_Pos_Int_dig34 or Comp_Pos_Int_dig5 or Comp_Pos_Fract_dig12 or Comp_Pos_Fract_dig34; \UART_Tx_Gate_impulse_gen1\ : impulse_gen_N_2cycle -- generate signal to latch data in UART Tx registers (2 clk width) port map(IN_SIGNAL => Data_ready_out_R, IN_CLK => SCLK_LF_IN, RESET_N => RESET_N , OUT_SIGNAL_N => open, OUT_SIGNAL_P => Position_Tx_gate_R); \Timer_pos_update_impulse_gen\ : impulse_gen_N_2cycle -- generate signal to update position (2 clk width) port map(IN_SIGNAL => update_count, IN_CLK => SCLK_Khz_IN, RESET_N => RESET_N , OUT_SIGNAL_N => open, OUT_SIGNAL_P => Latch_data_timer_imp); \bcd_decoder_4digit_int\ : bcd_4dig -- 4-digit BCD decoder (integer part of position) port map(number => Position_int_R(13 downto 0), thousands => pos_thousands_R, hundreds => pos_hundreds_R, tens => pos_tens_R , ones => pos_ones_R); \bcd_decoder_4digit_fract\ : bcd_4dig -- 4-digit BCD decoder (fractional part of position) port map(number => Position_fract_R, thousands => pos_fr_thousands_R, hundreds => pos_fr_hundreds_R, tens => pos_fr_tens_R , ones => pos_fr_ones_R); \comparator1\ : InEquality_comparator_8bit -- compare previous and current position data (int_digits 1&2) port map(DataA => Pos_Int_dig12_R, DataB => prev_Pos_Int_dig12_R, ANEB => Comp_Pos_Int_dig12); \comparator2\ : InEquality_comparator_8bit -- compare previous and current position data (int_digits 3&4) port map(DataA => Pos_Int_dig34_R, DataB => prev_Pos_Int_dig34_R, ANEB => Comp_Pos_Int_dig34); \comparator3\ : InEquality_comparator_4bit -- compare previous and current position data (int_digits 5&6) port map(DataA => Pos_Int_dig5_R, DataB => prev_Pos_Int_dig5_R, ANEB => Comp_Pos_Int_dig5); \comparator4\ : InEquality_comparator_8bit -- compare previous and current position data (fract_digits 1&2) port map(DataA => Pos_Fract_dig12_R, DataB => prev_Pos_Fract_dig12_R, ANEB => Comp_Pos_Fract_dig12); \comparator5\ : InEquality_comparator_8bit -- compare previous and current position data (fract_digits 1&2) port map(DataA => Pos_Fract_dig34_R, DataB => prev_Pos_Fract_dig34_R, ANEB => Comp_Pos_Fract_dig34); Data_latch: process( RESET_N, SCLK_LF_IN) begin if ( RESET_N ='0')then X_Pos_Int_R <= (OTHERS => '0'); X_pos_Fract_R <= (OTHERS => '0'); Y_Pos_Int_R <= (OTHERS => '0'); Y_pos_Fract_R <= (OTHERS => '0'); Z_Pos_Int_R <= (OTHERS => '0'); Z_pos_Fract_R <= (OTHERS => '0'); A4_Pos_Int_R <= (OTHERS => '0'); A4_pos_Fract_R <= (OTHERS => '0'); Data_ready_out_R <= '1'; -- set flag to prevent false trigger after reset elsif (falling_edge(SCLK_LF_IN)) then if (Data_ready_IN = '1' and Latch_data = '1') then -- new axis is selected or update timer expired X_Pos_Int_R <= X_Pos_Int_in; X_pos_Fract_R <= X_Pos_fract_in; Y_Pos_Int_R <= Y_Pos_Int_in; Y_pos_Fract_R <= Y_Pos_fract_in; Z_Pos_Int_R <= Z_Pos_Int_in; Z_pos_Fract_R <= Z_Pos_fract_in; A4_Pos_Int_R <= A4_Pos_Int_in; A4_pos_Fract_R <= A4_Pos_fract_in; Data_ready_out_R <= '0'; -- clear flag else -- if Latch_data_IN = '0' Data_ready_out_R <= '1'; --DELAYED FOR 1/2 CLK LF CYCLE end if; end if; end process Data_latch; DATA_MUX: process( RESET_N, SCLK_IN) begin if ( RESET_N ='0')then Position_sign_R <= '0'; Position_int_R <= (OTHERS => '0'); Position_fract_R <= (OTHERS => '0'); Pos_Int_dig12_R <= x"C0"; -- display: +0 Pos_Int_dig34_R <= (OTHERS => '0'); Pos_Int_dig5_R <= (OTHERS => '0'); Pos_Int_dig6_R <= x"A"; Pos_Fract_dig12_R <= (OTHERS => '0'); Pos_Fract_dig34_R <= (OTHERS => '0'); elsif (rising_edge(SCLK_IN)) then if (Latch_data = '0' and Data_ready_out_R = '0') then -- duration only 1/2 CLK LF cycle case (active_axis) is when "1000" => -- Active axis: X Position_int_R <= X_Pos_Int_R (13 downto 0); Position_fract_R <= X_Pos_Fract_R (13 downto 0); Position_sign_R <= X_Pos_Int_R (16); when "0100" => -- Active axis: Y Position_int_R <= Y_Pos_Int_R (13 downto 0); Position_fract_R <= Y_Pos_Fract_R (13 downto 0); Position_sign_R <= Y_Pos_Int_R (16); when "0010" => -- Active axis: Z Position_int_R <= Z_Pos_Int_R (13 downto 0); Position_fract_R <= Z_Pos_Fract_R (13 downto 0); Position_sign_R <= Z_Pos_Int_R (16); when "0001" => -- Active axis: 4 Position_int_R <= A4_Pos_Int_R (13 downto 0); Position_fract_R <= A4_Pos_Fract_R (13 downto 0); Position_sign_R <= A4_Pos_Int_R (16); when others => Position_int_R <= (OTHERS => '0'); Position_fract_R <= (OTHERS => '0'); Position_sign_R <= '0'; end case; -- push integer part of position to outputs Pos_Int_dig12_R <= Pos_Sign_code_R & pos_thousands_R; Pos_Int_dig34_R <= pos_hundreds_R & pos_tens_R; Pos_Int_dig5_R <= pos_ones_R; Pos_Int_dig6_R <= x"A"; -- push fractional part of position to outputs Pos_Fract_dig12_R <= pos_fr_thousands_R & pos_fr_hundreds_R; Pos_Fract_dig34_R <= pos_fr_tens_R & pos_fr_ones_R; else -- latching new data when Latch_data_IN = '1'; transmitting new UART data when Data_ready_out_R = '1' null; end if; end if; end process DATA_MUX; Sign_decoder: process( RESET_N, Position_sign_R) begin if ( RESET_N ='0')then Pos_Sign_code_R <= x"C"; -- -> "+" elsif (Position_sign_R = '0') then -- if '0' -> "+" Pos_Sign_code_R <= x"C"; else -- if '1' -> "-" Pos_Sign_code_R <= x"B"; end if; end process Sign_decoder; clock_divider: process( RESET_N, SCLK_LF_IN) begin if ( RESET_N ='0')then clk_divider <= (OTHERS => '0'); elsif (rising_edge(SCLK_KHz_IN)) then clk_divider <= clk_divider + 1; end if; end process clock_divider; update_count <= clk_divider(counter_width-1); update_timer: process( RESET_N, update_count) begin if ( RESET_N ='0')then UART_Send_Data_R <= '0'; -- active HIGH. "Sent new position data" is inactive elsif (falling_edge(update_count)) then -- delay between rising and falling edge is used to process new data if (New_data_available = '1') then -- new data is available UART_Send_Data_R <= '1'; -- set flag to send data via UART prev_Pos_Int_dig12_R <= Pos_Int_dig12_R; prev_Pos_Int_dig34_R <= Pos_Int_dig34_R; prev_Pos_Int_dig5_R <= Pos_Int_dig5_R; prev_Pos_Fract_dig12_R <= Pos_Fract_dig12_R; prev_Pos_Fract_dig34_R <= Pos_Fract_dig34_R; else UART_Send_Data_R <= '0'; -- clear flag end if; end if; end process update_timer; end a_Position;
--------------------------------------------------------------------- -- ____ _____ _______ -- / __ \ / ____|__ __| -- | | | | (___ | | -- | | | |\___ \ | | -- | |__| |____) | | | -- \____/|_____/ |_| -- -- O S T S C H W E I Z E R F A C H H O C H S C H U L E -- Campus Buchs - Werdenbergstrasse 4 - CH-9471 Buchs -- Tel. +41 (0)81 755 33 11 Fax +41 (0)81 756 54 34 --------------------------------------------------------------------- -- Title : TX_UART.vhd -- Project : FLINK -- Description : VHDL UART design --------------------------------------------------------------------- -- Copyright(C) 2020 : Fachhochschule Ostschweiz -- All rights reserved. --------------------------------------------------------------------- -- History -- 14.10.2020 ARAL : Initial version --------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; PACKAGE TX_UART_pkg IS COMPONENT TX_UART IS PORT ( isl_4x_uart_clk : IN STD_LOGIC; isl_reset : IN STD_LOGIC; isl_data_valid : IN STD_LOGIC; islv8_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0); osl_serial_data : OUT STD_LOGIC; osl_busy : OUT STD_LOGIC ); END COMPONENT TX_UART; END PACKAGE TX_UART_pkg; ---------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; ENTITY TX_UART IS PORT ( isl_4x_uart_clk : IN STD_LOGIC; isl_reset : IN STD_LOGIC; isl_data_valid : IN STD_LOGIC; islv8_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0); osl_serial_data : OUT STD_LOGIC; osl_busy : OUT STD_LOGIC ); END ENTITY TX_UART; ---------------------------------------------------------------------- ARCHITECTURE rtl of TX_UART IS TYPE t_tx_fsm_state IS (IDLE, START, D0, D1, D2, D3, D4, D5, D6, D7, D8, STOP1, STOP2); TYPE t_registers IS RECORD fsm_state : t_tx_fsm_state; usig2_clk_divider : UNSIGNED(1 DOWNTO 0); slv8_next_data : STD_LOGIC_VECTOR(7 DOWNTO 0); sl_next_data_ready : STD_LOGIC; slv8_data : STD_LOGIC_VECTOR(7 DOWNTO 0); sl_tx_data : STD_LOGIC; sl_busy : STD_LOGIC; END RECORD t_registers; SIGNAL r, r_next : t_registers := ( fsm_state => IDLE, usig2_clk_divider => (OTHERS => '0'), slv8_next_data => (OTHERS => '0'), sl_next_data_ready => '0', slv8_data => (OTHERS => '0'), sl_tx_data => '1', sl_busy => '0' ); BEGIN -- Clock is divided by 4 to be able to use the same clock as RX_UART -- Data is registered with "isl_data_valid", which will start transmission -- Format is 1 Start bit, 8 data bits, 2 stop bits, no parity --## Combinatorial Priocess --## --########################## comb_proc : PROCESS (r, isl_reset, isl_data_valid, islv8_data) VARIABLE v : t_registers; BEGIN v := r; -- Keep signals stable -- Capture data, when it is available IF isl_data_valid = '1' THEN v.slv8_next_data := islv8_data; v.sl_next_data_ready := '1'; END IF; v.usig2_clk_divider := r.usig2_clk_divider + 1; -- Modulo 4 counter IF r.usig2_clk_divider = "00" THEN -- Only take action every 4th cycle CASE r.fsm_state IS WHEN IDLE => -- Wait for Data valid signal v.sl_tx_data := '1'; v.sl_busy := '0'; IF (r.sl_next_data_ready = '1') THEN v.sl_next_data_ready := '0'; v.slv8_data := r.slv8_next_data; v.fsm_state := START; v.sl_busy := '1'; END IF; WHEN START => v.sl_tx_data := '0'; -- Send Start bit v.fsm_state := D0; WHEN D0 => v.sl_tx_data := r.slv8_data(0); v.slv8_data(7 DOWNTO 0) := '0' & r.slv8_data(7 DOWNTO 1); v.fsm_state := D1; WHEN D1 => v.sl_tx_data := r.slv8_data(0); v.slv8_data(7 DOWNTO 0) := '0' & r.slv8_data(7 DOWNTO 1); v.fsm_state := D2; WHEN D2 => v.sl_tx_data := r.slv8_data(0); v.slv8_data(7 DOWNTO 0) := '0' & r.slv8_data(7 DOWNTO 1); v.fsm_state := D3; WHEN D3 => v.sl_tx_data := r.slv8_data(0); v.slv8_data(7 DOWNTO 0) := '0' & r.slv8_data(7 DOWNTO 1); v.fsm_state := D4; WHEN D4 => v.sl_tx_data := r.slv8_data(0); v.slv8_data(7 DOWNTO 0) := '0' & r.slv8_data(7 DOWNTO 1); v.fsm_state := D5; WHEN D5 => v.sl_tx_data := r.slv8_data(0); v.slv8_data(7 DOWNTO 0) := '0' & r.slv8_data(7 DOWNTO 1); v.fsm_state := D6; WHEN D6 => v.sl_tx_data := r.slv8_data(0); v.slv8_data(7 DOWNTO 0) := '0' & r.slv8_data(7 DOWNTO 1); v.fsm_state := D7; WHEN D7 => v.sl_tx_data := r.slv8_data(0); v.slv8_data(7 DOWNTO 0) := '0' & r.slv8_data(7 DOWNTO 1); v.fsm_state := STOP1; WHEN STOP1 => v.sl_tx_data := '1'; -- Send Stop Bit v.slv8_data(7 DOWNTO 0) := '0' & r.slv8_data(7 DOWNTO 1); v.fsm_state := STOP2; WHEN STOP2 => v.sl_tx_data := '1'; -- Send Stop Bit v.slv8_data(7 DOWNTO 0) := '0' & r.slv8_data(7 DOWNTO 1); v.sl_busy := '0'; v.fsm_state := IDLE; WHEN OTHERS => v.fsm_state := IDLE; END CASE; END IF; -- Only take action every 4th clock cycle --## Reset Logic IF isl_reset = '1' THEN v.fsm_state := IDLE; v.usig2_clk_divider := (OTHERS => '0'); v.slv8_data := (OTHERS => '0'); v.sl_tx_data := '1'; v.sl_busy := '0'; END IF; r_next <= v; END PROCESS comb_proc; --## Registered Priocess --## --####################### reg_proc : PROCESS (isl_4x_uart_clk) BEGIN IF rising_edge(isl_4x_uart_clk) THEN r <= r_next; END IF; END PROCESS reg_proc; --## Output Assignments --## --###################### osl_serial_data <= r.sl_tx_data; osl_busy <= r.sl_busy; END ARCHITECTURE rtl;
------------------------------------------------------------------------------- -- Triple Buffer Control Logic -- -- Copyright (C) 2010 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact office@br-automation.com -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- -- This logic implements the virtual triple buffers, by selecting the -- appropriate address offset. The output address offset has to be added to the -- input address. The trigger signal switches to the next available buffer. -- The switch mechanism is implemented in the PCP's clock domain. Thus the -- switch over on the PCP side is performed without delay. An AP switch over -- crosses from AP to PCP clock domain (2x pcpClk) and back from PCP to AP -- (2x apClk). ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY tripleVBufLogic IS GENERIC( genOnePdiClkDomain_g : boolean := false; --base address of virtual buffers in DPR iVirtualBufferBase_g : INTEGER := 0; --size of one virtual buffer in DPR (must be aligned!!!) iVirtualBufferSize_g : INTEGER := 1024; --out address width iOutAddrWidth_g : INTEGER := 13; --in address width iInAddrWidth_g : INTEGER := 11; --ap is producer bApIsProducer : BOOLEAN := FALSE ); PORT ( pcpClk : IN STD_LOGIC; pcpReset : IN STD_LOGIC; pcpTrigger : IN STD_LOGIC; --trigger virtual buffer change --pcpInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0); pcpOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0); pcpOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer (one-hot coded) apClk : IN STD_LOGIC; apReset : IN STD_LOGIC; apTrigger : IN STD_LOGIC; --trigger virtual buffer change --apInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0); apOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0); apOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) --selected virtual buffer (one-hot coded) ); END ENTITY tripleVBufLogic; ARCHITECTURE rtl OF tripleVBufLogic IS --constants ---virtual buffer base address CONSTANT iVirtualBufferBase0_c : INTEGER := 0*iVirtualBufferSize_g + iVirtualBufferBase_g; CONSTANT iVirtualBufferBase1_c : INTEGER := 1*iVirtualBufferSize_g + iVirtualBufferBase_g; CONSTANT iVirtualBufferBase2_c : INTEGER := 2*iVirtualBufferSize_g + iVirtualBufferBase_g; ---one hot code constant cOneHotVirtualBuffer0 : std_logic_vector(2 downto 0) := "001"; constant cOneHotVirtualBuffer1 : std_logic_vector(2 downto 0) := "010"; constant cOneHotVirtualBuffer2 : std_logic_vector(2 downto 0) := "100"; ---triple buffer mechanism ----initial states CONSTANT initialValid_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer0; CONSTANT initialLocked_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer1; CONSTANT initialCurrent_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer2; --signals ---PCP and AP selected virtual buffer SIGNAL pcpSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by producer SIGNAL apSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by consumer SIGNAL lockedVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --locked virtual buffer in producer clk domain BEGIN pcpOutSelVBuf <= pcpSelVBuf_s; apOutSelVBuf <= apSelVBuf_s; theAddrCalcer : BLOCK --depending on the selected virtual buffer (???SelVBuf_s), the output address is calculated (???OutAddr) -- ???SelVBuf_s | ???OutAddr -- ------------------------- -- "001" | ???InAddr + iVirtualBufferBase0_c -- "010" | ???InAddr + iVirtualBufferBase1_c -- "100" | ???InAddr + iVirtualBufferBase2_c SIGNAL pcpAddrOffset, apAddrOffset: STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0); --SIGNAL pcpSum, apSum : STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0); BEGIN --select address offset pcpAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer0 ELSE CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer1 ELSE CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer2 ELSE (OTHERS => '0'); pcpOutAddrOff <= pcpAddrOffset; --calculate address for dpr, leading zero is a sign! --pcpSum <= ('0' & conv_std_logic_vector(conv_integer(pcpInAddr), iOutAddrWidth_g-1)) + ('0' & pcpAddrOffset); --pcpOutAddr <= pcpSum(pcpOutAddr'RANGE); --select address offset apAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer0 ELSE CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer1 ELSE CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer2 ELSE (OTHERS => '0'); apOutAddrOff <= apAddrOffset; --calculate address for dpr, leading zero is a sign! --apSum <= ('0' & conv_std_logic_vector(conv_integer(apInAddr), iOutAddrWidth_g-1)) + ('0' & apAddrOffset); --apOutAddr <= apSum(apOutAddr'RANGE); END BLOCK theAddrCalcer; theLockSync : block constant cBinLockWidth : integer := 2; constant cBinLock0 : std_logic_vector(cBinLockWidth-1 downto 0) := "01"; constant cBinLock1 : std_logic_vector(cBinLockWidth-1 downto 0) := "11"; constant cBinLock2 : std_logic_vector(cBinLockWidth-1 downto 0) := "10"; signal binLockedVBuf : std_logic_vector(cBinLockWidth-1 downto 0); signal binApSelVBuf : std_logic_vector(cBinLockWidth-1 downto 0); begin --conSelVBuf_s is in the PCP clock domain, thus the lockedVBuf_s signal must be -- synchronized from PCP clock- to AP clock domain! --In addition the one hot approach is transformed to save one line binLockedVBuf <= cBinLock0 when lockedVBuf_s = cOneHotVirtualBuffer0 else cBinLock1 when lockedVBuf_s = cOneHotVirtualBuffer1 else cBinLock2; apSelVBuf_s <= cOneHotVirtualBuffer0 when binApSelVBuf = cBinLock0 else cOneHotVirtualBuffer1 when binApSelVBuf = cBinLock1 else cOneHotVirtualBuffer2; vectorSync : FOR i in cBinLockWidth-1 DOWNTO 0 GENERATE theLockedSync : ENTITY work.sync generic map ( doSync_g => not genOnePdiClkDomain_g ) PORT MAP ( din => binLockedVBuf(i), dout => binApSelVBuf(i), clk => apClk, rst => apReset ); END GENERATE; end block; theTripleBufferLogic : BLOCK --The PCP triggers with triggerA and sets buffers to valid. --The AP triggers with triggerB and locks buffers for reading. SIGNAL clk, rst : STD_LOGIC; SIGNAL triggerA : STD_LOGIC; SIGNAL triggerB, triggerB_s : STD_LOGIC; --triggerB is in AP clock domain! SIGNAL toggleB, toggleBsync : STD_LOGIC; --toggleB is toggled by AP and synced to PCP SIGNAL toggleEdge : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL locked : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL currentA : STD_LOGIC_VECTOR(2 DOWNTO 0); --current selected buffer by PCP -- SIGNAL valid : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN --triple buffer logic is implemented in PCP clock domain! clk <= pcpClk; rst <= pcpReset; --triggerA is the producer's trigger triggerA <= pcpTrigger when bApIsProducer = false else triggerB_s; --conTrigger pulse is in AP clock domain, thus different clock rates will produce more or less pulses! ---thus a toggling signal crosses the clock domain genToggleB : PROCESS(apClk, apReset) BEGIN IF apReset = '1' THEN toggleB <= '0'; ELSIF apClk = '1' AND apClk'EVENT THEN --CAUTION: AP clock is used! IF apTrigger = '1' THEN toggleB <= not toggleB; END IF; END IF; END PROCESS genToggleB; theToggleSync : ENTITY work.sync generic map ( doSync_g => not genOnePdiClkDomain_g ) PORT MAP ( din => toggleB, dout => toggleBsync, clk => clk, rst => rst ); toggleShiftReg: PROCESS(clk, rst) BEGIN IF rst = '1' THEN toggleEdge <= (OTHERS => '0'); ELSIF clk = '1' AND clk'event THEN --shift register toggleEdge <= toggleEdge(0) & toggleBsync; END IF; END PROCESS toggleShiftReg; triggerB_s <= toggleEdge(1) xor toggleEdge(0); --triggerB is the consumer's trigger triggerB <= triggerB_s when bApIsProducer = false else pcpTrigger; --currentA is set by PCP (currently used buffer by PCP) pcpSelVBuf_s <= currentA when bApIsProducer = false else locked; --locked virtual buffer in PCP clock domain lockedVBuf_s <= locked when bApIsProducer = false else currentA; tripleBufMechanism : PROCESS(clk, rst) VARIABLE valid_v : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN IF rst = '1' THEN --initial state: ---buffer "001" is valid valid_v := initialValid_c; ---buffer "010" is locked locked <= initialLocked_c; ---buffer "100" is currently used by PCP currentA <= initialCurrent_c; ELSIF clk = '1' AND clk'EVENT THEN IF triggerA = '1' THEN --PCP triggers buffer change ---set valid to current selected buffer ---search for free buffer (not locked and valid) valid_v := currentA; --free buffer search ex.: -- locked "001" -- valid "010" -- ============ -- free "100" currentA <= not locked and not valid_v; END IF; IF triggerB = '1' THEN --AP triggers buffer change ---change AP to valid buffer locked <= valid_v; END IF; END IF; END PROCESS tripleBufMechanism; END BLOCK theTripleBufferLogic; END ARCHITECTURE rtl;
------------------------------------------------------------------------------- -- Triple Buffer Control Logic -- -- Copyright (C) 2010 B&R -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact office@br-automation.com -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- -- This logic implements the virtual triple buffers, by selecting the -- appropriate address offset. The output address offset has to be added to the -- input address. The trigger signal switches to the next available buffer. -- The switch mechanism is implemented in the PCP's clock domain. Thus the -- switch over on the PCP side is performed without delay. An AP switch over -- crosses from AP to PCP clock domain (2x pcpClk) and back from PCP to AP -- (2x apClk). ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY tripleVBufLogic IS GENERIC( genOnePdiClkDomain_g : boolean := false; --base address of virtual buffers in DPR iVirtualBufferBase_g : INTEGER := 0; --size of one virtual buffer in DPR (must be aligned!!!) iVirtualBufferSize_g : INTEGER := 1024; --out address width iOutAddrWidth_g : INTEGER := 13; --in address width iInAddrWidth_g : INTEGER := 11; --ap is producer bApIsProducer : BOOLEAN := FALSE ); PORT ( pcpClk : IN STD_LOGIC; pcpReset : IN STD_LOGIC; pcpTrigger : IN STD_LOGIC; --trigger virtual buffer change --pcpInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0); pcpOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0); pcpOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer (one-hot coded) apClk : IN STD_LOGIC; apReset : IN STD_LOGIC; apTrigger : IN STD_LOGIC; --trigger virtual buffer change --apInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0); apOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0); apOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) --selected virtual buffer (one-hot coded) ); END ENTITY tripleVBufLogic; ARCHITECTURE rtl OF tripleVBufLogic IS --constants ---virtual buffer base address CONSTANT iVirtualBufferBase0_c : INTEGER := 0*iVirtualBufferSize_g + iVirtualBufferBase_g; CONSTANT iVirtualBufferBase1_c : INTEGER := 1*iVirtualBufferSize_g + iVirtualBufferBase_g; CONSTANT iVirtualBufferBase2_c : INTEGER := 2*iVirtualBufferSize_g + iVirtualBufferBase_g; ---one hot code constant cOneHotVirtualBuffer0 : std_logic_vector(2 downto 0) := "001"; constant cOneHotVirtualBuffer1 : std_logic_vector(2 downto 0) := "010"; constant cOneHotVirtualBuffer2 : std_logic_vector(2 downto 0) := "100"; ---triple buffer mechanism ----initial states CONSTANT initialValid_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer0; CONSTANT initialLocked_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer1; CONSTANT initialCurrent_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer2; --signals ---PCP and AP selected virtual buffer SIGNAL pcpSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by producer SIGNAL apSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by consumer SIGNAL lockedVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --locked virtual buffer in producer clk domain BEGIN pcpOutSelVBuf <= pcpSelVBuf_s; apOutSelVBuf <= apSelVBuf_s; theAddrCalcer : BLOCK --depending on the selected virtual buffer (???SelVBuf_s), the output address is calculated (???OutAddr) -- ???SelVBuf_s | ???OutAddr -- ------------------------- -- "001" | ???InAddr + iVirtualBufferBase0_c -- "010" | ???InAddr + iVirtualBufferBase1_c -- "100" | ???InAddr + iVirtualBufferBase2_c SIGNAL pcpAddrOffset, apAddrOffset: STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0); --SIGNAL pcpSum, apSum : STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0); BEGIN --select address offset pcpAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer0 ELSE CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer1 ELSE CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer2 ELSE (OTHERS => '0'); pcpOutAddrOff <= pcpAddrOffset; --calculate address for dpr, leading zero is a sign! --pcpSum <= ('0' & conv_std_logic_vector(conv_integer(pcpInAddr), iOutAddrWidth_g-1)) + ('0' & pcpAddrOffset); --pcpOutAddr <= pcpSum(pcpOutAddr'RANGE); --select address offset apAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer0 ELSE CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer1 ELSE CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer2 ELSE (OTHERS => '0'); apOutAddrOff <= apAddrOffset; --calculate address for dpr, leading zero is a sign! --apSum <= ('0' & conv_std_logic_vector(conv_integer(apInAddr), iOutAddrWidth_g-1)) + ('0' & apAddrOffset); --apOutAddr <= apSum(apOutAddr'RANGE); END BLOCK theAddrCalcer; theLockSync : block constant cBinLockWidth : integer := 2; constant cBinLock0 : std_logic_vector(cBinLockWidth-1 downto 0) := "01"; constant cBinLock1 : std_logic_vector(cBinLockWidth-1 downto 0) := "11"; constant cBinLock2 : std_logic_vector(cBinLockWidth-1 downto 0) := "10"; signal binLockedVBuf : std_logic_vector(cBinLockWidth-1 downto 0); signal binApSelVBuf : std_logic_vector(cBinLockWidth-1 downto 0); begin --conSelVBuf_s is in the PCP clock domain, thus the lockedVBuf_s signal must be -- synchronized from PCP clock- to AP clock domain! --In addition the one hot approach is transformed to save one line binLockedVBuf <= cBinLock0 when lockedVBuf_s = cOneHotVirtualBuffer0 else cBinLock1 when lockedVBuf_s = cOneHotVirtualBuffer1 else cBinLock2; apSelVBuf_s <= cOneHotVirtualBuffer0 when binApSelVBuf = cBinLock0 else cOneHotVirtualBuffer1 when binApSelVBuf = cBinLock1 else cOneHotVirtualBuffer2; vectorSync : FOR i in cBinLockWidth-1 DOWNTO 0 GENERATE theLockedSync : ENTITY work.sync generic map ( doSync_g => not genOnePdiClkDomain_g ) PORT MAP ( din => binLockedVBuf(i), dout => binApSelVBuf(i), clk => apClk, rst => apReset ); END GENERATE; end block; theTripleBufferLogic : BLOCK --The PCP triggers with triggerA and sets buffers to valid. --The AP triggers with triggerB and locks buffers for reading. SIGNAL clk, rst : STD_LOGIC; SIGNAL triggerA : STD_LOGIC; SIGNAL triggerB, triggerB_s : STD_LOGIC; --triggerB is in AP clock domain! SIGNAL toggleB, toggleBsync : STD_LOGIC; --toggleB is toggled by AP and synced to PCP SIGNAL toggleEdge : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL locked : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL currentA : STD_LOGIC_VECTOR(2 DOWNTO 0); --current selected buffer by PCP -- SIGNAL valid : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN --triple buffer logic is implemented in PCP clock domain! clk <= pcpClk; rst <= pcpReset; --triggerA is the producer's trigger triggerA <= pcpTrigger when bApIsProducer = false else triggerB_s; --conTrigger pulse is in AP clock domain, thus different clock rates will produce more or less pulses! ---thus a toggling signal crosses the clock domain genToggleB : PROCESS(apClk, apReset) BEGIN IF apReset = '1' THEN toggleB <= '0'; ELSIF apClk = '1' AND apClk'EVENT THEN --CAUTION: AP clock is used! IF apTrigger = '1' THEN toggleB <= not toggleB; END IF; END IF; END PROCESS genToggleB; theToggleSync : ENTITY work.sync generic map ( doSync_g => not genOnePdiClkDomain_g ) PORT MAP ( din => toggleB, dout => toggleBsync, clk => clk, rst => rst ); toggleShiftReg: PROCESS(clk, rst) BEGIN IF rst = '1' THEN toggleEdge <= (OTHERS => '0'); ELSIF clk = '1' AND clk'event THEN --shift register toggleEdge <= toggleEdge(0) & toggleBsync; END IF; END PROCESS toggleShiftReg; triggerB_s <= toggleEdge(1) xor toggleEdge(0); --triggerB is the consumer's trigger triggerB <= triggerB_s when bApIsProducer = false else pcpTrigger; --currentA is set by PCP (currently used buffer by PCP) pcpSelVBuf_s <= currentA when bApIsProducer = false else locked; --locked virtual buffer in PCP clock domain lockedVBuf_s <= locked when bApIsProducer = false else currentA; tripleBufMechanism : PROCESS(clk, rst) VARIABLE valid_v : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN IF rst = '1' THEN --initial state: ---buffer "001" is valid valid_v := initialValid_c; ---buffer "010" is locked locked <= initialLocked_c; ---buffer "100" is currently used by PCP currentA <= initialCurrent_c; ELSIF clk = '1' AND clk'EVENT THEN IF triggerA = '1' THEN --PCP triggers buffer change ---set valid to current selected buffer ---search for free buffer (not locked and valid) valid_v := currentA; --free buffer search ex.: -- locked "001" -- valid "010" -- ============ -- free "100" currentA <= not locked and not valid_v; END IF; IF triggerB = '1' THEN --AP triggers buffer change ---change AP to valid buffer locked <= valid_v; END IF; END IF; END PROCESS tripleBufMechanism; END BLOCK theTripleBufferLogic; END ARCHITECTURE rtl;
entity tb_iassoc02 is end tb_iassoc02; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_iassoc02 is signal a : natural; signal b : natural; signal v : natural; begin dut: entity work.iassoc02 port map (v, a, b); process begin v <= 5; wait for 1 ns; assert a = 6 severity failure; assert b = 7 severity failure; v <= 203; wait for 1 ns; assert a = 204 severity failure; assert b = 205 severity failure; wait; end process; end behav;
------------------------------------------------------------------------------- --! @file convRmiiToMii-rtl-ea.vhd -- --! @brief RMII-to-MII converter -- --! @details This is an RMII-to-MII converter to convert MII phy traces to RMII. --! Example: MII PHY <--> RMII-to-MII converter <--> RMII MAC ------------------------------------------------------------------------------- -- -- (c) B&R, 2014 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact office@br-automation.com -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --! Common library library libcommon; --! Use common library global package use libcommon.global.all; --! Work library library work; --! use openmac package use work.openmacPkg.all; entity convRmiiToMii is port ( --! Reset iRst : in std_logic; --! RMII Clock iClk : in std_logic; --! RMII transmit path iRmiiTx : in tRmiiPath; --! RMII receive path oRmiiRx : out tRmiiPath; --! MII receive clock iMiiRxClk : in std_logic; --! MII receive path iMiiRx : in tMiiPath; --! MII receive error iMiiRxError : in std_logic; --! MII transmit clock iMiiTxClk : in std_logic; --! MII transmit path oMiiTx : out tMiiPath ); end convRmiiToMii; architecture rtl of convRmiiToMii is constant DIBIT_SIZE : integer := 2; constant NIBBLE_SIZE : integer := 4; begin TX_BLOCK : block --fifo size must not be larger than 2**5 constant FIFO_NIBBLES_LOG2 : integer := 5; signal fifo_half, fifo_full, fifo_empty, fifo_valid, txEnable_reg : std_logic; signal fifo_wr, fifo_rd : std_logic; signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0); signal fifo_dout, txData_reg : std_logic_vector(NIBBLE_SIZE-1 downto 0); signal fifo_rdUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0); --necessary for clr fifo signal aclr, rTxEn_l : std_logic; --convert dibits to nibble signal sel_dibit : std_logic; signal fifo_din_reg : std_logic_vector(iRmiiTx.data'range); begin fifo_din <= iRmiiTx.data & fifo_din_reg; fifo_wr <= sel_dibit; --convert dibits to nibble (to fit to fifo) process(iClk, iRst) begin if iRst = cActivated then sel_dibit <= cInactivated; fifo_din_reg <= (others => cInactivated); elsif iClk = cActivated and iClk'event then if iRmiiTx.enable = cActivated then sel_dibit <= not sel_dibit; if sel_dibit = cInactivated then fifo_din_reg <= iRmiiTx.data; end if; else sel_dibit <= cInactivated; end if; end if; end process; fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left); oMiiTx.data <= txData_reg; oMiiTx.enable <= txEnable_reg; process(iMiiTxClk, iRst) begin if iRst = cActivated then fifo_rd <= cInactivated; fifo_valid <= cInactivated; txData_reg <= (others => cInactivated); txEnable_reg <= cInactivated; elsif iMiiTxClk = cActivated and iMiiTxClk'event then txData_reg <= fifo_dout; txEnable_reg <= fifo_valid; if fifo_rd = cInactivated and fifo_half = cActivated then fifo_rd <= cActivated; elsif fifo_rd = cActivated and fifo_empty = cActivated then fifo_rd <= cInactivated; end if; if fifo_rd = cActivated and fifo_rdUsedWord > std_logic_vector(to_unsigned(1, fifo_rdUsedWord'length)) then fifo_valid <= cActivated; else fifo_valid <= cInactivated; end if; end if; end process; --! This is the asynchronous FIFO used to decouple RMII from MII. TXFIFO : entity work.asyncFifo generic map ( gDataWidth => NIBBLE_SIZE, gWordSize => 2**FIFO_NIBBLES_LOG2, gSyncStages => 2, gMemRes => "ON" ) port map ( iAclr => aclr, iWrClk => iClk, iWrReq => fifo_wr, iWrData => fifo_din, oWrEmpty => open, oWrFull => fifo_full, oWrUsedw => open, iRdClk => iMiiTxClk, iRdReq => fifo_rd, oRdData => fifo_dout, oRdEmpty => fifo_empty, oRdFull => open, oRdUsedw => fifo_rdUsedWord ); --sync Mii Tx En (=fifo_valid) to wr clk process(iClk, iRst) begin if iRst = cActivated then aclr <= cActivated; --reset fifo rTxEn_l <= cInactivated; elsif iClk = cActivated and iClk'event then rTxEn_l <= iRmiiTx.enable; aclr <= cInactivated; --default --clear the full fifo after TX on RMII side is done if fifo_full = cActivated and rTxEn_l = cActivated and iRmiiTx.enable = cInactivated then aclr <= cActivated; end if; end if; end process; end block; RX_BLOCK : block --fifo size must not be larger than 2**5 constant FIFO_NIBBLES_LOG2 : integer := 5; signal fifo_half, fifo_empty, fifo_valid : std_logic; signal rxDataValid_reg, fifo_rd : std_logic; signal rxError_reg : std_logic; signal fifo_wr : std_logic; signal rxData_reg : std_logic_vector(NIBBLE_SIZE-1 downto 0); signal fifo_dout : std_logic_vector(NIBBLE_SIZE-1 downto 0); signal fifo_rdUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0); signal fifo_wrUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0); --convert nibble to dibits signal sel_dibit : std_logic; signal fifo_rd_s : std_logic; begin process(iMiiRxClk, iRst) begin if iRst = cActivated then rxData_reg <= (others => cInactivated); rxDataValid_reg <= cInactivated; rxError_reg <= cInactivated; elsif iMiiRxClk = cActivated and iMiiRxClk'event then rxData_reg <= iMiiRx.data; rxDataValid_reg <= iMiiRx.enable; rxError_reg <= iMiiRxError; end if; end process; fifo_wr <= rxDataValid_reg and not rxError_reg; oRmiiRx.data <= fifo_dout(fifo_dout'right+1 downto 0) when sel_dibit = cActivated else fifo_dout(fifo_dout'left downto fifo_dout'left-1); oRmiiRx.enable <= fifo_valid; fifo_rd <= fifo_rd_s and not sel_dibit; process(iClk, iRst) begin if iRst = cActivated then sel_dibit <= cInactivated; elsif iClk = cActivated and iClk'event then if fifo_rd_s = cActivated or fifo_valid = cActivated then sel_dibit <= not sel_dibit; else sel_dibit <= cInactivated; end if; end if; end process; fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left); process(iClk, iRst) begin if iRst = cActivated then fifo_rd_s <= cInactivated; fifo_valid <= cInactivated; elsif iClk = cActivated and iClk'event then if fifo_rd_s = cInactivated and fifo_half = cActivated then fifo_rd_s <= cActivated; elsif fifo_rd_s = cActivated and fifo_empty = cActivated then fifo_rd_s <= cInactivated; end if; if fifo_rd_s = cActivated then fifo_valid <= cActivated; else fifo_valid <= cInactivated; end if; end if; end process; --! This is the asynchronous FIFO used to decouple RMII from MII. RXFIFO : entity work.asyncFifo generic map ( gDataWidth => NIBBLE_SIZE, gWordSize => 2**FIFO_NIBBLES_LOG2, gSyncStages => 2, gMemRes => "ON" ) port map ( iAclr => iRst, iWrClk => iMiiRxClk, iWrReq => fifo_wr, iWrData => rxData_reg, oWrEmpty => open, oWrFull => open, oWrUsedw => open, iRdClk => iClk, iRdReq => fifo_rd, oRdData => fifo_dout, oRdEmpty => fifo_empty, oRdFull => open, oRdUsedw => fifo_rdUsedWord ); end block; end rtl;
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 17:45:55 03/24/2015 -- Design Name: -- Module Name: C:/Users/Jeff Magina/Documents/GitHub/ECE368/Project1/DECODE/decode_tbd.vhd -- Project Name: decode -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: decode -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY decode_tbd IS END decode_tbd; ARCHITECTURE behavior OF decode_tbd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT decode PORT( CLK : IN std_logic; INST_IN : IN std_logic_vector(15 downto 0); OPCODE : OUT std_logic_vector(3 downto 0); REG_A : OUT std_logic_vector(3 downto 0); REG_B : OUT std_logic_vector(3 downto 0); IMMEDIATE : OUT std_logic_vector(3 downto 0) ); END COMPONENT; --Inputs signal CLK : std_logic := '0'; signal INST_IN : std_logic_vector(15 downto 0) := (others => '0'); --Outputs signal OPCODE : std_logic_vector(3 downto 0); signal REG_A : std_logic_vector(3 downto 0); signal REG_B : std_logic_vector(3 downto 0); signal IMMEDIATE : std_logic_vector(3 downto 0); -- Clock period definitions constant CLK_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: decode PORT MAP ( CLK => CLK, INST_IN => INST_IN, OPCODE => OPCODE, REG_A => REG_A, REG_B => REG_B, IMMEDIATE => IMMEDIATE ); -- Clock process definitions CLK_process :process begin CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; end process; -- Stimulus process tb: process begin -- hold reset state for 100 ns. wait for 20 ns; report "Start Debug Test Bench!" severity Note; INST_IN <= x"0FC0"; wait for CLK_period; INST_IN <= x"1671"; wait for CLK_period; INST_IN <= x"467A"; wait for CLK_period; INST_IN <= x"0682"; wait for CLK_period; wait for 100 ns; wait; end process; END;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity alien31_rom is port( addr: in std_logic_vector(9 downto 0); data: out std_logic_vector(2 downto 0) ); end alien31_rom; architecture content of alien31_rom is type rgb_array is array(0 to 31) of std_logic_vector(2 downto 0); type rom_type is array(0 to 31) of rgb_array; signal rgb_row: rgb_array; constant ALIEN: rom_type := ( ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000"), ("000", "000", "000", "000", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "000", "000", "000", "000"), ("000", "000", "000", "000", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000", "111", "111", "111", "111", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "000", "000", "111", "111", "111", "111", "111", "111", "000", "000", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "000", "111", "111", "111", "111", "111", "111", "111", "111", "000", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "000", "000", "111", "111", "111", "111", "111", "111", "000", "000", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "111", "000", "000", "111", "111", "111", "111", "000", "000", "111", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "111", "000", "111", "000", "111", "000", "111", "000", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "000", "111", "000", "111", "000", "111", "000", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "000", "111", "000", "111", "000", "111", "000", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "000", "111", "000", "111", "000", "111", "000", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "000", "000", "111", "111", "111", "111", "111", "111", "111", "111", "000", "000", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "111", "111", "111", "111", "111", "000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "111", "111", "111", "111", "111", "000", "000", "000", "000"), ("000", "000", "000", "000", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "000", "000", "000", "000"), ("000", "000", "000", "000", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "000", "000", "000", "000"), ("000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000") ); begin rgb_row <= ALIEN(conv_integer(addr(9 downto 5))); data <= rgb_row(conv_integer(addr(4 downto 0))); end content;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity alien31_rom is port( addr: in std_logic_vector(9 downto 0); data: out std_logic_vector(2 downto 0) ); end alien31_rom; architecture content of alien31_rom is type rgb_array is array(0 to 31) of std_logic_vector(2 downto 0); type rom_type is array(0 to 31) of rgb_array; signal rgb_row: rgb_array; constant ALIEN: rom_type := ( ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000"), ("000", "000", "000", "000", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "000", "000", "000", "000"), ("000", "000", "000", "000", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000", "111", "111", "111", "111", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "000", "000", "111", "111", "111", "111", "111", "111", "000", "000", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "000", "111", "111", "111", "111", "111", "111", "111", "111", "000", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "000", "000", "111", "111", "111", "111", "111", "111", "000", "000", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "111", "000", "000", "111", "111", "111", "111", "000", "000", "111", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "111", "000", "111", "000", "111", "000", "111", "000", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "000", "111", "000", "111", "000", "111", "000", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "000", "111", "000", "111", "000", "111", "000", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "000", "111", "000", "111", "000", "111", "000", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "111", "111", "111", "111", "111", "000", "000", "111", "111", "111", "111", "111", "111", "111", "111", "000", "000", "111", "111", "111", "111", "111", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "111", "111", "111", "111", "111", "000", "000", "000", "000", "111", "111", "111", "111", "111", "111", "000", "000", "000", "000", "111", "111", "111", "111", "111", "000", "000", "000", "000"), ("000", "000", "000", "000", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "000", "000", "000", "000"), ("000", "000", "000", "000", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "000", "000", "000", "000"), ("000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"), ("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000") ); begin rgb_row <= ALIEN(conv_integer(addr(9 downto 5))); data <= rgb_row(conv_integer(addr(4 downto 0))); end content;
-- ------------------------------------------------------------- -- -- Generated Configuration for inst_t_e -- -- Generated -- by: wig -- on: Mon Mar 5 13:21:41 2007 -- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -variant Calculate -nodelta ../../macro.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_t_e-rtl-conf-c.vhd,v 1.1 2007/03/05 13:22:43 wig Exp $ -- $Date: 2007/03/05 13:22:43 $ -- $Log: inst_t_e-rtl-conf-c.vhd,v $ -- Revision 1.1 2007/03/05 13:22:43 wig -- Added testcase for selection of macros with ::variant switch -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.47 , wilfried.gaensheimer@micronas.com -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/conf -- -- Start of Generated Configuration inst_t_e_rtl_conf / inst_t_e -- configuration inst_t_e_rtl_conf of inst_t_e is for rtl -- Generated Configuration for inst_3 : inst_3_e use configuration work.inst_3_e_rtl_conf; end for; for inst_4 : inst_4_e use configuration work.inst_4_e_rtl_conf; end for; for inst_5 : inst_5_e use configuration work.inst_5_e_rtl_conf; end for; for inst_a : inst_a_e use configuration work.inst_a_e_rtl_conf; end for; for inst_b : inst_b_e use configuration work.inst_b_e_rtl_conf; end for; for inst_k1_k2 : inst_k1_k2_e use configuration work.inst_k1_k2_rtl_conf; end for; for inst_k1_k4 : inst_k1_k4_e use configuration work.inst_k1_k4_rtl_conf; end for; for inst_k3_k2 : inst_k3_k2_e use configuration work.inst_k3_k2_rtl_conf; end for; for inst_k3_k4 : inst_k3_k4_e use configuration work.inst_k3_k4_rtl_conf; end for; for inst_ok_1 : inst_ok_1_e use configuration work.inst_ok_1_rtl_conf; end for; for inst_ok_10 : inst_ok_10_e use configuration work.inst_ok_10_rtl_conf; end for; for inst_ok_2 : inst_ok_2_e use configuration work.inst_ok_2_rtl_conf; end for; for inst_ok_3 : inst_ok_3_e use configuration work.inst_ok_3_rtl_conf; end for; for inst_ok_4 : inst_ok_4_e use configuration work.inst_ok_4_rtl_conf; end for; for inst_ok_5 : inst_ok_5_e use configuration work.inst_ok_5_rtl_conf; end for; for inst_ok_6 : inst_ok_6_e use configuration work.inst_ok_6_rtl_conf; end for; for inst_ok_7 : inst_ok_7_e use configuration work.inst_ok_7_rtl_conf; end for; for inst_ok_8 : inst_ok_8_e use configuration work.inst_ok_8_rtl_conf; end for; for inst_ok_9 : inst_ok_9_e use configuration work.inst_ok_9_rtl_conf; end for; for inst_shadow_1 : inst_shadow_1_e use configuration work.inst_shadow_1_rtl_conf; end for; for inst_shadow_10 : inst_shadow_10_e use configuration work.inst_shadow_10_rtl_conf; end for; for inst_shadow_2 : inst_shadow_2_e use configuration work.inst_shadow_2_rtl_conf; end for; for inst_shadow_3 : inst_shadow_3_e use configuration work.inst_shadow_3_rtl_conf; end for; for inst_shadow_4 : inst_shadow_4_e use configuration work.inst_shadow_4_rtl_conf; end for; for inst_shadow_5 : inst_shadow_5_e use configuration work.inst_shadow_5_rtl_conf; end for; for inst_shadow_6 : inst_shadow_6_e use configuration work.inst_shadow_6_rtl_conf; end for; for inst_shadow_7 : inst_shadow_7_e use configuration work.inst_shadow_7_rtl_conf; end for; for inst_shadow_8 : inst_shadow_8_e use configuration work.inst_shadow_8_rtl_conf; end for; for inst_shadow_9 : inst_shadow_9_e use configuration work.inst_shadow_9_rtl_conf; end for; for inst_shadow_a : inst_shadow_a_e use configuration work.inst_shadow_a_rtl_conf; end for; for inst_shadow_b : inst_shadow_b_e use configuration work.inst_shadow_b_rtl_conf; end for; for inst_shadow_k1_k2 : inst_shadow_k1_k2_e use configuration work.inst_shadow_k1_k2_rtl_conf; end for; for inst_shadow_k1_k4 : inst_shadow_k1_k4_e use configuration work.inst_shadow_k1_k4_rtl_conf; end for; for inst_shadow_k3_k2 : inst_shadow_k3_k2_e use configuration work.inst_shadow_k3_k2_rtl_conf; end for; for inst_shadow_k3_k4 : inst_shadow_k3_k4_e use configuration work.inst_shadow_k3_k4_rtl_conf; end for; for inst_shadow_ok_1 : inst_shadow_ok_1_e use configuration work.inst_shadow_ok_1_rtl_conf; end for; for inst_shadow_ok_10 : inst_shadow_ok_10_e use configuration work.inst_shadow_ok_10_rtl_conf; end for; for inst_shadow_ok_2 : inst_shadow_ok_2_e use configuration work.inst_shadow_ok_2_rtl_conf; end for; for inst_shadow_ok_3 : inst_shadow_ok_3_e use configuration work.inst_shadow_ok_3_rtl_conf; end for; for inst_shadow_ok_4 : inst_shadow_ok_4_e use configuration work.inst_shadow_ok_4_rtl_conf; end for; for inst_shadow_ok_5 : inst_shadow_ok_5_e use configuration work.inst_shadow_ok_5_rtl_conf; end for; for inst_shadow_ok_6 : inst_shadow_ok_6_e use configuration work.inst_shadow_ok_6_rtl_conf; end for; for inst_shadow_ok_7 : inst_shadow_ok_7_e use configuration work.inst_shadow_ok_7_rtl_conf; end for; for inst_shadow_ok_8 : inst_shadow_ok_8_e use configuration work.inst_shadow_ok_8_rtl_conf; end for; for inst_shadow_ok_9 : inst_shadow_ok_9_e use configuration work.inst_shadow_ok_9_rtl_conf; end for; for inst_shadow_t : inst_shadow_t_e use configuration work.inst_shadow_t_rtl_conf; end for; end for; end inst_t_e_rtl_conf; -- -- End of Generated Configuration inst_t_e_rtl_conf -- -- --!End of Configuration/ies -- --------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all; entity fulladder_generic is generic (N: integer:=8); port( a, b: in std_logic_vector (N-1 downto 0); ci: in std_logic; co: out std_logic; s: out std_logic_vector (N-1 downto 0); overf: out std_logic); end fulladder_generic; architecture behavior of fulladder_generic is component b1fulladder port( a, b, ci: IN std_logic; s,co: OUT std_logic); end component; signal internalco: std_logic_vector(N downto 0); signal sum: std_logic_vector(N-1 downto 0); begin internalco(0)<= ci; G1: for i in 1 to N generate additions: b1fulladder port map (a(i-1), b(i-1), internalco(i-1), sum(i-1), internalco(i)); end generate; co<=internalco(N); s<=sum; overf<=(a(N-1) and b(N-1) and (not sum(N-1))) or (not(a(N-1)) and not(b(N-1)) and sum(N-1)); end behavior;
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity image_filter_Mat2AXIvideo is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); img_data_stream_0_V_empty_n : IN STD_LOGIC; img_data_stream_0_V_read : OUT STD_LOGIC; img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); img_data_stream_1_V_empty_n : IN STD_LOGIC; img_data_stream_1_V_read : OUT STD_LOGIC; img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); img_data_stream_2_V_empty_n : IN STD_LOGIC; img_data_stream_2_V_read : OUT STD_LOGIC; OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0); OUTPUT_STREAM_TVALID : OUT STD_LOGIC; OUTPUT_STREAM_TREADY : IN STD_LOGIC; OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0); OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0); OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) ); end; architecture behav of image_filter_Mat2AXIvideo is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (3 downto 0) := "0001"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (3 downto 0) := "0010"; constant ap_ST_pp0_stg0_fsm_2 : STD_LOGIC_VECTOR (3 downto 0) := "0100"; constant ap_ST_st5_fsm_3 : STD_LOGIC_VECTOR (3 downto 0) := "1000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111"; constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000"; constant ap_const_lv13_1FFF : STD_LOGIC_VECTOR (12 downto 0) := "1111111111111"; constant ap_const_lv12_1 : STD_LOGIC_VECTOR (11 downto 0) := "000000000001"; constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111"; signal ap_done_reg : STD_LOGIC := '0'; signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC; signal ap_sig_bdd_23 : BOOLEAN; signal p_3_reg_170 : STD_LOGIC_VECTOR (11 downto 0); signal ap_sig_bdd_60 : BOOLEAN; signal op2_assign_fu_186_p2 : STD_LOGIC_VECTOR (12 downto 0); signal op2_assign_reg_267 : STD_LOGIC_VECTOR (12 downto 0); signal exitcond3_fu_197_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC; signal ap_sig_bdd_74 : BOOLEAN; signal i_V_fu_202_p2 : STD_LOGIC_VECTOR (11 downto 0); signal i_V_reg_276 : STD_LOGIC_VECTOR (11 downto 0); signal exitcond4_fu_208_p2 : STD_LOGIC_VECTOR (0 downto 0); signal exitcond4_reg_281 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_pp0_stg0_fsm_2 : STD_LOGIC; signal ap_sig_bdd_85 : BOOLEAN; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0'; signal ap_sig_bdd_99 : BOOLEAN; signal ap_sig_ioackin_OUTPUT_STREAM_TREADY : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal j_V_fu_213_p2 : STD_LOGIC_VECTOR (11 downto 0); signal axi_last_V_fu_223_p2 : STD_LOGIC_VECTOR (0 downto 0); signal axi_last_V_reg_290 : STD_LOGIC_VECTOR (0 downto 0); signal p_s_reg_159 : STD_LOGIC_VECTOR (11 downto 0); signal ap_sig_cseq_ST_st5_fsm_3 : STD_LOGIC; signal ap_sig_bdd_130 : BOOLEAN; signal tmp_user_V_fu_96 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ioackin_OUTPUT_STREAM_TREADY : STD_LOGIC := '0'; signal tmp_cast_fu_182_p1 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_cast_35_fu_219_p1 : STD_LOGIC_VECTOR (12 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0); begin -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_done_reg assign process. -- ap_done_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_done_reg <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_continue)) then ap_done_reg <= ap_const_logic_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_197_p2 = ap_const_lv1_0)))) then ap_done_reg <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ioackin_OUTPUT_STREAM_TREADY assign process. -- ap_reg_ioackin_OUTPUT_STREAM_TREADY_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0; else if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))))) then ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0; elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_99 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (ap_const_logic_1 = OUTPUT_STREAM_TREADY)))) then ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it0 assign process. -- ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0)))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_197_p2 = ap_const_lv1_0))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond4_fu_208_p2 = ap_const_lv1_0))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_1; elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_197_p2 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0))))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; end if; end if; end if; end process; -- p_3_reg_170 assign process. -- p_3_reg_170_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond4_fu_208_p2 = ap_const_lv1_0))) then p_3_reg_170 <= j_V_fu_213_p2; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_197_p2 = ap_const_lv1_0))) then p_3_reg_170 <= ap_const_lv12_0; end if; end if; end process; -- p_s_reg_159 assign process. -- p_s_reg_159_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_3)) then p_s_reg_159 <= i_V_reg_276; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_60))) then p_s_reg_159 <= ap_const_lv12_0; end if; end if; end process; -- tmp_user_V_fu_96 assign process. -- tmp_user_V_fu_96_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then tmp_user_V_fu_96 <= ap_const_lv1_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_60))) then tmp_user_V_fu_96 <= ap_const_lv1_1; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond4_fu_208_p2 = ap_const_lv1_0))) then axi_last_V_reg_290 <= axi_last_V_fu_223_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then exitcond4_reg_281 <= exitcond4_fu_208_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then i_V_reg_276 <= i_V_fu_202_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_60))) then op2_assign_reg_267 <= op2_assign_fu_186_p2; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_60, exitcond3_fu_197_p2, exitcond4_fu_208_p2, exitcond4_reg_281, ap_reg_ppiten_pp0_it0, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not(ap_sig_bdd_60)) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => if (not((exitcond3_fu_197_p2 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st1_fsm_0; else ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2; end if; when ap_ST_pp0_stg0_fsm_2 => if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0))))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0)))) then ap_NS_fsm <= ap_ST_st5_fsm_3; else ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2; end if; when ap_ST_st5_fsm_3 => ap_NS_fsm <= ap_ST_st2_fsm_1; when others => ap_NS_fsm <= "XXXX"; end case; end process; OUTPUT_STREAM_TDATA <= (((ap_const_lv8_FF & img_data_stream_2_V_dout) & img_data_stream_1_V_dout) & img_data_stream_0_V_dout); OUTPUT_STREAM_TDEST <= ap_const_lv1_0; OUTPUT_STREAM_TID <= ap_const_lv1_0; OUTPUT_STREAM_TKEEP <= ap_const_lv4_F; OUTPUT_STREAM_TLAST <= axi_last_V_reg_290; OUTPUT_STREAM_TSTRB <= ap_const_lv4_0; OUTPUT_STREAM_TUSER <= tmp_user_V_fu_96; -- OUTPUT_STREAM_TVALID assign process. -- OUTPUT_STREAM_TVALID_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_reg_ppiten_pp0_it1, ap_reg_ioackin_OUTPUT_STREAM_TREADY) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_99 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (ap_const_logic_0 = ap_reg_ioackin_OUTPUT_STREAM_TREADY)))) then OUTPUT_STREAM_TVALID <= ap_const_logic_1; else OUTPUT_STREAM_TVALID <= ap_const_logic_0; end if; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_done_reg, exitcond3_fu_197_p2, ap_sig_cseq_ST_st2_fsm_1) begin if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_197_p2 = ap_const_lv1_0))))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(exitcond3_fu_197_p2, ap_sig_cseq_ST_st2_fsm_1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_197_p2 = ap_const_lv1_0)))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; -- ap_sig_bdd_130 assign process. -- ap_sig_bdd_130_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_130 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3)); end process; -- ap_sig_bdd_23 assign process. -- ap_sig_bdd_23_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_23 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1); end process; -- ap_sig_bdd_60 assign process. -- ap_sig_bdd_60_assign_proc : process(ap_start, ap_done_reg) begin ap_sig_bdd_60 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1)); end process; -- ap_sig_bdd_74 assign process. -- ap_sig_bdd_74_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_74 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1)); end process; -- ap_sig_bdd_85 assign process. -- ap_sig_bdd_85_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_85 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2)); end process; -- ap_sig_bdd_99 assign process. -- ap_sig_bdd_99_assign_proc : process(img_data_stream_0_V_empty_n, img_data_stream_1_V_empty_n, img_data_stream_2_V_empty_n, exitcond4_reg_281) begin ap_sig_bdd_99 <= (((img_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond4_reg_281 = ap_const_lv1_0)) or ((exitcond4_reg_281 = ap_const_lv1_0) and (img_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond4_reg_281 = ap_const_lv1_0) and (img_data_stream_2_V_empty_n = ap_const_logic_0))); end process; -- ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. -- ap_sig_cseq_ST_pp0_stg0_fsm_2_assign_proc : process(ap_sig_bdd_85) begin if (ap_sig_bdd_85) then ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st1_fsm_0 assign process. -- ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_23) begin if (ap_sig_bdd_23) then ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1; else ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st2_fsm_1 assign process. -- ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_74) begin if (ap_sig_bdd_74) then ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1; else ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st5_fsm_3 assign process. -- ap_sig_cseq_ST_st5_fsm_3_assign_proc : process(ap_sig_bdd_130) begin if (ap_sig_bdd_130) then ap_sig_cseq_ST_st5_fsm_3 <= ap_const_logic_1; else ap_sig_cseq_ST_st5_fsm_3 <= ap_const_logic_0; end if; end process; -- ap_sig_ioackin_OUTPUT_STREAM_TREADY assign process. -- ap_sig_ioackin_OUTPUT_STREAM_TREADY_assign_proc : process(OUTPUT_STREAM_TREADY, ap_reg_ioackin_OUTPUT_STREAM_TREADY) begin if ((ap_const_logic_0 = ap_reg_ioackin_OUTPUT_STREAM_TREADY)) then ap_sig_ioackin_OUTPUT_STREAM_TREADY <= OUTPUT_STREAM_TREADY; else ap_sig_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_1; end if; end process; axi_last_V_fu_223_p2 <= "1" when (tmp_cast_35_fu_219_p1 = op2_assign_reg_267) else "0"; exitcond3_fu_197_p2 <= "1" when (p_s_reg_159 = img_rows_V_read) else "0"; exitcond4_fu_208_p2 <= "1" when (p_3_reg_170 = img_cols_V_read) else "0"; i_V_fu_202_p2 <= std_logic_vector(unsigned(p_s_reg_159) + unsigned(ap_const_lv12_1)); -- img_data_stream_0_V_read assign process. -- img_data_stream_0_V_read_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then img_data_stream_0_V_read <= ap_const_logic_1; else img_data_stream_0_V_read <= ap_const_logic_0; end if; end process; -- img_data_stream_1_V_read assign process. -- img_data_stream_1_V_read_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then img_data_stream_1_V_read <= ap_const_logic_1; else img_data_stream_1_V_read <= ap_const_logic_0; end if; end process; -- img_data_stream_2_V_read assign process. -- img_data_stream_2_V_read_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then img_data_stream_2_V_read <= ap_const_logic_1; else img_data_stream_2_V_read <= ap_const_logic_0; end if; end process; j_V_fu_213_p2 <= std_logic_vector(unsigned(p_3_reg_170) + unsigned(ap_const_lv12_1)); op2_assign_fu_186_p2 <= std_logic_vector(unsigned(tmp_cast_fu_182_p1) + unsigned(ap_const_lv13_1FFF)); tmp_cast_35_fu_219_p1 <= std_logic_vector(resize(unsigned(p_3_reg_170),13)); tmp_cast_fu_182_p1 <= std_logic_vector(resize(unsigned(img_cols_V_read),13)); end behav;
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity image_filter_Mat2AXIvideo is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); img_data_stream_0_V_empty_n : IN STD_LOGIC; img_data_stream_0_V_read : OUT STD_LOGIC; img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); img_data_stream_1_V_empty_n : IN STD_LOGIC; img_data_stream_1_V_read : OUT STD_LOGIC; img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); img_data_stream_2_V_empty_n : IN STD_LOGIC; img_data_stream_2_V_read : OUT STD_LOGIC; OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0); OUTPUT_STREAM_TVALID : OUT STD_LOGIC; OUTPUT_STREAM_TREADY : IN STD_LOGIC; OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0); OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0); OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) ); end; architecture behav of image_filter_Mat2AXIvideo is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (3 downto 0) := "0001"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (3 downto 0) := "0010"; constant ap_ST_pp0_stg0_fsm_2 : STD_LOGIC_VECTOR (3 downto 0) := "0100"; constant ap_ST_st5_fsm_3 : STD_LOGIC_VECTOR (3 downto 0) := "1000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111"; constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000"; constant ap_const_lv13_1FFF : STD_LOGIC_VECTOR (12 downto 0) := "1111111111111"; constant ap_const_lv12_1 : STD_LOGIC_VECTOR (11 downto 0) := "000000000001"; constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111"; signal ap_done_reg : STD_LOGIC := '0'; signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC; signal ap_sig_bdd_23 : BOOLEAN; signal p_3_reg_170 : STD_LOGIC_VECTOR (11 downto 0); signal ap_sig_bdd_60 : BOOLEAN; signal op2_assign_fu_186_p2 : STD_LOGIC_VECTOR (12 downto 0); signal op2_assign_reg_267 : STD_LOGIC_VECTOR (12 downto 0); signal exitcond3_fu_197_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC; signal ap_sig_bdd_74 : BOOLEAN; signal i_V_fu_202_p2 : STD_LOGIC_VECTOR (11 downto 0); signal i_V_reg_276 : STD_LOGIC_VECTOR (11 downto 0); signal exitcond4_fu_208_p2 : STD_LOGIC_VECTOR (0 downto 0); signal exitcond4_reg_281 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_pp0_stg0_fsm_2 : STD_LOGIC; signal ap_sig_bdd_85 : BOOLEAN; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0'; signal ap_sig_bdd_99 : BOOLEAN; signal ap_sig_ioackin_OUTPUT_STREAM_TREADY : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal j_V_fu_213_p2 : STD_LOGIC_VECTOR (11 downto 0); signal axi_last_V_fu_223_p2 : STD_LOGIC_VECTOR (0 downto 0); signal axi_last_V_reg_290 : STD_LOGIC_VECTOR (0 downto 0); signal p_s_reg_159 : STD_LOGIC_VECTOR (11 downto 0); signal ap_sig_cseq_ST_st5_fsm_3 : STD_LOGIC; signal ap_sig_bdd_130 : BOOLEAN; signal tmp_user_V_fu_96 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ioackin_OUTPUT_STREAM_TREADY : STD_LOGIC := '0'; signal tmp_cast_fu_182_p1 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_cast_35_fu_219_p1 : STD_LOGIC_VECTOR (12 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0); begin -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_done_reg assign process. -- ap_done_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_done_reg <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_continue)) then ap_done_reg <= ap_const_logic_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_197_p2 = ap_const_lv1_0)))) then ap_done_reg <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ioackin_OUTPUT_STREAM_TREADY assign process. -- ap_reg_ioackin_OUTPUT_STREAM_TREADY_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0; else if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))))) then ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0; elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_99 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (ap_const_logic_1 = OUTPUT_STREAM_TREADY)))) then ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it0 assign process. -- ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0)))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_197_p2 = ap_const_lv1_0))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond4_fu_208_p2 = ap_const_lv1_0))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_1; elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_197_p2 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0))))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; end if; end if; end if; end process; -- p_3_reg_170 assign process. -- p_3_reg_170_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond4_fu_208_p2 = ap_const_lv1_0))) then p_3_reg_170 <= j_V_fu_213_p2; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_197_p2 = ap_const_lv1_0))) then p_3_reg_170 <= ap_const_lv12_0; end if; end if; end process; -- p_s_reg_159 assign process. -- p_s_reg_159_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_3)) then p_s_reg_159 <= i_V_reg_276; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_60))) then p_s_reg_159 <= ap_const_lv12_0; end if; end if; end process; -- tmp_user_V_fu_96 assign process. -- tmp_user_V_fu_96_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then tmp_user_V_fu_96 <= ap_const_lv1_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_60))) then tmp_user_V_fu_96 <= ap_const_lv1_1; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond4_fu_208_p2 = ap_const_lv1_0))) then axi_last_V_reg_290 <= axi_last_V_fu_223_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then exitcond4_reg_281 <= exitcond4_fu_208_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then i_V_reg_276 <= i_V_fu_202_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_60))) then op2_assign_reg_267 <= op2_assign_fu_186_p2; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_60, exitcond3_fu_197_p2, exitcond4_fu_208_p2, exitcond4_reg_281, ap_reg_ppiten_pp0_it0, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not(ap_sig_bdd_60)) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => if (not((exitcond3_fu_197_p2 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st1_fsm_0; else ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2; end if; when ap_ST_pp0_stg0_fsm_2 => if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0))))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0)))) then ap_NS_fsm <= ap_ST_st5_fsm_3; else ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2; end if; when ap_ST_st5_fsm_3 => ap_NS_fsm <= ap_ST_st2_fsm_1; when others => ap_NS_fsm <= "XXXX"; end case; end process; OUTPUT_STREAM_TDATA <= (((ap_const_lv8_FF & img_data_stream_2_V_dout) & img_data_stream_1_V_dout) & img_data_stream_0_V_dout); OUTPUT_STREAM_TDEST <= ap_const_lv1_0; OUTPUT_STREAM_TID <= ap_const_lv1_0; OUTPUT_STREAM_TKEEP <= ap_const_lv4_F; OUTPUT_STREAM_TLAST <= axi_last_V_reg_290; OUTPUT_STREAM_TSTRB <= ap_const_lv4_0; OUTPUT_STREAM_TUSER <= tmp_user_V_fu_96; -- OUTPUT_STREAM_TVALID assign process. -- OUTPUT_STREAM_TVALID_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_reg_ppiten_pp0_it1, ap_reg_ioackin_OUTPUT_STREAM_TREADY) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_99 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (ap_const_logic_0 = ap_reg_ioackin_OUTPUT_STREAM_TREADY)))) then OUTPUT_STREAM_TVALID <= ap_const_logic_1; else OUTPUT_STREAM_TVALID <= ap_const_logic_0; end if; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_done_reg, exitcond3_fu_197_p2, ap_sig_cseq_ST_st2_fsm_1) begin if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_197_p2 = ap_const_lv1_0))))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(exitcond3_fu_197_p2, ap_sig_cseq_ST_st2_fsm_1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_197_p2 = ap_const_lv1_0)))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; -- ap_sig_bdd_130 assign process. -- ap_sig_bdd_130_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_130 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3)); end process; -- ap_sig_bdd_23 assign process. -- ap_sig_bdd_23_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_23 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1); end process; -- ap_sig_bdd_60 assign process. -- ap_sig_bdd_60_assign_proc : process(ap_start, ap_done_reg) begin ap_sig_bdd_60 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1)); end process; -- ap_sig_bdd_74 assign process. -- ap_sig_bdd_74_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_74 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1)); end process; -- ap_sig_bdd_85 assign process. -- ap_sig_bdd_85_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_85 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2)); end process; -- ap_sig_bdd_99 assign process. -- ap_sig_bdd_99_assign_proc : process(img_data_stream_0_V_empty_n, img_data_stream_1_V_empty_n, img_data_stream_2_V_empty_n, exitcond4_reg_281) begin ap_sig_bdd_99 <= (((img_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond4_reg_281 = ap_const_lv1_0)) or ((exitcond4_reg_281 = ap_const_lv1_0) and (img_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond4_reg_281 = ap_const_lv1_0) and (img_data_stream_2_V_empty_n = ap_const_logic_0))); end process; -- ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. -- ap_sig_cseq_ST_pp0_stg0_fsm_2_assign_proc : process(ap_sig_bdd_85) begin if (ap_sig_bdd_85) then ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st1_fsm_0 assign process. -- ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_23) begin if (ap_sig_bdd_23) then ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1; else ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st2_fsm_1 assign process. -- ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_74) begin if (ap_sig_bdd_74) then ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1; else ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st5_fsm_3 assign process. -- ap_sig_cseq_ST_st5_fsm_3_assign_proc : process(ap_sig_bdd_130) begin if (ap_sig_bdd_130) then ap_sig_cseq_ST_st5_fsm_3 <= ap_const_logic_1; else ap_sig_cseq_ST_st5_fsm_3 <= ap_const_logic_0; end if; end process; -- ap_sig_ioackin_OUTPUT_STREAM_TREADY assign process. -- ap_sig_ioackin_OUTPUT_STREAM_TREADY_assign_proc : process(OUTPUT_STREAM_TREADY, ap_reg_ioackin_OUTPUT_STREAM_TREADY) begin if ((ap_const_logic_0 = ap_reg_ioackin_OUTPUT_STREAM_TREADY)) then ap_sig_ioackin_OUTPUT_STREAM_TREADY <= OUTPUT_STREAM_TREADY; else ap_sig_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_1; end if; end process; axi_last_V_fu_223_p2 <= "1" when (tmp_cast_35_fu_219_p1 = op2_assign_reg_267) else "0"; exitcond3_fu_197_p2 <= "1" when (p_s_reg_159 = img_rows_V_read) else "0"; exitcond4_fu_208_p2 <= "1" when (p_3_reg_170 = img_cols_V_read) else "0"; i_V_fu_202_p2 <= std_logic_vector(unsigned(p_s_reg_159) + unsigned(ap_const_lv12_1)); -- img_data_stream_0_V_read assign process. -- img_data_stream_0_V_read_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then img_data_stream_0_V_read <= ap_const_logic_1; else img_data_stream_0_V_read <= ap_const_logic_0; end if; end process; -- img_data_stream_1_V_read assign process. -- img_data_stream_1_V_read_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then img_data_stream_1_V_read <= ap_const_logic_1; else img_data_stream_1_V_read <= ap_const_logic_0; end if; end process; -- img_data_stream_2_V_read assign process. -- img_data_stream_2_V_read_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then img_data_stream_2_V_read <= ap_const_logic_1; else img_data_stream_2_V_read <= ap_const_logic_0; end if; end process; j_V_fu_213_p2 <= std_logic_vector(unsigned(p_3_reg_170) + unsigned(ap_const_lv12_1)); op2_assign_fu_186_p2 <= std_logic_vector(unsigned(tmp_cast_fu_182_p1) + unsigned(ap_const_lv13_1FFF)); tmp_cast_35_fu_219_p1 <= std_logic_vector(resize(unsigned(p_3_reg_170),13)); tmp_cast_fu_182_p1 <= std_logic_vector(resize(unsigned(img_cols_V_read),13)); end behav;
---------------------------------------------------------------------------------- -- Company: -- Engineer: StrayWarrior -- -- Create Date: 23:26:40 11/19/2015 -- Design Name: -- Module Name: ForwardingUnit - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity ForwardingUnit is Port ( RegOpA : in STD_LOGIC_VECTOR (3 downto 0); RegOpB : in STD_LOGIC_VECTOR (3 downto 0); RegWE_MEM: in STD_LOGIC; RegDest_MEM : in STD_LOGIC_VECTOR (3 downto 0); RegWE_WB : in STD_LOGIC; RegDest_WB : STD_LOGIC_VECTOR (3 downto 0); MemRead_EXE : in STD_LOGIC; MemRead_WB : in STD_LOGIC; CReg : in STD_LOGIC; CRegA : in STD_LOGIC_VECTOR (3 downto 0); CRegB : in STD_LOGIC_VECTOR (3 downto 0); RegMemDIn_EXE : in STD_LOGIC_VECTOR (3 downto 0); RegMemDIn_MEM : in STD_LOGIC_VECTOR (3 downto 0); RegAValSel : out STD_LOGIC; RegBValSel : out STD_LOGIC; RegRAValSel : out STD_LOGIC; OperandASel : out STD_LOGIC_VECTOR (1 downto 0); OperandBSel : out STD_LOGIC_VECTOR (1 downto 0); MemDInSel_EXE : out STD_LOGIC_VECTOR (1 downto 0); MemDInSel_MEM : out STD_LOGIC ); end ForwardingUnit; architecture Behavioral of ForwardingUnit is begin OperandASel <= "01" when RegWE_MEM = '1' and RegDest_MEM /= "1111" and RegDest_MEM = RegOpA else "10" when RegWE_WB = '1' and RegDest_WB /= "1111" and RegDest_WB = RegOpA and (RegDest_MEM /= RegOpA or MemRead_WB = '1') else "00"; OperandBSel <= "01" when RegWE_MEM = '1' and RegDest_MEM /= "1111" and RegDest_MEM = RegOpB else "10" when RegWE_WB = '1' and RegDest_WB /= "1111" and RegDest_WB = RegOpB and (RegDest_MEM /= RegOpB or MemRead_WB = '1') else "00"; MemDInSel_EXE <= "01" when RegWE_MEM = '1' and RegDest_MEM /= "1111" and RegDest_MEM = RegMemDIn_EXE else "10" when RegWE_WB = '1' and RegDest_WB /= "1111" and RegDest_WB = RegMemDIn_EXE and (RegDest_MEM /= RegMemDIn_EXE or MemRead_WB = '1') else "00"; MemDInSel_MEM <= '1' when RegWE_WB = '1' and RegDest_WB /= "1111" and RegDest_WB = RegMemDIn_MEM else '0'; RegAValSel <= '1' when RegWE_MEM = '1' and RegDest_MEM /= "1111" and RegDest_MEM = CRegA else '0'; RegBValSel <= '1' when RegWE_MEM = '1' and RegDest_MEM /= "1111" and RegDest_MEM = CRegB else '0'; RegRAValSel <= '1' when RegWE_MEM = '1' and RegDest_MEM = "1000" else '0'; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity psr_modifier is Port( crs1 : in std_logic; ope2 : in std_logic; alur : in STD_LOGIC_VECTOR(31 downto 0); aluop : in std_logic_vector(5 downto 0); nzvc : out std_logic_vector(3 downto 0) ); end psr_modifier; architecture psr_modArq of psr_modifier is begin process(crs1, ope2, alur, aluop) begin -- ADDcc y ADDxcc if (aluop = "001000" or aluop = "01011") then nzvc(3) <= alur(31); if (alur = x"00000000") then nzvc(2) <= '1'; else nzvc(2) <= '0'; end if; nzvc(1) <= (crs1 and ope2 and (not alur(31))) or ((not crs1) and (not ope2) and alur(31)); nzvc(0) <= (crs1 and ope2) or ((not alur(31)) and (crs1 or ope2)); -- SUBcc y SUBxcc else if (aluop = "001001" or aluop = "001101")then nzvc(3) <= alur(31); if (alur = x"00000000") then nzvc(2) <= '1'; else nzvc(2) <= '0'; end if; nzvc(1) <= (crs1 and (not ope2) and (not alur(31))) or ((not crs1) and ope2 and alur(31)); nzvc(0) <= ((not crs1) and ope2) or (alur(31) and ((not crs1) or ope2)); --ANDcc, ANDNcc, ORcc, ORNcc, XORcc, XNORcc else if (aluop = "001111" or aluop = "010001" or aluop = "001110" or aluop = "010010" or aluop = "010000" or aluop = "010011")then nzvc(3) <= alur(31); if (alur = x"00000000") then nzvc(2) <= '1'; else nzvc(2) <= '0'; end if; nzvc(1) <= '0'; nzvc(0) <= '1'; end if; end if; end if; end process; end psr_modArq;
-- #################################### -- # Project: Yarr -- # Author: Timon Heim -- # E-Mail: timon.heim at cern.ch -- # Comments: Bridge between Rx core and Mem -- #################################### -- # Address Map: -- # 0x0000: Start Adr (RO) -- # 0x0001: Data Cnt (RO) -- # 0x0002[0]: Loopback (RW) -- # 0x0003: Data Rate (RO) -- # 0x0004: Loop Fifo (WO) library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity wb_rx_bridge is port ( -- Sys Connect sys_clk_i : in std_logic; rst_n_i : in std_logic; -- Wishbone slave interface wb_adr_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; wb_stall_o : out std_logic; -- Wishbone DMA Master Interface dma_clk_i : in std_logic; dma_adr_o : out std_logic_vector(31 downto 0); dma_dat_o : out std_logic_vector(31 downto 0); dma_dat_i : in std_logic_vector(31 downto 0); dma_cyc_o : out std_logic; dma_stb_o : out std_logic; dma_we_o : out std_logic; dma_ack_i : in std_logic; dma_stall_i : in std_logic; -- Rx Interface rx_data_i : in std_logic_vector(31 downto 0); rx_valid_i : in std_logic; -- Status In trig_pulse_i : in std_logic; -- Status out irq_o : out std_logic; busy_o : out std_logic ); end wb_rx_bridge; architecture Behavioral of wb_rx_bridge is -- Cmoponents COMPONENT rx_bridge_fifo PORT ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_full_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0); prog_empty_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC ); END COMPONENT; COMPONENT rx_bridge_ctrl_fifo PORT ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC ); END COMPONENT; -- Constants constant c_ALMOST_FULL_THRESHOLD : unsigned(10 downto 0) := TO_UNSIGNED(1900, 11); constant c_PACKAGE_SIZE : unsigned(31 downto 0) := TO_UNSIGNED((200*256), 32); -- 200kByte constant c_TIMEOUT : unsigned(31 downto 0) := TO_UNSIGNED(2**14, 32); -- Counts in 5ns = 0.1ms constant c_TIME_FRAME : unsigned(31 downto 0) := TO_UNSIGNED(200000000-1, 32); -- 200MHz clock cycles in 1 sec constant c_EMPTY_THRESHOLD : unsigned(10 downto 0) := TO_UNSIGNED(16, 11); constant c_EMPTY_TIMEOUT : unsigned(10 downto 0) := TO_UNSIGNED(2000, 11); -- Signals signal data_fifo_din : std_logic_vector(31 downto 0); signal data_fifo_dout : std_logic_vector(31 downto 0); signal data_fifo_wren : std_logic; signal data_fifo_rden : std_logic; signal data_fifo_full : std_logic; signal data_fifo_empty : std_logic; signal data_fifo_almost_full : std_logic; signal data_fifo_prog_empty : std_logic; signal data_fifo_empty_cnt : unsigned(10 downto 0); signal data_fifo_empty_true : std_logic; signal data_fifo_empty_pressure : std_logic; signal ctrl_fifo_din : std_logic_vector(63 downto 0); signal ctrl_fifo_dout : std_logic_vector(63 downto 0); signal ctrl_fifo_wren : std_logic; signal ctrl_fifo_rden : std_logic; signal ctrl_fifo_full : std_logic; signal ctrl_fifo_empty : std_logic; signal dma_stb_t : std_logic; signal dma_stb_valid : std_logic; signal dma_adr_cnt : unsigned(31 downto 0); signal dma_start_adr : unsigned(31 downto 0); signal dma_data_cnt : unsigned(31 downto 0); signal dma_data_cnt_d : unsigned(31 downto 0); signal dma_timeout_cnt : unsigned(31 downto 0); signal dma_ack_cnt : unsigned(7 downto 0); signal rx_data_local : std_logic_vector(31 downto 0); signal rx_valid_local : std_logic; signal rx_data_local_d : std_logic_vector(31 downto 0); signal rx_valid_local_d : std_logic; signal ctrl_fifo_dout_tmp : std_logic_vector(31 downto 0); signal time_cnt : unsigned(31 downto 0); signal time_pulse : std_logic; signal data_rate_cnt : unsigned(31 downto 0); signal trig_cnt : unsigned(31 downto 0); signal trig_pulse_d0 : std_logic; signal trig_pulse_d1 : std_logic; signal trig_pulse_pos : std_logic; -- Registers signal loopback : std_logic; signal data_rate : std_logic_vector(31 downto 0); begin --Tie offs irq_o <= '0'; busy_o <= data_fifo_full; -- Wishbone Slave wb_slave_proc: process(sys_clk_i, rst_n_i) begin if (rst_n_i = '0') then wb_dat_o <= (others => '0'); wb_ack_o <= '0'; wb_stall_o <= '0'; ctrl_fifo_rden <= '0'; rx_valid_local <= '0'; ctrl_fifo_dout_tmp <= (others => '0'); -- Regs loopback <= '0'; elsif rising_edge(sys_clk_i) then -- Default wb_ack_o <= '0'; ctrl_fifo_rden <= '0'; wb_stall_o <= '0'; rx_valid_local <= '0'; if (wb_cyc_i = '1' and wb_stb_i = '1') then if (wb_we_i = '0') then -- READ if (wb_adr_i(3 downto 0) = x"0") then -- Start Addr if (ctrl_fifo_empty = '0') then wb_dat_o <= ctrl_fifo_dout(31 downto 0); ctrl_fifo_dout_tmp <= ctrl_fifo_dout(63 downto 32); wb_ack_o <= '1'; ctrl_fifo_rden <= '1'; else wb_dat_o <= x"FFFFFFFF"; ctrl_fifo_dout_tmp <= (others => '0'); wb_ack_o <= '1'; ctrl_fifo_rden <= '0'; end if; elsif (wb_adr_i(3 downto 0) = x"1") then -- Count wb_dat_o <= ctrl_fifo_dout_tmp; wb_ack_o <= '1'; elsif (wb_adr_i(3 downto 0) = x"2") then -- Loopback wb_dat_o(31 downto 1) <= (others => '0'); wb_dat_o(0) <= loopback; wb_ack_o <= '1'; elsif (wb_adr_i(3 downto 0) = x"3") then -- Data Rate wb_dat_o <= data_rate; wb_ack_o <= '1'; elsif (wb_adr_i(3 downto 0) = x"5") then -- Bridge Empty wb_dat_o(31 downto 1) <= (others => '0'); wb_dat_o(0) <= data_fifo_empty_true; wb_ack_o <= '1'; elsif (wb_adr_i(3 downto 0) = x"6") then -- Cur Count wb_dat_o <= std_logic_vector(dma_data_cnt_d); wb_ack_o <= '1'; else wb_dat_o <= x"DEADBEEF"; wb_ack_o <= '1'; end if; else -- WRITE wb_ack_o <= '1'; if (wb_adr_i(3 downto 0) = x"2") then loopback <= wb_dat_i(0); elsif (wb_adr_i(3 downto 0) = x"4") then rx_valid_local <= '1'; end if; end if; end if; end if; end process wb_slave_proc; -- Data from Rx data_rec : process (sys_clk_i, rst_n_i) begin if (rst_n_i <= '0') then data_fifo_wren <= '0'; data_fifo_din <= (others => '0'); elsif rising_edge(sys_clk_i) then if (loopback = '1') then data_fifo_wren <= rx_valid_local_d; data_fifo_din <= rx_data_local_d; else data_fifo_wren <= rx_valid_i; data_fifo_din <= rx_data_i; end if; end if; end process data_rec; -- Empty logic to produce some backpressure data_fifo_empty <= '1' when (data_fifo_empty_true = '1') else data_fifo_empty_pressure; empty_proc : process(dma_clk_i, rst_n_i) begin if (rst_n_i = '0') then data_fifo_empty_pressure <= '0'; data_fifo_empty_cnt <= (others => '0'); elsif rising_edge(dma_clk_i) then -- Timeout Counter if (data_fifo_empty_true = '0' and data_fifo_empty_pressure = '1') then data_fifo_empty_cnt <= data_fifo_empty_cnt + 1; elsif (data_fifo_empty_true = '1') then data_fifo_empty_cnt <= (others => '0'); end if; if (data_fifo_empty_cnt > c_EMPTY_TIMEOUT) then data_fifo_empty_pressure <= '0'; elsif (data_fifo_prog_empty = '0') then data_fifo_empty_pressure <= '0'; elsif (data_fifo_empty_true = '1') then data_fifo_empty_pressure <= '1'; end if; end if; end process empty_proc; -- DMA Master and data control dma_stb_valid <= dma_stb_t and not data_fifo_empty; to_ddr_proc: process(dma_clk_i, rst_n_i) begin if(rst_n_i = '0') then dma_stb_t <= '0'; data_fifo_rden <= '0'; dma_adr_o <= (others => '0'); dma_dat_o <= (others => '0'); dma_cyc_o <= '0'; dma_stb_o <= '0'; dma_we_o <= '1'; -- Write only elsif rising_edge(dma_clk_i) then if (data_fifo_empty = '0' and dma_stall_i = '0' and ctrl_fifo_full = '0') then dma_stb_t <= '1'; data_fifo_rden <= '1'; else dma_stb_t <= '0'; data_fifo_rden <= '0'; end if; if (data_fifo_empty = '0' or dma_ack_cnt > 0) then dma_cyc_o <= '1'; else dma_cyc_o <= '0'; end if; dma_adr_o <= std_logic_vector(dma_adr_cnt); dma_dat_o <= data_fifo_dout; dma_stb_o <= dma_stb_t and not data_fifo_empty; dma_we_o <= '1'; -- Write only end if; end process to_ddr_proc; adr_proc : process (dma_clk_i, rst_n_i) begin if (rst_n_i = '0') then ctrl_fifo_wren <= '0'; dma_adr_cnt <= (others => '0'); dma_start_adr <= (others => '0'); dma_data_cnt <= (others => '0'); dma_data_cnt_d <= (others => '0'); dma_timeout_cnt <= (others => '0'); ctrl_fifo_din(63 downto 0) <= (others => '0'); dma_ack_cnt <= (others => '0'); elsif rising_edge(dma_clk_i) then -- Address Counter if (dma_stb_valid = '1') then dma_adr_cnt <= dma_adr_cnt + 1; end if; if (dma_stb_valid = '1' and dma_ack_i = '0') then dma_ack_cnt <= dma_ack_cnt + 1; elsif (dma_stb_valid = '0' and dma_ack_i = '1' and dma_ack_cnt > 0) then dma_ack_cnt <= dma_ack_cnt - 1; end if; -- Package size counter -- Check if Fifo is full if (dma_stb_valid = '1' and dma_data_cnt >= c_PACKAGE_SIZE and ctrl_fifo_full = '0') then ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt); ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr); dma_start_adr <= dma_start_adr + c_PACKAGE_SIZE; dma_data_cnt <= TO_UNSIGNED(1, 32); ctrl_fifo_wren <= '1'; elsif (dma_stb_valid = '0' and dma_data_cnt >= c_PACKAGE_SIZE and ctrl_fifo_full = '0') then ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt); ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr); dma_start_adr <= dma_start_adr + c_PACKAGE_SIZE; dma_data_cnt <= TO_UNSIGNED(0, 32); ctrl_fifo_wren <= '1'; elsif (dma_stb_valid = '0' and dma_timeout_cnt >= c_TIMEOUT and dma_data_cnt > 0 and ctrl_fifo_full ='0') then ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt); ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr); dma_start_adr <= dma_start_adr + dma_data_cnt; dma_data_cnt <= TO_UNSIGNED(0, 32); ctrl_fifo_wren <= '1'; elsif (dma_stb_valid = '1') then dma_data_cnt <= dma_data_cnt + 1; ctrl_fifo_wren <= '0'; else ctrl_fifo_wren <= '0'; end if; dma_data_cnt_d <= dma_data_cnt; -- if (dma_data_cnt = 0 and ctrl_fifo_wren = '1') then -- New package -- ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_adr_cnt); -- elsif (dma_data_cnt = 1 and ctrl_fifo_wren = '1') then -- Flying take over -- ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_adr_cnt-1); -- end if; -- Timeout counter if (dma_data_cnt > 0 and data_fifo_empty = '1') then dma_timeout_cnt <= dma_timeout_cnt + 1; elsif (data_fifo_empty = '0') then dma_timeout_cnt <= TO_UNSIGNED(0, 32); end if; end if; end process adr_proc; -- Data Rate maeasurement data_rate_proc: process(sys_clk_i, rst_n_i) begin if (rst_n_i = '0') then data_rate_cnt <= (others => '0'); data_rate <= (others => '0'); time_cnt <= (others => '0'); time_pulse <= '0'; elsif rising_edge(sys_clk_i) then -- 1Hz pulser if (time_cnt = c_TIME_FRAME) then time_cnt <= (others => '0'); time_pulse <= '1'; else time_cnt <= time_cnt + 1; time_pulse <= '0'; end if; if (time_pulse = '1') then data_rate <= std_logic_vector(data_rate_cnt); data_rate_cnt <= (others => '0'); elsif (data_fifo_wren = '1') then data_rate_cnt <= data_rate_cnt + 1; end if; end if; end process data_rate_proc; -- Loopback delay delayproc : process (sys_clk_i, rst_n_i) begin if (rst_n_i = '0') then rx_data_local <= (others => '0'); rx_data_local_d <= (others => '0'); rx_valid_local_d <= '0'; elsif rising_edge(sys_clk_i) then rx_data_local_d <= wb_dat_i; rx_valid_local_d <= rx_valid_local; end if; end process; -- Trigger sync and count trig_sync : process (sys_clk_i, rst_n_i) begin if (rst_n_i = '0') then trig_pulse_d0 <= '0'; trig_pulse_d1 <= '0'; trig_pulse_pos <= '0'; trig_cnt <= (others => '0'); elsif rising_edge(sys_clk_i) then trig_pulse_d0 <= trig_pulse_i; trig_pulse_d1 <= trig_pulse_d0; if (trig_pulse_d0 = '1' and trig_pulse_d1 = '0') then trig_pulse_pos <= '1'; else trig_pulse_pos <= '0'; end if; if (trig_pulse_pos = '1') then trig_cnt <= trig_cnt + 1; end if; end if; end process trig_sync; cmp_rx_bridge_fifo : rx_bridge_fifo PORT MAP ( rst => not rst_n_i, wr_clk => sys_clk_i, rd_clk => dma_clk_i, din => data_fifo_din, wr_en => data_fifo_wren, rd_en => data_fifo_rden, prog_full_thresh => std_logic_vector(c_ALMOST_FULL_THRESHOLD), prog_empty_thresh => std_logic_vector(c_EMPTY_THRESHOLD), dout => data_fifo_dout, full => data_fifo_full, empty => data_fifo_empty_true, prog_full => data_fifo_almost_full, prog_empty => data_fifo_prog_empty ); cmp_rx_bridge_ctrl_fifo : rx_bridge_ctrl_fifo PORT MAP ( rst => not rst_n_i, wr_clk => dma_clk_i, rd_clk => sys_clk_i, din => ctrl_fifo_din, wr_en => ctrl_fifo_wren, rd_en => ctrl_fifo_rden, dout => ctrl_fifo_dout, full => ctrl_fifo_full, empty => ctrl_fifo_empty ); end Behavioral;
-- #################################### -- # Project: Yarr -- # Author: Timon Heim -- # E-Mail: timon.heim at cern.ch -- # Comments: Bridge between Rx core and Mem -- #################################### -- # Address Map: -- # 0x0000: Start Adr (RO) -- # 0x0001: Data Cnt (RO) -- # 0x0002[0]: Loopback (RW) -- # 0x0003: Data Rate (RO) -- # 0x0004: Loop Fifo (WO) library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity wb_rx_bridge is port ( -- Sys Connect sys_clk_i : in std_logic; rst_n_i : in std_logic; -- Wishbone slave interface wb_adr_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; wb_stall_o : out std_logic; -- Wishbone DMA Master Interface dma_clk_i : in std_logic; dma_adr_o : out std_logic_vector(31 downto 0); dma_dat_o : out std_logic_vector(31 downto 0); dma_dat_i : in std_logic_vector(31 downto 0); dma_cyc_o : out std_logic; dma_stb_o : out std_logic; dma_we_o : out std_logic; dma_ack_i : in std_logic; dma_stall_i : in std_logic; -- Rx Interface rx_data_i : in std_logic_vector(31 downto 0); rx_valid_i : in std_logic; -- Status In trig_pulse_i : in std_logic; -- Status out irq_o : out std_logic; busy_o : out std_logic ); end wb_rx_bridge; architecture Behavioral of wb_rx_bridge is -- Cmoponents COMPONENT rx_bridge_fifo PORT ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_full_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0); prog_empty_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC ); END COMPONENT; COMPONENT rx_bridge_ctrl_fifo PORT ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC ); END COMPONENT; -- Constants constant c_ALMOST_FULL_THRESHOLD : unsigned(10 downto 0) := TO_UNSIGNED(1900, 11); constant c_PACKAGE_SIZE : unsigned(31 downto 0) := TO_UNSIGNED((200*256), 32); -- 200kByte constant c_TIMEOUT : unsigned(31 downto 0) := TO_UNSIGNED(2**14, 32); -- Counts in 5ns = 0.1ms constant c_TIME_FRAME : unsigned(31 downto 0) := TO_UNSIGNED(200000000-1, 32); -- 200MHz clock cycles in 1 sec constant c_EMPTY_THRESHOLD : unsigned(10 downto 0) := TO_UNSIGNED(16, 11); constant c_EMPTY_TIMEOUT : unsigned(10 downto 0) := TO_UNSIGNED(2000, 11); -- Signals signal data_fifo_din : std_logic_vector(31 downto 0); signal data_fifo_dout : std_logic_vector(31 downto 0); signal data_fifo_wren : std_logic; signal data_fifo_rden : std_logic; signal data_fifo_full : std_logic; signal data_fifo_empty : std_logic; signal data_fifo_almost_full : std_logic; signal data_fifo_prog_empty : std_logic; signal data_fifo_empty_cnt : unsigned(10 downto 0); signal data_fifo_empty_true : std_logic; signal data_fifo_empty_pressure : std_logic; signal ctrl_fifo_din : std_logic_vector(63 downto 0); signal ctrl_fifo_dout : std_logic_vector(63 downto 0); signal ctrl_fifo_wren : std_logic; signal ctrl_fifo_rden : std_logic; signal ctrl_fifo_full : std_logic; signal ctrl_fifo_empty : std_logic; signal dma_stb_t : std_logic; signal dma_stb_valid : std_logic; signal dma_adr_cnt : unsigned(31 downto 0); signal dma_start_adr : unsigned(31 downto 0); signal dma_data_cnt : unsigned(31 downto 0); signal dma_data_cnt_d : unsigned(31 downto 0); signal dma_timeout_cnt : unsigned(31 downto 0); signal dma_ack_cnt : unsigned(7 downto 0); signal rx_data_local : std_logic_vector(31 downto 0); signal rx_valid_local : std_logic; signal rx_data_local_d : std_logic_vector(31 downto 0); signal rx_valid_local_d : std_logic; signal ctrl_fifo_dout_tmp : std_logic_vector(31 downto 0); signal time_cnt : unsigned(31 downto 0); signal time_pulse : std_logic; signal data_rate_cnt : unsigned(31 downto 0); signal trig_cnt : unsigned(31 downto 0); signal trig_pulse_d0 : std_logic; signal trig_pulse_d1 : std_logic; signal trig_pulse_pos : std_logic; -- Registers signal loopback : std_logic; signal data_rate : std_logic_vector(31 downto 0); begin --Tie offs irq_o <= '0'; busy_o <= data_fifo_full; -- Wishbone Slave wb_slave_proc: process(sys_clk_i, rst_n_i) begin if (rst_n_i = '0') then wb_dat_o <= (others => '0'); wb_ack_o <= '0'; wb_stall_o <= '0'; ctrl_fifo_rden <= '0'; rx_valid_local <= '0'; ctrl_fifo_dout_tmp <= (others => '0'); -- Regs loopback <= '0'; elsif rising_edge(sys_clk_i) then -- Default wb_ack_o <= '0'; ctrl_fifo_rden <= '0'; wb_stall_o <= '0'; rx_valid_local <= '0'; if (wb_cyc_i = '1' and wb_stb_i = '1') then if (wb_we_i = '0') then -- READ if (wb_adr_i(3 downto 0) = x"0") then -- Start Addr if (ctrl_fifo_empty = '0') then wb_dat_o <= ctrl_fifo_dout(31 downto 0); ctrl_fifo_dout_tmp <= ctrl_fifo_dout(63 downto 32); wb_ack_o <= '1'; ctrl_fifo_rden <= '1'; else wb_dat_o <= x"FFFFFFFF"; ctrl_fifo_dout_tmp <= (others => '0'); wb_ack_o <= '1'; ctrl_fifo_rden <= '0'; end if; elsif (wb_adr_i(3 downto 0) = x"1") then -- Count wb_dat_o <= ctrl_fifo_dout_tmp; wb_ack_o <= '1'; elsif (wb_adr_i(3 downto 0) = x"2") then -- Loopback wb_dat_o(31 downto 1) <= (others => '0'); wb_dat_o(0) <= loopback; wb_ack_o <= '1'; elsif (wb_adr_i(3 downto 0) = x"3") then -- Data Rate wb_dat_o <= data_rate; wb_ack_o <= '1'; elsif (wb_adr_i(3 downto 0) = x"5") then -- Bridge Empty wb_dat_o(31 downto 1) <= (others => '0'); wb_dat_o(0) <= data_fifo_empty_true; wb_ack_o <= '1'; elsif (wb_adr_i(3 downto 0) = x"6") then -- Cur Count wb_dat_o <= std_logic_vector(dma_data_cnt_d); wb_ack_o <= '1'; else wb_dat_o <= x"DEADBEEF"; wb_ack_o <= '1'; end if; else -- WRITE wb_ack_o <= '1'; if (wb_adr_i(3 downto 0) = x"2") then loopback <= wb_dat_i(0); elsif (wb_adr_i(3 downto 0) = x"4") then rx_valid_local <= '1'; end if; end if; end if; end if; end process wb_slave_proc; -- Data from Rx data_rec : process (sys_clk_i, rst_n_i) begin if (rst_n_i <= '0') then data_fifo_wren <= '0'; data_fifo_din <= (others => '0'); elsif rising_edge(sys_clk_i) then if (loopback = '1') then data_fifo_wren <= rx_valid_local_d; data_fifo_din <= rx_data_local_d; else data_fifo_wren <= rx_valid_i; data_fifo_din <= rx_data_i; end if; end if; end process data_rec; -- Empty logic to produce some backpressure data_fifo_empty <= '1' when (data_fifo_empty_true = '1') else data_fifo_empty_pressure; empty_proc : process(dma_clk_i, rst_n_i) begin if (rst_n_i = '0') then data_fifo_empty_pressure <= '0'; data_fifo_empty_cnt <= (others => '0'); elsif rising_edge(dma_clk_i) then -- Timeout Counter if (data_fifo_empty_true = '0' and data_fifo_empty_pressure = '1') then data_fifo_empty_cnt <= data_fifo_empty_cnt + 1; elsif (data_fifo_empty_true = '1') then data_fifo_empty_cnt <= (others => '0'); end if; if (data_fifo_empty_cnt > c_EMPTY_TIMEOUT) then data_fifo_empty_pressure <= '0'; elsif (data_fifo_prog_empty = '0') then data_fifo_empty_pressure <= '0'; elsif (data_fifo_empty_true = '1') then data_fifo_empty_pressure <= '1'; end if; end if; end process empty_proc; -- DMA Master and data control dma_stb_valid <= dma_stb_t and not data_fifo_empty; to_ddr_proc: process(dma_clk_i, rst_n_i) begin if(rst_n_i = '0') then dma_stb_t <= '0'; data_fifo_rden <= '0'; dma_adr_o <= (others => '0'); dma_dat_o <= (others => '0'); dma_cyc_o <= '0'; dma_stb_o <= '0'; dma_we_o <= '1'; -- Write only elsif rising_edge(dma_clk_i) then if (data_fifo_empty = '0' and dma_stall_i = '0' and ctrl_fifo_full = '0') then dma_stb_t <= '1'; data_fifo_rden <= '1'; else dma_stb_t <= '0'; data_fifo_rden <= '0'; end if; if (data_fifo_empty = '0' or dma_ack_cnt > 0) then dma_cyc_o <= '1'; else dma_cyc_o <= '0'; end if; dma_adr_o <= std_logic_vector(dma_adr_cnt); dma_dat_o <= data_fifo_dout; dma_stb_o <= dma_stb_t and not data_fifo_empty; dma_we_o <= '1'; -- Write only end if; end process to_ddr_proc; adr_proc : process (dma_clk_i, rst_n_i) begin if (rst_n_i = '0') then ctrl_fifo_wren <= '0'; dma_adr_cnt <= (others => '0'); dma_start_adr <= (others => '0'); dma_data_cnt <= (others => '0'); dma_data_cnt_d <= (others => '0'); dma_timeout_cnt <= (others => '0'); ctrl_fifo_din(63 downto 0) <= (others => '0'); dma_ack_cnt <= (others => '0'); elsif rising_edge(dma_clk_i) then -- Address Counter if (dma_stb_valid = '1') then dma_adr_cnt <= dma_adr_cnt + 1; end if; if (dma_stb_valid = '1' and dma_ack_i = '0') then dma_ack_cnt <= dma_ack_cnt + 1; elsif (dma_stb_valid = '0' and dma_ack_i = '1' and dma_ack_cnt > 0) then dma_ack_cnt <= dma_ack_cnt - 1; end if; -- Package size counter -- Check if Fifo is full if (dma_stb_valid = '1' and dma_data_cnt >= c_PACKAGE_SIZE and ctrl_fifo_full = '0') then ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt); ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr); dma_start_adr <= dma_start_adr + c_PACKAGE_SIZE; dma_data_cnt <= TO_UNSIGNED(1, 32); ctrl_fifo_wren <= '1'; elsif (dma_stb_valid = '0' and dma_data_cnt >= c_PACKAGE_SIZE and ctrl_fifo_full = '0') then ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt); ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr); dma_start_adr <= dma_start_adr + c_PACKAGE_SIZE; dma_data_cnt <= TO_UNSIGNED(0, 32); ctrl_fifo_wren <= '1'; elsif (dma_stb_valid = '0' and dma_timeout_cnt >= c_TIMEOUT and dma_data_cnt > 0 and ctrl_fifo_full ='0') then ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt); ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr); dma_start_adr <= dma_start_adr + dma_data_cnt; dma_data_cnt <= TO_UNSIGNED(0, 32); ctrl_fifo_wren <= '1'; elsif (dma_stb_valid = '1') then dma_data_cnt <= dma_data_cnt + 1; ctrl_fifo_wren <= '0'; else ctrl_fifo_wren <= '0'; end if; dma_data_cnt_d <= dma_data_cnt; -- if (dma_data_cnt = 0 and ctrl_fifo_wren = '1') then -- New package -- ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_adr_cnt); -- elsif (dma_data_cnt = 1 and ctrl_fifo_wren = '1') then -- Flying take over -- ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_adr_cnt-1); -- end if; -- Timeout counter if (dma_data_cnt > 0 and data_fifo_empty = '1') then dma_timeout_cnt <= dma_timeout_cnt + 1; elsif (data_fifo_empty = '0') then dma_timeout_cnt <= TO_UNSIGNED(0, 32); end if; end if; end process adr_proc; -- Data Rate maeasurement data_rate_proc: process(sys_clk_i, rst_n_i) begin if (rst_n_i = '0') then data_rate_cnt <= (others => '0'); data_rate <= (others => '0'); time_cnt <= (others => '0'); time_pulse <= '0'; elsif rising_edge(sys_clk_i) then -- 1Hz pulser if (time_cnt = c_TIME_FRAME) then time_cnt <= (others => '0'); time_pulse <= '1'; else time_cnt <= time_cnt + 1; time_pulse <= '0'; end if; if (time_pulse = '1') then data_rate <= std_logic_vector(data_rate_cnt); data_rate_cnt <= (others => '0'); elsif (data_fifo_wren = '1') then data_rate_cnt <= data_rate_cnt + 1; end if; end if; end process data_rate_proc; -- Loopback delay delayproc : process (sys_clk_i, rst_n_i) begin if (rst_n_i = '0') then rx_data_local <= (others => '0'); rx_data_local_d <= (others => '0'); rx_valid_local_d <= '0'; elsif rising_edge(sys_clk_i) then rx_data_local_d <= wb_dat_i; rx_valid_local_d <= rx_valid_local; end if; end process; -- Trigger sync and count trig_sync : process (sys_clk_i, rst_n_i) begin if (rst_n_i = '0') then trig_pulse_d0 <= '0'; trig_pulse_d1 <= '0'; trig_pulse_pos <= '0'; trig_cnt <= (others => '0'); elsif rising_edge(sys_clk_i) then trig_pulse_d0 <= trig_pulse_i; trig_pulse_d1 <= trig_pulse_d0; if (trig_pulse_d0 = '1' and trig_pulse_d1 = '0') then trig_pulse_pos <= '1'; else trig_pulse_pos <= '0'; end if; if (trig_pulse_pos = '1') then trig_cnt <= trig_cnt + 1; end if; end if; end process trig_sync; cmp_rx_bridge_fifo : rx_bridge_fifo PORT MAP ( rst => not rst_n_i, wr_clk => sys_clk_i, rd_clk => dma_clk_i, din => data_fifo_din, wr_en => data_fifo_wren, rd_en => data_fifo_rden, prog_full_thresh => std_logic_vector(c_ALMOST_FULL_THRESHOLD), prog_empty_thresh => std_logic_vector(c_EMPTY_THRESHOLD), dout => data_fifo_dout, full => data_fifo_full, empty => data_fifo_empty_true, prog_full => data_fifo_almost_full, prog_empty => data_fifo_prog_empty ); cmp_rx_bridge_ctrl_fifo : rx_bridge_ctrl_fifo PORT MAP ( rst => not rst_n_i, wr_clk => dma_clk_i, rd_clk => sys_clk_i, din => ctrl_fifo_din, wr_en => ctrl_fifo_wren, rd_en => ctrl_fifo_rden, dout => ctrl_fifo_dout, full => ctrl_fifo_full, empty => ctrl_fifo_empty ); end Behavioral;
architecture RTL of FIFO is begin FOR_LABEL : for i in 0 to 7 generate signal sig1 : std_logic; constant con1 : std_logic; shared variable var1 : std_logic; alias a is name; alias a : subtype_indication is name; begin end generate; IF_LABEL : if a = '1' generate signal sig1 : std_logic; constant con1 : std_logic; shared variable var1 : std_logic; alias a is name; alias a : subtype_indication is name; begin end generate; CASE_LABEL : case data generate when a = 1 => signal sig1 : std_logic; constant con1 : std_logic; shared variable var1 : std_logic; alias a is name; alias a : subtype_indication is name; begin end generate; -- Violations below FOR_LABEL : for i in 0 to 7 generate signal sig1 : std_logic; constant con1 : std_logic; shared variable var1 : std_logic; alias a is name; alias a : subtype_indication is name; begin end generate; IF_LABEL : if a = '1' generate signal sig1 : std_logic; constant con1 : std_logic; shared variable var1 : std_logic; alias a is name; alias a : subtype_indication is name; begin end generate; CASE_LABEL : case data generate when a = 1 => signal sig1 : std_logic; constant con1 : std_logic; shared variable var1 : std_logic; alias a is name; alias a : subtype_indication is name; begin end generate; end;
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016 -- Date : Thu Sep 28 09:34:25 2017 -- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_stub.vhdl -- Design : fifo_generator_rx_inst -- Purpose : Stub declaration of top-level module interface -- Device : xc7k325tffg676-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 63 downto 0 ); wr_en : in STD_LOGIC; rd_en : in STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 63 downto 0 ); full : out STD_LOGIC; empty : out STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "clk,rst,din[63:0],wr_en,rd_en,dout[63:0],full,empty"; attribute x_core_info : string; attribute x_core_info of stub : architecture is "fifo_generator_v13_1_2,Vivado 2016.3"; begin end;
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Patrick Lehmann -- -- Module: A generic buffer module for the PoC.Stream protocol. -- -- Description: -- ------------------------------------ -- This module implements a generic buffer (FifO) for the PoC.Stream protocol. -- It is generic in DATA_BITS and in META_BITS as well as in FifO depths for -- data and meta information. -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library PoC; use PoC.config.all; use PoC.utils.all; use PoC.vectors.all; entity Stream_Mirror is generic ( portS : POSITIVE := 2; DATA_BITS : POSITIVE := 8; META_BITS : T_POSVEC := (0 => 8); META_LENGTH : T_POSVEC := (0 => 16) ); port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; In_Valid : in STD_LOGIC; In_Data : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); In_SOF : in STD_LOGIC; In_EOF : in STD_LOGIC; In_Ack : out STD_LOGIC; In_Meta_rst : out STD_LOGIC; In_Meta_nxt : out STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0); In_Meta_Data : in STD_LOGIC_VECTOR(isum(META_BITS) - 1 downto 0); Out_Valid : out STD_LOGIC_VECTOR(portS - 1 downto 0); Out_Data : out T_SLM(portS - 1 downto 0, DATA_BITS - 1 downto 0); Out_SOF : out STD_LOGIC_VECTOR(portS - 1 downto 0); Out_EOF : out STD_LOGIC_VECTOR(portS - 1 downto 0); Out_Ack : in STD_LOGIC_VECTOR(portS - 1 downto 0); Out_Meta_rst : in STD_LOGIC_VECTOR(portS - 1 downto 0); Out_Meta_nxt : in T_SLM(portS - 1 downto 0, META_BITS'length - 1 downto 0); Out_Meta_Data : out T_SLM(portS - 1 downto 0, isum(META_BITS) - 1 downto 0) ); end; architecture rtl of Stream_Mirror is attribute KEEP : BOOLEAN; attribute FSM_ENCODING : STRING; signal FifOGlue_put : STD_LOGIC; signal FifOGlue_DataIn : STD_LOGIC_VECTOR(DATA_BITS + 1 downto 0); signal FifOGlue_Full : STD_LOGIC; signal FifOGlue_Valid : STD_LOGIC; signal FifOGlue_DataOut : STD_LOGIC_VECTOR(DATA_BITS + 1 downto 0); signal FifOGlue_got : STD_LOGIC; signal Ack_i : STD_LOGIC; signal Mask_r : STD_LOGIC_VECTOR(portS - 1 downto 0) := (others => '1'); signal MetaOut_rst : STD_LOGIC_VECTOR(portS - 1 downto 0); signal Out_Data_i : T_SLM(portS - 1 downto 0, DATA_BITS - 1 downto 0) := (others => (others => 'Z')); signal Out_Meta_Data_i : T_SLM(portS - 1 downto 0, isum(META_BITS) - 1 downto 0) := (others => (others => 'Z')); begin -- Data path -- ========================================================================================================================================================== FifOGlue_put <= In_Valid; FifOGlue_DataIn(DATA_BITS - 1 downto 0) <= In_Data; FifOGlue_DataIn(DATA_BITS + 0) <= In_SOF; FifOGlue_DataIn(DATA_BITS + 1) <= In_EOF; In_Ack <= not FifOGlue_Full; FifOGlue : entity PoC.fifo_glue generic map ( D_BITS => DATA_BITS + 2 -- Data Width ) port map ( -- Control clk => Clock, -- Clock rst => Reset, -- Synchronous Reset -- Input put => FifOGlue_put, -- Put Value di => FifOGlue_DataIn, -- Data Input ful => FifOGlue_Full, -- Full -- Output vld => FifOGlue_Valid, -- Data Available do => FifOGlue_DataOut, -- Data Output got => FifOGlue_got -- Data Consumed ); genPorts : for i in 0 to portS - 1 generate assign_row(Out_Data_i, FifOGlue_DataOut(DATA_BITS - 1 downto 0), i); end generate; Ack_i <= slv_and(Out_Ack) or slv_and(not Mask_r or Out_Ack); FifOGlue_got <= Ack_i ; Out_Valid <= (portS - 1 downto 0 => FifOGlue_Valid) and Mask_r; Out_Data <= Out_Data_i; Out_SOF <= (portS - 1 downto 0 => FifOGlue_DataOut(DATA_BITS + 0)); Out_EOF <= (portS - 1 downto 0 => FifOGlue_DataOut(DATA_BITS + 1)); process(Clock) begin if rising_edge(Clock) then if ((Reset or Ack_i ) = '1') then Mask_r <= (others => '1'); else Mask_r <= Mask_r and not Out_Ack; end if; end if; end process; -- Metadata path -- ========================================================================================================================================================== In_Meta_rst <= slv_and(MetaOut_rst); genMeta : for i in 0 to META_BITS'length - 1 generate subtype T_METAMEMORY is STD_LOGIC_VECTOR(META_BITS(i) - 1 downto 0); type T_METAMEMORY_VECTOR is array(NATURAL range <>) of T_METAMEMORY; begin genReg : if (META_LENGTH(i) = 1) generate signal MetaMemory_en : STD_LOGIC; signal MetaMemory : T_METAMEMORY; begin MetaMemory_en <= In_Valid and In_SOF; process(Clock) begin if rising_edge(Clock) then if (MetaMemory_en = '1') then MetaMemory <= In_Meta_Data(high(META_BITS, I) downto low(META_BITS, I)); end if; end if; end process; genReader : FOR J IN 0 to portS - 1 generate assign_row(Out_Meta_Data_i, MetaMemory, J, high(META_BITS, I), low(META_BITS, I)); end generate; end generate; genMem : if (META_LENGTH(i) > 1) generate signal MetaMemory_en : STD_LOGIC; signal MetaMemory : T_METAMEMORY_VECTOR(META_LENGTH(i) - 1 downto 0); signal Writer_CounterControl : STD_LOGIC := '0'; signal Writer_en : STD_LOGIC; signal Writer_rst : STD_LOGIC; signal Writer_us : UNSIGNED(log2ceilnz(META_LENGTH(i)) - 1 downto 0) := (others => '0'); begin -- MetaMemory Write Pointer Control process(Clock) begin if rising_edge(Clock) then if (Reset = '1') then Writer_CounterControl <= '0'; else if ((In_Valid and In_SOF) = '1') then Writer_CounterControl <= '1'; ELSif (Writer_us = (META_LENGTH(i) - 1)) then Writer_CounterControl <= '0'; end if; end if; end if; end process; Writer_en <= (In_Valid and In_SOF) or Writer_CounterControl; In_Meta_nxt(i) <= Writer_en; MetaMemory_en <= Writer_en; MetaOut_rst(i) <= NOT Writer_en; -- MetaMemory - Write Pointer process(Clock) begin if rising_edge(Clock) then if (Writer_en = '0') then Writer_us <= (others => '0'); else Writer_us <= Writer_us + 1; end if; end if; end process; -- MetaMemory process(Clock) begin if rising_edge(Clock) then if (MetaMemory_en = '1') then MetaMemory(to_integer(Writer_us)) <= In_Meta_Data(high(META_BITS, I) downto low(META_BITS, I)); end if; end if; end process; genReader : for j in 0 to portS - 1 generate signal Row : T_METAMEMORY; signal Reader_en : STD_LOGIC; signal Reader_rst : STD_LOGIC; signal Reader_us : UNSIGNED(log2ceilnz(META_LENGTH(i)) - 1 downto 0) := (others => '0'); begin Reader_rst <= Out_Meta_rst(j) or (In_Valid and In_SOF); Reader_en <= Out_Meta_nxt(j, I); process(Clock) begin if rising_edge(Clock) then if (Reader_rst = '1') then Reader_us <= (others => '0'); ELSif (Reader_en = '1') then Reader_us <= Reader_us + 1; end if; end if; end process; Row <= MetaMemory(to_integer(Reader_us)); assign_row(Out_Meta_Data_i, Row, j, high(META_BITS, i), low(META_BITS, i)); end generate; -- for each port end generate; -- if length > 1 end generate; -- for each metadata stream Out_Meta_Data <= Out_Meta_Data_i; end architecture;
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Patrick Lehmann -- -- Module: A generic buffer module for the PoC.Stream protocol. -- -- Description: -- ------------------------------------ -- This module implements a generic buffer (FifO) for the PoC.Stream protocol. -- It is generic in DATA_BITS and in META_BITS as well as in FifO depths for -- data and meta information. -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library PoC; use PoC.config.all; use PoC.utils.all; use PoC.vectors.all; entity Stream_Mirror is generic ( portS : POSITIVE := 2; DATA_BITS : POSITIVE := 8; META_BITS : T_POSVEC := (0 => 8); META_LENGTH : T_POSVEC := (0 => 16) ); port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; In_Valid : in STD_LOGIC; In_Data : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); In_SOF : in STD_LOGIC; In_EOF : in STD_LOGIC; In_Ack : out STD_LOGIC; In_Meta_rst : out STD_LOGIC; In_Meta_nxt : out STD_LOGIC_VECTOR(META_BITS'length - 1 downto 0); In_Meta_Data : in STD_LOGIC_VECTOR(isum(META_BITS) - 1 downto 0); Out_Valid : out STD_LOGIC_VECTOR(portS - 1 downto 0); Out_Data : out T_SLM(portS - 1 downto 0, DATA_BITS - 1 downto 0); Out_SOF : out STD_LOGIC_VECTOR(portS - 1 downto 0); Out_EOF : out STD_LOGIC_VECTOR(portS - 1 downto 0); Out_Ack : in STD_LOGIC_VECTOR(portS - 1 downto 0); Out_Meta_rst : in STD_LOGIC_VECTOR(portS - 1 downto 0); Out_Meta_nxt : in T_SLM(portS - 1 downto 0, META_BITS'length - 1 downto 0); Out_Meta_Data : out T_SLM(portS - 1 downto 0, isum(META_BITS) - 1 downto 0) ); end; architecture rtl of Stream_Mirror is attribute KEEP : BOOLEAN; attribute FSM_ENCODING : STRING; signal FifOGlue_put : STD_LOGIC; signal FifOGlue_DataIn : STD_LOGIC_VECTOR(DATA_BITS + 1 downto 0); signal FifOGlue_Full : STD_LOGIC; signal FifOGlue_Valid : STD_LOGIC; signal FifOGlue_DataOut : STD_LOGIC_VECTOR(DATA_BITS + 1 downto 0); signal FifOGlue_got : STD_LOGIC; signal Ack_i : STD_LOGIC; signal Mask_r : STD_LOGIC_VECTOR(portS - 1 downto 0) := (others => '1'); signal MetaOut_rst : STD_LOGIC_VECTOR(portS - 1 downto 0); signal Out_Data_i : T_SLM(portS - 1 downto 0, DATA_BITS - 1 downto 0) := (others => (others => 'Z')); signal Out_Meta_Data_i : T_SLM(portS - 1 downto 0, isum(META_BITS) - 1 downto 0) := (others => (others => 'Z')); begin -- Data path -- ========================================================================================================================================================== FifOGlue_put <= In_Valid; FifOGlue_DataIn(DATA_BITS - 1 downto 0) <= In_Data; FifOGlue_DataIn(DATA_BITS + 0) <= In_SOF; FifOGlue_DataIn(DATA_BITS + 1) <= In_EOF; In_Ack <= not FifOGlue_Full; FifOGlue : entity PoC.fifo_glue generic map ( D_BITS => DATA_BITS + 2 -- Data Width ) port map ( -- Control clk => Clock, -- Clock rst => Reset, -- Synchronous Reset -- Input put => FifOGlue_put, -- Put Value di => FifOGlue_DataIn, -- Data Input ful => FifOGlue_Full, -- Full -- Output vld => FifOGlue_Valid, -- Data Available do => FifOGlue_DataOut, -- Data Output got => FifOGlue_got -- Data Consumed ); genPorts : for i in 0 to portS - 1 generate assign_row(Out_Data_i, FifOGlue_DataOut(DATA_BITS - 1 downto 0), i); end generate; Ack_i <= slv_and(Out_Ack) or slv_and(not Mask_r or Out_Ack); FifOGlue_got <= Ack_i ; Out_Valid <= (portS - 1 downto 0 => FifOGlue_Valid) and Mask_r; Out_Data <= Out_Data_i; Out_SOF <= (portS - 1 downto 0 => FifOGlue_DataOut(DATA_BITS + 0)); Out_EOF <= (portS - 1 downto 0 => FifOGlue_DataOut(DATA_BITS + 1)); process(Clock) begin if rising_edge(Clock) then if ((Reset or Ack_i ) = '1') then Mask_r <= (others => '1'); else Mask_r <= Mask_r and not Out_Ack; end if; end if; end process; -- Metadata path -- ========================================================================================================================================================== In_Meta_rst <= slv_and(MetaOut_rst); genMeta : for i in 0 to META_BITS'length - 1 generate subtype T_METAMEMORY is STD_LOGIC_VECTOR(META_BITS(i) - 1 downto 0); type T_METAMEMORY_VECTOR is array(NATURAL range <>) of T_METAMEMORY; begin genReg : if (META_LENGTH(i) = 1) generate signal MetaMemory_en : STD_LOGIC; signal MetaMemory : T_METAMEMORY; begin MetaMemory_en <= In_Valid and In_SOF; process(Clock) begin if rising_edge(Clock) then if (MetaMemory_en = '1') then MetaMemory <= In_Meta_Data(high(META_BITS, I) downto low(META_BITS, I)); end if; end if; end process; genReader : FOR J IN 0 to portS - 1 generate assign_row(Out_Meta_Data_i, MetaMemory, J, high(META_BITS, I), low(META_BITS, I)); end generate; end generate; genMem : if (META_LENGTH(i) > 1) generate signal MetaMemory_en : STD_LOGIC; signal MetaMemory : T_METAMEMORY_VECTOR(META_LENGTH(i) - 1 downto 0); signal Writer_CounterControl : STD_LOGIC := '0'; signal Writer_en : STD_LOGIC; signal Writer_rst : STD_LOGIC; signal Writer_us : UNSIGNED(log2ceilnz(META_LENGTH(i)) - 1 downto 0) := (others => '0'); begin -- MetaMemory Write Pointer Control process(Clock) begin if rising_edge(Clock) then if (Reset = '1') then Writer_CounterControl <= '0'; else if ((In_Valid and In_SOF) = '1') then Writer_CounterControl <= '1'; ELSif (Writer_us = (META_LENGTH(i) - 1)) then Writer_CounterControl <= '0'; end if; end if; end if; end process; Writer_en <= (In_Valid and In_SOF) or Writer_CounterControl; In_Meta_nxt(i) <= Writer_en; MetaMemory_en <= Writer_en; MetaOut_rst(i) <= NOT Writer_en; -- MetaMemory - Write Pointer process(Clock) begin if rising_edge(Clock) then if (Writer_en = '0') then Writer_us <= (others => '0'); else Writer_us <= Writer_us + 1; end if; end if; end process; -- MetaMemory process(Clock) begin if rising_edge(Clock) then if (MetaMemory_en = '1') then MetaMemory(to_integer(Writer_us)) <= In_Meta_Data(high(META_BITS, I) downto low(META_BITS, I)); end if; end if; end process; genReader : for j in 0 to portS - 1 generate signal Row : T_METAMEMORY; signal Reader_en : STD_LOGIC; signal Reader_rst : STD_LOGIC; signal Reader_us : UNSIGNED(log2ceilnz(META_LENGTH(i)) - 1 downto 0) := (others => '0'); begin Reader_rst <= Out_Meta_rst(j) or (In_Valid and In_SOF); Reader_en <= Out_Meta_nxt(j, I); process(Clock) begin if rising_edge(Clock) then if (Reader_rst = '1') then Reader_us <= (others => '0'); ELSif (Reader_en = '1') then Reader_us <= Reader_us + 1; end if; end if; end process; Row <= MetaMemory(to_integer(Reader_us)); assign_row(Out_Meta_Data_i, Row, j, high(META_BITS, i), low(META_BITS, i)); end generate; -- for each port end generate; -- if length > 1 end generate; -- for each metadata stream Out_Meta_Data <= Out_Meta_Data_i; end architecture;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block ZKfhb/O/9O3VzkC+hly9Up//iISdFC8YLIu67vmyKlWgV1Pf8EzbRLDK3TSnns4WnXzXBxd6auT6 9kRLDkexZw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WNX0rESjuf4ZMUvrCSC442STmckkuzY2Klwe6dQiJgprXrNJ0TmsOIUVbjc3gtQ7JltCLHAWieTl JHgvpCg/08nNzlPvNWQe6G98wEobIfjdpn9K/mfVZxoWFB7gawr3PiJb1zpfctEy9K54h5WHIhE4 gXqgNeo3abi4A/4Xgso= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block DOffJFs0Jb92js0LY37MWmwF8XoLxqZXl8s3/t/XXbU24Iz/NQfN1cselANiDjz5Gqm27Mhhgbs6 hMJB0FopfxaPHG0vlYbJuKBda4zTe7HPvrzKloNyea4MmBFXq/NDNwGSCJHTlx7X8d9gThLFvnKi talWtBae3ueX8DTMTSGGQFmmX3lOAJY+qkgYLIY/LMwxqzu0HxmcyM27QmIYvmpaE4pQlK3e3gnW i5Ny6TsJxccVPDKz4evshrZvUeNF0rAU1sZ9MsqP1Q1Zs8ewF81KJtWifMbHw9ZY5N7WBFbO5ayb EsQDrzhzQwX2H8OCFlgml84eOCkkpaD4qA4teQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 04xaq6kclgwCilULQ5P2I+3QCSL6jg4h7DZx6pOJu6WqEQtFEz6X5LSPDQzySC6sJPks+240TbWr 3Wx3VUGXtRrf6BX8b2IEAlXrcxTzSkV0XcK9D6LhHcytJKbM/KPJRADFFg46Yzgic4cpu6njUZhI Bx2KebSgh81iqZ5YNuA= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ln38ZB6MqP3Rw5EV5/o985jWb+3b+f4xlalBLdtOi3ayMCsvWXNzL41f4TFJaIzsZkGl1OsSRm/6 vH/XzAmjIN21G80/uLwsz3zDvDYG13rGz7+ddwKWRQ0gpexUr1lviD2yUFaZzZaTYfUR/lKbdzNB oT7/qFq5aH8RNIIegATwhv9ZbDbeGavhyEGGDR5PEDZzyXb+ZXYvWkGnI841KV7JmsWK0sGPrCRI fJwvqoreG85m4uZsoSdZTNg0mx31LaJYp0r81mqVNHhUo4J8JOilF9PssM5gKsZoQqAg3e9/wgn6 7/wvS6whjyDN04qKJ9ST+IixdBQZ4cHz+BB+yg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 280736) `protect data_block 0wtkqiMjuv1uhsO001olhMN7bXgjJp9mkIXLO3CJJXP9/TU3wMWhIVFG1quPtW4Ah4/bVsUZakH+ 9nVKwtrcPAp/hNHZ+tzRb0SYylVi0ftP2Txzb9DyTkV/sjt7/Ue4zJOy9BjR0ecdD95t9NgAhk58 bWe35TDnenNpBSh4SU7cq+tEYrZw68w1bNQacAe3tt/6X/iY6DGZOdYdE7ZlBSVmiqF9bQyYqPHu gTqTgBnnlbdoGtRO4+Mn17DEeIkeFPEnVPdW1QawB5T5dwwb9M1E2DyCtgRosfZotlWVD38YGhS0 ypd485Haf8GtZa/zawdU2xQBBRq7L5627n4fwyFcV/bRBLdjmwkgydzmW0hwpUc/E80D4s6MLuLq QKjaKqhetz0jQ2ltjtDfaEtoK8pRzPuGsvRbge3kEad4ewsEQ2suPapY4JZhCH4JrXCY/RDroSb1 N79NYt+7M50wLrmcNxWjmyWU3TYQ84ceNw7dFQCd4dfP36XR5QWKs3kcmOqXN2N9sSakXmsY5JGd xvzUH+gwNOjj0QDDL/XfjTN9BY9mCvu5Mq+YpCnI0MQXaEjOEfJwviBrDZh1zkSL7m+GhRcVAER6 3vpKLChMUb36YwjqxJqjFwKgwBQBwrSRIVVivU2JGRVQGSyK54vpfoYD6W0zwKUiPFl8Swy4ZD1O GM/B/rsPHL9Ic/bTIPj5D/YbZ1FPQBMVyVy9xexyZ9LHLjDi3hcbJspNhtIdfNkLmNSkB/IvcHP0 kMdsPpPvvwDU79TFbbhJptBWAoCaqi+z/n+MXxSvUqQXlhKPt2VtlwiYKlB0+cKf6LkCFnhVKR67 dlyhZVhZtAR+2GKxkN2iGsxQSahnLmiDr0FZshvE1fQJoTMr1RW63/tIu1RPbnmh/bDTfzxodHLo 7DHzzhIeJSAKaLx1Os7LQFyfeSTVl4+VklQ7anY3dSZnbxuapGaJr9C//rD8/ddz1X+fZSbDsbMZ A89pug469w+1gsbA2o7T+4fc/HQxLvL5oBm6d0QmTk2tJu4txszSMWV2VZDWYd2RUsvLF+zUhaev 5IhI9yeLee4d4kTR8hfbegvpqr0HX7d9xRMClhDSrB4akaDy+c6QQbVxMxxOH6dIvscHOfj5Or90 rHkyztQ8nyztC1ZfTX1ieb+Ts/c/OXcR0fKGk/Unz1+bx6gr1ZPrKrQm9+uBGt4vOkhCLLZ3eo6L iAV6YE0qQxEO0nADG6fp5c8PIHAPG0VZZ88n6O7LoiHlxkWI1WEGNmdFO48hyyR9VVDmeeoHlxSt cJ7KOxMWRi6HB2pGqpETPqzRI0tgmTOMEx1Fw2HYEMNA2sRxdNkLHQo3crCQAhnZUPLKuJjq2fqm hgtEAvY3gX3WigYG8Bt7rkU8nRuxDZyHweXDQ/RiTBtKyWoQUdvq5vxqFAtTfQaCGakUlDVZt2oM g1JVTaILHuMRTufjExj7lNNsp1iFUQZ73fjQqMfjxExVBnbrJgTix+XhLS0sLlEr/Vg9VLRqsXiz eeqfzpjS0B1d3yYRMW8Y4Qg2J02IPvrgpRmLtezgvl6vwAu06fYt9kmW8g+8w1nf0dhJMm6px7qX XqGnllMuLWWuLvihQGJ6h0yaOi/5N6SZgmADCbPHSXpqghVr50p+LVX3C2/hgATwbzDm33/0kLoY dyktvVQDf+04IPF2WvyO/OGOij+7PBqwBWQtH0pJ5Ng6RBDHqCnVLoZA9PLKROYWekDhSYY4xEOM qFsx2JT3uoB/4CS2pRMusC/xbbCu6+6ylIPYqr4pTgC0C+XO52pzm+sGyhPQQaJFAUUMHIBZGqUo 1vn+//pvvicE6ctcyzM5fxjFQFcavyRiSl3Q+WT5CXJlVmy4ae8t7e/nQqlQXQIbj8xsL8p/vNen mKKQYrOA5vm5NXriVGeq8SMz9e+mvETG9DZ2dHZ0xB2Rw+UbDuFS8HBwTWC6DAzvyssPr37Imq/r Sv4fpydAqcPj8MRad5pdsVr9ZtAP/xNTUWT1e6mGFIYDfDwvnyd9Xv1xfuI8o4nciO9Zpj7FF888 l0k2PMuU4ZC3HOUqeUNr//tFKrSW7paRutnwr5vFu98WRa9J0NDVINrIhV7qGTpOsTaW70kGBPlW giX2DUD8a7btKMH0i0igakEeUNXHyBzrI4WWbYpy0N1waJup6fYNYPxqTlzvT18PpPL9r83ZUNMM gigvGj58dXfHD95dACbmhgCt6vjM6/sP8RcbloZH5CcE+8Nb234qH5dqn43ktsCt283Mi6qBmjAv l8pKHjblVBjdDUd1dowXcaFwjwhtwH7D8mvEFy//AEAq4xcun0QLd981yNEux8j04H8HX/XkC6Nw 5obuXBxr/skOCiQgFcl8UvZ4s7OAfqcg2Z6JahRS77bi4wfNbgG0S+iBnZ8yqrcvGcAAZpSc7kPJ a65EyXg6L83AAzteIMlse5DKB76sZlLUDlaXKDF9fcVr3lWwhnXEKuHGnOJ6luPnZa9KjAg/MxHD sNoS/zMQ6fpAdsecenZyiDJFkX0D11/ECoIOfzHa03Di7hwjfhRaMmYaFsliZPsuteQ5VQO8oZFJ atW5LS/M7L24cO51WDnkMojHO8ShJDj/FfBktQNiULuZfG/3X1IYH1UTGkFEfdpynRa6FR8wFjKK WBFxK3PyWhP5zzlFQMImM7FvJaEhyN9bugGm80JCSPbOxnYYxscqj7FTxE6TWUUpuffdLYSK//Lz 7GzcOD1bFbJPGxr7VLNM/E/oU3z6J6y2izNHUzeK4uDs0LSLMQ/umEc2P8mxO6swVUJ/GILyA4N1 eNcJGrZeY1zDAtWMehP4MMvAwxcsbhZRxxg04yV71DxjFygL5kcie5w4K/mMfZ4pFsEOUXz3SuST 0FZ4owzAIRF+mxSQigcBTr0lhqB8omIrrLHuioWiTPlBkQ2iUcp8y7iDWT/7sjiat1a21ZcLlLCq FbbZbvJ/P6FoTHIlywmV28tfJ3anyiJKw2VUaDOB+UIvKrWHWXoukvgQj97mNdpb4pzkX84/Mo+9 v4QwCCW6D892Q3O/xzZELlLMsrDjTWa3U3c/nrPV/cEl70Xk3hfXmp53aNuLg6xiy8LXK9IUamIM a/qNtw4prpidlAhVrj3uAbelhuZYVnMmzB/2wIG/13fFNd22XEgxU67oXqoIb9icxqhVCTEhUJ3r dMVVNKPZhgsEvt7F3p15v1SIW6gkQk7dQBslzMe9D979O2K6AqUUBXk6yq6uK9OyqlMpq59xNkNG 7zhV+a4TXwCDlm30tg61YWewY7tdM0ShbMk2UeaKI/KkRCeFOXUERv0u0g1OvWrQi2vRfbmX6or5 TCUmQI9ksnhfJqoWoTD4HKoq8FkYAfX26zbX9GxgpTk24woU0O1iXyVOb1h93WkNg3xJAnJ6lG8U p6sD9UIjXBj9JECQqWaHLTBNo/BsZhI04rmTRWrN4MSGbvUiKdaQY0Po2/rWvf/HueERH11kw9ML b4oglitZxxUR5pLFAxxuAwKDIxDzWLE4+BwLxSnIo6PXAQAz/yYXVf+AyxE/gbIwdEDcs+/fa5WK kc8mMVEfVt3CMf9+wBU58GCtfUI4Axg/UXzAjlnunM71b0u2FOjSumID4d9QSym81lqmluZE8J8z ejlIgb1axStGjhnQtQmG/mak5c/hP1US5PVrH9nVrxy9ocQKXO5cLbXUyILFaHweoSfEMMV+TPR0 JmuZax0Nxj8yiM8hbvTSEgEGjJGaCxBCv9lXtA9KRJ8+HuOvdjPimUvET4fvC2GJOL3tr8TqK+Sn 3ZXuXiIF8qcThtzBYH1/laE+M+jmKqWGBzUAxdcqEAFf+hhOMY7fk7E7L/VfrBHkQe+TSGQKKNgH 5NQQJNjzErXF1uX7ExbUC6hqSm5+cxgBMHMplUv+xl9XY2rt+NhvFrfqZMk1UInfBKgt5v5RmBQV V1Ga4cgAD94wxjoGeToKfGLj+b9Xe1AlWrYjrsjeh8PfXIrQaDyvbqK7ke82TTX53AxLJrVochUU LwPWfSvZCdN6ShjohfspIzMjTuok4Wy0S9BeQx356qChxU1sZGuQ+DAO6fecUjXuXRrPM2pj122y LLJP+dxlxA0yAgRUH4Q5mnj0tsinkCtzH2MCo+uqxRycZv2BRs68ClFWDTi3iSmZ8LyOGX6CDCDs IA6g2VO2C2Uv6FxsGrAy+uyiajnQcp+eH/RSly2NPtc/iHAQqjiRpwAX9NslRIrgIc336U5G+kci SwZHnVoGxgFP9+7am7yZJ5B8Y1uAeQMrSyZOlVSY5iHMHWGIHpYo80hzI9fpTK4rlLf5IZziWBqM V/mERx4/WBTgJuoUX7YcZ4LSOxYlNCgezla82bRZ9kIe5ebh1s9DV/GfNbQ7u4hL5hvC8MLVZ89Y kkjw/28B2+veeYAQElNRx1ka08PA8ZjgKrPecFJGFyNwltMXNztPK5+tepHbSNF+T2OS4aeJilc8 9Y4CyITuRzvqGp8CxuAZSjfSq8Kp5Esz9RJwsziO/0bkdaWemoWnkbYfCh0/GlmQP3l6tREna0hb 3t1XnLwRoPYEfRGKiD73hez8CFUMpeI9BiF4HlknGNlhqLRbPteRPKD7J4u4rVBEgtaG/mAAhY2W HMOY4VB7u8qHmRtS4ZNqJVOcNbx5evtKkDuqhv2xBhPw3Te6Md9PCh2zfyg0jO5TbG+eibbZLBvL UQFP8vz6yZYg4aFfw1aBRRq3gtMDrlUjRgXJ6weygioZnPpEE01xi9O8xledd5DhTAW6dhlXQLsY X0NDL19c0MkfJYF2IaywGfr4ctYcuYMqhO+B0ZLcFz6d1B0RcjJEjxZIHYETMUbgH2n7L0YOWZeg oLplevntrD7qDfDC91zXmrymJhkxBSzgti538kkoyvgNt8Ner1MhaS5ab3suWAgrSPsv5ckn9tLK Mt/SbekadIixSMVWTDhAPBW1hFnnkcp8DXSgxD4tJmXFpeAFZmgqieBqMVw9YQSi4bNj9jB6dkv1 eDT6yLavtJsR4uSDpYRX1P3GMolxJNGKbaW8lD67tps9eNoOOHNDzUMN4PO08ETJDbbeZfWobLvb RaGgGGvXBn/rCJ8Dpy8nGME1JIYfa91+IAC3ipGrottWb6HK12988WqlvuKABNL3grpU889i9ku4 I+54K8Gg/SeQQVGcJZDrFr7XatMZbXKOj0IOblDYL6aL5nmdSsVnHqGDgZ2cPViRJbbfib4f5Br/ Zzv71md3qswPusROPiQfYTAejUE5/q4PtoGNpt7jWWFs6bkwSfjk5E/JfI7nvNKMJphJoKMRu5aB DS76a+wXeLRj23F4Nbiu+pYFcdemUZ8WMnVCnX1gDjl6TNSldbcLaz4LaQde5Nrp1Efnrp8EuIdQ pVvjAtRnzFj4rzZLKJ4rrMV0h7PkIjHf18K4Vh7puXGc6OFAi2sH41Kx0QesswwgbqAyIvCERv/K 6n0GbLIl1hrqk9/ltLf9CknNHaYodov6mGML8JSZku/YcCy6YIXO30R8YtOXIEp528+b9AxO7Hpy 7kU+8/JJ6jWtd5uqu2deGCjvkMAlY+PM8rZwYZuntgb0feQBrnx4c8M5wJL2pQ9JoloAHP86/bWo nJilP0Noky7014Gz2ugihln+V2f+y480axjmDB1LoD0mjRr9i0WbseLCIBUecdIueELhPGvvdYz+ Id8BTtmfXbq51u2RkazOO3rS+OR9hqd2lhtMdQsv/yZwNgLCfSHkVFP1WnPF+kLosut+5GL2q1SI reGlOd9FpJJTtTgaCN49pD8yMm+fvjN6uehaxsC6OjEFImhfBIYrCAOQJokGY6BK7DD87YSOUrcN 8xTOMi22zWQRTvwG32J3XGWTpjOemlnuTfdY8iJfvQRNVhIwew7Pj4wbxajK2dwYC6QTiVFHrLl3 tVfU/qe0TFPsmbPf9Xiyvuk8UxhcKmWCD6979XE/upDvdJHk84bfdMXCwXSUB6TlSRj+xz8zPXE+ B3E29aw/+xooBhaJQZoIJ/47E3FrcF5x71EH4NWatelTQdkaK/Ambm9YtEtxpHKSPD6kigcIeMxI AEz89y4a4ZYXA4FvEj41DxIPD/OSK9E8RRDZVJ+xrClAS8YeRX94ufdSGATs3nivPMi5abmog1+S 5AB7yyjv56Vygu+DYteU/9iU/kGwmTfuG+c91V+lWNCz0XF56HU1ME8evgE785tL3lUYplGXTcIi e5QQ9WaSKwm9qkSU5UzzqVcZrtGjqFgEnZN9iT704nyTbABOSO0BOuCku1131SaUyPGYwVPA8nsl HhQg1ofbWsbL41mQXG+TyE2u2pF5T0Z4fhR1p92PVQWFlhfKMTUqXZ6oj61kJgWaWrHlhAxIvo9e lBrGy0b7ZTwJHSe3/RiNMJ+RmYGRZaFLk2zdK0pCfqkGpUDWXiNNCrCjexU0WpLy0w94kdITVazU 7nHP70WFhUVdziMj+vU1LeY4LDg1X2EYRNpPAjh6Wy7EsBBMX0LUGJDssStAka5CYD0ud32/ssAK MF2fe6s7NpiYP7fEGxHEOCy+OVsUWE1vrm7Rg4+hX+KmHVYu25vqkf8iJjOzf7UnmYbAfZDm0ejM wP5eyxG/5Tw/HleQZij4jEcejM0jI4WDIT0AzZK4LJ1Oqir0tngzgi3s160GvooJd0kDXO1LK3kd Gns7yTILm+TiMX0sbKMat1Dx2QuKCaxmTNCzXyatbHDStT+CK7fJu+ovD35wgXu7K+nhtw//Paz6 ueo91qTlSTRL1UV8ULEVAzNq2AHVaezBWVNzWfAIs1C4bucDfg+5y0OTjbQTzNDalEyl+jxgCYBi gTi78kxUgmuOu/t3Yqiyn5IUExJ9D3eh5iQ8N/Ci0f1ECeaenDVV4wbNYmQ5xdkZlF3/PLR37+V2 gtMuDJcQQMUKvLWAYBJLb2waUMMZmwMJxFjavgnQpHlMYSktBwX5dofg6rzHda1A3An4T/DD/1vP e9Q5menJguld5MBhOFVxWOweUnay2L3hDdLD/PEP4xpnyt96OLLxTLnThn6fCi9NKmO5UHaug4Lv X5yE4r1VE6KzGv17ujpjkyNfL/G8Orivw8kUfOogF2eU0NWASpQZ8Bhf8P3jcHJLLnSDHE4QlqGM sXeyZ3xy7VPZIoHBnr5CE/AXoy4rqQHg0xPdg6/KXCTkvTche9mEdG9mdJ14/ibRdRTTufU2hKRF LhMPp0lrMF+tWaKK/sHe8JauxSo0AoCK9FcaNSn0F4X3uTSwIhX2lJMzdXRLXFWAcjCWLjAlOF1i yTCkt87usMePyY2Je1ZBW18yi5F+yfneObEW+8RQ4BnnzTkT4H8XWWCU9pAqZDZUiMMX1f2TdQmu hnMZgKOFrw2LwutOBlsZxqEJrfIRyFP1OqZSdic/LiMOu5k8s1DcohExXChuVmci5D6UcXp3r0CP Ert2FFi9Z94xXnQi00qC1K9dDsLCWi4p65Gc8Gy5Y4gJnjYlvtbI0R53Bvuq9M68ptXks5kOWKmf qeUthzHup7dalgenH8IiMnNC8fQNcUaXk1dUiI8Kg5lApSyTIHPELZDxtw6YwIcqJJiluFXKouOe WvZg3qt02hb3Y524VXT+WxiDaykAeuuYpoCIgXyGfms6E6vlbdcRUcCRYZE/752h7LtQ7ajrH/MP HSPyJZtCjOqAJzvbAahcj7LO2aHBYfE1cP1vUG6Bl/T5YlzFBJrHEXAtyo+uEgGncZhPBDO9IZWm bL52wFGyQMQ2u16WFdRnixHCg4G7tmdUnzOvnoYbDwgeCUpkWkKfNtTKLVn7JqCSTAelve+NQmrV 1v8/ccTFWVHdnDJWLXcqfh9P576aNZOaINlN1hXNnlqpx84U5KQh5fXmlTnSeCdIDrxWOCEcMto1 5GiVl+KO7PpNfHRHqX1p3LPhkH4ILUe9yVfLhNTOpuTZTiDm1VKXKLMJwt5PP4Dvm6IL3hocevaa mE3CDhseIFQEERwfkzWaZe0YBAsB6hCDhjZBbs5tnHdMEVhCQ7MYFvAPD+AhGjtSVhFdKFT650lj H0De7DoDC40b+qwdZv2l4uk9WyhKO7Wbjsy7x7VJBAJmCbT6wGwH9hjIAmmxrYNpYtQreSqgY2en OGolShTKaJj2BdG5tl8UlCJ7RqqhoXqpaqvDZjNpqjswIz76wptAEWzvflBXKiV+CSc3QLU9hSGT ZyxRAhMIW/8KUcN1jY9k7OJjyjBQxthUEatDZ9UvcQ4UnZ9tsURQ/VdBlUJgwgNpP4NO4cY9vZPF ZUOlFo83Q6LJC6p+ZAmAkJahjm2dHRWPDuvRmjAlk3w3AaWa+VjZ8Xs4kR/zWNydpPtx61HJvdy9 yPOMFaNBYbkX92KKKdkrIOh9NZggwA4PF5HEm47MLFBnIlAqS/dtACxO6uDclNogjXjq2kxQkj/f EbvoiWZ/NW48IZyHr01Fc+PmMviN4kZVrPUVvnujyYQJf/B/rRwEX3KmfpQ9gohKx9CZ5w5rJ46n qbWNox4vf8gkJ1/XrjVaZZYtWIamCzJIJmCoEjrK/ZCuua+lAo9BB8jZls13aV0BXaZMbWMCdNPS MkzYBH1XzjOpxbfTU6hlKrjTM9RG57aHAqBDttWHw1C+QF3dgC1fugWvVxeNV9slF4ed5Ku9YrYW gInajy1e3jnlZ0IFEqsKE+L3mk37k3+zXktkYcicsJ29aVZ2d4WfTCMI6/v6jfkuiWYZ7gkKqj/V WKTUGaYpKjVzaZ2l1Gm+hsl/+1Hu0pbxMbz6f9BZaNU4Cdur9uhPHfh1bS1bCVNW8v36qshGyDRW XpcRWdray/8MFIqQeYuiqEzMZoOOAYGtzTQ4j7mV9s3I0llILOcgn79D5JEKsV1BNTXk5xVOjQlQ fdgAmOYm5U4ymwxuSJ+/sjPZnuzcJ4bsZVKzUYsjeipDogRAWQMxKIe0K/H2ojK4cmZL2l0SmHo8 1opgvi6bO51vlYQWgMF6GjwdsL+xjTLYrme2SKRatFKE93PlpOcQYiQ+mQn+N5fErVysee+5uEzA Y1YsBROsabh5cNT0xfrk3zykbsHzAh/tV5QKe20YdbmLMBODPPTEdsuRdB72bRBVt3bKzDLFaKyM tQK4eZuasLs88W/07LRhxHtfCEwAkvKYrUt5AxkkGkbnNEOSN3oQ7Z9LvBKg/C3NEgc12a2WnAxz z0vkSQl+Mp5IRk1DSQ4UQHCD5lJZSw2BP08BT1OfKzAdkkKJKujMw1O76+cUx+oWq//uXOBwQGEs jID9VDQKBxenIRvR3r0gsPTqhCNj1BSmtPtl9Ew/a7c9t40+PdeOVJaOwC6uwhn0vMfYE2zAafeI 4GUEco+aTvmJiqGx1chZCkMeDKzWyTIIkHsACfUhYYA9suQC7LRf0BgRltAT2uSxiJSzb4eOlBws +kBRPuK0QF92Drqy5LA/YeW6XcoJh1N6DcFa4/tNv1eqLKbUj/M2NNP1a0/nhCf6wohlYFvUr2WD zWnwHgGmoEfpm5hmdfZZJfFlJFxPrRQChRxiN6B3OT+BXaeBaqvhAgajHyRtW9GkGd7KyIO3YxD4 ggqbW76avnqawqldAS3Z4U3D2cMK4PmJXLPPXksMt+cnW4IUW1uFSc9b730w28lUJyJ+n5cN8Ik1 b+u/OeBucWGATCEhxpjfV50P3BW/9xvvS2WjRiW0PdZlW1XItK1a2+Gcr7fYSYaJaDkKgQf5hOm7 ZTKduVZBi3GrfMsdmFvSyo6PrQfXrXEbkH0taIP7u94z6XavU2e7thPxy2FJpqM7LCWWeBPlWOrT Wr8rQhTof8f1WC3/PQipJGUH0uH7jrVrMC1mF8m0WggjbZlMfcvj9cFTRHgFTsaFBBjUJHZpy8Pw PnnX43lxYCltHBuCj6zCS4FbyUoHgq9hMcXtrcuS/tfP+szaeXtsEY51lss/R2Zz0uhC+kj//3Jv AxTorKbzVp/JeOmUj8HU4b+kkZw+qqE7uGy0YQDIFCJ1B9A0ZgqnclILd/Pcg/EYc26joaDW36hE JoNb1+v5JsVb9UmseXRB4egxk1OIINJyH59D+6cP4LfCkailHxzkFlNBvIlRnRL7ll5kNqrli7mC A1jm/UZJb/HOUDcHtW/gcMqCIELo0QqDsLGEh8XLdyu/xTSGRDcAyckBQtjb348ZvWNpayi/YCKZ 3hliB32of3t+nqFNx03UymNs5SsOBQWcB0mMSHbvafWsY3Zrd659oJo2maDB/rlIdGEPmLhK1TPu WdRbO+Px33nlZURyRFxf4lZevmG/o3jToHH86mN3E5G1YDGDCai3pe71nI8VIM6KKzdPLuLJ1EMc sBYEjTfRMbCWMal9UDia6A1wsEdxERcf88nid/fWYMo1YTrGXjIgEH/626NJefY6DiCptFMuj2fS poV0jB6oVDV7Mikt+x0uL9pcutt6LDVdJmmoJRBbQoo8Ew/vtBQ89G15qY74TXAaL2Z0AwBo5X/d SN8Qd8L+9Ow5wc1eHp072Ajsc1yK/ATOilJAZvFpJtXZczyHd6C2ddi6yd+BNfwQ66eywjb4tRUT j3Z9YBhbV7O4J4vUJWTx9AS7fVcZytd4EOdkn1iQ9nkQVhSp8jlrFtbn8j/oOUhcxbwPaVGwqNCn B1/guI7F9emuo65yuRUgx/uXbe0lDp4XiCHAWve9VF/Z6mb+tQawYJ3lo5EBoCEoVCPHnisMY5ma BMqz106paBO0/9fvwwHaekbTvMSwOr+o10Pauj1uBJftoAY/fLDiKFj+lBzbdHWevXPLJr+o/nOB SxLJ7o/mKTCL6YZ8My75Ei5acGsVel04DVX2TunqpF9h1HGbdyMrJ8s4fltuEPktNFEfjZW+LcKc egfETVc78rWDU3SLsjpQ+TEs0JslG692uyq8ppi8FWuuQVhH4e9ibiei5KmZvBbuVWfQrSRTc9on BmkO/77gL6HPR/HqQLhrISqI0Z3IPmhjOAgNXi8cehyqqiRuqFLZJ7Urk8cDfFyHOAcydPtrZoGi Ti7P+DoorZ6k9xPNF+JtkgdHf7KK8BYngpmdXWexG/fyzu31i934CWwiNk64en/aXjssB2A6e8N9 5QeA92NLr/Mm4k8N/HBGNam4H25TJKvSiTUHHIdhb4N8PNwpUBSdGqezO1fd8A/2ZlYQfeSlX5jO dPlOFVjay1GsMoeDTfUicqZwffp2UiuybJOU3/8qFc71cP7PVMN+JdCxxNryWy1s6SbNO2iwcLXW HlDwIHWPQkPovQJgO4sTr+Ds8Nnl9OxHkL5lTIymzTwfLezwke1ICcPV6j3ej//IHUE5HT9S73JL PYmjMi9pMA3JicG7s7YvUTPfjkSPy/7q4GDuWkEdpnVgICX4e00jY2EuDOlfC3+NupLRGmkH63eN PdlM7Py6jhLRiAC7UHWnj9+sRZA/lklhQIqTks9icTuocVKPotEE/YjaQ5RoTz3iDvnnRiAOemvJ AepP0PEKx5W49CMpEstG97dGMixqX8Nr30tGwp89TLKmW1/pbs223Qngs5x3ydp7rBx6alLWJ2TA cFD56WWcfcl0eGPB3YFons1wxLQ18wp1fZMvo6fan4H8vIQBZdshxa6xWOmUscwvekxQ3NWbSE1c 5eN/fKx+0DIVLjkxcZn1SXb/VyOdWYT6cd0csjcwPEtpePfZnwWMigd7kw/JUYcGXNyr17Qqvo6i P5EkNaQNmZANDlnP1NnZCUHMq0e7r2Av93DMvPCO5A6hgV0AFgGi0mOa9Q0QmST1TY28GpK+TiDt Wm/EVAxrzw4hIeLZKnOW/5pgDylt9SRYc9eaWIN8zBNkMfKa122pt8l+qoRMAlzDl8cR2TmaR/qn afamLTAY2ynYGqmrFBsDRRPee/EE5Zl81ZGU/UaNeRoksIpq5o8QzqBx+nmtOvEJY9ZDXUbtR6ez 5Fas+TSAs7xfOZViahUgny8VePSIX0EV5VHu3PJzhosNNL9db/l8OF+FxKETn24ImeuOxf6W3Aup LmhjNZclKC9HSoCAgkxVm9wjROUOAb0v3HSur6sO7LIzJWq2M54nVMQf7s7wpW78m3WgEcPv7rkM meqNXDTj3CHzKqTsJgwkQnlmPGaahWrGC6jQLf073d7Ur4gh5bmabTabLnkneKvZZP1aeycid5Xy EeHFnp49J/+7utRkK1R8Uaf/c1/R0vUn+VR8VbwtLL4Dv2ldCmKMhEyqcm2JkCMO3Md1+oYNzq7P knYnhHAz1k/L1Z0IBKI3vkSNsFZts8bPpxZxom153xf1VSk5Rimk8n8hr+YhAwrvJ6ddCFw2TfwG dKjl917nbFSXurV2az93LkJWWClTo6Zp673nR8ppiG0wN0ffy9pi4i5nC8sSvaHbD8oE65PooXYM xKpnjzTR4IAlAyEbvldIkyOBGoPPjy5h0BhgeAdSj0QMZYv+BFQHOy52QhTkQH73XvweSHK7+LJl wT6gQ52UJ/mBUA9q6OiHczpvZdNUBIu7+K3bd3DjZmr5b23NLhmf1ZdVy5SgXeY2yC64yDX81gXQ JpIQBYpNEXivnEOJ8IbTIyi5nKq1qTyYFahcHc6wMY66P1xpunKier3AdeTuOf0AdoPyc8DhBh+K f8BptXVXLbl5hRZ+gM0xCz0KdFHD81XgwprPGPU8G6SpO7k8qrppEWR01v92IPPX2b1BWFWmVzAx Eac7Sf4AEw8wi7UO+Fo69OrfK34Y+TV58zKtBJHYi3IDyNxAcEmNxw1b6OPn+XiDL/VC/2eFGVi1 sKoRbkP82WPLaoi9rZ9DnbTQLr9wW9boTigmsOBN4Pmb4JgfGcOXClfD94RDogf8FrMS83zMpwFD Z4niReor45r3Bu3RvDxrlzwoOaMykxI3wmvfOUCt4kTLEDrMA+hLz4GRxU585A7ufnEGjWmubm67 1HDDqOHEpYUuuUIiai9SynAb5nVv6Jr6N0LJs1hSVciiDVuSYC6W8n44Qr9tTCv0RGoNo0umHlVw CVJi1AnkX4fBZ/rcz1rYEdg04JJbRBBao/WihNtQp9e87koYZmjM+Sm55op1HNYRRaCRjx20Hr+k 862k1qqSn1jihgWbQYZV/G3rwNTceXByo8CiYgTCXObD7iOqxFJ/+IlOkfiC3mQGML3vJWYuHney qj078XoWUCPkEEhm7OTeqfGpdiw7kNS9h/xk6m3ACan5+4Pv4MIcer3LGOZm0IMQXPtE193dbR66 VOQAa1AF95gw/ZplRyg3i9VnOabsmQjoHwIvlT3eCUMBHiimS3LnMaRQGUSBLaXmUXlUlthGagfN C7RW2Yj1GDPEEaxm1sVOU/Gwvsn5uK0288gWhBlNwt3jkw8PogMN7Y6y5oahkX3g6SKk9yjlFVAi PQkcWz4qWXZIOIQSrXVwYHfGY0+VGCfuysy7F+ixP4DZSjWVfCDKoard/s+1lRBrfqmkb8M/scJ2 D+SZY3LRTOW9MqPn475SxOV93h14qTROkt66uLd3LdolHKYS2wz/oSSOL//BV7HH9GhF32pZ4H2L O7EBP82dcNexNouI/txNKgJe0LxZr5IL+VTn8asSC9HQuMB6vpwUat6GvhxzC94p2ZshSI0NX30G KDOGrkGMW3M01AIh0SfHB9I5rTJ5OM04gAGVMVxcDmXcUpdiUXW7bZCGBNlyH+mpY+heyIJIJeaz +5Vp9jURJlwcFMz7uOvWL8EVg/iV4M6UqNULy7LtPwbs/7WIUco46FJJeIQNQ/gjUmYTD+WEzNaO rc/0i6jzlHu9zlk29tQ1mhDrBuJ9H60dx7o4EZxHcNByYdruRGSHTV7SxfQfFRyHDFvn80o2a20s wvucmdVmcg5HhGNGgCl+KpEkuCCStV7QUdlnvdd7NXxoTG/J/edGZmAa9ROHAl7FbMe0W5E7q+kd /Py+HgrkO2/7akXA0GVnVZBzv6On5vQpSV3rPqkDeay39sKcWXWTTJN2bgPpQvvukkvvYDS4Mrh7 D9LUuxCoSGftudwnsH61BjI1EdZP5GpbWQHAQEGRqZQv51w5SyeR9vENaT8fo0H4x4vrm+zjeWgJ 0XzEa3LNYDMWRABoGxj5p5mRNQpYimLjAcFwb/zNkzeRhsB/Q3w2PfcAKips80ez/QmEp0FPZzIr NBHi08GHmBQkGSsmdKttqzeABRAIESkel2UKkyd4y5hzJMfd5cBUyWXZtexXrVwPlDm/D8t32Fd1 YWJvuNLMFgGrH3E9el6gJ19nK8lIwYYRQFcCKB3Xp+AIAwxK7lmplUDrYDpRicAqu8Oz617a3R2a uCQjx7l07fPrVIKxn3i9vAnSww0hpMOyJaEhKXnI6vg6tlBj3ZWnmilw1qMQJfTHptjeeGFZcoLr jN0Sxfg8BdEKdsBLskUWC/4k5qflT4028SvWT8Vy5ihFn4Um4xN5ME818NsRaZmAB0UJXPcai0OS 666nuQcMSymOf5L/ivnGL5L+ahpkhO89KQMp9p3QRFFrQ8992Bs1d1JiHNnXdpbtZFWrHgp+TX33 W64FMPNOzaFdGAaVOUazBypUQ5z0p9ekvrmgAUAOkFZWTPYCJDmcjOvYUOfnDoCSf0iIuWqzTgjo XCfPcHgpiBs98AR9L7YbI2gCqM+Gos5DNlf58+PVGNx+t4by+mx41KwtI8UwpQ2quzxmdCMSN1hJ UBEbtmiu35vrI2nHv3L38Ub0UzAJbUTAuVH1Vz5flqK3lY0ZNyWT6CPZi2DjvvqcPUIdAWrXaZVz j3yfqfTmfSL1PLLWJ7enP27G3Z81nrD5xcG9hNtyXKY0UpSDlv7a1+hduQ47X8YwvUOu1rLCF02A +Gct6oBa8ZeeZNQ48BU9FZGmxrzb51t+XDniQJHspu6W07USCDDSCZqqoHfKDI91SkMislrg5R28 hSNqPtLysXhG6qyoX2BmpyyCMCgy9zBjmXLFduRIKaJPEqgWxSO9MfO49r+K4cNsRGKTRx1U/doP 9CFnUZmoNcEN3JtcpGvy13+vJ98yjJ/fcGetYhmKDQ4qx+B30TDdp9HRu7QE3lclCVTQcXjTolI6 42rfEYt2ipbhbJmWTU9Qf9qNk9aJRB+KaTUbdRngZ7qHkEp4xecthWtvj2mE26CfjO3bMZldVJJf jEV+yuoLjDwDdgnCUjaZKL1yLGKxD7SNrFIO7YsmPWlpkjntXGiMux9e5Aj9JTAHrkc9Pk/BLtSC /IiPHwj1znUhDlDVCFEOh3qOiK8auZn9rrz7/LKlc2TnmOP3J/LcPhRD41grZ9cTynLYmgg+3K9W j1L0YyIAAbO+yFQV7mLA1xnHheEGlp4COILxvuzloK9z5ofNkIg4rboF+t+kcgMvXiZrB3M3tvp/ qXgW6HkFhQFujl2AOJ8TD8Cd/wH2dqf1hOcTTE6giogpWEJ1nWh5+GQGj6/q36xrlGhmooMIwyMc A7Niv9/WLwdXf7RJopR5D2gn5N+pQRf+yyaH6ng8fAlrTq1CZ4fhwUzBsnyRA96PnRhKix+d/nHB su75iJj68L9tdctytkvsnW5Yi9Fk1QH1hWUwy9HNlZ8RBm9hpI/doIVa9zoy8WqB2Ydwzrgqs61U v9pEAkjBJD+ZXOwl9FmpcpC1pmsLWu9WNsowqF0hb029Ymes7qUj0g9LIdd4h64PknSyphCIX160 Q1LR45hYgtiDkDM7Eff/P3KB1wDvwEH1IsJPjJD5iGcKrzSwEne91x42DmWdyH1yWSe4eeQheG7t KUoHGjK18WxthmmTu1dB+ap/zNYxoHN1iSbLi4qCyc3FeQbRUXDy4KcuFzx+60u+Qe387Nd2wjjU keyDKgt9bVkrZjECHizgI/d5wweCWMCQCNI6j96KFtOjIjJeuIhpbztd7McnhFT6A3/PSthb7dAW UIs/fHMcnemJsSdUmTBZeXq5/DcoHfocb9v/eez6WiaHkJTC7dwbaPstF0Z5ljz/lRqEaoetw382 BcgldpJgoDQPevrGEdN1kJn4zBEta/CbMMT/sweii1WYIMBXjoZyUWTWIsB9tvOMLL5q5qGsb3m0 WjQoACckomU7ikX9ABJOGGtIdpiyiNAW69JeQCKAZu6JFhPP2F7FHHaxfqAlvHOEiv/ilBggk+c0 TOB1rQNmHc7K/yvKa2KHJZ+JtWoJzMlVO1wxtgCg8mEmqsaQeA5EydJEaR7eeQQaRnPhy/vjHA9T PLZCWW8qsHusvR/RDnHJ07FJf8sAdOfs8bSWBwXsU43YayAQG8tWtoLxwWCXqb2Ei3RHhnApcK+L bpc2wtvCZcx0mcxlsqVDg2FwdDSdfO8JqcjbX+yJfBKbMhWJU3q3jsc8HNViyhVIEY373bwxxbV2 QFV37OKx3UVBUk0NbaO2+5E1Z0EpQ5kvaFuQyvlkXzab07fUag2Ye9S0C7PmKQc3+O8KqgnbN0q9 +e7JdUXcHLUC6LbH6s5/PZY5aJ+uJfFCyugSVGoe51L5f5XfcE5qp0OmsmZyud9q79efsu37xMiC Rc0BB5ML7TdcZv/8rOnsb/xgXRS2Xa+Uw/4PGYVFGc01/Scm8rZCFaerW+zsmPOeiUWgQz/ZqfOd g1XAJ0OUSMGEfZhQRAfj6FYz5ceBhbcHthqE83m8+Ysd8vRoq0GJ8NXlz2VmmN1qidxOMMXkunhr qv7ZIC7JEd1zwoGEz32wj1Bos2bnGFAFkq4673W6idGsSQ0Y6jyYuPTOqrplGfPN1ZXQ1zA8/ljq 5b8DO1YxOfC6y3Uu8Wd+TEDIWG5Zlil6QgpOj/d1U2ycws+tN+dulGRZnW4JH91uyIOwPUZ1ZybG cuWAqYQj/RJMegi8jDzkkZsl0fWoYUrYtHI7QqWsPLJtQCoLyZLviTLbWaAh9AQUi0nGzCeEmlNF gnS6yO4h+jvTIuazSPZUgeedsb/8uNH8S1rsk2cORhg2Te28zprFrByLAlaD0JaCTYhD2rQfe083 pF7IzQeWTrfNZjHDEaE2z+xKOM5AVg0mfAGWX5U5sgEI64fBvVWOV1zYIGdGG0KadSzP9DSmFjwV MP43AKI0SSfPS9M0n0OwY5X7pcB0RcavcayX55lxDe0hquKOZ2prdxxlorW3qrY0nn2YX6wNLM0S yasFh6PRhKwHeKCGRQhKNQsmR7PjsOY0evRAxVB30R0hcV7BgKdlMIMZ8GUo0S/OEdwfwBhfTli4 EbGJn7GkSSHnEjtFE1bz/Aa8PmfV6AH5DQaVZWl1JiPuySbMk9Qp9xuk2M4CZB4t9fRaf7UarsaI yIQwg0fpKdnVsQe32rcgOgiU2X0Wv1BCXAMdYSr0J2I7Hyn0dgcXGjEXs0cm9P0s9ohmKV1bjf2H M2zTv5Ug2yqoUef8yjOdFnD1l718a6WG3AXTHvY3SItEgV9WAasauJDc/LLPbBqKyiCAJuCBjMpk MHpifQ0GsW/M+cPjXXDgMd3HVYAAJHYcRZsCj/Z3vIIoBF+ffGHShqrkrdcWT6fSbZvguS65rWu0 8uY3Y/5VNRsH25kFjarA/i76SqtC+CClRvIz4svRFLMxKCUqe7VFHXszWkHQ9xdEDb5XCKcnz0ac sWfkxxdgTnxKBC3qf8qIXEjEjw4lQgyUxflyYq8TlSHJMFhj/EpR1BFLWf79M/u/uR84ypxcJF4Z pUfuIXJCtcoXRoT8TR3ieuer2NmnkpuovvW1c9o8LBF76E0EUfPQqb0y3qXH1ULw9Tv5Pmzaug4b tpopapxGc8me3+KkQCf5AauYU7ew/8QPHCvkebLhKCX6yQCcBpNg5vm1A4KJMbruq7QlzytFlohm nZpPsLIG+XpnMaPw56phzu8IVHKQHNqLxWq3dwjX7ViF4HvAfQwTsvNXp4NoLDzhKSqxb1COfzWb EG0WrsEJTqrK0v+JO0SpyZITQ9ivC5+HJKYPAqMun0eEzgKf2zoJ/v4O87FvUbXM2/0O9lLMQrcL d/ais4D2+B7IOS/U6x+vSPePgLkn5A2goEmIWlXVU4JNnPTcHTWqIAZywcOLl2N1el0iAocg8tho qMEQGoyh57lhOwxbgGB0GATA0VXUr5Gd9RXM2UrPPazMnh9+Vgt7Z1ckaXmwKjKDjxM3r/jg/O6D QOKbPvz+TSNg6zGDV/fNnObFhhKDwV1cOuF44/hPoBBbnA11ZlIB4QtpNmV/X7/uYKQHcS4+UcpB LkejcVeLqfDxPOqvDK/AAPICpSmXxkutLAarnWf63sgpZIWCeorWF7lXtcB0tgWrSqmsnzMY3SaM IZS7kgz38sEnW3BewUXGWAtZt7mJX129aD/SV8QzghuEPa3VeFxRpMorDiz5Ym5NmIYe+zO4uf4P l5hJdB706/Pe2Yr7xMijJtKKfhD98JUR7v2I1U2bYM7JIUuKE2coUfYga77VLGlbl517fI+ugZ45 IxyWZ6fGKCW58QxIlgCn6rLN8jtGMZNEc/Y45y28YxTbF0GEF+DUGeZ0p98gCdErcWepfzDhy68b vH2eLEh/KFUCGVI17P6DrKTSpuliObF/ldN56fq607MhLOzu3NlZg11CnP7ADKTxDTHmbe2gxFqW X82X0iE43HJeOjctFWlkXpx5+gp8G8HdSSLp699PkHkw4oC3hGvj1qi9mLlo/uiaU5AfzTvsIH0J 54jIigiT8SbhxxPow9zWEpqGDiq1RjEVbnvhpjwDN5Ti8y9zNLOXTexzFmP6GpXRnjMRRze28Dnz lBue33R7TMMgmS9BFvjd5UHqBUX8g/UI9dmDE+XoUu22C0XW2vSp5CcdeWqTdXM/2ftu+gX70oZf zLw4dCi+mqRRdMcYJyZL0JlhTIsFGYwkFrIUrmmgexs/gbKfdphQvHJIsgkPkzacp7PycTxbW2tc a09v0mCHkX23hAwQXxMz4mlGQXZGIXJdSQ41byPZgbjNw/xCWxsWyIhL5Ps7btGnza0eT6dnT0Jh rUpp+vKLBABVa9OKNUdGPqWmXD4zlLP1QJleM74xObojLxOyZHQLrvrQ+91jBq9cBT2to4SlVvO3 4QRIfG0kvLRKzWFduFEKb3XU42XJ2CyEEMHDQC2ZmU0Znsd9Bey+76744JIukmeN1JMLVaGs7u/f Mqj3L+kkZZlQigcbNMKDyyff+huiYfED9VlpqSJVdmZV2qB9RtK+A2Hmazwpe4KllntWzrVA1Nnr AjDHtIh9fkMjsWVXbE/V4aXMZCdG0m4rSP/hboo/keTFDCDmXHFxu9eRkSj0W5zNaQECDcCSIMXX wDtT+CmIV8Y4VjOym6j63VYr1BLFIvfaSgKl7cNxC3O1xSgZB4X/pUYVLuLwyIHHOzP3X/zS/HYX 8F+/gdXpHlN4KNpg9oR8zYzRxXYRk0AAduaHEr6CV5g9BQi3+kizMA98EFyqwJ6290o8rzojbUcD zXd7GifIYHf4OI52zErYOLdFrqMRwhd7Z3bzXILhny4v0j35tCEKzcmiRVZBM/3WfCHKpZmfuItZ RxkCz3eShYuc+ggPjdIPC77vhX4gHGAZFM5I3ewpASXEK5dW62qWH0JIE+coc3iaDOHfWfBYcjMb cEiTVig+EdWwm1I7IJpqyXlAZv1T7yxSEGBIeE9k8fZ4le66aTyB30UwDs7EFrGxS1bYmeShjQvR rMkdgahXY3Q+T4MltrUGQaDwOLn89F3/1oq/abipp4j8hhHofTbg8pF0LLRrDX5mX1omBL6ApuoZ CDuFmz0zq7lm1XTjzm6QBEAimtMJl4vOh3fPw6iEVJaTLZQhKN34UDbPpQAjti3laAmf9lHOgjda 39ohgMXFzc637mHQr0s/wzOHsOUQxp6LhRgJZU3wUnndqFxp9hJ6rjhMtunsCiPRAAen5OvQ0xou iAItMFKfaunBpQ+8QbicM4LPiiTywxbaFrNin1J363O0FLEjYCkWd2kLFyrRLBIDIgWqzq1h5Ufh hLN3ZDpcyHFJyCqDCDELTmExtk9pV6RtREZfR2hsmrHWaqHtDmi6bLDu24zO/DrleVO9Um4XPy7B 9f75+qij1ucRqB31T1vl4T/UoQu/yCcBL1zO2emqrx78LtZ+ikkE+Y7aVWy/7cOLUL+TATEA24VX cRoSHNZFrQARL3psysCrADfQ8RXv9HJPh0Epuliwx4SBGXzkaxMWGJdrX7/qEARk3xfvAowAnCud 4YUF8LzLWPNEcJQ4TvXcTq06bcULWXAn3MuVPVHTmqcP7VbxzUyfYpHRPCiR+GXRYu031o5FIOl9 nplHflZlWeocMHTXlv/Ucl764SNc7q+TbdC+U72rTOUpwNN26cJNTXlrRl8D+QeSc5jrpb9yvOD0 0n3d5EoQKPnGZwcw4F6jUrYajmLn3PGg7h/Qt4Z8xZxD/8rcEOqMjqc4+7S39xR/fyB56N1fqlQ+ f10yGdSMMgAUVCITVRxgyYySwvZoQjldqAaTlf0eb01WR1FL24wFddffWUbfr/cS5w8MqDGnbJod wAdlAw0Qbfx3K7TUj5F9PxJ0AW9lkM2jDHhZDVJkQbQlzXiAYwfuGE5BCqeYZpdyBUmg0IKyzO3Z /IEKsPWGCUMs3tVKujX525pOVH2v81Eumse4YsS/GYb4o6KqtJyeqAcmEuCx2yPWmJQhlnO0oOQf 5Kk3jV1lWlHsW8tgqYluRvp/PJI4v6Gee7y1My7E4yLF9GJUMIGDpz+PGYslH+jzD5K6uLNwahlc b42WrmU/b2VRBk7VO/0+N+CDRz7Oshu7qHCJhOSnjudbvw75ULmHqSGb54ZAR/RlnVywksCT9Lmd vkfZhW7GLflA6TU4TMy446wum5h9xlV/JEWuFDtd5XYlhPeRAkgzOeqPr+5+HdPx+OUGN/X3ZFia U7G7FDlGoMyHl/dtsTJP84mWjnG/mKJLIAKiJ/pEiig+WdmurZcCfpHI1AxWqe90672KS0kjfASA MaAJEM2spdPGZAGaZkme7GS7kkpgiaXErzszyFejRI/AX5Da19bt5cMHEZTMwIOrPQwboe88YdDX yQHIddJAdP2/CNUvBpBitqlRduw6jdCSt3FUmUeEPTc1NDiNT8nlabEg8DV/rpJ29JfJBdpym+hi fczr4RZ/RdjicgZCkwL0nlENCbzbuG0AdC3t4wbqmLZ12l7e8MnOqiH6BIVLWzlSYgRncKoSuqQ5 80AFvA5XU0pcATbD2T8gzC/GB9Cnun3PceM7lEgO2oxcOxv3qzo7/X9kOYabJ4lvnNPiSZ/XhbPp mNXl2gNITD6d2vQ+vTve9UWRjH7RsqT+LFKNAWM+so2uwdktOITyf8o4Kjeeq3U9Dh/NTY9x26ZB aaUU1sJqPL9cq9JW1IcnQePSIATaUEyARzgbFvOcWCT0Tw4d8L0vqi80M7HOvsL0mURGLUgGWHjJ +ugtsfpEX5T4zx+KDstu6JziYU6ygX4hHEa7LTLkV30F5YqbSYWkJLNNCQ3g5FoL6jM6PrCI93oS MrOHE/p7r2n9KFjnyuINEUVp1MJNx0oUgI6jG/xvSLW+wLM3H4aGtMPB5wW2fU7gD8R76Xbl31pL SHuY/sXrquIK6YOypjnN7tOim5Hr/LooNOuuZIAtVqdtUd4CPOe7xzrMRwPNMS/XP4MFAG2jQ1WW deI6E7QMQWKa+U/nD0eH9Y+BI72VWtTZ/xXvFfcRATJTHeDmAS99cCgStQJ4PQBqb7KIoBHBQG/i UldOXVw8OJ5khRrqqalmZqIIYPO7nT+7oPHKwL2jACNp8ROvAQvDo2f53hiJ0zbL+nRczzSz10HM +X47Xu9pmU6Nn1nn5aVBZJY+bIZ8UcXcjyrlROFwVzxKFsiGWe8hqBqXt6hx8Gb3bwU5OOl5g4oU Sk9ek5DM7C6hQ9E7Akc1J8jpYVCa4ii2GvZfkqiFKVQNG+kTx3mG6eHWSw4DxvVm36RkMMG0SO0u 1Hv50MUcWaste4eeBqV4FeSajdmfaOrAlZKXqgb8DWK6ZcFNN6H0sEwOICX3abvwABVTbnxgiByq fL3sFK4JwbTqQAdWVd1yFLj9HTs33ySf5LXiPXkF5+9Kr/bSTfypWr4KWgEfzdDjPc+LbH7/VMHA gdwKe77U2Mkq37LQEES60GG6OOF4UD5OtAHWeEHsITke2DNxtU5oxicIwa+Hh1GYynjba9wMYoYe iCoWC6BmejdnS1AIRgctHd2c9QJnwFSLZnqY9b1DAR9zgYifymBQPgwWWzwclIej/H9CritJiwp9 Zz+pn3nH/lmwer4nXCttXlk+FOgUzmBcY23wUreg6PQHyjSyMku0IzpRw4ILbqGDvgajoKNcrT+Z FavWzH121TG8TuJfOGEcN6qVZnSKCPAfa6EQs8GGpCtvA64nPgu2lZetE02iF9+UhaqA/S8uTaXe zCs6RsQUGv+yncA34a6ePJs22icYCINxkHDcCDLx47vHcPh2YV+sS+9qAA54qwd/31PfPHvzZjr2 IMsByACOo5TtmfMLQEwlYjO1DMCFyben3GJwINTk6JYCV8uXxQMJFBA4p/x35oUJKk8VfXeyK80j NdUjtcgsD3MLzzjfsFJoO/T9XPrWbfJFCQZDAOOhSe5ojQssRKoj5faxxqd6ZjCwIOcHotkQcSKl 3l75cc2klD0OZT3gX1JQBo1aI9wEPxDo5uLzuEJohZG+EjdXrDQGR4j2NUL07oYdKTyWjL5k68jz lLsf/Tmfbf5y7pPf6I0QxoxgZp1tmTfvgD3PV9HX/HPZ3nyo4qXw1aayPRT4Z6+QGXw/n5aoLvG7 KSG+uCnm5hb/M+0FnwSi+IWV5abPVKbjEorEKiTFMcY5UN3ibjMMwht75EQ9oM/PEJrrdFvJSgfk d3yLEjjNU8XaGWvepVbwbNESxxHIySQOkDsWDl9AbSxRrb9cfd6pNd6scdQhvsT3vZTJ3bAZGLso uq7L05rVqjswic6NQ1aXprX6A5ui0aHuScYvbw3xUpvMr+XBVZjQXQ822dX85U8s7Eev9DuFq2tg MqfSBjRSGdcVgswun3qQNoVynKASKDngZf/W7jY81Ef17L/OOulxxded5XWmie0NZaNeoNQD4dy+ wNCh20mORJhsJrYisxtqBxRDtIdd8dnPsz2wnVP+FAXxWYryActi/O7KOcHl4ttTOkP3suhHgSJB 70kmDaMuq9odoqxf9MK/I1ZiI2H13/szQzQ54AsN5jccXfq1H/JBhcOUu8drbbgXKBaxMDua+Kau cFAaXViiN2W9kkCfnpB6EnZZ5ZhX/ksNWb8q0U8+jZ0ef5K3nJWO6XU0pFLWIJtVadSS15tVfTPu 4tthHUmiI3tSjqGaqypjDegNN4+BatT3vBZWW7qV8FA69LUGv7I4vJ1lMIrvwbi5BePdMPBj8dS9 dQf1Fr2TczhF3TgHpQRYup5gMN84b/ramt5/ylBOh3Qwf9I1335rZv3ZoyD42Vl7KzkbcH1+YbTO YmrNk2QCISm2qDXHUPxx+3bstbfMtnfLVeG09nNlHfp+pDVy+x8Q+Dqj5/0tI+w0s8zzHEnI/OJb bo4vZ1Sn8OSZzEQf+63AL5vVC6rvJhKFDcu2Uu2LAHyxd+2sT9BG6863RSfl8d3B2dMr6dK8GGM5 ZIgoM4lRAZcZ6CnsGIOkE7hYyPC7iHHe6ny3S/1c2CgyGK7kj9oEsFlD9IsFiYAdh+qz16cniV0O t5K6nCFa2Ik77t2JVHLGrj3WNz5W9PYmjnQjkToxOOcPkFnIZWayxenKS3e66+D3nI6e6w8USn4c 1T2n2z43b/HmWwefktYr/wDeWgjzbtm6IawTPgyYkSanPBYL02wmYL61ADNgm8c13gW5QPHJX5Ub 92ykU55v/Ldnb9cq3wjGl3lo/DB5gJAOdXwRmvIzGauqz6YkolQAKwffcqc1/kAJZmbuCoJ5Zh+i eOsjmdIzHHdsPRPtDoxKVFUe5It+tT421ZDZLsSscBFXP6zbKLaVm7PoRi2bjYtojqOJAdnuS089 w1awwkCUAnRWPt4+T/KBfuSLRAJNdHCSQFW3Efw7qKrqc9wWu+d6m2noE2p5bz64hYN79iB4dKrH mbvB/fnhl3IrzKzsEQf6+SMoQOF+nPVu0fO/b3oQtmY3/op9GM5Y6iUosJgmCONcCCQEtwYU3xgA c1LKGEqKlr5ox0PbbEciXK7rOYy4Qp52ksOcKckiwr5ORqEYjaeXSsRuN3aaxNSNow7zECXhl8zy ncDNttaQ3tRmn8Of9BcO5VSFOGUttPl/JGfxxoPKxEEq2Aw7w/OQOed66RP/wwlGGdvo+r+xtNc7 zlEsH2LjAk0VrUXH/7592gtmhLEj+VJARy8rTS3WlWgX6WFF1DcPN5FTP9Cr/xIw41f5fxnS1ARs 0E/zO1jHKqnKOB924ND6nBFo+evb9/3UJ5DWQ9uq6EFJT7svGT+2BBXkStX3FWZkt6vsrxuAM0tK 53b9NUBAQ7j/ZXBQaPfk+r2RseRUZ6ip5xDuiISp5i2UnuMAgdYlrvw/rsxBW227LohVH4z8IOMF KNp9Z5Ag6yuaO79ukg+TAipk+v469sph+PH6ZAGsjIxwWQjJm7LaH1oXPPIgJVIYArF+6MzoucFq m5dhr05np9DoN3ju5QLz4yvV3qIGSuo9PXiQww690SkBPu28/9Z/Q5DdUm0gkYsEJNsLRcf2b7ua quUWwSlL3OYxytgHkvMYKLywbjZQdmoQ4vaKp56b4OxMd64RnxgHtroyQU3x8eRCGv+02pm3z7e0 KgCmkx5jAIpWxi3M6ElETbKnGWmC/NoKU8H1nFrEK+oweBEVeN872LO4zSSvKGBX5V7Wh+ry1zlm khCTtV/noyUYgqg3sL/VcnopCkzVzfSRu6L2UCtM2GLODI7muVmZsTZ2qQ01CDUN7KmwQ+E9kUal inUPcK48lHI+KpvBDsQuALyF5Vd8YkPgYHoG1444ZQZlxaX1x89DVuicIP/xkmPfXzlkGBFLfrLW vKDroKdXVfGZZctkLo0q1IrI5Q6zf9eyEUhQquKcThcobHHDDSGMgMZ7Xd7B40y2D/XlUfeAFvcL uAjeVONsdi1Nsoq6pB0SoPBL/ITffEUyS4cVobOL003ngcOc8ODOn4jPaP7OiRb6/njLDuxOOOJ5 wyddbT8RW3w9VbZec48Xv9gtwQIvUbBAbT9GxLIoqsXy8IJzIr0hdT4i+18h644SX+QOkOGflZzW AjwIAqKHLnRekcKnQ89GJd5CQJd4Z6LF0gQHki9ykn6wxzHp0GFWGUEQKQk84yisxggsqjvLmiih wTq5cpBirBRIfPkVRqP+Q75lvYHAfqW1hIhHS0eRQAhG18IcRi8pCNJTacZVwGojKXuBbdMEd9VJ Pm+9zmaHrwA2L4pQEGKw8MpLNVUdIdw3PIywG6XBgBvHRb1zux/jsCfjffPU25d8dPoVRmR5siAY FG8Vdwgte0sKFh2CGr0rn6AKBUkBZ7E5R834o1SrAeI0jibk1dsQ26akhbXOBccniO1v+Gj2EHwy T8agFtETWF58dIEnxwVDngGCq/J5f8vWvYHlZO40Hy6NmfO4HL9mNIlwzEp5Sfnc2BTvdYUxUiTb GZIJ5z3CMStMAykkqkLQOjWshO23+fAIqW9Fm3dS5Gmh9ErP3BosoU1o8J0+sgZYuhe1c6pdJ/1g yRsh66oaw0pUhF9sKRKUOVDfSYSXZQXyET0L9TdPUmpRVMEFVJvvG9wudiSHLEL5zFtPLCvxi3VK uoELeaizA6UN6wH8OaGswNT+TdrISyKt/o1sJSUVpadTgzGwz6+vgwYnp4tPflD2eO+aUNHU2dih BieQgvxRWIkSvaLkEGrK5fIR8bzz0eeY74TLKxpGpcRqPlmW1LSUR7hduAREkaK44gmc5MGonYQC my1ZHdhPpqPvJGPsbOQBoBdKLVyAoIfotN3JRb7Kd9hZNQO1nbTA0KdpX8IkZNAh0ipKVP+TOSPz JpF8icyD9K/B/wIWSNMB1mHVQZYWF6wgASK+MWW/IlBZWmPE+kf1l7NyirUSMXINx0kAi25b/EPM NE3FerwWvWkgNkMYo5OabMHhGEQWCVzPjwsxARxeZVt595cFCZZNMnXYVy7BloYudAUWGfBF/P+M lHkwSTRyWd0kly/mc7Eo9LOuDDPgWa9H9iT5QQnirQgrWgpz0i++ZYz1WlAc1lDWPD1CPDp9mYie c+T7c4NaN/AYAGiFTYNGezUvc4EpX+TFNXkEVGas0QvuZ8sxOj+Kw984ABsqlIM55KRyvl8K5hb8 qswdlTrPngP/0IzxfBKIKkM9oqVoRAHuaQ/fNdyAnNGQYFofFf9RRnlTRLtFg1Gg81SnsxgLLDwu vUOZI0QTthpTQm/e+cERI2GzZxtJ0ZmklVJLLpMok5fzXFxB8KMv69IJCMFIiQHQGY2U6xb1Ubx8 bYjoOEBWzzhalaDBc7PgvdrAigKOBCF9aWIi6GBTME2g9pBaQ5pJ0tCVueDShVQWXy+v2iPn8Nd9 p3CqXIiPL2c/GUTLRxCKakKJ0M87SJHn/2Y2LbdyBtT3rlBTT1vu3DcQoEO9NNUUyTFEFN+By5sW 9+siIeaEinUXWuLRau0SzdmwxidnjXy+ayvsd6ZLcSNSBcYI8IMGTbZzqXKsC9R1oJPOCthXRyTT ikqJGYeuYOkuodsnap8LWPOnJW88lLWMZPVphMJ8t+IVqKzlO9SpM6TOJg1v+9cnVWl2q/M0l7tp Cq7OQvM8f6Uh3UQFWn6IY1OUT+jJl/FqpF5IWiLiPF2BwV+/l7NqVTS5PepXaIZKcWzqj+bSb6nr cIAzV05TkPMQLzoOUf25j4WwnBgk+Z06VpTPWXUB7n/8WzS7kPiw5wbQEGMPP0zNXi90IRsl3CWM Ci6UzQeorp302THruM/Hucq7OpWEz0ebm0Wql6nxyKUDUPADcpaPlZBNoNNGuRnd2zKWPS2aLpyr QKPKw47UH9dE2PwJ1vPCuUdHpOLhkkLEQUmXafHYcBa2ZchwvIidv/HajrxGVa3/TDJxgWpZNCJ5 oq6PAHjkDN6ZezMsTKs3vzjy1vgDcLrOJcAYT9yfCa9UGHI5VBG7/4elhgFTMLBX7X0QVUp6B3I3 R/e+Qq/rw5665UzODJSEoEEAx6jV2H5AZ4wlv0VqG6898OPVOP7DC2RttxvFel1IkgHFHXPLLBfF xLTvwZGQ97PrTNryq00DkoqSSMG6iKAfPYYMBql6/i6pColaZn2yC5erYEO4SiGIJda59KNuY9FB TWrLSNttsS554Lv6q4mA6U/rxC7pPVFQHWrgRJAdCpmfSl/4YPJyPWYrbGKApxE5ZrJVEuYjDr5t Zql/UUVyo6ajahU3KaCfnusjf/nJRKYnW2OUnLrW1t3Dr0m0ZiWs26ZdG0LpTahwtBcUFPyTO7UK Fhsy8BKMwQwbpTXrmm7kHCyGJM2QjWadjpwpi4/JudfI8+NVHPZyATqrsxBXdIwn/yTbdyPGfYh5 eocDjU1PGeWdpS35kPrMOM57er3J83XENi1kvzcyT4gMnw6XCNCrbzMf5DGMoRDm3mNlIV82gQt5 hfqFcFb24uqLmtpgKIl55WMS7HXUz/cu2YVrX4xgFH96TLpmCqkdASnFHb1+4OytgLULLi74ar4g 99cuTQHwrFyvEvCmJVWziQ8RpWxCFf6ymxzyT/pLcnbuHXKyyNhKx/4Z1CfdlR5PrpShgJNq2uSD LIhTAwPLQ6cgoL4+6EMu2vRGRSX1i/gLxuMPBPBkFidFme3NCBhr851+b3ZNChcQeJ0kns0Ym6g7 EIfoFU5LNlkDVDIWMR+c45jrO76E31+t677ABztCNH3Vvu9fzHg13L4cR+GyMVEV3cAfgaYZ8kbz T9FBB22fGpcdmmtr7ZR3qd+RWsK+/DDwE6Py6bHpQv8X0Tv/hoUHQx44xr+27jq0PPVkLk2nGtcW pX8/zCP4ZiS3O1bUEvMEyMeEH2tXGrX/IH0adBK5RGWczv/SgnZ7z5tZhgX2qbKJoSY04rCUfYhb OtOJxgBSYqF0qn1SL1YGk4N1z4wETxsjTtaoSPxHn9Dfh3B4VvWu3y4/YoaDJm9KqJHUMrzKtfTf rNT3aMx05j0vd6p6eImdp6qOcauaRFwCb73dVkLbcUe2ligeg8w+/UBXU8v6fIF5pLi5CxyBU8wm 2Ir8fnQHCP6rItyYOlMDrkdemIHFAGpRnmeyOHxGuW+GnJ5eO3/E/12it2usR0RYJUCjg8DONhn0 lx0SnSNWynQWOpSzZ1k5gd8W4ly1uAdPHUJHmvbxcvXfqr91/IpZmifnXoFYigq+i3vmRcxqWGrZ NIqLfQiaw84PkhnvXO/CWWhYe+8e0hoNbfdVunDuNaUU2855qfFX5T8oyQ+LlOWXDv2Qu+q3uq6B FwPrkohMgi9O4pEW4imusKlhnxrFeiU2FsDKK4pRO1+r0gtsNilByjI9bM5/alBbx3oh2eq5N/u2 dIbQpSH5vwGlp7y6iAfTT/JX2WcGyVbyfkqLuwAjxejcurasQvzmSsv7c8ATY0KUpNa72mRFag4G epBtO07bdqpPFnM0eQaOineWwkEDlE4vNIlVLfAv7pxZUuK05CQw9uoaPj1T8cPratwFZnH51dM9 4LhPnkyQKbp6GsFeJz3nwejNkzvSfYSNUqxC1otoRdr/r2SuGW29b39FspAzvQ+TrNZH3+Yr8Hjd vj5vrtvmLS1yQw24RkjtskrW9OhBli5CKp9Dxw/gfm6bQueJs98QE1+kXSQ9ZDLOPT7Vj5R/8Q4T gUrL/Xij6ZL4eeR4scA1cOFJYKqTUNFiL4IXMg9Y5D5kk2IZhwfWLRBv+3MdHh9KhLqELcAgggAq sWX7gBPcCwKRYzOcPzsB5l+uHkptgRo19Xtj+LJJ86HmklxKpb/DLl3bO+VTnPw7dcnqelEYW0ii KSn7Il6Nc5DVOYCQqmueeEz0CEABgS2G/9e2UFckfG9JJgSvyHajYbLhqhrtC1Nlbq92HuN6x/9U oC4BEQ85ZV4GFwHjdUo77orCDViX46p3ECqww0VPthjk1ASWQLdgWDlBNYlFaNDW5mAn8+Tkn6YX hH79vHrEbUTaW8EG6S/DrVrlNPfs5sjNAAYqn6e//DubfocskpIGBElFLrHlHQncSttfe5kL477S MCQzMR33chRb2+T+897QEHjZ8BwUqlLwdJ1Wlw9/j0OJvC7Z3J56Tt0FkIflyYtq3cBN7ZZAE6Z3 xWCm1Qssk23VO4Vs6efA7dAcZJlpNwqgA6gyJjtc8CmOh0JvIhxf/tdOOsagTT6UtrQY2bWtv9fR 7NcfgJP/++Fx2fIISAQJ2cCOhTUJ4IYpYg/dr2WmT+e9tPjtpZ09+XCc5VCe8q/VwkaXPInsqF9H CBaqewZIo0kEbceSu44lPOLuJDdQ+p2xA2DOW6vVXyiqHx5W193jBoSu5fQxh8vfXEwhzCd/rp57 Xr13o9mlAGWwGx12oyCN0oGCMkQoHUR8g3D1uBav4WEPdsk3dgiim3u5cHCZx7697E9sUgChDX9G odqR6cf0uN5B1fnfxk3d9RHWKnPpFuFlgwoZq8LNnExnc80JJH/um0nCSqRwDaOQChNnOinqxfce Xc8+2hI7haElL6MB0vuI4GOlZt1Vj6RtSVZFYdBQzCbNIxwrPqZXr0BiLR83CfYN3GMY+i9zRlOu Mv4+f1Y8RMxEYz88IZBzKPKaqGaNrvPrEAuPoMfcjQHIQgHeZrsojmQiJo90NWSAWlRR6tTwzFm2 vthNpX1ra6MiVH7NH/n36M28coIK48g+kV0+5iLYZKI0GdEwYGTH5pD2LxFnOLAT9FOYD2jbV5DD HV0xQ5Xf8+cvPX04ehs5V6C6Ps4vod8VorYbYiwIctkpwtpHBLcqjuYAZ68nfVouQyMvWfQDdJpu Tvson1iFlUVZ/ok5iacHWM7LHFPTznuKB4TGGmO6sYaVrIJkOOiePGNQVyTCwUkEVAoyLlhZ7ej0 xGh62PJskOlhWjqThQ5SmbpUrhVYcmmgew1vqbo2WGXlhzPjoufMgQV3D/xYGES6f/s2PHdsIxsY zQ8+WxEvX1EYKaIyIllBE7TCA3FlSCb/wvghFQp9dhzNFYejIMBGvq6JxaICViS4NS71Ja1CiklX xuvNe2xMceH608T9uQNzkFzI/8BxW/lR82uUt1QLYjMmVSBvWhRrV+N8+5Buc5OOFh9oUnqs+qAa TF4kQgOGBixDyTHjINNjuWWLkVoP2PnpMovJgqB4YWdQpyYpMrzRxyFX7EMG0WTU40wLEk6EyuXe gXOwHaEHye7n01n7LMmppaKlSC/Gh4FsW39ynnTfS5FbogVdBUkVPrzx7+1jERFx3mON4aiRmujz SHQ8wfT5hKp2Me1LW5EqfeY7kdKRGQddzS16Pwq+d4PQcPUpEYMrJ5JiqMu1pzQUpPz7FvZ/CAQo OfgpichGaGEP/Ajjf/OyNwUYqNCWxp0e8Kx0cPBO042/YlTuySzlj9Cyu0NaG+hjEUrM6AVWLe9m B1ZSRaAM4hkXhQTPzmESUu6oGn3sFpAkKlY6SpO09JP9ZNOm3I3UgDuQRNh0yWNcbOOk7/RqW6f8 ss5igVXamDKPXTds0b07bgNxl+Z4314wrIOIdjfpfmz1VKix7d/8qeMkIMsxmuf3rx0wU8gzpJyb EvAt0BaShHBQ/WDTxG20vknsMkQ2BIj7vzoPHerv9ZaSvh82ia8sfLS5oxZ7FD6hpt0jQghBQrw1 rT/eCi00O/nHq+R34oiyh79AmPpv2zUbtiUvOX+xtmB5SXy8L53Roh0PScrAJfumiwPYw1mOS7cD 4KEeVJ2NCJc3798ctHBVn6c6bT0sxdV7f/cYSeUELmIzx6LoPxX8PQEwNpbEqtg6VOol9YlHxMcz rQ36ZPSkWx5/iOHwm+XGFvRCRCPX9P8ANaUu5MeQaQM2mseEfN+5ym8z4Kfmz+c5R5PK3wI2kB/I 7JGc7ZWXX+hBKQlvv5YzrJy8S/4t+3yNe+fioenMIooMHVu5YZXQO3QyYMfS6mu2cPlKrKK9BaJW /j+4nSmKNaHkW6VaLfQ8nY22qhZQblz6il3VwVn90jkH5apYaglnNcppmmsOmIYS+OziA3bucQjF 25brsPk5fnLxkwRq3552ZCqmPRvClxByq2HEKn0veWlz8XAgh3F1l2zA3yPsmRUWPaI6CCpPa78P bP+Pf3l9meoA0ok70dFz2nNzYYOZrQGkL6ovz6JTQGOTwunfZt8suX9qTUQ16Iz9o02F3UUK10cA iK6rSQ0fdfXpLQZ6W+FiHAbrSoVS4ob8R0sQaX6iaEqH5Xb+GnnuBv7yuQdqGDLHjY7k7D87aAqU l5XoH+X2bjD0V+mHNDPJ/yylQUBwBLsoJFgrGML9KO/aU0uicUL8f+4GRdIzYsL0gS4U/ReI4IAx szN7v5OfUafjwxqnzrbKH1jRhjGYsHTDiUUXW8CtofgmW0mO/0PI7fCHF6tj5trVJXiZE1/8au8R EuBc+93/zcWbLhajv+2KKNndEIgNhOa0egeMzWK+CcmKYedkdh+c+88/Qk7F7Nt8YT5vSvlbK9bd vj/L32RxH6w4UkN+mRUyv4/aVHyDbuig4kExulp95yq20IGK7WSt4MHlS4X5e25OqEAjc7UHK8Lv hENk2945dYjP0nSi5ZEh+pdsN/Vt+HRzBvcK6TodJt1QZ4A0XKw7WQ0pvE0wVco5lES6vxpTZtP7 nqTL/MGx6gjaX3SzwBP4Nl7800Qtpndjri0qMA7ipw8EG+g7YXGmltxAZTuPnGVekgZLebUApZzM Rmh290mZV9+U/kFo0AtJ4iPdj0/ijusuBTkcotaBKxnZ1vu3T79EU4Nnz85bIq/8CCYy4hEM4vWK PARed+eJ4zWEIuS6r2uee7oyqtCxg0Inczpvv8LTmbtyW9OSdUM6urTSU6sJLFJnGA9LT7B0D6m2 Kqt/MDh7Va/OH4TWSur+1CwlcPrwg7aIWaN7l6mU0eGV7AW3mSKI9JUQSXMbgKFtIlXtTTY6Ay4R 1zGhxQS20mIWxuNdWUBQa9XTpISwqisJO8/kqWeBj+5t7Pig3PeeqNLu8PpMQNr4wrXo3fYKk+qZ KiS+B9Z3UIBWFR2VnpAz9QQlHxspc1mbzctuz81rnymiFKDFscjWinsuDWmHfFg7cqLQE5b6ND1E 6KOF1ASp/AGM4deMJ+WwwtEIuzznR0svXdETONY0VSkwXbpyd49k7JMl4a4teYihojB28K+RtGcR b0OXWAXGh/eiHmsDnRzDT84xfereEgnv2KMcUPYUO+utKEokga1ReBd90nt3HZ4RN5yCZTijh9Cs dbhbn9rhBq7UQjN5Fzb8qLMYfNbzZP7TdYW25J+I9+UZStMxbrO5SngBw3gn/zrKB7wvETkK4x+F uvhdSkNh2Jpfagejem2z2WtQEAs02cuKYACx7m8mP7q+/7IB+Ighsvna1C1lbi27a0K51TMG6ko5 7cxdG+QIuSn6MQ14Ejt44bEBhaHf8Hwe6Pw0YgNSsWitPnw0hf0nVHCHUzqyvQVwsw7sXwy2JMZs 7bcs5ebYtkQywh4AQRLTQbqtMQ88HEYyMwpFwUc8aGopF7wX3zO0Znj9MQtEG6UeICx8qsRRAWk/ 6iGpw9i+NHW34mLxjBxjIsTjn7bMW17YUT4TAQjgULTerEKwSwRwm1ANd77bSpQep7c2vqfk6FJZ pZhYrkI4T5cL470rFNlDN8RzIpBvYnvtPc29FzQkbxaK52xClkjc7nu6yWXGHLTf9bRSw9H8h/Rw gkAIRDWZhoJamocWaH9HSYLqXEyrhMFnMPS/BXciYNXvP3W9LU4srqRH35zNoqBmWwDwB5XVWn0n xOO1jqCmQKH/ja07fW7QzijliN2vNFDj8lOGrLfdUpes2jVCPCeFcQtWkQsCUSCEDb7OukWpnWVJ rYirthtJSZqgh3d2HXealX3JD6CUHf25mjew+ChqU6H7lCj99Ody5A3KI0nLGuQAw6yp3X3S6q4Y kF6aBTUIkyTyea0l2kap1r4xcX/IOVqdI6EzluV92fsRv5l7itiRrUbPFHobs8ijYg9M2spUED8v rTJYIrws6eOUlbfj6Uv1bkKQdYdRO+9RfyqrsZvF5MH6v0G3u8ijx3AbcvTMAmF9y3/YbHWbGxk4 zOwFkLc1wy6Bxbp8wrRC7+GXmmzpovGguUyTROfEd2OnV1DhXpnH7SxryeRYxddnhAHp74I3tFhz AbA53ZmCptFAavx/jwxLSFRApbLk2tXAgSKatwj6Lf4FDo/IjU7bcIqyJay5idWIClfw09o7dGvv S4OFiJ9pC++ZyM4eUpiC5q6AH7+YWKa3oF0cPZMi9rY4go9zAJIdEEOrJwqy5W9m2f3O5Nuck6Tf D5b6S+nyZx4kqithvH0faO+z3tsfC3DS+cKbdYqo3uFh/6R4NPKGKwj5SRwVJEsLSruWc4vb9wU/ lZ8biKsgFim20eiMc8ODTcLbgVMWNJ/E8zBD0VxTnar0p/0AnP43CRZNi89u4UQBTZGYGvyrMzVa XGtSuG+ox7ftIVgZ0Y5i9a95O/qv55NvNUhLTAfaP1h361V/M5KbvzPzXfwnG51O/msb9+tVWBae H2BZ/UBfSyrRnxvBgypJc6QMaoPK7Pg4ClXPFuDHY+pZwud0UGbGKnOfWGuQBqv1EAVU5wIcGRWx dxK0RCqxFKy4lXIAhZ5cULLvIeGGnXgSaYq+aP0pseJrUO2z8KeGV2HctndjpDCl0qVDplgoTm5F e3cFeyQNMv6Gw1uBl6/83O0M3VdRQONW9SXkTrif/2hXLBcGU5LkbT5s/3E2NPGG5mP2+r0uGb8D 1sagXAveXP1yDjv4mCkWTO+Qsj4Z7jdstY3JPYYWqrl0+mNMSZwCfE3UTc9z9SJQN+9A48TJQNgX rCEQiJ5qJE5j1CPNdoQtPCMF+2MqoxAdLXmB5bPqmUJOKpSqPuQ3xBgMxOX820uu0BWb0zBLm4Vk ozwwPE1u4tps0PhlqYpYSQyyIp6qh4dM6By/k5243Ph6au/7Tm5Xh+I09GByf32mjSrD56yechXC KiNvfapvf0K4AsqcYmF9sn4cFOHrGZuY0Bx/L2kn13NbBPnKMK9+shX8BuJ6pgba7MF94o3Y5S0p uVQBV9KSBxRhMlgacXce3OWBD3TEH0+DVyzeK6y3obdGbhxzqMMYHnC03QTrAeJFHdd8sbSmQ5d6 /AB3IanjE2Az5UeoFGMyufzMK2ihvFGjau7CcQXZ1Gzu/8KhcPE34GOzNBXcrz/boP0iCNWJ6FzA v/2GUJMepao3gDG2GuzUKzIYDP4AxRf9W/jV2l3Xb/KnpR/kvLezQ586+6vu/w9yEdlbZc6oAwSd fd1lM4i4n5qfuNTLvLWcmO5bmNA+N+N4Wcu6iRIhYpmCn8xQP09QR8T1FUN2XX4tP+Ox3Zh6t6tQ JxTYuR7kJ5JL52CJ99SPBml03waMF3aZUALPyvrkoFtkJOanUfb8RxWais+ST9XRxQ67O7QT3A0E 74TaXxGSgEKuhFI2cZL6MJC3tf4Wi5iVXpowsLv7vPDaQqpyjVMPePE7NCfCsFJxvVvpYARrAWhQ wGcBCbRt+uSgv0l4GoCfMfgU9ATza2wLI6AOg0hhvd44C9YdpIdmvUInBdU/nYdimFl3UFl9XNrN H/nENBaujLTsIZE2hKQSz771Q0MWGIX4nernSY8H9Sio3cfXk1Yi1f051PVu10c9j9OA0UMKKAXB g831CJpvcwliFIHzUJz1HYF8eljFzEfesLyUvbBDJ9oVBmWQ74kh9jL0cr+gD03pZ68dc9ql134w nH9s6d5RZv6sx90vkzuGSWCniGjEsqJS638pfRDI+JBvo5Mrzv/alIf0gXaqESbfeJ5utlLWUdCS MDcGPoYtrehdbAn5GqmhXhdl5O609wCEMnsVfaxpJav677P3paJrrNpyhFpMXwDObzyD57kaD2Y+ AeFaTBLsPl/sye3FGqNltgkED2E08r4m+avB84Tzs5Bf5oMbHYPwXgx1A3hYVuzMo4UZbfNDqgQg Lkx/4F1m5inTznNX2FQLPGQoO3rzdyhFFvMMS2NCG2hQeSUtquyDnSSS/vpFDmr3b8owTn0ikajj JWxjEfobe9VmlNmSVz8I87Ol2Qi1pbj+sI6NFgw58coMQ343PN0IZjSeRJObZEBuIh2gkCqJ1P5B Lvwv78BMVXsptbxAknmZBVT3Kc1Godpg0MSV8Tx7psQmWC47O532UZBdGndbVAdP2QVWZkdaO3bv Bqv9T+IoYyvQqc+ER5xWiIhSHQeO+DmeMv38DxZl2bW4o7uoFqEzNj0GUzzRPupYigH3MJcFnGGz pujXjeDT2ltvKMztuFNtWHMh6SLbaI2rM4xNFm9lcJ+XBGPquSlKKnu4WG2S9ERu7nVecmKKt83R MJFCnrr57mj+/Y3wHrdu/PJgl4hxIi9IX7+da9Xtzhe6Gn7qhn3OYo6Ot/Xfc60qimJrFcJreF4Q P3zBQmB3ccF9aHM3OHyMRrUMUERSRRdafMxqiHvdL2dn8pmTApYHjPDJgY9plZc0ubBmPDgLKvBq mQjGRMMYots1u2H9QdAb1cwEFRPJcRnqt1hgAvrw6qF/cWzA5bU8u8Y0aqfPJlCnpMXC9yDHUPsX iOkJrySE3CDG28FmgLdePLlHIfphuBda5mQn6Mt8BKstTOBZU5VT2DqEUniRXW/+z/0AuLAF1jkr pEzrbQXtcSCrkCbrEjJEFAL3h5q79fkasAUUkMGdVNz4wDsX8DcuyARGrlZWhHFeVixRPWzXLlwA rytP8LyOW1JM4IdzSETjoYbCBmfmW6agcNvf+o0gqpVuGEKJiviKU/hVSFvSgzMUOQc4kKxb9z4t g+rTELCJ25RfJlpCK2Jg6iguCtn9xIWrfrvQsk6/kHbkNQErDOOk+JY8CuCnREp+HLe9ucF6Mo/X uVvUPnuCxtvXBK9vwGf0Z2EG9S8v8BGjpoRwwCMBj/dLgiydTEmrY3Z/qpegHGOuaKxqZFUthdAn ldChh97egqj/wj4krVU0LqeFuctq9pu7yXzk5uMIGC1KacAH8njdLk5V55nEk89Uk1ZgsuKoYtSK BWgznK94o6eu2HAcSORFn02WBytAgUwvCnZUjJaiWOLgd4C6pRGPJ/GRSl1hTZydcu2X0G4o5s+m MAYkjPunSl4DCJQS6fXcyhOKmQrVL3HMxG+kUNVvoXSxQayV3/LiNr19d1ZB+onMDP4j+9LIkM8R QudIZPJdjZ+JVdbTDZc6IgkOxWD0Q6vvztLO+AKVF+sLnsGHDMSFC37+PdMzED1N5dmcfNuTeIEN mzmlP+xmooBjl5nCJ8T+ZJSauz4lpuVYR5q9+GXHT5/79wek3W5+wZg+hV1pqVTrQF6V92eAPR55 FdBxiIHwXRIDW7GKKw2RPauGWTvrAqVkSKn63jPaoKmYKeOC4bdzXZGRUacEwcN9eShsgV8XNf4C PwMcJ2nIYHeKspJx8Yr68dyOHz2vx2yd9wd3kiLurBrAqCNbWlErL2LTPr9FRgOdXHCQzxxX0ohB BcHRwuBkezKRZ9itQCfMkGHqE0csbHPhz/M3K4swpBxKXNEtZJSmiVA7geU0NzGsXRZuyHcrqkPr OA4I6EfQ6zPHMisWXj1mCzB61KK5pNnizFCC+U6GqIBo10ahd2F0pwS2fy51aHaBwzmkQfYXcQGo MNGzym1jg7FUoW1lmXSqFvLkpt6ZnakHrt62vC0g1leNL7ttTYwLIMUAM8JHS7P6TbdLLT3Lti+A cKx7YAMEixArFbgKTUSaFS+3ZVRyPlI3fxAPLndsk6ZYNR49i3+NplbX9mgakml2DPRZvfbcge0C Eks5OgUeGqwxwKjoX/1DX7TpBPXJkW0gxBlBa+Tc9Y+JIc05WSX9Yngg/dj6B1RbhChrtl0dI2b4 nQmb6nX9nb/PQ8qNxDityib7MxlUYqxzIWisoLWhVWqWuQ1zIKmo26XKTQuwWXibPTFU1giPfuTI 2uiV0s4qmU0o5JG098WJLDY/dVphaOswK9gDYth58swJP87W8abJfuWL4W0jL4yk5iywpKMHO3c1 RM5VsmtCHaAlPlyRhdbn5RWa7TyUPgwmOD63A0ZZ/JUCCPLVnF+gisM9z10CzcPUd8sQYQ2r3gJb iyQd7XBEbySzIz5/m8D0E7O4g8YBh0uRbqqkYr6v14zsPrWAxD20XJ1ii33dM2xR6lCQEB3LtJy6 U8wyucnnNEjD8C7dlYW6QqPCQ8kiUHDV6ACjsHotH5LnfpEBJ8aumhBZ5RINEskhQh8yxjJLC2YX shSFX+U5kW2Ca6GwW3YNNq8Y95q8NVduXVK/iiVqlCSHBkHbVkJH0nbBSrWETR//V3s5fPvnfa9D v8DiDQBFawIIg5ufXrHW5oLiFqe8wtCoi38MWYkCCJp+0/+OWhjgMlkhyJ1OCV3X4yQl3AuchwBA QMGbOSldolc+yso0esfzYZdopVUIi3aYHgRpeUyml7GhZQpRs8wzcIKVk3h0+I/KKcWeItT4y4w3 sTZXLUNK6xzNqIIPNIbANIQIC8iKsLTfZkBjh9lgPxEvqWPO8vOf/0MuajWSt+L3rIg5yZ9d7mi4 ALhkZTLJe1J50DmSVx2FHla1M/UcWPnUvsvGnN0vSAM4g0YSdqLTFNODVTuE8FGpsBFXa2TWxqJ7 di0l1wHMqPydBudVKpthWQJt8q86bkCJa6vMF12UWODjYSEHH0ZHTn5Jc5gCIx7y4iybJ+/QE1WQ zYIx5aLX4Ruq6o9ihWB3BNf08K5Lk85XwEQIgV8w2X3dXCmOGTrMhF64suiK71fCxEeFXFv2Y6i4 WeB7qZXKdflK5ZX6YhGlgUZtjDUHO4VO8edOQ+EguVf5TxTr/k3SlZCNn6cTZnJL70fPj6fzVkN5 voJZLXdkw0k/dsmDygWTr0sh8IsnGIsBvgueb+xRoZ+IHiHy6VBRzMXU7f4ywgCsAQjWEZZ0mzzE fUQ5Pw6AmB8ao4GEQKPxY+g0/dC6bSQ5LQDDFjqO7OD4HdMGv2FZtcqCQOSYxrrMfSOMggW9AUnp IBqh9f5HT8ga6G+m7wzhFsLgpj0jHifHr3HF9YbM969D7XwZdHqycP6SGiOXYR9DYR8JDSKJq3sQ yHXRQPScMip2FjaRSRsql5FiaDkBImHwB1BUODQL4VzDK5av4w6+y86T5kyzTSvJXylCaa5RKhGT yD/dgUR6HJyBMizqgX0x031RSayh6VQnNUC476VFFDuWnRkxphAfWEf3Rq2CT3Gmx7MCoYISLv7o jyDJjzoNEuSkNgfz5LgOXdSuDbU3NjRzrkxxeo5h/D6tgWtmJ2pbnHaJ882nA7KZPxfWYzCqF47P KMQ0Wb8eUnvG+2SDOeVWzxyQze3GG+bo6gRPFLr9Q2MSG4mbfJ4dfvXUhFon13HNH/4eDkK9iKBT fwvf4VDO15bs/DWEFvYJ/NNaiju3vVIwBt6ovX3xw3uieVqRE6L2RGFzP/pefNiskPIUJKLiLjyt 5d6Awns8WgrLhaLNoNdpACzYtbJqX8qJ78RZPuyC4vSIbl7XdAoBohbJPfKxkQmaQWlkSS2JgwDw fNWIK19I5pLWnPoTHmGD/IEYbhHFDNSvFqWKtuEKInEfxu5LjrzHkydp66/zm8+AAF0zTgDVAoYw z3SRnFFttXlfsytMFj73EOXDM2vuYCsyyEbWCahjZ3Ukh3hdLTMwQZTonUycvQidSd9/kBCVpk7m GA0qE4d7cn/WGNFCXCSd3KffAIfkl6b9m8sn8YPKFbyqMMRRHn04+Oxcgi3ULLg0KgJEqsBlu4pw hFtaahviRz0fQGnDWJI0sQlY11GHcSHSKRZOodppJdXMUYYTb2h3TiR4JgwOHFWlX0+Bj6nrrgaK 7bTCmXDda0vzBnoI3m0IxgHGe0X9g3/Zg6BHiGSQ5067dU4GxRdvNCREGP1t1zJGPp4DicG0K4ES cXEXZrgNBwKQyLlKTWBjHw9/G1gL00OSac6msGhqYz5OK3pldxUB9FRCwIU6ULAATNd86XMNokGz elG3vzMkTl084mlEPEwvcuCix/qzl3WxrGF4MkFT80ZedA2OLSzoG4XTl0ksvt3N6CK9eCs7JbBv gS6skpJufBeEIHj3bql6Y6eRsh5l6JqystIkZk4eqXGqQ2RWCDrLPBSeAFmmG9cpa1ge8J7oejqP iyNEwmJ+pY0v5wtJsQ6oFOBX50gqFS+uvBIv2B0AkEWXnzZMaI8w5H6zs2MGlbuLOiUKq4FDoxRh pTSS1NAXfJk7FSoDQl68l55Skkm2n0Q478pWuhifBAXm3t5onQduXKv/aU3zUPlaa+qsYSv6YGbg ZV8vFqbbetQLWGltGux1Y1hWdJLMwJ0BIi9so0TOnozs4F27oCOQ3cxmspZCp69PfM5xhT7V4Lct q7IHkNpGo5KQ5WIDhbs4O3QJraXSs4VG6uOQ5gfryeQTkhPljyMHTDLzZ+f4ZE22E0QCra3MOHAE VplHwSWhmBHFjnKSkHLr8HO3u3/nhVGWw+xsRcDND1yHWge9t9nkRu3VUOa5p7lRR5A4q0XEW+J7 dQbvTaDMz6ylt5EON+KY+xNKnk4ujqQpd5IpIMPB+QTJt72tlrHmLtLV7io4sHJQLW3V/SSl3ri7 8O+7wWjaIfSRCr/cfrfc+kR6YkkP/71Tuuq+t6jhlelrrzA+/MdH5YjzraJtNb2hGwY+yPt+Y5H3 f0P56KP3D/CbG+OC3v/Jo6UbXbPdvzx2ci1i6QLgzbRR9JrjIqlP/V+LRV2sppcMYlVhzL2JYVOe FaKI0jjxWSy/m1lqfHjoCenPaL5d5hK9eS0nOjjhxBbvBx7aFUxriUye89gm5vuOeITyaShyawgb XEusKWmOxjk7/lLUkBj5A7qt0JNa+Wjgg5l7IAkYxqRpHkwYbKTJ/U5IrEi7dquYCt0QToKICYyZ jMj1t6mmchdMjLFwOOBoQlShLWqnuHi76XMzm3GroAfxmHjmDB4s/GjVmOooqp/wksnGUdKcSoi2 ZSGnfH1qDy09Zhj1+xsjzm7iIXA9FtGRM4MbJGdTT0/pWOELhxZ2mt+Yy/UtUlQ0OUt8PCdv0vs9 U/n+lduakMWB2vJJWjqoNHeEXfnbMVV976o+vMu8OpLsMlMLnr1DbkaMDizYPTPcXm2/4HFkJlvZ lxiAmbmKZmv5+rwQlFGXly6Pe0+TKxWFC/zdfwa9po/iaee42jxRUIzExijDnhp+Z8WkCXSqhB08 P3WNEWDaCSUJ4moxg5TzNQqkpQCoF9Ebsk7gmdFxEHl6gFA7gjNQfZ+FG9Qi/TOzPkktgu231Pc8 u4xwactptVfol8H86m0o9w75Qz7v7b00EKJ4B0uwSUMyt61CeLxXtVe4vmbX9BqFaGMRJQy3Gb9a A+z2R0/9qxzJZJJCGsXNfm04Tt/06FuHImygyX53t8yobF8H6ZMY8vcu0TSUW7xK9OQ6rBhU/8az PrVUfm1kCyb6zz3YqqW/BdHRNax7hqsxNltJZ5KGCKoCTXTf4xGMFKo/fQ3BlRXwn0kPtMJadOco /cN8kFUvwaW/+BLEW7AgHegAi32Snv+Jhs6F2DkOVJCAmA9IWE/hAWYMcugu+F+IHeRikP+xKqCY vXLfeXhJGGLR+sb22Wj8sHmtFAwrU0OIfY4uBLXp9pjQsQXj6n5VztHqBTUKTpPvepcaBloiislO bz8NeePUAmDxs91Qx8K1HBlvU3Ypvw+wo95CVJUof1LifEiv/IFE6uIzp6pFnNgRIUkzJ6ggVne8 UkY24a6+hzni466dLMzhoOoCUepAIALIEjjPqcQJK+Jymcv/KVCTaVCzPhT84AFWXcwO+/5mtLcr GlbQlOKT3E1iWGkQ85deNv+RZMgcavuWugUjH/qeNsLod9qBD5N7DxU6T5PDy7ejXgb6W3y2IwCv 2AFybpD+Y/RDulhffq1wAXBZIXrGQG7djJKVUP7ZmlqX84+xKOsoqT2ziLJc6fJSEbZ3PV7nBITL VnS9aZ5OHzYBRhKTr4ylfmFY5Tu8+eC2T4UUlS2xtRr3kFVx9P05wzgQKgz1yMsdpITQMPLxNXhA 4c+u2jz0y9wn/RuQxBn4FhZOPIezpc8iWd7R7ug4Lgs0jmMbaM5eciqJtfOfyVLBXXpNfdgAlHHU dlyf9N6AZFgBol/7xCJXAwG1Zkc5gBXzqFa1JiUsiaCx06I5bs6niaoTXkbr038kaYhPMA5vWrby aExnEBFniYb9IlXgnPPV+YBUvKiK6KXmcsN7kj0OWSLREW8Lrwm2H03iWMymeyq5vKYQJPlH0jo7 ISnwn6hCgcfTHCpkm4xytHYjfp2pnhz/WpTxYcZhoyx5MtHD6YfxXqGRB088mVuPPHR4Bqp5DClm 3vGJfSUesH6m5DSP/uY7cio7foSk5K58gKaUUabOJHeeJZsbHFn/zvQX7C4GGN43YAkVPpgpKfA0 qfE3XnEUwo8WwNoaJlbODkKyhKibwGkgKYzn3DDmvbiGiOA4nYleAii5RLOVjfY4RFuUHcRNDSMr tHAvKD2z4l21bX9h+7MtYKLYGwNWkroMvf0Ww8Y5uh1Y5FSFBxQm3rH9g7/Ku1FM1TSkDGkLs4K+ nafgl5hI0aYZY2ws3R2cMSgFcGLroox4qQbx2uPS+2zOg5ou2mal6So9E9eaqnfL2ZkX6ogGvhWr M6kn7bv9sYV3V07PCLld1EJsPQyPPWRzdl0qzT1ayuZNVMqOBrli3/8dwmsU08L69nsxYcvCYAon GslXHs2LOReH+0dNw+TAckjKZq/1rhRpqqQuvXq2xlqSV/VukAN3d/YNi8ZK8KsdQmIUcO612Tce uEALtdseOIuAwOQ5ng3eR01cJfcxltT7XjasT7/ThL+VFKXngkgnYSYhpo11+jN1uZrKHMGIQPqY kfMjsR5XHyP0AtLQdtyWrrXz/F0syjR2cGFNWo5bWL702M4N3WeA3hPiiUOn6w+CqG5YkxB8jgHj KfOkAJv2mpcVcmVtgjpw3L04af1nLhN6d3feyfNbbpIBeBhrnWVLeUvvAfwrPUQ5jlQDwXDAd+vr rECssuM2NOMPp7vrfMbnGTgtOLDLIfHC2OYi7gmUqifgb0YBeyql+Glo3R5qBvwdfvzeHzkt2aBS EOzBGc/wULX4uM3Ju9xOFe8Qj+S+eaD7nPqn1ssPUqN53jlcbk3PtNXLPe9LuMGM4bUUpEHy4DOK +HbiSxH8Iurrg/hgYVFUn07lhE7ipSKOp+zv/jwhe6QLUo3nLASFnHxDsQidX1osOk0MFBK4ivjg pcG/+MW2vH+OFcvAxI1varbDX+Q85K1Dnp5qgTnWnE2lxtYCvwjhoermxmZX9yfAH1SkSgqnCEeY /MWxiJ90qny7Oqs1J9geKeyY1qCD6RaEhn/I79K1JbkqiioKZQmwgQfhoZ2iNbfbYCRaKhoZgXdS DiGv14ns7y4a9deDE9AvbJxqEa0y3H8JOrl/4NX7dhGjb/kDHB8585CphAybi6KPUdPtA9n6CkFM ENQITRpxTC16sdGiyrCQjTyhyp820zuOcGE5uBeoZ/eKR9P2O83BmPzZk+epVozr0PIvXOKxYHt/ POk9FY6VBywYFSNxYsCyTkG5bDtEzFzL/FP1mQx5juVF+iya7qEhcLJnMo3kWGDqJkWLyHe7jeIA TMMiiTd+PNzcdduT2PRm1OdkGNIPIIIeiFSD6zTMGxf+7cWQNmglJGsrDjQT+kgSKnlUCyivFqOl aEyHDwsukM9l9rw2wrH/pQC8yaY5uYlpNv6HX6hdo8QXRT29gjaftNsdCwZGqM6v0oA18uW24Y/U m/ebscDVMe/+fNm41H5t14SN1ERXOyxhm2JqDbsh0IVwX5stprZOPHtITlQJBkN01L7KFvWnW0BD BH1z+n38ukz69sE/PGGT/nhhep+st9t9u4AWy1w8+OjzsCmEowdZ9j0onSLR7FTEWPEouUDr8utK Zj/40ifRPkZAUUeijx8hmPdSY9IhWunXpUTKxbwJp3k5s4m4yp46AAAZPoMI2jPins+r/u3ehSQi xCrrFjm7igIgNIygPN47cdMhLN/zeg3AJATcylE1eOaWw8xvq9KrzNuiH0KWahmu8c/7TVvbNTaw Ue+y4ibnsW4D0l7aeO0TmBSVo+lA5/+DPdbQISQrfpzuVbDlpuzqMDecvYCTP8oM4Tkfl27JbHCQ Mkegq5dQ3wo3qJAsT6/Lh3eeY18g2bxIXmBi9nkYMWoUiUiJ1KpNZ+Ud5InTUbFNW2CSPl2GVxWq 4SaI7lMlEqCcT01khZ1gpCgJ1LjwjtAloGVXnk2gqe5r9/lzAX68Qua8LwFaOLTei9EodUHZpg6G whKJtYM/S8C+/An/f2zfKt3kHdxcsA6CdOLqUrjgE1tGWxc3uz9B5eOOh4LZciGkDtKey/h+4mYo x/18gVQTLwRzPRqH77dRkPJLMi63TseFkhAXrpoxtmzrKqbOycPS9eZDK3TrpDAV2oliukl5vzKo UZJJCU7TDwJgK8wJJyPajofq79xUPUtqz0hmYqG/30nTCrXxWok/rBOABIBx3r8msDIUalikds3w WXibmOgr4aSpDPeIwNyksaSPAWsA4FmxSc7rIRJdErs7/Yk1K6LKkhnJO78Wc39w8aXR7tD0eUGo Tmc+Ih3OqF6LLNOWE9sw3vaH7LhZ9FdjyuxLETMUPJGfhTGWNf3s/R68rrIv9adfAmSjr/qo9CLn DzqHxiXhXtie4GXlqPcXjySocZKqLTnn4C9JneQHA+gp56AMsECg/+DlIOVuufSmVmliE1Rwgyba PjCTJpLUTCcuuBch4FVqu24+ZfQtway9d+UjnAFeG/CC+Ojfayvltq6jzIagPeoN1K+7VpKG4ene CORv2EN+KtJTLJMqqq0utZHwdrWGacIsBVp8DTUZtP+WV1UyrYYoLSRjWvEuUV4M+udUDFXfhAZh fWQOUaNywcCRLGmjiizLmQzFXUGm9IWOfsOJhRczD0iSlWau9ILC4t/cfsx/AFtRo7ngp9FqXNMk zBPmnUD5JRThFde5hLfuIWsu2kPFxGXRnrptFy0MjhSgXbuWGnvV9z6rgt1cRrxiDliBhPIGVHNN LyNN52fbZEPj2tpHmos42aYd27xSpa6RrQkjRFkasybB448MkSMwSgYsEOMoi0S2HBtCCcU2hDDC FxK/qxZkS2dYHEXDm++O8F5NSPy7S8+bwImYoBIf3XB9ldCiEgXgswplekyXdDm+YJ35Y5e7TaXv jLlRwltRHgmSiX/kDOgDxjv6bJzIfuEltVjrNiAhLq1QodISRl06h1/rrzU/vgS8Hdo916HZKyuG oLEUoz9jYCoLM2X4j7GHMW3LIpg5tZ0Xr0qepteG2XO3FOyapoXXt35wTLerW+XBo2gYAYbKrRkv ruTF5xT8MkaFjILEFCqa4TQUFQwbLSUVkrGjdGHUe6O8zT95AgIhEvVTezTbmWqJ+JbLduybC68H BirFSPjJMJ8D7dVIp9OhlU8mWUO2ZYMB2D/z/43zvYHQCVpVTDoNuPngI4+IfhQ/TPSIWj3/FwBz aysFvaqc5DDfizhy8f6rctfqV3T+jzkJXhQr2SH1sFZQMN/Ctj+DPmoM4gdsikwKGhr3uQ+HRWwZ A+/yvsRKeUVYwnf7lIeq2e9bLVNjiUIQaE11aWpJ5GWY0XB4+PUzc+cJ/Jrwfem6aUrQ9tbx2ZIr hYMOnLZKc5PuNhzgpRAJaUh70urIqT64yBOnl3HZbva8FQV3HcrtQa7T1opE84IE5bQtMv2iJkgI 1z+/0rSYTxVohf21bih4KX0ZtFAX2ne2K5N9HgMPmCAL20FusIVzPv16ZqtxGR2ExkCEcAtVfC3L F2YvunIFnFZo6fOC4++eKc1uWWUvvXDPgXnnrsSIUu8stSnvWG5/0/TYasUbCa5TXGALXN06dVt8 VEE5CkG2U8XLK/yYnFO6csJT2jIU67FxJt5laZf1iSlBM0nY0SpS2JoGoU5BwQsB27Zn8DXOjjpp BRfndQ6F3yYFZkMu0tlhUSflCYMnsKPrw4ZGjT26lKaRlWO5cdCTFajkIUuumOUhXdq2iYDp/yye 7eRBErm97voOhsCebl4fq0D6DpYyZfKEDh0D8WuUh1XLdHQopvrEGor3Xe51n5qbpOi0TIa/AYY/ JI93LwkPyCrscH5opqp+WiP3dq0oTVXiUwvE3BLBGzMbaXJEj+JrvLipv8Fm8VvAB+F+5B5/g3U9 sFh2djJC3e78/fT1M2xWuFVbcWMnVL9So3c+AhbgAagoDHoSw23EnfkaY7Yx4IQubrv83wiMrprM A++/o7GA/FoFin8mjiV4Aw8GidzI/0hnFVCVOxVkZ5wtzPczVY4pI0xdUXsf8C8NVGWP9qqkd1wJ KOffb87rtWPfsQRsN4XGuSv9PHXX5xzMqy7EghhqOb8nxYPNpFryxOyzOR69syekhDRE62UsW4jB PEGyylj4TuKj4iVGUdjgFaKUWz65cOOEIKHznpz9uGnpT+mnCF1Wob9gGDFcNgXT5Ql5fVCQSmBp MDFRbCdRtsjgl+pHjzSFWRy1BMZaOHueMIhzYMqP1VNKpm4xQJvpet3SI0RY/ngE882c9xuLPWTC eoLWcBtlBsO8lBJT1sap8tx+fjbiSUxmARJ7XLZKxACpIndBTh+3gIouEEgGAbFg5DOJ/uJFCy6c C2yhB33C1ixSzO+LPPi/CMxt5XWOiHr1wx5CNhH681WLNgn3Vdn3wVy3HwcyTxpQcMfy4mUqd+/S 53RP4KoC/5M54xU/cogIeIi5FnwanF42O5HPyR/H00t3WEBY9isrmks0M1c2DLs99XeP5omjZBEH 6rystc3NQ107ladBmEOIUqjhvG8KtxTYPEH628239j/idHpiZibelzaaimrZ+DYvwptaFIabrClu UbxOUsKaYfhtg45O0w55Sto/orCj2nHX3MFXVLYsjKI1RNfIIvQbE2ab9QJdhTdgAoq+99so/NPX 5jn17RPU7jKd+uhmQUPaTWvdOG4BE9qBkkvUZekbfhWv2R5diA5hiYFAUXUY89Tvowr1jNTTOz3X 7i5r2JczNzFYefwFlLK9zu73V/5hJ38FnREZbnghVxACpGBQ7tQqBgxUnQ/QRIZcNdj+BwHgK8MJ VeBxCk7uju1Y1fOj5PWD7/Q06w7i3H0D2goiw6BA0OraziClYnO3PziD5/cXQGFC+V1rW17tuODs CSJo4xYAcgk4j7xMwc6Dnbhj2CCOlYdPcq9mDxpvoOeIsubgalrLWipbda98OK6a0G0f5EU/soF8 alaSUvAaZMBm4mdyqCdpnXp0yteRMy+hEW2B6a0DPIJIQV6lRNxztvtn1F15g8dYozW+xcRF5I9d moejH+9FvfAnj8y9ePb125s4igNNh0FZmPWgUXzyHx0Fgc6LvUvy8VdX4irmJ1lxrwniCYnQtwVE Tiikk86/O3aqWFGXfEIShDVZbvOSNbGE7tdeL+3mYz25siR/WYOGDEkavO5LTk62ZiakzLAsHFrX dpAFk3pZnXut/rSclmjh/yg614KIYyAFTd+OvNJijlDyAfTbIF4FASd286AVgTg7zccGZ4J+oEPU i7dCDNcPk6YKeOoPJUmmh59u1eNjUN0qoSYPrPVgFYp9RjkgfGJVOdfDfh0xr36Nehg0Qo4Xrvl7 QFWu+IxsYNnOnFPV5DmFrC5Uesw5UEnhKTYFlhP7ePHijL8QSLCLiyAxg43ubG0pI4RumrEvzQgS thOnJDZkadhfq/VjK60t8zBqaHOaHSh9DD6Prx0rTlmPPDL62GSWU31i+eDcsrtRtH3cHiMikbip P/kCU3/mwcG1/P2/OhAd58oNLH0mLzMZRIKJHRPKr+s1gKjQET/BJxaoRvYAeCNi3NOqcBIligf5 2X1esXxtIHf4iR3QORr/VEeh9ckj6/mxgWVy0Q0z0Bby5/mHI7+21glWQ1QMSjpHvq4dMtjgU25a 96+0sAzy8cdiTt8Dg+XCnFzd4HukqM0LNLhKN9WN5uBpDoAYE5THrKSyjUFCn8Uj/l2UDjRE+4VN rr9zY+C3wCTxQSuC6QPlIzWHuuLDkAYh+180jTgL5IA07za2dQjAxC1m6PLzfkmpVaUtn5QkbE8d yTSpDn8WWYqF1ByB3FgdpKwiRIqLNgojT5OssiyVK/WUxB9yXF6LUtmaYRZw9LBg4k766lI6MtgM fgnzJrYqX4XOI5vug36xJ/1KvUUvRsV7zAS9WP5yivPPZH6CzJJQTsLtNZq54l+bn1ZP4c2Z2w79 rxqF2IGHW/KzHXi6Y54m4/X/jQs0ShUT6t7BG9IiLwNk6vqDbGC1J+jIJAaNu6lqp9fNudw24mbr HyV2Y3UMu/07hn49FYECkCZDB7FAE8nOQqmLck7SH3jVUxlUjbpDm5S5x//FzgJiEmTO1w3zq+W6 rH68KK3YQYEx8Fu1FTEtbjQ4NuasRDQuMPDuKmBiuMIn9o7SKFrhbPGvNEGrw9iIYLIGNYgbeO+v RR3WBOQ0qPI2d+N9H132JETM6solYaJCNzchVcxEGodZfIacEVqaNYun7dAns1+n5lcPz22RApLn +yIt5DKqcqp7sjQ+NPtz62D18gQ5ZjFKmnwsQDkGb4mC1I/N1d2iDxV9qn7LC/U0om5s5i9P8e4q Vr4sRBwg7iHCNKD2xlEvfYafd49mHSFQitNr7UNvsHvW6i9KN/llf84CxJL7VsV4Kd6x7DKJ2GXH JolYbwb7ECbuvRvKAHeKOPuKTckU1tsi85GcmNfYwkfi31pC18WhFpuXRuSAHNmJzx63SlJOEz0/ o68eJjFJwMzukkCkyJjNEmVpTzXy2yZ5N3T1QOYGezgDUPuvHIRLlqgNTRGcdSO9VTaGxE//lEcN pe/S1+sQ+RAVkx+Y71qT8m28y64/1mD4Rth5WoGaT09vdp2ymDCidIkQWrqd7VyITB08Yfx1RANK boOvEBNwKYHOu+USj7g6L/Dq6tnAD91oDH2M9UxNKhH/Mq6oKITRE6vd737RhCb8AWFz8avAsEp3 DqtWN15Du5xfQtEnbknyV5Pmw4A+jIm6KNcCaVnWc4VZV8S2nqoM2MHb0d00jJZ21DYvR70/XmXx F45PdwDsyTDxCf6brXviyIQNOR/uCIFaXx4sfIB5qSBwuWP6xlJD7Tzv7GB2DoC6Mfd9o7M3vkom mJgnSO2ToC9bC+pq1hLR885cJTa0jlnt8SVDN+UUeqU8WYQsz/AuC2qfjMJnSvFegQhcdGP4fTIE TPJT4INMRXt6aiG/dshvK+JQRvEulz6BT5pVsMvfmRUvJj3QdGNJBge3eFR3RTAW0FA8C2RHwOt/ eFQFU17WfbbDN0S3b+kyXtb3VWAYXPp0bNzAY7oW/u4rWZmHStkaNpewNH5BeNab01qfJDqbhZnK gN05QDOlJwX6NCrXraVQPwhAzpPFURf7aoe+a2pb9f4UOgYLZDYr9ceCWvlKzLZoMZI6xO6sCyaL lFC8aaIwzgxRhfg901kCfMTLCBxr6veoc9H8XGWgbeTn/sVPIkm87XkpXYwsEcmapK5K48x55t1X hLfZN35JXhf2WgOQ6fvOOeygLXbO5fHUIaP3oga18S1HqPldV2UCebCJ4FK8uNqO/ZLLHqqx/5qP bQwDIxQcm2Vkr1cPTUJQCVmRcVHuwN6awVYAw+1sm/sLpHiCUA+3UVsii/z/Jyd8oZXEpqIC/WW4 UbaCFaAGU8AgmrZtZsF6VVTtFzpY7s3CbehPk4wtFJhbXN+Au9pShrQkESnjToqwj5YB0eRSR14B HAoMKKOTGKxuDOvZk9zJnm3FOiCOlMiDXuTMyM1pZA5Ir7IUuyM5u9MTWDjZwcK121iA4uuqqL4A ny6Rm8IX3Kxx7J4yVAzmAh7izUeYghP+SjEZfSxHnvvK0Ceow1j5+KkjOtChrKu3jKlv5n2LT1k6 FDMOgLZvj7dlpKwSELKFNLw6Il2xyH+GiIby2V4tKJj7Gs35n74p6KDTe8RHsCA7GmRTZK9kqrW2 jVwadGO8ZxMQ6r9J3G7b/8hZlNMYFvncXFLwlmDYXLaNXqvhxh1FQjybn26NIM8NCPCNKGD0IiqX xVCB76s9BkijrpORSjiau6nLAhEZnbCFmqZXM7JCfxDTmm/ICgBM5tJk4+U75TZ6egKbhaT7+Giq wcKKPBBRzksej+F0n41FItl5guChGvuTqFi+IpnkPZhgJuDHatDVAU1abn8yb6vYh8Gr3f6wg5d0 KMp5gKjBohzasC7xaB0gIRQPvT7ow+cCP36SqIAxdWnoPRRwixGniwLun2vUzzxl5V89K6vVse8c iITBh1uK8C83aGMNUbu0qmlvU3pgF20uCcGp58iNNwJh5x8BbJw409mIDoqysOTPzXdvO63WkLaE qYaY669T6I2kfbqUzdS11mCRE/gBHRJ6eYnuT+WwYcSfrcgpe4kjI+40Nxy07/cep9crWwfqF+JF ew+DhqP+JmjriiKy1T7xjQVTOm6GK1x/Ww8AKvh1VR+AzlEQ+C6SAXCvSXVBsFCQsBc+0xCGcp65 6fCTFPeTmtxKdKrBX/rVPaIyTASYjHHs5ckcduu+StPH7nHH3dAawq9g867DPA+Z/1qXHH5is+Vv Q79pM9qnecTRf1m/SXYLsB22EH85KmXUFgjYrCe9o28lKXbskDJIN4TFUNFa6NU6qshvTuUZ7nAD YolyOYKcZoMpLNiPwcF/IPK4v4KxjeGLq5+UzZmJj/+eS2D04kCXnaUhva3bg2ENazf0MClp+ArR KQ/GjTkdtJiNSOZkfSsGrZXQVpcHkS7NlMU/08U0nnlKMo9kB3SYZJ3O+79+TAs7iC3LyS1sa5sJ AScwwWgymHC45IjHQXBiQeN8CpgoVN4k0bxnkZKvhG1YVglYhwdiaHsr6kdRjA1/CD0Y+Ner3aqE ZoBc1u4uNmXtK/rRBsrO7bu1R6l8oZKpVvLd/OKULhRCbFSiDjF5m0Wxl5qFwXiTA6jze2JTs7az s0yzvM5qYVfRPpnWJFL/sZamGxB3CjOGFSj6ddZ+rn1G7oBi0c6Wm/6GpSpEmrddPW1jOAQMflua jFCtfen8F8x08TP4RD4v9Z9C6w5nOc5WCwazIilb46dYg+Bk6H21OQUTtg1giAx1k1wcACGy56LP QjAb69fcw7Nuk1xYexai5UjZYnOpAzdEhvdJ+0iASdbyHtkedAMWe+Q8T2nC8k1knyMTQ6OojEMy VBwsZEwnnLxsOpfwKXfaoSe0Vj/GyYPP1Kq6LDI4O90VJ9IJOYBRp7P6XCPX50dGOGaG7GDZ9Kh4 xEB8H5YyRSWEHULiw/5MZHTtsaATy8Lp0j8D3+NHGo+4Ed65GAdv/v5h8IPpWnLgRoHT5AaXeU+n E8Q4eA8LIdK14EIYLDNx2s45kXeVev7oQtYmq0JN4ikjhaa7OYwDd2ifvYVfhYiyD0N20me/PlfL EUDb9WNH7NrrIRlfwicXKd4AjugpNRvhnrMBXrga+0QFSpeF7fh07qTUrfDXpFP4DualZYzJ3xyN Gkxjo3Ip8nftxeydjfwhDqoccAaOzm1H77/C40W8F+6z3UQVyD5FfCbsqoD81Q0kHgWpdQ4Jg2mq 5VdGAxBPT835FPTP4YJ0z0wQ+YaaYcovjWvOQr7CNt922wY9wqrPXrxmMNtQsHfICxZIBPpeCdji IEgatwa+jy+RsI9L805C78leKbvmSqPRo+AgA8FHRVQ2wgAbsV4VokMIhuduI0OYj5WLDP8cq23R x+fXPg7h1/275os06vK25aci5Iyj06ATwme5ipKVKqUNacTAvWwKRxFHPg2/Gbmqu9SlWWJI9ppd XvIdwFSK1p37iBHzWHOoffo63DNcuwitRWu1pAsFXCtxLYMtvAymA+kKUGN0mkH694KmYf4LU3Y7 0UI7ZkXFrZ07PSEZl4PYPHFghwJC/Yg3wzHN7wXVN3qWVDzSWOVXkq7p+esuiWyAphS8nRJuWU/F jd87k3XxFf/U1mubWLWHsRKiIbMZHCxa9hPB4TPh58ypn4UA25ko4eaRTgM/lCIjw66vaCK5nG9h 14Cte4P9E3vukWAFDAsSryPy+UI+wS0npmVVpVm7RWmB8ZueCxiw3f9xkbf+R4faXG5H5NEzdE79 ndL1ndEACtlvJd+FbboS7p1CsDB3PXfTYsYKOt96knRGdOmEr2xLkxxbT4h67342a6hFG8GyJPX7 FT1xJ+YhsCce1xBS5t+EdLN4SLN+It/Yh4Ma71pJbza2gGxYAtG0DKQRa71hVfCitwwhUY4+vYLv bBH9Oi+oWCZjTHvV4bbli4dBgnf6L7N4qX+HTA0+h1AyZOhcI38AKA9+wEL8EMTwqqw79B/b7yV3 aJjQFY6FnTPcnUF4Ew3tNTHuJRHpUs50oCQc/7yR+8nZS82V3jdJjNL3JYArPZelRxg7oLeu87tr mmiQt2bOawZ/qsy02UnTWjTnIuPn9s6OKm6WTz5ZZ2aXhpCc90QgNwtf6dqLXAtHqWFS/tamrFdp nQF318f6cKmdzX2BR3vAeIlGfuXl0ZwFGv9nGLQ9nNAPmJ4fsOecY/mGQsDpJrzcTLxmaaGV/Yin aOqLTiiP5sm0J5lpK28kGiDS5IER0z091OIHeM8tN9SwK/jQvN/PfgXeViDpRnsq8eR7u08Q6KR6 a3BQZ7fauFhplJ228liLJmvtAaocOUnG6An7tGBpVY/9c9x4WLwWpeqejLjBNKxJNSsn0Jirey5K w5YdWwd3ubIsMoWh41w9ie/ifLvhpVfS41oIxipuSlc5Y174yO3vW+6MKoJaSbglC+TToTk6+xry 09ltfNXgNtpjhocNnvGA5bOLoPlHaeU24Vh39v9sEBdWaPpQVG59GnFmRB0oGCNjhHlOOyg/okaB mRO7YPNVjq31FYprqE60naOCeTX+guyKIpuBzPfjGZxFHve1JROccHzMY+IPFxOOeMO0NGSTxI77 jgF6ax47/tVE79YmmIDyu2AAF16MbXStvHeKgwuiSFwebFzZTadND3ABvPcDrw/HhCFr7quqriXn z9Kjno5OUlyyvw3hl3JtcBK/PJeoF4LITxMJRstPaQgMg1Pj8O+u0gg85B1j+y7/Gpl1aQFiHjB1 THzS/3CDbuUvU/dC5EooVcrbSTbO8MVrN9o7QsK7BCP7l11qFeJJrKVofyRVCD2dlzVZSdC3nX0F 0Zgrbq4o1DmqHHpg7wdAdtTMvMoyHe/lKP4pmfg6xpLBorIr2Cr/lBvzM2HuThd6cXsinfoBVKhi Ab89OgUnWlOuj1Q9dhYc++ImLAA+aJi8dkkzJz2uoaQlRw0vL7fpc10GnPgg9kmuijroFE93RuRm SrBGk6wn8zcSSpymBmTGHJ7/RFDahJC57d9p6R3ksX3Q4D1sqWWX8nEqmmwPv7jMSZLrWczJzaqw Z4jrtXXtcXiKI1Zg9Yy6QVOKQtw7ovP3OujOsATX+jZDXI8Ga44xt3VmnZI+52HSehh7xmXTDD5N So2CpilL9dQ+O9B20LKmuN4RQ3JmCWOV5W/RydErVrNgMHH/Sq+bEWzjcLt5mK4c0PSmjIobScZe hBGvMWgxrYY+CWDppyfFQj620gcA5gfPa5NPq6ZXRBU4+7odhBCIWL2laInJeUpXEUSZU0cp5m29 GodyUqKXz0QPqp5HVq3B6g4ApEDsMcZ51VNcy91WNRBMUSxcHBTXPPtT6pYGL4A0wZpOoX5R84nD C3GCxLCek+OVDYiqThMBKoAxE2qd//YlMuNGYlv9FtIq+b2b2cdt+p8ffTRXZtDsJArsPuhnD3qR ZPXXMHyq2AkZ9i8gcG3tQK00mwilJ/x+FjzZIhgP2Uf2FXpiLVuHEvQ7BBt91r1ZYKX4ZTp53xAd no2Oe3Hh9KZy98fRBIAYels0s33/HKNpoThQkeJ5yChrjGuUmbY0ZYMFrjDoD1qZHcWJX/hMMEPZ y3gSZs2UW3/FCy+wXtZ/GMcGHjuQuxk1CfivL0coQQJn0vi2jxyPBhxTC/e/qmMOCseUH6CPm92z tJ5G0R5qZEhXVyuCfLrj6sWqO5tlcsMyfPaJ2OjueHbbWtKDjxgY5BTilryZBHylMQ2wE9ObQyq8 +8A7cuWPXIMla3CDuOovB1LgxpBK4w+PoZO6I08PPJ8zSeYxl9EIv/NcdJIlnVnwz5V/5c3d7K+k PDg5rAhO6wVJRykySC++Q2mZFpuR4YUyGO5KjbmwmMa1j49SpEV6DklcNtwWoat1U6+mWKsCf7ti hVXbt2AomxNg1YzwR5RVM/QRGkV7hEGTG8oFVqUr+ifxOfUOkwaPdtHLyd3mQ1DJKW1NMLxXdBvA 6Eq8icjWPpm3urPMM/tvN7JwYRWpTpFw7487n9qzP79Uc6Ew9a1iOu8l/S18SvUcTJJJoQE4c4A3 BKrUAXIu8/pMaMIju1xWCIqcqqnzlz/t4zKfBbqX+9gygzJwkE9vXYQOAscgVfVp/TDYVPMtJem3 pv1WgHDO92cLpbP+p2KuIFpGQqZe991kp2JB26r9MXC/ZoGv5HRgdsAqcNThz6D1sVSTkRFTBixH NZyNJGAsyAYWxJn9lE8gyRBoNKJJ6xl3UMCV1eLxZPtl80MOeMlJlc3P0Nf5EBYZ0OhTzJ/UA7lL ZLoeFP/epFwW8NsCkB/yBm26Djtu4buDJnYLjAL3G28wagOKS1LktDRymKdq6BpVjAJdLRMhx9oS 6+hnglSGYXdtid9DQZ4zK+1HWUQVa+pofDP+N/vHVdKU9IaNCO7BKrs7pmM9d1B0meaD9O+CmRMQ fmFAxnqYwOoTu79JKdhbCxZdTFGT4i9I3uNFW5Xj7KNXO6TfM6LumrPRja1IRO+PSyQ3x+k8RXxX UtnCRmQ1lJBx5ZFUhs70IMW3UeVPOYASVzYWiHhuAVjc0pJo39RSKv27osGQ3uTJKGmyNO37TjNw x7vxBiREydv6LGzMBi5P7IQJC8tm5NdhJarNV7nH8kV79/NCYBeQLuJUMgpwCrqprbTPJCWngePX YiYeiOo7hgj7Ig/s9CHaRQmvrGTH0Q8RdskZ/pGLvuKiYUCvZkDilsDovxvtujSDxF8/spH13Cpy q6B9829kvSNjLPiTtuyz8FRIbdXVgtleJEpRJVS7MZKAixsF2lOrARFr2pKNaQ7VU3+1MFT9M2O7 9J61fqiDXEUZOtxodtd9GEAWo68H+81+djK+sR8T7y8kkjGZfDeuSiIHVIcPjHvpyfphk15y/shn zIT/fMdWUPTypA+h8AQilHm8gh+zrx04bLNjVgpseUoY+jN+YWW0wxQkQTU6qIbH0pshHC3mi5jL Kw9mSL3i6L+GyAxLl+r8rB9X8u2V7s0uq/xON+kpP0t1KM0BeS5/Wjhcwzq3RemGl57d1ZJIwEhu 0tfcTFLOAYa7eh9ID9WBy0sN2+uVJbJHgsDYXJmq3DldvemqgHcqfaoCrz2yHgYwEyqnyyBZerTx lGviEcfpEfSt22Y/VFNs1bm4ceU+UpkDERPrnCPPVa2ktHbz5DBVb9zQe+lKOm9TbaTU484ZXPGM D2WN5LdFQVBMr4SNeIY8wCrclC6Zz4PCipwM1PtxXVbJz1pYaX9skQWEEwT6xORLkenbr76tIMs/ lqoTkQ7Wzkyz6K8jJfFei5WxQZ1eenPr56TnqMx7KhYEAAe3201CM1R0wySpBwBePVMaVKXtqdm4 JLwYnoWesWhmuWWL/qvUp4jWGI+X5jsMhftfPjcphsnFZKL6m7JeoJ8rKbYEGpagVphIFqeNKmI7 wGo+b11vSMs2Dd3kTDDGBg7+6zpDxBHJEyxnXnVkKcgXOMaGI25nvRTO1UkA82G5edFhViks98Wj f0BjtflMEex4B9XFDQ+qXEIS58dZfERh9/maohE4Q7jPu3hNkptMIiOB/ixKTbd6x0F7rnsXjiVL /V1BhaTxK3fjVAmhYduRng1rmHcj/pHHSW4gGfeq6aJDtE+/OraFJ5+LN9loyBgz6HyXwOcsnxNq SP8MByu77POXYPo8pg1glCiieLl/F/3OPaWyX38FKDTs2O0ISQNrFmLMdJft+NhUI4zBRdTJ+kn2 44nCzZH+0XAU7XIn+ZciBT2VXTiLGa76JZ4COYkJC2u6Wikkf1aIG0r5gbBet+fjqIYArJ+ld6Yw UIJA/a5KGayGJ+gw05aBEvrlGBDaHOHOAzVs3X/5iRWHZaZBpe2fpzuvbn9qDEbZmN9wFEDxHZI5 EZ7dhP/l69O0Bt2YYQ0f+cir9NbKkwKT1yllSqlxNItHXlb7BhqEfHPlqavjXkA2/1UIq3HEvvlA FATjbBWsl2uMOOIY4+M1dnnbOhe6dIFQbw4lcoPoJjKoJNiBAOzGg9LJYjm2cce8t7jJ281haOG1 aJYRyl4HMnvzEZ718no1QFn6HKChql0CHy5z59grsf9Qn54rhQBX568nt+cx8zwBp1yenfXhPO9g /JFX2xf59kg9ClJRbj2fXQwybhaNB2fepi/jtn3U2xw7OFXLIuh60uzrUnuVQR2nTMKBDG3MbId3 QBTJ6opKqHsLy6JR4XdTcJI1VqNu+cakIj3kSs2DGBE9BWAMNtQWXqVyBNHOJ0Rb5LH/ijVjBjAs q7GtrdDY8dN8LZVWhroFwGZ+N3lrSWyqvTtN+mXwjzzszBZKYvvOyHbvYJ9gsCvrPmmmg8IryldH qrWh/aeHsPg0Dtj27yvCGT/Vna05tCkVvEnQn3VXpjImZTnUKkmbCDQX92lsSdvqTLFOnbDatTCo Lcdad6DZpiaSKYpX1EJMz8iwKnBfRr3sHPomRLvHsGcuLT91coDU6mc1higBp3is9RFzcPqTr+kA DbvuDBc+pKq6foQPsFttEFwZK78jrBUg0PbHiX8h4V469t1loGTsFIMMy8udIpoQ7AAvkYU4+lGO IPxlAi4Qqb1eWdQfgRlLGJqOOTohOy/UNxS3YH0hkDwEHdR6RTRIqpw54cp8FtdbIIfUacwqB60U yaM4FUODqp2qDs/yCX89B43jR98Tbby2cKO6I/F1r+Uo3MeZTKhn9JjcyjgrSNYUyrtbWi19AUmp v8/r4y28V/7haN1Fw/GayfBwS1mKcJ4TviXvraU5homJryAgm69aVBQc8Qz0XbkxMbtP23VT0Rv5 VAA9uwHppebnQzIeFqOiI1YF95PfsNMPby/vghXsucTrZe32pFPPxthpo/YEKxehtyACA4yfXaJC qAdP6BrPioqP51fmi26VKbzsbTovHaQ2rvRBpoaQsiA13plqKLcGbpW9Jz+WUTyV+QF7lRYuckGx sfDZ92UcHZEjvnXoV31S7uUu26Dh/RdkA2cKfgTnidf/Uj5idNDSQQNPZ+EN5aLy/XIxxHM4Q4mA 2g0inZS9gyVwF+xuPSYHEoIQvNI5MMula3u46C6CNYyBAmFiXF0M2BQzur94S4dRw4KX3dDU/HfJ b313BytmjHiaBtpqHUYSRvy5DSnz6rh22Ne43TMtf0yhceHGkmb4sZ/oU7HMkLemtmAsiYIygVVC dQxW3axY/Ruh1QfY6NhumaqNKMERAM/BjQQjnlQm0sRqVcFz0481xYYUde7/YpY6a9H6MTin64N/ cg/AXEsf3cL+gVWKGQWTpxBsSuwR8dcnUl/xziKlI36+dNWxFuyx1uAIcxBZL6LA1FpHGpHSKl6k xFN3NWOgczoJyofQj8jx2JC1H+bHiA11Pv/mkkTS++yTtBJhR0i6m3rOSkbPtpKya250tJfgIztO B75t5pfdRTze8VOgLQ7I6hlINSXvdPWbeZ1SUldUJGuD1abYS0MbgHGHIv6jJf+u2cpmMtspOTWb +whwIeTXmHl5vtKFSRe+Kmtn1WveEYCEhnn/x4r9dt6IcUn2j6uP2RJt5mYeel/BzXGAurYbjgUj XP/cCR+0C/DaGA4HfzeGs8CU6KUzyvO2o7gVq848vxKCUmSts2rq14upTbJ0vSIGlQwkBUm8+ANM axdDcq/yALgKG1klyEImSwFMztO5aZsfHcmP/iTQmvM6xtG8GZrtVx8Y0K06L5japR8+NHeiZqW1 zxd1UgswAGAjnkiZhvVX5VKxY+rSla4n1m4DYVi/2tJhJzEV4ek33LoS9b065HRJg7yU8PO9z6Po SA6UlipMpZ160vwcHGEOfnkpSwtLLIpSC8jWAtxHMB0gAz9drgA//nmZC10aAvB3FQtcTV0rWJya Ddkis3dBxjO6j6dUHJbM7RPOH19boegee1chmjgB9BXVsJmcH9wliw5yNDuR8h6ATdbvPPqE9llC UPa/zya2fcylKulBAoOE0Jqn+UgqmSaA90aVntdr6+XxG4yHgoM8eSqYlrVogp8H9hEGaiv626lL EzNZl9lSukTf9hBYeQ3HCOs/esg5NHO7l4Fj+5cr7poCQl9vmdo4+skSk6R2S67388+RgCL7CfxA LWbfsoJhGJ3uOsOzpqmFEdoBtJR41qDcbS/0R/M5UhEyztbSSEbOSakP7QPqd67/WamowwmISvIG Lst01Qd2epz1EPmXTodfrdXNXoEu/ahv0fYqoay/QttbKDyq+AsXwG9nLX2dLC5IbZmJXKrnvvaE rDgWFziL58g8zXS8sM58wjlHIJI/dA55Uk037H4KXkbh6NiMPS7Xli+XHS8CdyKGdeYyTrrcrmqe J3AE/d0japtbwtcVDt/yADY5DG5WwJMaAa1woCq/cPFWlvogYRFdDuCRDwC+mfN68nhjVQchibvW fIJrBKksM7pvxzRB/ZLrsxuXtcNRHjYX5L68ufX3qp6UaPXxFvS+fn7J9+0Ann3xlM1qDSzRPc8O T/+TftFj1JjWmqOlSRYSZO56q3/5yTwP/nDCvJN6fDpWHsbGHSe4wC6IPv0qbNL7uf2WBsSVWR1z GFaGgwxcTnpCQxgo7+UGT1OGovWoNHBf/VKsZOPavfJNcIK/xXz/jE26jV3jC+T33a6yLjZQCx7C D1rI3MEZuLE718gsUhltXGepNsOWf+SIahL3VSFNNZjuAEm1Lw9ujbYVaEr9DZPctNgtlxmB098V uvRhYfmYMEDOCf79dAz+L4kdIQV5W4AjPMApNorQOnncBZzN5axarwxjCTy44sw/whgscmWp95Pk Dvz2Kxus2U7IiPrxdwluioj3HSG9oaWO/KzWGtoyXwvJ/ZziVvIGilQb5oM9VIIo1YDD3KG/2fXI QE8l+LrXoX/gRqMHV7XEaUzTGLoeOgqbnORwxbwOLlLsUokE5KerUNDyVCZ0Ef5uc8GPsXi+GBB5 KT4BRAoVd/b61Q6YYuU2mqKITnkoimt5fA/PW8CtxXQ7Avgh4TADfWIPC14K7H5roc4J2PX3IjFo KWR7yJDFbOVwsnKIoy/HTOhj+EtifHgIlfa4bepPtev5rrRTMENy7tY7VoQ8oC3H9+U5dnIl69r+ y/yVhfJcsJYOdvP5PgKMbCCm8jkUig7Kkf3LMHQVQn+s/FpUD4+S2YDx0oXux2X7tOMdBBbxTbFs ruMA5pmRFng1REt5v+5ifbP3v92eRZcmiFL42hQWW2nH3vsJ+4stOnXveqVCCq+7XePWxyAAonPX N2iBPE3maMBONCoGMhVEplbrE9nIIGReWwO9263hapkk5oA8xgdoIF0GmmUUmQiSYrnZYkpkhCFb jNdJjvfVullfyIGi9A0Oqk81zpaq22zFQlez6s6jb7fDi4LwOPrMlf+r0ubhDtUQ07ZmdQ87mMGz 4Ldg04YjG6n6hLVYcEZaEHQUk8VxBOAapKdcR9efJ9fxL8GyaqtDgHxIQqwoOlfSUUY4eXk1t23Y mr4/v172h86VCYBKeUtP05a70LQrZ5c2gsN9GE3gEVtBd7EPDgdmU2H2uIrtdG1O0t//s3/Xg4Bu hv2lVliOe7jsXDLWcU89t+r9h1+JdB9uLKvJs+3kunWqfoFxWedh7myB6dYCBQTUkMNBtpVx4rN2 QqnrAcSW0IxjilYpLfTVegxRlFkx67pUbRcPgqdWZnwsA2/p6i3cOdnYAQK6XLCUelxVJ3VTI6ye 5dSUBg7LCW6aXqwVtFy70RISovHhAXrv6oG5tuA28147SsAK/+8OIY10FdLneqt8/5p+tgUmMPF5 EeYPUuwWKhMmmz1MhSW0arDvjuxZgzbs607PjsHzFjLywYJt2nnGxQEAYoeUktHJ2cPyt//C71vg DrFXkBWzpyYkDGGn/ocsrNZ6aS+cWHbcS8zORRWexxvK1s7OvWHnXCb+vlAr5Rop1WPf6pTmrUNb Fqrey44nwA9ymKNaPq6mMpn7GBP8fxGWm8wfLOM7O9Yv/kPhqIoFsPg4yu+2/y1hGyBZplBx87xf 7PUFhEcCMOmFu6CqD4kdJ9u+ppmepzFsAFvzYlpXTvQsvyp+023T07vsQ5B1Gef+f2UKqFWVXNn4 LV96xl5JW47Ureului96Oo1v/Q7KM+58Jphxy2EoThghtbwtbTMJiDzQUYD6oguRoL6zae7//tv5 JvX/29WldnoGJ2ru/IP8FGtFZBErchhhBAM3G9v3lNoVF2G0jR76jKD0F0hUMTAC9kwsrZgz5tPI Mg6kOsegkTuYRChBzbXcnSDtBWLXmYNeg1US6QKrPPaLvhndAPRaMMOtd9jd7M7sS5dxJDQNf04m QfLfne/7P9iccriY5S9egSgFkCMtriECkgsOcGJDWCGH42LcIEl0o6gtnWCRLIVPh3VLIi7Yw/6e KGYLoxCgkUVvGHDf0g04FnwVMoMMIIRFbzRJAAwkQ7pxvqFqCshuEV6wUPskO6HnL2E6Xq71mVF9 tRzQJP/J8CPpLvPEVcWu2rbmZP+mQTOTP3T7vxdzkfzF4GMkuD+ZNA5WzTRWUwPNRFuIctaQxyZk Ld274hAoJCiFrR4ttLosZTSzE3oIecWmlyq2TDzgKF08CjT3NXphsyzVoASohKruJXct/OgS3GLF slcbvbrhmmm9GQKVnPBf3hQ90olcSaMNsoxUctCZgNfZIt0AELTp7IfFRCnUFZvUx0qdTGqAzDS/ e5RW1wDmCvh3/UnhGHiSs+qYjxo1r3zvtM/BCRsrlKmzZsu88kFmbtJOmg7ahWNEr4oAIGm0UK1I h4krocXJlBw2KUUSfl3Bfr7QYWuV9uMteXdg1LtcjaIKt8X1MHJrhcpV8ZgpxVueDVX8lFPUtdAl y+awsaPHzPKammzl+FmbzDxuLxgPTykhVUfwPlpWniUzOk5i2+2548udOlPMzRxclNPilTVjPIwh KSCwj3ZUJmJuokXPaqOXnoYslh1OGdVR0JyllGt65Hem4ItjLSnV4wikOkK1zc1FD7GxSSWvQolO Jj7CfkSC4bYYfyvwovh/biNtO2OWiwISqV86hP2WdiZ62kl/igg3Ziv3NS0ynKOzM3JcPIzaLr0+ yBfWtxOHRyH0n0+E7hDkYpop19BhHeicgpN1x17cx8/MxCthENOKSvVPl2S0vXwpOXAF3BtEqPoR d0QZV+4UrPsPd4Wkppuhr12ldhBpSgomuLQfUdFm6nXWMk6reXLstXzcAXQ5U7YmEfw/BcTII1rE i+E0glEJ3SznseVccp3qgae1JGngTtY5YlvdItEshEp5pu7C+KC/H/9lPCzAiry+YrpwtgTrqtoq gpplf5HKpXOKlzYukkEuo9ftsPKAbRfuKr2us5vt/gbASAekLJsL83i410mLlDrKzoCjPq1YRr9C GZMJIzVfVOSPD3PTiLTWm2Y5xov9Tad/pAjg7I0GSkigtdemRAk84jh7vxXD3CiROy2ahWM0aYcJ /W47E1tgC1OSxFOjeaN9BaBsM/qm6KrM3/bmTL4oza6ZT+lwDAxJfmSI5eUeW4R0tliyaLt4rISr 1vIqurk0PwD+XZN5htmgMNoNG3Vcl4yqprMOwg+GlBHJl4lzaqm4T5hwFtBe1pWSRx9UiwhnXqIA HslDEz4R70WZyCSc98QkPYRSHlvrBDWHkU+uaasik4oesPldUDF3ZwhcVNM8J1Zi+4TCjFvTjmLm DputKtqdOVRkchv2/OruS8pJHdIw9Y236GvV4/lccn5T2tyrCuG19lOj417tQ1eCFiU5ruwqHFf6 osPWuJqFT0kABIFh/W84baUslUefGBuNV8NnpVl4OczzgTw4n8LSQBqJHsFJw0rOJIr3nn4wlT7q 2VA53PwsJYAYCiEqPvsxA9YasAzf/E/8+8K66Gq1GWVtPvfidKNQdGRRRki3GEiunoYAhvlsQgtP 132eU8rXSRsHYToV+nfK0Z9ZKHCBZJBNKyWCV8xBjD5/jMtq1OieVn3uOidkQPrT4gOgvriFnp7j p3hTKIyuTqLfEuem1/oFEHZQhMmFH9+Az1zo+CTLPiEb+Pai8E5cPb5wj3yoiPNrV6pYt01kI2fT WlNMmRVVUHowKTFTEXMI1gvIiw1Ziidlraj9dj8T+7+QI0OH80YKJbffC28hLusqLQ/ZJ79D+u69 VnzJ6/5hXxZ6QsKYPTCR99945j/vkfCex7crcCP96IKekhi70MVZJLZrzY9ki7Qhc26Iuxn1I/dI zoveeGu2zwQ5FXroe/yjsrwZtwDtpoiI1/9+gpS9vvdjkuSv9tgcogy64YVFVWbsSd1po3JPDAb8 H/p2Ham+nkySMJtZTU/ZfhbTINFw+TGDrJPuRgUC+SR8oYl3IiViAztGI8lTw4+lT3ZjTLLKNS6s hUdUKit94rY4PNaA8yLmQnIj4q+ZhJJjgObOIqbklFGjeuXnLP2nBaCCSTNcQqinJzo5PqkLvG2/ dWqUN5Ip8HvJWaIYxJz59ov6YRQkdJeQnSg91ifqtjAO8raxfY/jggHHTkSwIj6Zx5XS2AwbCbR4 AnY3JAbYVVk19+us3nBeg9ebCe7Jc2rXPUS54CfdsB8dcUzT5qk4fycupVSldo7/FZrUrGTfqxQ9 yWdUtrWMNLSdBUHlr95Jpj8EGw26MeXoab/MuFwMXNdUj5nZ7EO/z+uzyQEn6jN2Po1+V3sFJsbG KoQethSiaJGZVVQ4Qb0xbU33hglVOgN/TJH8rKXZlp5dBQ+g6OSanzjkPc5wRjZ+cOROviT5APAa XWkVSIZCvtNvwTKWFBUN8vw24YWR3Lv3JVysSG5zb+BM9QVmsWql+DOQVnaczbmkSuTR2do6eqdD OmBnamYcxiBeAt5zkwTrrPqJEFRm7K2BpZoUCQ8EXRyi1o6bu8hO60IsNbGC6WqbyVkpJi9K86oW +PWOmUCQNd4onXZ7bI/CSC+OFxL5cILJx+CkpjihjX9S2zh77LEys3DXJW0Wx4lGLhBRMNaG84Xe bV4AOBUyUH0/MBJ0q/fhaAwfJyOlQjRan/qMyImBlZgbZNC737pbRKvRWn0pvVTq3+RfjFdNM6nM DrrZI+jm4H2rAPl1EkRKntHfRAhIqypeaMhxCY4NQZWV4VHn4/Humc1uw4Mtzs0lh0Nhch/m8Ocd 2oZZ2Skl5NYm0DpXWIoRnADP2pL+kvN56YNI9rDEXR5gQwaagL8e/RVQapNoMfr34Jp732ibio4l ShjI3QYMaI+OKH13tmyGvR5RDegphvp/i+6fQkG7J+gm0N2HKSxD1lYh9CgvMWhkdcxarr6tMxVJ zJrPAr56x+sIRl0bcwBxZe9brTq6twT/utX4t998qe1hJpjunSxlT4/AtLwWidksqS8tMikrFhfL J88tPubzEw++gyGD7hWDHHHGJXHOLVfaeBEo7aJFc3pvyrtgtGZlgwyYjE1MD5ibFzGqC1nYzNKx AsVNdyptgfLkm6T4JvlyEhK0O+0xWcJMSZpNPvsn31754WjGe4HUd160PwnbJN6BMdDEopseSyTD U6xBhLUMgUorbuEi8zRCTtUhaIqvGn5SqWlk58dMOX3wnir4qgl+pzbaVp3b95rok7kHOE3TWh1e T9vzG0H9DP0zMlXYJeKGFiFXiBEwE90q0uBrTag+nxXF44ptXer7KY7IGzQcBV1wULhpmDy7j9/N Mf+orrlkrQMLE5cD73q4pzZrsiDYPnQhEK6Fp2+d5jtgzEEFq/uxj/HwMg+uq1t7jJzQoTbHeJzj aASe15iHZGCx0Z/j94l5wfnH/17WCiEVXPmdN3SPhK3lP0d5t0RlniwtvfX5G1onk9WrtoAXpMRX LeS/TFQn2pmRpIEq2RN3EYZEaHvqOl/8Zax8Wmc0xcpJcnziiqUPUSjWtyDLLTmVaV6mdwXGjQ7T Mzt3DJ0nHZ6xly1pkZz4+Y6tsGaLwhO0VrUmeS6hXwcheNyFaOHuukc9BjnIckVald/zCxZia+zI zBPW4OFyuegfqrHbCGSVbdG9j1/2EkUUUrB84ZJzsVF1h/VMFHjQWJq1RncKGRXb6wEfysKYcV9v wJkyGappgRf0etrHfYXKZUDC+UnsEWODTQMSq4AJZdfvi4x5MhEqsYIxyme5GPRY6k78N6IOcO5z MS5AE/Qm9730rc36bC8ZFKmwucpgTBPo3jmxbyuV/8vXGgqf/47kiZcZ3hbxDy9EaNY9p6ewhNg0 ppi4irkiIzxMumcpAE0JK9g1rRkSq6p114iy36LZS0oTPPzJRajGrzjfQzKyxfLDpY+oQruzRKNR xmxuXPsAbLqPVLP0MY6JS/m7Tb3g+A+YMJeF/YRWq1xT3nYOzpbK05IalKnBBG8xeAWBIMLSuZ21 MqmJLXg/MPDfAOe5lEdOt/Vg6yEQ7Ncc8dhrCzqJglk8qOm1S778VZ9KhZYoNWTjvvNW/UjwjtWT dx58clIjDrCwqwH+RsieavDwY968KHN/Dtsq6BAB4THAnl/QfGwoYqa5fqhhrlPRoRh+TGpPcQ8Q CaHsLqQrZHEN7A0aYjZd7uSBGyOUTWP07AHZ/+l2DYZyHBdLNUuQgMYiH5m7RiTpwN66Hzo9Si08 TMkv7TZJ5+WIGSgvPKKupjVyZpvdGctjy2o/RdcdsFzyx0g/uWZ7QbhKv7e70xnuldEnHHZ8UgKv 9OSTmvoM2kBHz6QqcQ6THwHHYfZjcsswbk/QPF28T9MOWbgW9bR7aYfKmnjI8C7+E/ojoapiMX9h 87Q/EZn0YG/tF9nDxFq+TogS9osDZB7ZO+TbMcEH+tQbbZE68HsThowRPNDgTlnZsJPm5HWaA9EG ZEgFWfwxZfXZYENQC4jMJaAwpS3vq9uO53g6whJsgaABgElauN1etP01Nsh9qXW2h2bSL6SG/v8j I2fcg6fWpC+hU7KYtyip+in64onqQKJWxTgJFbtClCDk0qge4gnWV+Zc8WIbCkAcheUNFIfqlJz9 MfBYD2678RVN0/cNlwMNQjxuvTpvz6wGa05rkEuTaFeydT57IJxN+4dyEW9WJvR10neY2LO8gpkH nXCsJoV0r5Gszrn2GenUx06mvTKaJP9mB4LH9zNVPg5iLw3GbzOoCUYwXudrxmCmjjAhFd3G42Oq TUd3bSwze8Xc5c5TxCKVGqc/pxKmN0C8q8+sVa/TJ3LphfIZ0ytjAscGhCKtF+f7mKnpd/Zc2ijI yhAGXoz39XiHhfKDPz0PuTnnuUk3CRG2eQTNdLKLR3VxIc4V1Fl4CaDHu6nzmfA1DGMrXHOjfaJJ fKlzkGVe6vn0DOFbjIhO2YEGvd7dWKU+7HdZDcgljue8VaNnwP4BwAXk6xzy4OfI7w8iK87M28hV hToqvVx0J8zQbFsk4a4x5ci9gGCxez7Lw8jJ0ogxhd7NzWpXeH7gTnEQxpthRx6eKRgllY5TNvd0 Yk5eMrDC5NUVgYyk1TCJnMOBQLMrkUZcj+x7hJjv9XtAWHHnWgCE2G6H35MRi1Tum1nICUwERyC4 7YynluaYYPCwT7hbioxrQEZJ0NwPn2YV6Sm73nbKB00cWaR3lvSnbpor7dqV3U+Ow3WMc3G0OPcq HZjURhP5nnjfULsRVqbD9ajVtwyj2CfWl24skcVHbC/KrbtKCwIl0vv+OiKsfpVGkzAZtZHVJUzm O6gZK/7yleOjIinbpPhXR/YGv7jaPsp6qbhqXG7mAlE59uZDNWzjS9xqTAOXtOJN91eYcDAmXXX6 SYRTaz8UVaX2epkaJr8SCCj5LrqqXn4SZXdZhYsHrMI7GKidWQjVcS+qsMz/fENMkEbtdPFU8PQv pIok7MmMmzJ9bra7OrHTkjT1YW8S0MS1zTgdreyW6eWjq/GYTRm2XXVj6YBUhmcxOJetare4whCT lduSK+In3sPosAE9164s1gbRm245ogCSliuuMo8DKQ/3dukLl9CJ1PUCCUa1GPsb3GxcS48eClwj GoqXRdYy4eQSHqV9rTRdTTlVDI0csOX23XCqhipJE9zvM4kAHHIxSrJUulgoRXREBvVLPPm4Ni+1 Hg2JHphOs/M5JTCcWIQzgjJXxvFRNrGlC7miJVN9Wf3ahkeh4g2QhSEoDJbief396+/Rzrkg1+uW +GISeB/kHYZ/ZpB/9YUJlByu5v+p2aTpswn0XidDJT9TWaX6n/GBFLKPLfCFD9f/mThY0Bi4m+Z4 8f8zpttCHcNdbJmK3Pbr/M4uc9W4c2j0Ew9nstJTY5TbaV1HRqk35RhY94+8epzoy/d7Bss2ekmF 6dw18pXCIIiKAt271nzZfSPiRj53d1saVtJikEgZxRYsO/0vM/lslZWWa13yv0KlCDFIkZ0Q4chm T9uvUAUm+LaU72UfwTybud4rEsoOmUge8LTxXv9SdGrBFnMy5jZGkuLM7U9n990YXuLbcNrCSfHL rZrZDm8o9P9c668+m6DYdKLK4x+dMowpSnUgu+AUAzKtFooQy4ExGzBOy/MzMmVVy9ChPyPc8Mgf PaFACYOD16eq0rRV/PNgVdjgfte15bSppkZMHmBieFpkgtqqwmk2pX77u/vPqChO4Nao1jL7RBlD mNXeI8EPGmqhJhU0W/Vz2A8YNnTI/+jJ6MZSJ2SW1a8LVjg3W2z8GozTSxLIXFvOQWhC9nQfsdp9 hbVZ08mEHAOjFaMWL9LsfBGbSCEdDEUrY2ecLaACrtY1OTAsc3wmJ38zx7dyvPcN8tGW+2c3sked mJT/+NzNZTSd+QzIMmQ61ly4ofaStPOoxEtaNvmSnCkwNg4sdjb0eWnTWIMaDpRGe0gDG9GRpgUT qtpi0ARpKlSH6YEDOkXjXdh9FY1pi5MDyFrwvg0qV0HRDpuOLY7NgAH4YcDmTxjeprcb/85FZ0G8 QNTGZ3o+w/4vnLK+mCJZlpRplfZwPzWdO4MbEy3Kmifl94sqIfYGLU9ITHUpVvyXTfOuw7EJiFgr +rSrBkcv3jW7MCMFN4PF09q2XnCkGGXAeA4tdtyaxTvbnSQSdHCoP70uIrf97NnVDVX9codkVIf/ WhBk3VxOfrRFWXNJEiMoY1qkb5pLBhrYVUFalv2bZ14tbCgukLoJwlptE+rdAlmrajtD8ULa79dU fMXcaTZNuZtvrmbDK9HXFzKpYv9oyyHoWlmVZ9WgEbi9EBJvRcG/uZeU3N5y+hr8jR/FvDyKhcDx +FmZMqWNW6Xm0iA86FCdIffTEEunSCPQAGNyHsY8JaLrHiQG1cwYpIi60buAlqO3lssnNqGMIplZ xKC1cCoYOMnNLJtf+L8F5Cfzo3eR4I6MYPHT8QzSKszbPSJX9M124QnainPFjB6s8GNqibGO7n5s y+43YUJhucUhbYWOM4sTOSkkUPJ9ICrrrhSkd9th8Iunwn//pxHS1rMI/gi4qbyxfqy4+ejq552C 3e7EDbpaPdynXgqQ72TeNcei8lmeHqM9ynpH2iOlfKBk+u8gNYwikLGM4kLRetT3i2SRd/8w1sxU 81gH9yoqWB5mXKQShoNc3VfhmuDzK+L7k2KSdCIovPge5anihYYtjXwIhUGMO8xXz9qmE2VXXCEm 8KJqhAKEAtMROVQ2OGrkC8HEZG7S2YIzrspwia2oRhYabmpGGpqcsMHsox2GFDGsEJhh2z0TGj/3 1+zfYWlChEwxAxLcYGBjFl54VynnhmdrOqp+M0shCLtTqE0GEZvAs7FCNEGJHP6p4amxfI+mQS58 mYaFrVprEPuhGFL143nK8bCeGV7I1HsdO5fkmu/EZsMOKJ/cHNMXNrr7pKLWeT0VcBb6Bqod4fxF K/mK0e6D1CAeBIavp0cWJhpx+FFaLEYgiJrrCFZbd5tRNaEkPcZPwJdCmQufUbKWSIhDdisagi6e hpym2q5XbBnvDNMW807IbkwEEsp6NB46wqfY8ofZwklFvjcXHEcIAxOLvgbryZYiOyqe0au3g/Y8 KS4TNrOZTW3jJxh40+o8P2QOG0dxFL3jIfCW2nkYVOLs6a+f8uwFw7/KptT9qP9QXRbYiV3M6OT2 J3m80UaJtREVIe6Mk+DD1dScXUdf4jbAXb4bWj0IimIil6LB3KGKnOoIerR+xRQBTQaYZ1jlkulI J42JalNrjxQpu6uEjDjZ05SbtD/ay9nzLu3r8LoTnUzaBNsZMufxOUZxo9A23ERh1g0bU4IeMDsW fn+pF1qftnh4pgm1X+qEb+XXwLRk7ygc+eRlbaWyxdts9yi3RUS2tiYcAGTn4fZUdkOdH/N8J/lB /YTRzkfJjF8frIsTJyrqAvThDiewiHGN4qNt4npU31fO7hEL6KwJp7PpAT5uuc58ZMVTiT9QmdFK ihgVKIIzPYdvsUoTsOBSrsVssm7YVZq1h/zVaIFVjxz7z7FUZIKYzHz/sNV2gQzvVu7VvZmER3nr V1AqEhGl75t1pT0Emkstq9Q90XNmEUWmFwschdlboPKUsIT5YN5g5kYMlXud477pgEUzj0L/26bj RBX3CkB31Mql17oz6cxkk1CiCUHlfk78timQMFJ4cCV8AS06ypIynUvvPgeQeVthdlfr1bcA186f /XbvKbykfUMPojxxl9yhs5c43v9Vkru62IWRMfcYj8B78Onf7nbh8biWecfSNPO77MYAiw/Vsdw9 CvoFM3IUg7epEjZAKZLYu4rhkUBfrI3vAWu69Ol/nxy6NWtwKY0pf9sRKZ6EwGWAEBjPdniI1C1s 8gPmshHYUgpZg4O0Fogmlincq5ZWMAcwM/queKIj3sIL65I/c5vtYCaAlQRq/U7d9iMh6+eMuP1O 4pAHuFup+4ttYwll3AZt2fts3FM5IGKjEHYH/TddCCUB2hW46dV+2M8u24KTmryxDeeFjlPc/NkT FwhF7kpqX6r2VCMhxawwWR9qTky5cKcSO+A9l+02cPkjzXmKiXP5gCyOyX7/3qViYS1AsNS3I8oV nnPab1BHfMZbb10ue6CO6mikaPT5SILNkEvCYCRLGk//loH1Oj7t4UAXgqk2WMjXZHK2A4NuBRFb r+4ZhsVt6KFTp/SL0veNyLSNhsH/2o9DvV9UJHZqIL8gRMx2LhP3aA6vfdFHpFX1OvwFoqD/jT9N 0olf7so+b1B//8Jaqg4cKwQ9rDIYTzeYvSBGynj3op1Y20S2u9CzIptJRFTC3AqpnkNfSCZs1uvD C6ErN6h2AkdkbVbHkAyESCRzs1ucrRXixW/YAopECbYSHfLJOOypfr7612K33RkRrPUu67Iffo7B 7zhDDsKmn91C7rWwL34KCpc/N/aCbwXg6HjRzIzV1Vq4TbhrDkca3fAFtAdZInvQUt1i2zKepAUo yNX5rD8stcgfLh5QessxkBf0HIjyXkF7xFbRS9lvOVlvvqurTayyctpmbfCrVE7KxhhOA6IweAoT CIDMg/W0nlMdkqkcAb0+f7pjzo94n3AKp1iOKoeCPzNU0kCO+FY8VmV7BnfNDtPcxYMumwH+NEmL oa42+CEFxG0f30K3FzkwEDJ8pXJNRuOp+YZqhT3LBYNhoKJ/R/RfKSE2zmZw3PhxEebimOIPAUvh B/7i/MPNsflFu6RpL5+DX2r/1gUVqa94J1hSgDGCO7AfFtcEhlF0FzKvD9zcS6UCPDkbMim3c/6M OXSCk+4knv/XYXg8WNaEnZmnV3ekJvj9tk9M6jVQhHjPVJz8iKtTYMOmMW6TGPj3KF7hgImg9fY0 xqeXRCIcdZc1vuGQTCeekBbMYR5Z12ipZmQ322xPNxNnfzQwuD9p2ZuAehGmeI0AJlH7YIy0tVke 2yHlFZPSAHNAbxLAz0sf1mVuQpwFaZk8E7ZEHHXNiQN4h0AXHSZ2DGWPnCzf3OXbBjhL0lF1JNle L/LnjzKbJG/2H6iQriRl6tNB6DrLUdmCSSUuj+LDelQg4d/9hkilgFs8rxb+ozWn0ggjDdRAQkEl oo2d3o5OWZkv1ngAa3yqIsmZswbaGLzLOh6sGOTZjQEsTjRKrBuyIpYYAPEL3QxYsbzzl1I4CzWr 5NaV1Pg8rUNR8aYbAnvTcg/0UXTP5v8FwcaEmJPGxRKTGNE9dTaZXyvVnLOb5ock7oYr29LHyCNZ 67GN8Penk/KObj1E3ZMfiR5oama3Q3ilnh6jB4E06GeDDJXm8t7BReO39cPtMJdohCMq0YWYt+NN Vm4yufVvgCq0lEdMityN1+OxCekKiuvHhd1+VSf7nZUOpHpL52XmGhYd5YOor5Npkn/sMa3406tV 4gnaGLYBst7GpEpYb2mos8XSqmPc0PFTbCDI2RRunv4He8rq3sQ3PcxxIkGK5ivKZDbypD1n4Or6 fB1+nerAZ/Bigi7Mu00pX6d5HZiUfVT/qXhvNYGXG9Sx4ITgm7w7xc84YOUPA9N3cZhi1JRlH4Uq NJi+XHcKR6n2t1Ayk2KWHuAy6QQToQvpi1GJ990eaNTfS2v258HxnefA2AYsWTf52uk7it+C1bD3 Xigk3vrJlwPVwi2W32pbnYUqZvKIUj/MQg8ufDX4Clg4OFys0u001aLR+moORCBU1S7hUxdmT1f8 +3xk06rlMvXzuOXxkjIddCkRPYDpBrIOWaVFYktOn/fE2edsIPSKkz88lW/RYSqZpDMbZ1hxVItK 2RbZu+18O2zBkzYgbrYTAFETCNLxA/ce2b1KPuT6OGunzfbHTY1EUnQIuDLZiimL6jIcDkrcQ6uC 1r+4vKy7Atbgqadn/OcWHIJKy3XCa4NoKIdtj1SKNVNSdHfREIiXRVfQlEFkH+kO5tSgSPKjON7M MFDWZ/fzrOXVDJdU2+HN05J6pF9YIXbtDwVR2ofGyI8QjVofOiFsogfNsIwCZoE/uprn7Dg2xbik w0ftQMueOIo9YlHFJEms52N2vVedHHCsXGwteZ8zkcI8ng4KwcNLuwAj0vczD+AbQ36OsV67861u jhIsbhRpaj3wP+7NuXigrI942QHFFR64vY1pvSr9kdsQmdw18WiCmaGX3ewdezOkZidAmZ3Ac1Z0 CDeM2bEkStGPV8hppeOr78dKQMcDscm9eD1fkORabZC7h27Mfy45uxRHvb36qWhGU7FqQi+//nu1 ZsM/pkivAvp4/QDrnCSH4CGD00ZmLHm0M3b4hDlUySUBoAguRvktnDB1g+sLq4nZI0kE00AolAN/ 7HCQbBpuvkZ3KPz5jzfqmj+Ir1peVSgboj7bn49bI0QVx6boNIeryp/MxyWvRFQFksf3Ycum9k+T ew2CPu0OLWkZvh8F3iEisomKAHO3uhN7Bg8L81flF9CcROf26pm6a+u0ZyuGgHLmO8BjZ7qEyH0F B7NYTjuSRKST3gLRmWavwilgFzYlyhLN/iowlEu/R5c1K7lXyAJ8ZWD2pEk8B1ctlvEhlEjbJO7l Dda8NwSl0JSf1dgO35QEMMypP0ow0dPYJurJttdb3TmwjZTEwli0AfREO9DkYrJYVcBipc0eotMd UCMhE8cr4P4uH4+lWbmRGoKag04ZVj3r6ZkLw0TV6XGdWY0ySkLnJVv/CXG2Jn3bIGlf77JyfFUv PjqSUMZ81kc5bsZsyxnRrJZ07fc0RSZD/f5LzAZF+6hQ0nXOhyDtXOI1KEwOV68aRgrl3l88BWpX x4zEieUyjeNsDznrwjdbsQvdoPaZqR8OUw7qWGSc0ZdkKK/d9/1piZoRVNyEgh9IVoE8n4lCYktv RLLVXA27zmrGw2GdBfcL8aftqVz4JaYjih1Zs5qGIbs4gr6P7hHTpXFOUHttHmBwAcgZSi6+kyiX T+bZCgmRd/hD/qFu5M/CHZvsdVr2I4aq0WBrYDaer6PZ+4P0E5T2+5jGKuIFwAQet/anuvDogGHL ylTs9jOYpD8kdTQsD37KuT0gMkDebCaRV5IIw21QoLXf75kYDRmx2xqENe6esK/szDKUtbAXJ+L1 f5kJgCnt7FFthYQT/IpcNd99JhG5BOznPuQZ0gG90k93eyJUiIQWni6/INDhUO8McQy4WFHjgYla UC19d2m+gegTUJq1tP0LoXI2B6bNtlURqoBtDTxXX3jQ+KS0WzkUFa5KAnkw1AZaCeKnIowC740R zdHIoGxrMvbaS8apLeuz9peshR30KhyQmnL0sHvT3RWoaFZgabl6jEq5isE4YEMLP+EVWvZEhkE3 htNtrrwXDbbblZ2hy1BHiepCochagoz+ZcYeG9cNcmlK8odN/F+MnVVgsWmSOM2MVEBJlu6GiMX1 Zct009KFekdUGLz1XKC4KE9JJ1Uf2FfIh283Ds20V+uCMF6jt3cQwYUwdzf9AAiWg6CbxKK7AuI2 qhP8WpohaPvBJ6FfZ1pSini3y+EL6w/1hEEikJtM/IKW9/nwcLQWTTZq8nDNxhmZHATkg45TaAtS Cp+YjkCsCdKuZ3NmDPQgP/XuV/5ABqAdr4/kP0KxmzcyqbEY/ty1Ox88XbTtizmVxohp591lWG/q yKcMMyRmgROg8r/3kDOFUYO07JjVECVyRcmsvH+ArHN+M+AY1XeG4c0diKKLFjmDqlyyXLttm+Zl OyMUwzaP+zp+CQ03VBkDV+HlQhUKYcimSN7IAvfCbEps8pj+nArOH5v2GhyXDOp9dzpw0+eq1dei rEMNJNDq8qKNPd4AvPbyp4fK0E8Wdoy//fQltEKp85TmK85teur08kjrgEldeG3hwj2WDiAru8xo G0NvQVmEyofL+IV969A/eyvDms7y7ZBdcrhLYTo7OWNHnagbsOlbnWgi8HBJ9Sc4sEii6jdEvwT0 QdMhEd/50IXpB1M60U8/XEarei2O+A6lj2WKD8Z5VVjOxFBtmHaBRkFfrs80Kgii4Ez8Y5PJi7uk fLE6cFPQ5D8FCvt4U3r4JsFtftMofxZyg5lYPcSIeGSMh+koeqznk5SrGbY8SP3EhoNrB4a9R5/U a4sKPSHd+XbpOwvyVmvSmNm2cncbcsCok21O/VIyosCoBFsvteORkH22HeNZiZvMFPCiv88TyuMM PqCV6PY2ydzYL+m+5X4cZexFKy3s4WN8FqxIkpr850Em+xyl3o1joqVdDdlbke4PEgNJG7CPQFLU OAVGLV+UsRt4Xm52hhW+jvbfww5/YDXvWWzY+n7fKczrQgEzl91/iC2C5ndYgVyUz1Pb6PBW8EZg XMJ+p95G9sPCST8FK3Lwrk57xVfWNVDgowdG0ndan10mqLNCgFyDumZULsgcp4n7LkksO7ZrZkWb UacW3UyiPifaPT09Z1+3TT/IlqOzWBT7j/0sGJuPlsmr8LD4z7Nxbo2QfJg/i+PPL9Hj+73D5sRM DbOMO1igz3fwVmSveGwFUghbMpSFuCHO1i9bB7V62X8E2eqjkIgK6d3RtJ9TvcUyp5dLZsA+32j/ XCMp2NRHqQL2rYMZBOc1tH0E5HIVIEbKg+Pwyt6yF4K3TkgSoiUrR+dYgP26lFPgEVmyrH5f6CaI 1S5JOVm8SBqoVe1Mo2vh8FGuuQoOQXB6GeSnT5NADyvwIHtGIuXM8JS5Zqibo8UH6XDZeL8HPWDz DqVuiXZl0BNLblokbgqOY4fzasI9v43rXISWjGdKRwpfsk8jFKk8XM5mAD2rS8K/IQzCO4lFRAOa A3XQfhhIOzVwITHqFnJqv5HR7yq+7Nk3OM8+TFKcD0lJij4c3Ddk706xTKUmdE+sdabdAfVqgVVz nusyNzGjWUFm01PFaG/iIwOdXhC4gH2rmYWGH0bLmxM30tA2D+4T+bHuvEacU8nrwXMWtBkfgqL5 qDWuLN82D0GRm4vEV+xC8+CgPC+j9d6eSVe2V0aarVfGUmir1nMj5mbGfamHRucVnnNnJ/Y9Al26 K1fnxG1M9FyjvHW0SXIfBSz9hrziFYQiCM3tXOwt/hCgdWZc/UGsCFN3eJilQBmhi+mZ+ufH82Dq huKd8HhyCNPCsU6dGj9F5xSoNgpamS2NxIptQt9MJ+A3lAcVz+vQeZiSb7DNLQL8H8jFj5lGUtPb nR6vGKIWT+KUVV05C2giKC0EdT9wTrtKEmW971cbsiL1GAVVCaxleBOuh1bBe2gFKy0cb+JkhQLZ jvhKryQZqkmhnJaUH8m7F7okYZhpwAjPPI0W+oF3dGNc/kE8D0AADExTqrvRojnA7hHKfAAFiq4B w+5nlgVsEJz7WwOZOiAEFs5yOqR2Amh6LjQacYhkS8nez26tqcE/Gs8d/VkRjKgBYiLXJ7WJrwBf rPGylic0S4RqsxsV97T1cbfgZsfv9hOUhJkRFqUg7H3QaSO5wGg6+wLv/eKME/8PA9x1H0UZxut5 w0jgaM4748UG8wamk7ZmqYTh33f0wy9iMTuogVTnoYfyppOKCf5ztxF0V/6ACk5l37KhEp5hgDNq vxoSi0NpwvocJ+ftjvryoJ39MnxxNKKBGrfSDxl8l8fhkl/I5syH7WnzC8xhVtEWDGoqCqcO+3Mi kUOA0rmK+sBhaYYlPJBNAvMn39t1bmdcv2Z7DOsMoLtWW1lSkAiW/7vIW2xLYGDYyWuL/xgUJCQl 7WKE3Yp1hg4ZOjSEMED1/bVghG0vkcWLh5SiOAX/PwMRz/4a4yu+DwP4rL7fSkWOxwXHMZkbF16W PjBMT4mb18f0e2D/XrjRtWLh4R9WHLjsNmvAKHsmIob0G0BUqbdnU7ti7KW47Ajelxxy7Hta6z3m laOJt3/6FE9e5zpZDsy7zXdo20HXq2nAISeQjE51g7J+g5hJjq8F0UOlDpf99RvWCQtNHY8Ga1XB uN6303FWtgeVRBexcE7WDbdGpiOk11fkFmU3bvGz9Qp/G4nP4YNH/UurO43iGj4v/LMqvaS4Azi0 oujyY1pMyMm8AXvHZeXtYJGu0DBLPtVOeJGHu3LZ/2SQfqDkvgX3AFffg0gkZhAaNPNluNtM8j3p M0p/HEHcZ9wdEgyO2u1h8uc/FoUNv9fPNIOJzvZbrnPuBYBrM7BFyoiEmKIz51YDP1kNByGWCzHK 7Ro0Q4tllB2PGB0qqCJjRA9uYpemGTYny7B2yAv19j2G9SEN3NdWcnIMto6iJd4Bkmzfx43UCJP4 5rtlaIiA3y2RUzA/VPLNU7W40RDVCdy+fd1XmO8d0bVFweTA7zbGMmlt/Iqraoj79fhzCxZjEJ6t GJZTlvMiteOgJh2XxdhimxGwwiXqnG/YGC1Yc5lP5go3Wlw2RNUq8swI1Owivo9s1YZhJ+FAaCJb CaUPRdK2wwNEBfoP15388iUhUUdAr1yTm1xKx/ZMjmhR+y5j3Jg2uNj8wag8AEXOkl4nc+sPQzaa VkunqfAsb1p40DD1Ljo0wa/U1s6AtQpG2KnH33DOYO23iI5jqZPVVEUWLpEPrvzOE0fKzqYaG9Fs uxrp+blPOLJoy3zirD8i1VpCH9J3NrPaMfAw3s/hXd28uTiD0APcJKWu3R4ASj+nhFf/WU/KUu3m V2TqDToZSdp73vRp3RRD2l9GHzAES/eTBSVNMDl29YVb5gGRORtgn7aG8iULTX26DJH7OGmGQKOi g7AzDGc8OGUA6yZjkVazrm0hy2bJBZHuRrU+2Ax0gjamTDtq5p6movKaq1d/1AfnFD/BeX6l+uzx ypltO315q6ngMUqph4KFmOooTGMv3kkUKQuKfLwfZ0636kW+GNoujkviN2lAOB5PtawFwxkxVh/p zdcMis8JgbCI9XOzN8gCfaKTLN5v3O2UonxshYRx+blxfmvw3b+pN+XGdAGXHec22vqIWTsvphaD 52E8S854an5tel2HN5pONs/Dt9sDvT99BN3uPq/qMWviRaB+p/UxOoKF8YuLQSuOeVlnK+HXas6l 8+hrrV3NKXXxfdqe6i1KJEkZKlr0dusCS+nd+L7MoApPFBInB6b/13LI0penA/uqEKJTXgnp5O5d dR+CMXcGWMd6izv8nPHCgudPpFoVyd0BhNpqD5UZY3Ug1TdhrEEx7Mj/ZkyADKbsWeU7NDallJ8R g3vDkmQBaVo2LPmCvdrZgbDJL9I6B2F0W6JSkyOoM3UwX5fxhHTggDfKadU/WR3bWhLSRoaf4Eyu v3Csh0hrtQOaVLSWVR2p9MZQ2iqEAddq1et+rT/vXbSIs/ACxgX3SKJp78yCL/Vza2NCicSwrwW3 lPv5+EEJ4ne41Q9m2Ye+hTSkPA+3hP2rbHQRTcoqmWUo4cYKHXl7vV+TR6Ty6zAndGS2xvecRV+N ncI48Yx0Dojf+hoPSArufx/OStllTDhIoLYxLpzSFaCvunbr48Fhyu3EmTqiLWxv1wgVWfnOFgYR C05GGLNF7Ok2IGMJT3SY+cyjeabAXxOG00e8JloNfpCm9Ckdbsc6inTVVux6siX7YeV3Wej5Css+ NWx3vpziphEgNbiTzUW3JpqdByLoii2BbYz+/QaF83CMGVdKqhcJ1kad6QhIbNe+e8VwbhobnUll +iiXt1VabmcDfFYc8z8Mx+sUlE9nIdQ7a5UUqeFvDhALT7049Z8vr2ThCP2u8C1uuDEXCX4QpS6C 1qEHJwBhaCkOVkZ7M8um09rsidsTWGYYTsbIvstk999kocFkkO1KjXduhVc1iO40foTeq7VY0M8d xxG/J1uwSd2QM4ZeZz7mgWd4IW+xZN8Sbldhlp7mok2h950A8RbnmK7/t5w74BRynMKLjl82b+0w V2dI4JLBxIeG+2V0SFzMJM2Ko7sU6iDiOmX1MhI6p2p8eRZfJXPoZiVmmWtUOq3hiQYejrgadd6P kGZRFPy9FHFgGm9ng+rHIsiezLg9C7z/+yqfWWcV2H2JHT3wVFbZaZNXrLuiHDqUGV45IxZscHNe bsfFiq3bNFq+YseOitbh8feTbQ6wbhlZIM71ZSntnDbgFlYV1dUMBftnDwuv3NS195izr1as/dT/ BoZjoiCDH7HQ5n3JLtsCmTdfSKSmuWvprJ0ElP/doWZmbdOWct1KtKoAdjMNGRcCE0XiAFuxbmqd XWXIzTX5gKwtFnWS3EpoCRx+Ikecy0+1ck+qOY/yQ7TUcCcSBaC3Qj36LgmiEX2II6dWMs5kJIje U5Tk+/KS5HaMRvAikysgyjk1givBm8ucHVf2lwOJMzdh33A2SXERxzPnUruHkYzKFLpKO+gRe27b gi1rVm/JXfCNgifcHDW6KJbUYDiU5DVCJbVx3hmvCBlzEblXvcIli7W58bG52P9kWb+T1oGoCBkx iQQHB0ny4JoNIXOymwdwY0GaozIMtsWBFCwsHaYWd9d4Ae8XoL6I4JFqqi6CZ5OJeJMNougLjwh6 VDa6SsTcaogvJygYOu2OKchfS71pECAeZQUUfIJilH0+UgBhqnv8gyiFxw7xECm/PqGvJBIsleRj 7KuZXnGIKNE6nGJL/dU94qp/BDHoq+BpnOChJv4a4obVbVHLjOQiDTBmKTo3Am3e7DXMG9VWNYTp e04GpNL1WloLGzskow6sP/T1xoPJUYARohZS0I3L0Z1pMfXh+uhG0zHcXckrPu+MVyjNYnk1SpYk zsWO7fQkojFY8KiEATiLeFz4uaYnyUYfqhFEsaRdrF64akJ7E7GcBMS6iCbwwftHadJzaNopfGZ/ Lebj3RUJT829MF5CajQC8AqNZaMVCJ7/Z37MFcoxwcYLxMvcex/0tcP+Rw0YtXv79q0nbLtNffAO dGb/a2KCVq2OgX2o0Kh0mKw/Ufd72XlLLX7dNMSdUiBy/Pz2A52dQ0rX5b4yOTQGXzdzWrXZgIPm huGlXQOZVscnj7Uil7uSFLGbeP2AGbADMBJ16NXxyfirUXWxWQSJui6GJTTUdcfY/LtnEon3EuXh 7QHihtcH+PJugXewBHTE9TW6ZmHDgEJ8hBGIpKSnAKtGVUp1rNHds57H8ekoXcGwXR02gweamt3u +RsEz/r5PWW0WorIg+Y99+z4wLLNtw49NdoiD7F47ffNfyoNlbEuxEWjgla7er96nl+BBhe/bM55 tuLqSx525Z6qB0k4FhdzT79OGL5msIsMTuy6AD2AQ4mBUfisiZXA4NaCNWPc9zTSsNkxx8NXCcNI naGqQgn1cvw4gHv9wMPNvQMlttW9nFxH2eLBSc7ctLlHDUd/1GKJ7IrYx3FBp6/NJBtGa9SqJj2a A5DOwvSt0rw/IZDy1sVvhyjlGRos2hgav6hwBfE9ihNmu2EN8pIp3bCdv2xKDNxwe0No0CYZjVxI 7I4+BZCMxrYC2Tq9Pj/dwE3XK1jXkqzcc7UU7NdeZZUEx0oxPNnN48T5Z2RFX1+4rWQKv03OKbkt OgRrQJFP93SzRe0+O3oS04sVw6H1uh0X18BhE0Tx04Gcvvurcf+33xiC0ZJJGOACATA+HbO45NVI HQDNKKu7eHjX7kmmvilQ6XlakLt3G3gUTTdCFNsodgVXQQ8Vg3xH9/UQOuRImN0nxTILH+qenlUj 9150gdm7uPkV6kUUIeDDJ4aHIPv/QY7jMCv0Y0ds+hqSUlmIkzlgfOHJphIOi1fzfWim7QYuRjjZ g6Wy70fop/FCLE8BntxT20JteGm/U5enWidYxtBa9HYhGcsXd/mN1kDVPuj6iutP84joTMOVgwuP 2XA+BkquVgvggxz4Gw5SpUZvFdzWzQKfxgbwwyBXnCp0nqqOI7HmYgO18wa3pHOpI7Nqv/sOxtxH 9/u4Cb8jqgKbG4BX4iqo/kpUNqNKtsPa5aKzSs+KYjG2EDZR2SsIoqTD2jqmH4z5NBGVzNp7gxYq Vje8sklphr/Ygbv+PVXxhZq7PNZNhvtwcjp27CyeobwaEd8B4EZSL5T8iTF+DCkKbNNd5Mg6FJks tPuC45KI0PGvBpzthG9txky9FIavAHDAf3+iiRooY46D/9wtm2xbOAHEjcj7qb2blsGjofT/JCxF dUcuX7S/HRMvcIzK6EXN9dnyiZF0Dao3oFffoiNpjhu7eRgHMJ67sC5AyGIjwJJ98c0a+OwveRGQ GK7KPZCQeHlRCj5ovJsUEQPEEt8HKaI46GYgBcWYNmtkrNUrrdDmIBX947pWkvVrtW3oiyLwmtRt XzwgvjPLdzLLIxfqtqZ6rGiyMAqfK+P3BQW/Yctko132KNdK+bjUnvCTi6lABDO9EJr8Jlj9CPU8 +ZKtXRy0Yshn84aGfQC7jiKBxgMlojQ7QHKZ18gvm+rqkqc8vB8/kiWnhLLGA7jiboE9xTLszQOD 5N1j0hAVL/QrkBZuaBtPAb7xx3IJrjHSITxrkFF1/xRDBC/VjkcBm+NsXbbRjT99tzJN+2WtDC9l QPELCKWsSc9oifwGOUST0B7Z4RCZp001oZNtzJUXcuTL9ub50j8u7xYFoJNxXF9eH71t9tsMuw/B 9QfloKhVe8JkyTClirdBqBMyr3k+TxHcb677bi2yCyIy9HHVTEgqtl67rrfkNG9nUWr2GmAWl7n8 TtkdVlAoRNnz9DxnyGrkT5w6XBrUD5GsAtmFahq49++ANKsPrXp6IAmeHpNWO806YP9Yz/DdGbWn 1jqMcgd8EX46PXTlUTflkOq9+/MLeam3dDv9v/35UrdCKDMoQA+HY+AGdB2VElxUeCwesX82NfWG P8r9/Y32mQ6dybqjs839VOH1AOKrazN1jIm1+dPjCanfXkziLCJsIw/HhUcdCRvRlB4y8flBeTxM knqP3gL8Rssvb+n4toW+IzN+oPsURlqm6UYNrjvpadnrpTrb0L3FDZiwa7v3sHc3FitTJQSkEhNu oPyi22Fq4O9kqwmsyTGok4XP9I0jT7UDQWjZ3tmf+vOeLD0kNvCg2Pdp58ho9L7YNsektMkQRZaL ds6oFPB7rgNliNQUqrCiRNP/igk4tUyFeRw1vLVzsqhsRptpQFc7Iv1B5Lf1LVFi0fv0D9JGTDOv ArCYrE+piv1DRH0k+bnARrnaUQ2VRFsnwJLEyKNe/kWQoYR4YtDjJs9R+dZaQzJ7U20fboNdKzul WhMNCUjSa+osMaoywqd6OBgfo4KFhpnrqeiV2EFl0cGkRPwTDkCTtcPXjxGfCAE/Gt086ni46MYR fOY7A4XMrv9cdNh9DctpCosvvxx7W9rHNncnMFevYfelj1NfgmqnLcs8ykr0UeoeXULaKcXvb+ub nt98KEKu8NDOCFmr/2iFkgkGFxyEA0ZeMi6hOAUMjTHsbPghjOLdJDZVAPzvUqv2uqp9hPMmPV46 QZfwIyQ90Ktef/RJMzKez1GtHKvoeDEbfkbgzxmmmBrYfi7EvSQziG1kjZKvZbamuX+ROthFHow2 gMR618uqwwEex2HbitCCyQZSD1TZiexGuAMnLesjQsFFuQyEShrryoWMlkc9O0tD6RvlNTBPu2BB vsVKTrJlwYYH4NN1PiRcEtaKQ2DqzmjAcJcB39mSvYtzv+KxYHfKqSOpVbIULYpjQI6JEJhYwrUH rr3o2q09UAE7h0V3EBoK3WvVKAquRJ1Ex82cujbNyQD43HdMWrjcfNAgxBTDo18BcNPRVMySb0Qu I9Cn3exw42LnPupBM7qlGn/sE5gLtru12sdNLapPozQjO7MAj10kfx0zGtO/mn0boNc+dZgEwWdN kPuks0tazpMklPs4/vtaf8R/ceydT9odMXwOSxMX0N2v1YCAdXo5empax8h4es4Y+FL0wGnrP2Tt Dr0yfYde4lzuYBtQIRO+E+5mxnL37xVh4wUCBpF/KoR2CpnSQxUjol+MbizKe2CgU4Lr0L8fQpA2 C7v3i/IhIbRv8EJAUjSash8kqEDX1Zd0gvHflxnGDl+p5TzLANFZ2OwbCqrXmOgOk5GMOJZWZ2sz YtRj2Mi3e3YCH9y0MYDZW+1W+iPxVA8vXn4GqbuRV+yHEj3Feui2p5MtIGn6T4MTXa45AhyqAPMc P2Cf+4FCwSabqZLjaZ2frymBSD3jnqz12e6+IVX0n5TxB9xgAnhT+0CrP+xccBRbEuyZKni67Os7 hqn6UF+nhGSWd/kWjh04+pcXzpSqjaZSE/VRb0QYcKZSrn1SeDRDS6M6T44sA3ZI6AoUmCzLiEIc 2esEy8T1//VLYC1O13851iaEVyZyMEm9Qe/TNmZO8cM3OLkJwz9ZDA2SnDrTEaq7ty9RjDSR+o21 5NC5B/bYsfGixJ4Vzl3qkQ/s1jBtb2b9fSBtFgusVyUzWykGROZMd+ZBbhaEerlCgLya+DBTzUXf QLK+n8L0lXnJa7ZsvAYPLIIvSYMBR+cq/LI1LjAPdMaqvkUXNBQjOoceUo3DzkKqTNuAWPy+eYZo /o6bS8GppssVnB23xEfDAsuuy1A9xCvUjErNqxQh/jzPt5DnC+ifGnXVFSE/iLiXNAd6/dMAJDMe +N7xL9ytrwivuYBbJOLsJr1Bhi2gEHDv9SWI1hmM6WmuOVGJtV08p1pVg3jmNXrrZhLoTi8Y+oLh dQ5b2qCicBhshCrQu/zvHF6wNzYp6tTFMGHIiuVWwIdldcOdQSoq1Zt1U0pP7e2EW2X54RBVYVOH fkRg45yKRzNprDWzTj/fem8gEPvTXZZuF+A26itbM0m8i7vn2sQtSHC4XeDYk1OMuC3FI/P9JXHQ 2lFdJTxdbMQhmBtir0gFTF9xfy0pN1uC1KOLmJHLNcGqTOhQBUNoPg23mcyZkQ6AGpwrLHfGBhzz HKW+JfREpwg09N010PQ31ePwxDCtcyyBI1Vzrd4NBk1VStl5ZDV8EEppvD/C9kKfmWNJ9P4TnIXO vGBjJ+hPHlIhkHRNVrLcnc3fUg+bceZC9p8eTJV1y6LhMsNs7qKU4/yJunkCLJoyWiDdd1ghNhCY DJiKyZFGgeeOZkwemEbAU7cYBsnvUSw9ioVzPqZ2oJj+Maa3XXPppIbgmtRRI2YRHEf64PNy0Esx fGgcdLn//mM7eGczDRE0v51KmktetQEIHJq4Qfye3PIJ+Jz1ERwvfi/Xtk8f7bVcz3RbmER7XtQ3 2vP++H29Rwm8pv6LCP2YuwSSuBBEqay+6t8ZEUJ3gnVYjKGQ8RxzKjFrnwomBTVrDfN+6OUj3Od4 1MUPXvVh7aEbw0RvdYYkDBV65vfRgbvinnQ+6iAGdnMDmKirltaTYDZrCddBhL/dpGUAQNrd2+WM iD/2IgfVCYPlThZwu+dSJshzdDW2HpPLHXOelp+fNkG0KcnqFkTOg/TbeTnZmOFASK4j1EmTJh4P UMIsliNG5nhcJNLw6AL8tBE5VHfrFPCZgVFPwc9Dw/P88vty1OOrE1w/fEFtScRNZedrGGuT4HgS Y61jUES1zvKyi/mfeWa5zcreH6r5tyG5q9zOkswghvrvx3TssezwcLl+dzfWmsOD0a8Sp3XszPfx KWSvWk1LGxf0GgGHqVcFhxzCTCEIMrjs3WfpVyaAoHvNwgdB9BO4Zm6ex5ng8j1TzagQRJ76ribt byF9lGBpSaG5Eg1v9nJ0jJnzPiU2vdoYttRjj//CdFzmvKIVqft7V5zf0d6Nfvk70w5jhLRcTser XC/WVPne0b7BO+qapT0PPiMRN+at+JnFPvuYyA582tV2r6vKZrRmQe9hXw8NWepojBnPsGQDP2mQ w5XaccB6SiOgOoksnHf9BuzyNBGAfTSUC4e3ifbsHPb65J8+HjPXnhUmoL0Bcc39CPzvPJzAhWh6 tiE4f/py4eNaydjHQ14vc/gSGpSI3zy+V1gPlmy4mdsbVxnDzMFtZ6mwBSE2E21r+IYdkJhSC0iv aVBhZbWf9M9Iqbs5sPCeSWxhUZdOjZWVUCW7T3zF/HreKvR+U1Gd/rKInTfoAeC6BUyl/bG5vsm6 u+XpdjJZGfYIYVvxxvsmoyhKPehktJuQePfvWYDq3IxgY1yUd8zXknH71m5TykICwmgZmePKKfER zyrzMb+O3dln6K79MxE1357T+jysA58fYtoo3fDUYsUQE6eKVtxXU2iSl9AUpZAMYmcfYJeyinsN h/2QQSqLkyXy23LnINy2rKvvTxjws0Z/O0WxvZKFYKcIycXKMjscG2IyZDZf/HZ1BF61iNpOHql4 n5taCj39DBTX/wKN0CRhe3of7P8nB1HJU2ZSoGP/6YXknhplzttUr9itXi81FFkY1vLB/3i9CaXl ujNUdoXCGIQC8L217+lnRHGROOCVpIXxLPfqnmhSJBb1g4Qu/0gyO4IvJTVLv7p/mPdFttiKpy1f ieL9e7/sxtSJJ2+EIBoaD01zcM4PQ3KyKPZCY40x1ZNwHYMKTaxxo8sJD2sZZQhkYzdNGtUvdTIi HKuYIVm2lQnjno/Tpe0KO9sq721gfyysWP3ujQkID+6CBWN8sCFG9Vteccc6ksAQzBcCQvEPXPKn ZFLtgDzr40g8qQ+H+KKZfYr5JDtInRZfSlkdCin4xewBaYmLEBTRfeiTC90xPBymjGJiAbu0ntn8 df7vCFPa4lnj2ZIG/zyJ50082pltSRYmw4jtBgNxNKwKBtwPrlu8mYoFFyIud+q8InUh9GWOuU5Y JFW7Ykzj4jBasfncXabJYmHDxWYoUuh8ODZUrox2IKtn2jFVWWlbm+wvpy4XGzz47MXh80Mv0+rn 9WqqXTrMWs3Zb0CF7yLGKGSAezisMLbKWgKjVo57Mb6G6dQxKPDjvu3vlWmuy1eGxXJqeROQKydo s/iv3+18yQl7EFhAbWEGpzTgZtObyOD5bboA7l1LFWO8sPo2pmUefb44mRaY+uKBZtNoGywRJ9x2 uQdnTvjTBtWtac3MjPSA/1oLuwC2m8/bpuj56Lv2tXbL7bnfTjRjsWuuLUSH1kcgKuwZWVsDADsr x2+0kLPv6OIqqOrzZ3g75lh0FJT673yfXbEbWb/aZeeov0Jy+mn26PP8hkQIuWKfPsNQ/mdjMfYu hzevxb9v3f6vJS1SgYl+cViosSyhOFlNsRjPEH235EiM2Vy6S2zodA0aVqejWqpnYwFbAj1tHBmt I/kX7sV34q3Zr+UapI1yFMr8rkpsfO7yPjz9Pop9i67tDpldZ/PShBjJrRBME4b6a6WCRiAAksEP AjSuopLJFwC0a/TiuQ/QcJIqm0AjjiMTmNyIhym+RYISyU4eGNHwzJ2sCxWAwkf23mc0BMIDIXgV ilBKwzfNg+W5+UigLHlLhbfxL1n9VsU2QqB2/znRqKr4Gu8kYzW+mXK6etQmWfZFe3AzKyB9snP8 sDwEM0IjBkI9RAHPpkn1LBbbHRX06bKWtewaLh4dPo3UjAAZepPSVM46i6YaFg0DHhAMLlxExbFW oYkUyVl0vXTSWWI2yI5vWcdgW75QfLhV8JgzH/adYpaDS0L86uPvtAK6N77YOXToJWlwjMerX4jF D5Oo29cpMJ/U4y/YNHhZBqjPmjWsO7G3tnPcAHhOv44mFHD3hq1x6bLxy1UnLDbuV655AKsH3cNq Fe+sAStekd5PID1eUh8Kuq/KPedyON7Iy79YB9zPJYnr+IZ6GAE/bRA+dtc/OcCh9WMVsSeUIbQg Zqq/4VfTIjcCIK0Q1HT2rVk30xe2/ej20fSBAsY8agfDNMycKAxM7131DHWgjbXXLhWhX52KwXCP kTVrYzwi8NLXsVIPrxIGrKtN1WujRPuWXUtdu+Sx7Q/9N5SAMbcAkb3AiJxx21Q64f1lr8/liNNb MoKI71ebVWxHRgTe9uIFhCa7K1L8huBmbexCdMp00/RIvzT6Z6LhMXQ6y3df87E+0Ncdv5ZqUGRk Xdr1XumCyOZwnzJTzRwC10V8lkSmh+oCg5AVAXKyyxrGygyHnnQ/rngPZRjzY8XQ3gWTHdgm+SxQ +DMsqKvAsA/v6oYe7zC2YCxMOQvEnUnrPKpHHv8A3ECz7CzgcRBwS6eMJRKiX0m+53ZyoOSWndOz cU6Qg/ztdNyDIr0F2v/GAXhw7KkBhcOYlVxdEZFMyPCLZ0rtykBkqGCEE5Wzx1mK0txrKC6oCkKS EuXMW6MxQVrqUPsCziDw5OHIlJU4E17wKgIQn0yBNvZgXQ4UYRDhdG6vVFpcl/7dn2BpwG1cphOV jbNlKevPOcNmGM7RdapyBm6icSJSobPNxhXPtW4YXtG43n9DLMHZtuwxu4kx476VUKpRtMR4tJmR l87oeo7DK6Uxm+0LY024AcJsID+0a/Z4RioAkc818J2PnylTYSGefdIjj+Zl8ua7xuq5Cbn8p/rv xupXd0FrTVQu/gYh/4GkBycn63CNNyjtBrcNh8T7M5bTsB5Mia0MgfLJqAb7So5LGLp2gRP41rSe 1RE0P7wEsa9wCjdOGxyQWlvF7rN2K9xGRhwUpdoeqFePVgOq6SlFXhKdF18kjwmLq6FrVb2+T9vY e/bHTS6HmJhd+0HHd3o0FILb7iFqqcjkVZPCKH52X+iflS99hNj8McN+nfzoqlY9pbh98PkUYfHR Jmt5IG1+sv/CdcNjbz5V994vrnRcLOc2Nn4Z5uiJ0SJuBhclEyOGCtnHzg/HZjc3vKjf+6BA4ayZ UWPZwsZ8DwY5sitSgvKRYOOrJ7AwzAaMAAXoxfBwbfqHI9dcjdlhRGxkZmsC/g60ddCAKNTVe3F8 3WxLz1hsmE8rVK/arJueRDIaVqwj3yEQpmOk05wzptoflWrbkiirYCRUBhPK9YKL0FFKPIswQdwq DoIlTaE2bTtVjeIsa0enH9Z9SE2nXKpIFhNJorEl+GSxkn91muATQCcaYZ40uC/VqKLp1/nHSIjZ Uklqe5iy0xDPjzTgn2x6kscVzCTylb8r/BB/qfVwZqoCr8U0fPmXQHmuCgCcFbbqbR7I2gbjc32h 0iMX8+uqKYyOPnCU1cZzxsGUIXkxzuh+6f/1MFC5txxUGZ7Qs/iWTBv77MKnaI0jYguwkHkmL6WE 63DK6/Qb6XwIghABuoBOrUw+fuwpS4qsmF6VyLiSmjelLb/p7c7Rfp/LIlC3I2prPHge+Hfg+AnH 2dqdBqfPcVr+iCWlGLy+EDgamliMc5W/Kt9EiJfft1pRtrYdZjJrnhkghck47jR06aqqQ2JbRufY z9LdJMaJDFfxV3qRNMPuDoGhB/zLemwQ4siRYCigqpWdfVOpsZ6IiZMm+n8aRnSxNOme7u72bZJZ 2nslcpvafTti2Se4lu7Fi6pUogOq6/P7Ymc73rW1hgGCAJKKv0aduPFbfniNV3O1qM6eN1ZKvZpe WRRO2cV+h3gzQUMAkR1eLZJEdWUE9DyG1UiFNrUSUVrKy/DPlA3591BKlvqPQz6NdTmkO90jYoI1 LIBeAe9Uh0OJEjRv+xOXG/mpe81lV1PC8q0EDVZH1yeTcbq8t2vLomr+yNjDzUhbT6LUFTM14ESx 2+tASKEZK81PM4E3d0xNRkArtXfwPWtTzUYoIdTrr35dWhD/zDT6fRDRm7923ghMNFskd6WQDPxn e3MFlAyP350kta9xGXsbZuO9Sewud4lLxbfdpAf3OaFVqgpNp1ppRBXEIVqkqzGZOcHnzXP5+AWo 5uVi6tRHo3zy9hxXXyKwBmaGasXK/jOTbgbhsOCiekH9atiAVDCGubRr5p0A2xu1yGYZrqDcVk3b VlwjKPS78L1uZUKSxMds7RjMclCExr+gS4zeh6/wGIrB0WiBjwTELBpM5CglvQqa5JOrKngEyjlT Dmr0O3QM1vO4zr5bNFrc7SF0gpJS+k0HuW7q5A8zb3q8Z7CVNnvNKxN/pTQ9rz4qBQKxvihtOVF+ PlEjFTgMgjSWFUm+wgkm/lnm6Gf9NXo/BBtcp+Z+25nBAoSlfIsHDDJTkNEJqUc80QrNR+bqFgCf 7w4AQGeK4BRwj4yMGocCndnCim/vE2T4Wt4OaKWVXqFBi6UsPCSz0EIgGlj+M8AJk7ek3/TqFgm9 GosE0xdjubBmGqi5WRbv+HplEuw84m36hT6BGJJ6Vsw8VhURF1OHlkBI4Fc9md7rVV6we7DJ9Znx BHfx/xWtGdBG93Q2mIP7DPDgp4pl04UopiiJJ3Mt/cXa/qcphfsD9mzfjwO4TJZIHXPP3EFz1hpN o+2fRxRm+Xj6s1u8sT/rhrMfn0hgp/ratTcBtp9k1Yf4j4oP82p/npXD5UIuF2f4B4F/qVKYGR8h 4SYRK1W0mUbD4FwZO3BxWEZHiBp55TUnE9NGdTGBlD8q/fpmG20tCwXq/ACTQMPdVjX/MosyuTEc 6Q3utt0SsVEFHoQlwrvvbk+FzrYoIweqceXH7H3u7wz2yrb25lMfjpK0MMWlcxg6ElyC6aow2mJE T/PZIMfZPlrJyQt1OjzYXMWn2UyW4R6LG19b/BZPs2tg100W83CTmHfxRni5+smNDhOl15hcNRRJ ACylk0uGNjSoU/2KAvvrdzAKEBw4+m16SBSeMLa1EH5U85lejlLSDQkIEsgEgbGoN0Nvu5LodhGb 5Cs5hCvdJitK3crqwty3IKkuMEzaYl6zDdX7puJWWfhP7FPVDLP/2QmUIpO0qWnsTmo4wDy1uWGm 0NGB520tXS2iEnX/aHoktnVMtQ1nhkadBF/jHpuZIC9AHNN6ZReE8LdiJdb/Ax++maYTk6ZSNgBP DnMzXFP+qqu0IC7fb6hxon19W+SuDhKz4eV1wVDVjcirYveJiqPABAsMH+/1Hwg2W9me1ugRcFme vZVkofmUBJBZzxdSha0wbmF9pVnt9C3D+KgDyShA4qO6/gOmx2XGwKzMzBtcOxmPyzsUsjEt5h2t RjJKE/tl9SP/ZrLbIzLOZbpbXrFNaMxcO/Ry46hY9p5PIKxQw5tvC2s/HMjsQDprtZagEvPvQMAJ qpTr+bun+7eeq0l8AMNfre/IDcWojUkkC2tkq/iXbue3tyfG81HMjiLc4c5LjpHlettbhR0Mtl7/ 36oMK9rAy9L8yi+zg+h1Q20FjqmuYEzHg/KJSUhfyYKOiKtfnh6G8WDj/K1lz+f8choZJua+U1lC ve6KSXBzp9hsmWq2nMfOLFVAE037D8S8yVsU30PGy4Am/pTC3lYxZkU9P2BfIUnIwtupFaJxMmoQ KQZXYd2DmuD0GAAtT589Twkx2NLVXbgXnWh6qxiUerGKFn1rl764hTuCG1w4OmulhmDPHMxVcdjz a70fS2JEU98zigBl9Qscp9mPHYWvcspoWQ/dYdGoZFPA08LxMV5J9tRsESXWxyVUdWqE0dLJiDRr mRgmGKEmT7Nm61Bhpp2T4MLwxBVOrx4o+jLudNEU3LK2maaFgoskbKxBkQJp4Ni+T0h3/oj4zQY+ nFLDwmYmN8jPmBs9yfEuwCaVQKJhqwvz7FovSMaRGQ47Jtx/oOECg4SLwQ1R3B8vMw1SmuCW6ZSV LSEkt4eQ79uvV/LVydoCtj6rquXxwb7TJa8FD6DvmdsNJLxBDLRXgGMKfZx5HXhSGsjPcFWMYsIy UVYvlCP+XsDa0C9yPEOF3g321EK+vNkrZYZgPEdEb1G5UpSziX4qGopOnFWuqR5jafgJ9nqF1IzR bjWq3o31Tr0t/LIEvax/pESjOT/mPV5556YKYT+BNNBRc4HN25jZB1EDX/3MMcaAUu+ExWulZKk6 WYN2NR8tg+hNh7KMb6VcHuIEwoA1ZXjtWgixeb7jL2gIfRvJOQPfO0A1lo0BFhFe1eXhDHnehDK+ rQrF1010gp/nEt9sXxWTnxThouxhZejbtZd+WA4KkaEfsU1af2/ckN5Wf0zBr4lCRyPXQuvMDr7y 0D9u5D1AqVYd0e+2euw03Vlvs3sialGJMw8LPvu4mLQ95G4wRBtyPtqiCLxl/UEzGwRAT4ltIXNG /bAD1bd0Z8sQES66ICQ/2gKcvqwFTaJFQxMPTHw13Fyeoqe2VsrEu2w/VClha++gfLEjaIRlSfIB 2lp5UMHN9feTDrJA4e8HgVUOzrCppUIe1l50Pt+J3MQuK9MdXVO0yvqCAByXJE3lNOJ/7rRzNPXN YKnSC1H7BnTw95gUE6Beh0IP2TBUsd/hpzSipjTzNAmGeSYTTO6ZzFzXJkdtx3xKYsOJnPDe9VVQ CAWPphgXq2zMkJl2Iv7UP8/72PNUcuUpbvQC0XPBmW8vWslCVzqxumCHzlTRGTU1IRA9HbXddc1x IbwY4JPs3hthZ9Ypt5zeDHNtLCqp8ubkFKPjI6VfW5HvV4BrDEce+NWhE4mvxpzhOZafgmHHN1t9 4ZRP/kRMAi2Ji/4xZbyuFLbFigwWSIEN+cmeclgFD2/uweR5ezIZQwAzjnXY5H1mNpK7N5gbU8nF CteK83XRLK40rXGhF6dHS+iViHJVTYBd1ggEQUQPNA8iHARk/jgqNuFl3Ue4YWOwHbzRRlFyv4pn 2cz82q8qMT8Nrv1woPhh8Yo+QkQndPO2b4SmJZ58JIysON3FwmQqM633x675j7DlHCl+2tcFrvHx 9aOxKAXcKhtBgSmi3NJF1qqcJXGYZTYeAuxmTw80wewlblHG7c0mSJ1NEkSVuM1vmy7pIKon62Yj M79uhleC/gRJhAOHwWVTqu13WmcfG6HWBjC04L8jzLA/rmxpckgUBYgfAfChCLneyKs7fl3DJRyN uroEJko24AtjPQPQh1DsZdHKLbvsQOnw4Z/nNTfquJmeX8GKbXT8Hc2gmQ9o5If6V5xrUVxHlLur eWeFuyDZip27vuo9HZUCbrbS3hKTRQZNovQfz9Bl/yR3ioDwGKzKyzcm+nT9nunXYK5Vd4ySjH4H pGcWZ1e+iVko38Kgfj0aN3Aq5r1zUFNgphDt42jI9hLCTFwhbi/1CxZT10Baac7k/7NBgDdwpdBl xIbG1OOounS9LtUc+lHN4JXxlj+hBsDwcIxzc0qkdlz8Al1BhvDdLggKfRLFjJ5tWRcrihCLvmRt S7a57oamacCI28OUix58qKed4QZez3yoCl9UzP6dGVdDX+a/jDl14CS+fbQ3fOPzb7aGmxxy4Mdf kD79KkpjQ0pRgUGpuQTs0su+Fq0kPgMiajRRhgTw6deAuOYKG5aUt31rfcJ+zYkvKuyYZgvRoJ7Y XHN6XBOr/ugYXKSgrj5tErj8w6BHFfCA7U1EoP0LaaTAl+zdi+eB2BKUzPJcgfqfQbrLWXffKNEm cWm388LHgtGk4s9Vufd9GCzFbv/11qDI0m71bkzg96ffJ64dI+zChl7QCHBfiay7NHd993WCtnjZ Ds5mbMZO4iqxPxzzj0oaBvJYECBkQqkjOpQudJCASIcwGmIMaNJ0yXr1uxH8vxCCcUwRfxPviMG6 AxKuavuP/XPgandYZpNU5g2fa5qbVodwOj5AgDQGfXW5JbYPD81fUtKPDOpiGhajHBEQnWliTlCq VLSa+M42T9du41QDQu6mp6gZU3Is8cJ8kcRDWdZHnd+YuVkb472QUrDlSVFjIMuR/ROiSSjB+Bpe U6RquPemLTUlY7uBxU0MRnzyI6YGy+b7XeMOnWMQOsyhLbUIz4eUMVEJrs6AuDHVS0iZlDSHWpYy AWTcPPlhLdiUWLi/1wSFdk89QmhyPfHuHOBfeIW4S7Uc+VXapvlZIuj88cOB/VhXdpcqJKCO6k5g y4ZXu2Q3RFRTSgaq0ACQgWXIdZfuotyl70d9emerpLuoSNfvX6UkWnXKJPM/xDNHYA9rOSWoYIZ9 c3cmDfXXPzkqAdwWePZohr6DRZPz5nS828qrXl/SJRq2inyAmMkGgHlQf29s8uMSFqstyEHfAQlz C0DTNDAgcVBmLIBlzIuFfB4hZk8tsE0nbM0F4ebQCTlLeWAcaOF19XQwfJnnuk0dXaj9FJ8gr+Or A3tNI+28FFv233Wc263Qj70WjZKDbE+k7mdHUdTTdzGXhIQDwq1ktVDGRes2DQWVM5k3pKY+To7M ZsWt8Pz8KS4OXnleJv6BkMLrfrytorsFbH7mo5S55CobbDbGylfDCA0UfEieGOLzov+X9EejGGDY jr/OqdOLCQTOASrVZcyl4wDXT4tGwC2VtZqEYUXPrZAG0mf0G8qI7JCP3RizUZJM7/Cx3ZolUshO wcl7JDlq/BKKYIPXiVKK/ZchFCNlaPcLAOqGKGQEeiOHio/JsOUAfSIJg5v1daWDKOujUAY8JEh+ rpLMg5ioyxk3QMih3J8t8mUpEO4LUEwGHilKiN4bcFykogcv4WggKUg1B7ughtEB4HuGEvKTN3xh oqT368e/7tjIPI5MQFu8Rnc7h2vx2DeONx5Flnb2xaaF6RdWCixuOQj/YbFuoetKlPnja182LGez ocBlfsT+l+myQE8o8bVFSFjIG/yY3f+h0LqvGgzNFHdfjtcSifEMwpkwafwQrMYmDWFKkFkHBl/P QI5sTzW7ef2GYajXiH8bI8BR765Jmu1poBTnWN/RWirQEbGusqHe9Q8rfgwzm8oqlSfoIywR8/tk CmxLCdL1DdVCrRMwKHhzzd5K21kX2v6xcFLhyyHEb2ZXExZWDvh43qc6kjyIIvDsGBgvZBRdPvat /f6/MxHl+ukCbp+HRr22e1K/seir795P9Jz2oeCKv1LNbLafnQ1Qa/LVnZs9b88mMnXqktLrnxKg 8oJU8OcdyjbDZV8M+9hX4oQ3PXULYEtudknl7hTGIo2RT5LkNeDz0LHTlOJPX7rnHM2lhlKE217a u3B3ljBACXoaSPx3cKTaSddFJzDZTtVrJCMwr6rEr+/vvzO3wNdTt/Qc3ukJBsQtDE4r643VCqSS Xj+f6TnrdgSNbEZpo21Bj753DNgaD17OC4UXZXLwBNE8ZclIpn/zewTVLc8HYaYE7l/0ZvfZuI/J 9XKa0SXgXs5F0vrHimWPVP3EBeTkyR4NNLoFIzT/aBP8FTILAWDNIvo/3GXb3/uoy/R5sVFeOvRd KjMOv3NCzpKVnvAkUrW+tmajqyGpILfJtPdzwd3YKnIHkGJll59o8E35wjX5NpIw9Yhk3dHLln8Q elP351Vd7v2VxxcsyxGOzghro43i5rLT/JAfC7uZVuFOw24rPrt/D02TOKDAtJwcBVTJSM9RLNzW qadjLDM5d3aL7+CmmalCMWLocmNwb4PPBF3oS4YKXiYcDegiuaCYpH3VlYJKzWgSUNw7wcoP7MjL wr/qxaMpix6PVpfiqkc5/sgU/yAzTg6IfsGgE5UjY/Ilt8Kzha2Ob4tH0StVWwIgOTyW9JuEj5tg L7pJp9V9NrVEBPnHdl0lAGjZgr1W1jZ4OHgcS3rC29PvCe+5tXN1eAqL/N3eTeekBOrjlJejMts3 2my88SMnZdtN7kUhObNS6ZjpGNWh35/ZhHH9JPAhYA2R2z835YY2CqQ4v4MSJWUuYxutbjtJFKjI +cT6u+kn7KEQTaY5wV5BOnlhaSYyjXvG566hKglAFfqN4bYBSvznkJ3etUZOPuRWuLW6k5hBev5P ImVGIyEBSpW8sOcXxTfGfZNtP7ZKsUq/YSgnuoTuIn7IlUoP1iITmmCO8m67/XeCo9FsFk2opxJu NKdnUjGi+kGL9uGIRBEdM31dIiyUJ47nRFXLyVDfke/8WULpL4uPisnrhpfh1WM8EwjBopc9ZGhq nA7YP9I3wP/jS7DY53qCygQilJ204zKgBVka1j/04JggLP1AMCLVc3y5h5nb3V69eTjTBp+xFTu3 +U4C9Oi9URxTh1WUI2WGkZr7X02z9IuzcsoYdX60UkpBSIhaMB8u/VtJdbWB2rXzMpbdNNVTbAnG wD88pZPSYMXUY/IJjfjRgtBhFdSCrANPXDKc85YyA82Sww12wAJxO8TqHNmO1i+A+qFGrJWJjHMe cts1j5pT3hUqmRi9YKyuNOKeXlpPO2sr5JVWNAuE+qKubJvH4QGtWmwpWZyEDCrAfqXJpAqiGJOo 4dPDDmaFt53ffjgrkYsHgBTxbMkxJSvHIgBRRFGZF6GyYQDtdVI+96Z+Dd6aYaZggzBqGwoCXCYc xbEA3OaxctXVb1XKERNCxIherpIKU7tKgZ8cPK35EDUE46GgkbeSbN90b6f3H9oU3VrLoB5RqXW9 GtJje6KsYQteRjZFiGsk2l6obYI75afFGMK7xWplVP4IlxIsKzwdj9mbyHbG03NHxfroN8QUAnK3 wS4xL4ukqaIHPjk87xNPqm0HNdDPbWM+aJLxXfzsy40dMkMm6OvoC7WipKqB4OwkCr1PKELByzoU JOWabflSMuYufYPyw2l2D5IHQpzxmjlSXQRO7XrMD6nb2mptnk2OrAgS4UzkxnG4SBkwYwU1gmnP 0r3+2qo9D8fEsu/QZaya3pnN3sMzrUc5w4yW00fvcvT/PVs3cMLmNHo2GLNu5QEkBBy2a3eR/c8d TELuJqUgxz99YidXN+BCoMvVl01zi29Fc0uGWu2kyXlWpVm/qa9E6LAraLFEC2k68TqMBdDrpzWs 5c+QJIP29lp0AEAyTt+2ME65Y5Tctva3VpGcztg420Q3JGxDtVmJbPZRKmLQ0xDi4/GQ4imPI6Th vtM+wQYKFHryFVC8hwu28Y4rb/MIPiDoS00NQkH/8JrCxegGCJjowtwAoeRmveOVMn1zQxUUQelx t6H+GowbJEnpzZvQLH3opVhXnYjTCWW8nFKUGfl+MP+UHQr+ODqT26zt13LOvCL5Du54J/6ts6B4 b74U1NLIQz2za8KX8w/MQXpcbRlXyf3CwgklvnfOUGiACupDiJ1DhN5E+HkYq8OTSyVxGlv/mcOK gmMTBkL3LAx7Q4bSiX68y6RsoZRkMkqBkCJdYBu/QXFhNc2yieWJ9p6ePO+Y37yWIFEhkkdsWTfB 8hRq/vaoYkKv/J1kd+W2m4wL2UCDwwD090Wp8vjQCEo1TG3swxVPabgQOs8mXHDuu8Ek9PFTWlju ndRL2k6TOo9R+BmIdgewIAkPDIfGYz7RFKFgu4IjEaft2WY4UwSnPfOO9KHYIkZBfzwOtd+29NfI jxYhv+J3hyFI/2lYrw4JOLadcHaw0dj8C4HDwlbBabMWvZmm0vDErJ2VBHT/Pdy6QE51Uf7SACi9 gYNKkVwt1/qGGc5EN0SxM3GGX1FVb9nS9bzgEEspEG7iVTKfahcp3heeRO6d27ZyqVgPCpWHFqRB ygwBK2erD46hURW2yd0ge7MNVGmVGMd1VhGPN8kglXQAsoOXPs51SCZyjrtPcA6/BCNmBs4JjdNh g3SkUYBCqIDtrTWDl2VYRaKft2qP6Hr4DcP0A7XVFmDw/Yik5iFpERDhuO/2NJ35oAlY8dgkqhtC pS15Lkpp/Ba1adO8MOfDK30XgOE5+AXlHUVAAFUGKU+hScmx9XrxAi78UDjWqzdalRDsykrEXgF7 uVk9femjSX7mALeAc5otyAqwwGTX2t6dVPUitBkUyjzm1sMCfwGJsSN+38uh3Y6f1hJppuOUEHha qAqerW3IXPF2X9i5RmIpdkMuYZ0UTVs6gIFjoM2x+Atubd50OoV8CB564RDWwghuKWwsoFx+g422 9z0ifJq5YoZRTTOr6+OVezwQuocCU/oG+yxH7AB+WZSd0OYrQ1NX731l0V4JSYswm1LwoBgUfy14 d0m+2qxy8wTO/KmZqqCq3QsJRxDeH+9D+YLyZ7vukXxXH5DgT42nY8bXDFro3ah93za7QXq8P6u7 jzgVRdBHy0voaygpW+V3V9pJPW6aOX9lXaiG6pVG4OCz8UgfCHYWs22LuvqNEQcy+z6FSGBzD31P x0GqspmOUiISKbF76YZbKP2MY50MaQf2agEVuRuH1VsiZe0CPu7tSByEoH65CAGeFzYEmk2eQXml w+D92r1RRUEelBSw3wTkR2vHacp5QLcSWNUNMuK3EAY4QjW4yTk32iqc12o2AVmpNTndZg+p7tCQ EhwKL7IA5r74MkSqUiSvZHqPeqhU1zy7VIPi34SUurWuE8YBdbQPn3bkgXRTmlugmWT5wmglzQL9 vXHrvqVDlMVusBInjL4LREH8HTCv10HNyWNC3sZr5NB5N2Z2Q0iYdZ5KCgq56hsfF6EHbQYKCnI/ eNz66wscvXuNBZqpfPgRR1sDl1mXnez33+R8BXyFqTl5QcqcGQmz0VbOlRY32q5iP9e32yOw/Y/g vFA9owaRBBGwqMQNk72hYuhA7teDEQrzPEWYfZWxfI8JxumBtgeBdKJX9Fho6R27IUjsjZLrrW2L JJBsJJtanMwSF6vlPnlQVMUQxv8fjxSeVuqHYj3Xbik3IQHrBZyyMQUK+BpB/LcJ9r0f736IT4bN Nd/oWWL9vBdh5XBynSrC/imTJpDaEFoinAzaYjEPD2J+90odkBcJ0O8+MmXU/DYnCJd79BhwODQJ r6WOIyfCqXR/F7p0ACInWpXbfKeyL1sRGbFqsW8l3CW3zeM8QmBcFsBp5nYsYyY+fEvYy4gSCTFe VhASdBX7q37drX28l0zoevwVYgPJXpbdHVKqvinAuTBAPfMEY/GGixLiHpab6kaN0xNdE6ZEo9NA 5ncXo+1r8rlhfcw6H64Vly61Nr9XbXUtH3QGfMnoEiKHRKOm+B2Yj50b0GTU+oQLYmUHvxZz+d9t 09o1o+oti/HaaI+FtZymBvGxmrtBn6nIDAgju9HNTy4CuL/dD6rRfVV0RAPc62faQSG/E8dt49bL +dkAlPb10VzOcDLIqaPWMY0BHeari+cegh/ijlbj41d3kOpGRWTwYOlfH9fumQZZUeUDcEbt02dg AHRqGjmmk2xFYpapABSarFL4o/GGUze//Gk6PKs/OLSs710zKxZsqyQCq1tRQ5QZ5Bf9pTrGRjL4 QUycZJ/K6c/yDrU6dbXu1zDxO1/pZBpT07ZziFG3ya0vWND/Q2PC5HW4ecp7Fnvvsxh2RY2lLUbm Mwdm2J1kh+G+g24H+U022dqmnfINTM0Vy8E/A4icZw9P24IR9hEnE3RJmtdjyLfyP0W7DzBICsS8 tyRF9FAbfSfHSaMY2EDfetMq/wUkTqi1P2Qk65/CdPLmyn6zzgKbtxAqu6CFDitbRABTh7tW+F4o 9vthlypJXmfVtma9+nMOs5LlxqKw0qgb62+I3gcOT4T6cUnXSOAUcRD7Zdb0acKiShMFFl5Ik86+ pk0yoGaoa25TOUEgGAszAMuVFHY5c9OD1e9aa6pfbEp52CRBaQMt1TPD3r+GjbI/m0z13QirqLSW 6AMIeSiPQ46wLf81vM81QaCsb5Q2hvPVB5JBh+POl9M9ad7YKkQZc4KjFQt9okt/tLdt1JdeTQft +t2X1h331R6cwizlxaNszVJYopzpu1tZn8koud71c4oQ7vnuEJNR1RDTzHlp0ohjnskmu4DkFnOD kbK5aStr1hSTbg1ljX1dvyK4rS2AgVU1SbJQHPdih2OFKc3LIfUKQ05CjB5H4h5deZ7Fwt4c4dT+ Z1B8LFWJsadmT8oxpR/ogOSY9efMpA9vuQJYsGQ/w+gJegz/mr73f00EKFqUpyEGnqkAURFwygux WOEsyqPkMYeYC9gjI4N/+xmsn/Osniwrgy6NqF+rsymVQyW3lBApITOeOF23KZRLd3XeKWVXAY8l 8p5SMgxWTCeW9a7a3BG66qAuTVudjVEaNDUF7vc2g9HsUYamMsytzTuuevN0+3DTJIlzhvuahZ0D 1KcLUx0hRXC/Pfv3M18IOZ8kON6IgMVsxZaoOo6MZ00g3M5vgW3HEQ1s6ABV3H3b65Pw29/6DSgT eUGtGqRXKlqDlN7iH7kgHtQk7ZlWD7vHTHO4xBBnnzlNqREQCsAdwCTStlxSLAyixD6CUTZ1MsAK wn5KAI2aqd2mVJLaPAHS+bdlVsY2wuBzjfF/VkVvyds0Whj7SKnNSzhpNvprmeXvdhjEbAKgRYv+ dVH/ZQOumt7ahRFAY7fZcKBsD2IeIfUliJUmVEyEU6cUi5j3iggPOYCj69nSejhYkX1n9GAmsGXB GbJVJg9Z0uYk5pGX8jE/S5d3TPqqjAxrKv1zW5im1hxB2OdgQSGAsSX6xdbMV/DP+Yrgsp6oKGB3 ZYz1ZQkZMGrM/v3G6KwQ8Z28KQFu/1hIKpMMGKNIgu7Mffm6FTe6795lrwJiMh04UZD530YIXdFx vCdWwW7BuRChYNikhFHyw+TBrMslL1PGp9sucxTXujY5DEmUAPR1e3K9ELxnlEJENkrV98ZU2UIZ IMttgarDGiDH3E9ewMM9VoxlCa+UUw8oS2LjREUbSuie7sbMLdZ5gmpYkjZmbVPLbRdHCGg2xgR0 Cknq5LMVoFMMZrvZXc3D8rxE59/O2beFI3Yxd+N0qmOt7+Cj+2Tw9FEbdSKcch686g7AGIBncBEB 7PQZtD1VtyR0TYCOX56TAKYSV27wemBXlZTknd9H+OinsBKwHQkJxvgWYpzAICxBtUdPSxGAR4c7 3GS+AwTotcsG5DXK14jGqLOPzqANqhPhqp5YOjhKcxvs7xLKHH6CTFUku0yB36Zq2+d8WprhO6Mq phZzDti7NsTjNSqwnvjolwxkaX48Em9gr+7IqBzvFK16ndnzcgfao/2aKpg9l5KecIMbkgcuxJFy i/5fCUSFlTsvrGvyHQneW/fyshPMo3vXXYhsWlkuz0ft3py7BjRbLkEzpN4X5batRwPGl1KcinhN +Kl/siSh8eYNWbzSSs8pMUFnCU78BgOX4Xkhdla3EANWJp1qbSyGmJ2FuJFZCqlnAfP0dERnxtn0 hqFujOKaDZzS0I63CJG0UolQO7Bhn0WgCCpyS+NU+1ZFXqa1MAmxIFx0VtYtPSLfv9DluIFTQ85E qw3QhTmrnhbmFRC9ONFGETpYVmfNk0JAeVZoMDsJhulNz3b3AeoGQXMGIkI+QFy7vWK73zPVgtqX HqWEFS5jbHaOm+0QNexUthvtKWJ3ySvtR3TqvkzyDunmQq6XgbyUliI2xd03V5roF5Gqpz09MudY PLvnsxSAM/iJrbqx5LGZC/UyyOa8ugQX8lGymGyJMnUau7kY5L/6SAhtG6wgVmtzOj03yTjW9q5A WwPRfVJW93o0DeZxbN5Lveuzbbxsn2YaHMBLv48pzo6CiDL1ES/XKdF1AATq1uQj21dRcxcre06M IcPYlUTlo5Y4TamzRMOMVPHKZJoPoOJRoF6MZSi68arSG4mqgM+3/uS/4nTV7DsOLuGKrKxigC34 wBjKwlZdUHCXWoZbSRoXzUJ0wRgZjab+KlrGykVr+PTp3H0g/PhH/7pRGaSiM5btgAXy8QgaEmGO 6MonetOeHIut85/w1MMYEAzt3IU11DAFS7ZqglnhkW64vqoESf58/R5nigy7rOhLG03o1wjG2+gd epIPULbrEipv04XexkiL6+dVvC44bAzGI9mfYAyp88nVgF2CU5qCvGzDCWhc072pxUm330QqBmtD gxaZEsMVTaB857cgmBX7v5b6v8vWayJ72moL9s4bcGhZbTfU5r+IwMjm1+5Uy+toN9k1G+YwJyHL 2GoNahKyY/Qao+W7Fn0EaSsBAGc0gA5TymuNuzroK7VASJr4P4Ots5f5EMmuotF1UF8iADOBMJ6l Yoy5Qx5cmxjygDWo/LDzgnIm3ASEgkE3HGDsmh13SCLQF1b9FiRkYZKCfYKIwDiO8zlScGFqMbZb Hyw42mCWeTA2J9i4T8PQtYJvHJpHr94av7Ri3S387lAOX/ErpZEXUlURPi2JZHIEjZwV0FucHnQb TjSE1e5uzVuH53ReowlNckw0hyH/x9S/bxhe+bmNMgtxPCKMyEq/otvPSO8ynWZT5E8oQ9eRanDt Bttbvb5TpYGJZP/bosuiaqoIlKkySDI2xASb8pt+4Cr/JLG1RiRM2YmAGtZZlavda/LIPPLEuhWi Ks5a6NCamOaHEbChHNBIzgQAeLy6LKiH8WH5+1yiMmeHaK+sueNOlETqdXlkPpCIS/xFCskWtyZ6 7h7hFJbHbabC3RiY9sKCnjO4dau7oauEdIwABW46Zb+1eD/YqENr8MKxY4EEqRkX7QLJ4i/RmkIe zD8tDTqz21JzvevfLvis156hRQtgxlOUQbOe/jXplSGqh4c0fZpTdLaBjqqUQZjvLtDLnX/BqFmw lFBOr24hUvgn4v92yq4XCaPdsjDXt35vbqi1ruXiGmQDlfZ9CHRqdjiXCVVsCs6iEhWpWdotiQxx rdPSZxLukjd+76Bi5angLmlf9raHgys8yjFypsVSifUSYhfHSY1PJSdjodPkhGHHycqcsMAP+Oos wXNwHQSggzooMbEfpHRit95uK71ugpMT6iYLY1sybzoaJq3D6+VE2ouh/Ts3RZ5iqcVOaeWC10Wb wrtiH1wpHGMBgVe1uVBmoVvu8dpk/2S7P/4AyXYR1N4uaIbQuVxKOVTNXakPbEpNPWm4v1JxNUgt FsoWuum7dKtJ4OFDQmFXoUZxRvWFaau8+dIq60Nm9Q7QH2uXTsxcv0iNm2SHR27IyYoNE2PM1Hr8 UYtAOKQ4NmoT78TEHWOqSeoGbK9mU8N394hpfZgbJKlwgKbbLeoW4xX1rNJpBFcScdgFQoXBcMs3 e3DqeAZ/xLyDOLctahSGSn5KliLvcKtqYBMj5SI3zDnZiHDJM6P0kg4XrwShllGNks7NGnOng8pE uy/pEpn9hxSO//PmY2RiE97j6oyVFbGaYbo4FJRtIO5NtpiB577sYH8NvWPPQOL8m9qX/A703ArU rd1MZCiPIJDm4zbykRnjYzUfLaiPPT+InqlH5BMqvEtcM5QzQT6biJ1WDnIF43CaPJ/KEiQ6orQX wIy8xLBi/2Od0XuIgTVVaKVFjKmCT94T+CE0YhUc0l/jKCJeoiyH7dfIFesAZfaIHU6SdwQm7zNW LJgL/YbFojcnj6KlduHa73p2Y2vDDyJzifoolMJSoDORY9irFm/GaGfPpkK/6dD2/EzpzAQar85h iHUcBXGcVkUBRwsKSB4qt8z8koOFFvENu4+TnfmG/OL+YIaEBU1vEmk7NtgTz8pNLT28d44xM1zi VrbKNa0zetEg/5hqIL7pjMyO9KcD+ksF0sNxbpbRti/F+kSPuNJGF4PXmTBuYV/CPxtTJCmi2dFp LJCGTlAXY4wR/OC23MeVjmYl54SsUeedF9ps7EtBSaKA8xeW8PStygb37XfB+N0QMr1OIDsV2n3s NcMTLilPKby0ILjPWuQ1Jcycp0tWvOoh+Hl+IoMT8l1h4QHIU1lLkvrdY2eSU6uUhbKcCFEH5l5t /YV//SfXHTsxWOb9htv2XsTtdHTz+Pg2YF8g6/LdFPL/akGwUhFzrso2heQDeFSOwCzAjasUszXA sG1WQqg0IjWAOcBQ0jtph0Q4iTSRvTeJDApk7cqtDlY5kizVYvQa1Vm5xvcf2aw6HwjPh8lGno5Y 5opuIsb+v1D3UoFJU9jR6qSwOJt+WpriR+HK1Uue+SLv3JiWk3IEF1kfLFjzfX5FfFYBTI0VL6cp T/YM37FF1TqgfL8eCtaJK/PfA2D51G8f23Ii7tQM4rVb59FygfW2e2FEu8o36V96XzSidsBGen2G CCLvpyPQZ8SX2GpETA2GL6t58vFqKOFNOEWOt1OyK7b1PsiaK4R9obA1HmCGk5dArJGQsx8e1TTq 1msQxZWupQEY3vZ8qVrsYfJkJv6jAKEq+NxgDgAbTOhMg6xvvxqzLLWV2Wuma/n35PrRwIFZ86M6 DkN8JxFKR0ABKw9UDIkfPgQp3bRGDOTJsK/jbWxvnTbKdMs3RXy9Nq9RM6f5/4PlAQz/Rrxrg5Fs PihsL8pIyIwaFRmKjESZtbCxJ1Yvz+eRSEnxBVyXp3IGhngQ9DDg/XuwHw9vH9Qq4PBM0RizMoA9 /vaNfAKbkC2C6kyuaunK1t8EUYyfg+6mUsCPa2fAaVvKlgcASiHdUFfMqN4Iww+MMI7OUiOn81ke r0JDLfEvU56jKEWTSgSq8JL+OoNOrc0Qu9YtSJJxh6lu5NYoeLL5znPBMPJpuJBpjKWspmY8lNfW wP4n9sGl8ONESrc+lBqqGWm2mQ96lylFmNvjW6o46uMGdZPC46GwyTmWZhLnmBXgeDAPt9oGNb85 WZgXNNuIDarO6wlBZaUZEanBtYObDJX7Hb8yRj815t4aS1zK/IPeu/43C/GzG8vFUEnkZXSfSVZ8 UZWH4NcTbsJhTVzz71nasdH6CwNeJoqGF08eU83/ltN/8whkZgkwuLyIVrClO1SSmRpzGWyuxkeq Xi3WxeoPeUSiRfex33iZ8DC8dIbpoZT6kg0HD1T5Zn8H+5GI0M49UJhQQrtlYAPBhk5LI7BGuXY9 GkoQOEP/SthWycYtH7heUHf32qIIsrRMYAsubNqXFy5B6MTnP/iCIvB73520X779W/ZO7NMCk8wX qknAlxbQtCWUoUnOpAeerf7r6itLnw8VuSqjGA+neh/cx9MKw5il4U6A7lRdmQDYZu3EbsBy9eWi dUEZkOn595k2KKIOIbN0Y7NzVvmisqBgQi5Y2+gO4Lx8NYCiw6KBQERVU4R7Xaje81GP7HRqzVAa kkZrgXY4Ivl4P3U0MbO2KZzti06qmpOlsUg+39efuxl49DC3IwZ3BHuNaLdblb7L7G3MU7dPFZJU s7mM37fk6UK5PeT0jXeB4snhsNq2XUN+215mgK2PI2S9gmmqkfv6AdPwovwwyxFV9k2CDV9zuWbw 82uWyNAtcGDtcnJsdrIbIuFeGhtQMukURDNjlBMYiJg4k3aZPLdye5O9tKJpKSqZ0XnJc6QBv0kH NIMYw53+pJDH+DC8lRB2pOuqMs1bwBrpnzDIQIJqEr7+aMx3H8vyVJhpubVQjNcdq1paETUwiucX 0hFwy2uqbR+AUJ2FienWS35D5eZOHznMxkm18jFCu9NcjwJeu1ILs8dBIjyN1+iVPS1X7Onmnejv 31g6vnMGcP4cPaajRHaxcWspL+HMdan1XXF4e6/GctMwSZgInTBcQojS+OwoLQ5kQpsMZNmQFfz8 FvbgLK3oalKfZB2wN/djKwdRxHAHRSm+rdA5AyrSSGiRT/f7fk6ywKy+kUHnkHo7GL3Pnt3O3y8L CfEGMP1EATmckiwVydxRVDzeULAhE6UohXQEIONqsXI9Snj4DH1DG3I2tM9OB85NOYSTWoJd4jwu lL3H8DnYRVP7ynrkBTc9lgd9HWBYsNrKfYOFaTU12fxsSpNXTicyFy6vOuhU58aiEBL/FRC9LnXa 5N1xFqmFMnrH7LJfjTY77mPH3cq8SROXtfXrORuoSFeRFufa5j1f+Ksv7CoLQAMWgWkZu8JQlznz u8l2mQbG+Ax5qr7uxx4/574ZYc/O48hjQNj3IXzIeAdKAmGgDU9i2ubDy0uzXYWrZThciXjo2XFD pKedydzEFEEuMhjz58ZAVoSyDemvDB2HE+uofdPJvTyXBtoBh6y35Jd87iTZa8EBSm1CZJ9CdA7d 2uZvd9g+dKwcbVMUdUaEEqQ39GBJCvgyT9ALa1cgfAhN2aZLfx4BbhKt5ZpPcaBUUt7M/ZMwIMN/ 6MliXD/zvMzTcRw/EA9a4VkEN5rIJ9aIf/Vdx9yjDs/Bt/dm1KImSXj57/uNPPASKYaOJUgj6Rul 6DAKES6hz73lmoQkecVLijuFYy6Ewc23rb2YU/McMfYa1GcfNlRbZtOSalcgfk+CSdYHiNSVPBy/ EIuNPCX42dyMBhQVriHJs6BkXsoLp8IlbMnsOLu1b2edGtQN23e/HBMNrs2jKN3BuAvalRV+hk8v ELjCyeWjpZdNHggRp4C+I5mDslPvuhR9x1th7fM3qCKsQzURRRJUpQslMk3zJQoqd8ZMWAZF5Ezb rOFqXbhNlbRc6KhF6KpiaEOZbbWkeZ6yWZtWhSG+yX5dhKU7pQyy3GroTiR21RHgxH75tNIAMhF2 nW6wywo81YIqykmhMntFWddBO2j++/qVTGmNeiud79alc2sBNAKxWbDR/rJrlEPzE7EzohcLOPpT Br2e1inYd+ObAcCLFBkbXMa0zAAUWQ5Zb4B5/jZWKbFL78JP4HUwgHEgE/RbR+stR8FTz8TRC6+t 8P21m3uHwBMbr0Ueh0bOexgSraTRCyRiLR60VIW7aITixMycYOcZisxKqzgQlOllyGXPUch2dZEA 49lpJu1ebTzlIznqC4uvrj6tvSCdzA8ad/kVhAnNQEaHUhCicNj0yGHNIzTsq8wRG1MmzVIm92c0 uMTFc/FMabl5gJKPO/6vOTRjzfliZ73cNUT7ox6A0eR0mxZG8QuKhaH3zfYhg/ZecAOkguyYykbo /h1sptiLLxxJU4V+LC/1Uti3936YhspVKzh51J9fdoEdVqFA7xibxaFP6a9wkYzqw4iY/CKgL1qp eUVZxjZE7T++S5PgbZyBs7z5SBnUk0EmUGUlKkwPR9f2i7Y7XubReNsyGjljE0VJtahjAtCDFWTg pxVYtyhkTTMl+mweA+R9rRveVz/Fsk4RNm41e5cIDW+E93Qf0BG1SmTk2PvSxh7dhvL/1Vk/HUMA TCA7FMFQSHgo3L22Mhc2e9rtOE5s1w45Gpu4fFMBdqWY0g+6IZcIYsu+rdW8JHXIfREkTSrP0HMv lghIWPJfRrlOrxDxDYrvKghs7NGSgqMypQICsAbk3Cvim4CxmCR5wAK+H2v2grdQK2CxzmqQFIfo OrxWX3pRLbgSLt++KSDOUfU7MuxLF0tl0XA//sFB+J8yuHL5c8DvErHJzV46QmYnWMm/Jt66Ul6C sAwvmX9PT/YKgYT2nCwHcrKVgGTveRJDhVvhxfre9W2eBaBrA3wj/73fPDrtKYhq0jVeEFP4dA/3 RPnN8c916UeTEEEUUmqCTjhl2Fr6JhOzp7RbYEivluW8m6Se2wFLmwI9aPSF94tgPgWO3b6Wxg5V vzPcheMQokP3bwR6xEDAPH4bhtYSlQ7cJFpCMZpUWa0BKyEs4/c9HRmoKGbxWdYTmza5i7V1Rx+E zgMMP6Fqiv19bUiWTUHJoW4vhKIHWAaWWsNzbdvmGUq+i8n8EFYw9kpNltkZQ+dwJYkkO99KWb0k RyT961nksx0AhnlW7Qvj05eutYPG0v50ul5rXVIznfrdSdQZvW9+pSppar5AEmYJjMNpUNg7qNzD J1v0GrvNlKogOPgr4pp/MQNHQF7nReVie363xUFY0j7ZHEt27bNC8uLBs98x9B+Y4UiyAbLAvxkd seDJxoWKjNDboD18KmTGAlSrmH/OqNs6rc3UYdnuEgT7VKaiFB+OebMge3Obbtc7GcOn+Qp340W9 +enVprk6td1Nwsc9d1FS/rLcXkuXtunAT/XXJsKBKAnU+0mn+mkNITFakOu9+PRPqezB07LJPg+I YdXx9xh4INOiFGL5S5J23X22A/wg1cm7h+Qh4PivYn3DcYE7/GRi6RnmJHYJKmQ3Dd6SuP67A7e5 BVkL6pFX6ZMEUOAPEOX96l+EAOWdLHB7QKYQbmvyLMVwx00xFhp7h0LsFulkwDzJwmk6kG2tAIMD nyVsU7kdyWjfpugEyOb4H9CvbkKVjmxOl328qHwYih0Yk2VgbHeu/RM/1sf1PYY1IH8VZ6IK7K0v xQI4gvV7EX8hgDDVtzd6FmgFCQwhur/ts1iylr1guj0z80p+PYAdrG41TyuTA7n7W3QERGscVfAw vFdH86197ic8Q4VILs1VwPtFXJYj5tSBwFwNlzI0zg4/DfYHGQNxvU0KAnofvYXgFMYuYuPCyPr+ 7BsxZ/DrvAxFbwPGviPW57WC6Te9fWhIdrqElYgGtF2nmPOl5uaPcm8Llzy8pcuLLjJ7VWLvySEw hWlOQaOPB0fb213GBkVcAprbUPVxvxwjyHTYS7H9dT/Nn89lyBTQgksarcY9ae6DPRdB3p0xKP2M fN5ESxYEA+TfM4MZpzN5aw43DwhlA7AAJMT9JRiLCk0GPFhMnXjjrcRNatdqG5d0tlp1paFPKbUq VwuEdhZVWUxDAufJJtp0AeAnHS4kixtZ9GK2hj8gCjX9WzRzFceyVJiUSfyUpylweGtlvJtcLRnQ eDr60E/0gtw7slc6tyyhDyK2PyuYI1FA9CU8e/Czp1XR2ZHuRYS4yoN1bNVYNlnv4j3ehxyqHdFs WEaNdyn3o0stZhbA1Z/eFJRx3UaAVcO9+5kpzKKXhePUN4+f+ddKluEeRWOKKjqPjVm9ZfqSfDXg GJiEuybM0UK1ilKwnKhN3IiaAbahGxe46g4+ioo0joTldf1+5Q5pbCiQS1h0omjiuis2y2SqogoB t+3knfTCY0rfEt6FivWmIwhBGowcl84OX0rCpZX8dlAxyXjA9AbQJvOehQTBPaK1UZFJGYCIQ9eB gRBgsnjUEgxUTT5Djxng9OAYAOZ6i3MS67N4dCyD4VM8AxEHFQowLebugyAbBaN4Ka6LXyQr/hD4 SlcofIi6BjRrOd0G/Z59gsvqEFe8GB8X7wj/BOiXc6V4iT1QEUPSRd/4dvWXMREfBKDVmtrERzbN 01HWZeVtMtTdaIbKam2guwGAjFv3XzQVYrp0Jb24LqNdUDj7AZFAu6mDY6tvcbg52NsU3/2xjDRq 4nvp4ulG2+zQ2nnAeAk6gecQds47mZr4nksTiES2petvxd7YDWvsVXXIBlpMKEkq9+EdrJMqOlaj 2cuN7MXQwi5x89RVTe2W42sjYOkI9Syf19kS0FfNPXQKPExRRBSXZAjia8Gs6URtcz+HywWNRpS8 8uRrL19icfghGBKxHcJd0FzqDTdPH5HG7kxLQNMNjVb6Zp3I7rp4fRaMc44WFZ0L2Bb3NAv0hv+B 0/KCUpJny9S7gP1lYYarbJjwOJ/odIM7RjKPFcM5Zv59oBU6JGxHfvXOvH/z9vN+OAcsm1qx8w84 XdHOze/k+IJ9ZpsPyThfO8lQY11Q1nC7StVEXJtVgaPNzf5MVNkHSm/ca7bp4rMUMbxDwqmDNmpC oDcw3qD5S2Wx5yevfpDypw5axIybhSfC5Dm5Eyyc0yRRCaTKB90q749Y1pZmNRhCKXUsTZyLu4LF 7QIetJjonrI5+w1cEL56rP5Bwwr2HrzYv/PFh2vhQpT7KZFi/zYAURzJm+w4UvGwx+PjfX+PffP0 XEGwLQFg47PAjqz7ouGjEjCPcJ4bd/IlDYiBNRJB8Gudr38u/qmhKycfY+QcrKdPmVzI1rPG9wXZ S7ebdHF21IbYoSc8vunlnKQu3Eg0TAcAY9cfQtxxxlnEF5lSXP1PDq6rustFvKpDi80aB0AkjHaa hgH0LpnIOFwsAe+g7iEHeaW2g6K7FvtdDXh1TtjbhRNQa8inWYSSAFHKyS2o+hR+RsIjPkhfcRq7 s2pmMYkp18cUrpoaFjg30JmuO5q6df7TsUPZ+lSjOaDEpvxG5dLT/ydei/Rn4mB/vappwFYSTo5I ycnvVeruE2IIFGtFUDZzi7j07dBy7zsDp5pjSvnPfdTGTT9nLDNvlwTh0jJWoGxnWLEQNNcN3nut 7zyuNzrSRiSa7Y8UEntfDR4gh0DFfZTj2ePs+YfX3P1omDOoEH4B6yZVUP27vmWWgyajI0VFBp8S DrqIn/J6+IoIcmW72tbqzMlhPvsahVCBnu+U4CmFvVI+TlFhxJzRw5G3DbHfU+HxdJ7xH8SaEAiS zqqCMX3jpe0/PtOaacrQPIpEoVXZdXD8krMjHLOWpBViDmzefWvsUXNCAwe4DoS2E0l1fBboElnv ro5kNi1ZnSdsPTwrWM8xxEG/h4gkgwqlDavILpG2iaGFUtvmwbj3DTWg3MD9eeBnX0gOx6kuk5Ri 0GMFyatwE1m9Ln3PBvna8c/KLz8+K4DY4qnZnmrSi1kxI3pf0OoWTPqVJaiILOT0msbJXVR0dYna amFpQCyGsRo27Aij2TjT7AGl3H5i68SIYkZogks3zWii5D5opd8jbJMRhPGQeLG2mw9Y0mY+Cq6s +oQuxwoksBCmCB1T34+wIZfPzg2ZDn1MiFmfwYy8WUeW+4tVPCq38kq1CwNGUsLaexVrMbv7Vepf QPOcSxKa7Obi25U4omXztLtTXtCB5ci5cUIcn4X2U5oIaJwErJbdU35AYen4EOlrY+61M6iKx9a0 7I6gU13i9/cyyRmgdJyPTxH7rVGNTwH1uFjh9DFm9p+9AH3Uz3lic/taPQr5aokPLcTRuLkNy4GD YRKeWgC61EOLFaCiIKAZO86wIU0Kzfna2YLmc6rK4359zFt+xL6eqrV7IrGRNsUpyJ+TQIhENJRL m4gRqbWzHI4OH8nweTtJIazmug07+8gYwGTM9/XDvBcWHlycRX9XYJwTxs/hX7GM2kzEROpCef1E FPqiqgSuw+F9z/Sq1tm64WxFHKe9k9G/bs64VWmrWr60PWAGbNkVr9pozoh2NCttuA1vE6+Uh7u3 oQUpSFQAYE0jCBNMWmRg3QtBr/MOcn4+nm9Vdq5ddh+CUHdg5ES1NHkHbDD6acme8WtaYZNEvrSn EequHdaeDZ/M2YJNKgKTmRDSzEAnRrq/QHtu4Y5R7KVw7s+I4jA3fko+x2xWu20ROpcXXRBBQMhh YAJHtItphHr57aS0PeQJyJ1IKH34ZrtfU1sNELROW5zuWHb6pyBwEj2v4zX3L5Bnv9WftMMu9Aqv wkXtwCgkg365cfA5K18VyiALNiB5XC5SzvvWksgDCfZqcRNOw6JmjxT6S7s5w35nhsZNCYqoKVSx ARy85X1aSij9Xrkt2GoPTU6yJCK0c7uCFQ9Yh/lghfRmdOqJZglt182Yp3du1YhVRrppl5DwE87Q PYS69TTV1IINilEK22Mbc5sdkK4a2jD8GcCqfg/ZFauNl/HTyiD42K3hjEa4ffcjmlrCr7qpPeky k2zYrKAUX0m7naEf/Y5aUb8dQB/TgxPV1n1FDTm91yXTiXaI+6q9HcEcw8OpWQ/ZV/hbyd161vbZ L1D0NJgb29tYJegQKpaLF5Bt9EBnDOBqUrS9/L7K70d5FIH/nsXWRiDW2LmyLc3ZO2q1uG8fyRNw Mbxy7vGBr3Ddc6ABYl8XQ6QKnvNDwMQMqXANsHqAyejm1B9Er5Wh53rcb7BP1QfE3k1rAXLlUDxM d54a8ei1SF2QwoeFvUEySOFIJn2y6kS4KJAQpxCSgzlms4IGrHDeI5LN2qdM/YVp6yglEGmz4Y+e vaBH+eXGOfZzHgQsBxkQGhTnS3I1Qts3EKmI8iGZS5sjYiCamAhyzj6fTuHqfBBIr9eKGFel8A3Z WELFgHuLlE2g6zo1pkaaoG4NCGycm1mldNszMe6eo/IhUjpIq4yj3bocArlKd2UitomL0h/BsaQ1 RzTdFkdbXqhCnkY4Js2xX2WzcxladIzyIbTELsSrDuNNt/EJ6EmtchTZ/5lM8JiXk3u0T0HeutIu oodyu8xTkhB/P4qYhEOdZQ3mYvKAcbAIyFkdy7lFOIYHRjaypYd9uJwtYeLwuqxKQ3HIz3WRrPzt 6iIGSWUOwvM0bJRRBEOm9H/DshJCg3KaHZ4KR7MIn3R0/lg0LYqaTGdVx6XwgCfd4COezD3WDFG2 OaQTf8r76DzFa723rXBsbYqU2k7iTv9aCAIAjzuXc4PVnQTWZQ2kKA4rsbg1YIQidOIkIzRm6q+x wo9+xagG9RiFxTWz/cWA4Tfhtd76voy6lUAnCtM9QSpJhzMAX8OTPPVf9GV+SKd9OvA+xiBC0Abp yLCjkX1N6KYp/PLOTaiznD/kUjeZfuYrywktTHvs+4/eY3HbxeXLRMv4EvIprzhoPpjDC3xyeLPZ qwHK87aK+pM6Vbu2JRaE/RkZkF7SiXOf9mZloB+xAFhS6l1AVD/ouhv7TRb3YYRbeqOL9o1EZdh2 XgWo706hd38OYRThUbrxcBIRwfqcelgSO+UCsulqTUVtTrNIBl9rdBiSTH6jRm2K6saQe30LQ0i7 v6MxAJUFpi86jMo5aDKAROIPZoKOCH6sCkHDzLtgJEJbVK1HuV+ObGno8PyaV+I1qtI6yWaE6SL7 mNizv3m7HIIDMa9gnXBlbEgNTZYfYWK100/UCnamVhtyZLaUAvBqZ/sh2SLdWocfDe1p2otVwlzn d2T4pxjSFZouHKX+CTJwVrRrUIJNAh4jJfATM+Z49Wbr6fuo8sUp7GOpWvGAWCVkBfja57Q4ihxm iHpmAZtfgKX/kaUOcz79Vfg8eW1CJfrvCSpFPYv/ey8q3N3jxQ3CebjtkXZZn7j4g5X96Hq6vraO wLCoghQulUV+52TjV9m5gh1ueFw+HPcOHVQp5Ue1tQUcH8CqGtgHJLhx5WCG8w7RzbTCXZ3+/6sr DwbAgAFQwsOI/U9SEvTwlOfDgQiSS1VcdkcNZ3yHE7gxKtHCwG3Iq37aQz+FvphKZAAvcF2HdWaD d2837vaUmT8jVK7Imm37kSEDhWiX7WddlZK1bdD2YTX/cUap+9pVLbQhuiLwoCwtemA9VFjf1bc0 OGvqXiRLCOZ/yH227FsaFCv990Sp4rzLVcrNmTaXQ15UOewBjzJstYMXNkv20b0NSAnlaTrwIlfT 3rLInXkFpIeiXh2hjDZ96RTJW/wITX7qLZ59Ar3WVJ11HFlrlsUkRK2P41GrW/awKeZsRiVMhb7b XOSblo+g3dHYUgxvpJX/1zhfSqknNXm3LMGzsmp3ccwxRDRRhWGDuLWP07KWf9rXsbj5JFFZfbj0 7dFxoJdBi5k1dCEwPIanauGfFAkO2DrGjyeCEZUPrGbcjxHME9frpmtQsAZw9LVczwyW9K8rfL4+ HJ8WJMxKEBSATGHgRx+ByO++sQ4xf5akBVkL1dJZFTQSdhkRYF4y77B1JmzmBEvxTuNSWFDQeJmu kGQQ+pY2xdgjxFewjAFTlRv9vlqcDO2nGHS20dV/DxPjG9MYkOmW917GUrmhqXfPbBt9Gjc2Z872 VsUpWPcPBmK5HxbHlSJ+DyiDgEqXkp+JT1oc+nhntuc3PDP/9aXMNHxHbIlMcg1AZr/8Tyxz6P1i /IDLWBY6QILrwbzLkGlqCc+DGyozSCqa3uWztjDi1XBodOnb4Oy2JiPHdbD9raM8ZRvJtT12DXsu Kqvc8ssKilbzQnvvlojrJkBz3rJckIcmmuhOMt5kMGzHS2TxErghVBsbyI41n1SobuPb5vgbLgDK QqPOffp8G5l+P7WfMKT363KkREsEMevYMrhIQLQZpP4F+/uqT5SIz1dkb5snUcbqCWKREe0gVnJl zUIb9cNYma9LeRg4YxcLcFg9anW18ONqhlN3C/MrJuH2yKYgXwOtvIp87WwrHMcDBHmC+3AVKgGX XpUGLqTe1r8yEEuevRPsqA4rullgVKJfrIIGXJmnfnSqx3yxi3oSGcm1CJO5Wn3j+9KX49eYK8C0 KHjpthNYF4undzt3+IFupaz1/iH267aTy/qEaNzvc8zWnXqF1Kb6XTJlodfUOS7mKE6uDRcHTehv y2ruOpTRHZlUWSb9939FwgoCpi8innuU7fV2IVqVB08gYTHSFeur6N8TCDOsAst6rB0qhpWGUryX 2TK/LvDEQAoZm4WQjhG5UK0UECAC8dLHhpqFbjRLLJB9odWvIrSRGBFFmqeuYHcOTu8sFUswKuC5 UeyqA62F2u5KtJt9y7Cwik9yxsQtuuRRdcOZ9nv4CI3FpW7006enyRQogrPpOqSnrYwxvbCYg1kE CB1gyKBT1DeqP0eh/6bi9W3CIUhmBMPClMaEueInaXX4GLPWpr/1U/pzuWzwSxfzOyZX5JRJI/2D h8uBIV4j5scBWxBWXBQhQ7sVhDMX967350m7dYUZ5TIDhTDhvHcqKK4pwCnH1VEtmSMy92yyxMT5 nfGvZd6ur9kiqJ4z26ZVet9lCBpfzO0+XLapcjuF4n0VyBMgy3Y4lR0yd13q0yHJrY4+Rg+HGMkN MEEO8S3FFkBBT3L1hUIAdEAB7BOu+4O/Xm6INcdYPGXwEdU9T3LLBXh0B8mmQuPwTPLFPBML032L gJmPTJwm1pI3NI7Jo0RzVnUPPmW1psTROCuzyg6BqK8zawrPYjfXmgjvD0YA4GQdHvtgWBwuAuW8 BeoBplXF6hgwyljQS+tvcsEy7cT8s9BjBksyLqVbcf7rt/w+sXUHNngqqmbT3oK3AE5agAtrp+vz 70s07AWre2s5oiPFrR8E/YYJ7SrkSy3hl8y/0uWoS/sNlAJk4nfuqI4EvE3ZbE1RbJLHWfQevMWS fG5FF9W8VbieIo0tiwp7tGTqROH23R196aZlyY6JeaSi/w+yh6ZOsVFLiNJthZkFoneNaIFYU35Y oC4oTKbRyryKFYYn8VMZGjIcVf+iai+gTBYx1drpoDq0nZE43NFmi9LGju3PLiS4w0gTWBHNkV9T NoJ9Er5ALiUaX4L79HX7TbebBu4HTRPCxjQ14UOiC0/iYqquQeivR07XUohlJPBEO1Ib8CJxI6Fg e7L9ror+lcvZWLZn+OSTG02aKs5yvjqmv2f1iaDWxz9FZqsnZCRgQKrLigcsY8iMAbGNBSDPJX+3 F2RaKImooOzWrzTcIUg3iv4rNomsO5ECGV264n4lypi1a7spzBBxsfsVU5jXq/BSNWxjt5YbAhmQ UYp1U6CdFFhto1o5R+5CARIOCVP10KhAAuZzPBvwXoad2BLUP/bZc2+O4vsafKPumVUnAm44Sy4R ywZv17tacXhQirBbVAF9HPrubcBgE3fNVmhGbSJQjRZrqdAFG8Ul5FLUxefsdQuLZUqXowBJSTxU zdkXg0+Y1ZO5yJwdT0G8UzOuW80mqorebHrK+hWCxsFPVDo7CbkxxZFR4vzta5yJTLOUd9aWzhBD 9hGiKaFmYs+NU5Vvk2LfAf/Cg/kmy235ksGu+j3VT5sk/Xm2D3ky8ufs5OMKTChgpa6j6Z0jMomx saUnI8HbDwYMnYMbOHrmT5A8Ql4Pd0xCZUsCQ3T4JJmBoWq+jDDUmWr5cmYzOl8kAVd0qcmYB8UL fhH9gi8swmwwkweiBf27yEyGfGbnrB3xSClaITVdP08jKXjK3JJ2fffs/KOrkV5YaUSbZsKZnjFf PhSvKIB9ar7/UzIMWyHqfrRgXQiW3H4fE9k5Lxpmg3kvQW1X2k48+fGgm/k7a3xKe6VFVDejnD10 pfgbMmtj9H/CrRIh9Ykk1Uq2l9VEoCUIqnFwa1Z1gfZysHezNuboCN4PnxUC7Dea7w8t8EFtkq46 q4IpJtwYUyFAn8gBGfolDdWmA9XluSUA26q+C7VSMvbnfzE8UPDbdGvZ/zB81YACvBrVJ+riRvZf iUjo6Yt1kyD5Kuc5s+YZxltMPhcsN7H6j77ydi+qVMh1g8yf5ViR1n+yDaJRG2c3wYBzW6vpHNOx tmSnkt6jwTFj7VBsyZEdNDyz6phU8fbGR9sO3h/QClbrm5Fci7KmFJoRtSx/BvLu2WnOLuQaHst5 EovLgsHV+ONxtzjmsABVaRuHeFXDF4FG1uacQTdd9j0SlJY8UA9/uFcijZxSOCN0Yc8y38dFGm9K kkCFTmJkV3xdIs7ClG1zBB842+nPHevXRPjkM03G88hN+nPUlnGDFuGUqAa/BHsZFXpgEtIVB2Al eSHIMrr0hUpIE4EcLaL9yw/q/6QsCqxNsaglfc18bINrq9cJWZZpD3vUEdW9Tc2PyvicLOpnvinv Qz9ltB01tPfY5hopILv5D6822nFJ9RO4mVrbQ1+UjmtgUy6w07YgVG6tVy7JWd4JYv2YDjdPQ79U iiP76PrfXrNHmAwng0cMvQ3c7+42Q1jioduAwdxknCyODcAKdylPrLmBKS4F6TDRNPHKq5qYMvLa eoEYJrGfMKZs6mcM5rdCtj/b69+Ey/jgqTVg0eFglCNQQRHJvOrRCtc+e32nMSgNqvIW4pFNJ5er BdpF8RMHzm/LjTs8oK9t+wlzFFaCJ1f+SjGxwfv5nF67RGfz1CESobEzmOR86D0QfdId+gfio1gU d7xkTJVAiJihD3JqCdTm7kDvvgXokwvCgJUCiMwmSNvBGL4R7Y1lA0gJ3qp4QjTaE1lAjJA/X3K7 FUpZrNArl4ZjNlfsy+dI6m0Ebb/1GDdVToIjWNtrovhiCx6c64cZ58Y19vvkjzrPcbMF9HdxWIFq C5x8jXKDO5sf8Z5iGsnt2VxGE9XRLo8c8GtwoSMnVuWwYvK4m5u7oxdaEPverPGWsJuT7HsosCAh QeW3+TuOBA79Jw4sjipkiCMz7c0IZBwqeKdPJP6vueP0rJ2WZ/7y42Ln1YPWjy9X+zTTpTNPaLkH rbD8Vk4gDJ2vwMxLK5BqRKmCHilKtLKOjGxen9l94AB7lXiUWJeZBk1fTjyL4tfiExay3iCbPHMr U94OYDwZT+T2lZo4IIokxpyPmdohhg4KQzAtp7Vsp9BcfZ23ilYTYQdL/GyYvbVaCM37g3nETxAQ ZMF/oBQ9phqtgCxgYN3T0HdJl5emVW9zV8qfL54n5FriXYZHVo3Mb7yJCvwK6yo3EI+2KNy/eomD 4lOigbpOwBA2iXb6H+MSJzaBVrnVapMkJ6gyYyB0qwBTvzeB6+gwqr1v6aFfeuWTfp8jG9k9Jr9i E21pKHDXZ0V4JjIah/useUGgvWpGCpObbqvhaqI7cIu6yq/k5+tHJOkglkHrDFtKKBnH1WiqT3dW vVXdFXuoPDh8y+iim52N4xEvi0KeRn5n9Qk5SivaHC4vorBNPP3/SPHAtcBhnZ+7HtPfnU29HQ/M xP927dwkT+8Dl8QEWesTiVU1QSxUw+F3Md8G3hQuLEGdQ5uO9UPwT/HLDBcCYQ5FTOslL+GX1LRr pog7ZKr6RdgHnC4ViY8ySKQBVc/w/I7zSjdkXUguRz1PLL/QutRlii8yS1P0ICL2dfle17i0aUOZ p05YmZyTqtpACjxCWZIIPrRXSfKCwUNqicXHG9i9DmyeE7AfCJeLUjCiyG5DJ3CRzi9FL+/xrhXX +B4wiN9Xnmm0/avJysIEurhAnpZfzRlGxNzTY3rrFEVrzYhGc+U2HwFjcGlUnkhb5ub2a0OQ4ALZ mypnJcdtkvkW93W7I1wwKPul+c3Qkhjw60J5/W3bqt5q1PnfaZJeyFuGX5FwTcu48FlpdnOuyv+j B0+B8e+I8t7k67/f57I9PwJjRa9lDtO2gwSPeLgd12HY5AwyD23NIM1+UumOpF3sk2gpAY2AdkqO Y40GBa5GKqWk9xlnwDOfbLNPUP7Ge7RAqDGVmMNh5kMp8J8UDg9Cxl4SHwqCY+c1kfjfaXcRUFKh vz2DecdaKTr18YPiEkeO1Kz4Y0igNV4adg51BOfUjpHWcTS7cj1vnw3b655trrCcq7wYAS7oAcIT l4P3ZW5BHB5+nrq4NfVz663NmA2/0Jri90q6QPCh2IZSkFt4qEyNEgMu01DCJ6kL2o0xFBHJXEUE Dsh0Nj4oL7VY/c8LRz1c8LLxtPWWQRgF412jppp1U4ABb2z4a41qPX0pIKTJl7s57VBmwm2MyrEm 8gMz6qsJXwrHa3YihB/zmTJRAeeYfYvTdtT2WMfBz2QHxVt4lwzrvLB7i2iIQnrB4ksJ0MhMK3B9 VpwSRYxOVm2rLfXeCPtRGIUA6kkab4w1hbUwAED0RnoRitSBGTY0ppsaMo7jNqdXwI/Jfnf3Gs9t Ce9E+RuyneBNoCK/ftG9uHTR0hQ5PdS6RsIeowPT/bD2luXv7QchQctLfqUxrOZuZbZwixp3gGtE yN6JZCi7MaTvELe8T0805KLf63KHfTYBE48/ASKdyCmOzbJCogNhWmOf5vGlK+IEVR1hgI3d3r1z s+2hDy0vm/1CJ0H2DEe34f1v0bZoLJqRUdF40I7/uNUfbF96jl9OopF1pY8x7LryGYWQQAQZhYQ5 z5S1I2ilqtLG8leG/l2jLknZialuXSwKE404cX3BhHDlOy2CyeO9ypZpUqHzQqDbVnQQCVFmbZSR D/6O60zyyAgdjV06q9hy0kNWFbjM2Jc4apMOj5JNrGvFtBbV25NKCEK/2BKaNuc6CEiQbqbyAJm4 qsS+sw8y/05IGfOQyb0PTJU2pV0aaU3Ly5DkbY8eiaNFFlLHFQXlMoYAq30tX42xH1ASUMpzayoZ nRPod3IiocSYmpAqBiGZF1hzjn8d/mMtZCRYkY3o5mYbCK4wh/Us3sgc9jhuW7DNDmQHYCt2cF/A HdAddC+1VvGqvB6SC7BS+KXpAFnDByEcAEN4OLQyAklEl211V2+oRzlieoU1NoMx7ud7d4rXZlOu AHDyta2Bj8d+7y/4kIA6xjB/UArr0f3fvVHrs3aasnYob5mr/eAJs2J9Bccx6LS43OjyqPMYngnT AtqgNa0ZzEIZApXk13qVaPMzhXabdoHxChhbVtKIYY5QsDtrRKSvGOKQnxL/fV1JgptLrHhz+xfp j+cBkI+hscoe1Wjr0vuZFA7QvhpUMsogL0oLAETgVljODXCVQvzOxDnJJ19Xg6ATSrXMLUwS/ZRG 0vydz34cMJiB3NkT2DFLTfSf3/QEivj+cMekb+vD2AXXOxz9hgl7bXvAVWJVyuIBEMjs8KqMxFfU IE4RmQ7ZoJmBOZe578lT7t0Oq2t2PfYWaFu9afvr4Z5dTINnNOU1XRXxTNvdLAGsTA6ac4+SvhOT 1eIjdhqLM9KzPZW5S6qWqzEV0+gmD9bDt7ahBJIgiaUMKaEdZ+Zek/WkzQskvrmtmjoS2sKuHLEG 31F97FEOExRdTq+f96QXEzoYXWXohzSEt37gHmnXVXEGdSyLy4KAykUDnCTeIC0QE0yICO3lBIFf zhDs9xvsrnewUmTTmH0S3sgJY0hjuOSCLR6sy43gdF5MuNBUePhyYKzKsvwEmlXOXtMdP7ehPXWt R46LqlDYjYv5qpNvZ59olRj3iSH5huYKzfYHOk4LkOJf77kL8hbKeWi2FJIZ4voI2IHh65EfZd1S y3N80oyYjQ5iBZmOkIR85YVRmVo3fdAkiWBYM0QfR6CesEm013I9qqQI5SDOhxXAfYTonUOZohcQ DlhjnVdMClfgJO7IG7duB8fR8W8uDwcy6xAzcurdv27K+zgTKXuLQUyI3hXV/3hKLniuQ1vGFcYK JuU2gpti+b/aX9PJMrj9fHJ1g9l02e6KqVcD06lEgWRID3wU0akObB7h0kOBu4loXz3K84/DIkBf Rt46b3sb5dQfK6uPV+PDd+Pbg2EhqUtOJ6sgZAM3a4eNyof/RoLlsfNfuN5sV17mu/gdiMwoXKL9 ilQ8t9ihf5JmH4UXK5UZFXbWkziLTMQjM2GpUqV3SZYe4AqP8wWIRW6TYUQ0lN3yi6jhPOGPDBQv GCyZ5jZ3i0geyeSv3ftOSP77ToIASOffwwUvf3KJcVqPrWE7Zl4hTXa97dbJGpGbWZtNcVdPg40Z CFkl1TttBYnut38ehnKD7GSDcLgelBJkMoYfAn0f5Fd0o4KUAvwtquj4v5bZo3iEqP0/df543BkY fvpf6lt06VfEKuM40vuJskWhkFn9/EdbjUlX6IWBy5SRL0mL16g7yDi8Qt/leO2rR4qT4Zxk1TaS H4U338vTchyBZjx/B+LPXWyXrnA5F8Dgl59kfXIJXvLkpQBiCGBhinm2otwM6PC9x/9KgzQE8h+9 dtxM7fcSPpe7iT0JVSMJJCiyqDjer0wCThHYt0HHmJNF1n8HsH2la4Q+qw1cXCBr7v1rMqpEeEsh GdSSnVUtCP7Yvu4r1q0ZXAlyuBeHlwIsq/X92KU5Vu+Qgbq3zDKhLz/6zZk8nleaF6QUWA3d1dau G5y+0uoyCqJ9/uhblnqFOv+ZUBtWj8+SgFiqHT+ftioEbNT5oEfN8sdIk/4h4Az6c2Mmhk3TWQNn +ufoZEXyE4VHV/MDC+xTgeBSbW02daJL2Ea0slBg0sh8vrze7v6x2bxBcu+VTfyD0s5124ogO+Bf rBhyiT+pMbbuYVsVsL9070qc+5MANYBADJYFgM8yFhPwrT2jNKdqdV7oJbu777/3/ZBRT+o1e6LJ vJuUPp/YPIPzh/0bLfqMxP5dNoL42LRiOafE09/t9HtaoEOR8bGC/A6RC0HMl+yypvgHIGyRffz1 rGL774DB8e+ODjywuYwwdeGmRrUcFH5d1FEk/mdMqV7bTHNDzJCJf+kBKKEXBc+zhbhgcfCtJUlS 8QqnW/s60on7PfXvlWZPOtLoQBAEnDYcdCtIqZs4BVrp0PKLSlqpID+JRDIfPh0bdvvDfnPZRcYw 8G6GhMmzWhy4kyXGdVnTedI8AQdp9M4XZexrwB97b1LRnJnrZCthKTFKWtxvvubSNGQCiY9XeQHV Z7JHjjnZUYt3xmuFR3f8ZSVjtqv/AXgzg3+5ZjfWVGcPrbQEZfBewiHE5I3HSiLB5upsfkkKqE8b cg5a2a/cPg/X/MJScZGJpELYTjAEqozn7EHlhdEOMvbMvdj3YhFxy/BOvBnT9Kqe/Jdg/CzeePCv KHV873hkScuJ7s/E0fE/WxW9mgPenxavxNPaZTUxaG1PG8KmvBohfnwmM/biVqPRvRRmqxcZEq7J YvZHQe7vsb/mFUdvyme1QnvFV6Ex4CO1105Vklp0uPJNkYXD2pqiORNklvE34T16+MLixsQlrWkw 21bdpUe3DTH1LyiT4wnfFELRCUw/4hLOwI66unpKszE+T3QnzAvz49i3LvvNCnwOWZHGfMrAWqJr gZqEcV5lX7lSbAUMGZaFRoA7Rzox7z3AeUGjuqwguaY5RLqY2pnuam6tQBNRIhr/xpg+uV56F77e u67j6+zWM2lft5AFQLujWH5xmSrB/qjFh70GNFYTPfRgX4sNt9brSDQoK7J1KeahAFBX5lPIW8l0 j4VMw5jl2qm7SFjRxi38pqkEXW4FJzf4n94PIiIfPLYRyRL+naEz2MI8W8d1pCHsbRc5nqvhY5sw stqfOTEtzFBghi1Biaw7qTjbUhFbN1dBrI0IKpMFAK8wCJIvMd7s8a0v7q/KzVNmbmqGoti/Jd4x Yg7e3Uper3M/Jihva4LKi+rmAbS7XT3qLTz4MVkcjCC7l0KT45uvXaW6X6Nxu2k5OtAhNceFa9v/ cP+hCThoBrMWwC6bsDYsrV7BrAhCsWu9WGlqT1ygO0tp2iwx6hHRcV2EaqNNDzLQA4xb+vkVRrdU qYhGj9NDUw9eAIDH7rN7ULMj5y/XRDyEarLJiCtHdfxbAZDNDBAmxrb0fEevzOUzNv69iwu/Z4Ht 3I+hNBk1zWg+IDoug2CCeHbUSDuuPDqTMQMvRtGeANsQT0SBCJR7nT0GuqaqAM+8LzXl6htFAQph VurbwRQff54qHGBfg8BNsG/yp2Hng9AkbXEEwBVLPtfEeUn184zxRst7UGvC3Jxf2T2TqjI9b9+s 6g3dEw+wklp/WLxx9MuVy9NIPGm9pmDC2MVZDs9Rr9Fr93L+OLHBUKYptFX0Cyj1cSqaR0x5NJP+ sdH+J0v7zIUsPmwS2DP+uRgpgOiY0718/ulz1dS1E2RdGTwzGAQ6qo2X+uv7eQpd2YYIPHY5Z6R+ myAYAH8vPU+0y9w7ijI+f0h7/bLKFiUGmNcMDG31riSjHZ/+bw0O7WX5jtEpNfVU6xHtE9zYbofq oDBWJuLoWF35XUqLsSqhYWUQrHsMNutWrB/kgXn4CKGco4Wz9cqDTQGECBybZNXkxXXj2eZZe7bZ HxYB0tP0Cu5VA8Ul0u9BJk9n7v5bnQDVv4I9rkUosuo0iaBX7foc6TCTe10wrf3dhGFbtFq62roO c+gvxBC15pOOsfN8Exjz87Dfd4mmF+dDLL7m1N/OMPwPli7iunsojCqH/LJyNUmSg40llLqDz2f8 PD+0Zf1g+7psnsw1kWJZbT/qdews5/uOh8FbPZdrMRIxbkwAyCp5BMGqjBo0yQK/KfwYM6/HBi2k iVHZmygY9Gn5hWBkhELquZ6SGUKhwZAbsaL/tENJSaHjXGqbdnmGFwTz+sw6nq8ox/K28+DQj7os nSeOjsy9dmaqkhSvTSgt4K80oXUWOo7Nbp4SFTg7E6a3U0IqJhZ+oIX/28NMqQgu1afNE5DuNSN/ bCLHHD3kwHW+wF1KR28S3oNO1rQK/IEE4N6uV3Y7ywHVR5FrrPyqo32y+ii76xRLM89DVUAGHRuR t/RuUSGiFIC6MGfy7y33hN2dzcORfJ+Ci7GQ6GcoIwrNOcQI68LicdQG/ayaLNBvAvXsNqyeBoRJ 0TAKmNKjIkt5tCdMwJrMw9O7csXDjEUEV4IlbxGZj1yV+nMaCqzawgoWWjHVhvCpw3HR0zkiFbgn V3a/2m0/FB/EzRBzZDsfcs4+H/4kC/D0br206XZzgCmxAzUW1PSyB38gZZZv19Ok6/L4Kt0RqxqL oaPQbSGTsu1uGICKABhhFytnty8wjVPs98/qGTSjIr/gAJj2+3ibu9sUSy5WP6s6Xy6pjkWCccVd ExOk5Fo0ee38KnNXiI7UXvZIntuIUcjLG6bwWPoUXeX6xUNsbfoM7lKz8BZqfNQRXIX1lxnl0MHX D/+9ISO966tI/HTr0rOJeV56FwpWTVcTB1/3FUunUBIXg8xK8ZH8e1ia/tOQOyuD2LomavNXUbt0 fKH3yALpG8QQl9/BJsPBFUHvRKOoYk2pQb09TS3JBgTy+R+BafzdQ4Mp/8DRbwBvcso6Wf2+jUQe Q/0Aqnhmc6G9Jw0jL4fV7PLH87nXSO9BdynUCuvHCqI8BPUo8Q8IG4TM7zWcBAbF2OZ99J+OlAgs ZG2g1VjAvbH0EoQM2WhtlQDNL/OR+wOx6TgTJL9YI7YZo+mjWHGc6KxY9zpH2dYaxjztLIDpVwjJ 9Atg5X3eINZfxqMngEo6nJ8BLC5FSiX74HuLtq1lq3Hz6/8tgbA3ew9tRLM+bBde+eBh6y0Do8NK Oj5c1N/5N19fKeOdgSeBbHesHDaLqi9P+3Vdp25sF/8WnaSlj62Z3Q8v0w52291LBGfakwGLMqiM VGYAQSNU6pZkAgS0Vdeiit3MaJ9Kdq0SPvcVEtQ/JQ4BBlf5VRLvIggkkDOpO0KDHfymTMXSa2RI sXHgj+uut8JZO3l+4f3KdksdOzPyMQoneWWbnv3Ya/sCEnTxDBKCPdC6jpameml7HC4Z029ropyt cQY5EqqTtV8OVKLeY7eAKNpR3KvikE4MscLErHt1sD0/u+a4d++HdbrIazPPXwUMJFwKbFvkv47C vSX6Wf+w7fDIgZsQtP9eO8xbPA9BJ8vaL43KaxbY/2kevGSYOiJ64zUSaYi/QvXpewgHk7FAijkQ uEvfc1I6dG2rTKlL4MBRr2JcRcV0XbEa2mc5LWGdBKbaBHwIzQKYrUZNvwEGtLi9FSH17bhsmz9q 9dNYhUXGIFfqTFPy2br8j3Bqwo05I2AGupOw3UZbz7h7mDOPm9xg+Nbs+4QpkQRaHsqdFN3S3fUz DwkpVYdc24f2SFXc1p84G474QD03LCJfZNKCYyfg5T7Ne7AJG/DWWaxvwi9eQn98gFCjSlEIVzcS Zxu+dG2GK6rZj27ZB+KN3iKmxvD5ZsTw+y94yZyXTNWTxIFjsx2nArslujPW2s5Fe/7fNv2Db7az KPMjVrO4j5447YPWVgaLUCATKIfYEYn+jlYodwshVMAK+6joc+K2Oyp66dyxsYnObllfu0CHLgyI 84WQhjVPn+l7U232LYo9Xn/XvWyqTWeAZ6yfRQ5avNUi4WIF8Z59VfBkdFoTLfQ3BKfvXpwwNPow X/1WE+dnwYHKCNvN0j0vHpp+1Q81t9/Bydm0eoqExtRNJ21Sj+dKvyHJCT6NsSz1X6n5q9DJC09l 593wlO2MIp6c1R6AIsH1NQyeQZaJwUrZu3YU/ejZkxjcUNgHMML2yrKCIVXVKi8PwZKhMIyZ1lC8 N9wzWBBG0d6eg3XNFnFLFEcEW87P2rcVFLbA3EpLSjji7GT6sIk2+QZ1bBsrDgV2i3N+G5YxpMpE fUWeQrXsH2YDCJSdYIpntkrBxWbtqBI/hiRMApnStg9Nvvt1cSPZExgbjaHCy2qbTEgYyLiPWyNQ 19Yfxjy3R+SkRzCvzaq9GmjwGXN/5gDToJvqRutKShJmXdYSIAlovCpb8eFcQDnPoigpJ0W4iOM1 qAMF6HzAMJjPm+xUk23h86eiKthJvKSyl4uz/3OIcYXRtTBFzjSgm1gkVCSlKZNciu2owywS5n49 Jka0rJ05YkeDBz8X0PfqgCcmgAzsFqed06EH9PP9ceh8I4yt0EcSVFQwg/55iowg2m+gSMxt8Lxv z8bO+/MYH3iNtNB3F+Ieiim4q/XjWdhFIIk2o7+K63IZ46dqxrOy3YAQKcAdMI7cehi92LLZW3ae IySX9ErTrItW9DJaEJWahcDqBLMJaqUxXdxBLctD5czwFHFsuBGtNzDF3bPEEdENgam1iE2Ir6fr wJPqw0zG2wiJwTSLBbZuEXwYohcb/00WZenWdlS+17hph1qajid+L/phC1uFXQuG1W3gha/t12QO tG939tqRAwpxouUJUByA0RFNCtG9GFEyeUaY1hEvTlAHmKaGIw+IJxIxYFBCbQ0rHBf4bkjTy+IP dv0HSEPd7gmGS26cOYcNScK/yy36JA+YHgTA436PRnv9ex52Ej48BaE2Jb6iws+BXYLxug0FCDll jHEX5WK7FlSm8uX91GBmukNa7+FFgoY1ANS7WmFWwktlkGv1qDqtIMbjSaW6QV7HmCGn0mo+cNcu +dy68/OAHOUs/eMpoZwv5cxOS9oMOzm1XH2QS0S6TBVZ9/aE6diihKH1oHujufUqtYV+Bsszs8Lt /BUK5eQbxT/ZND7dUQMPL4IT1jtMfqLwVGwAIThkODxB2JMx77fSb1lb3RX+2tspsQL58dqRg2Sg qiDZo8si2MML+yLUfVHN+CKP4KA3uvOnO+aX2NRKZUcBkf2sHk4cfXf1MlMbpQ+/r61EFrIc3HtT r5kcPeUT3xGAM2VJ4AmuK2jku8sCXHx6/4XHhjOO5j/2cIkHQ0hVzQli1n8vdK563QQZge6ZO9+m 33jVNuVqrDYUgb0ttLZxYUw3OJxzGMmLpSehCYlpV10dFy6MiAB63bdpQNTkXqXMVth7511G/cPP tMJEWEfEQJ5ePFnABOPh9AvrOfh3YEgMT7dJjGP9D2McWwEe8cIcZXamN5QGVPlomVZU7QVloiZW Q1eyihEbdU2895PVML1kyBBAI6ZGVb5EMW9Ua0bYZuKbViJaHYAvBtKBUeRGX0k7upRbaZ1X5huF D4en/aJ7GgnLqB04vEoPmZUMJcYrkTwpmnLqFtV5sEjfjgWINNdUae+JFDYUALzyJTRQFEqJNIqf +zbfM0F563ofYSdYiO4lCuAW7p/+JlZQzspWPFyJ/AuEPmAIFGNh13KFcEj6uQzwIG0MFGop5nPe TxpedSYGqqM6gChBparEjKl18WHhb66kP9b3rDB7nH3XY+MW/l9C/KWKqTsKFkekdUhiH0HTkqi9 2wNpIDExBillj0O3yvaqmI1kR3I7e9KGjkOGObWl0FMyGuhaOEQQHEbcRQTqjyXdDib/K6s6mtXX mOsKhc5gghjhJJ/i6uIeYEymUjH8tS7BUjT49RYBWrP5KkteBcfhuiIry80MW+PQaqbfWSiBmXlr LSpHnNWizbrhsiwNEL2Dq0fUSwyCNDVT+iytuyKsymqa/4mgxkWkdNfm5OC3wstt/OG+t8n6YXA1 O8rAMw7Tx/EIpVShepRkDSEQ3yrMQqEsvpbgJoFxsX1HLgCg+yPTkzB80zIc2lxor1NfoZT6OggF +5TJHLNSbG7F7LjaaWzbqGbZlUx3hNN4p8A7Iux2GgdR2uYWqf84r/WhwKTnNIHANGFm1+dRqhKr 1dp5gmPTewYqh/1Uz4ZjZVGCOGA9ZLFPqU2SKhhXmRNOUx3ZPQY8a5IwoYrE2UVtjVUOGQeOhBb/ 4wJOg6bf5h+iGKAFsPeHvHScMLS8i5U8RD6EC5r024dFqRFH8cVUNK+kPkoNlFMPr/mG5Pq7mllo F1v0UVRMARBmbViTvtkgWhqdPgHHFyJpwOB1Yk5i4OZQabH9EyKHbg4seCoi5zNUGuZ9OHARAUYq McqAozHSoFUiYB5cO/53zyqWNudQqJOjjpKsNJ98dhRtaGaiU66onKqHTup8njs5PMax6XMfZHsl kk1/ldofRTjHj9nGZdjiMkoSRG+ep811/DWFYzflsCW+ci7MoRwyIGEtTDDaFBVbUp9uM30Gn/Qg H5Gxe9nPqlFpIBEZ95waLrMKJXGMhHqKDX4ykkfEA1AhZZtzB1CtLDGI3wt1ryyTx8AwxPyaz4bP 4Kje7guJm4iqZONiVotWlxT1IdoBI9emQ4N9E+XVJdvK4b7OY/0pfY8SncMBA5cdthYJfF/04qZJ WqhWjButFK1qvMMTxiO1dvbUZYYQ4ncpPptHvxbsVEWUCeV4gdaW//hdavTT9UGu2PXFJHTiyY0a QXVT2A1V+hOXV8g/iKhpBSBXEVoMAeDOo85kAc2S6qoczs6y6st7oQ81L5eiYvfaycfC7qf33x9K OouB6g40xk8qsX15SXzCK8IswVPcuwgMKvkUC5S5t11iqZJyLRzbcKrf6C1T/HIsPRKTWAMhMQdH VyGqtplHfiQNB/wuDxlUZ4uueYId3/qT3rmmGNbl4P0207zHwYwy8SAY6giQkpcFZ+X6riuC3Yq/ /PQKtW9lqjXSoxEYDCM2G0HNW7SESFI1sbQFu5gxhaHH8Bc2cQid8/aIUDjSsRe2w8iOUvHbCTo+ S19KHY8rRMXHnq3x+htmq2tqoWWM6ukfBDoFXNcriTFC17XKh3C3ux8J7G7B3B0SRPCsd9pCzVYE k03kaAhzSndJRsfS91Yor+QQXrAcVvAqgSsym4uaRxD1E7HKQVlrULrVDeX8UHT//GNGUvWXY+xY Soa+OLMX7pa0iBIPG5nFFUuzSxI1guzZXIHyJ795vqkZ3ScaBu/s3ig1eicH5gWeQvuhK02u+pNX P29zkXr50z0AmJzSPHFd22zbnGpBTbJSXEKCSxj9mBoRpObUfvM27kOomRaR2oktGHBgWIQ64XD4 qatiqCMuNwvAptVE1Uzy3zjyD+b80tdQFA4Hav7aM8xpqG2l4VMh6vbW8ayb51Xoqb5G814X6IX9 sejvVbE0MspIM80lQPmIV7lU/JhZhL6gNmYc3rAwSldx2s5wtxlNzUmEZXOpwD2bM2HR+iTLtbQJ dfuBqGLpDdBFAbpCjHxMFElkaTeB5j6zMOiMn2u5feXob7LArpQ2t5JDg2bh/r6StyAYOgzCuvxb K5vbY7dRPEdM+tizaYPMuUejfef5DaP8EcVF7tpDf3Lrx/ALcMU5Lb6zNqiXJs6fdzRpf5MgR78O yU1afZWLFtpuTuqnUsvpmGsa/4AsZvRVVuzg8kfHiEUbhV+bVMtHeM4d1Le3pchEOmBj8UKMQwyY irrN1gJ9oeqZmL1PUdnq904Dzvhju8/iG+N0d0c1RVP2NboiEOLHQgxwJ/MPBnKPZvpwxxGfINx5 sd5kM0QgG5eZ5XLBk6Uewvh+fmaCQfQRFj+vhHSwYSZ5Rm0KpuqpjBUNoQB2VSpEr0FQBB7ncgd8 bFm48nhhr8lU54yvc+X8viaj9/yMBFayGrojVNE9Jbm7pfdmTnktxAYmY/13VCpW4iVI1IVDCW4g vJ+SvPe5NkVCF9zZvQpTZl72OnvOt+XARdCt8BwXzIeF9j/ew3cqwcH7FqJRrirjFK12EzvhSZqM tcCp1bL2Y89S2D09KdED2ZqRWdkeTfu4DQWrPixM+RVfHqqQo1nAutQTKnWfYH5U2wwO3AjCkCeQ 3qPMOn324WDQ/26gUNImltmMvPNrjP9GuZXM3vibMBvIefyL2++Xt5ivymLu0GcWEidq4uOn4mtW W3m+0+MXRjhh5vR/WdLoDEIiX7yzx2qoxiKSJBPRMnnQdRMaUVPnizA+EdUn8e+zittzXVNxfoJs UoShqyHpd2H/6t97BoDpy4ou4klJc5B1ICipayIH6dbmIXAcbeNzuoonZeN4JLfwMVX+OJ13d497 D13vw7kO9TqpObO25ME2Jb4PP9r4dTEb/TkyjCamULBLieCSjkc4wMHerLNzzidd8GbZpJSy7HHO bfPL5G610Hoomy2+EBQViFa4U4OUdVwjdx5djENtL4e2IzPE5k3stUS5KqT2T9/7tZj0hl5cE2hZ hFXj7cOBhA29ikpY4PJty9fEuaSOWmcPVRqDuaSAjugOa5juYK8cmYkOv9JKNL4Ldv0egUFytMsH FB57xAByCgN+JhWZI7YhRRF2ihStSmiOPws4C31zpdSI8PQr/3HG9lMXp3KMowKr5fJyUhSoOZYu h9B+KNzTzme5aqMK4tmFWNzmRNr7SCri+lAx5IlmbOvwdF7ft8vtUmnyJyo8ghc1Az7ap/IfYBAV bBZR8IbJ6tXmS5SndxKB4C1U7QOsd5epeKGXZi9Q6pp3hbBWKS4Rn8aANK8J5jdIfrJoCgb9KZfP MXAPfF17Vq5UqsHFDJDex5ey6PY3k5MYwcwNbn26yRoV1QZDttuplmdo6z3kd1dNK7XSGcGy8MxZ d6JYLZwbdnQRpAQGuNTjxcCGod7ou8EB6XIG//3CSx3wmTZ0Agonef1T1bQ3E5jNYYvCvnWydlB4 B9mG+fEQCJKAyd/nPBLX5kP9lVq09u9qisiBWUBI0c0nCDD6Zo+A8EkmUGfEuExh0VmTTU1t/3/V NnjI4vVlM1BUX2D/bYHRwyaniD9dc7PNrGPWJTd2TVDnOkQxARx+VFGfPmde+qNfbULlWs4b3YsJ kNugyAB2YLTvQthet5B+yle2Pi7MiZNBwRY2iKuQn3cMxT0v4RMo2cYnWENco8sm82hkzQkmobEs aR4Lf5FszK+I1dN9WD1zCXBYuIDUQ577b8zraHNJcpZZBbV+22CMggaPBzW9MgKr9xOqFPjCtRJw sNyd4Vo7eLMhUM0tpN4fkXnzYY5lfNrWiA7Y54TeBFqNTxuGbPA/U0k5ra5YVHxJtc75wiD0uE4H sPvbeHVquiAqGikWxYidBPE03yk+sP6dZ0NBIwSAR4hsFSYeA19U+fjpBEclH9aOPNPffJ/rEW1A 94B8N/iCSO/U7SsIj8yfJRhPD0Af5s3jWBc+prCSSIcG6fuyMfqHVksbzbgF/jF8591x4rfmcO2q mHQOFtoiDFZ3fGDSLA/So6EG+2EReIYzyFGHlnTBq0W21gIlNDWKJwrYiNIpfW/hj6WrSNWz0sZC eZc6Fo5/ktF7Zq0OoUzpQgDJNb/v9DMjWcMXnrrJSKhxKDoolsphmFl3OcAmdxNuSHucerioPyir GTofiWVtV9E9A+Z3brkQM3uLLqexiN5nVzPyulomTWHbEr2B8dA6yvE+4FSrlw0BE4ttiGBmnQdF Kz3Rawil57VvHstonVbe6klxyxhVQoQIy2Qiwlh3BPfpJy319luGx/v2BQMmt6/dyMeMg01hkBMK O1zPoAds0YkfOfN6VqThg75mx3yfZjPkoGs+W0QWszm6cpqOXUtAlM07tMU1T3nncxaMfi2bDp9D gb4yhmBoy/rWopz/1hDuBN3ev7yaeZxPUZAD8VEkq2TK/cKsrWAOd6OsG3ogfBIN2K6CS31Jt4sx nQhA+RJeWqAC/8kTW/k99woBNLAVfDaRcJumkgEZ/yiWT/cqQkPfj/Uz5wUL18s2TL24S7gyxpbJ 563Fda1OafaACPnt7k7Nc2LVGdbh4fJcUWx7tjyxIYG7ipQ1cRSSmDaEIZmUu9A3oMTUp+Ls0jKZ 1tgI1Ilh4Xkgz5Na4QIBAho62Ke/FsnZhWGoTY8ZEwJmcPQBjaCFPEpKkiVvfMSw+hDcxzWooHR1 ntcb22Jz22inHRe+14leWL00jx7jj00gLOJ1rN4AnXge6TF0iXJVEbi7SqMMr635KRqruibsI/51 vULyz6Z3cn7Q4yoq3IAxXI9A90JxPE3egRphlKuCLTWYY8Z8Qbgdtm4sH1QmvUoJnM/3uObpLv+T DeYLlhKGKfVML/AtT+ZULv9u0869rS369zx+F15VoBFZ86jRzo0L6tWCEkVpG0t96gdPwg8v4HFD 7j4iOPPLbEAJvKPU1g47k/+Ocyp6IIL43iPH6MeBjdh+jkVLN5gPrxp7TkdLHjUvSRUo94+azli8 D40oIFitPn9uYTLfxjNP2HJBcZ7OjHfMJCvB+zAQlW6XNETHxyPVdT0KyC+UPH29SD6IfKMIZe9m 91PFIRfNxicK3mpCQ1jPGzGqBQdKVkOsND4weJ3wrmTvisOp42WJc6R+GuhhU06lswoDiiVxGku8 3YvjtoDnKBSDf4qub3y5+1TwWSzD7b12ohJUHKt4YwI+I4DN+8j32PC04iJZ40hgzZk/ZczTd1ox WQVjXpvLAtMYMQnhwByD+BhHb/y+0Qax7vwnOPTz98xqrWGeJASTdNSGiWL4aypI7BSaLxclWvkk B9IfjBm5sSVZVjwEB3VhnRTzgguskRseb1I2G+WOhjV0W9dv9K2VJodK++Nm6/1gJ/3djlLAIV8g eLotYiFTNQJkLh/IcjTzd4JlpzkXK0j5A5JuTZLjz1hkDFfu9/sFzQh4AS9PNezG/ySCqkrJxm+R D8cyy8JVoJKh51dNrAaVikeoksVcD/C8B5sg8Gxlao58kAAaviisMcYu7AzDpjhNv0MhMk94I++i Te7wOg/BJrdcn+s6kyV/UblMTX3K6TVrEQb0glvcK/BKq67P57d7RmVZfMlXdkvGGbtKCgN8fazS sGgX0RORqoJT+D+EWBb9QFuSlngwZow9cR6qJDQwuXfqSl7+NUaqrsc/Lyl0GNvha/yHGIm5urFO 4jxsf4W4aAnzmkQDfcqlM0ZI+mcgJaOa3OCpt7KnC+UfMePoa7mJ5//iITT/fKhIDfK1cGMiBScm ZGkBO16t2kZlPeNyobEHQMhjdS114Gu0Vvw/0QtYGcc+0bl4cNsEvv1JWMs5Ijpubb8zn5UNufBh RoPqvoQpqHTzCDEMgL+5IMBLFbJ74M3oQdfWoL/UqW4/fxInwM1gIsNjQ5sTD4Qm7Zvl+Wtgrdzp m0CCFTnRWSHzRBHc+J6JN85r5kC+rdpl7m+194opWdJmbX/tGA/te9fNyQ7hLQEX2z0my1UTbPU9 XREMEEo0DFyV2xP6hJioBnIm5ICFLTl6WT58fgU6UgZNJNXDET6Zxenr9JMYWNJZlQ7uf6Ct+2CF D5FJJ16i7IsvixIjiybFsLGMRCllLBJZszxorleSeQrYnTD2gNqC2pkfcGMQmO1qjbdIvjEBxEAu qY9G9EUExPnC+qM6L5QXM4kuzRF3eAhmyMTAngWrkbVP8bOiXVVhMnEro6mJR+k+WBc1qHSe1+Wn sQb+QAhkeHgsQADJ53q2r9FgGtUfcwJr7HPpyXOZHFTLNiBdzFHKOE6yeo6rkBkWf5atN82LCM8G 90Hw0v7iqE/3IP8UOZGezSSdFDWFqwsuFg1yw6vbTVMqEL8Qcj7JEt6kZ/P7+msWycqWUWPANyYn QcgOXoZ+qqgLiHWWFGMbjTAPaaY4QsadfJqzweQsPoKbclNBZObkiREjcicIG/gkJ+P9fB8BZ+rp xgDdEW6o9F8t/iov963zL3vG306jh3NR1cwxY1/miP7OynuR2moXAH3NEzY5Y7e/2hTo/ad5K6wh 7PTf6bVDYSe3GV71/Du/lT2Fg/M8kRF++S+Ib8/HWyfdSrzwj1HppVtpVHAEmI6RXDtKBTv5quai d+n1F/aEzmfsyhZYj8MqQ5Tb45cDaSutQ8BbBNFXVdZ30i4s8F+prc1Xt8eVtkkUKoyBVFOZtrKV KZsH/AgRsheSJ3/91XBC/jbSmLMq3U49Nkd4Xd67YzLeiGgbFASdn2Jv6kIo+Fguzvrdnb9IYkqt MIc3iA32/rfjbG9tNYQy4avV3PeagLNX5J5kcpQFFGiB7B2G+yBio095Das5YZYJyv1YbsZPgR7Q Tiyc8VeHOieRDMr/4VG/b5bKA3L49PnTm3YzESvCmKdqRFbLpXcc5ksMUWmAkBH/MnC12vo/spZ9 9yG7EBWApqsPmrdpFpUI++naiH5fRB3ia6p45niPcnoeC88Dp7AnSmwXTHZw37tk/DboHY8/mJ8C PJuX6I6qTPNLl8oSfy7XOx5UnXGTBh5gy9bsfNjr8MvAPQxUAm0RfAhW72lo6HGUg20rm8PICzok n5QVe/MEMl+2PH4j0XX3NCiMgvfTOIer84mnqAhWSu3CMIyXjadGVJir6uFDH3kUkkgW0/wB0SMg Vu8B2ETzftq0/UVtESoYuLzSz4cbcHCgpbCjy0BMspzVNSn04cmjAOAFf8HM53iaPUsX1X010IGO GTqkf4Vsw/3tYfNoySjFzeRg/eU3sBuwijIiqHr/JB0R4bs3Vtc97iYvLOIAGnZpyZritwRenHdX 5YmgtJRiinI0gyjQu+9VX4xtmAlS682cgUD1TUgrtBlCXL8eK29vpE0pOUHNqLHNGQYBs9P0iZ/A RE3pOzycKLcIAIHLPcCyzu847O39Hjwr75c/2ZV+mdn6zAJbVs7AQghnCOQXFPSL2Zc2EE6KDHdq /vV1bAe6qFiDvxHFQWSktZM8o8JrlaPF3nv8kpGwUOHUi+2MxjipjkqhuKwweh+cR7lm8m/wxml8 O/x7TqqdjWOBmkL03WCbs5funMA3Rr1pmFV0yTIPopK/UhWbJg7hP/dly9viMpCZ7U5Cr/Y4ZO2o 2eLcTMzozvQ5ZEnB1sXlgJbClHZdKR/gVazYkKI1nSq96qGjoxAUU2X3U2DXt5HsECYQ5Wy8mk6v u4CR6LzsgKLdUtiKSxYBZvdwTOFCA7yGh5Dk3MCv+vPKwzzISBaoUvEx9KJtjUDDN7d07IL4bf4d qe/npNTDFzkd6dTIJBIu1C1VTKlekom9+NbRMzeCXT+MgNvCbjBnIKI9KJ/cgvZxtrev6doldrQ4 AMyy9WDc1TmZTdd/S9s0a1JhjvKsMZVtx2kM0vIiia83ugyhnlVn8KHROqQbl7qCuQjuGcAGvB3q xbUQex9BVc7f+SM0RrnIro4h+eLwB1dpVQ/OyYK+EuviPt/icw5fFwGujd0+YoMJVNUm+KBe+BRW 1g8xOWTHWpX5Dt66M13G571FWk58GNQmkxDDhCoPe2GONEf8w7nKpeJcOKBAkXs6panhTDsYjUuq Eh+LgaTjeRpOexGWi0zYtkXUSmWs+GQpCR2mnddPGxSoJy9ysM466xxixmeRoGa2E8pqNwXAgnop uLECpcWgk06ceTJ0Mvtd3uVfhWrJbUHnQNLecfPF2h0T2A7PAivcWFzuFalBVIupDuXS+SST3J0q YkJ7S3HiuEuVsxo85UwH2PkbXVtfc9rLgnvk5JP3tSeStg5VdZxKZ088EQubAsaA2wD2ILumXT6v xmcGO6+69dNE5ig9QLUkdL91sJRiG5/IWuiB0ILA9xQ22AWEWd7mc6/wkz4JTsX9yKONr+DAehjn sacJ9GuYCk5VHS5PoKeyQ07bZAK7J5prUkJw6ZmOCl7RnIdonrjdtmenpTshkxIVNe9hKXYKHMce iEE2jb47ycd/r2mS+rpQX0UqmJY+PJxx1/4XVblzMJHrXoYXLFAUlwQO9F9qQBnNQsdp+aPg2x65 WUqpw0oCEZUTGlVHeIvWE9sJoOrYPtn6hf0zscdOX1IpW1vx9lrSTh32p1BLBp13KBocs2gCtdyz eNKDq+6+J+70oCiZI3Jnp6aURewVdOWfA433Zsas7gnNOcttW/j966i4tP/h/RdKGWN6vRzNq2nX aU9pL1UNh5suFD5H863phlEdwnJ63K2XljrjgXKgCW8zTEoozdVJVCOhCtPr3awTqrQeE6Ejq7wJ FpNwTMIAx86y/QeiC49kXXdNejP1EPNAXrtvunqew3lQIpmoDlnbqtiKdJhA9MpxBpIW6oa6pv2m d9ZUG6N65g5mbkE563ma83LG3rmARCp02rOWGJE0PEGtA3nETNZsq9Q5Q7/mZm7mJwWO14btmVkY 8UPYQpF01JNlwqMZ1Y5Sc4sXSYBhC3YEa1iSkVbVb2T94Gqhq6hbaaQojrK8Sszz95r6t1stzRkt qQcyzgO8iwgKB4SROfn7vA2RjtntXNKFGtBrXyiJr8RijjQUMp8/9mE7GXthmicXtelJsxBUQ3Cr PCxyKBIINYvC0yeQgRDF5d1FwjcXHTl/h19yWa3eTq3/iR8V+q9n5+kzA1pcBhyRPFmKjWqlr2dO x7EV/7Gl/JZ0TYiEzL7cw+T99F016TwXwGpFOG4QJLuQhnEQJUYOgzNbdJDjEA/SqFeB+gNaD2zT erbYRk+8s/I2Yne9viEAPyZmoXgmlo/fn9QezGvTDHMqVR5RpgeUvga0SuqLMLYExgGecS83dmTT rDWGA2wxPKBVv7QuOjwKII+Yn3HmTmDecKT9U/Itp0LUbqKlZsd4CwR0BxOL4SnrheqrOU0Dz547 bPMQnUvGSOLMiBxZzWR03ZwnmaVBG4PRtOQBu2sH8yj2TTDGvmT8/5ffHxTZ+MHhUifTQP86kh5c Vkde1t7UdiCxRSwRhCu1pfJhUv3EWnmx35Qb749dO/uLrzNSPX1xWtB9D3Hu9GWqIak/bRwNjDj2 36SuJbIicaCpWzSGnQPeR+K5juUQ3DOtTb16eM03b8QsZLBELfpJKfcdXjXSjQlWArPfdToYl2su VuZW1UAx2YE5UMxxibJXQk841ObfsoDhCPHANeA+dZcMyd0HUIp7kkN9VcG5hfujy7P+0FlJ/Rec tcYDgOtSnMf+R1Db5I13/YDUludSAlrYzLImNSlrvJT07T08KrlueFgf0fkKrg3m5LPjn94FQkq1 A7Mim4T/wTPLre5/+0QbgpTwZhmMRfdjR8z6VpqCGEu9trN2QJUHR1FRPCfgdKM52xnlK8BFoStM cft5MQnGlX8jHxkxbjnE2zQWxomPt1b/GaNZFU+/MJ4Z/Z89/agL1y17chGqHrmlkjpxA2VGUMGW c3tk1xKS8aQ4NhfS4s/O3ZIJcqASsAC7s2UdpdFseDKHw5GTm2yBOgdFbi7j+DqaxjDLEBZG4cTK BzTI7cI3SRcV7lu7QbbH+aMHJD7BCygcuf+lbjLQgvQ31Eowmh0vHbFQ7Z53ibXP+xzy325TCYCp ku+kjQI6mQTu5TukbFcDNdGSISNKrPlqHUrMUHwk0RobAbHYjOmfpAFJZVBnPE0gCr63rAU1w+G8 B/rbH3Xhv9My2orBURiSazAnlQtlQxHFF+USL0RG+Q6iGsqG5ygtCAeG0xRjedPQCNZs6mRieYY8 9EIVhJ0NThOD8oi2NFBZoEaMD6HiF0IFCyQD5QF+iKjVmhiGDSZSlz9KPEkRENN50jS5SjEBOCm0 TtcRd4ibJj+waCzKjAwClFaWEf9ErkED+VLSAYJBUcDl4391EBrTj4aj4C4QxDPI2im+gw3gS0zq Hb1+9emIeoqa+cKSezMNMmzr6V91GBfRm0EVOA+jlZk+NrZbmf6idxCLr1mtBatJAY92V16stgfm w/sNQt+ubXazBU0U3aoB8my2EYn2eGAYsugphoMLXMVUJOsWy44BYOzoD7cLnuudg82wAH032aY3 6mQ3OhQ8zygTlTaHd/ZotGwSxIiq7Fy3xzEwvHhU/ntQLLYs6ENwNQOIsg+HrbBk7sU2cQUhtHzP SP7S5YTX8OiVnPHAm5VyQ66GhWd503SqBDwJg5gocwjSzIIF8wSLxRAvT9TFh9O7UwiNyxXpVkKU kwen7SzSkmaS236yAop9LZPrJjZH4rGEuPrRo9Rq9fhpwwMErEtZUuuK4z6/QhPVFkXvbrM6sy75 b43hZeXI7jqa7wzC+tHBYjqXi5x3YrS5e4OaMtLPQuoQXU+V+U8qdnW4nyjj1eQ4s0duIDTg7e8Q 5s3uCT9YUS3wm+t8ARtOqpFO1kEGQasuJR88PtAx7RoJJYazAgaQjdAdYikX/65woViZDRGNcPKf cWFY1FjROcfRHDA+qR4LDuIgmyhn/vTHkE6vDpmtqFAFMu2MZPKJq2lbbRLBM2Tuaz11ubnuH/ty idmMcuYuWTA2a/q7rt18yHtg/HrrwO8nBGXG7dXdd1a0emdzqJjIKMHq6NR+WBlFjScIYw8wAOvQ IHC1g5f40GK2MMQ3mTDHRGodcS1R1UPbcGFNq/xl6RYfEtV43U9GamZGuuf/rb+DSGPg6i7LJ8hn /uDDj780bznBt4cA4yMgLoiJ6Lx06gMeYyxYrOOInL5cBUp3ecfWQJrvkqYOGh/Uw0U1/ZWqaXl2 yo1mbOUCQwsbyytr1TAL8YOoHl71N3+LPaORZZ4cWIjdo8Dre8H1m5RezVdIAzVA+MRxf1YEDYQK oaAh0gD4qa4f4ZG/+tXIxjyWQmibbyLUqt/hOD1+JQZFiU0tcr70A/NNsQriUZM72rhCvHmuchlT fh9619153yWy/c0q0mdIAJ3cCq312iDpcwTL96tlQi9hmHjAM0FcIqPxPW5n8jyXsfCmKG4Xwgwi TQgmRJD5LyOCfL/fg3g4qG0i3/23dNQnAiNt6zTKPluBVV6HGDIc5chcnya7QFDLv32G5l7Mr+b/ YQtNRU2GbSnaIYI08JaVx9JvnnRUoqMyTye/hr/fhLj8aRK3xs2O4UgXc40VKD/XyMXFioAbY0Mb jcVIVcW3Uucu+XqFAUb+ipvtXAUy4A76HHjpZ3qVQc9pq0vVZwNroB9aeV5lTzk0pEH1BLTmCZHj fENHjlK6RF1LHrq6v9dzEt5s2z4gPPxaaHq4kJ9Jl9Y9B9WPq4w+1ZW3bF3pgwy2GINCS5NNXLHN LmaE4GChqlP4IRTl9/72Q8dpD3urxD7Y5ndl1j8oBYebB1JX4HvPliLkWcrfgHMDBnQvkLfpCW0x e9MXEL4f2cIpgZT1LWTiPko04wINdopdx0mxk2j3HLLZPaxxRDFFvb1bOEfudUpL/Obqs0ep/TxP Zk8sHyLFZ0S7H9c9WEBvBpDm3DaEDN1x1VPLkcVmuwjDpHLgrCg8ZON8FRS8vbg8XG7PdWBcMD/S AaG2SIlDrCklUzKANAYzM/QsIJ6QYME1Yp149OL06M+v3yzkG3nVdbx8qCLc8wcW1JyDqapCC4rA BwczrxnGmnhyM+BslwDqhDvx1JGRIqnvgfC+d75FSt2DjEcs/oL9vHeOC2kttfMmIDsi94n0fd8Z xEbvQlGkSpSpN8LOAfJz+dbPBfciO1ONb3s9k56u04618PP8V3NAxlvA3IYD8W8qy0t89KZaHt77 iVBd1nBjcp2KQa7xHdL2782txcqjHXUcyEgLXSY10ePBiPQbJoSmMG7UnlgLui0XHkgFO4HIHrNu AP9W5LtrxBWHzFfVVf6Rw+m9WSov1YS59O2l5TSxod6a5xGO/m+2CKd2FIhk7T4A1HKYNxQH29HM Wqq7Y6nGFyr5v0M2tqQXJLyNWt14RlXtUkP781+wdgAxYgbgjo/Q1N0QfT2/XTAcNkf1Zki/Rdez mCUii9+yaMWBJidfCpU+mlll34nS08g5TVG9PsSmIAeaGmo3IqvX9JNcuytRq8Nx8yVzxMVnGUqW Apd/RZPy2sNbOeZrZZ6dyssD86Wk0DyMLghHer+PbTdRA3St3Sn5pEjYQhd0ChxUxrgLSqHAX4sO AQqxkgcofIQwCyn2zW44xsu+3JDiV5Ujj3PfzCy+gd7bEU2arpPYb/LPEfeQiwlGkZCZth961lsF yRMI1j9atZKtcHiKcP/l0yF3sOG9gJHvjQKrk4XhGTVPaOkdBZMe/Gf2UNDdsVWy63psXNQxJ6iJ hufm+CrrHDDc15aEQyHCsGqb1O+SSBEqyw39cXXWUE0a7sNlsIXiJuz0jbHGZ5RdbujkCLPJFkqx JRyoo+zDnV/94mmdjE9PhgHLz+3kqKmqD2eVXt1HZWN1+R6z3zHv8K7f7JrR26U2mwFEwu1/CfAU g2De0ueTUirCRmOtijA4EAxMA7LZdasMeYNqcfj+RpdbeD6cDHJqgGDYQ2qj5idOBJYItBg6hLO1 Kc9W/YSNoOT6McQiaS/c0ACQQedGsqVvEbFIKjy9Cfob5dp11K1ETqsD32x9E0NRSrwtz3prmF0i SsRnuN6gV0l+PZRcepiW/IQrmw+Y5J//63isiGRCrX2zf2GG0bbx+v9JqwDBWGYUXxoREDxJwrRN l73XV8X79ZfF2XsGmzEhezWIRiu3F3N1+JUt3yEcJZ8mzbZmgOQqxl3B2s8mRtAWDI7Cbyif1vrx xAS6pjuZlNaOwDuEwj8FNy3YlBsSdSZ/k5xVbMzMFRMd+J55YqyDwfZAy1L9y51yurb7h4wFZ2oo XS8CqzXbZKY4PDNo9VCIWgb/XkNxHIBKZioJ49Er4j8/iQxFffbQGQm9oXdaNChUyjGRJynXMATP wRFr2y3YlSynem+iG0/SnM9FtBZWDamsSXd3FAF649frpC/hSXtCl9QKTCl/Q+iP1xkUSbIO/LxL hVRtwBFtReDiy6KrJ7b3iO7tbe/Ml8+8m0J5yGO03o7oq1JfMplkvUVOq7gi5JjdmLNcI4/tBR3a C/O5QKdi+b8UFVfraEiu8bXhpUW7NVTKEJPewUMXhOjcqbrKUigT6SnRMOpAIdaQI6VstcKtOAFo n+CzxvT2TKCM1AVGzDNhwH41bFcEwfMIVorOXKtgkZnOwrbzGVUU9bicUTL3Uq7j5Gcx/0JDFLcG L6uSE5padX1S9zYpr5vLxYOV4yhB9t/z6TrIrD830OEKwxriDm4jgCmucMCcHvjJ1LqlV8xXg/40 hEOyQ/V0/2zxqnco8dESYVGWT712M+DjojoLFiY9uVL8OqTwn918lmJWdKxoJiieOwn57LrhVlYY kreLGfdcWhHqd6QVr2PKLg7imelgADxmMesFk1VkYLtixjnwJgdM2I73CVYHBmVHR0KoZH6t2mmN c/Yfc9odJJBNrmWoJ82bUIvVrQYPYGWGEktjO+Ws27bcEa6aw8angIG9uPRN/mSawcbWeMriW6Nw eSUXAcSNMIMODd0zZ1rh6JAGV/dRxj/OILps6wp7lREybXsY0RFkUYIGeX4GCqbgT6PuT8VLhFwe +zpoFvWVECehhTy+hh9+XEXNrXHNFfHhVDSizS9fMfacts5X+iRKZRo69cC6PrWzvZkwbuzPMWYu 1lfrv+9rmR+ACSz5sn6IVvFd19fhrpTwJta6wzJK3GwlhhrY/7OFfkzTK1Gi9ARqFbJzTCwZTv4S 06tjCcQKorbRZdHjLViaOh8Bb96B6U0qtlT+j72MNJ40rKQrQ7IM8rIVdfOOQZBUBKm7osztONKV 9qN2v5MuvGKjovUHlqpb91Woa4+MKa6ZwbFiX0RQ58G8Xh55RMcu5JXAovUfxI+C0HTvx5xaP8WW rBcAJv7gJe58NHRUaOoUTYAtG6oOofxKPb29Ft6hkgdHOLhIkZ61ID4RAg7ukU9MKfGGNuM1j+8j VbXDbkMzl4M0GlWV59rVXdLt0vBN+uc9gY3ncI6PrSUlo4jAyGt/qI0tz7iuQjRw7THWPQU+iZ6l swWmf6hIe/JgBopWOb7GbQS++kt2Jk57vZMHCg7ZAfWkL3i+mgDEw2pkik93Mu5ftfOMfCiM9HNJ k5beMNYqxD9QaXNtIJKhFIQNgzC9qewbEGzibfzqtTM+Vw9gGyD2dMiBm63WyHtv7O8UBr4m+KTb WdiBv2KcY8oGR2U/CnenqKrsX0acL7hCHQd8f6xdlGxTenPwy/lhWjGIT0LBpXWY3C0o8gQtjp2z 0XPVZOye6hscf7t20D8adyTT9YW9nH7igJxLfVc/FRseZ5OWz9onw3uRF9ky8vTUAZEy83Rl6ZjV zsuI5qrxJ17akL8+S7CrW/y9r2tsxed6jqoDSBlZNKjQquyfGFA9yZU+iXT12dK8cAbyzo42EeQB tiaMyZ99kTGh+7EpHSUpI9imR4ZATmBo86qqieR0KDLKJIDn0YlSEZ7wHT5AU+xxHlo/gmn2dtRc slrHWhhNYyRfr4bfAXuH9fsMMR6BxzhwIOsVU4WJUemRhM7xyoX4FVH6IvuseT4rmgiPYMMNr8JR A+JNhvb8h+1ZczogymZXaL04rmS78XWzvv15aFiIXa+gSig7jUSl4uoSN2OJL5BtjWlrR0jqdPxi wwluNTY++PvvmcwPdADivuvEx2B2HPz+/vgoUSO9N+tMtGJqhPp+wwFY9QQuRqkTq84H4GZIYDxw vbP8EvvSMMNrijqqQBu5tyPeYSPNrO34zBdr2FGuh1CwiiEdN4VqMwrR8rZ9vsJN8ioL+UkVE2KJ orApIDY2RQZYxZcf9Rpd/qCRHpxIH1oSxBM2LQRKpHvNeYmOHvI6pIZeUxHicaCpfrzkSwxUElmw Ror9TlHM/6sUlCrTFgwTXMX0CszZrDQ97bmerZv4yNFBojefiB2Zj/sfHWbtFsFqNk4ckFD0hDg4 fMaO6I90ag26hcRJWIIjDrS2AlFAvec/evZWHkbRQgZxP7hOuZjpR3pVjPqSGn7SC8BmfnxEedqB RnmMwX35KbqT25HzP0Sepf7c2hvTzSqPJIXa9fMx4T0CSn+ANs91MCEQJ+4tjqx6rZkm0H9b7fGA ti98bb5UNqdLS/aQuOwo1qhBoWI8GX9Chs5EsX1KReCo/yqQQbhVXEODzS6TPC1NqSzsrVFdB3dM lg8STGMHAPmMmmEv+MnbynPAqwbJMV8VxxMMaBC5vjRknk9YACikSIgk3BsYhze+X4ZXrCIyPi4Z 7LDamLZwoFl08r0h4rpzM43m/NBTE1a5k56lHa0wrD4jedRkiDiu9EQf33ov1ryeLMWEkYKDUHl9 dZhcrIWUilCrl5f0xuT31PKLcWBCQrw4npEYudwUvihpdYON/mWwcEj2J4xN1NFduJrLwhn3bxNy yq/nYXMa5SGo+QnCWrTKLFeALX0QzBKtuh5HhYH5oA6hufXHJXWDrNhXXx6xTsfrznCVu6G2hWT3 gnuf+TKj8AIg8TZxyEHFT01/zb41N3l7njsl3I3toaBG0xyrk84aqLIATZHqBHvRInzwX1XHlUmV 6cLLC2oWrZr8z14+waSNdIHdccaMbgp1xD7w6EKzvtHzyAE8Y6whWV65MqWT5vG2Mke1L4EvKfhL 66kbWL2+/bdKUfywvEhAb7RVpvsGU53ZH2bBa15PyjOBaVDEfceb1ohPMmkEAnRJTr1Ab6IMwTEq E2rOxsOtLVPAmRVQLfSxDsqwvxx8lcGElIwmxo/MCtSTl4IfSAw/nqONrs9RZ5f2t5Yd0q2fnHJ7 +sQ5UCnzDvxuMlGfsNzwe5WtkGR3YQUXG9YPb8Gx1BPfAjDd0vPGucwTaSdlzz7epGx5QW9MI0bd j9+IzN2yx1ivJHO5paj/o60dpOquY3DlYYTVEk7Py1t1BJSkhVZFmJ/Gn6xBSzOle2kEUtvC+8U9 UMnaWBOdHIZmzS3BRd2EQ5W/1hfnmNh7RP+JjoCZtkyRzUKYkcVa0wyVKM7INJKWSvhnsRb9+Xzg RYkIkdjSKRlfEtTtWOuHuBTGrRsKz6+L/nSRQghbRVaYzD3sivcA00Gfa2Hv9hsp/SrLBCbJoQVc nOmtWw8FI+amDnAToQTiB3OyqTZ2EI3ChfQoyJJuaswA8mZHtWWg1rruOHLsuBr5f0xJo4qcjZDX gKsMxhO5VFyNu7bSp2hBQLvnRvDgo+YmPHG3ZE/KaSUHzHCjduQBa47qv4ui6kQGL8bMMOu7QdQx B7ZKa7+MsF0LSdu6+j+XW6ZlRtCltjajajpqDDAu8zBbtw01CMraDDduZeVv75zy0P7iefEqPXvd wwxShZsQmb6u1MuRU6aHpp+rHO/hw69x+yg6tZhGpH30EU7Yp5JjcnpHWfuOhptuv0BLqGnZkMKC XN4c/ibdrIuW2vk7E5J0AcSlVxa3qwYDBl7QL3dr3y8h5ZFOUMozdh9Kdj48JT1HB0HxlAFUIS2n uOHQwyj11QsSH0iD9R/OCdHDm7PXrO/J8+sn1DZMMA97aQ37gkjyKVJVtalmxv7PKoipe8heiYtx jROZHj2OiyxHDEkt07DrrNJPtRr68NkU7vrwbIybC8IvvlH9DeMR+Xnsh+YM/qkT0w+JE+WRBimR V/fWOEqwNypCKOJhllUKAp/+iygLosqYWbKX7O03eyt6xNee4/E490/5OHSN73QSmkE44isc/bmo 2JH6A82DnxjHIwI8g8+4CezOxhhzjnmHHqIMN7K3S/3mDI5yjPKvzdc2JzbsXEGOoBOa/WJs6Qjy /InArUyfGHQOM8hdRKmAy2EuDDx2p4H32Yn4TTRZ08RTVQ2SdpJgxz0B+fweMQw4yFMheixI4/QK hSzb8+7SDdeI92dT0Lt1Z9z09Wu7UBbO1tYq4jR/1MkvXWTAMCE+dtMN/wQOsrH0dC1ll9m19b2B acR5d3P1aazSWgt34sYjrkU4SK3LBsr1g7LkBfPDguagL0sBoGzqL7Sw6fSCHNyDBEi1LY9ZosdN GJa4cEWntKfcHL7NrSRpHYaVxwS/kf+0Kq/172OpdvqbPJq+TyjkzMQJstvBlC5dvpsNYOWOTnGx h/JqUhPmGUmG3bT6lFNZow+L5MN5YrxzESTiTiqTmvdVUmQJhTDmxQkdfL/3MXgtLwF278F4C4jA CIle/J5e6/+jyogFO/BKUZA0YkqPfa6TbXF02DsybJwgRm5HOjPcVuj/LbEn0TlP9ifQB681V6ND 9YdRLWsfzBpU1wjFxFpzSWpS4WzFgvOgY2S8eIrsMlYsMwxpmtyCNLknmV8BZlVk3DQFlxBoQnMR qP0fEBkixx9MNjz0VUwsKJ8YtLgp3BEyHzJIVyERMJGlG6VndrxfHPxS2hn3sm4QwBF60c0sMNEY hYhGVFrExJRM4ktj5F84r4oymqMd5CsJRc96XQtZidQL65pMLP/nfDUeZLvrycAMZU8xBRPhRJVB 7dgVmM19DXv5j5Y+flcLjhUa0aTCMqdx0+/MXC3jDZox4lbvmimp+iyPfD//g/4w2CCxiMwpl9RP olBibOZ2Iy8zKx8h4Ay0/E1YrKAvjEzsA5JTs+WQU98pzsNbGa4kvEt1zzWMYr+ZJ8Qq6eIY3YFz c5qu6XWEghmddE8vhjrxt3pbyDg5flbQYM+59xbNLdXnLxG9lGq+6XQMvEsbllJufeEKN5T2rvJI oScnwa6LQAN8ORt7JCZcB+ktOvRsA7MGSKglgZjHK+IhUc2lp0ksrQbq5TgmWcjPhRYSaaCLnBek N7rBNiN5l0kWFPwcEbQGEL55aJMCvU2f9wwb/2CCL4DArczgrd5of78g1qhxQpbHAecsIbzVPP2v N4YtIXkE+bSMdBNMQfsGWhm0V14QyyfOTsdhVkpZQxOpWDVq7SAcClcBPr/qEwQt5N5ceYa8dlCU IOh5+xoz4yRDsUEPCFkyVzJvENB+1hw+Pe0jIkERVQDb8+2B/Uls6DIMJp2ZPKfc//1d6aKseo45 v+OFhGsT6fYXLq60MQpvc6Uw5XZCDMCjMJ5t+7apEM1PxLYFxmaGndIl6z3dgS9QtgMD4arEJ7U7 tmnr2r5Nq7vakLMttwBYyouccIDfR6FpXKAJSZ4B1PKj7+ZlwRMJ1N+0Jq8m++wat8uJszRkBVSb L5upO3WAAe7/lJkc3dl78b0lG03Q/KTqu9rUflcxLVD2xRwc8lVN7jGG8u9OOcRiEMqwKa/0Pyne pqiAdci+ZzcWhTaQJyvcm0Ki297Y/igdJFla16RmeUhp5E/x/luZlFG+3yhCMtoGMGpCChLnDY9t 3mYRuIS+AuSJFQM+Ofw3e1mai4CLpPhuNMm3ARRYBwSEuyRYilbfkklkPOnkgcL9cC/j9KCwkLhy 4m4qSzncnPV9vyUg6iwmCGDgczj+T5ygSmkmmkrmYzsSC9oEtS4aba5on0lDVY6FwTFwRpan7ueT xHPiDpfvpjwWF7S8o8XmaSFAL1VdAJ7/a5uHk01D4st7IJ8d+1MJOcJGCRsO7iBNX3dXqegdkU/i aSE6saE2Ozz6lQaNeC/l4hfQX+M84/WZdVc85ntVjhO4KHvat0Mm2R54r/eCVIEG5UmXNAi0nA/C IxwErCOUsUXfH10yBxStBjFwjwodLyys7KeRt4DA47xJC1g1uFFPYuErs2JSqBwCrb2ZdCc7/6Ij TP+L6x8Hc3qf2pYS9YrQQOfPbxbACgPwSCXukE79llwBcsmFk3MAxoP/UTpsHUWPirq73bxfa/Fb wnc/D3wQBOwZHI/rYbSyPTUXbfTbCA9IkKoBaiX/WdjUo8GOAUVQNMcS5skaKZ4qi+4p1ldnWEaP Sih8+mXBXwv/36+5BI0Sx31MusIuQfs63lN6a/0mwFhGl2cG4mhUOWCrGvMjrxp9wzntt8msY1Kx CHG4bnLTUZmmsBV4VBJKOfSqcs85KQ/V007aakGnUQgTULrjSG1zQ97pEClPtZBeqxcADGxE3NJ3 XssS7EBC3Wbwk4d6g1oUW8946Ld5nXg15B4aU/KeC5mEuH4R+j+d/y2SJK5nxUJnOr3pKQuN5rkl q3P4ZwUyozDfvFfv3jKV4Bu+pNDyMhRHyCZ5sQm5Kb1WNoVRM38wy/oCHsXRkdMWj8j8Akuxewto 3Y1UdY9+gAZftvwc8hF+Tn9JeRQIuX5+TZtkLrvaEe7TupaLXzpdYX1oywnY3IKXSR39A2lXdCkQ GvlJovUVumj1vYCiWwFJadl0ii0KQKD6J7hNotS4qDf8YnQeUVneo+kVwc2goaojYn/r/ZuPdE8c N1rDk+OZnuGjuPfM1WDN00gdWVBj44KE4staKqkcpz9+K0RLSd6x7bKF1mN9bZZCloHaDjgrffhP wernSQT/+luQdqH/+Y+NT/rT8AP95UPR1c+ywjuVfqs1cStUbxuasjBpqsQX71EaM9tNkUSW5gd1 EIYrw6piMWSmcOdHfm/P590S6NWzHJd5JsCbJ1tY9N2jIYXBKJf4BkqSESQZ1Wp1TQusO5fWSPdy Cm+altQoxxvlWwwV0zLNx/HmcuMZHgIrZ+NQXc3/M1eHiLGBabRmNo5HEsclC+kVtHjQVGeVFLDz Gs1Dj778wFCbylDeReTbK1ISvAEs3wzooTvWznKeHzEpfD02xuke71423tQ8Auw1Kg/YZ/lMQwfr 5NSB5X23slpqlWDiSVXiLP+ICUBbCvEO3TFWcfsZCEE6ivbsixgB6s8MT8DRpYtRBSIlo23U6DHa UKNObeLG/XovTShRdET5FjOvv3bpwlFTCUdr2nIEAKDD2LHPRJwoNIDEmOwJREI+UegjLOnkLf8X YA7bNIdMF+hYRYsBo7UXMMCGhhTZ7HfQX3ABJtRcWmmhoZvp+3ercNMLHU2GdVCIaiYdwHfOQ6Zy ndkHERr3YFI8SKwpNj7Nusy/F3GKkAS/TkEGfZ3rNupuVz0oTLqdH2zvZLBV59D29LBZjsHUKbXa nnwdQkcTSHIqnYSX0NJpJh6LX46XRNQpMebHs8FdQ0BY0QcOkyt3vGvY+kkUjfW8ww4L7wWmVZAj YpXNsHy/t95ll7GzdrpFkqcEyb0f/zm02M0dMusm7K+9iA5UdUqLJyQFaELeOLD3y1eMWeuzeAuR vX8PzB9F1KRfH3F2TOC6Rmml19ndxJQ49Y8RVd1jHUt5HsrQ9UkU8K+ZYnhWG+e9vB5rU7lyScjC moxkFh1zYWQOwPa6I1oRmXKZ7lx9JVQ2U63AUzhXUo19ZVvm6s80VOMlMBczlxazb7Skh5vbbAH8 vXHPwvxiNKJTt1UylvPdnkOUCPL7kfcmXifLu7dB6nZteh/MDETIGt99F0qFBrf2vBgNHtqDDbjH Bpf2xr7xFFmH/HXItJDVw8bCUyw2uJ7yRe0LAlP0eAvjEdcpzfcgOgBa/TC12lt+zNOiNQgAZjQP rQRHplLybfYdUjWC1GeQCQIAHQO/6pjbmLhSOJTuQv4bzwNmpj4ybIUGRgzLsVypHANMvvnxSgzb oq6jKQUK/UiiT09I+1ZRYUciQpAIea0tfVSaYI1U+xEOurWgoi68q7E2h6C6VY0X3PwWp54Ch0fs lHoWCDrumNwHWsUi/s743g72ou7ca7IxLbcC1yDJIyVRrKw4AXN4ggZB9GO+hgWrfJi+6Cfco4+6 yzECS9ie1kecyejotlandJv76RUrvl5FnNbkHZfaueToiCLB871FPw3vCfJfMOJ+7d4GSxQirOvv hdBv0VZKpR9fmwWu2hH/PQ90MeHAy3vOE48MVElieCoqpNEn4E8mwddq5VbHK9wvCUHRqVU3P6tX vXpLZKzBcgcH4hlj/1ok0w6csCq7a9lB09oyZodyjxt5AcpUM5uJQCXbSDiHX1Vr50PuDQeM/VQ0 QLTESPZO56Y5ytnz1oyiclZTqI01yRaGFFvkxa6g831y2pJcHyNgfTsoVfT3leG7u/np0QaAkP6H U57STkj9gSMXq+/d1yg79w59busXeNhUWruCMG1JMaZvEWh2x4l2erCV8SVb8uKEKpvL833NW7hp 2+MtCTZFMXRPPeAaC3nT4O82Gjz7RM4scySbnq8amLN23OlOu8dWeZhyNB72tUAYJFQlRJZqFVNT PTVsoX7DcgQn0OJFvHTrsmbTbcyOs54Op6BW4O/q2DB3CuT50MB15sOr3cjBU8bEGszbhkKAuao1 ngbvaK3p5flK7xM9XStmra0Q35EpvCsogR5ULUge+p3gfU+6DTwKIq2xMZYkuXiBKEsF9cf+Dtcc n5x8J2l3TcbpRfBdpkxKCghZgfAONSpCQ9OKfaGqFwSGE9y68nOfc5OHpUq7NEJMlI3UT87T+pQl mk1VZc8YFZtJHcPjNjnkUXN+0PrfR6cAUEj6ik+ZumGcJlpAkrjbrVAsGbvgK7XDf4NihudooVA0 ngfiCKsBLn5K2k7RB4AxrYPEAwUh5rPWPoIP1zh13r/75Pca94qoABRBqfcsMNQLJswxxNJcxB8Q s6Yq7nir7S2Y7Mu0aX6NjOyhqouNW/jyjAuQBj06euchx4Cl86bhN97EhFPafAuuoTpHQziDDpH2 ENSq29QVVhC8Mhii0Wg/69EmVLxmXFoQtXqQfcfwdbJF47zpinO8APwP097yJpPt9DVBK47Im4Z1 jXD5PN4kAABVRkJt1cctwruCjxmn5Tl3nuUsSXPsMloj22JZUezbr2Z3M365Kcc6zK1CLqQBjcCz 0GKCNHzes2qzkVpLPG2ZZW0t3OdjpySfhWdcFwb6zoi7EQZSaMIBT6Cbg1rdvNazATYE+Ji/o0RL 1wlvX/OWImPDLSWgnuccV1RmZWn1JEhK84kEJRRLqioyA5Pft3smbEnYDqrcDiG5s2iQTCoH6iJA eRdjaaJscdQgsRrdgUGijI9VPsrX9P+NaIaW1fV2h4u2JodYF4Ir5ja+1LlqDS56j0zfX1A2Jec2 Vwr24ZoM++82OfZHvWZz/LVq96pvo43YxtFC0dn1oPFu2lKABAA+GsHJvSJ9rBafDBtzAJBov4UC Icxec8wtThO8vj8A3pJ4deBoyN5Lymz5LPlf+F/REFe8H/9vrkkuN0XyMhx186XXBy2LgfxGHnVF QwKf136hMzftvyFYiUfr60Uqiux130Qv0XpArjXC86QBYsRaE7GyLL9lyNM5NxG7y+vxFJTIf2nw 20eEixVRbFxRLVlXOXOvEUYK2DKVf2dlhLMgtnyLoWt5tPN5GLWTF4VHX94fwMwGU+vIa4d0l1eu 9L0DKv7soa2CvSszUIhrQTE61OmwYvczv7O8p6IzId/HtKQuW0GZn2T+2qYn9lwf7yl85tCGDN6a udGAr0QeWpiTLpq0E7YI0VsfTEBpIvHJbj5RVyFJ26fLK/45j4aUn4N+RJzbvktEWqvB0Hv3VYce nv4Gd3Q9CKvfgKgFrXx3pgcg5/dhGRfYhI3utQncu068Ws7suj7eFitkmT4WPagPkEbxl2+zuJ2u wh8ddLwAc+SL7aCMhb0U06qiEjOakX9oH5C+yRXchsDTD1Bs0UGH7wtPwqEasKRsUtVj193qHHOb dugBR87QosKRshpbxBNE3EFgOh2lK9lkZTnWeUrHvTE7xs3464EL7gIUyHgou4PcZc9HrMMO9Ne8 xpi6XStUxl32S4SEUkAx8l2OgnYLLbsfE5s69WxVhHGIDX7iFYwZ8cfj9zI5t9U2CdTXimAbkI8y aEG/FZou9NeVuSfN2+00XNrNzXcsatPe0OzYwheNnBLBASEkfm3TQENllL/gkQ07FoaFQtl9k/1w Si01dv+ShSmqwz07ZS9bUBO2KxG8hh74yrEQcvT/9pq3OYY6YEuORorUmgMFNHim6phScpd0D3/e RH6yc08ubbt7E95qCqYaHcqbQdpEKHAEVzBSRbeCh/CAKA2FUpawKmSdIkYOY9dXq9uOvh3eVKpb AHx3bfiDxMwAcOtwqUuNvu8bqRqq5rfykw7dho1WNRdL7ywF2qKbwHu+JH6J73i1FIEUUFQFGX2V TNbqqPmMK6/D3tJFHdvuEoQRLoj048AdY0u/gyqIhUeWtwFgn13SJCv5OyknoeQ2++FXN+B+j/A5 iRWU8SBG/Z+pp2NF4ekUutptnM3FHltghaIhPD54cwRyztdP8sLYyl1zk/EgTYsvWIu/VJZumDOz TpIT/e5CKHNdvPG5EHC1nxDZAnGRxKBzU4J+5tKt/uE9JL1Mj7y6+jrZpUzC5DqK7Gbp6+gS9gpk GMDk6edu02WpEheHzK03sVxo7Vc0fFMWarZZ2Tddt8vd7AgR4sWbIBPBoa/rek2nnZ4zbqZIZaTo 98AMjFJ8Sb469rqHOpS5Xs9GaezybAOo7VHsppQnkQ2ZVoVhcE53Hnku1RzFfEoqtGhUiOVPU9IE CqM9uXCf4neNJ3EyXBeHgCTqYb1OZuCE8izGM47Qt4rWDCzX84HDJn3tvxTf0JII7xs9WGRjB2CK UzABDu9sBAqtxLD1OkG3uUXfawD7oKsoD2k1zBpZQD2I0NDQ/Q3rf8wZRGK0UfrqYOhHaWTU4bYV TddmnW7LCYSxkUvjTcnwqNFZ0FKYxjc86zm33/a/jqerh93xaQe9N94iZMQlrqGA7QR4vOZ4Stcy ZJZhkupVZLXFNutmBFpGIfPy+SpFl3Tnz240Fz37P2iPXlk88BVEjMWEFz51zBHn8QgO+p+5QIli mzLCbc+4ABDksFUobJUXISVI8PVIA/EfCrVMKBQtIbU9M40DaMhtItHZIYUf5IgOtyaKABmlBc2A LB0YBsCxeZC21Cvq9DVNniI1yesJz4g3iHZ1Dnk4MgxqzXJQqONZ0RZTxl+Cfo6jpnl37nL3P6ni J5BYgKKQlK9KgtveTvaN5PbbRuac+8pULz+zQv6d5vgI/kFIUhTYiAYI6PQIpo50pAZgXEeLyFvw U2fEV85IezrV4PtrzMzkyi/weBXxRVShN4H46peM57HH3Rtbot3Yd5sfqji4jZtipMrC1b+WLW0Q fuEAdwswCSsImbU2YrwhTcDvyuD9n4qdNX8v6pJThNnjKDgEOMk1mIgAHEn3llyIxsHtBBZy3mPG /9T/f1KZZzyCYk81o/oaB6j6SBMlfcYkgclfg0kgbzUvPKNM3m+pWYS+qgFZh9/5gNGTzKGE4K+V bz/AP7nU+r/gIvSh7ULmirKf18tHNBnXHjyMyEuf3i5+l7pDUJFB/JYfEdQ4cpdooJJZZSqn1xU5 CAtd87pBbjM2ONYjRhbOzI+PinvxgI58F94YgCv0uVo3uy4RGUayU5RxagETcbT6Z7nqwH5YIrJd R0VOtl698cNHnERxgPvzEnzkMwc7WvBJ8M92wBREaNwE8xjmBVgOFg56h+gZtitNIL8Mb5h2W6wI dGzNuOazGNlk2R+fnJHm78DhB2c+TeP9qxjnP4uPinzDsehzfwL2JBHFepzskR5SixMEzuZKem1f 61aBD5LdLJl/TJI7C3peKAjDGwpnWGl5htKES52THb7nbxdvjEnheLpf3p/ojwmxTk56SqoqnDiW 7bUPfAWFrPFabJamYAvQAVtcj7T5WjkOELZZwJYyibIayaCCxRkOFG+rxh7PDsGeEgqmSbCcDZbj DaOnZedBQdnP+iuRh8JsWbjaN2tXcJiMM8aq6Ex86OpLY4F0mABo7BsuLk1oCrjeI0rkgXmafC6Y 65Tz/6wb+XGOKEdhNUmOe/4QZ1bINy8MVgAKB6e3ZR9ywsXIjpgqlYdweXHrBlRlZQbY/j2u4Dvg +zDYxbrDB1Cf7FCt/KCugGBG+hmLW7c01Iam1lRr9cJMhzyiLQJo4nY+L+saYJkuXvCix2zov9FL Ecc52mw5SmNIVM2n+SW8UbryUJ8yknZZJzat0X7/GZWUAEl0YcPXNrqArhnSKfyMAcdiG0OoO7N/ ZPfhWHmbVLn0VcyqJce7OxZzqEPbt6HifphJo6axSnoYT6V+stHcgixoEj3R6h79FUViueiJtibo jHsd1+wwoc+gNiASPdHSDURXVXccLjpy5WYLUoFlicSPfGgf46qxLZKP+wnDUOf1zTFHedRS45g+ 8bLfzK8QMsLUW4HW+XgwdZM766goieJgzQuKneogqXLdVRUkS6wMYNuf1AvvrzaqaehmcFBcjlw5 UDmOBwgaE+QKnBZzIWWF/Zxh+n6T7JzDAdggZx6RtTkel9xGM0plNNFHaZ6hoV3eqaB2BXR9xTI0 v6hgT57+VZvt/Aho1cKN1GdQ8czWSZ7dXXeMqPOuLmO6XGoKzTLDP5wjSKnwWzQnKm6w8dKHUJsT M6p9kKdGEDJ1gSvWU8vVKgDOfQYMt+8XOpVGJn5wNxaUPjPcBxwVmDYJeq9pYWdSy7d4ztkglGzk kbi7kodQoOPwC6+zayKDfrMMcpuU3K3NTp2NDrwfcKEbOjLmzhl6r7nnviLUT7VMpuGKCQ8+y8+R fQikzOYjjaPHQgl704TUgM7U9cMusMhL3tvCy7R9hNJGxpS6ed2USBEipxrUU8xtqzg6l8QEPapi a0jybCg7E6hrGKj7dZZnACH91QhDIe70+3pz3jrRbGd6ozZHo1qpHM+IZ6Dzer+NL4vyh274gzzF MNfW/t9yLVvKDYZlQdhZfl4v854czCSJ8L+wi2baawQmWwYUP+dr4H+dU89rR7bljQ+PJfg5qaRe 9TfSRAIx7o2Eo6K9Lcr3ccjbzBPuisXbfMtXLghImdGlUhArQXdfXYx4udIFGzYbPZQJk/ffxDDu VVTycMVMzJp6+XkCrbjokPDGrbtdmUn6KVIL3vWPc5GGSzsYwP68oBVz/DjDMq/u1Fy1FspYRmSq g+z56+Qw6Yh551OaxtUMEAv53Q7jZl3nSXxot6JGHN23+6VQ5YzCcdC/zZbqpgtkZ1FP4XqeDTym ivixKzePJrY9Df9IMBABfI3EkBvJL213mjaIjyYijH1fUvH9K54M0K0qg6vOoTLcXD8wkowsS0WO qSayGEgPHeYHAxxzxgmRqFbyhWaU/S6J2MIhy5z6vysmb2165w+8AXm/GW1aPemlSxXu5qodhJzf VFzbkdsnlJEVPAqtKsy5kBs4doUQ+qaNIqvt1joc+e9bqlumzh9eDPCDKs71F4/ei7gtUX1hheu2 uCTrCkN1odRJBX+62d7O2MbOAZN5Try++UfPy16/dK1GadJF5JLZVAnY6+/ZRxKJcnKkX7aQDVbl QsQwG1gtVzJR9FQg7MoINrnUK1to8c3MnESFh6Qh2iLNH4vJf2X4eTkzD6xGMR4s4q+/TICCllvj UEHVu33Q8LulydSumBcZHtiayjEDi+LQNq0M8ZX+0END5q/gR96/1ufJcL6ksv1LCJt4+wxgCdvS aEnll0xmuPWrrGjNn03qZgjj8k9DewZcoGEDpG12g4N5MzGtaSDrU6lPOpN4BtefwQsZdH55d1Ba rXQ2eraEy1U0gwNBHc9Cxrq4FOJYSHVA3/Yrh4rz7YMDJsqd208t4klEttm0/OqtBoUyvOsL197v T5nf5Z+fgv03WR/3EJ3SESl6nRMaGXye5Yo6LuAP4u1guRCwstUe6DX/kH1EiTIxvJCJkgUvHrZj ijs2i1QGf/kKGvbwfG1gKUJLA3Kmv0zsH7ccIpEDe8kgIZyOPp/mK74htyAB24eWPfmIK+5ygmS5 uiWKTvYBWu09MvP5WPq+ROkEG0jNf1TjvMMugremyY7Hh25sNCXjyRzhEqRYxcuq2OwSzE3ZVGTi gTnp1xq2pyzE0ITa331Co2HCGyac/cwUL2mu9L48jFyLM6IiwE1hXQll5x9HMJSPgPFTv9ZJRcd0 dwdgPVhgDmDtfNsC1QslwkjqYE0XbQ01JR1P9rMVsBA290jyxgEArqH+iySvU1i61B4ICp8huh9y OBRjJMlL1HEO8qwv+bJDDLPiz7G8Rbwp1my60nvm8OPYT804RHWG3SGqfZsx9YALH21RuVZbKboN LFhzn50vd1toKFxK7GsZIG7F4+MurNZUvz+qoT2w9Ea230YZdellDByawo7enlh5GydvXSvuCuMm XbHhoG1A1uaf2DiQxYpUrj2asf2C4xfiZRWqm1MlvkjWVd2QRodYEryPwICYXAz6zeH9xnxFbESk xrQt7WJKeGfMuoLeVtaiOQluBmgdZjlVR14K2tI/WcRwQAiGKK2twQQbt9ylfQJCu8TzV8JTDCSr OSpDcm1o1BShH4EYNpL6s68RsfXl5bV6rtd7V7JUh2vFryualkOvTenVMRl689Z4JjTbofSYZLIE yLCjFgYXNTlbr/Ij/eobwD9UrHoh9AWe3u/mH1bgW4KoTl4v4qic0U47xQu4yNK90iDoPZe+t3ve 9TiUA8Fi9RoWrJIQF5NqrCjDrHpFxgJg0xgLK9NY0daheN+GIz9uPdUT1uwabUIOxqJLgaCzUIpa wDci7dgk+ZozPTzZktDfFFiP0A2wQzJNZHJGmlhOpa/FsSAxKCmq5eNuzNMNwWqIbzIuRO20y3Uh i9x9ZliLOYbuDzG8mElWH1KIsS4MJ3RyTg7f8LkTiee5o/m0xeSZIZOn/XgKkAlLUshs/Ksb0hUO LanJaEGy6IJBDIL/6am5ktDUziFH3yE4Sg+4dwX15P2rsvvZXH9GI9vW7YrYEo83HO7/yyC9WgfA 8QEQC9PRgW6h9wSQ9tu7l4tBEZ0qiIh82F7vQ3joIvDNTjrarmxbiLOWbv4IXg3FS/Lkhydx9w96 LRnadyFWCFXQ0U0a0SxtD+o9VYTvhG19lrNEkJKYtWQwp6X8ld0WHLp0PfS+IxrUnRyjJC8q+QDw sIYRvc6Pv/9vt9Krgx3gdV4vGEMBBPeWu5Spdrf05vlb7xpFqaYWdBfslbF2Y2q2MPC5EzNyqMVM s1QRdYx2/8iiTejP3QSUZ4zYzTneFE6gkzRyjhbXUopNvVrpLFPnF7BolmneH1tZ3c+/M3TD/H+D CvwnvCKjrCj3DTNgLcniCKi4jxPd4nn4Ii8rmMMq7axhstAwxupltxZ14rE9uU8dRCT2Y42HArzL 4eR6P1S5S1b6cYkqgqF90KZxpBHUwFkYlkfVhdfQPdNashTjZYs7SUyqlFbxLiDul5aQMYwfnRND CM52XWAc3BV/Ilb1bXexAAmAx/MsVHDxdVYa+drYsUYnlo9MCH99DNa7bug8+MOKBx61c3gzyXDz 8iy+Sz1aTF/Wv1EZNzhsxKb2GxBnat/F3hCUBSCGozjMG+cmgfNse4RfNUUQwyzPEtcG/vgJ8S1s YxR5qy4kUKmkzXFJlOqyAIMYzJGuMkjheyttqo74Ie/sV+DJdJnIMY3bvAjvskr9hBzoRiu31wy6 r+BsQ298xT6oFEPcL9r/blHOFfdbIWaqDjGnD8Hj5NTcrsbbrvgW/RUYZA6D8iXFY0u762AT0qCw iqtcVAEBfqYTYRr1N2HAfmhorhUU9TYIuD/0icKlG5mTPOBOxXWZXRSQMYmJOn8pCiVz3A4jhy3L 6R2JyT8uCor5x2SewJ5kkGouxFrnD2o3UwffMcLJgsVF1jj+kKnHcajv3UoMf1Ga6+FoccOj9XHs BRaJrSZFO0uPxoI5vhcbdkrlVPXq5M0vVgsBRbj1PluyKcXhNgDMv9sauqz3xpUYEAuBVLU5XsPD rI3XFBu+LkDSvr0rcrpR8LYqL1zGQUzMZG/sY9IgU3Hq93rypMhvN/80dLrHRUz5yAEGbX+hzHFZ Yt4xFW+tNPwh6XKiZUSsxnRdNhFnEqr2qL0zDW/1CkCY93hsH7MqRvJSfCgBnI38kJYk9DYuCSR1 kZSM3o7ac3JL0coklTbdlnObqTSX4E5vyPbTd6ovr1yhynelUxujqObNJsJXngQHT99n3uCVgwGM 2fckGrRYqgFlmG4UAs/EnBKZ8nD236XovkZzv+ZL16R6S9NTAfVyWjomK/tJ26fJHOYLfK6PFc6q eEcEODj5MSIhFg0BNlDCsznR6PgyawpKP2E+Fx/uScTv04+1/KybJR85dFDOnKnSSExc8aCfuYWJ /wAYqeKZbEUDhKLAZnIwedcnVRI1N6cT8ASdxk32rDOFst+2IPSyQ4u3yKjMjXQ5A6FQVa6XLp5y A8fgf+P7Y5DTsnS7YxGNlHVAnRORR7u43sez0Y0w0DaPXBInY4w3G7j6qJBdB2nmexOzw6FQa1tN uCXXugpUY4+hStOrWbecYD1UHC6QdA89QS6fJ8P1uDiUdRc0tVrkoC/uCp1DDi12Owb6xLP2qCGf Uz2nRwPcu60EkI7x7DIpEgXNjBzYnMe+c5Cy8EjLV6LNEgbXbu3eJwMTqYqAc6xlPBlJ/joonsxd njtrMQunV1GiekHeyWwG6C3MZXle6JlgHUtvIF6AGedDv2aSzuAKtiyII+usE61hdRipZjyLB3yB 0y8fGuMYuBMx0JZeSURFCv+zfcY0L4kNLAVbjknDHTLwPYhcjlTri9ws5dU2xWFuag9Y6wAt8TmE jUi3KIpywEBQ9MTeNykO7KzTMF2JxexTPEWCvRA5MlvqTBFYjXJ73UoLoGlFalzoP0C99Azu5N4o mbJvSNZM7dqT7NeqL1m7MxzmN3qUuw08/n8AoydvZVovRghfcoeYS+qgdbZWtot5W06tq2TNcrzl KJtdEAan7mdx0Wz6+wiYf/s6YMypxrKmjt70RBfkfKWEUQOKzJG334HcVy+nMUqLyVcn4QrQ39ra Uxa6ISWOR8yrmajFFjOOnKQIC+VlF83TYljRtEd/6UtV10mEBnPcLJsjseKNvpNS2DOfB1Zp/jpV z0ewjAGow3juxuWtFNax+uZqww0VLLyCamvb4orxB2NHzbZV7xML1JPWrClF2P34Um/UMMmMgvka 7R4K43mcPV9amD0Cs4RUN4HNbLoiI/scEVg/Cz/go/zKYuuLcwXVefjK1X8ijnMDi5+p/TJk0QyN 8KwOpvZttGONrVg78MRzalocw9TmWepLTrGwkheupdsGM47gz6ZKjum/YjkVzTUU/LHuTrMSb6dj UtbdZmJkNUIcBw+ac4MM8sft6T16Xjh6PCDFcJITNv06TrIAWWAf0Ib/Mfgj4Q1XCXxYPXmgdVlg hzg4ihd6Ofv/p2/ieSCa29kWraJg7JFrgCMwlCtZQHB1A9NHvv17yOnrth0QXwolOGCokWV1vCOP vz5YZ15RhCgpPoNLdfPCW4enWUe9ywgoSNCEEgp4oMFt/cKGPjdoXX/pGgTnxxYlgMsIYc3JQEiF XmJVqLiqaVH+//M51pqSUQvti+qadx/lygARgk27+fOg6o7Lo5Fq9AY4IF4v4xReI+byD4WXIm9W VQmP/dq61exn/dsNJu7GwF+hk0ywRVCwefb/BQWPrm7XwzM/hgT8S0Z3djhl8aRUuG9EI9+RGzay OjwKjngnXI6HFctY7Z7V52mQouw+s9t8HQ4wzl2Znvc0FPS+XAbLUwf1xrrZed+cIzV3iNpU4KBK K/7R8NEUTNLd+Ry8w7pxCWhhDatoQkH9UDISnLA+tfL4IVZh8DEKTyPhmlXPijSy4FC0XmY6Cpd6 4YBt5AHrvx8bX2eWFFG+qj4qMPDayfIyqBAgZvyAY4oqU0UFjd0+2rq2h8QGGYt3bthQ5F0nXzXA FX083tAj3R0gj1jsxooPaZoHi9HwGZcbrVOpXELY+OXqTq4EMVBb6cweEBTYGfx9sZReoF7Df5BK o+UZ5DDfJDFL2+vY4c1eOmC5+LwVTV4bDHtgpDnUSEgoRg+43tYusQ/fugILHv8tCu/Q/hzhp0Yu zk+b45CB4Y/0b2gZRVskNMrZEpEEm7yUlmsQ63phpm6XOpXFxBL52EoUteM73dpYCY9a4B0RSCo9 qvTYNPqxHCl8BghiTuFgfhtT9PrGpZ1UelHXwF1jeSRWjliTXLgsHijltUT2EwjLEL+WCaX9cumH +oGBlGEPAWCFiOuC6YjeSDyK0OdNr3lzBdNwTmZC3/pUjx+CAPXfCEzhrUGvjUDT1K5dQy4NVQMk XznuCtQVwymCY6mo33kPvGFIOLSn+A1Ny2s2trE1e0LbfHzKSw5TNgUzBusF5/P0E+nHQjI47FVt V81WmeJZQ9Bjkysu1V3w6ZpwSWb2ZSSjn3zRAdAb9HjtMIh7TQtFQjEBLHcCSO0IS/lXTTHT9whs 1BXtZNJo0K4HTYtN5iZGyTTcwLQTtHXVecjPe5GVAy+GTGUTOCylyHOf7QDUZWMMfb7SZNMDcg45 mTUC+5wivWWS4zvYKn30cM1xjpk/q56hwMs0cMOlOpgVcXRfw0zBK8wyT+QmmSv4yvulKOFPkTyv LY8xiGVUIopraklFkDDICWn/RDICMqBFLGpqHoq+ocarjIljNxHuMxZb7DiVPTw7ADmQCbDB90xI 7AuKCi5jKp4ePQQw3sZteqcfgw9hKNRAl6OAwCUJPwKlrdXAieh6lu5uRBRR1SgpNyIG1jYtgKcz Bqlm+RcCrPfcPycekyfU2v9dNupKgpHHJW+pyOf8J/ScIJpDNpamUTd/kzzrNbbVMsLTCS2ZI2d6 54StwXHg948ndlq0KyEbldUIigOhv7b8S38uy/KTeqNnQ7/nTjv/0+wB5Y32TXttVG7WVhmXiBv/ Erek35WaPhaTf0+mKpjskSucVWPzuYm9S4vzlcPeFVXJ7eTGZonLQUTnbjjzMz/GRhwq1nsNfyvq G7zwCqYaBelplT9LWNRIi7Qwwbl4ZVm8gDtUVMLx/vI25PpUhiqaUW2bh7kon3Dm8ERrVdeUPByy zSIoDZwOUThcPTtT0ucky6ThSaLUdNHPK9lqW/K+e7PEMNiJ4qUqnscziD7s/ZDB7+697bmM4ZzP XHh8acEsc2VCdhkCiOP+biA8SUu9vpM7eexaWth4Fit1jIFxRKhLn62Z7kdfTcb0FtU1GZpgiaYa DlTNP6igPN/kcRZOQ5HGHBEBfOIak1G0b6QYzNYcuHZ5I6YmlNrVuE+oNEAYtVl/Qv7UZBQwjQvq yrIB8zieisNJYBBjrgsHKOPNs+m+qUeuo3rWQVlAxzaERdqvvls1VZ2ZxiV6vE9ZfqfDUqExI/Uy z5DDZ5GSS3Bd5HyasuvGz3qWX37qi5w2gnvv5Wh/2aqXSf8jKE1RrvTfvF9eRYN6+cxYDfes+jZC KT08G5mAE5YfniHZk9f4lqe+WkinxWU6JFQkj2GrzEr2U/zBNeCLZNdt+8MACzNTBWzPYpP1De9+ Ta+dqTwufiyTethxx5/us/tvfZv0gTHM0TieQiLbTMVlVfT9MrfPf7hSKe6aSeCo8zwVe7pv/rgi ABfKi8Q0iOdTKiBYm5hRzWQMMZDJtY7TGtbqBonUt342TPpZCX2GpcP0CsHDo5xwtF1rTpxzKynh WU+C1/07r/DUUcsfnCybYvmbFbOP6mhFKcvI7/0QvH6UBEe7TNR+2MEHqaW4NUQqzySMhRblN0Rr IN79JPu/iCtiy+PrmBRBYJIvOHKSE6NZg2Jwo7g890HznCRUCi3H6FhvC/2rs6MsyTUsPoMQsDqt bGlTUXJwzuaVIcWEoXzd1wlylk5Sxk59kw9eTdND1uyAOQcivcqiAl6765XCg3wGlDdxhmVkiR1I N2q6Eu8U30aTeBN433PfRxTq7bLeF0t6ck5eCdA1xE/bJqIXxNk/jFlXwh7LeGil4rkWJ12Hus++ eDtAulkF2RGz0nBb/q5t6hRmDws+TcTVgxov42Uamc1vv/TY2wZHY/pmXJuBNnZ1SEbmuKkk8qMp IydBC91IOg9Ds1h9ixYpxqnymnWTkgWyPNOBg2utmYlUoXucnev8cwD0qVPBDTwdRNbetEc+mGbY wSyHuV6YS7LjMtMS3ujchTmi3iMm+CinhTN5NGuiCRpyD4oVseZbRM6PxcbeG342I70DxF58tnfo rZVsBGyS5qaR7vHQXWXPqOzZ5i+iM9GXwAywzICAmoInlm7EMe5OKd4GNCUByv5QfCTOks0osgYV M8FCQ7tFONfhq07auLBRUBDC9dcedpIo3kgOiCjO/64qrHx0MsOpSU9WinzH/0KpifupfABluyh+ 6Yfp3RiuLljIeaj4jwG8PJDILPEZCDAE/uHNfS7iinsnzHMtwfgohehCvFCHAV6326jcYbpw8jbV tPLSCESECVBSwhXkqgyFRCm8YxHeZbGwhttxfP6uiLzN7/uJYMBZQeVWh2GXvNDk8fDh4hUU2bRP m6kvgTDihJXOErS3Kh71ONTAQMuLmWNB+14H8pIdQudmC9WmPJooq7YZkofgMnC6l2QAgv3uo3G3 cccbND3HW7dM6JohU9xEOwvKX1IYr2Cpiyrmd2hjkXEmkNZJLhdvmf2MaJb/Nb1VEE1PZeDAjn8E R+pwBnEvdhYPqAk4/q3n72qI6jdTUYIwbUfY3mbZaBIOwoQGz91kEk+3SAquua4aAOa/bTwur4z+ 0VnojiFt8MBz1bH1HnYWB3E7A/I2ezD3N5w1VvYivRBG4qSqrzRufVSLk8GuENyzoWXVKTMxuaiT sIb5uknn7cXdc8uGzRsCh+t8Fw8nHQPshgGMxJF0bo6u2l+/QEAujEGRhd8Oo7Pa/4FLLkPPewHJ tlhCFYG1D+R7oC7l7FmYddQXXLjJkbkTBzBT5Z8EJS4DUyMA1LxiuyGc2NvNLSfHkGEPr/49xlxg JqyGi2JwoLLP/bQswL3YR4FYkAurO/1WA9cVSvJ4YQ1XbNNpScp9NCiJO2w5qc3KaHS6KRiiKkjf pHNFzRb6JNeiBk1anio0di8AK2T3Ux4RpHs3zjESziulf5KtLi/qQ1sVmQ+LT+99uzIWM+J5DVVV ZeOyzfGUr6sOV4DIWylL9W9fY4dRa99qCIwOUGIKSmAAg64DzOb2wFsbDeOjGyXPbmxQCXuQEk6X YHsfXQWzg4cHaq4FZ2joFYVZqu1mnoQR8AW3MpDk3kau9BwrfrTd2b4F+toAvQ3LNyIlfArTLeqF PxK4KiDpZLiS+cgmUubIN3fE5cPSwXslWq4NAxexTWIHS4vXgtA5bg/LSTbrzrMDYLEkbtSFOHxG IdwfjtsTRrvtrVE7WIU9yqarTgYZJpY5O/Ta9ttESALsycl1EJAUWcJK4b8Lk+av0xlAbZslVR8X xWpOuVVRok9HEkomz8hJ0clFRTeiONMPmb/rHoZq62eBV28oyqS5q684GTWqUQStaonN3Ush6QXG A/grlxpf9ozLZmPRJEdqM2sc2F65rWK2ftP8NLU93uouTKzNXycaNMvf7yNkUfx1VgCrluYRZ1lM a28Z7pYuJtFcrTJkwCHPNbMyNVRtbmbpBJqKrBlmQH8M9V+PI3XGlfkLww1wa21XST4+NFooqDrm +AN+O661cF8rAwO/SIPkGXz+JvVFcJSY4CCt5IMHKco/aEt+l9wRoqO1GKZ81XLOz30Nipynjv3v EdPrxKrgJqzGtvfl0H9CTbaUiodGZnxSFz5v50FeKFjeb5TPbUHuELIUGw/yMFG3XvBFeICKny/M MR+vMqm6kJul6ifYCyQoNhGYGhhEU3UH3S4WT0RRUvh6KbfE4FuS20OO5iZk67cQhOEnzrUdgw/g 7FfCeErVKvm4nxTn9PgW8VK3Np47J1O6b++MSdPuQsIwfIQjJTwWzmcDX32Veiwo/p3IT9BNfFO+ 0WWtyn88S1cYQ/nWXg2R/AdovBDj9ZAsFmbtCb6iWp+1PIR6GrFYmoZM1cyfvrcGk30jb4dnbV3O bYXttWMMWCCDTsQJPXsT4xkd9oTiBM7ZRF+bSt3cXAyqigapkmh1/zvwZIUiWnaKMFvP2ShBh78g 8JGF8MV/aukk2OSVSZ8/qLC6biSf2b+ZhcIsw9UDaC5l5heSIZu7UxeZHdQEn4TIuHfyMygYRgPc 8V5KWU89O3wx+ia18E1SjgehFLI6r2hVp1ABasoEnXG0Bru2/rNNSQA+zD28tI2iNFlMujR4yikD uELT0CBIEncmI/iNSHTqd3w8x7gjxysJq7ZX0buXTcXMSTkSYYWSm2RLI7iqc9RE+Gq2SqFSTuxD fRu/C+d1gqz0EGKOB45VR4EHoP85BpVlnQ0aSiZXDV1wJ09mzbUomTPO5Pe+POTeIWP7L4VquuRC 4/nKEu7IeIcGbzBS5xt4Wav7IXFGMjAe/Ne9A87rNOmRlxTuIA2OTf8u7hiP0n0K/3QunymyxsmN bHi8RvmDwyXG1XiOCzY7TTavztAajJuqMirMlKdKMO/HF8uWiq8ieyWwMnTwKHyycqcgawwJxvtY wfwKLDtvZKonArWDsnpMRbR8bShGI3tLpG3XkAnqoKOz4YwxfChN/pNoqDPijl6w9VVv+JbUNQYH S64cUB0M8QHjM36SI9Pgp9yNlLTkL2bEiLHpeN2UaijLnEjVoNhsvZIDFvVtEUwScOfPn7xifCTy rJZfNsmdOqJV4ovxG1G48eNDvg5P9FSV0qP/7kg4foEL1CpdHeDnpfvXHHDH8uyXefx+uDv8Hg3M DEx5iyrQ4jhJsNPw9iKmOhk1ZPqAB8Oqmy+fEQIpGQCyFlv4SH2LU8Trwy8+ZVwzQz4UtwVzMGHz J+J2vku+f6yiLOshI3XpTwBIWdjCFiWThJt0PogpIPxe2VL3gKtX+nX89CWZyd8sZA+Ikj+LCExe CCxpExljtDIL9X4Zy5DxAdrF1rffdrVE5CJ0p5SnOLEayghKUD4xJZBBSf700BeH+mXSLkxlmeUk y3yoWB16Hh5vuVVXIYI+hFfHoJFiabCsEisN1TmeUIb9UANgrQVmecKHZ+xruhwawjEMdmyumYrT B2p5ZecrKJ4tT0rAr2hkCOzKOtek2CesemNYSvQejTsRDDiN7snATT/KAXdGyqBNTfPSXaZ/vrdE 5NKIw0YXYpPBSFsuwrnkLKZWphZNJxLOnfAk1krxZAx/f44I9Sy2ML3wD8JURQjjaVR+DdfdtkaA C747DnjaTYtXEwP8ldxeW7KdnLkN+Kna3n9zxbxp08UPiz5r2P9+t7iBmCJAEvrsQO8xYF+BsEp1 fik5bxok3MdbHGp+8+LV9DMgXhXeWDtrtrPFzMj2GjPfb1ddSb5kzQju8lHSkCra9q2QR2mf6gYy BmZrRctZ3hC1iK/n3Fb7hW6xWoS5YUkvvq161Xcfmr8bKbTxfjks5crgOkSUaBpbQ2yyLxnJzGb+ 99ZiuaTs4NP5fHdXsy6xFXtE9QNMOrYBabzeJME+Hr2s5fGsyVyq0pEbutW6MxPRVbkZU6QWWMYp /qx0TNNTtZ4p4II7RX2dspaTGuogvv3t6QsF/i/cgR+NdK5L9eXd/azmDfsbGiB8hM8Gr+NuV3pU 16pNBHiigi280b7Grj9S1TkOtM3dhiALACoHXekLwyjJFKIVZgO6YL2IFfepJBOlyOyUTOhCsFjA toFtc7rXzpPDFHYG96idSx/IwF3huFsDfI+OvbC1SLI6fNPmnu13VmcHvgFiftH0PjrEYpfSQGb+ g3Hpsh7GxKsPKwDsBs4NpFt6+nyYzZnPE1awYgrM1HUpzzs8CzS/gJpDFxE7qM8cBCoILwNSzgUG I1lRvIAMl3aBy3NMVzXfhowV4rQHqbxTgrOH3eQr4CnI7gsUECj+gLSoR1uK7G5u+W4IFN5Bt95M bYjQQhzA39XMtpH7kpKtBAr7703OUl4bgOumX2bhSK+tZRVhiHdVls+HQBct1uAjSoR/LdGktRmB 5aRIp3t9xBDWZFwloS8vmy/LXmDTwtcITzgZ2DTlsRN+OwdJafR154ecvjGJrCTPAtkswqEmA+dN 0l4exs3G2fyGV2fx38XM+gH64SKakgy5i6TYM78CcoPI98NkYBB6MG5z+pOCofjJKqNACHLpzx6b iCrSn31Cqy6KiaMnTaJR6YowmBJa5Qv39i5qqqcNg+WegJyFECutXNw3uBqtaQvMwHW8w7hWrcxj PQNVmU2LT/GzsmCQFZ43QO4aPgV8+BIQQlNDrNLhmtMFesJdNr4bexfF3HmoVIPdD5wmfH3Yo0I5 sA52HVpAaTziF2CFIwaCohuN+9Qjp9RvJzVlTYJd9aVU8Q4GhXv5DlyZmJMgHEeQZ5/WLmfyjdw9 lrJ3zFKVJUZthDUW4s1K4NokM4zMfcko1Vfn7qmSwKiB4VlcJwoE09mbGfEya0J2/FL7JYLUOboN JoXZIQ+CGbJavZCAz0GKRIerXcwp/zL/0wglmVf1dkzJ0TvLHxqlhm75Oce3GZIOaltcgrCFaX+n gm21fLqZ1D0Cok2USLKkIDXnr4R78bO3usO4bPUtwe/pyis+fasbEPCRN3twI4sd1AR5hexMOPMR jJFQFrf60oxzu0+2ScJQICYC+3jgt678HV8zEV2zMpEE1I7Ml5P5Gt9OcNZZYIz3I5QYpxJdQE2i wUDaixDfkgNsSnU7rMrLN6H4v2T7CjTNYk494vkp/mjzDQhuVyl+FqnR1vOkjzgoZp+y6I/sSi9d iiOityjdaDwyZC/tRNceRKVP4/mdKwx0IWm6hwzbk5gt2ULEnQxKOvJjnDYihQLNCvbswG4FAiTu uoSAYOIJSIUMZIQMC84pYZTCSbQ9eOPBMm/TrOT86CXlaA5bjKKf17AoxcDxYN0w72mFipLCDdtF Opvnk3kuuwPR4O2mDEGOP+4UwztyvGUpo1icL/gE8L1D8Wb2lXVBDfE1CL2L0co6Om0f8jSE+ABB 8of1Pdlmf9s16OPo1dZjqkLx9FRYMFvUgvaWg9rCV0GS53Bw5UTZ54lG4XRwpymDJXXt+BYFfUb4 PoNdzmRFYUjXbxuxdai3H+34Lw4hkKs+tVZS43JyILSPyvZxj7Rj4WMokfkGY92sFxxF0xgr1TeP mojsFHjO/zJVwgppgIXraO6Z5OUso/4IEXZL8knvi3oFgZSRjGwd6bqiDI2YRx1b7OXnFGzR7znj Iot2dImjt+2K1Rb9SyM9PO5Eoz64jhxeZdP0RtE9PMHwX67RAS+Z3v8cWSHONgtni7zGDidM7w/u xoOFT35t8e0M83cs/vdlzR4eTVJQ+PbrWI7rp25R9KKPdOklDR3GZGiXEhqacAobvKkdFJfPXrq9 f4rRGULii+Wp5dDqACJC12T/2mSsTyw0BoKpuHiCp4yVw/O9Lyr1ott8QeXw5NR75kS5A9RB1KMU JBWRC2VuoIJpEsw32tmLf4PjdPOuddRgwNK91UtZsP9WDMSnicQCfG0cMGtx9E6efy3nS5x/EVdF PmHwlf40oNjjkOGNUr33+1FowxoIx6RxTIWaUPYT6QeMfdUNLuQzs2btaUJkjp6dFI7NbnZxm+8E PxtfLR21gGAV8rjPxwZ6JTebqdxmlTd9IXgXv2adyWKvHBXDwLgcGTBS6PTbqUITydfPupcgYfK8 IhoyzQ8E6zggjzCDyV3adex8Aq2/LLFxvahdjyuMPBVWRsf9BSaYz3MMv9xSB5J8ze9UKM6TCiQ0 mRQyNgSgR6AoGBC6e03Lz2o9pvPXg+U+om4lraXe3qyv8iO0Plg3/22RY86pVpxLpsulsCnt0LXa 9FH0H0jRrgotSsatZrP0psBJ7G/e9Ihsda9b3xIDpzaNqjCLNFcCmcj7IZMdQEXb9LpctoAszons O8i0+JeO2+3OQviE5qAjf55T9/MYOuBPFQ2kAunOGxmcmbIjWWekolllK26aPaJE10uME/wkcj4i jauoQrAkokzcO5Wl4ce8wMXStHPK2hM84lnvX+10z62Hm5YDmX2S4joBKNFShybHnbG2VNPKbsuO VxQjdHdGlmOqOVOMp/mB0XIezWyNx/sGUrsabDd7i979UPqtAT+l0NLBFMXmuNdrbaMDRvoO1B+K j7JCSe1hPGnV+SWE8Kyup/9B1bleC71trBkSFchYzsSfSWI/sEbkPKBjnupE0uvgGTc5J/N5Jc++ QCzeMn8oISkH6Y+/WKIkxYHfjdC/5cLmUpiOPAoJuq5XHTGyPV36h9L8TyKjRMpmPBqy2wmP0NHo y8k464TWxT+tUNf8CD+2NYfCsWt7p+/XCiCR9EsKR9uFq56FvCZKM3GeOGITgpzf2RbjsAw/00J3 iXrBnOkvxvJfg8U1rPDk0R0o/G3AvrCVPUp92m1BP5t/xGt8wJ+MzD6jWG2IVD9QC+ciNWyTl4h3 gGxuudAcgmSw3fpt75pkd6KgGO4Qwa/QfO+0Q+mBr6xQv/10bQWzedBfANh7VBKmq51fg12/nCNT dl3Qfajr9THkGswdSfQpuyUvXSzP06sWUWiDzyOqdQwfttraUsDUxR30LRxuh5r5hdSx0Rrn34lf DxWQiqUz35OCmkwF24AjIwJOBM+l1BGa3Cpgi/0MjxXPPMWujd5S5h8NTO3k4eI+S+s3hJukSBhk rNs08KtrZex1wjM9EXaiQbpyrDWZBnBLuKOyG0MQH2n1q5ppXbmkDt0s+HgFBSNQBlIwpKAQRmrr t3lKM+zp1dFRkvOQtaNFPqSJvBydreazh+z76pcA0Cw3QB+f2BkL0w4yV77I0VTf68DxnlSAQe9Y Ie7hv2Wp90hephYUfylML/F/qP5cLja9xXyXympbz9B/URQ8gQ6VCOIzp3VhbW0POXeWTo/K49tg /dOBNgMocC6+XqyDalNffHd10CB4mkgj8pRurLbiknnhx3Z6DtiVv/JEWwQtVyB6g287XGiRMZO0 3uAr6ObHL65S1h2LKX0KvsbzjJUqPgPCrz663QmA+thCSrcTaqINQeBVAVX11kZTRZehW0yFg504 wb/xjexJEC3eMKLO0w2JmTak4W18ij0S9hZDrlNxzMrYEqVFFjy074x9x1bXzYU3g9D3jUkHhl9m Y3ljj0kSaHo16vg9NqyBsWtp/vH96QiCX5nsnp4gSiMeA2hyCQVVUG0NhsDkVXdci1KVN81lU2L2 ZPHBmh/G2xCMlZDySZGeRrSw5CkS2xZ0dHnmaOaskgJ/dl9MBf1SjjMQ16m9lFE1p0Sp31UoWbmB 1xF7T25Ck70Oz76VoqeacGLKacEumRsPe2+tV4Wry5A8d+bOeEc9O5RB27BOarUfb0UZyj6T0Wor LdbssNCvmCt22ilV2FwD8dWxdgXve0AeXCQ52s/jcFyQc/c0M2diNbHiErDPnRPjcvViqeqV0RXD 1TFCohpaAZ4LI4K5GFHPlxm8XDCpFWdnuwd7XXH+jRHdHBceF+7n4O+moDlBj+3usFciGs52EgQ7 1ZvGEv3eTnFZ45qgYzc8n5/Fsh0W46sJu3pYyYoSgMWMsKaOhcEwi9EGwJfuCIoOAabgfSwK5QUH sMVw29+Wlr+fdcndVq/7WiGvJB15QzDquw4BnYNxkx5zQs1YU1DfiPbYqUCAUwQR0mDjtfPiDUHT Pj9QxMoff98c9GJDHJLQyF1cLX+NHZmtZ23OwIhwD+aR3bapXHIHtTcpS56tL0t/PVUBuOn9/H2V x61OQ7uZQeWsuU+TsoHmsG4cvH6tz08U0Ff8RZgzjWckkhv+48nRquTCIeBiaiHMdvVzN4xZaban qqt5VDh0O5GFKLIQeJDUnpfvkglGAwnI2zMoV3jLPFI/o4A5qL5pFxhCQcPzhElPg6rUEaqK/2sf XBuqsUTANQgomID70p5D3qKGQd8KbNvV7EdqdchxOvSgWUgvLXpl3yvbDPQ8mGOBQEvC7YYdRyEH sDkPK7E4r7VuXMxi7fXdELKitC1JEJDBOifp9CKQwzk5UxOzCDnOjw7W/JvGhPw7xvYJaS5yEXtn /kv9ru+hpQC7KaWy91rsicvOZZYKz0iCDKB2JHVd5uTzOkYU/HbCMqxa7sQxHQuiAth5yELW9pj1 fnPrx3e82OMkp0XAMLMODyQCd51CIN475u0dfJgKbGA5HQizfWmd8iqY0XhSamw9tpG5/6019gIx C+6Yyll3aiRDIXvZ9Qrpr+YRFJZAyoFv95YU7rEhUAnDnEe8kmAITohi7lTYWaH5kvLCg5HPeubx MZJZ+wQV6LMRc7lyWYviQvLlZvJ8dung7OBWY51FDf53NuAzm+plC7QCk5X1WYsYLkVbPZqeUJyo 44YZ9kHE/0sy/55t1Qk+JxS7WiYZiR9Fqwtqs+2tp789zooK2Rekjo4+im/98AVvMXX5mmTL7oFB EnZRyUofhOl6Sc309EjNrFRbBCqK1EgsGriK90ricade84VtjFWTRb5Oj9otGxcdhKSPYZMJUIKy brIHsBTfGDsD80CfjnpA8GXlfQ0KIskTM/02MVKhlP8oZZCFfP52OGf/ovijXxf22C+dC2tIsAPn W00I0IV9wY7J33QPS1DlMdelfRU9+pREpnkdvmaG7N0sXOW0xXlorpV2wWRhw5TlKWckIWe3BMdi tggfHT+cLcqKpxLxEZomMutqQw5aiULsQD4zQFuv/qp5V2MORH43tpJjopA9rgKdNYsHSUN+Xw5r zxgk3rmkqhBD2s50y5a0dELuMFHXC9PbSzb61FQRyUzpgPK5xawCh4RnWWCkVA6wX/VSzpCdknba w/YNQk1TLKx1AmkVo2pPDoP1kzFDOVuuFljC51wFQB0Thh1SQWaqjqYRzLnIWORxC/RAI9RIibmS s53jqqN36MKFi7Z/abVcxM0gN7SQcOXj4dNP6lnRQVZQucvUgLGnv6Ch9zHTHgMkEC4J6F3kyIhn 9jNkePcWKMonZpFwvBRJZx+xMct70KstoaXDTQ2xoBNj7q6mmj49kWoQBNhTdRKkYUvVR29G+s9v FGuGlCXUDuWZo4QuF67d05jWH/U0X2Rm2lV7rgS4Fbn4ZakmHYNhd4QEOhwwzP1b/oEU5XZvAgbH 2ZNCFO0vasU7NKgS5ac9HJYC+yUxeyjKSw5LK/pUj5hQLNQQz+w2Hrue/CYE+1ZcMxl4UgRmgMLm x0WWqr0HoscEMCEMMTAcUrsDSlPjV2FVim4eqZz1dx2PPlTBvD0ulUn9YwAU45p2NLYqO+UWzuPf YTm6+TXhch93xuX8xDqD2PYHPkZ9T3agKqKiei3DkKV2VF6ar2tndDWQctyrZo/iospyZNyBG4IE 6q81DINovoJvt1T/1LRbeLBlqBsrtsloKstCwolN8Y+3GO4K9oI+xjR/SyDfV+g//w8r1gUB1nIH KLd5BKtYOw4yFFM4Rad+B//vqr/4HLGzO3yT9Mb95NtdR3N/cRROvXiu89/oKxUCZ4/RvhkBki2l nEs/uGvA81HA3yzyn8OWwiAuWf3HuhIEJmJmh7SCmyxMwPy5crgo8Mtrb+NnrVaD7qf2WMjIgu+D y+XP7djh2KQU5JelrcnXbmrVijioyoD+QBTJ3v5hSWyyZbCaRbNoPC6Ng/IhYoS/k/bFy9UA+cdo UrtYAttfaW3dCXSE1pFhOU+z/K00LWY2jbVtIp54WokipJxX0YBdVdRBRWK0BtKm80BlVswLSC1F yzwWbSZCaIm+p43/omCv4K+h0svYz+gmM/p5zKUqeMkG3Ljl8GxKoAb7zwyk9Z1O1DoqStSQSZon OtRqNf4PLXSp2nZR3Tb1cW46bqaPtIaI4ykfbkUW/4I7TdZo4bJqHVNUz6R6Woke40+sJWCdghG5 oaZCivrqOTg8HeriO/7ccEYCQNsY9a+rmUEWd95D9ZhGTC7I9kitV8+h4++HWdn1jW1845807itD rlA0ujYx4AP0QDXqTQyXLoTBGEK3Hgx9x46etQywwnwWAiuktUavziFspMjHxkIQfJJgaJOIIub5 psNRf4hf7mI1cZYgZGdaLcZyXVI0xneV/UIbkO9BvcjMGQL8hit+WRfHWn4d9B9eKX5sNiJJ+JPm 6yH6xiEi56WSfxKTZ/QF9VDGCKaSDiViQQPULR7WbUYcFvZeBE+6Kgrr88FBioHjGXEP+JJWLNgh 8VXSgjdzQYCp55F/6TrFXITKC3ZnMBXC+ZaSapV2HyC2TJ0JfEtT5DMGvDylVPJ5rLwFzrj6oFaL HCA+92a9M4Kf9N996Hoq8FvuTKvCs8DipHXKoAFiWfhlqHf/rIUrkiaruwyZSiYzsTi9Cy8VP8sD Os1JQxyFp6ySQACcFIkgXMZCweVfNrRUwtp8Lcq0CKv5MF6SNMicN7vbM8l8aLcEuzsrZpaIsxbf 8xv+e4Ih/JPGAfNCkCX0Qp11bBaZB7Aa+1xkZ+2IonJqnzH3DJHgd661LpPrcmyPPQdJq8utl/Hf LfXZUegwo8nZcww6rIvmWR3Qpg6GD7qedppxp+HZIzl/YORvDvp/QriYOAiTefh28ArBbrrSEpA3 btZKHRt2y8XRUTul4peQuLdZdrW1ITbARE8o8Sxg9XAUG7GuKrjSvutQEtQ7L2DM5F+7nsnOum88 /toy20ay9gGTEuFUMMaqJuk3dquhUsYndxofdMCtepLgSccdYz0CUasYS6zL8wOw7HXjxRhzwb5k MRamJBvSxVfzQfxc31Sh24RlIdU0CxkyTc4qnyS7BCJ/aEaU+b+j9/tCoC4sPd+YUDzSHMoBtxlw IIC2pi8of+JASmpG6/VOkb7XViwRETh1xOqy8pL/JxdEK0ObGdPuHEkAojeidEJqQVqiNU93WdsY 12zMre5zGdXIApTJLMo1A/17PL55Twdb90fw6omsVU9EJezH44dyMIrhnp1stzNCgk+hJCfPWP6n rsy8jls2xlt80uJhtrOeQhGlBR39vwYCph4plFu6STXC5hR0bpsAy5olKXvqLFODyQH3jlYYys6E exBFBxUdRRvqvy3jcYCsGhGVfDtJT8L+ZcXZusVFYgvzKsZ/p8vm2ArXfuzIEyr+vBvAJ9btq9zy dnMam51G40aNZa7X5FbA1CpiRoGYu+k6AeGaDAQa7dXdoaEOgdd4GTc05OVM1JaMhwInnP7ju3Hg IZcRasiaCjhvdfIRUVy8QqfHFbg7Hwjoaahs3/IseeM8BCqs92d+hmojIhX965n3jC0ZBmJjQnxe Vjrg47M6l9btxQHqcjeJ7XdtKQypLNpW1Y+QLRTDtRFV4NQZFFTY6qWuhQLM4iNLtXGZeZMbsW+Q R+bgI8tRURKaqT6iZx4EwViYrmM5qbPW0FuZ9zGZ60nOl6WG2zrzh2o/WIRsbITMayEFTTPt0c1l axIk90tAuvfRcX3fQZrLC4mr2OblWhdbeTt12l6KYcfEnW+0UoGhHMXBiiTRiZSCWgRsbXZh2y7Z vsjMlirYvp3nKXXeygCAiilhdgePE7x6saOqlmBEZzgVFwolBZ93f4FPa3IjA77XK4CwLl46wFXH nyXo2RfRIQqW0XF8R1UvRc338r1iZNz98lIiGXb3KAnlqs8eBE9IGc6b5ZevG4g6I5smPPiNvM+6 ZrtQUWL+gkNiWYBf0OQQC8CNYFnI3OtB6fSV3US/0Iu0eHUrCigDM5x8LUv61P92/MBottf04AJ4 D7BRM/Q4KCzjZ9DUJToh867i4HCDc5v6lF+FrO2Kof1b6Tf+X8S5JU77uiS0c+CVxX40yfd4U0PC eJQfuglHkZlbZ9nvr2rRuaE54s0Xl8qt0w7InsG8rMakTwd4QbrWoNPwzSnskySHYQOXNQPp5oLS HNAfoelvUc8nLJ2RNxt8Bsz/bILXbebs+qMzLJ8uDzc7N8EoG2kPJZFbxsZ4qluSbDi/jA1y/vXn gElSTcLi8qRV/TgShAsiW84rAOgY6lYn20m9nSRvszhCgTMjhQkBrMZcWaEdQAxrHucN9TgCcdSP 8lutF3i93mm1OxvnPLzv7QV7CBIw5SDhhtsMYpdSuZcv+pps/8rpNfDtwQTdmU2v3J1O9Ti42Ge9 bj6oRFnzMMukpJv/vw3hqcGwyulST8VWCsjdpuolDL+A9UhmfjWsuuVTPizz7u7R1cgGMDmZZoE5 E0riGNMX78AVKJLGl2rIltukl18dbaiKi3L3RwkM6SPlg7IqMrGDwwYNU2BPGDP8I7AO/Lm1qfhT gJykwcZDTEp2XJ4nrbFxOjZdvPYMPNBRik6b6X0uquA9+x+OUm5pjAjNlTpiNwj7xM8cpUUYsTq8 mjmA4Rc1rzfmwNmlKEaXBFVvUbshSZuQsvLlrkw3cIwTePYW5TlmGqzJqApGL5eysXj6Spy8zWHM DNZ2Z1REotKu6adNg3l/XKSTeXCHKIIWArJu0QoZH9twbCb7v07SYpA0mTII3VhvAOQS3K7yXywx 21GgUJUv2EjqhpWmMwVP8nRWOAn4SuJ3kG+cr20IoU8TAuNWHCokwU+olPORs0SihKV29uKrzjvz NQURPXepnkJHfhXNxM0EZAniafu4yWxTUUgUrT9FL5ChwMo4ahTK2edjWbNeJ7Bj9gvXlDIMmRpt d2pPo7K6/hU357xZ0hFckjEYWmwNi/v29b/t05/yheALWCHVaw2Aj8NwdmAdgfS+B14eruvwfoIb 67GDlDCZZ2rH4Az6daUkQJZC24J85L79LYHJCkl/ctAKNz5U5f7KanmtE6ooiy2V//QnaIB0sVGV WMQKC1w5ct+Kj1UN6/kUR41uROe+7BZ13NSUuA3Bz9W18cB2uUW6iTj7N5pR5nnyl29MovgJmRmm 31qVyuPpzAMUi3AYTvy/mnxFJlTbK56gsdvpE8wjLyD0QfRZCSIMsWum1Ja5owLpCus7aKChxMfq TMZhRTKuWLb7IRd6QgJjSNG2Oi3qLqFLNHTbitNos6Pf2Pp7cqYekvyIHgsz8317fBmNFkWZxsSO XrCOOegUNCHiz97gqwmuc557rS7Bhh4vs7kKGHMP4JLJec+QYaBOPqM4XwCL13szi0OF9DpE9lrG cZAzHUo9mBNDkXh8tzqhtr5mwd0pS+pKFvyNHwauh5ebKWTM+fxfDzsYRYtQm1HfcV7K1F9sFJkh HGDQvhP9jJFUxcOZ0b+1kDefx/17UmBYcJDiBx84XZmKc7OJtLHRUdEQTD4CYONKA455H7SNJqQy kpunjYaBGXXyhaw8whde5ibovSp0j1vwLn91K9EYXYStK5LnMV1uxEoTk5Br7u8bRfwjJqv9pagn Tk4O9f0vr1r4TFBwGTNyYuY/tBT+kvWlMoAfbFATiVLJMBKUZrMauiwpXbJKgZxN9//MRXpi9iKW 0UI9i19wKucViOwCsTIhNyjTY4OaEeobbJzfKaJKE88LWK8E4F4kIo7B93Jpqv8qcVr22QvWMLQ4 fKZ3TAstPGzMHRZkXaHxa7dO8E63RPNnY06JRUgtsXYh83PDlxNyqGkmVp/xU0PhF7L88Tv9ygAb RPi13wpyIOpqC2GHkolNAD0iSkTbz0Ymppd2AglLEFd2x1P69XbFySCIo3kdO6oco5rKHBLuz7Wt bNaX2f1GLzXkz67plab8TorK1WCBGowBrkz7Uelu1OrLU/pH9+FYGkgNxZyBzbogotHY6mRDmPyx wyrNd9Ji3z23qvf9uBR8EyFTc6F/7IqAQfccXoWhuR467BQxbmPY4Khd20rNKNh2I6MR/enAGR9e swOvMshIfrX0Hp1qTiq9dCjqQ2Cz8DzJo7Dj/QE5gWS7INhsBvf+x/zaY+q8lfP6DOxHAdfVyNqv frx3rVsNmS1WAHNdISzwpyc5OLbUMobbwtpQJrz2m2V1bx9v/DT4qyYSZFgfWs6fzbuXqwRNzxmD MA4toy85/QClag8mbfT7vxXXio9txnmGt+Tmntoj4wy72uRbZt9GHDvfLsOUKN6sEKsLewDBuGQf g+PTMk2sIIjiYnHxgW0ioR5s/HeK09/E1TUpOLF462HjyDx+BL1a9MYB2NpCgGfOoZ7pUbs+kUrZ cSY4UoJbVgpuIFzleLaBPVvRNfKEgT17zDtajVZcvuK3k5ckz5RzwSKV0Ydz9Q5zsvW51UH74xxp 5ECFdqI3KK05OsCnR32ueoIJHpMgGWi6WYFi34I6bT2yRlmxRdaZ62besoFmD4PJyxMNKWx1nimm ghIH9fusAew7WLV5gOLKp+sh3eKO7PmcLAh52GOCkwxiTwXH35SX4n47u5tWDrYSfqQsV5Mh54K6 YjeIcqy3ZFLWwE70cuoSFdYMx5n//Ax0ZtMtd9mJ/qK5yjjJbEXs4s+MrwwPs6FFf5mybKz50HdC ntnBHqbkol1i0nTFPR7kgk7ybtESDd3lEfGXFqm/iRdLF4M4MMMFnRci9HjaSMTcoWBFkPGJC5AK LUfYvnDlG6YnPwqmc++HDenpcsucstmSHI93VMxu1kZoxdgYxrHZJbZqf6NnYW+PgYPt08kxIz9u lXckkkDQy3F/wZrsNRZ8/VPPGviCxcn+IcCNKo1jv5sJvxVh1P/U1zXQCpbCGm/4yZiwoNcmnvz+ ZbFU2tRbVKZv8XNSdrM9TKTR8pPAJagaAxPIHqXDkyhzRng50JpDwdakhq9YKB2T7v5u4j1lSnlF kEZDFGbEAYj0gLjkCVR514p+eA833v+Hm9mUkK4cG4Bd0XIipETZAjFPDLScxhX/zji6sLhcSPGC cw1Xkz2b549H3BE+TbfFw/vSU4oUvPuqnqgGriPhXI8GmIosZJDexgP6A1PoGOQjZwQcezy6dnPp Q4AiLrc6S3GInPehsiERnDZoSg+spdnOeN1cD94Z9tNvoloTXaW/oOcRmMROZLEFwAcDqhNg9OtK YJEso3fbVo14GpdEz/A9tSSjBBJz2wTIZxcQaTkT4Ecr5p09FOmY6YdHQCg+Dyy5UadezXmFyh/g WEOKV7OfIcHp8IA+ZSnpc11N2JalgFaSQUHBcjafGqE1ZjVNE8hx29/DeVTMHru1uVT7GrZHDXY1 J0MphmsHNtTIR5Yf823USM4hFA6OrDYMqiRvMaUxJfyGZpkiJXPhfPdoYbUmeeadZdZUU87w4QXb S24GfaItFdM45zHGFpmI4MQKr3sYg6AGJA9i2iDfjYpFQItFH9Gph3gx7C9AlNsSOS2lGZaqP6s3 FZ1wFpWPuK9RPjCTZaGFpxwAXwFXnL/fzOk3pW7xmGUEwrmmFFhwYoAKno+RlamniKO5geU+nP/c 3xgDjf2qq5oiTtd9CiyNjxg7bDnEBHhL0oJPRyG5wdNDS9Hfvi8MZDzs8jLfXvxMk7Y49bmUttdu R/tVz92oCgWVUm6BVV3Yws++DCgqzZ7l21dDnE+x+AKiH/pQweVlqZ3GXBnQ8jzHqLyiRrSCv/6o Igu99eDFKPClEq1YfIOKESZLqt6gu8jqWRqfGU4UzefxQzEVObF076nOMtsR9JoREi45nKu/+7DI UxlyhBqWK28KJRpHjY7sIv1zFQE2aTgJ2NcPnmf+yUAQwhvPYYyhTO81rfHaf8hBfFlzY0B0Pefk +VvXsOjmXhmF7Rr+TB5p7ATLSzEDdWhAdZBOvTVQUqCkaiMXN1YjNAcz+TqVK0BlTVwx0N+oXboQ 6KWQLCRMeqWNzBpDefrhgmVDE3Wt4wuQ4Z5nMBLn4+Y2sewVVZA9y8cMEc3lKM3j/2BINU+iF0sX CgfRweEauS/KEnRWyN2tlr9JxcUygWpGJj59dTCVOhhn634vSrkGc5r8H8WYEKLT2y2C0n7Fkelt gfrq4Dy2BEMJfvlUum1ryxOYF0BZQq5vs4rYyBZZ4T1O731WZoHHE1lqrZyio18DYO0uuZXFvijk Ln3DAHHMjltm2j/6eOHqd+2hNF8gGEbuee3BJevCVKvqWXEDVsP1NxXGCbA8ei3EAaabgsA0er5e N3ZDQiFaicHg/BJqliDF7sO8UmCwvQsF0QA4fDurGmlD8UoQn1KkAxDEoC0CG2MYsGWxwK3d1Ev2 q04j3s1EEjykDK8+dvxXNos7/McMEWGIAA2sLAYeGiUx+SWyGzY+Nb5+S8G0eftEpgvgA9tGrGj6 7KI1o0dQKA9wY0MA9EiNM/xnkTx0zT6JgBdTw5N85QTznLRML50rwtgvyLGms+aQ0tQZ1o+oFerH jYjagYwlynC/y7N5ctvoiDP7zI5GVqAtR+BNOcvKw/b33sKH7JiF0UYUaiwIE8SFhZBsUCU3j611 7TMyVpYrxHCJEs1Q4VDwECONba2Xh8c7r4aPWaa5fMGUo2L5T5iEl60RwAsq6TlwtLaLCQfLKqde qdlsJKSAFCWt42wwEy18XdOuEod8OfrC/ZejQNHJFxfT39AwJ57vsHxL1tvTuD9DlBVIUYfP0if0 jXF1rAnn2WxJ9kyLeBJ0vhmPem9G4PA5qve6XeK0FHR5LPlzAYc/4raWDWu4LnCppih005+vj9q4 RRKtKFkFwXYH075f9KMP6rK4/Jd09UFbxjafhnAQD/+H6EOG5TOxkw7N3iHLhJHIy5JhBSjzTftG xIwIqHdidevZn51BAG+e6WFU7GHVKpJNVftp4EEKi1eUzOernORVBGDEBCCRFmnDwlcYem6W+7s/ iagl+jNeEEtvn5GSVK51ybLFAvD/JIfY9Edpz3QJchOfMwASgVca+84TjCX9alZI6etOa59m4AAG l477gkoIFUx1IvdwhTD8I2wsQ7w0e1odX2+XBlAH7BHC9bVqQ1/GXXRbm+Y15zfTHFZNFvXD4Qhm +HX7dV6/iibyiTOWakToiw8fvf8mz+AnfUMzi+QTuYEcLoP62Pui0XItHekLgRZiIIgg2T/VK4IL R2rGuzoVmHtYmyL37wkzgCcm8pSca7WR1L2cgpcwvEiIcYYw7LMMYAfOrjvtKJ4wXQxzd8D9562a FoDcV3hmTxkECX0BVPneKPnLA6m7gk37q8uyUQrGdfM8vEbDMpG86TtJAuDBymi5UN3+RWxLz4ni 4cz7akzUrd+tMzxwqJ748vy97NwbwBWYVTooqENntU6X0UGLDHxvPxic5undx2V6TTaOrB4ns+PT 9tyIpGncvhv+Sljwb/GLb3kHBDkz+EfUvk05pWBBQZIB3MFfeWA9GE0Jnx2cjYJKlj+g4WbLEngf Qwp9PwcO7+OyBGWzZZXezWiY8vkwCjfcUbrKu1fbLyZHi4gqeoyvKtnT1TlMdiGqeHCr07V/n881 kNVS1kEyZqXkubiAY+XYIjP4+xKuaeIASmQjGKUopqR+yBJEEzQcATIk+MFLXPViGiudNJInowTQ z+S+uVrXj4mCZNC0li5eGcWZcXZK2tEV2FuXTKg3tEUat0rBhFypLbyfcZ23HBrVFOOd6XHXijX4 sH2nfBZxeuL32ThKlC86r6AuJaPAdnAKpjyocI6lZi9Zu8Wl65wZxJXAEjRfRBRmXeGeFXO+HzeR OQOdTYJ++v852bkVcNAwAso9ukRThMcb3VWD5VYGg7DCJflZ20IassOBcRJJCREWc9m0e9hWHitd x2aSrmovMuRFR0AzeIbxevM6l5lErlR4h4CNFwc5O6fE9DmbITeoN8Ci0UyLnSkR7FFcIEhkrSt0 bNRyJKjTAXOPf2SP8CXxN/j6ZipJsxYkasBYRisrgaSo8fRa5n91T08CqX6ls4v3HkJwxXvprtXt 4Cnq4b4bw3wZKBzFJ5P9EittsNVimY6YIhMd9rWOaiRmvRVGUR4mDu/use8sDZzDH+6tOO610dK8 Mxrkmi1A1yZKO7/dB6yYjtavrXkyn7oq1xvw1pY2bLmqwhE58k1Kn6qDufRQ0AGgzvsufXVLg2da qNAUhRSnkW5D1BlHqmjK5Bom0nToS9zriWZ/YOD29oxVyJ/vIIqG7mKnICxW/5SIEAu6HloniPZJ epyetVkUQTVq+LsdzbO+OymSBHcscG5D7KZjlvTCykrWebxRiUmRd6SLcQm3DkxWK53XDFb1eCK/ /vNENj3c3xMrF73RgG2Vex3yP9+rhJZ+sE0xIHxQ6CDhKf8q8jt6izbdX2fbBZOPobbE0oNfbb5a 91aj1OGpLc9k6p9urDvJizZVGJKlYJmNJbL6uqwtKfF3DMCvWB3IVvodysDqzV7tw2W3HDnZFy6O uWfdAaXegecdlPDUgQLKRlMVPXwtxo+cjjKI8SkTxKDBXeG+GNMQzcEguiWO67M0HTgvPMYTnnVM Az/7fM+Y5/ch66hf6AqkHxcMaTe4FzpEakuxSco3bqPD7Vtk6yhSXxiW30iqr9nXsiKrpKFHjWCw anmIb2xCse87MTlmUIp013iBVX4fcPztxn7+Fj+VImyGuCJc0eFk352/xCafURLPMSU8JzL0TL8Y oW76xWMhL72tSLmCpwooO+o28u8SIU2x91rHM/UcI5FVszGnVZFh5z+DjnVZASY6k2mTXMOQvoUY i8qJBLUv+uU7HpRNHXFFZGmI6HBUQlh7z04g0WRa0i15lCpXOqMLpCKv4c0yYetAehbVmt3WlMTo iE117ZqN6diVzOdYeZRHXvSlaxxl0Ikwkog9HjIqfnTX+Du5hf7KfhdXe9XWQcdN+G9FYC9PCv64 dvzuopAJP1Rw9h3eG+mLGDWm6QZF113z0yshi3Vh+ttz9OKra7v4egM9tMBh0YcQfsOqmUwDXV73 /9bnY5bz6kpx/Zw7rPhiy39RyzAk5up3UhNeVaBnBBqFw32xZKAWW3kJ13Gwz6V4Uv8/P1dcAKgD t5Jbe5T669+Nuid6SAMqmhglLfFGoPbd2BuhZX7mkb1Fv9rtF+xbMdTZQAr4GTAhZr6Ardbgc2h9 o21fOa/rQV/KbCf4pbOX2VcM0pvenaPFmy+WMJGiFSZIHN6vUrrfbjT3x+juL/+dn9d0NDN6xcTH lgNR8mXXWsSnKjRaWSb7MD2smDY36PC/rQDwD0SzPyoWFXWypMszYQ0J2s/izgrwWnF/v70+S4v4 RWgAAXtxNiUgB1vKygLiUjEhB3gVSh4K3zpDPO7+TjMtwsxLPK1o+8P8iau1iJDdOywShTL8Z0k9 XldLHazNnEfCTmSsLf5Ukr82H4dq9pMG7KW4o1FHa/prCAFtvDVQb1HfcTG9z/N5oiN+iXj3xuL/ ZJkw0p5HlyaTonX7XCKQFQ5X3Z1nsJ3yHae7693cIlPcHoPN3fNbthnz14v9axh2MkvMMYjKH0J2 ymoDh9+TMT6AzEJFiPQU9OpW6vA1q8kNFC86u+5rtlrixCJVwz1XnEBWOWi29B7U6BKGiFgQam1w 6uL9wML3bb8hY/51/KZ0knD6+ZJs4CVSlyVMSgAsmzIS9OWDb7jtmCpvgkHC88z6wypCXGPNVg+w ojwJ4lj3XJlBF59j7C2nyHBfuO6PqzGp7PvOuNu2Rh+mRe1qROPxbPdT5YemP5WasGNQhdk2cWa4 6wGqk4YVsIwzJMcfeqTA0gbEbKqvp4Z5DJEFgE5Ixc5YOaCcpn+dSXlNKZH3Ge38nyDFai+y07lk CdxE9CEM1a9W8ZH6k8CpHDVf63BwEADOTbFBoXR4Lwd5EyTbM3Olk+DDYljtIHa+vQgmDjw5cANS ZqlQpvRXFpbIIOOVmeMRRuBnO9wKQ3RVFn0QYl6+lDs0sULTkfX5hHtqY0e5zTXhj6jq5II5iQv5 Cfp9krHm7ND1MRTepuezqPAD+fq45FmjhmYInPi68orsxDPSXAmZYuWz+N9yAr5zQzGiDcpSaQGB NsfJ4SY4cRIkuBlrJqpauF/jHkdzbERb2CTcIHxW+mZyqFMjWL2zXbL69gOzE/Jjd5loL8FrP79S NurZenmLa1EzubdqeznvfVJiG3gamGeGBC7Cn5J7lYEAJtBiPNQxoD7I0qncAjYwz1dJvSXxX1Q5 o6xJXINKyro/GAi+R45ubsDlWOQDYysL0rjQ3CRsRwdgYVzegKje4DNT397OUPlBe5cbE5csxIdc vlzdwy5j6d/cJYaliKbE1arS6eKH+rJ1v1EgTV42dtTfZdevtl71nrUEVwgyEheTxR6cLqQt66El 7YrIf69xnS8jm4Nel0t7bLWYoARKDa6d0knaqwmaXHxBS/IXpxjpugQO065FGwxwjlEH7drFl1Aw 9M9B2FJDLyprkl2QAN6NBHbSnuMP5I6bVhIrD2nqfQTkSO6YntEi7ic5R+7AxCKGFYewHi6FF8G6 QiiuzPeWgP/48XcbQhZabWrZx9t9YNmBhXI/8jcU+Ks9YcXevgCSeroMEbwCI3Thq72uLcqwXL0+ SN91pY4E1IfqqcmrOyF9bf+/uSn1K9JFd7OLSzxBoAJFUckfRVifn9Uo/6sPWPUqDtpwOZ3ndWez elG62Ti70wvDEnWLH/vRYw931iEhd4bcpf6Gvl6/X0IcFPH3rmKstLgJpg81egcnhQ3RBosfhZyw JQyMBWxuxvm10ZCdz1orb/Cspz+KeRkbw5JoFKMny3jPliraMzrhX8PwsvTE3sBYGtRI3wO41hDh GFcgAqTQITJ6lyH3V47WTOP4gao1MOYVYFEM/IdWytaXNKMaOV0FBollLmoOrGpuCVgJIwwSqybY 9R/Nc0s2seK9Vgd9b9wcVhVRRYQ3nHbVdGYbKnZKXBDzYH+BPfwqiR4mZ1sQEVjE3lG12x3LM3dp 8JHe9AY20OP8AMySXTYd5cWet0ItUMaLiezId/dYbYbxDt612mBYmaZ1+Hix62sGCD2XwnpkyZXZ h8MFU9pO8q9vOZ8Dg2mOBT9OWh2hN7qbply7He2qiGJ6GL0wpc3pulTTARkRfAxs9MyjLDfnlsTM l07tkebEsKEUzFjgETZCWHhBoUAxyMms/dNT/naSQT7yDd9pJ/hbA+bmjYufqlircbmwIa2O8wvm B3/tiKBlnP1VU+PvTFOx6wOyEWqnTyq0ScehV6ouBcQ21PlIFaJj8Hc+Zi4K9yHhOMuYTWA8g4Mo cMAm5gwiHDVDzJzDD7dkPK7xkN/vwwfgoysBxkV+Ar6YgTbP9UVmzc0hFrTiJcDDJ8ZHWr4uYOaz R18mGYY40tilVOltLuV4wWEqmmLKVHjGrG1S+yUlgVhHDpERNA5NIEZiChCiCrCYTQYolg9pQ4vx ECCMfm23Qn5pcrCrJ1rs7R9bit20XBKFXBJZIQtXjizQ2ljDzXkZPIrnXWR4c+2O+sysuq5vlnu8 iK+XV75dbprxUs7rG+DfrVUc7TLRSQQlVezzuF8fgghtpjV61Cu9F6XKhr4WxVcL1ESu7DdbjTxb 8CmzQhmVW2uWGJQdvHa7lBPvJBc4ZqaoAyY/JoYdwmo5aXnaYkVKl2KfIXxRqSmy7G+r0wHGRua9 gL9q8eRATL1aGq2q3jbkD0TpurEhnm2+kmSru1v0bDBlaXwSXRdck6rfDDbkx641z8YamdpywnPj dFaKhp5ABHD+hdvUBIY1J1ktbEL6H2zIpF4FzOrY/guNBEbfLeRCjoPwqL5l0/0gTFJlT48iFzL5 Hp/QpE3bTJAMDStAzhjYWrBe5fofR08q0D4RpcxYX31F6i+6vIMOh1makd/SryGDSfP6vSt/R3im /J5nBe4ki+CyPQxYDe7XBn/hEpVIAQI6YsiFOiJpTZ6hPn/vOsh8vOUmG84WJCOsWQaYQOd/JINf pKb2xrk52ZumqzJ3BCWETJfjzQCl9UL7sC2rLMt7tV6lCVBSB1l+glWhxD0MefewVQ+9K0yDmspb +j8qT5jv7NZigM9c2Dw7/pQribUK0F7lElljv4XjPWiPd8UI6YA3e/CFn4V6Kem4ycxqPxwBc5MY QZkj9z++vc7X7B2aK9Yv1S2MSv4nCqJvOpqoffrXGQjf5p4C85xeKgIQe6ohJRz/NIfwL23IYq7H gzQUGShstIe4xGjJ4jE6k5OhH17ldtgV9ohytVGTqLdiRUaWvGRISpvmm81p40WFX3BjULfcR/zV T/GUaJlWorIguY1N0vdpMtTpIXRzTO+Y622X2k3miwVYoYXO6mzuAZtQyeJE/Hc6hejgVe7rrk2o zR4GeAXHUoszT10H7luxEwDk92WZIfC6RgOhMvRRhlQdQwX6h+F5XsGOhdMVYT6b/hR/jtACW0ks TYa0WxA4C5/o7jlWu0xTG/jH4rIJxlWcG4QLM59Prl2DkDSzfo6/ROdPLG5V1xZsNA12lovkz+wy uKSIkVyqroRj31iHoK/+rvTcrq7dFIyjKnKY3rstJ/sNJZ7ELKM5hsLHkiAv7ypaC3kCaleGCWdU A8rF5tk6rscU6cEKlMxvsNrjFrtqNBepLiKO8PvjCcx//ACoJsZ/JNnEBhICKZYq1aOFMWUcdWDP n0opHbxvzYMBexConwkuPYfViL+HRotOAz7fIRZDK29ywLM6ItXyKwsMWZjL3kC2hKALUmT7i03b m+H7UojIt8UXPOMaMop4Im9yoWvgdzew/fOnkxtesbFXrpt3zQXHJu675Cxpl/kUWg5gkZ3sQMHB URUL37vKLD9G1yRKzNsosAslEtPOf5rJi0RpnWHFqO3Mt1ap1W7INf24JPX2iYeKTSHUs3d+jAMb QBpCLGEbH79AMrxcJxio+qsutyiI2VRYZEv6HjGvN8uIPV60jFKzMRhAQZ0eBpRpOlQ4EA2Rsf1v qzO049ZkXqVo9c1eEcx6YPajq7BTQVseueB+kANWsSb+Z8Y87RS+TBCHGcdjeYzJcDMzdtc2qE/+ 5ULa3hudPcevxAlvp8zctHWZc2aWTG6XSxXpsX1yw1SUts/tB5D0Y+ZN85LPB2zbgucmM6JOyDsB wyJo4N7NJ3s6RTfxJPa9yh6U/fLS3s+MYFCjNo+zTvZvsbETHdSU0ZHd7MekWvAWxX9kE0hlKndk BmtPzIOw6UI83bnVbsoUBYpHOEraHtCS4ZNAyw+3WDgzM7/ApekEEtStGlSAhQ8g2Z/7PZXxTkeQ SWJiX3HwmtcznsQ5wt8voIxdfxf+6aMTBMCRHnpeJvE/kZue0d+7YAANeLZ/nibDYTh7U/dUaNz9 rjMn56FFF82Ya9Hm+tWjgNB7e8ePqjTnPOzaNnpUb/6Ksopcprwb6uzlyJUVccUKhDMI799PSPx9 IkYr+AorWm5Ae6zPtEPC4MdmYgmloqy3Xc8KCW+i6TZOMA/wmfWxSrKjE8zP+xu3uEdBl6WDyXEG p4/R8gzvPC3ZRF4aQiXlMcdZ71fEswmdqSvjn7yGnYYYCQH7RyKGKCBLqNBUXXXXpRBfYrxitSDz 2XpQY20BX3GAAMGUhHF4RqahIMfNpqKoEhJZFFLHpSDcRyLMKiaSU+Hi4TVOBO4ax9vCmDm4y3x7 GI30d2n9TsZUDNWDKSGP5nyhxkE1iwyFYjluoXr9CQU7jSU4gURl8r8r3itQDzwVCLyU493h7Xxk aiRfckKQh8Hfpd3AqAcKOZ3DDCJ7lBl8GMINd9DLW6eI0PEVCWC1blS0Cqc/Ni9zMP8XP0ZsBCql K+Gs6HdjwdTPHmgWcTPK9CyGtkdZRVdjAbZNvO9Ipojxqfo9oxdYNliuS6wPtX485481c62NNZIe FEaqarwZoBXmNRFUFyVpR9V+d8IBcPHt/RqrftuiUK9WfPHwlwtHycv5vVNnq2+Gsc03AkF5AH2v vY4YbV/JVTI7GaQ662I6N3Fph1HE+M4UzcVsMvK9om/couoEvBKio0g3z8QXRjMRtvxzQtrcHWaf FpdYNS9y04MJ18y7lnFFBAu3xPUpnQd/cRGgS5vO99/1dmeZPQODdxHend/eSxKXuePfG6otI3N1 B3z+OSFNbYYtr3wqO2Vnjrj0xcxoaTkKbkD5ZL8zO4omi+Dys1KyrlXns1atVGKSWrCebYOSN9mz Uc2oGG+4fBXxaSPhxqAMS8/Yp1XEZTbB47e6HiByAPuS2Y1//i8bl7jZghRLlb4YoeegRw37VtD1 X2bdfuiOI+ASRxA3TT7gjekyZ7UiI8Ln58jf3LO++0Ko9nMbLpw2aiuD66fyArUZQ5T306ZpxPlY U2xAP2vCp7uy+swcyAm71XhLnF4MNzz6h5M6hNUDsuRY7TpSlJaqF6P3uSHQPfMnyxfXnwwKRqdz G/RVzLxLxpnEz21F7oyCcFAGsrTznKmPchvvPbJvfJ7WQeRLoH9na/34N6KWFaT9QTt0THezW/If dllS3EKwAEXAtI+upbiqdBH9N09i4Y6wJysXLU0bdtgKB6/U9Aor6YDYRaYiF2QeixBd0hEc4ftE V9ffkIefmGScIz6O76x/ffq6XFAe6/OFYvMybQA43SuduXIyHWQviPPgUxjU14j7niML+E/42at4 Y9DfUq0fUzyve9NUv5gDqT73NmmZIdEA2KDhEE7la4t8JOFiOwpEsZMqgzR3S2H0yQ9QT+rkfpgg x4Eoyp3NbtomGw24YQeoPTkH6bD4tMjs1WcZO6hvHDnizYEYzL0zPy7l99XjfO6M8boMBwgi8I22 o4Ixb15E43hndLedGBHKCeA2D0272RrBwXLOLRxDrI2kXmI0GumSAhHtsaB4t/mlbPfRTguPEnFV 7kDUWKzgH3Gu72BME4T1axsbRwN2EMtHKXPqaVpSWq/THKg+wOdaOkEKBFdpNaB61wgLhWl50tTP oMi26HtJXrxd16OYhtHGbI3wxdYCpSW9HkrqgSd2I5fRzD+q+f3ihC10TISz3MJ72p1D7o5renIo IoUW8+pZg+MJJI9H7Lzs2Kt9jcjLc6yP7+QrsEyJaFCDg4vUovlRNBaUqZ3MderY9PpuvL55iJK+ JYdT6WURtGx4ZCm+M08rIgFP3tgJ+GhL4boz2yzuVCh1ASngDRbwLPgJve1vu7lRg4VQcOWR/bLW vmCXKqZc9hSX2blpuPpdda5B4WT7R9masRadT6Lyy7cx12v1T3BnCBi+u49RCIoaTAD2HbO9xnpL yKR0P7RwDP+Gk2yTaWjWQpIeFwudZpWW/CFz9poMZ28otr/cCGkU3nBFydYYItT46ZWXkI38yTD/ /2Gt1lTFqV9LmFiOIFNpy/GACSuQZRT/jYDdVQP+XVgivTJthOqiamMJS7gsXrgwmoiGPYfDnH8o 6FOdUYCM9iJ1Oaz6UndXWpbJfDi68FJjLt67uuYWnQpm96uFxDLQNpnE8709tMdPVIbbTQRAywww T0vv3QXhC+UA9Cmkz+2MCgPyw6+T/RzEeZ6MS+Or8MhjPgt6VfxmNbBrXmdoYnyVigLXsTtQilsU CjTpidcamjWb3nM9RQJuAYn6LBnt29Kd9ENkitdH9qT/FX75Sr1pbuv7Ymu+xVN/TSeRX5+xFpiZ /gEZF+SOfERwPp94CNStq++gOfvmC9T4YBN4nqoQPn7/2imYu4/FYIhZ46AVk5PUQcXvs7IMvhAi zE1Ja8IX0lXSc+bobePfpDarwyGyRF54/qSEkZBCujiBqZlMmt7rkrniV5SZt8yuhbh/dyBoPBNv YRIjO78Qbs6P+t/Pwfk+8xO0j8Btwtyj4LZ03Qcf7RhyNN0G9VkQSalkwpiZh8I0CR0VEcjAE2wU fGrzmEH8fFQVmM/D3zBZkNYH6Ga+4ofUsmXp9YR7J6Ja9FbX9XflH2ZdxLn4RZ5zF0Aj2A1FYLao hvHpKmKkJF8Q6Nmcu96ciKxxO6hv4vCPrBqwEu4hwI3+tsDxq8Ntw2xbbM0IUvGo83FBQvGaBvKv EsjvG9h0aAwFVTdhc+DudtOYdcNpGN7tUbWGrbYwog15VkMWr3WGMOLLzzbaOb4TcfX4wKF5nbjo 6uB5IRh5MlEjLFArDF9wb3EBPCrP/5p+6axcEui05ybRFn4N0mkDuDY54xOxvK0gVm616kYkNQiN tveZC5B/b2KyQMKHhyTptwDTOybQuGCRXdxqmt+8KD2gyEG+W4pNkRipjh6/cL8WwQQ1VjPtUU0Z D9hYBdzIWyzs57faz3wzw5wcZ4nIjowcBO4Zv8YhsvGE/NsZXroRMSOG4nf9sm9kPSlAYzYZm/A3 F8ADHt/IzWrh4WJEqsWNpL5+OWkv7Qirbk1QKSxio8XJe3gzRqmb81KI2tZM5hrp32vJJ0ABGOMq vMHY1V6v4lkR0huKjzzDnAHedTYcL76DEPAtMtQv7jS68b+KuYzmE7ny6fGo/3OYlHm2OM+tb5o5 HOjkm8XBX8J5uKPIpcNXaOT46DiClGVA4zf8H2Zz+IR0tZL/R1DuSYqBUOjyaT9b5MNe7c32LZJI +HKKInIC4OGLxr28D0AX9SgpgEIAhXFiQ6cGJPn8+Hrua3QA0c/VYv8c0aCQzp8yguur2fXTr8i6 BNR0ZNSIr0dGuFeJ0FLpcnvdeF0g3dWm0VzxJosC2zU2WkPzt9TOT9sQH1cYFw2av02LadFyTxLA mOY6/JGRrpV7KPsAKmbr6T1Z7KM0oWUoEHXV7oLAyFRK09XjHq+kcLYGzcUKLk04Bn5ugVY7lVdh m2cg8gnD4uHZID7b0nhldYMAF8b53rVY+TKNoYU+heVKBzlxtgAopWn9pjVqtVoO1it58/t9/p6j vdM32efcezoKVb5LN88DTA3WAhPs2A4jRZCtIpps+Nuoe9nK8m0Gz2tjaAbRuLunuOw343L9GRKb 1vO97hV+QFixnQXOt2L94vx/JL3/OMIfWU0jFxLfQsujJO9TbqUpI3D/eUx/iTAM86HnRDCxisIH ZyTRnz1lX+gXORlDqlK7OYJUsgCpmdG2oje39tu+cSe2JYsAimfgcPURR/qRIy+R2YPpzp33WUzx /aMw8lAdA9lRb66nzynhhh91kcOTYYS1Q9FETPlFTzPn+JGenHGHFQLhV5UgqWOEuacg+eczK66p mvGULfrD2inqJJnp8YO/YzeXB80J9kXkYVwsA5IzokjN9uQmDf6qCynbiyR/q8Ip1uu6dbPrzklp MBbVUi5oMGDJe7kYwh9Z6aJoOxbEZj3k3wm1I4LmLHkJpvC6S5/9scH/O0x1fYRetsPKX2twEF0y /Jd3gN4t7u/2+n0jpMpY25t0eBh3n4LWEsRsVPOXCGEWlXcted5Nz26eR6JGK1Us00Hq3CWdUUUX tk3YZSXzEWQoMXtBt+JTrBNPuKgCe/e/0nX00oMxoFv0FVG7ObEjWgwRHS6WE9p6QcnomradRGtx kqCbbnRVBqxz5Mf8cFTvpXjEdEYe3Axx53i34Za7hXi4g0C99nfejxnCqNa0Ln2uvJSJfDnKG8XN V+mNGPnkCE4GjAafVUFyfxwZJzZMg7zGJy9KMrK+T5FraUslQvtOi/DIB80m2u3zyK6Ml25WKviL 8EhruySyogyXl6gu2P83jHlfWG53MsIIUUBnaENzCZnDvzhINL5I+wanrALh3QOcLGifGTXqh4cv X1SqTG1N2mD543yxn6rv67Td/g9o8Un5RIIwRfHOVWLO4yEJYd4NyHtksphJLaLogB6TsTC+nFbI 8a1rmn2ChIB62qzuQRXAzKScBRlXasNCuIeFHCohSNQXP6d2/PNV2KaIsFcRc2Rfva5+vrflRYHm XzZQSs370usHQakj5ujl/vt6qZALQoxx82X9hK2LohtD4RAgIqZpevIC9xZTGFOKQZCM6WADMLO9 Sy/MUsVYHmSNZA75iP2m+unTeIcCeXhRQwNUnChJGwjM/X+lx0nDtFwX3ICrXe8Opc5UTLnPG4yL uFPUuveh4i0LfpSU71o8s8jJIQrRxYn6XWv9KwuFwYOf1uiVLgSrqiK8Mm6qT+9rnEyFX/eMFWIt hrRM+v9IgrSafiqGANLJOqVOP7vMtRWF6tF39qfh0xYV4/nrLSadoEV6MPt8LwNdwdyc0/IHf6zR D4UHlqrsQEyl/J0YG0tuFiR19tnXKdQ/nrCE/FGRFx+URVkWFzEEaKvTjkNKrsccMS+jz3o+5B0d m4tQyw3L3OXLAw4K3jmYbnSUH115rcjHdouHOhMLj5zRROFxXdqxI+fFnb0bkBSrUJaI6nJVropo B3ISgI9pLymWdcR4/SUFy9eR7KLsv3DpaVHkTc6l2LA9CKxtgbKYPtDFIYrVu937sYfils1RP0F7 1dzJsrERTn1zQ2B/fR+04zstK1lOmGHfZOltCjv2iifTND7x2yHFJ7Hf98DFFd1Pr+gbSeEQTm+/ mJ13UHOpxkEWVGBwen99gmv2bID2R5qfdga56dU4Yef6wx1BJsgWagM7/Dc9YW4qJD4YadmDSDp3 JAkLSqvVxG6CEITaGUOPStWJgCUP2FTlee1dO3P7RTqqIPPiH64OLuGjuO1nKjN2LY9aYGB3TGlU oPrthJl/hWGjH+cPnqQCKalFV55sM+wm1cO5tM/IahiIRjfGGYoluoWsycu3C/vJz47/RzQ+TGJs gd3ZuJR9IIPdCu96tI5RDyQJ41mkd9l9dSBoKOYavc1qG6koJ9E6SBP7jJdR+J4lgMbbe10Rr058 iaM3GzXg2cMGiQO6a8J6YEr6d0+TUMI9KzMEIiENL9ntcvd+3w+8P0vy/Xkp/l7O9ViTS22TLHMz SvLPi9myMfprOfbfbBSZq/pXnoBzWi4Ur6laM4pZ9n219SfRzTByxLzYNBOcOSEywBjBozuUZpRj gYrV/cHBFSiEciblkk1UjK3wqhi5OPnJPTFCAeDbqEKiCG+nkndduyrWx53g5Rp/hqcFlM0d3RGK FqB4nVivLl7rNfqKz9H1pKyaXhT9FZnFLsmHBe/8fZ+G4kv0251zSDhcB2mHxf2ulDZlHU+lSzOr IDYUEFNLTlHpxL8OUsn48Q5QO3ppHfKEWLuOC5KGjJ6QhwYqVaHGKJzAwl65xmomN469AQBV+8Pe ZjDFUAs9ZlPWTa0VaeLAR9n0NRCeVIGP3Mu3odAQjUQU4T5f/M/y7uKHMPA9hTIHUiVY36EPoXeo QqLtmNCrKZpMrSUaYxwY2wGMszd3HBM6Kmy29NkSTzvIy0lNmxH7EtCH4Bm2CCG5HI+AgICns2OF DAwSDm4YEm/T1fePyp1CoWzfD3J6K0Wz1KfRf27q1UNDpp3xEQwookWSRp5F29mMJT8sdH8xbdY3 I2z8YGjzdZP0u9wRrALqjzKFog6FNYdGZMYz32ZQ66AZFUrtpDUeflJzcp0DiKrNT6l5hjaMMqY2 06aYOPtiHcJ1WVrGi3wLthO1xM6O3P6T59WC7zK5LPTr7QPsaMiBs8Oz2O8BPBvZU9LSY2d2v3Hb BOofWfJmEo0sEY4K+qU5U/a/TK60KJUJohJ5+f8eZZzNErGFqdFHYZaezwwLsmDYNG7+kTjfi23E 6TXPNnrcL7Q3MU65kQZek+3EJB8KaH6snhplJwo/5MaKjP7bbGsCRLKYORxwpXGnIS4By2U0QRUM xqLYu1UvDOmLotrHFC3oHa4LmFYoOTYRD3O6H2iHKhFvByN8Lhwq5lrAvEsL6SKgUzA4IF30DMbN zaQ8jtE2hXmXZGUomypNf7J2oqwM5YCwoJnmgCCgJ4EMXxKmcoFL+KTde4617vmcr4ZHKnjy2FMk z/ZqxLLNus9nYcqs91REgmBs0NOzk2Jj874cH6manYSRBQ+3xKpsPlk650nLU3pu5G/zDgd7J9GB 1E1SMNIwfZ68SWeU8ARIV/UywTIEY7o0wQJA2Hz/gNRd0JEtj7TiOLcgZc8GJzKztdZABAE9T+n5 eszuf6T9V4ibar2y20NtN45pJH/RwznzvbgoI+pcbqTWavEfez+GT0e+p1+BiDYfKMmzPRafN0fY S4DKxzpjhSt4pCsgOw8k1WvUFuhN1DmkBATSz6WONUuRx3o3ZrTQbhyy1LErUrmS4bRvRwZQza8N kg6JCnbzbDaSMq+0L+ZQbPEaSr3GNO1KAgk4G4zYfwQXMBqs9AzUDUeM7HrSvXxngMMKQT8+jmWH iNSt1kZSp38E9youRWnLQTiinWt1pvvDX0RH67iMUsoabghzr9bN/wYpAXEtYUXsbY7IT0QghYWJ 0gIbHL6qg3XAd9TjC2sRJuFCrIilEEgVnIGITvTOc+Ffz+3MJfygml6MyO50LnNObFfQIiSHJMap nmUA+Bj+kvMgqrAGKENmNsjMljB6Brlnf5vxONS8qn/8OeVD4bpn0UkyUA1Q5VthjN0rp4znjaX9 v1BcYydhf0+i67mqvvHyu/1IV2bT7LteUVgGJc7qWYtvldjfIcHHOJw40OLonzsx2amdUoBswH+G LPCpdKa74zgAqBGrzf+/jGAbNWui+41mfJLThQZ7csVb4T1ZnSI4wuuRKKrBwIfmnNfdQGMp1wIh 8QvYJOCkQ/ext47r1+yhpvXWC8Hm5ueVafBnjXu7DYEb/z79BnsKCVyH3X0b4G0P3W92+wEgyVTR HiejHjBA0J2lHMjiiKaUvpnbink/+U+0ZfZ1O1oc2Lb9QaENfSmR8tCUH5nDTZPbI2pD9vx9gQu5 0OaD1BuvHymyu+Qa3JqoKtZLydl01+BFzBb6V4Ab20Qj+Xv5XCSJuJF77+VahABZ3ZkaNUMXVaCL i19poOdST8ngR2MHuYJ0EStOW+MgLIKh9vWj+bgD/xxDrxookpKFKvTFW6maf3zsEicGkzb7wLjQ CxzqVYFzBacIAR7zalpy4fEK3/6/j3uRNHfztbwRhGvcs0y6xlbL6+iJ9QeuZXBZBJ/YtolWM7rf vvuFSvf17jT6RXyFDgDiPjkAv4oQURpOyRq/M3mn6a91V2RKO8cM4gr1DVLspNqs/5UV90jw+9Ah JknqbnF7NifvDl5/q8tILOrePux2OEd0zp9wMH9XO7aOKVSV/plwZW9xlub8rC/pLJpSISPZ8xL9 yFqtD3mrXzypKaQdYEJQRFgiopDrkCkp2qLxPa6YGdObOIs+Zp+W03q8/FdI4F8FPnm+F9r9WtkW 9PL5sbmXgZwOo9zlEYmLceq8ENoWLFHRE9RHbNrOtW0F9I8VQ/fT1nPNIG3eYTya/T3H62kvL1vm PPH9rItxrtH4rkHx7tzi6RA+fSLUTVR+8tgn7/A4edK6lXQ4zTjGLvPiDwDo1I2V44bqbcvISAWa oMiguQ51yw0KIUQcsIBB2vF3ASMRS/+DTlR9DzJTdQZwmqSy0FTuCS09KhrUcxc5NlpX12PhgOdN ELQUibI/Qy/Ljvcn2at8vSainbL6wBu7ihPWHwGzbEXqwg+zDQadodh7o32YHhKfpKVEPp8+ynVP f2AHxjzqD3zO3u7rhjvOXk+O8O29KlBdTV7F0ZNRxb3D7PfFhs5y2y6rYqqjBfsEi5habyVG5VJE mdLd9Bsh8l1iYPqZ6powhdGwgkF+eYk0NscKG3pJ91zVNDgV3lmgsLqsz3MWHSqg3k5vFQHzjc+x 7PzreRrsCdNCWEs1Dml1OSBteHbI1M4EZ2TPBk1FHQzidDTLDaUXQJSZGOu+7+a6bNKhmJc4363j fCTHwSQFIfSXnwU6tv/vsqLzX3cI9hRsKYL6lpXTApyRf9bht9ZORdrlXu9MXmes4LV2q5/BkW4K Hu+X2SCaQutbYXqAQmEeggKM6oLeHlaZY/N/rnQ73WBwZN5WupbFb6MADPHWe+Ly7/5pqQWTnFnc 0sJD0WzWLa96gHvGQbPgIruoa03tLv0Fk6NatsbYOnenq/qNMoWiiGHb0a4B+3fGEAHOUKQM2Iqk 82Lr4qrR56Iws+mqAv3+fcRBEQRH1ZX6dW24i1f+HFOf3uiNJ6glLvbWfaSffldyBsc/k/VZacp2 FevdVTfNs4hAynpV2houNtns+4X7sL5M232i0vkd6AKYl9yvRq9n9l1ZmfWVhH92LYBE5fCeKAji Si+KDljn5X5PwyA9Ffm5hJ8KRxjAmgOxxvseMxQGjNyxpALm5Wts/z6zd0UL1qEWTMlmANicI8yb 4mV9mVbKjr2TeCzW/11ROAuLGQz3n9UZdc7wz9CoHdgOgQVe4EPHmZzw/KB4LdLbBcJoBxhrZ/ox JwQCnxD27gFMxQOJriWOQfoQYlIeoZIz1s2+R6ZC5vWlBLJeHGx/dQJy46eU05oEc9PZYFt1LMC1 bwivUmyBi3/G07QIHup9fvguIfBW+ucej/q3P3fB+Mj9Xg19ilhxatAAnPuNqUrYBNWbhrOWbhig vfb7de3x/GBfbk+cNF/P31q0isyPRJC8GJEN0NEnDWWR69Z3hwpjkAwoRwBjYdnt/sxrSf9jh6E7 XEw0tmeOPHu0LoI54kNn0UkVmDoMpnOviDIylq4tMno227ybD/N03ZERHsfx+bAfgDmDF/muusHL e7e4PMwsINsBca8VsLbEzpuYPJZsQlIwjxI0lzl6Km75cchhdtpiiK4EK9szhU/Ki9c/uU2VnhEk xrO3BmzztYmIEQb9gmG50d/zTXV1vRwSrZ9z0A+aI2wfRxbz+fHaJmIG+xOYEd6Zzb+O8RHYTkFk Js+BT9TW8ZEUzb8rYXKEE2Zl7Mv9ldk6QGNdh8rSIDdyY5MyE5xXRsdA07atihml98lpIq+aMNkK O/xHPfDY8zEjXJZ1gkI9sTHkEG4EYmdBMK615IuALJsMvVVecPpwyfj4WESY21+TilHekpDaUR66 pxa/AZaGn752EHceVIrEef4rrAZ8BiCrq1IN64gevZtjJOKGo59IBNHmzJYbf/pdJiy8C7TGHgy/ +qpGH5gIQB+eVmJLSE3PSZ3EsvHtv5+PY3D1Iige1EqErfk/2+XdfZa3s0VW0arJKahLVZ+3Yh3Z s+ocWa10X66NjGuJBzxtkcSsLrJQoqO+KSLoVOxTht1h8uzyD2KPp4ejLUqczzRmPbUTPtxpDLQO jclHdWdq5lOjtwRMkr/HOwL+qL/HaRWc+8Z25n8w7C0BZ0JHB0DaqZh1uKQhzN6yWS8+tCryngCl LulWET7umJ7nUP//jBRh6XNLdumR37bhlLd+Ot41gImY+MWFFxI6CjOsD6kep4vLOFDYZgcLstYh n2QurSN8LZr2W6SfPkxdymEKYTuyL4QdqDv+S+Xi/TgHM+I9KyJhaCuMcE0KQ1j4hUlOJyR6+xr8 7zsQYcKdjxj/zmIPhx8hX4LcXcPohSixpHpUsC65fOobozfHHpD9gKVMSNhlQZyi436LD7QWYGOW 6X/GKqG//YgSuvrN6OXLnUNkqZYFQiwgwT8qK3KVQm7n8eMkpN1b32tVkudV+0qUeQHI3OtmxeHg kNkWmljb6PhWP1b43f5qCX4KcR2ptpNtjdm16rXq2lYz+iSmocemqzv9F+rVyq4k+tdoguKRxKiH i1tFAfofG0lEfUpNQaQkido29tJS5jhTN7k7xbkwJfEJ5kAmPczplmC/H2WwViCbhamEkosXYOP5 J/4iLJ3g5T5q+vugt8P6I/k7U1k/MegRGaHXWJveXM1ZuEaFwanK8iwMhGbTV0NKNc1A+z7kbwbo lhWzYaLTmShgAXvxj7jq+S1ixSuAhdMjB1fo9ALCYgrAppY2z2T/oW314Nm0M62BM+wmSXjbF9jU FF5pijjl6QbBfYkjFXAbxUQHTbdmA6VG6auAyKouHR6mGeQiCqwl6PH5OAlCqFziFh6+56ISELJf JGyuSGC+6nbZHCFVjB1u6X9SZRE3JZrw99+cXd9zKT9czgsaq4drwpxZ+ScKmBqX1UkhDMvb06OF VsNH4CtMfvug1lofqedN7CIb5JqX851gyz+5YH6g6P9GSWJbb/Od0Zs+bkXEWr6f0TfeVhcbW0ug 606bzSDTV+UDl7d3Y/mHv3DgVvirBR9Ls5Fjn4uPxQmA3iUCJaTeZYeMoSnDgYmr/w57vjuOJhz/ Bn52KJqGOZQCiJHV8Bs5/wwQgvSWgRTDOGYKDHxy8wU8tOhbzcsvihjNbr/iB/J0pLcSrmGl8aJT HWqYx90bpde6D0xjKsolJwLxVAlqKhb9wFlwBKQImhVLw92e2xdisFdYHT5NYylgpoQ/gIR4WbkH T/h+nOUoN9odtafnXWKckOLINTctGRNNA7vTf2NKIDNrigtTszMo1B28C2Lx7Z3QGzCaaOTH0jOI B5iAsoPhm1nvxm0LJHOuZhkdWco3ELqCPSqHcOfB39NKcDPbCgkZzOzQ5j1zaMMAVrdZ9LMqCUhq qrDagRAZrQzY+U22VMyTVHDqbPEpvd8R8urkfhwt0vlWoKdLzzW70mbPfOISLfkMjGOP8IBjCZmk ritxru4WtHkN0yQRBXfp2aU+GcDDidEG00IwXic/PbDl1ZyyJmRcGHsScTll/zaknCGqspRux7Zk 9ynCSPcM/AKcYHLAZ8PrqsqVn/aVnPwgIzjMtfQ2Oyq14NZMGIoZNxUiW3sa00/uz9kKBr+q0Qh5 XSAm3r+JJ+6MrwssQVy7SzY9gHzc7Lsb3/dVxS7f2+d/2NvJl5KEUzxdIOppJOADmiPq01mmHOnv yv0A/8VKE68jHj/SR+QW8zMJcpTfiUmeTFSoi5PiIWMakhvsO/LjDras44sBP2a7REOP09jxEEaM MNej/ozvCIczeyW3TdxDiR7+DlNWcgCtpNgj+AMrElGn/3FqOyL5F2BxYfYPKTM+tSY0QkKqwldB p+7Ioc66rJvxWLHN2iRyEAuSqlR1AXcgVjBsOTgrvtBSoLGeFhR32n6N2xE2yh9UpuW3xXXwBMOu M3D7GMQ1iC9M8/lKcfhdNIMhwnhM9tOKuA4ZvxdB6nxDrNeDVTq7vqnqWfEVBeO7po6mlrTYB3kj bWlOajy0L9TsA/kViFyTHXMN/syxUkgzV+C77E48v+DVPEn9KrTPNDEnS6qYV/hPrVtRHw35/gzI 4CllEuG2EOU1GaCwLwPuJbPv3+oCqIJ4M0saOfbuheN2U4IyvpcsA1QJDd3Y9vqPmWbwf+4Ra7C3 OvtLinUCASLkj4zHrlN79So2/84KP//VHoygNmpb0teCWO0gig218VnKeuvKTx3rgDLxdZ8V6r4a Qfie+azsB48P31/dbkrsyqcHaCcCf5opnHWw/2fMKm9SysqNMmTCl6J+bCe1yewzdMNgwSh7zCJt 31XJT47CLMsJiGoQsTvviNFrAFcg3lo69LJ/1+ral0sqlYirAFCB86II0A4S3Lo3v9iXSOPd5A4Y FY44AyK72k3/b3BhDAyf2It+jUJApVZ+MJFAOXe1xNY1zKm6bQvhwaJXoOKyJzjkslcf8eqHVV1Y 9d98XjmAN+pas0D78eCiJvE4sl26VVA7mA4qt4sC4HcRqdLnmuOAanPJ7ObHueHTiah4lM9Jhcwy pSIsf4WfpOqf8+oRHX1v+fcSlztmlK8glSqYAx5YWG8DCnLNKSRxXbUm44/TW/ABh6ujXLA7z24M KM+bSTLhKa7mpq8sK86VcbFTpU9Y/l2ZhTACuY7iegSD5ugZoO2lODtWgSNB/RqrAEbMksbAcYWd SJ4ifbQOdv2ZoFnvvfMIXNEllT49tYLGD6nLH6O/AHFQ5DzjSKUzi32VIZoZvdYamZq1ro0w0OGL ZnO+ozOaiYX6j1Ip0Rhg0umVIj4qnbnv3XasYjzq8LQTLm/IXN2sBlxmLtP2T34H7aK06l3EqSM1 QCc0el9tr8n0wwSWVZzsxkxOy50dQ0iO5SxFfb1lG2IeScwGc9pWEppky5Nbrb46EGZgyzJGWmAC pBCEFcgD4Zmuy0oMW5HGrbfPbneimOPVrOS1+xh3BItlbyEDt1x4q4sHmCUXqSfnxNnp9ggIrjJj kD1pcUyIUJ3puzzBa/5rwb/U/Um+YDnVFX+57aXU1HMLWCOTm0aDJw6sZGvClq/2lBJfBkTAOsXO 4smpoAaTSTB1jiwPwV3pKSGn/hBu/y5tpZEZIYu+IQTxCoD2XdSGZ5opAGQf/PIQTJmuXJXrAyqG 21C6FhazJb8Mef928CM8pYLq07fg6O8yyKgA6WKmWeOVhyh/Xv4Ds87Wct4gPcnoYNq5S23HEcyB Rq9qk5y74jtPMhIzUmcpnwvsJ7FymsYW8wipnz81Ynyemj/Cl1b/T1gGKL1guYsZlsMLYhhJvflP S4vA+4T9mpwVCH+n7tbOiVsTywghGq/K1zk3waiSl45otemtVaiD0mUrg2VCSoOBXyQd+HtOAYxU R2yRyaJBaNXjwps6n2wGgof3+w+vmbRy1A6+SXAITLd0deUr1g/aZJOzTLkpOsmfThHtHKfbV7Bo 0ZlrlwHG4ulvy2V7sZU6oFKbMVE0fq5vZocWHY8xBZ7F4kSGC6FM2MI+LpQXc8dazWEXuGirRC1v gTpZmLDNVxH71a8UGh928rYPR6dWegANhyeHAQJOLUiZzt+wsnfPle0UQujPlnDdyCTim8UWZzo0 eiTPeUay7Cf2NZQKrMZxx0Ta/aEXm1k9PLcfWQ97edSDF9LZGFjC93ZLD47EU3I6XTaZrBVf+FRI J4YCx3vyAQJ4PT+Gb9T7J8JM4CTDYH/JBojnQTjqajaC0xYHadSMl5uBZHXtWMjRjklrR5FfIeQ4 yeTaXc/rXxikWSu4AndEi8C9IwdHB4Mb28kBjUmibm+dnAwkwtR7+1KonyMucxy7FHx6VSGnOr/q 3HRj4yCcqeP37F7Jrc0zL4mcmm6TqZWAQ0qIfcwRM9lG/TFDvSXRa0KqD/ru1fI93YeRYAK3M18t zWnsKqfjO8WJMo1CCrPrcotT32+u8RS3U2UBSW1TDuwN30+WI9wN+Jy7CnqbOEPz4m8PgjDaizHj vTvGwCTiw1Nd+qaYbfl7F69YwmmryVsdWVbBD/P3RYdJkxGYZQpuSG6o692DzrdpgKaircHJVf80 w7wG4k/pMqiZBx2ygTlKLJ5CAtsA7f4JuBFeL2xu7pOdBpYzpmpsEoWwcK0ad8PwV3idLpT8dXI+ N9W209rnzJL5wmcSsQJ7okCPUSDI+0kAz3JpecHyJialF7noFL4aVcuT77ChtaIeaJ9rSKot3fFj 0wmL0bnLK9AwRZQhydoVefvpFreQcmHZJVoWzb+KOh8uSPCfpVD9eB1Bn0Nm+mzEuICHxFnegv1L jH/XoXPjJT/69MtN0szvm4J7L3JdOy/gik7Qspa1qpeF3flqvynzz4JQ34DhzvbeEB2PFe1mjczr TnsgkEhOfIqiEr0o7SKdpsk5NIN8q86S8G0BMHKpKDTPuvkbY3ISHX8LoWilU8fwaGBREmZ4/+eB cLNCCD+ePshdgjCWBo6lCPxEOJ8vlS1v7d7ImiA6GnAVKYuq0tKOdyXRB0qjPGXl5dJEI8TnaDFb tRJC3mLGmbYQXeWZqPJ+LHUWnxxUonBMVPJ3J65ZmMyPoOIC3Sbuit1ka/FfJjLUzMF0X865wWQq ZJ9Enfb/pxiszlnhYWxziuA6tuJtnqBvjUpxo4LLP/s/7dhH3YrYTRqx0E2sH6S9Tlx84FGeyTCL FRa4DcXjedUnDhwlwlgsYGw/g3ECDRA1vK5LU5j48NHeMTCt5CSs1y3U2bF8vlHJhLjVlfv3Ieee aciodqBlgceanrLwar/KhD3URbkctmbQyPa+LcazvdSoqZPI5tCGcRyzkjsojpzJgmB4BG0PkmNu MfW6gI8rHkPaz/rQzkaJVJdkSbNEQSdc8QuzeugkhJNbaulBvP5KNdRptBb8Zk5UzHqTtto1pB0p Pd43bDy51l6cmHfT5BpglvHMX55zqnBYeoA8sJMnWwwkadnI0aGORiPDI5+yxgrIWumO4iJESMgy U6d8sh80AsC73/HhFbKwa3rsGavHtCyGiVA9R7mb/8k8PzU2GpTzmD0cpJxMrA65h2JPjFqtT/tb OYGGOUA8E8v5vucm+d5xyM1/BVIcpjrjerffEvjcCpBngeyud/QNN8O7PIpiWDzML2KshqAw6/7B rrQqZq8L3NvmPpk8F3/B4ktSA1wraXa3VYfXg3/dY5/C5r0s3dRrZKiDQ5KxtXQRazR6ZQnwntQH qF09LdYP/EDRsvz8aVLW7Ngcj5vshWcOoIX+b3gvbVzOEG3p1j2gykDNLF2sYBrF16fELMTW+4nN kK7WKMvUkBk4inVXCt+m3Te4VA64z4TwiINcRdwurloD6aVPQ/7KxECz3y708QXPCBhn1W4j6KMa kt86dVr9cD7mPmo4WdC8prwnKVzW3rSvAhLJ9qAHE/7P2xQmY0ht6gM/VMcuQxt0/jo1gxl6uzU/ F1VCn59M2P4qttFD9yyrYGctLbIVCMYLJqgnSqWIwz3tXM8KINaDJVN3Vp7t5VdVc6Yf93zuwdX1 XH7YBKQMKwJ7jzhlEK/+/P5xP3cC0H3UtvSnGxBWSGobHhZ2tcd6Nqn1DUNCnWkf47U18KYHszOa ESnJFr1Gu43jF7YBNN2PplochpxR20TNKfYMCJckPacQXzhSvYAVtutnofDPvCc87mGas4eK02to wsaGz9i5BLpBzoTFzYr7GSyYvu9a1WEzq8zNRKC44W5/2OH5QV9Ng55mBK5Bd9YER+cV25wwAGb2 jxSVsmpFMY1c7i2W+/fFpjxVTPPRFMTkV+hTmEw9B8YLzm7uVibSVMKILYJlOLpeeqlhOx95uS1j tulglmlJtdHxeYveivYksKgUVDE0B1xO7affu9tT9Jl+CiuaR+kOJ48Pyd65s3LIgsWTJ9FlzXMx R7VjUjhSBb9smcFnsFA0ndVG+av9ZtIORAkbB1Eb4i25PFROFFETi3mKKPL6r04UwvbbmQU/6XBF 5VaVcPOyR0Jj0arlF4HC5Wbkr4+8eAheBxx9+cn215sbarZTHwqRdMbBII+0P8UeDcEPwkFoKqUU eYI/U6e3FkDL7LHc8KHYrYCX+IugzrlaBJHDXaE0F8nJiqxtmsAiomCT0jsZKkSO/etUqZSSuiAS +jVR1JDOqsSyq32ynjcNN6GXr6EGxyUE/8v/X0T7uKy9xomI7CScFT6czlJSHj3PNxOSONO7TOjx 2DGZiPVL2Lh6tf2a48Pnw87F6Hzjzmhs9zPJ7sYjz5gdDQmcOQx8TRtMu+zyL3PCYmU2/QxsZtvM qz+eYwvAy2cmgjyaSXpkRilptQ5NpWhbyveE5MZtho/DH25vxHDFQLG0UEdLaxtQuAmVS2Clr4+f QG2dj4HV2DtKbLVS9GsavG5XaLcEJVa1KKcxMSrRM0xRBVjtNVNubZKiq6/zN7BWPjQ5DOS9Ew6N Kaq0lr+e2zDt9tPdoejhcxVn+3Z/NM6vpi6kwHuMsdK3KR/t8lw/h7yzjMtFTu+JTp0KskHJySVN vXvQcRFLQ/vfwWcHDj7lMOm0sU08L9G0aGl4Gsqb67KbUzk3IkRlHGd4D+ovEnAji+7ZmY9zH9dv rPfZyG8UB0tdn0AgKP1r/3mKesMOQFdy0DVcIZqiJuIx6Apwu3oso9yTzQShPK/D0TSnajHzQDSe XWU/YIobSDw0U2E9gpQZqPVTy4Vt+8RA/ByQbkJ4EQSX1Q6sh67EEo0sRzBjmVVAVdEx36x8uT0j H8bIoAzg0KC6z6hNqpTgY2DLsK6q0ML+VZ2Lsaf8vLI6EDK64uypDPmzwe9CoFi6R8P/1WXJG6v2 OiVSTASACh4pf5nQ6SXllNr9yd0L15rHQp9S/jDQlIVgzcRKGkMkY5nM3JCzYcp65HKLP+fYJ6on GbaYHLVnhZHOTPSAIL6Hx4VzK9/RwWOb/kQak3kGpeaK0yFT8uAZ094gQyeIjdPruSLEkUGHPSP2 uhRIM4ID52hYDMkhvf4qUCgtfz8QZ0HDIPp3um7bnlfQ2v3QF0xCU5uvvbw7UIdcdLJDfH7tpmso A0/wKIKc5k3roqjmf5qpMt3jjNBQuBj4S659PDArQVqtCyWo9OVSXjWBtepsGosz59IRm7v9Bjfi lIqZdZa+yYi3WM9u3MpORCYX3ph8uw9CSwMkorlPZ+aQlKvg2E8HZm6gER3QZLc+35+4LwPuMk/+ UmxqidTFkiYsyg2MFZpBQtV+8wIArjXayk85s/aVH3LcOcCvz/ROqw+zPjnyFeCl3eCiEWbrUUrB xx3xeswFGlyveVG/b/U5wUI3XvZ6wBrweLf2w6u3DFlLpjEfjKRaSPHMhQWSXkgCgPAftqHvAhlr eEi2zr3ZmeHJ++Gj8SmKn6Ks/p9160dqFVSuD3SQFv4lg3WJH2d7O1ZAN5JPSMMsBTEAL6EbJa4X uCvpiHnH6HZVfTZ8SkQhpCEMbHQdwsLwuSek2qJdRak4n02G62t3H0aSKUIpgvn8mH3Dq0AOUbsn A5FJ1dcQdzx3ojwqTyQLzfP8xSTsG7UM8oP+rAhZWmqcN0HuyowvPcACv6bkC+KeyVGVnN2SvlZo P6fvttbQ9duWtl9Y65Plgo2oaEznJWObOtcr94a3WljTBVkONjhTNhhukruvuZnqmbcRlBJ/JQK3 lezHrPMkIpW7uiSSH0GiIif1XYGbX8HsO1jIgHD+erqWAEbUIlTTxpPgUQvwZ0BWe0NQQzR5fwLv JorE5qWLCyclWuq+xOw1o3sMzdPEqPBP3mrE0KNt8kzdAWT/ugobxAOuRarGs0B/CKvUBncfBg0G nEjVgBxTO4KSAbWhYI3jhrINZyj4qkl1BN+5F4Pvd1bkeOnZyiuYIfCF4BvqAkVSz//JuhOh+i3A b2odaDEL0iH0AzXtgxxPxlTv9GBlhOKeNax2oaZuMSCR8QVo6xoZKMxhfyFY2VdCLCmrQwjPcB2B rIz3DDthryWqjHytYiZb2uP2d8ACC78kEj2+O141YiBXO6GQ8FEbLDwYKOQ2DjaWHi9EvUqlm4KH kjKekRLBgIdN0ydzUJ8/dNL1gsv9AnZTIvHNYaDAOGCg/yeLxWIYu5XhImKk2lgR9p9ZMLVLbEZv JXZE+G5MshxQfEr/poXo/rqyHtDorNL6GLgH+LyBEN0oQnKWaWu2OvyGQ8iomnOASCcEmfp2vDvz kDB20n3zwFlP0KfLliUysG4FLUMPof73SgsxY7cHaFqeuQaQ6myl7fNJdmtEefaFYzJujOA9+eKT h2GCHiiKTR4IUPUS7uCa1z7F8GLvNo+8KTdaJ17HcRLPnRSQELcOiIQ/CT1fY9irI9TTmTefGz0A ZSGYVs7Ju5sJkDE3WP32y8zP44e8Tb8fOczM99GlWNTqjD0hwCVwGwe+MQTFHs55g6FjS0m9Cf5O quPfo1oNWgatUy+/omibitiv0ETunFxaJG1GUJBmPBhl1PKwZjzqkdyfY6pmRkO0wcRJ0MWAg6Vm Y8jZ7xHi5qWx9r28bwWjIdbILlYXpJs3fFsVv5LRXs6HrBCqZp3/5rizQxf7umI/AcI0Oz4YFAm0 JtHnylQdJY5DYG+olelyXAkGE8y2WV8Y/whYAeBAUe0kZgLdDJY9b34tWKGKcqvPD2gTIxel6xX0 MJa1pewYSh6jkUwsIpMeOdCZscuf2GN4/H2EQPomTNaNFJNpTl4b7Er+OcvC8lOTIiuKvZFNH7Z3 fYjZ18RLN1cQnLd6uJ8x061gNDpFDbAxrqISeW4oGyVMZUHNTWJb5wQXg/Sbxdl+hJ+NmxFjK3a9 Bat4B6uJAzuveNHoV6EIQvHuKVyECnI+h6QsqVbu/KkVh8/lzO9+AU0NswocQWcYOb443Gx1b9M5 cYcJDA3JE5xkm68MUvFy+5Ev5tZniQyQvywKyqChOKMP8IAN9AIsrsCgTpHqTOgRGqLiK/TY0zzA uZS46sZhiO4fID0bPfy6VIAAm4WvHlVcqY5VI7POxb3xCA8WlRCQ8i0zO6Mx7kw1+/7oSO5dZlVZ DhTVFnK4bhnBQzz91vwVZzkVMKYaarK/hMQVppmKKVj0J0HTNohN18qqZVqxYQbY+vAZIi1AvP4N hNDOTGt1GOQhEzH22xB309+J8ygnx+K+3AED+Tg0je86qGhJ5cSD++FBU1mIA+7/mYf4OYLTEW+3 JvGPhN9Im/B7sfVJLESMb5J2Z5sRZOXMhEG1F6HVLeKqO4SQguNqhrvGxR8aEU2O0sytBQ5sMuN2 9biqBoKfLXg28xPmViHJEwt5nK+PgBfQIBKkjoqg1htZaG9UN9HHveNlNjzIQ+0AhkIy1fqdSKn/ tNSgSLbSyFNKFC6pzoFWch/Elitph+z037RGsglBbFLXKIsXOj6dSDmRvHu6dpqLZiOf/KDs5jTJ IeW8GZJ8xjWdZgLoH5WtG8lYMcEWfAFD/O/Gw0dVF7Y9oric67EZdMFYuOJzEmpF1rGFYI3DTOP+ NfYqrJkZqA9AiE5VsRF0Ca0qA8yUlGA1Ml6VWYke2FFINnwotFtl6iECOZ8+dcUVlQ9bX1h7vAKT fmRM/MgCatt6ZPtjG9/YlnDgrzYbaN8qrRJAmgKgz4zHRsYA7dxFNQF1lGE5X/4ASmXyBpgapzqu 0t+rp9hyJNvsugkJ8tKKAgQJjFL9S7ycekAJjHuDTaKkpkgLC8YwpV3fDtTjq2Jr8RaAFjQY9KZK NqDeFAmy4xCVFEjTvGQHl2zEJziqFwLpuFTGsEFIxFPzk+83TkVBYGHvYJt+qvkrCDesMLsO0lOm q34fsqYQRw4cDO+jfAPfoNDGjzoIWskvNThiGN7DvHwd2sAWEpZYIwKSDy8aG2aUtZw9VuBHQ0ND gYknQmKc7Yw3SGJBCS+UPNtfW/WiEZ9UgX+UQjz/5h7jvtMxo4Z37DhOZr1Q+pJXOj4SdEMHjeWl pYsrqqGWyaXM/qyUkEknVcoLCfzChD7GqUcFdU2JjHOmlmIUeeGP/cVB0x+mD1xXRIfyaDwOgFcz HmD/3MMj7WuQgZxMG/sJuOEMiyOWnc6lhLVyuPUbgXUhZGySlpVv2pUQfNPWpuGUaNV6WmvAJkty gbKorPq06eIPhPnkOMpeqpE6rNg1DoIaApNR4AkQA1HHnVnzPPJiqb86Fjf0IJ2eeJtmq6BEXiGA zv/fCXbt1GQ7uXq8HfXOsUsizEULiD0pf4KquUEoxEqQcg5Sv97n09RdVLGbqrHhjoUXkUFUTE+k RAKORHUPzFRVDFbJRDvIPqw3Lzi/e6QvrgNKsyVkfVrJWMCEq9NSdBAhxI77wZURThunSx73Ftda ZHGiBpzSbuh2Mjch3d6mblesD8p8bN//SgpVClNdYg74JayVpiozO/PatnW9Skzpy8Yj49vbuOXI fCBUy6NXrt3tA16FrM0/xP9RDuGlt/nKhwz8AROBt6baq5yJhG/AHbNzWpeuQuymtjQlPVj7/MxN k9JANGnByh7uFIPyiqc7Wli9qOKmB/wFNHs1OWGnUVrvlU68YXohLR1PDcwLFNbx7QQYs/+rVQd8 hQd/eNlEH1VN2OUuDxfuedfRSRVGHI9jTB3MGtTDGMN8oXN29oqCfDBtw3f4Skjqj6wZPDNYByY+ DV/VqDqW5htRfgAwMqR4oTDSiZsv/9AEalHFlHBigwR9AtSAFcovSoTEBuybQKxn25Iqu2tDZUgj +DK+kZ6LmQ+qTy2jZzZ5v5+BMysSH6ODexbBjyEJgOdIGWGskd3i/Cjn0YqBSVsTn2RUNIuVS7sT i6jwC3yQKln5ISe14tJEOrvo+pnivdBaZLfj39V1stCrBfIzxyGTZ7R+TyTRQPLKe4E2YqMHV9ix zItvW+aXwjChtM2MjCXrFoolELVXBoskvg8wV2O4n3yR/UgWqcCCNz03cpRIF7ZPKtGA4Vhjrawi Op3wghK/xeK9yuPKzB9T/64E69GRpIL2F9SPQ5mpIVAN1JXas3lXFlRt8FTLZDj3tYD7hMC6+9eL lJQfTnReWESmW4dhHsYcrtC+Eh+3M9aaJY+ha7tr9tMQsqG6ve05E/1VOVBChGQ+HnpkhvZBN+1o SnqSU9SJQWUWf84WE84i/7gxUNe65bTk2D0B0nCOgvug+XrlYLMV2hhmUMo84vIB8zphnoXjlp1b 51u+iNXsUexg0qHlR5jyP8O9nIts2NzDBCP61GnZsdC3uAd5tQm1BR6VEEZP5D1eweO6OxQw6nZZ a3aeZJZucH2LoY87HeUiACEshexDQygLXR6Q1S7AI3w+4SGy2pk0UIxmwZc1XkiRy5lK0u6pQG4/ kXAfdzbJT6T+2U6menwzdauENfkchvum1jQlRBCsqy1NlYC1oK8vag1CgeR0PGcj0c36TUCOpL1v fM3U9QUXIBo9xalPZMuR0h8DDNI6hDBRr+sAnqwySLOWolwoeZXj49X3d1eR9Cx2D9J1W4z/zfte XUHIceH6hReqokmyX+nXGHBldcdLqYZCKxkU0cj8OAhqLxgpvdVD+SSa2pdsxhAICMzPePbDWtWt 2t4PPXisKJsr2f2hqX8JcAKWVpR8He+FsrqV9EVCCf8wu5Ljk+KmhwgUp+Vjun+NQZPf6J3AjQ/e qrrdEUVUezYeHxF9hQcxy4E2dmjLQaTbry0ZNVXcgqrrRd0P1Fd4EmsjozA5P/FMdVJqHjS+Dx5c f87/lbyPrUHfxRl5qV9jRtqffKT2tZqICYujXuZHXI6mAkRA4J2uje7j/NA9avcN5ZzoOKeb89mi 5ahzAw6cNC10X5paqbYDEgbifKTntKruFIuNyZcPY1x0d4aqG07enCSw78wPJLYq3fP3z1DCJKUc QpCQ6u6oizt+EvYvU8lH9Px8Nc6Yd0Yw2EoXhDC84WAdf/T+UKCjPUNMQUjynZGTcohtek2OGeta y9Y+4yht2hIKPUY1b+dodDi0QeZDTJIlpeXHJzdwz4am95j1BdLO7gcJuwNeXmtBfdW23DivAd5y wsos7S+AtdE4jced8c+bYuXNoTLiCqbI04cFRXtSqUCIMsX09cQaFbmtP2SrTIfUFBZ8J4X/+L/7 0pdsduVomf3tErKNFzU9freltjXdvM3+s55zz+2fbhvCK0oU2bLWoztyT+Ey/0ZWlytFYhBvR0ds sso7aSJfrLk7lVldcZxktu3ENS0s+yJ0zDfQ0WnePbYZsdaMxXUTmdrAQ/3P19dWtJIvhGvXtENG Zp0ds2CxjocQOnMQOC7e4Z6nuZnCE83Ak1xbHjBqdJDWCX7n/3YbecNPvbhhDL3OVsgnM82BDSRF +prVnutOkTgkkz6tk92aawsXw1dgj8ofbbnzjqHpBm29u7++1rAURZ3NbC0DOQ9JK3Q3sw31Kw1r TmmGD4RpVGXvlpuDlz6H3O8d9/SMoqTeom5cIa1vr2d0Xm7Yz29vqS5NwIdgtokl6BELa1J3mwch IL9wlvwiswKYzZLLtOnvMUxDt9lj6j6zqcHYRdx0rYwptxeUd3VLGG9PmV/yE0aIFPz3sN+UHGQF f1CfoTZC547n2FU4cGnS8V8f72iXUnsYOX52K0i+/VThRBedQ7XXKDld+eeubcRuuVYcP8ZDn/io PCQrv8QP6I9e28zCEBsS6T8LTpr33TeRV+oRk3zZS4JBIRu+HBjjTLZqJ29v+hGfrHqkwdla9NVh OuW5QNlZ/iuQtly1AIJtI7Tgys2UHtATUEoGk8fxuqGdQkBWZFSZOcTPHeb3LyCW9iY9c4jgHTJU mgxDqCC6ndjt5TbSUkx85qM3iog2YAxNvBNxUF+8hdESYraivxgeaFSnpA3xlQsXHcbEQ0DwVl8e NCfxlS8bxGjnb1JpQO5iJaFOF9Pwssu5H37EecJ7l3BgMzVcJfRnPYUjglHrsOG/SmfyRcWmSSX+ zp5nEmc59VoOYtLwKxVQRvT7LUPojjtLwtvXDKmRJ640z9HuXeci0sPPfqqun/E9rXE6PR9JJH2e 9ygUK7KigN4zFRtX3YFfsQSGFnvBYlX+5YDpwftqNZ6sHwOFW0/+xfjuB4ZwxlHtSJFgWx1C5C/0 1r3K9Blow1rnHOgk1UvawWl5TUcS65MtWOCznoR+Axpw8kkBo07xuSdC7uNm1pcxJvFnIIUUPysI of6Tk6bU7fOYxPE1fjnySreD6BQ5NA/0DqlvdEV14KqOXnFSvmz1NqDH1G55CGW/awkfhF1EzfdZ efGdSyHzgXEO1TMk+1ojQtgOQ/rVm70niLgDE14LaxYNFI8geamtrDMsGt2p1AkpeLlaq0wEO+Er czbrLJNQRwrV2xZoPEyodsXAHUK2QmCk4IVna1XzMdizweXmOm0b5Pa64MDNwjlvZoj+cB4LN/td 6NNmJ0arlLuNjS5nXg2L8YXT5JiAy12oxOoD9h564WV/pWpOj0jOzHcjOTdWO2pHDHKRH721y+rw +5CTLvmL527XqiOqm1oo1ghKD6vMdXEjgChKXx4zvsOtnqIIbx8aI3CE/UzxVQsHP4KE0S3RAt70 97IHdLyOLZDdR04XhWgwkWzck4Es8aDNa2WGzwS5ErXGnbLOuSOaUFUGuZk2MuE0bdclMtIFLfPx bQIh3mvKYz7U0uavCPBeIx5tl7lgevZHNVFS3qqsTjJIUeyZk5DXmH8r4vYTi+8I9V4SQxOK8xZL YLRNoh5EMl5cQe+J2XjgGb27c19R9tmsupkQOYFssztBDrL528dC4Y9cneXXXY/59Atl8yKmSPkc 5t1MatkiEXmH313losKcAEJ//WWdmYzs2DYeZFq6HrFvov8rctR5OcosNIuJXAQ4/LCuNwpWITRl K7HbtYc4rD63DZ2Kr+Da1tdw5Ed0QJsWEyvhd6xAvcdqCseNFLMLsdTPEpzlYv8olSPsN7R7sTgb dAz611FElhQ3wqpT4cOR5v/76uKEx8q95E/7PZusqR/uz9wXy9dGMM3+VDYQiohMN5ueuev7QpW8 a3vGNdC1MybOCOpWeKjymKLgSgD95FpWX2CGKITrZzt1kVHU68RzggDal7Oo+OwqDLVFunDo57lG pYZkDC//LN+uXsiYqH+pTPVgMp8qEdxkX+60jNHugeynnv6LcSBFo8jOQFfzkUIklCoCIFnukRdQ lW3I1PlnnjDhS/8fvtcpCQe7TuARYkSSdbwWn1eQNEbhGrS1C/yhRlg7r6URyrb0bUToHfiawkmZ C4U9r419WmCAR2fsUiof/83c94BXwxrUrW7W+DGPZzWBlHk+Dd2gXZB9thNDy1q98Xqdc5A62c59 V2mxg+snPDDdxfMe7Up90Vow8TvSHSRpbiZG/Ctlgl2XViekB1ifb0XJXb2eACPkZiZUnzVISVaM YaHEYK2F5BSTth8r+omHeL4EKCz7KduoWHhtF8SoSl+DveSiHswBBKt+YTQDsvZ/2Yfac0GoVyda 68ni8xuDBOPUd3pULGMTsqv+l6Gic4zVtHKycoYlmwLHRO/YMfm3hFoazlgvsTwMSVs1nuN3q3fp duWkNzblpVUWKpO56QEuric4Idk+1301ysE93BnmAPnmVNxFkLx7i861+K97lI3JzoTKD3p43IZb JifEzZz6A74R+OzSGxEbMD5KKqJfyeWcmbDKO5uj1H18wEL4BxHbZ1ifrROFOifDYLNcfaGEgUdu GBqjjFGyEsfOAp5QY6IJl6WJVncX0IOxP+qA/lumWVZHcDMnuwcNVS2AVtKCQt194xZ6Gzg7ZQQc vYvm0Auc2g1iVXrySSrwUKOdWsIkX3mIxWzXSL7y75yJkeGNROEeBqsRFeP7sZ8OTk8A5/ahGCB9 00lHIztRqnPD6/zbIGQmEdqq+4c9XBOnotFEYIH/5Nu50zJARN+J9aXuzJqzbHKnQNQgFVN6/VaA sFqrV+ClG2micMYN2/v9nlaNuW1DE349TwbT+NwEo13A6wOI6vsz1ujFtySM8ZVfO0WOXA3c4YgZ Tb8Woc0Sn2OpkYqWEVUAlHZglY+YdFwXffVCubBaDcDriXhVwnMXnLut66W9XrhufBlgW266WOa6 K8KVrHPImHMbIu4G+ohhCEIwb/0qhP7+luwJZ590PMnfB+SzGGS0ECfuuUqV+6lbj8rFe1NGg5nT znNsLmpGsgNHgoB9E1d4BSLWlxIri3EwzjwOEPNvY1hTea6VVAhKbz/TgWqtWywlylZ6mZvd9sdQ o1Hg7ftAKTw7n7otnV3M3aVkb63pHKckstlhHuYxXZMWEfKx1wIaHdA0YTZNR13SPiUA4AIDHMEe yiSKE+FdP/pOAAVGGsFUIRnoIUUqM8XRBLp7OrbvBjQ+zqpvQuDyUIq4eqeTcLIHDc64gLjhryKv SYPada80HH6/tNclkBiHJA5hpzewUjXLmW7WCzIVFd6CQsZWWPrkeh1s69L/BHdaDEbs1OQSu4eH zO68elSLPGFnW0k67FjGa4Cny7Vki4x8lH4dbxA5+mjLzMU5Q/rt0MoSBDCr2dFAI4+PeeOXmYMr 37Kkcum8VQpMXGkZqRkcU5M+Kbt+UJ2AEUY9QnSx+m1aiT7DAr83EmQ0tjm9QklkprgDq0wlV5u0 AV2FngrsryG4+qrDZ3gkqx/BTv3mPQI5BUqT5hq7DXHnA0cBOncAlKHKNnTuxCS7oUrOcue/2VAD U6SodpByUQX0562WGnGP9rEU5hj4Z1mJEyegf9GyTCsymmHqEkP+mmAufFlYD4gc9/AmuXeU1mTF i9sNnBxke9eVI+IPSDnux8Dh7oE7dafujPLGcphC9WTylioAtgTfwkxiuku9k1wYzNBG70VE+CxL dphYpajqrJNO8FTaT4MlWsYw3Nx9R4CTQmLNMvUiDSmxZpxJ5+d/u3H5BLq1VRUGqtWHru9hUC/n 6I4vYFAfAtWo9EHYphlk36M1b3ebJdEkunYsZyxTzCRCznjr/cDLIRmp3E/dYsCCOtAr5ZI6a+Ss plUKLAaERWlIsyceT2CRMu0jC+5Fys5uwb7AuZ9jGThArjVNFer37mllJ4PqGX+wBttIN4Nj2SRf XCdEyq/8VQr7gbyYR3z0WvdVmr4SnTlCZpwDIC4Bo5WFDf5gWF5UJvr0B7XKIZ5cSPLKxdLknQUv hfQFIpHvtDuglXQv3aJ+uGhvymi9jws6XGw1B8KlhPfxv2oPn7oAFoOURLm+kU84USx27MC3nB5v CRyJQxIlRb7Se1h2sF+Jo7EqXFDPtkwnayKALBgKoEIC92R4V7kFIi337n36UQasa5gXm2k7ydnW axAea5qpX6x9uwmTauY2UGwxmCyGI3byvYn+hGBqle843sYbycI8O7qocAoD4dTxU5jmFXT+wPJZ V6dM+c19A4naXUFP7pCzgDtNpEUK2mUzASQhPFdN8OZPF7zpQyAUhUaFuT6/zJ6E901spHH9wQkS rw/8azCgxXO3XI+pdSeyzyy1MMnqRZsRkoTALmnZGmNZkOfrWsVyLJgWau8sfKCycG0C/1eQLuZl RM7LxEnd7D+jQJOQCla0cFrkMiD8K1VTKGMlCS8SYk9yeKsEmilpb4dG5dlPVotHAJKbnMT2Njsw gfg7HLuVwiSnX0uQYwVJkp2uF8pJih7qELSIwLpGiS2uf2gYp/2y8oqoVImMunh8S6DmkUNug9+V I4Zj7p2Mi09GhOgdCzloPtuw3uZK6pOMKGg0boZAScWOTe0u/UyCSIN3Sb5GiD7R6dL427gWuysK bD75ox8YwgkUgr6M8/a+70YnjmEFa2fCVoJwnmiRI23tWKMsCVL71RXzX5U8HmVPlOx3nsAb0NIs iVaCyIEia9fd0YnTmFXqfaIM3Gkklsu9bkvJIjlwCc4lEbDNp7hthkI6DZl04ROp2o0uJC1E1UeV 4BE4LbhMdwO2a0plCS6QGykUN8/ioyGpMaBuVL3zc1m791SMSxKVJHvJQ+kVzyDkBLxeBgH6kd3O 2UKd/hHgQQxlsMAS4ytd8mXqQKDn97qwi7WG2HWQRXIe/n9IiZLrMGjcg9VRcTNWdEjwzvDkWdVN ReIP9WMQEpUCFmo8avvT4cvg1fY1QCX4l4S/J3HnK9J9aw45moaY8fCkik+1waM+mH0WLIjV3gId oSedVkoKCoVRXhl068/nh+OFPB0aTAjJfh691I0CwG1vTNOH5S0S6c2ABBgjFsBa5mlQA9fxQaLr inayMU2i1BEr2Lf44A3ex3H8Klhf7MOpBKo038MfEuJlYhPU/S1Xwb0EYfmq+suvXZEuJBQ3cG84 DwVUNAUBoMddhffNtlZtzN4tII+ES0bkdHhMv+GmF6eBFhyyhC1o4stUHb1C33XVQ/c9sCePxhsC e7JfchPsVxPk63qGko+jU/mPSAl3aI6oa1zj8+zTRC3oRVuBzylTXl8z1+cenOjIJOf5oYnfDdrh 00U8skSXRA7ZbFFFQZIBGtAO4BSQjLtVLinQ9F9o2w1wHfOSnoE7NyY3dKNlEOgh+0dRZLuGZXnR S3K7Qv+eywp8VNWnie0iXhOtIFExYYEvBQue5EmNEu0JQACogg8weglHtOkyPU3yMLcWy0QKhxbP XEfu8fV256OHRdwpgQGmTug46X7yGgzWfEGON0dz1oz4yBoRskGrJ4Ez5C9CgLULi4beqVY9xOJn y2RpuhhuIOiQE2Ks3DkSBrETQfHOJt/7QOes3CBnCAQMO2b0hbheN71ZvUEmPw8ySw8/IEyarzXy n4YCf70RAnH2d7yu2GJYzC4LqLZRquDKJc4pp5wjGX2tdD1K0dg2QM75+8jA3VXS/n46gkeSOYR9 MIIjPN23sueNaXspIvRQoYprDbHeVRHLotECC5LdIdnpQz8HqY7aaZQIhLtAbNL3b4q6O/RVJc4G DATItpTdnn/epiX03s+bYCjqJtwzSEoIGvRU2k3j3Z9Ix6qH4Yz6LdSPstAd2QilIAx7ZDtUwNlO 8c0w5GU1u/trUDGbhha5sr07TDwpP3VpKJ6GTULgz5DHTosbTCTAQ3Kz3B6KQBYtIQaeFPBS77GV BSmN1poacGkbpOqTHAUFJDLhsaQQbueVy042KP+RzuVX//memFYRMaaXePSTDlxaMa7wgoOzVeAA V1ERQtLgKAuwZ20nrjFrG8Y5Zzn31UYkO4EPJ8KwhhKa2SwmlhNB5xwJ5alymJxZrPqQT8Q3m9X+ ckH2pUm9ZXjnj0i858tAdEJCRAiOdT+/h9/w9tQFp55s2sjrlDeBX9likjMcZeI413dQlbLBB44G k3S2U0BmfCxRHzzJLEk4IiBSV87HeKXF2Z7SKshtNV8xydnMcMFcCrteo1HoIjA7WyQKdZd16tDN Otyu3pk1+RvoSdoPFjySVmq2+EzPjU0VHLhjh5+05iNP2YfA+158/gb3Eqpc0SDFbHyIaEDSKfV9 E3fstequwZric1G0nGcZycaMe0rsGWZxBoGHbMx0s95bKkdPePwjm6wjkmh7ohWLhJd2MOrAnVOZ 6RfuALW+sDUbmSFd3YnNkiW0Lna94CxdlBp1Nj72q89zKhRm5jc5hdNsSjI1WCFkeXm2N49NKBw1 sgCSR/QB/ztoVlp8D+N873a/VD2xt46uW+Kik2F3kGVq55xHQALqChspSvd9BNCqu6YsZLWOkRZc F845HRLhRdaFP3jrxn7YI8HX2k1tkJryB32/qM5xKfdMBHH4Ux+QV5JC8NY8k7hpbqKVwXUBriLJ QmzYt6s6zZFuJWl7f43onpIbamM12U6v7TrZ7xnep3VNSXWADCbTqHIeZuEQV9gJ1knFdhNFzgby J9/CU4XkMf25GRuLonOzi25lsr1fEapUeaPBlvQpzFmNyRP6NTjh1uJFSrCXqlP2M9jmSUVyKQUT TwEDfBIA+GrkmyUWRrHjnO/hGJkpLmps80VuGyXWIR41w3XWVwqcgTD6pBgxIZ6J3YsvshhV8Q7l HrdHHB00ZCZ2jsYK9uQ95VLohiuaarqKe4aVAX/RTXzLXl/T03e94n7ES7flQY96NMia/GoV92tT J41l5SsP+KniBWH5zdIiWcCZi7/DZqLP2EUY8E0vCSkIu51f2ZPNwArkq1kfodoskLdLk2D8aFaY JRc5RKbK3mTySrZkyvuapxJz6YiV8iWhbwdIVnKGcTcNNxSETuQr0BhfSaj7T6nRrl4ogAZbmS2Z N2VF1efkN+tHoOiFSYg0xRqAl7SmiH9KoD92nH6B+T9j0lcJRgqr7j/gU40+r8NCYtBsWKkv2IfU N2RUAeLPhMxXgw+iI4n14Ah/5dXvfW/qFC1KR7R8CcZeyLWZFlKqpgMf4JlSX9EGvPYq8Z5MVzlJ vZEbnT7eoaxyp3DWurOzKEpTDiZ+rAtm+Lex60ZwYfH9YzsDvuBs/ywYe47uaXEBS8Ce4PkUtG/G eWf2WWY70Bx1huYAVfM9aS3sGpYBENMaBT7nCC3xQBC5IDDU75Qgx2XSNoY29z5eWxxJkJWU4B0T pXFVChC/PB3n1ovAYf7rWOWUCyvobtr7SCq62aqdBdBTaTTeylEaoSSz7N3ND8OXeRWTh7R5VTBN y4psDsW/wFa/Om/VRwZvdF5w79zQKGVNbIPmyyzIaUPb3mT9Hc5Sbo1diyrwNH7t9P2Yd2MXJJrJ +p7nqkqlMGtdu14DrQMa2vD8B1o3b3NJ6zhTIpINyyqGJfwUUU9hz5+Hq+ZhmuZz5uYbT1U4yJ7y G/lwwFScWtDjLwlz72ATv+fLOXkle0UmmwPgks2Bwvsj+VxxqF7CCHcEsoHrwNsNYmJLcGR3SX4v EqLwtYMfyQZvfyWF0cGWttJDrQEKLGiC5nZHgZJpiDSPxCaJc7mspx0FdyzmEWvboQEeOQuYejDF H2Wy7cOEWffQQObHLvCoVusb1lCEb5fYxuzUEojj6y5/MYB8W2BdKtF8+SxKGcksPh8j5oRzi2jW 974Hw1vXn4CkAZa908p7d/16Uek2AysKptf83kO4hbId3QnnU5JwKQJdLYkD1eSKelSH1Lnx4gdc BRFOmENALpDZITmXJsNCl1ohTAGJdfqaUZbKOZdCXhIh/pPII0PJklmLs9J6v6D28ivHxBcOeDDK 38+Hvhg7Y3HhuLS/bwjZgyc+xhENZICBFHHaSp08NYKFfkurUu9uBmI8hmzN0uiu7CA4P52Buntm HnNl2y5VqsqeDry2bMFgiZAeQVlaagur1TskFCnMrzh0c11YqLYP7kC8dyW1JYCJB69cIK3R1gO6 xoXEjgkI8mFNkC81Ajnn7GuMdWxqI6yPNo972UdsuSRplm2ddG8F7Vmsf9t9my3n4IIM/EP2wrB1 x+xwsdwY0JOrVaLOkkhnYXPIoN6PuhFGd9SQqGYsvHvoO6WDXxG0YN3z0Zws42cqncZZ0uERAQGV I4Ea2YZLMBLvWoyzUmOJPX+gge3mcG+pFOnM2M2wJ666z4dB+lOHryCQijTiYpxhbiYm6LrYiVXq 348OWoN2i94k7Ibw6CUJHW51p9oUgsgaC2d1O+NNGzA2711HbTcM36B1UARVIPTNb5GZ+SflqoWV t4W43q8uxFzW6Hjy0MC6RtFSZH75LOhC1GmMaTIaGZn+ZniAK8E4Dbb9mWp8nhPWeiijFdKzvCFe YOkt3zaQ79Pjer1qXnX1untBDto/Vaj+EinukEGKy0Ein9KvWotVJwAlxyGrn+bHGi+F/e6sJaVt MSJvRg4JAfjS/hX2/E5cxlNzBl/8kwz7Puy8RBRYkXmYwCwj2a886VjAXuvumbg8O2jCXTkvTter E/vr3yO1YNMxvOJlJZTlgVbOz7CzyjzmHFlSi8OjnqAl1bbZvjPAVMWY6oOlS1nseDKN2lxxoF2K kFuISRr69tQKVObXcGboziHr0WfB96sFiVjlt7Vc8fWy2LJFBmbdauQ2rPp1PDq5alS+XWMEpLUv /i6guuYRXrmuXsJZ9uVqr9v60S7lJoUQ+v4QbmFPNJhGhkrpP55gSIBhsW5I2jJvXQHTqpi4VJ2O O7oJsxW2XIZylzIsJDkOEDRvPBUbBR+/VGbBvRUosqM+svgRgrUZWP2vVhIoKiiiGwTwFnYIdSD+ 9V5E/HKYffIMqTRXCtttQ1bpTM55I7Cmcs0Nl1TcVj6EZ8C+ONnN/h17JBLKlSeHuO6Kf7V1kMqo yISZCx0d3sZ2hZHfUmnlG5xDqTHXcqigyUY3l8h4S9QnD9RxSe2xWN8snDDBAoMUdRE9uRUGHWRX EKiKyg78mJPRfzslH6jIJMAHO1e6pieUC5T0gKW94gEye97yKig48kySp1U6KTcBMcN2XPfJJYaO jfvnZ8JGSoIgRCxAba1Mwh2fcldCcHm/h0YxviTpFz9WQ56J86abtgPV5MG7dWK0CI1TfViGrhHU 0nCa+22EBQ0e0FeDxX2dj2An2gNxMSjp9Unk1oyaeokN2O+7gNRfCeAF+iw+HEJj1zHF7DBS6X5D ncVexuYS5DyI4Q5XkfKBHP3kpsJySuNkCbjJG6bQ+KHhqs10k/kXh1/XPDV31q5r1bfM4b7qIINW DnuSStwo4Jz91fdr9wtNI2lwwYWjyC/NT7XT3sQvaQVCdoPK0SnKXV20OAvksMjcpJNHGlazEIER PF8kFeVgsjaBvx/+MrY/iU8JHxZrkRSmDwvH+HLU+QFrYjZCxyYLaXsEDUQRnAvrSYfM7KmGLpOQ tccP71xIN/o/ApctpCOq/zzMFp3UWkei3/9XAw86SMv6eoDTuD272Sl+7z/Eb18sW466EyjYcx7S lX/yNxaLk1D5Jzasbnvk/T0qcfd0mVvWW+vugjpRlbyHqQ4PVsWX66LsUeWtLJD0vbYc42m0GW5h EBDaLHqh03AL289g+SbPDlgwkI8ZiHjbh2u0FDxpaLr0ZoEUBG+bdMo5He6ETikudp84L2RnYGmE V9CZtw8w7G88mvkSpheoE2zL/WY4RyJE7Gzua81yZ4zMYslpp53gahEvGFpbu7JU8mk0vuLc5FZo xT6JvFboUb/WBa/qtsIzN9hec55JSfhneqgRs0ZMdC4g1rfGVsMUknZBo7uZBPXDvOrf0t2hieVT pEWcq0CIxdvwkAQsQQrHc6FhR+g5hHjFRDjgHZa4jphjygA+cWwRTGaXWOLQgozQ79IhXpzXb12G NCyusGdNlyjhE3MZZhkxPf59FsPEIdZsCNsLF7oPaIf1pGmy+GNBs/j44mM1p5FoZonejr26bP/h Idj/PfgnR6Vkz+iPGLU076l33cGBLa5z3O2XByQyrfB9bbzk+IDR5O/+kMftgaes6bq0ANObzTTx A1n5DocFgng0pvKe1OnTK96dhAa5WN+Gso5Hn9AWbjJrYeBewHrzhKTnvocHt3A5DGCNvvjNSGK7 se3dmfvPz2ajoCTZoW9Ez/s6QclHJGVKkMp6rWPClKGRmhetSP10IQ5vrOVmN6pajuokS69UeGn/ kcEVbPNANexHCXpaeXliM+iCd8xzRlzbeQQKFpcDXf/+Nr423kMDDxWwjdfxF6qAolj5wys/z3zG KGjpjTqhx2V+6i+TIXS5STbh/sAA1v1dA2avjFcZIpBmtlcVNcBM55ie7WDr5e//oW23k2V8zokp KpFOCkfhHD54iM34eKUbk/BryM+zQZS2+3CYLlfsQACPEZUBPhXQIxsTq6OqQKwPO6ij0zsInV2e nK0PLVrWwL5mzTZ1GjE0n2jAUxqp6l/hZ0N3iqHzcPO3Zy+mKOC4ypOkJtr4dnf5S6Or+Tng0us3 4IRmgnuf9Otugb1ug/+XFna4MFQHEbuV4nm7EN0N30oBXfTZSzEuBDPcuFT4vsDWGt1ED7j5FcO0 x/TzSiqHN8eNWXyg4qmmJ+yqD5bJ/zSW/n/vhGh4iOUDcWknvITYXqGwIYuWZGUPAsF8f9oO9z2j C/wkNpQDhTiIpNVl6nbppxaxs8v1mWRxABXDP6ZAu76SOXBnxoRJ/8sobJH8Iq+q6iOWvwxpqhV5 SmeTZ+/RAr3VNJr2YrjJ3QzDDpPvHK+mxkJafIS8dCe60UjOo+aC+0ufidk9pORqCYf0lj3n9M9B +RcggGFtRNAoyJ4ExuXCxzRcmC8+pqvmcK7/tLJjjX2wxa4epo852Wt05B2h6wvqpJhV3L1gPwT7 sG2IdbbPGuek5FLOuJp5XfSWh32ktsth7V/nEsNhDE6RuzajJs7HcLPZ3CsUVVzAldYm5mQan14J WEWlDYzWziJiKc+LoFpEjqD7Ok0E82lf2JrnLFPTlO6zg9xK0fqu/uMrRBGHSipDfNfmp2GjMVTk zt4B7WLeNH7fgYmSoC+FfyBcY6Pv+kLZDut7h6TBThWhmPLPqnu95n2p8wgSxLfa7AEq5HBy5Hbt /PrIL0lQUj7LHeUUGRfKXmscLkpEbbiVHQrzuRQuFvLU1Dy7TAYmWjeJUj0JzIYBIJtJta1gmkHe z6JSTtJgYIcmMZmyoPhHvO9hrX5q9I/Cx+tKAPAHtzLvUoLJ97WyqolziN5qxasJFnZ1iiHvJ5fd 0PpfC7yqVnbOea5Oi3Z0bni4AqnK4snLA6IXBER5AZvvhscEj/CO/ue8GnzWuNcAktQr3qWrL2Iu XesaFjrWsQAmP74q/rvLSt3lKYyyrEBksgBZlOcO1eijpZRXNdq8dsTGGSKQGw2SBkTCvleJEIvG NiIBkgymdKmNoDl4fthV44N7574X8/YmzrfPc2mWX1ekpX1mwVX220xOHJ3Cw1+oNKnr156Il3yj FP5JuCcFfUpghErM8p9XclUltMPegBKNzABMIlC0tsgc+u9JShjtCVHDJ4cpgjQd0tcZT/8FxNZJ sSVWohprfnFCJUAuKYOKGOelnjwi8Z2GAhsoDMvY+PrQZGhvpmNIL+Ng/in6h2LhR9TIh64QfqRb nCuj4VY8HLn37H0QcDKoKyAc7tZnJfryyaQ86Ix1CP2lFbaIdniALbjBjC03dpCaksplxjbs9oDG d4Lmty5ktZYRff0o37QLtWFZ2sWiUioTm86nOXcLdfGUgNFyM7yCabPRgYD08VTHnqPFDA4pRdlD 05egmphYE/+g21gEvFDvHSpGoWu3LDG9W3EGh7dkRNVBQiZZVaUk9r1A+Rq+VNn7W92i0MkU5PSa VYs+Hvs1GA/cJxgY1q4WIu2H7Mv/Hbz2Vwded8Oen3mAOQz0QPiNKPM8J1+dgxyvoZ9bdk1Hyw2a EXkg3AGjamjHst+IEu6VXRgIHN4I9HmMOo686K8RiUPhWg0k4NQPLAnhJQ62wqhGsU5YE3RSRcVP anK4P/jXZ+3Ov+fim9RE8jwSsWbMro5p+1ZIn6bQZvJ8YBn3/3A1gwfVQp4vXCEJIWeJdbBTVnJI swT7kBqmO2ek+PfKgNRqTT5++6N9DZS8Qit+rikwA69DEVHPIBv7ZeafffDbOgfJ7UWyjsVKu1vC zkOvmFywJjhgJuHujCNOLNHPLiyPrj6Mfhp6U4C0bqEWGdI89yjoKDB4lrE5FqG7eGXLyAZEH8ZY 2HpTcYjvdu6S38s8gEDJfiJ2eWUd3XNLDwUdbEEqF/ejUebU+b02YM6gIq1chbn9W1Nra1+ppT9f DxAx0FVHgrp049u7MfsdVot/QvoPDtX2fufC0bWsBHBiQ0P3marfKCfrsMhyBfwruPqLAAUnae71 p75JsB4uTq8mTizjGJxLEYnG7ljekdAfIwWdV4mc26aKwhKFkfibWzy7PFk627r6Xe6vQ2J7zbbQ RkLtMax9QAAf+HODNiOS27nw4A+ewelNGsBY97psaFxlZZneHdNZdyojc+0H/H1FApayu2G4HzEt x6ZSwovGfXqEARKTFmCv68tCQz9O3VnsHikxxBOqxvJ2Io9J6FVewRImkV6LEMTLJIm09ZmRVTBW 03rXSHuq8qDp9m9LlG7cBKeb3/YmIkg5xaTbh3qUG74G+zGsPj3FBIbb1J3SQhgQ4gHMruOsMrFl 7a7BdBHoA4jEwh/ZQ75GM9oPB7EkLUzFOlKwqLK02LQgbS8mJa6M5TwX/8j8qhwZacJPmq5uRFu9 uhazBkQKvMfWJ6Fjm/F64Yu831Rl5HiMUOqlbDVabHOBnJs4ttQF+i0T74TW3ESg95BZOwyL2trp fqN3iS1anCw5umOjqgRaAMSm02PX1yIIL0y/C9pBs8FbR3DbZGgsW1Z8K5p3qqaJrz4tBiHAps2t y0ydle0ecl1VXrCZJPTEXV/xpAisvoKaqjZ18juBBQOP33VetyjZexttms+d7YGiJDwaB077b4Sw Yndh42NUt6nuIG1Cq2fMYM3yXlY6aE0J/mp/EFN1BAytEC+4+YNjqmHUrCa8FxqPXlhaXtRJ8WRD sX2EUfRDVbP1LvEdO3PCAM5N07qNSGzarXGFgNQPjtV9f+BGfxTwCFfrFLgGyL+j764y1onYHJoN y4fssscGPCs06Tu6BHHf7ZipG+Mk27GowNc3E8g+r9wHiQv3/QD/BoZ84xsPUL85M4GD31x7W14O q70DP43OuGGUaZx7Zc6/MPd0DKOFQfZrazBmoa8QjemXhFjwKZiSfRPfA5I9qdSG3TCjjOKVTwuO sLiwLtwPljWVbPuNx2o7LZBjF0Mm+q8yFBGS6drZPORTWrOj/Y9Vp1e54rRY3QlVhqEMLPW5HSGP 6yasrH6AnIip0XhxVZ/AaEG0csuIBs3Q2lsOTzbd+SFplHmSLruaUrziFGH+HQZh4y+odPu6xBuc bNvRnz4v4p8StcVDdNIa6eraWD1/G3Fs/P0XSnK/jN/Pa726XLAD9kYmPAeloRTS6bf0UzQBDNz/ ngLJPw2mg7nrjbelcenxKvYh5pF7nD4Tex7Y/drGC/J6RjpFhHat7/R+B72X1Rj1caTcvOYsyqi5 TbHaMlDm7BE4lGN1isfFAArYYXhmTZH7Lq2pXqz7e0nPBy2fpDRC8rzfPT/4ar6Tjw3fv+h8+UJX L6ClmMN/e1tDIp6EovgHhz+mlX4jGwpCaaUgY0uREV2om5lzyGw3fs+z0rKbSjdsBdpCpn4qXwKW QWIkQ4bRfSAmkQJhcjLBtpFjDhyX43iU+iL8i8bQ2RAsW8GFQywwHMJrJPL2Fq86VVWVbQCIZN0J a3wiBlKfZXmY7REdQ7dP1HNy2R460tPlGX45ONdDRv7JEGtVZOJi/mgOUj4BYkwW+aSO2/d/Ef4y gLWcd/p2eJAe7/o+IHT/k8AlLP2XUwqJp6mbhkShMTFhgESegeBNYrusoaFshF7YiFes7OdwZIPt RpcN20iUmyDAmdcZYrMxZ3wK8VUkzvldhwefefo+NBPdXeTPlqmkCrFB3bSXJcg63KbgLpHASwzU PgZ9K0Lvjtcrgdt0c4ghcKPcM6Uzgh++Ern7HQQnQrYxTGrI/RID4/DDlUCf2xeUutt/Wcr+Ofdl 5xEfEqvKgHqARYqISiForGU1iZuZlvXTMO7qAUkgwDooR5kmmJ6cGutYWE5+eDyjdt1Kne+O+u5L NRZlrG3j3yzZl41v6KCkKGy/VsxjH9ksjrVLKDNcH957fVr4WGSnGBr9zXnhWHLxMDSgOEqKSRv5 ORLXo//QNlAJEO2ehFWbw2nANtq7G0wwRlpx83QuM6khPqeODbR37LwQf8NEfkw5rWAlBxHOpb9F FS/RkmT+opEymT1TRY4suDwPBlR173Wrtr0lh7VivyZb1a0ioX+weVHekwmq0GrbDPMKZ5Kn1Ajf dIPv15Bi7gNQ/T9XZ1d8JbydQnd6G6E5O2PDaP1MvITT3OCAMYKGLZnvsmZIkC3Jj434N/R5mCTN 8QfzdYLgn4x1LO2jQ8BU8IHlq77ymhidbMTteOn2tEMW058irL6SshbvlrpJBPlRfaaRen0GNJcO iW9C0w1pWO5cgIa6EbnqKojhga+fGTDNiwjM8SUDO46Tq1uu4aY2uqPfx3oJd7nNW7zTh4nLL/vK yJRAFUnP7c3Js+FXq3X7ROQlvQZ8MFWv5j6pc242VUF1JY1sZbtI1l1vwL2P2VH4vyZxrSU9wVhd mzak4Wh3GPaWMlM8qTznuu+bgpDXGWbHSb7tesNS2NvHB4Pd0WuNBAbFsF7M4IXVx4mixoJ0yddY Kf7hDB1vimJZ5Vty5UNXQOeKlr9xw3G45FNMcWkhjAuU1T9Ivx+qZ5bRhJPb08hlsUtJFjFiGnUc /PmtKagjW9K71aA0UcGhMwW9JnrqU3KNQS1rtQY5ojskcY9ofuuEueW7WoAV3OxF3GfOdbLLLSWf mJJJd0YILDarnzC1prn3cqE51SXn785xWTN9dN4JQuYpnQwO/jC2DGXfscmmb95yIUJda/gwAhFe 25wZkVPHJeA4NggH0eOeAvvcxKDg6kAFdEKlkVfy+KJvL2jXe8w7D2aaVMISc3PH6EAdwleLQ5qa pfK+gVg2eLUBZMpcqGCJ5w0fz+KTFHkfPhY+CDzaUGrDStc0W/R0uTRc5bJ8uoBNQ9oaWle2/aeu Y2G6gAv+TBth0+jNk3ht4E2qgjnHb5JLxMMKUCmITobVGDrRh5FLqpmAYIINpF2dkJnJ0W5/q1S4 UE1+WBDUT7VWxpxROIDPP/WKNC1PdEArjLoY3hJrYL6gavxMl9akyy3b77p0ff5LDD0L31yBzj5B gtLkZjp8A8iVEVjSmZiUg3piL6+C3TPj93kqr2zRCkvWbvjB760EY3lm+fYz3r/pZ4JpeupgbAvM fqcbxEFMhetVSYoOdapuB8LVljJwrE4Y4Ie5WzfGDOSdZm8PHFUXEu03WeZej2YfTDxZVHOoRcM4 H5gj3XOMci5fDopu7ljVWNWGfYsUwp3V5MRRyG1r1Ajwlbzt0vtgE2tK2n4Ae3O1rBY7R2YeDS21 T0OcK+oSr7dLAEyLLPz4gGt+M+uchD1pXGYjwfUahZtO39pJg9W4x7vfAfetCVtmn/e9ZKQAxxML 8e6j+hvJ3N/TibnGMzQ747gAzhR6y1CWlhZX3BahTiQ8WPxuw7ax4+pzVt7773MSXPHvCpZJXAl7 2PBt9sJ93AKdDkGLSMDwKniovN7DxFBnHJDrUrQUPmagvCr4Vxl0z0q5fOyTh0hFJ7UgfFYzpHHz NGzOU5FiOq+zlKVm/bv8XHFdrUiU0haEVCneM5csvpIcElk42t5dfDYhn3BL1QCAgQQoV8R+mfQ9 Anoiq9erKH2JxJpvtU3qcjl+Pd2kUxlJXY/iJ8C7gFcnmPdfWx6bFxyc/odxXbKqao0mjokDRGQr om86WQhN5+NwczBEi5c7pxry2mdXZyZmjY3DNXfh5F26Ub7Jvz0uJ4gq/xU+bfAEj3cUUS3tJr2o 6uEGG5tzQ2E9vvjnm4JfLX7f1mQINAfPnlGIMzTZzzkyKargDbrcCQqa3jfJCdfyZr0RlQvxG+0X S8N0F6su/vuorcC130tFg5GFpjlyV6RDM3Daw5W1iprx8NMOcSa0CmqdfJTm6vGTvG7ed2uJqTS2 2Em0YcAZsySAKMKDUrFpf+VeuiInc+7MvFRM7FjO40aA2sLjZS1c31lg3Sa8GW+90VqCuxusx2RX dk0XJGs4NJUt0dXSOObHrHi/X26kXnf+xV97kBnQlQQsng0c5PeDuKQ7bdquawqksaLp4U3yqE4A 0UANH0efHe9wsp1tF400tmZ8lcWFkxsYuhz/REHB+ZxKzMaAjX9aGGse2tiQ58k4wtHif6i5bAWL Zf4HdUEBAChkxT9RJgjxMMwVQhOJKUQpEl5LWYkFUsmajzGjJTC6ZvjU7VuiSNS/0k+p4C1JziCG WtF30plAryi8nGp2z7bRurNgzV/6bly9euNMgLGPlxOQJbB/LmWoDHsACTx9JTLl79l6bgWmPhuT VWbQItk5HUgGnYUafUWCUc+2Y2YqFTcfIHiF+8sHIXE0adKSv6eaUGn0JUQwuDoadRhg37nKCgbM cKtDAL5jiRAesdUxQFLMKVSsomdHhIRiTfF+lL+yXeNoETiczMwniTjDrO/FfmfuCQ75DMhEz4Ua IMBZY5YiGtuFQRaC6UCUjVDIYHzBEPM7+zQ1DXRLMrd36at9j8TLBLbH6NkI4Rgbtptmj3BwkI6M OnWO5xi4HXbowmiZidJhxH9MiqSR+nyyQjcOfba0UBqL6DOXcJk8Ty18mXtIC9iCIBHbxZMCIRhm 2LgPrfGoo9VcOpZi3FPa86zrK9QRmRxduAz/yeQ2LwOeLnmaSYO/rudKNpBhaQTjyf2g/ma2hswu EdncLgOag5f3h+oxmAEJq4HztfPR+0japVKq+xPn7GkQ5VuRraR/Vt7Nn89ZSdcfz5KRS3rczCbI H/h3FskOYuMe6xsI20w38YFYqRgsU2OJxCTzoPTu3FS88IZBAVEW1EcaHUbfDA5U3BL/05dXESB2 tLdouzH8JUgGwiorxmTuVNk5TvowHYltM54N+cemCfgtsFl1MJqfdtyYZi6jpO2OBaxbvgqFMd2l AAJfFamCBkmvyYw9Tiz0DOuVvIp6SpwSQPxjQl6b0YZGRN4OZWxqNtFh+6V7Bdkjx70JkQXVIGDv qdrOTXrS7J4SOAN4arWDTDRfqhocnPk2Gblyy9OY8UM8s7JS4N9yOiAEa+Pw5oDF++CZm8Wu4y5y ZirjmPqZX51xsZTkez3UPHmR9cDu8A7Q48GypYPDLQ3Ri19+aOP31mqaZ7NfbqvGlGtvmD9dDWP9 tTOPe6Q6AM2SugLeFQlRP0F7OSy2+9JJIH8ZLidQGBXrVSrc10v8kXn/ojHRRbXTgzJSIsbIEePn Dxp+pEYwu3ZxKPCkhIpi2rhGlQO+4wg98je1NqgYCTajZNGdDccVVQDoa7KX0byMjaJvJpFLmctX /2pzNnwL/Yffd8WE+wNfgMWh46L/OYlmdSSt7Ol+kTYsCgakFLSn0r4s68M/3zmyCEzwJ+eFaLf7 wXUB/vcQDBjmGLR2XHZl3pQ0a9Pp4eaFB2f03IInB8k9yem2rj+THO6HC2gqF3CvLupyS97+FW1E wk35INaZ+k3WJwSbevhmgNcJUr8K1Odq5IAAj5CmAgTg2R2aTMBS5DzIrlPoSie1dtvNFEJQnxOL sL8nPTvzSfFcZYQ7dTxBmEnXpTbuI0PBs71cVhPBOCOteo5dt4qOK+1ifKrtQSrepAaTCW6tA2BP kbcveIiWaZ2960i2Nl0dZmTrksufHo8nZW7N6OwPDkBkXnOo2FsH5Ha36ksDz3j8jYGz0drGZawR m66iTLH+vetkXo4f6Nz9udhHbSXW+HUR9V3RVLtzK7Gl/c1p196y8XHqnOEKAZhvt4v3yQiTWxrh rT8mujlx9I5BQ6n5c961XlrKFrDgQ/wIj/jkt3H9PzVyByn8MyPX5rkMavKS7/hZOi8UfwMf/vU0 wKt16Ke4F+teXnzdpCvLYzL45EUodYhFa2Y0gVkEcpyU+UnCZORLskTuktKDMvG2IN3qBebOGSPY 226Jmit3goEmYetTBAIoNHqHWeEAaa6Nqf8xoRUgAN6OxAuQoXrxVNwAQLpTm8oOqHXKTSN0G78F C0PrIvftqb3eh1a56uyC1jinEmYkztgJXTdNFcjfKf7twF4sIipmcXJHuU9wPJFXcSGWYlkRL8WX PwyrEzzle99j9Y7bKCThv569NOx/DRXmns8ZRgNwZpjIFTJMx+2eBlwqddnZxJZIDxrmd2EZaIir taGpiopXh6fNEXNWGoEciedPiOHpLbH7aygGhsMPRYNs294SVaRRu1QFpcMUqAN1dW4VNizijAyH Q1DsA90Ee7A1Spt7BcBuK1+ZnP2u6O37QciTQV6IvBeDRgylw5dpjRtEttXnh01VNRxiKvtRjwuK wch7Kamq7fHQNoMGXFQAlFRGR/KlFQVJ3nzzm23MeQV3fY8L5Cl8Hc0vZQ/xzJGf5nK+NhjKj2HA gtFCPf8PCLzFsEpiS7Gb52xzlJY0bvRDP/nCZn9PMIIvo4nl28t3oGPuG4fVp9zUxeEAG2e4qB1S 2BuDRLU4G/JtccQS8q6UcIMPLx6g8BzyswVkghlwBgJa2pb07rHoiLWhwtN61z/fb+TgvPsMpxdu RTfUCEnjX61XEoCp/YRI/kIpUBf3LZmPPXBBzV8QVBfAmwwCmbwQEBeeuPHJgWnQypQXZp1h6jvy 3BJjhtl1m/doq0IWVD87UXFAG4ePHkShP5N4tYAbTtavUFxAFM8LjzdqsTUuuUXTSW4vniNdZuvy d1saSH0nAyofeyVShGCTMAfhnd1x+D6LH6LFuv3Dm5urHGEtuOXh7j6gsWMxMHGTxwYxsDt7MjhA Uo7+SKFKmok9W0MWKkJ+WSp/JxE26uyYTJ5nrBAmQW+Uuy0ZWkF6gnrm7DlZYVQnZLZeZYXuO33U CNsrsvJw1l378HC95wZWpbwfaGxEzKDotMctYkAyFdNIshq/TNKlfI+5hOCp/g/ma4vIhQEVI9Nu UM7hKd5oYeX249ABd2VKoRv8Z0Rehx6i4PEzPBlHdSjZKdt5zmzbsvAivoULyvB4upkOmmYK/rUj VkpKpm6O1jPrxfUrpVdTKpnhKTz+jACxE0kWnLelV+VmgRGY2SYH2Fq8vJX51YpD63+UzkPIqMzc VXVsqA56UiXYQxexLt5grHSRjM2Ar1g7VEwUhl9AWN17Hne6yq7m9xNTN/4T7wMfpGf/heVMyeDH /IV2Oypx34/zAvPtY/LGMab9aKNvHwxQKHScti2UeinYzbswgbgI7npHhF1Hjl2Wp0FdQAAmfLPz aijoHfZeuFGGCnCCaFKhBfJmigaDeZBY7bSWhFJ7IV5FL+7xCJk0OXUrPegmAN1SDc2bkTRUaUm0 4UxukpQ6HhEAS2/YMyTQ4KimUcbV015VVQt5geCFKZo7WM6ayuma8tbyqdTJbA3pkxCTYD2eUTS0 yZYLKPQ19VTig60+JhBL5JRjX8GLKOuB5etEiGEVCUqdGgEfUJdn094u7s9iuMDWkWjg6UZCJLXc eTMGnoPwbIsnkbdiBayae0hFB2jV70QgYQ5gleZMhHnBgs5lcs9qYqP/WF+MXPbTt/qPeBSqMaoQ JnhBXjL3ldNUh0ijs0omgoZJ02UtywnqyDRbKW9isAAGR73xhKV4rTeEe3WLf9ECcZuIK1zVDSrs FVmvaRp4jgUl8UZEQoYDOIxY8OmmbXHRSkNPFTYIaa+c9I+diFgvWIqFQw1eAszWLLZsoVA1uAbV olxHBMmFhkisDCtHDFITMoiZ1eqY/wVgfZpIWzaampPm5C52rzdzv295ZdEaBfG0RsnvvjBzhHt9 D+dMOTjQdtW1zyttnjB8Q0oqQ9UMbIvtweEBFBx8Avn050A7/YuzSmZ7NyfnGnWpTnuRf9/Q+Unt 5tG8mM/F73P0uKyac5T0RB55riW2sj4def1zycGONSWxYWrl93t2u8zQfZAn1kjukvLhCnY/P0RP 61xT6D5gvUOEY3gjzrxZJ4F6YyJs1idToBGqi4XjV68YaYB118bhYFrO5wmwPyxDFkJ+Ul2gcO0z z09Sv9UJBjNTejBbRPmzjWjApZWtC9zGQLmGJh7rKwd/7RABwH24/orVx8yusyNAVoP/MdkNVzKm 71DHH3Q9MNvWn3821ksdRklJfcI0u29d1pYWKgJjgwc6rX/gxLGPqOjDZhksByXS8WitFB0rNlS1 ohHcejWxAWnQOs1Be33glQJ5T67BttWgHxgZeQME3yor5P7jFEyfMpak4wNbTpc15rZrHifJb1HM l/8Ud0YSB+a+zvv45rjBoJ+xPBr2U31VIc6I4uhG7wy1Xfg88LWcmCXLxHMmyxRLpXjwo9oZ2BYR +a6CYpw4D1PivV7Dfjd5tdoUNJ3Rf6R3J99jtUaBPMUE0itFUnL9WjOgWQxtMLo620xco0tIeNGr hkoxMVbiHt+DDFRuVpqjOK19YjLMb1yu8yr5K3mHClWPNkWtO7QQ3KW9N4tzNqPPZw4oh/6ZYpif k5ckokAZFVRK9JpA0BSZq4n0cfIaMcNjeXbOCtbcQXorFdmN80x6ufCnj8x9OVAbCtQthupqQdBu ypI+2H8ivymK8mmpR1hqbmJyYOYY6rVIB8BtF2zGHhSMl/cA2feUYIm8pU+0ro1gROv12VktND40 V4HX8P8xzjYFu60ZQNsjEWOrPELrr8UDJ7oUeyO0rtGM6z6lQsETQz7afBGJkJYKk36rob2NYC6r yfVmsJvpEPgmy5kJ/P8PirbYqINQ27t5dmI23nIVS6TLXPTI1765GlZxzsYyyU1X0Vqui9TZKr1H 2fgk/3FWIc6puGSEr8nFOu/m04ArzB5GHvKD1ifC0VsckZVAoJnKZ1+mwMIgKn75m/OUTExRHFnp 7kBYl7hZ20hfPdGHvTSFkDGJSFPilGxpLvI99YK6tAjlXFq/dxWynbpdEpAwbMjSmMBJKs3YQ1JJ MOdHFbNNupa0nGKfrCwSWiEyo7xDrTF1ldbI/aDR6wFlMWiFJhsNoGQf+1GX4c3E011VgwiyaULy D+2rWy6FIT0PaysnAR466FcPk5Y4jT3FD5rrNXDjOwetJtjGuegCBjBz89ZuRPNNQYOE99c7tjQa NWnYO3uQihhjDPACKRcinh/2GBoZFzSILBfI4NNLpZcwDaLhVyvvky4CTow6Kk9y+zFqkemWn+jI tZ3AlcVQdhLULzD9X+14qNU83bRwTlgrAYhSzjkVfTjwX9vMmic7h3PU1HDaL8FuVHwXSM/Wjzxp ZuwgcurpTdJcEev99epiMpA0l5umwE0bKq2QXgMJySkJrJrUH8GeTdKPNgJjI+4dA71j7aat6Fsk JNcmNt3ZSTGKLS3ZVwX/+g1jv5OMREu/YQ6VH8rca73dcrMf/BfCfMfYWLlgFmscgxspJavwgSqk dDrX+FOiKftD6X7jmm0rdShThQBu8VpjkNc2mJfJd1UcClf0NmYO0JvzPUMCrrVfz+uMCImSv6Sa F7yaXN9KZXHkfMiHs/c/OSOfRTV8KEjGCS7gm0lt6zRgWd4vrVDOlv0j463wdjfUdRJSAszQ11GL dthAhk1yw885GuA5mpnA66UZTvvop6g0x6PfQ1WfME9jxDp3u3SLHI7QGUPY6YFMWqH4VImnR3Fa sM8cs83x2GlF8P0VRyHC/5s07sgeQog+WOebR2bl9HF+LZ41moOonB7yDDcCpxTyiwQ4FnPMOMIb dvTs3e5N42z7PJz8TySgD0k8N0XU5KvOJryu3o7MMWqhYAPA0cpwolj3IeBAWJGBDkrv/iGCJhg/ Alkcz3kIo5Z6xGRLVF6OTuptg9gasI/KVbY0xaN7MZa4NDvIn2Jpj9Id9FZH7yaN+oLw+iiJizlc DZa00vMJDaLA3Ie4vpw7xijratUkl4+lAy4J+68MoT7xqMmwlIv/43YCHz5PQpqtA2mUe1o1Znl1 6jDOifWErNyFepBwvwCIvmDEfc2NPkX8kHh0fzWD1NJptU6ITia37rPzU9zvwJXFbGP7DLPnyV5h IZKXIECsqbVPunr2gH5PxyTQTwH2ezBderEiTl7lZARgcWj5l6GMIpdI3EDLlE1V+Cw9uAbgdkIU 4dvJEjdhs13kapR4CL/7Vihhe+2B8wTCAGWZc0Q4QXCmT6Ht6ftJ0KRBIt8x4T/ecnYXSUKVf4gE ze7GOPv3kZFqC1DM83KTNhW7oNz5Tbi1Ywh2eaQ8FYDy2Ldcj67iTTpKkFN/C/8836TD3oaa3s0u 3t2E02C36kjQ4y4iamBl8hEmL/OgYj2SNhi+haXQcb6pdnCL3vjAnwNPvV5liedkB0c/rU0s0CY6 XSXUAnLaiGlGPs5OYaKZT8WfGU7wI5zoxCAIfIAoFo+Sw0AZPKjl7kA7MYBg9HbrUu1+4dZRT+RG ASB608dDPOh69ddUnHRwW1BhNnhJA88bEjGC/YabLSdnxvojH/RLCDNW45fJ8+o7+p4jpvYeCNAG ZiYiN5ByJL4Za2aP0Z5jUmALRAgGQ9uc3AgKLmnj23h/SdSnn4T2/Rd5SVJsfXt5rbbMisjZ7P4S zXSO2yROqkuAjWiRYxfckMD0dtOzh86BjISHl7haYpfmVv3yDKuofC1O7DKVA2KuuEV0VbgbMTGk oqeowBf07+o0K31ldsMP46Or94Y7tR81IYGYp9nPXnv8DJWN9SuZqhfWOUQy7DL0RP36DZG6wV28 e+lPFSHgyYezHMAfyDU5PlVufCymErdy3ey03iJWzNbjB7BtK+yZdqCKlpLdElot60s+/w/X+79X fCFqwXPsNsZY4SgnAmgwTdpA++RglLzLivd+xUAILJiBUbzPSerBANkbxm1CZoJdfYNyafNT1RJ2 8pDtFXVSYd2FwniDcetWtfyv2qRLecsbVU5wBkabEO4m0NG1btCMFXYJAIPw8TwnzhtPbPWTw+A3 wtd7F9ULp1orxBaVx8rMVeqI+YFzJFdxykeXNXBWI24SKJRtiBw5qDOJG0MDMShIopChcQIebmIm aXTPxSi3Yv/588JGME8MlsvrfvW6wg78bKJDl6914EvYqaVmx0LkggSseIieFZLgDYwtYyW/sJWp cchME54Ve3DZWRNh777tqvCDHG8jTFTjaPJFJiFo6DxmwbWblzt3J7ZFW5PB5w/fqgDn3TNW2DqM JBF+0EnejJlyVNEZ6Mqw/1Ud7mfVkoAwgKpbiWrRBDkGxgMW4aFi3L5GY9VVhEKfKWwDZnWGcgXR ELjVDdfaqAPCi46GvmKxJYEy6mZOAigW3jUGmyIGoNJuh0tVCGnrcYZhrRw30h9Bo8eJBGC+UyMX oBglmUiz6gveuBWbls6Bj94+HINmiW3ynuhZHkoG2iL9TXpC3GDwAR6YMjhBTAXUsiukIejfemHN TFSYY9QLz+mxm8psLXoEntvc5RF/ey+w4g8obhIBEMjdzC1BUrVpPAkp2uE7oABcXlTqKZI5c72s FqjmpJfgH8Hr6d1+jkkEt4bA6aeyRFg6AJB6/ChoLw8QBcuMOtdWxZ6VmIBnQTCLxduGIpyhYEy3 tDg9uK1Dqm5R4hryaN8rhZvJaX0ARiwREFvI7Jv5s+J0AzUR5ErM+OcureUPgByDR79h+i5iPigZ WvUgOnkpFmT66EEAfWkhD/TWDfRF9W1YhZuAVq+TgBxP56cOvELUP/y9uAUcSef+VaONns0zjcoW nyKdSSXtU69rcKr7WmAdtcxb55wFjgy6gOHWO2dHuI/qFcnTgUAxt7UprLyBLB9zCgIBBsLg3+6p rU5YU55K5V+09iAlylzHuNaRTQmg5vIzwD4gju3GzXqPxwVvPxizbXIoPCc62TactvchpgVyCLRU XoRcoUqlnyVpFKfmhLsRE4fz8Lu9aCBVkBTQzgShUMDG88IxCSSexsM9BXPKUFH+gqLN+i/0Sh5u k1UryG9fuRSZQh/pTHtGt0BVRFvzVsUDTA1Wwmys5Vgx9pPHQ4IPXzhxpAk4Xw+KhXVUeT39x8g8 K+30WANvjvg7J6hccP0FAdgglihccNS99ymg4CJjlRnSmZkNMSFwVn5ApPMI5xVOA1C8VOQ91GEk Iqpj16QmgTrHjOPHCw9RsaZ92wCH+ohCQVSIlz8PY/OTWny2KcCxQnuhtA+GKCCLPmQZmXVQ1x8Q Fc52W+oorEqztDZM/BpJFhB11PyQ7LMOCU7P5RAJ//4pFz73nmI11RLimnPbt7q6+Ejrug3UfBif wXvUvlBLsJxom8VrKLN4bVd9sOPKA0v/5A47gzlwJyE03Z7AYMBNbyffnKMzy6Ylfy2ESvoui7pb woVGajBnf8ZkGpqTBj3yFIiFHYBo+8VYPjUnepdld+cnNO5/iBIiXh+yvFoAIZ2gjEEolrRvzXyB E9ky4W1EfDGt09wq9VKV6rgTZa5EYsT/lzGyzSrrz/T36mOiVSu6Lp6GYuqZvgOvrT0gjD/0MNRg p/kQD3sRK92TTzToNSRfRdj195d5k6qsJjiNppmjUc/hSaq5r6DOVk80F2NrcnJxOCRzbezd2BhA 7Tc0Hr4psgFVP2xh2up3/PPSg9uf2mBEqy1hIoovUah39qcNzexYypRXkmW/8eI19dAEsaMK06A5 2qH2klzncVjCyV1bC/GIjDs3u708GRNV+WyBV/A3nPPDQskzZFSuQUZKB0OJ4iCoKj/dcw994g3n Quht0wQgE6NTIMS+8V9JPnqtrKwMXtKKjq4wc3m1BNJr9u3151ubZAtcmvumQTQn1LFyYy36mCjm sYT0Q+4GIf+YRxJOvOlKAWwPVJ929o0/ay3DDrNr5icFS1hKsx92Y0ADbKj7xeGchKuofXZKlddk uBDHU5Pt+AdbKiVynMowg0YsSPPqyxWjItagGDU9wqvWnUPFpfoLO1eGYE3uIpItqJ3Yw8SwvLnO S6GGkvyvHujUbkwwFVKt3ydIdEx4LX7qH5qyZ9SAhi69ZrQSFyIMgD9R8ASnKgTa0Yx3XropWQid Wa4OMSBcs3Waj0mXTFNTaYHjfRzI/s7soTf+8lEdQaKCA/KOnD1kEbmEVfEf1kPJFFhjoEW3MMMQ nlGUrLZcmPjDJQE44pr+hsVLcqreMGe7m4y0ci2yK32K/i5nWH0rHDsiB5GNXdLiblgZMW32bAVX J/W18ZOvEeTmUSDiaDmnSlpuHworxo1DtElTRsGZ+U5371NZxNqaEhzgePk6IuM+C4r8MYdVKAaM sfiv2pMtTtZr5531hPXP6i3O9ruz04yPXaKYGeJtI+s5r6WjeNDzgkzeJ2qKEy7IzktivIc92yvB E3Rqcd3oXVBarKpXJl2rZZGQPGIO1fD5K+0iQ/3x77sbqlP8jpe/lG6K+xxWONNF9HCizVHqjnuJ VIlXkUz/h8hdDvFcxm5ck+QuaNx7S9rjAB4cWZ14n3T4zbr56J2E5jA1Kp/il7B/St4hIbjV0IAH sT/eYG3MZXNyNWyDG3P/rM4IrQfEhJptyJSHNdskXQpmKMMXc4oxPJszdK1KFtWpANqYutVTJx6P qvO6ChL5xkdhf5mWBeokqrmHlesf6u5atd1aBEQtQQUYtcmCXYtnS8hrHt6FUQnISKifRPYSMMS+ rRTpHqS11Ch4Cdqj+S/BS40wfRaZb5go5lBrSBAavEH6j7ajGR4FZ4InM8YI+NydFHkOgMt1IumT tU6yI1iQr+RF9ZKxIwXaGd3RIGWFyDmXzlE5EFU62waZF988Wt9DL/dtC2tkHYIKQjDfxxR8lvQz iJtlVDI9NfOK9aUkVsUxRhtmqUjminkON5eNAX/7UQ07PZWjPtHtdxjqLi8w2AFffAiIe4cVCzwz xz6AoGdsNHOYYvPAr7u3m+cmXRknggwiore5Iaxywt/yQK2ALuArWY14Ho98h/Dx+wt9DmnBfedH 4wy0CcDe/VZSvhzIUHyFYaTLHJSiED2KNkAa08pxahjL5mTfSfMPvys7dvXHs3NOUXuvPY7OwPqo wDbbM7BdymoopvyOi6/ExwH+eluuD/59yr7NGfSLJe6OUW47IyqAM0rfIhe/LGHDF/pl/+PRN9Va 7unDx9HyAgZkW//FWZUbJP94owTpzMfbIdcnHKzzf+4hg9nMkHJg/f0yf9zNH8kVlZc5FC3K1Z9F KHbRbiiHAy5IkBAez0HwdziGPTXPupW7Nh0MKLWgCeofaQCGcIs8DROpjTe52uqasAvvfTvZ7X/Q TxTb2PesStxQ0sEYVDvw+XWnJ9H5sawNzIZlIcYlkSgi2M09hXekJAlV2Hyc6wspS3XPquhw5gFk RoW+oyywgzuNou4J5I1VXgqY46sLujhzjdBeGGtxRUXk7K7rLGofqtmgiThgRWg+lSOqvMlQu7UE 2/zBJyqWwyo4IB30/PyYN3RfXxcfmlvLjxdffMciD4/KF7+E3y9cwFDOKmxiWLNANjl51Q/XMiR8 oChWCXVp2Va0s0Kwj9jY3ftpTIxuILzTU48iGXb1UVMYCnup6q/iroNNfUJN5NG8X2e7Ppu3jZia ArKk1qqlw6oB3att5f+vdFUW38DuMf3whg0oIxjdi/KDnQyxFmB1PgvEQwqBWohLRNAK9s2bV9HA swWL33ed9vU6UHJv+ltUzIV3XqATfnAa5e9XFcCSbAxgLL0i0GJzTuRDXTPx3wJNU+4khmn16NNJ BOOBoRectOYrGOcThufHWDkIcuaitqNudABsrDQDcvnXxNZpLtRa0eVghEotTd9mJWMZMsuPJofY y79KFnAAdg9SScBnsu3wsP9PkyeXPw0yqP8rxp4ivTvpANu42TkHbHUweFPotPJ5mTDC8BwunpLH cvYbwVopxkeb+m57/Ms3/cGEaSClBLU5xqxawfyBdyYF4TKHr4bM61KNmOSDEzRUhDA+MHn7+20G iLvhzVtZKg+LbOPnxPe0wSjXhmCSrb+yBH+knw6WYrVA/K1b3PY7E6N2WwOj3rc1QluLnQqtKQKT CwVQVcExVZ0Ciw1FMZyd/wOvJOVBx0jJuIkiG+fu4lZarAgNq33I0Qe402I4+2Lwa2nDMQREb4FQ CcXiGA5yGhOn9by+ig9OX6PF3pFeIswAOE+3TVBksMwti79ry2hCKHIueNbl6Oi1rwb0WWTPKC4B yTgn+nvXoQxMlty0INZe1tOmx1aGXde044l97ASbXwR7eKX48W71qfiY+OHNcVTLF+8buBKoKfJX zC1GXMLtAh/T1ZrcSkwrfmuhI3ni1AcqQvpzF9QDnrcaPg91zGT5nX6lBLgCBreLQ1aNngZwEXxT bl3qKDOmFhI4acE09gS4teJ/BFE3KOyHF9MQppg70P0HzSFG8taJFVnuTpya3ubj7xmYALpj/r70 MnIRR1UTwGCSwyITdX5zUFl1iAVT/hq47TJDBbiYmcXAThiIj4VslyiuzJL4Bx+xRXziMAi0P9rJ rza85CNFydXT7DUwj6Q+o1K1tpJWnmjYLxsP2s7jjyNNLDF5SSYccH7eNvRgnTD/nz0IaJ0GPiJI AIZk8yY4iLw8Af/lgpWeYun8TPwAHTSl6Jo79BzQ4hd5Iy0Cic9j7SmOsiDhNwHrAH7zqpXZyGs5 Ac6nGJwMGkblN4o2DAaz0WEanY/+aIa5D6Oq42nnRvc0r8HXlxF6lwji/68SoO0vE0DW4cGCM0GU B8B2OY6FlH9IUcnAZ2xhCI0dgM6fh6OZgUKcx/13SQ2pTeFbgf8hRBLtvKxrZU1jiFSxnMhIHr7n qdfRzi2RSkvdoiKcWdrcdLFqV6ej0hLzhtiad4Z0hTAXNQE8VaH8onDnx64iYJyfZgHRcuTx1+0q kcdsKnYv73AXKfJhCgEn+m3FcHHCCM+STlSU2GTzr7GNKTGLcrvzHUKPYvP5g3oOjj/CJAwRDyPo 8x6ud4nyNDmQAxhPLxxEEgIrNsoNyjxqD2VyEpJjkpM4wKfuOiKMgukEOdS7vLh8ao+FjQwy7p4r 3C7usZwVBpN1pJ1gMJ8DWfuDs6li1TbCKIkz2YxCLJOmheRxIIOBeNZbsp6cnnQ3T8dWEMmsjDBW 1oNNY1tPapEFkpPcdIn0nyK0JjBdnG1W088oTEubKmbgP7Mr6ciwDA5TkcsMzeGdOfkbFV5TARUz 096CYTAa2jZWHZgXPT6coRo48WmSW59nPHS/Vp0rQ/AhcpcdvW+sZOc07MaDCRa0XjJVC+txfOe2 d1qRM3TxbwMx6neXbk83a5rj168BzuI8x6FiCO+tpU6PmKadYfYF+eZOs6TereN167S+14ftxA38 I93AZuOAkCrF4w/dhP09ucwPptTbre1dAOM7znclFeVnIQ+ES739PSiegLyJUid5YNFToZDaideu ZDdUN45E+dNNXSnPY9z/hol0y7qTLFgWmFe0yLiAUKNi5Pzffa1Sc78xNRzUbHA8pKA9NP44dqDV li3IASM9wl7vVX7LFlz+h84hElhXhzE8cyEGQOc2uA8G7KZFPb6N4gqoD5PYgOvzImF/we8qwNSM 0t/VQ/0xsjpoOpNAzx5gXswSd8xJ+nd9zefI3XJCNYqO8g8KOzrvVNIG5hwm78ch/Y46L1wOJIsn OhBDfo9z/oSfjUXjXq+hYMd4OUghnJbXtlImt/qWX8i/NrKDhTNsOy1KgAZ/+KoMTqXgLL1pp773 cp5oUkaGypODpyD0AoyYmkdjT4uz7EnjbF+wxNQ1RBybegrEIcq8bADPE9L3QWMLFCO3yBrV3L1n 03PKhHyx9DmQn4zvlNWDVWxgAp/rCVYmoHBPb4wng79l3GblgPBlWN+gNTilG+yuL2Opmvl9VR4H cir5pVSYQyMjMFOKdjfPB2pdXee5VH6V/5nuK59bq2Me6HRSEXZ5GpKkNcBrD81q3V/ZqElCf5Qe CTUHv4OSOOiparL5ZJU/mn5VcwofHNT9+UhstOAwxRiYw8lTwsSn6Cei9+Vtqq76MpMUo4ZHyw2l Z555JBXGr3CQ0Ac367GOio7MqmEPGcEmUdHO1ntCYy/jktYhIpgB2ff95N8+JJIpoCb80tP1oC6o +Zr7TEkR8ofbimhMNf7VKrWZ3IK0nVfU/QVEstBuGicuA17EXJlv6qTHbJvSfVc/Koq2boZAjgA3 eiCdPMWf1uSeCbQp56nMnN9sL2bd5L7y+gyaKq7SZSwdkb+HHqDO1QKt0mh51ohrhvnRPY+yLYLa tX3TCMIJkqz2S0VuiEnMCMBypkh6NGx+8xZnadRTnQXd+VWYO0vLGagr3dNgKk7NUVYEq0zZJ8id xOCyy1pqh3Dkz4lRK/jrklGHWAwbvtyvIT7LYaTWwM170erkcylAj5DnY4KgVox07OHUIGQS4lqU DrXawaa6eTgvhc/Ou86s9hHx6ptT8PzdLw11k0ARFtCAfUU6eRplGxWxIgQF/9+D7aujs/T+Tezh c5EFnM4zCfx2QiIuq/rfkwEb4I1gQJH38yL1iafvEwCTqa8DLkGIV628Txu9m4P71dubkrjtZdcm ikNO3X18h+N8bYmS45WipoTejfMxmb3dYnlV56EyaPGR0tWPuGhkZKEFqVQ+6iy/NxTU9E110zbA +LymZi1CuZpXcDcccTvXmXpTV9uM/eARW2anI1XoGzetq5h1qTjLTAljJSr7y0PPHduTGMYvYuAL DaIWVOntbS+hDAVr+eSbhv1U6j/w5ZHvod85s1rEn5y1iRxg3HIxvmFH/5NGDvXAqKD5fpNAGd8U tRNMI1JgH/ygEnKHRQQltQj+QQ7u+HcIUlm10oVK9etKiZpQgw5opYrgbEoyCAWMy8Szw5Uky8YM /aHHTSar5wrZQoOwt5iBlu+NZBf26q+mJvVBH+NoYOBEZj/3kvWeZym/NpV4dQWra+6+x+PCKiVV ecoh2+sb9kFlI99G/GlAHIJhlgI4Sz1KVPhXgNHxNi6SeJNt87D/m8A5UYsgLvpyGn5j22omFcKq ZfJO5PP5ieheO7i5xapnkhUqG+8SS9LtZmovBewk9IVz7Vum8T37lEDHWMDop82fe4H6OiUvwXYh vLDxDJhW+h14zy3I1DKchw1jh/47xpezYqsy9+22AI9qMw+vhd69IomtDiCTmbVR2M/lv2BIwKIc RQrBjFYH/hK8eJw8bRxruUdKLPADWFWQBqnFNyXm4OgVQfO4GMh0av/jFGPyDwGFOP0xrW0OOXK9 y/mUw5aB28L/o3b2NBJaxLe1Ow3iC1UktrbZKSsOIQSsoeoTPrAsOHyGgk+E4dXM8G4Y85G8OAxj cCbc7b2DvRkltbwlOK/YnMwOu8ME4WR/kFX+B0XdJfSCO+qHEzfxGu+n80uYCINMtwV85pziD9V2 kwWYQXVy/IR1J7vIDsG0R0b/IYoQnQ+4t+329y7UiAdsiHw210nNyxJkG184YFhOX6z+uKBdLtf8 5ek2eOL3aX3oAROxdrCqAIoY7meB8lvBKuLaQWMkQLGFJxqFjVxUo8SL2LSpvHAgNhzp9Su/+ZVL 0SY5AZJIt/4sbsMXkYw6+dhPm+Q00px/G1e/zUdXV2HMq75JpDf6uxHhzFfAREOtPhJvHaU1/swG k7H3KFPBha6WX7+JnQ9DMj5EdRFRZV5A6592pKSt5Dl0otwJ9xkhauKBDhXju99gRQJbes0pzbAj /xXGfhtNm6UVxpU5CJGNAVehH1tZV1kLFwnbGJyUREylm2tltMW5naEOxMrBmpolI+mTY3wQsggg UIs7BmLa0QpJ6hGcDwCqxFSI5GREy97/XWzPtBkUI6ADtFKCXiHnJUcvWsZutv6wIXLWAFuLxE00 JeCU8ksO9rzBC5po3S6rF1KLHDnLWJamXvBshrVjo2ug1Bevcs02XmOSBzR5SxsukozYhEFGC1Xo SlExKw3HEvBOkz12i8Bcq1soh9y0z1xK771zl0VVdwT4Mae2OcsFl6tbzqMBJyPB0XqKvNXoPNwF 55hlQtrhvtI5put2UaVRKqyXXru/101BFsBUSmbSKmBlLcvBVGfru1/fbqhnaKzmdMPbIJrIuLVu 2DIo2WhF/rnOOzcpGIs2gTgZla1QKNFR6Bmq2xQscPSv5Sqog6sPgwB8FryhcJ4Wn4sN1+CmkIlZ VzbBtRzIrWK2YQYF4p86N2qsuyvZ743hYtSYG2PG4bvh+f3SGsTDHGWb2lUF+XDApYc7b6h9Bbr5 //YZjTsFGPOxw6XyaNGS5BJQCaMZe26DV6sOWmw8C46HN90McgLqpqpiC1SdT0m4Vi+4MSaTXwuy iTIeEV5dGOnqxAzOMczNhX6vIU4er07raNMKGCwACEa6EyUmxQbmw/nWcZKSrZT1HcawoRNCq6o2 76NqjUnqyW3BFqyFtQ7mXdj/W0xd7qOwfgQYvqOwiR9jDt+Q5ovMjL/D11s4qk8cIfPpz8HAq2g7 Y0neUHtxseL4rr6CR0n04ALK/NVD/IK9qha89vrjcjiBTcuohJBMhXBDgoGyGZnNBVxail2wl+o5 Hi0wZ834tN7KJVIm8oxn1jbcXOpRQUq54p3sd6UTYGwhIjk+NJKlEc+QkEqn5v316uKzTDw2Xs4t 9mlAIG4JIoUOkqLfSfrVNvkl1y+S4Rp+7uNcxjSiyj2Hb/SZCsPQPp4+io42sF7J4rYyLzgDH0TW h6ZvKFuKjjS0kSeQNg7WcszodXgHTXS6LVLvAL8mKarK0EOzqGdDAYxwb0K+OzUMSle88fS28Vpt 560Jga3UzQ2BXtir0tQlEk4tDKfIiL2eOxQboj8Ozj2Le9SjywRnD2Ig9q5YjyMeGU5QkfTL7Ra7 1tY0GVeHTqQm41ORMLdQOIed+MrSD60P45oq2CuVafqyvAYV/zroRmVB+I9X08vDlYCSb0+ipZNU 79hnwJDaKpCs+BG/hEcPAqhN+XYt1XzDwgyqhQwmu3v1i8VuuDGsofyXiyE/cPyGnOYepClY6iCl oCXMCp250WamsV6qB/gZP6OUSPaXlYLQ+tyjJCL4TvbqDx97Zqqppc1v3NWo21XLt7FZ93e/1K9U ZM3sN6ay9KxIW74Tsp9MC91hem7yAtQ0bMCFg4z9cb5JQKEO4ypv/S1m1WQUUabnd2zFnEM/8Zot zEBeAZBq/wLjycAHoTah/niFva/Cyz+qRkT4mJQROdrmwtmjX0V6p/n4KcAjXINfpdsl1Ca4/eCB 9UpO/4FqvYW8RXEo8FWeUO0bolkcVTAi8Q22GZzQjRFnRlBad4z6O+ukI9CHvVCuklMS/DRdEHrV XEcTYqCq+V4GX26wnNdj8htAsdL1+I+lYYRoc8wbatPiurWxUoI91UeC37Vhzx49Ir2zSSkRu3WZ 3uaI3CzLVTfPUlUFOu8xycWODzetRMwpIc1VyqwW9flYxY4H6x073HbFK9+4K6dfpngp2gK4Q0C1 KjQnhI5HbRf66RBNYUfbsrXIzSnjBdPhKq6s5R2Wa7FxUWMYvkj0xiBNXBlfOz+WywbkaXeBUSnl FY75dyFYY/k3+y6i8xGL2MadBPWElxEB4uZGF3M+wZ4g31ZLYA5wHI2cVF26BN07MQdinOB7/bXR O650SiLmFvVgu1w7e2piqh3xyoumLlHGrcAC2GF7LW2DhlHCqKzUDga2YoOVFU4APYNrMUHy+4dd Va2hxMsAJbXqiYX3y3SY7meXGPcsAPLfXVRMUmH+XYTkPBkOqPmRtzpGNSW/LCfo3dd+fW5n35Fg g+kw1vtdVTt8rO/AIVfBTJymzf0Eif100NoMuT1WqC0EYZ10mO/GW1CanwOzrO/TOlCEh5gVzQNb aVvBZzy2TCWafrrrrPkX3sTRUp11MKvQT35iD6JMuwwbYsVKP2xe2H3viq+Unr6wlJtViCUyFjSJ oV0XllAj8kez3/nH+XnbdXHBU4yTVNaEmojBrcFBl7t+ptfj/iabhPW7KD8p3ZDH4+JIBgUDi9IN p5UP98+apRl0DlxsL0Nb9SuMJtBB2LCiq6P1iwu3QSa7AKy+O5SNYhSujo1N8Aes4zefNxJ4PIFe JANpMKjCFwnGsYWhf7nWy0Do8errjhXoEbfzC3+GGRwV2dr/2HCT0aTKH/VPKR5Pf3xm8cpuLEgL 7wLY1acuqwMzyndPcpW5hqRrrKvw9MnCuJ9ri0cSp/OfNM4yP26squ7uPV5FjzaoTNQ/v1YfhzSb Yad6T9Sgxl7/z14L1uwB7G7mGGns5J0cQ4+oz0iLgze0f9EXhAuEjgxgjaonALh/eEC4hbvy/N2K bOhiytfoHRLktTlhAUIn7iJ+ogY1Qyf/115uoMP1V2T9vvBqaLiPJl4+pWVxoGl6KTStWqiqsBgL b9H1Iiug+OxhCX8iMykgRAcyaCWOxT5kOjKvGfMHxqdbBfGshJiW1MUOFQAM7Bn/MOJVjng05vc7 SOymE3bjNCVqAOGolLUo5RY7uiGi/Q8JUS2ugdZg504C6Qague/GgRD8NHnmk1rQmcawl0tir59z CeR+ocFCkS0a+oMNtY29U/W83gdcXea02HGM1e7sMKwqlQm5ukxK9KxhXQK0KQOY4pBucsrt5q/H mwJZRXcP4hhV/Bz6HY+l0j3M3xyfUIFjdlGbYtuEINkVNevlJpS30X0WkRyeGWZisLszPhL8n/Sz cl2I/irGjXKVWlFOj61U+TpiM+6ohAU8K6z+7gWh/bvIAYp1fV+ZuJ3cAC1ID6iU0IHrUnHfI/g5 RLJZG2POHtdq2L15fG/NAQHSRO+36zfBWf2rIQmDvn3Zz82wMd3unoyapY/MnY+ktfUPI9kPpvDE +p2HGNnbiayjnSe6CszMkXHUOdg6qrjv9R8SfUe8qoWfEZBEzhm59v8hqPp52jfSXCvfN8o6lSSE tb8DoJFRvjWuEvp1BAUPrWTSXa5PMBm7yQTSE4xtadxKL3vyhpr3N0F6kNkOho5cJzpeFjjljL8z EQI/VgwPb3ySDlUFhY6qqesCwNSTJxVuKHAOyAZR1tdhONtA/u4Au6OosP/2uzhAw9/85lgeR+Kz 1Bjz5mUZ9dLvvhbmOqTkbiGtc8Opau6qeK+0pbq8pxPlOmEw4xRftuunH+ogWHJ8d7Q9qK5OOjQ/ K3FBs1gvtyjCSOERDuPQxutjxe3nyvj2mCcs4vRyBlolXe2f9eIFeM7b2BXl7KsquGqcuhEopgcF RQ41hpLdV5QSGKalmTBIFAfmq3VTbXYQpgmLZ6Fivm9xcdTHGfYywoEZIVN/aWCZVXWjtEodBwTC 3XSkVpOY/1SFccVhi0eTg/ShIVgqML+gcTTvDuxLrYJryd5xRxDLi5rRmwDldaNpi6lrVO9Rn/IH 72ctATaIcOyxR2Q0dEfa6pBP7GxUdnHXZBdACNqsMgawLC85yJenvrGOtzkBAi01ztcvAgmybr2U 46idfRMqFsA2ctzPWZUkDAQM1XaPqOUJ+SELvqP4gR6A6bmgi+hSHfMRGn70Cbsbr6a7eqJQqj/f GtfJKN2BQwtjSA2hwgIA0b7NdsEGnH6Ia5++EOne5Mbw483I3/0D1QO3W8TEknNMTB5EoiotKTdz fSqT5xppxFEmlPn9mjOSksCxY3fT+ybLiDjXrBoPmEzyGpvcyubCwxFHjvKOKq+QMkDFp3MEraUg Lw2lrGxTFF4cBJUARC55O3PwgOr8Psu0krGNb3oTVeS4pZrbki81N4jKrdedp1SoL0LPT4V1PgHz EtOovwIh4Ke75QhXebQ/42EITlJUd3G5ypwyZnPP/+8YG5gX1oysWv1pCK/Vwf/lv/TJyeNqdx6D 5tSdgY6lz9SQcD2Jy7w2ld3WX9MxCT2urR8NHG+/p47QDBVz6qdEswDPboN25sK1oflz54NxmjIp xPPqZJ74VdZTOXpFb40S9OFS4VKMVF8SFnz0UXaGu4lUwASjxHHFBegDKEN8Nq55zEKDixzTzu7p wWlOACXRgMNDVrrF+kpcbRBTxYDmRAZg4XYlHx/48T98ZdrLTZTFV1fSP6lWsLiKMF3UNnG6HVdA Iodxf9+uW5j2Ied5kWAQ2lIqnYAjJflXLYkWvrYIdXhN7hk3kEx4jLrYSt3sU+5Qs5gMu+glsLH3 778N+xFBF9f9BJRRmXEb8nuChVooVXuV64WUBeM2UTEa3l0603a8E7VCwTTDlNB2RmhXpo0PrDBD 0Yv28DdAj4mY+T2jGjNwc2jy/TRc6k2ODQ6VnV1SC3gWgHT8XT6QQ7JfHVjjGMB56b/S+QBRpBTm xtrsUk15k2Gla0C4byZ6K50m8rmKsKG6AQ8+9WT2Lcym8KIdRIM4RBpdLqXLaazdLOc3TElE6uLh +xsXGiZtCgBXnRIKrkDw+M2La20Pa6T0WofjGcv0PcCFbVlK2E0poNrcOEvl+RKns96B/MFwYtJE ylaE+DuZ4pwMMhGXVsFxwYwpL1xyWmNS4CSIB4X83npk9trxoXbkMPRFX2P/vqo8BFP0NXsIOpMz 9RlYJvseY8P1+TQ4ekYpu3hEjbUHkYvBOXV+55XetzZUuaZ1OYd1X7gQjDkg+TLSXX3DpHBgjVU/ t9B2pd6XR5msRFDyqI6gPoFZeyV7aFU9hlg0JNWkmgVlXjagt2JWjvnIi2jrF42al+tyo945m8qX 0+PenLxeK02XRk6XGPLr88S0FVtUGlByGSAQUs5b4eVrApMI79PUvU0KaAwN/Kw/zJfj14Yi6gzt rjqffiSTroX2SQXvIkwhWDmwxXkDT22zZsokLgTgC3huDvAeEAbx2Ev6PDkAiclvK1mbSFw3BK+k AI0GBLGQa/qVIikipRsQJHZzHzbPdquQhg1sRRIXfkX8n6SOEiyJzjoyaeF5Ajh0323eqty/JsBy 8unlMMVslxeqi8TlKvoOmvXbh7WIfk2Y5Uu8VFBnmHphGT2pHYelHCpSMV4kDeIJiffNEyHxzFeI 6GwI045ozYtxO/fYmterqt+3AzV/sPE41m935of/6Zr7csZHsvb8TBqrLv7dCQ1FnD0DeLVLKoZo wr15oFgJsFzDe3lQ/WReBmzXroM3QjE6q6G/ckr/0/Ka2Uo1Fg9hs4PLPvBFgxPyA+oISDBjXX5a u+5PG0+X9impRIEUMo/BIz/OAJk4st7zEqOxd3BK67NsfMj2uOuIbVR1QffeTpBanH1mQD35ARGy kzM6f5lN2VnrSmSirtCZrSX6FL7iFsdzOYh0LVV7IxSIqY/0aMgYofBTuAPXqFk9HarWesWX2jt0 5xSCjXkiJ0nbc5o8JEoFYI5gC1eaDm3dbkAeYHHtPbZxV5St40t/AoYx4OdxS2vRh5FM6WmXI5l8 lofpR0yrrKmmrcFFI6gxYRDUZTRe5TgESlrFaHVTiNw4KQi5TUDjBfSa6psMm13f/ojHf2tkNM6G xKFI51yRRU+DTz8oOvOYX1AXoVrIdrejzkLIwjFB/qpfgBIY9SD5JhhF/cRlU2iNoN9d7Ba4Yd5o y9KkZgy5ZQgv9d3Ojq/Tjf08g4f766OqjsGU1cExDpsZuXhqoqOH3vMdvMXexHRlNIjpf8bCX8Ni Ucpyp44zDH4SUgoKootXseid/SsJ1/pWZXECsgc3x43AGWwwKe3WIsoUm7MQmH6QYAw6oxyu73MK V2BivAqPEXhkummhM5WusswOAMR5GOwdt9ruNGH9CSqUO/8lnh3KXXpwGzVMY1sRlSdR6hhpGepY OLXnc9dKq3mPh0eVoicaMRqENShApuRL1sZXLpE0l/pFRWOaLYM3c56cINOx8DTsG+evcxbZBDVm WGPPKABP+Oal8judphDxRkfolWSX7J0A73XXhj8+bMd0C7K8LCcU1Sxi2B2YsI/u7v5vN9bPGLS2 ZJrJR//lnN1OV10+GdHrdf2NdQ52mRB/9W82l7OmJ2JfHZjsOq2ObPkgfE30641Xms/HlDERC3Mw YNlvUKNAM3ZgtYVCVAWg4JcPhpsm2AdsnKIH6+PioR8N3L9h4mZFp8cqfTw3b0YRJzxwBlObNYYQ PXGUCWyn22rDa7H8h3JE0UxufksZDVaWLg1uuPrVmjJQMxlMPa6JAnle37j6ZoVr7zb9q0wVaRYv L71reoUKqgv9yiB3EdrEyuDDQyVx5hRBTsaBc1JviPL1zYo1+CPQJOwdkgz3hxwwjHh3w1YmEJ/4 OK2cvDRtqsY/LpRGTYKxJeo5eTvW9U7NVEARqZ1S/mjupX27maUAUFnpZMlb+KYfbuWnZLC5B/Ra UvIruUZkzQlLg3zkm5TwiDF0LW9iU8687CVJgn2Bt2xjqPUNRaw1IfU80XrkDcZ4CzCJFDpaO+nH Y6xS/IbfPLXmd/W2svHOImjU2GkJcyhr4naqmpbe3nZpYbW5mKtyzEjirgQ/E4Jh89oY0qLvAO/Y zr7UnJO80Jvw6QUXE2VdB/C+23aZ9YfONkmxx9fVjszAnIp0XCssPj60vl5LNVoH/E0TO2iRyPb1 TdoZ+VDnXhDanbSxEXlIa2wu4KBax3SdzXJ1y4q2k21+Uv7nfvGjYr6aqugkcrKy+2hdu+UsrxzN KlfElWDWqnujxELFR4QaHe+ofS/MwDksOqPKrTey6KS0A4Y+NHFfvlXabVcKTazglweXBV0MPVoD EE+J7VJEJKXDzEO06KwhOene4cw1HUQvGWZEm83eEigt8K7zgXMA914vOy3/AIfUvfitdkB7vPjo i4jY9KQnpltUeOfwndfkvL5DR+oaX45RQwrn06nMlpeEKpCyutszq6EetiUatYUTcc0NdE82PQLt x96rIACGV78X7b9OigW+Ch5alVjW2QZET0SFN1IoNLDS1PR16FfEL/Hs7mwx6uMdSf/TAXCGJDXv jn0w560mt+monY/xhUm67+2Kfoy+f3UxerqU7Z+IDS45qq1P0MgaENXcKsyVWFWw6nvsp9COcRQr lmWJNEimvT0j/zN7LkJ4S2/UcSoXT9oHP/SPPaCSp8K5a0X5ITtUYDHIPiewaGGwxQjSwvP2tzQI 4yC/yNkja25hLPjMwNlszya4U/v4hDhVpVn9tL7jNFDaDBCfzvK8T/5uz9rTB9unCpqGxzgH9STP pDZhh4UrjH0m91fYQ5b03jptfhoGxA9M7HW64Z4hkd2oCcyNZpULZ/4bGKt1740VjeUUDXzCzMkJ RDqy2fhx4a7BdXp4aiPx4fj7K8FHNn+Vp7eQGj1/jbbfQFDK3H+nG1T0Stg2IpdfHCwYgWcINK5K jp8my14i9dsue19rcf/UOt/NVrRHCgRt2LnpS9s/+KsqY5/9v6V4Y9LE/L31/IUrVvwu6Ay4eatr 5ouCRbH/3IQyg15Iz8JCb+QUP/iFdIJctOruSqrQ6KzNQdSIO97zZJczfS5mgdQKffCeULHM6EdD wTMILJ088xtZaHDVdP2wVmNyr+b5XhAw5T6YRzQTOhmef0U5kEzrmzPjF6j4w8EIEDVC4/QKCVE8 b0XKjpIfzcDCgfec2G9ei48FTaCfK1yOeMnB1FLcscX/p6BNd1ORytHOereNELATk4w0O5eugF37 gfl/IzpEe1rja38vNSOoMN641olOiMTmePVOqnemi05VT7Sj0B6CrfXjkWSpjT+EiaDDcjXnNH/h g6MihRIUcm7X6ZfDIa0ZYbo3A42a1qIlMzG3Wd3qdIxsCouZmMn1gE3f96VZ3Zl6p8u/C8gxn/En Hx4O5zUSBcIeciJ4+4IxDy6sqfYODQA0O3MnknMAdW0u/WqVHA+8DRFmbp1T5TDQ4RaYMTEbfNer 5noKsnObbqngKMHZIuBUq4BHqPF1GJZoN/exUZI68vYEO7er7hqGzuWh3hHfUhnjQa0CgpbFrlqZ qDa33RbHDHy89926xhKVeFSLajfnk1xqagt311SVMoQyGTfiVVPp06DemVJZtFPRLfd+AE8VNvwS b4GWtly0qsUgX7Bf0D4JLVhtTdMT3FPHcYh3oMOMSvF8QKn4K1P5dNZTac4PfmfJHXSyORLymGmB tN+5sjaZcdt4G/I6Phu4JC010QgsztJjM7zy8lF0FikmnlPySEBT3K14yu6G8GJm5vchRkCNJ9PM DV7nqKrmeW3ypa8eUT5Gi0ZlYWjtVQx9N2VhJ2A1qCBYiRG9TnF8/IEb5arGSdV/yqeApaOTY+Yz fpOmxol2teKHmp+bstN8N6tmKCUCBSnnRwyUGtrzXUKI/rLjtNu4A70i2L+f4nXO30K3gea9Bm9x 3SZXVd7UguWY/Mtj/RF00WKbR4TgpC9YepbG/EMowzsLjY52uVL5MQjUIotCIjBNxCvrg2drHFFD 2YAQ6K0lIZvIirmh72gSegGC5mKF0ItwDR9Ie55ARX7upelCoUhANCoI2+snF6+gMDAMij0B1na3 VkMq3OyMuhjyMYvunaAxoapSaKQGXV+ejSTF4l8s9TuzFuXEfyARMwUYpSZgvXVFCi8daNJx/NoN fyYsGx56zkK03I4nRXj/0df9M8d/bIhMOS3FBZNH1hJOxduP8VDTvtsp+I5X496hub4cZJNw8dUY DddRnLe5vI9kW8ghFaSPJ/wrmBuc/ZxeUwgctZWyq5PodUTXbuHgkvxCKr3Ep4h6XfH4jV+I6Msm qChnRmL+tDvLWNJU/NA4MgKu6mTmYyjIly08lPaG8ezekeKiNQHpCiQOAmyWR4vvoXXrNkvpzhmg Gy6tV0wG919VZE/33w3+KZatr8Bz9J6WS0IXqYbdl1Gv3Y3rExehATbhV9zbqW6OAetL/1aC62+n DZw0H0I5hpg2IDGBPeYQTyMTCss9zK8fZRxNDhw4L8ZKEn+o8INuFlIMxFc0Burk/z9HEhvjtKZd 7GsS2wHKt1hMZvMn1vpAZdrXqgdZcpYrWZWk4wGqKCn733NWljkYXGqHnZ29JfH+tA7CkIbKYAVk 1E+07vL5ngrF+GpZMrvAytrp4OSuTGY8yrHfo2WlUIbS3SlN4/JnH97+Hsd4l1owwSiMW1OEZs5T vVTsE0xzk0MXqVavpOUsxD1KbDJr0dhUPOe6Xz6x8AVSyWzUDXNPhIVHR5NnA3Wyeu/C+eM4jQNo +u1AAgXg8WoAkzLRWOj8qf7tTEpRHhfu7mu4ChILLtJvVVSeQivoY/CS4EYCYe5Rnl/5opDrOFWa YSz38TF8MG22imK2NCqjQrqFP2Dyl4jKYPlTDIh1q+BWZHlKcaDQ2IA1CKpHvqsciDIpEb+ZygnK mKU+oFujQTKFaUIjDlZqoUwoFruDCyD4HgEAjJMel56RtgcIWzYRpPbb+DuNZ2BanHe6W7GubMz4 aOE/+fiDB0yinAayjjBQcloSOmy7VhKCIn+7fKEaZ3O/lLNXkf5FzW+uCEeQbzoYDPGSigRrGLMO +wioCwIJEAhkAjilTq7YogKbCtJ58cJuTZv7d+RYy4uVI7NKQo3vfSgMAWF5bWrp45tkIxvoNwHA XQ3eUPZO5Zp3fopGb0doM4a9fHH+DtDdc3H7Q289jxK5ZgdlxsmxCCV/tPZv6lArhk+7mePgvh7F Syr1OulloOXAHUYeMuqbCM9Cu/xUvNmuckCIPaXkm6K5L9g1jvwkJ7/Kwn0Zf4dH5T86qv0EK+8X l5uZjmWAMZzqoFX8sYW+TtjXG/TNmNprvGGaqsR8M+XyIvXyqRLi8fUOr12o0nfQtv9wbYNiua8b aViQkVTRUsfxyqPbQEjW/l1B0qZKJ1NawtYsG5N/nEZOdJGjupzMYA64U6DVwnYGH94qCMhEQXen DZMpTiXcCykd3dfPnDeQ+C2senZNvUsKiYCW/ueyLLp/M5w8p5qMh7bg7dn+9SybF9rPs1WG9nHg Gdn1B0zdmOH+AeMBcC1w7A2jBWjy4QiJyErlG6Oeq0xomijfpXb1CcogMhTfeG1VUYyx1tM/tNBL 7qlgZUxyL/IVj1478z7ZQ3w7GwI191kzUahG5H7fcsVxbtCr18XrsZHmtlfFXpyUE24Ys88qqcGw Gngkx8Sm1vV7wZhKJJNck8wG7SznIRb178MJrHOD9HCj6c3VVgq4vM0798gORx7Tt3y66rIey9L0 BNTxtelBmHdQoL7enMf9xL19P8fNMSrJUYKZo1qKsmJlbeL5DJTMBWHnfFj2KHfdql6qj41HxEqe wLDaOmxkajcEMBUhOwZjsAXm9DKw5G5qqq338Kh/MJp5NBrrMIoLEJJaSNJ403GLNWAMh+K6ZZKx II6jtI8eE9SLZ3P9l/gHOxkk7pHdjzYpikk25wKbMAUePrus6kfnrYI8l8y81GxPbNfTSMSVJEod 7JxMUrkOyDgslYuwJTb1CZRGk8Z7XFHH8UUjI3AXbr5YnRD0NbMdotkFW95Cfrtj3cgF2K0xDaQU L+C8zcPBGk7qBi0PFuVxUU66KOMGbQyIm01aomobVaSG9EXIH3yuV90Bw4mFznRag7pP0xFkpj8X CB3lbCbVrMo8Xh4nqMi3I5PXujQl6eddyHy86QeXzOB9iPlVXLb0cbmVA2QwZgEeocQxmckWHM+H T0xqn4iEg0nZP8PaEvR+fuckgDSUu33PzVn1dImlf1FJJ84S2gkeQN30RKNBXFqK0GNwlo8iyHVx kboKHIHCX4U9KsLQrA2dZPx0kQFhrMDdLn27SYW41KIBZg/wQ3kIdpexcL1omO6K7vSn/zjaMw1/ i8PcRnANjMqmh7PNl7GKiLeuMswompPkzoBjd1j1/YY2Df61tNx3LTwNnPLpqyyk3d6OZl8O3yM1 OJxpLv6sRVjFoX4sABhl2vht9dSvwCM45rAGM+XgfGslwDnSmbxCNfVCfRhvAPrtIAHVCVbOq272 ie2jfu2IC2cBeTRHjz9HZg2Dc2TP41EXCmQ5l5U3Kmjny2frUTnNnJ7uHxON0zOXh5EE0urLES56 hL2yfyjOcJRAA8K5CzVAVot/ZmNP85O+SAxI4WwLJuy4YYdDT+8Lmf+LYbZCLggeR1VXJaIxbfqN XVMbrPVkxBxt+H+/j+cAbPpWj/FyzQrnVfZArywvNApbPPynifazyG9b+IQ7u1RXsDkWhRJ17cZg bJJX6sTjk/JA1S9btwTTCLHzInk8folCjXqCMmm36yebRrd9nXyBlJ9XrmHN9k8E6hlpx87uLsfQ kk4tVgzpHjfo3MYOk067nQE/kxx1GLjWAVUcBZR2Ah3QLsWKJBwzTEfdVSObFvveUs2a/A6NXVvh Tx4W+dETkbeoCIQjOrQHF/AlQi3tVnHM5vRepWl1LIXbEg+MHwEbLBJqf1yTjCKV3MXBlndz5h/d BPKngbyHCMz4aaLvpqjO12U3hcr+PDu7GkXcdpA5Z4bPNnA7wIPzt+Vj9JukjeDvMN5c4Tk+ww8t vkDSnhrWX/031229tqxHC3cwzEe+0+I0erDhFPt6pO+OgDwKsf51LBllQLVaLCcNFnwBOZf4/aqd Bn1JL6+aWdz1dbr+2s/7M/R/iS262qm+gHeQfWk1iyRkgxuDkefhl0Y64yZj8GlU3BGAXKnLB7FZ q805uxnEnS7ecsySU2ZE2N+hxYWwGdxxqicr+Psd9XvTzaC2Ehg1I1VWuOziNWJhup2NoZZ6VXPt dKKzCXPgsdfLNgiZJy1yoR5z9Nllmk1xvQbHGzLPA5MYXzh5JG7tHGSHRlQ/5vS4p8Fr6DH97yyL GyMofQgsZKrbfKfkVBFfQi3eIMeUAQH6p+GBbdMEffLN6fG9YE7znTc/ATWtGaOfFBDqEX4ZUdAh oal+OKbQ7ds+Yv0cSBTAZdC9Mm1Jjmmx4xYFkcr4DkADUW//vHUOD1/JOZHhxzq7vgI0/92LqVvS H3j7C1pV8h748mRp1sSHtgzfa5fqVNsQP/VIUxFsk19bHRmmHIgu1XelFuLuFg1lisOKXeNf3Ne7 4wegZITvqrZHJhj6mgjWZUlBkUMKEHjr/eWXrnpbjgi86mx5nHifEwu+F1kTYuUayxqWzJ2DH6up 9YUKxzB80FdBPh28qzzbXasLyR3X3CEEDehx/62+2Cpny4iBguHzEJI4KCgqk52Fb+gZ8PQcZPLe waRejWucwExgzDc8N/4Rhkj2qqbWjKoTXkbWJsyh4moabCssX52GcdbTzYiZY6so4lRWRj3Yl/iQ tQxspuqJBgJ929nD4QY+nshjBLk1oCqWCOY6i39lVX6p+pi6coQBOreBqzQD4JNlqs1S+x51vIgl BwDp3785T95RvhBHW0tXCpJAFSH9HKWhp6PnHKCSUXIVqKopkX5IAgG9GAnjEGqX4g2uL0NcHJ9a Ujo7+6/fLD05UAYX1XWhhTx1ABHdWLID8sycd5o4NrpojaOEMcY7oduGSNgY0o6M6tMcL9U7XOfw /6cH3IYiZMNk1PmmgfYARcoDhmjBJDlXvtBVSa8JUDsFRonpZCF5yr5QzK1GyGCnd8f2t7cvUVOI UcKFuu9JYi0MIlkEzOw/8jZK9YE6Dw68h5c6+z4X/D9DZ1uoFOVUjHbKhHf8QEGdSNMEsKh1QGMu 0io2QeSeIn8dU3rW6r9sSCgcnz24xEnKgckaXAKoYjyLoer3jx4m9wVYLg9DgcB4oLxSz1YrHSE4 C4083ZuvT72jkqXu99RmJqc4KmX0Q0qAiKVPvYalU64HMAZ2NDGOwKTpx+WWdH3p8/Ys24EU/ZC2 h8T82wah1hj1pcDEeLwd9G5W7gNOl8p2fuu5eRXeb8d/SzZ5OWRXP/bw/tDwIiWBOW4myZeTFgA4 15wAMLgtfq9lGIh9zTtTIN0Mmx57phIZnhbzg553jBNVXgIkv8IrcFUB574aqFQK0axOzVfYAks6 4WHbVgzi2d4t2vqkgpLnlggV057Q1YLbcXPkyw+clhUNuG8GZY3jidIk94tQkLxaBTLNRw5Y5QSV penNgY9RhzEAZSi0qbhJCH7DK/0WQRsioS7dWLdGQS6YZSov4jnVfXYezzY6B6IUTxb4kID3OGFw uiHyvzSX56A4wLJMXfV8H9exax3O48f7l4eQ3gaOr6l+0SQAu/691zLHvO4WKENK58jTjdabIgWM 7VI0DbuXQJeNPwvSq7ncT0Fzde7ZDFanEdigsmhQReuCSfbCTjN3mgX2QVjOakWJZBMJbVrzVDW+ s/8JkQ+O+Ht0v1+COATWGLcXq7JxBfxkxY54eNIZFZdN1AsLzsX6HU2Vt5pPhHAh39DixAxmjL+F 9N7phsF1dFibloXTHUjc9cgR2zrMK62/xc5hKs0LxsA8wLAsPY0xAg8JgSMRcI+LugNQE4cc9ssx uM5NWO7aGyTX2QoG4YPYsDn/ILM4V+m4c0LoDiyffn2lqX6oezuW0vnMsWKskv3mn9xShWl8G45E eHGjfA8HVIk3/EUOKr5UQCssa5HrC1PRSIDnbZeBpLxxpAObsl2TvIpPEqHGafDr4Vez/vGOPqyH x8CgALR3WhnJj88F+AdDHEp+T1Ot43CND43xl6jRcYWccxddUEpXuwmSwYot5nJ0cc46qqrFkJqM PZst7iksPk2XO1xustMjVLWZ28Bov1wLEqYhGUMi85QpQEAfKNockFi+4hwNf6KirFQJYfzwJCiW o2KpmTlZAV/7edLLTX2q3hQdp0rQk8gTiZXwer8NUk/QE4cc57neyrSCYUXB/LpOmZ9UH80YCwAW SQAnHm4KWFkp/eGtzzKY2UGPR2Q8Sn0yZ6u+5+oTG1Acmo/ZjJkRMEqfQOzUc+Xcl5N2xP0HbRcW aPPXirwaa1v5e4sSk2OmMnAGwnkjdf4RJgSxFpQOuWzKnOJCyVaLpFESK5ArHtwM6bueekZ7Lrah wFQeYy6OtCgUcE5LtqncT6EMxhjGq+zPPNDnCvE2nPRIZq3KSBvWdKzFL2kKBFWfPjmSlIrcRww3 K9O3wLH53oov9hRclLZjiGLB8AYQRntTab2tpQkP1yzLhzb3WcXXKbhdZ0lJ61uqQ4vnsIdo1ZH3 99Ynonr/EvcYWtoUwFNtF+4cw8q7TEvAwntE/5nOcYsVKXHmI29Z/xwYEXsv+6gLIVDnVe4SfkYH tXCU+dfR2lYxvQogPP27ARYhTBLYDwtsIG4iNbxBPr+rRWo3JpYPGV6Z5z4I6dvXJT0Pzz2L9Z8E xrxkSTQ0otMHYE7LqYKKjGRIusB2ScMYhl/Ipo9THhYE+NIOaLAA4g1ewdhpFsRJmZAHqvJkMLr1 Ji8yqtJuf9ETv4N31KygW6O4jK52OwSt+ttf/uO7nNRDKeM6eUefJgjPsKB/t4W7GJnjr6by/Hoc OzWerzfBdwY0P/UnS/oMSWr2eeEaEJGBx2/ljhA6RFVa1hCNmZfVC+iD81Y4BmhpG0yDtDqkxys/ IvRnIvVWMwB4smgGYwImtdqVrreOjgpFsbxBzOwvdJAw0r/bNxfg8++blQdx8koluAa+/tJPaOqJ 9yzaFZKz0ad5ru5k5uhsKwIrwouztkcLuNBK21LSQhyacAvb5YJZix4Ope1o8CLXVpob619mCBG/ eZB4kuPpJ5XZQcTYJ9fLLd2IZRO1qu9bpV3FpflGgZPKZmFRk6BalKgYvRAXrak56xXpUVu6mMz3 aQ6ymunSFGsr48jCfiWAy0Oo5fjKHv330Fqfzw0xSJBbZ0QPtu2TEPUfJk43JTd57ahq7zqhdU+g B/0IzZu65p9s2/pBo9Ux6DojZxyXLVzAuKHdYNUs6BosHv/oohRY0ipyor/ekWP53bXctzqtRUDo hnMaLxpXJHU+nRYhZC8+6rZI2UF+KGxLXEaQhYj27bCdf7Rgn1trgUJ24KZvdAbuRQCS1btbQim6 7IP5LX2g8LXYLEbFeR3XJb0SaUyvtC63Lwv+vCvB5HjT9NpKGLpSt6v6CUI/xNzYmUZIiuPugpWL 11mYBR/LkYDK0kqAdnEyUmu9ZjI9O8rcGdJGKU/IbUqYfvX21Lvywkk83ETRn5QLC/qP2tdHN3Iz dS7Sh/vZepSQb0m9np94oNHK3HEv8iKpcyz26jghTw95UNxJQncUGijkb+yoqSUj0swzV0LJd50+ eDOMJpP0FgAw6UDP1dP089IMEZuQe456Gs8tbhbwdUO7BpZXJc6yQZ8GBLKFDI4TN5QVCgnq6C8v 98cmxCwA0cEct9WZQEH7d8t56t7VXsIin0jR9bsIWYzuoZMtkaUXZevdaAWWQMkIlrlJI6Ri8U/m 0b94kiLOMw4tl6viGy1jJ0OAgZmIRbh3AUN6jRpKBvoNLZIW4hRbCZLlttvbtssUkgmgao/Mr7Q6 i/Kv50pfbEBDiB1Kx0E5z07OeJNxOgbFss4mBLEKg+kPUpymziRxHXQp9iRkvBRzV4mXtFtK8Vda OX2ngpNbSYDhC8KXrLZxldFgimr1LGH9sjcwEwlzWvahoJuXHU1lUq9nKv+RTdtHYRbjRHb27Di3 NbvhGZjQIIRWfaXOyzxn18uQ0LEcfn2Kg9RObHmAcqVWnPOQ/P9Hb1wQz+SzCxMJVEIb9dvbKODn BLg/oqEQYee/u0LYJ/Ndw4FWJX3BynqQCctVb4RFghHzDkhUiyToapRtuyCsx1EtODS8xFKpKJzN /EWvY9noVBwmgA8Zpcln5n/aInh+qJ9So2d4vWWt9D6kN9AboWS/ILEyG9xGzrNeELwEk8j3aztd IwnWETCtZ75t6jDcu+hyIZ7IlZ4pRlc6zgQ7xMClFKoYCmhsZxTo+eJ23YWcT2ichnnoMwl9oRYT ZG7j6rVTSYwFaVPS7x7qU4gc11Dv3CJXhslwI9t4OMQRkFoJ26LEoacYA5OF9TsAe4Ny+sm19H6N /TmbKZzuxDeThoCSbSxOyxKhFROYHFseteGnH1G3pPTHU8KGWHqCtttIxHpi4pbLJ2enpRqXXhsn m2fJEpqVZoSwxivXuqvGWiAPxv5Thlcr3PHfzHXmVEAS3sj3hNkaBcfUgiZMr74CQujhseTqRaBT 8YO7nP9rB9RbqoMITcW9l6fLDlbpR+UsKk9Klrw0IxOSMJjiwVkMR8172CuPj396j6Jkhv/wsYu7 uKwGed+uKVHjeisDopm9+sCsK1aPFo+u/CI7yPGAV4Vo5ASzQ+P5e58f05LU0EPTF2c0MAaWAEe0 oXAh0AzcC1x6PxBrFOf9ymVAFBjRcUK8HL9LoQJmT4hPsL/D5C02t2+CK7vTi8VtGwoaQ42AsEV3 ug4UvRBrhUNRdv8fE9c07HydmUCrU51jFskfVIzWsovCvSiZJnKZmAMUwPupSrKxCh3H7zg2zMu2 MUge8u5UWs65db0PURju2ejhYwKscyhjCMM7yZJMPgrSnIWhXRmSJW4hsPof4oww73OI/+/V9sqH ERxIiKN5MWMaYR7pJ+Oy4jo51B/yQdz7a0eyb/8kshVdtzQ76hCbyZ5Hz7cIOQUX/ZBlpsu1Gaxy DtwrqXcmDKDCm2oVgCjzWBzpVKJGSi+Pb3ZIYfu4ULmBQYR3fwJTVs+Kvtxy+bxu0fveapTLgUOV NWL/9mEYRKg4TAVmSEMeDu37zYVmBz9jo+6tNeLGuomoLwyQ5djs5EVgLScFo6kq7fSW4c5zpKxb HfsXrHEffdx88s2HgtKU33ETjTgWoZ6JCjebzsk40BsoPLDAX90jx5QqHVsSBWP0BrvZKfj7EJrs DE13xUaHDNoo+98wEaNfylIX5zQyja4c7Rga1O/hkTIraeEPGbOjotfCuWAhC3hjzdqLMNYHz/Vr SIfihemJ6wTWxVKYs903wlhy2DkOymB6ic6j4mCyLoNvt0niMEFHs+qg6v9UStPINpE8IKH/GAJu hYMNcGIET8OxN7uWj9yoCKI3JVdeZwdiSWiiZz7BkhLM5nMSLuTATO9DSKTNLTAU0/JdPY+lgeeF atOqFIi48XEEdU5R+LMiY+4rjTKV/F6SRV7TdMTOkc1GhE6laW1SmEdZhN/eRnO5A63SOKgH8bpj jnT2VhEXE+pJd+MRO3eYfHT/+LG8Ge9om9t6OoKTvDnY1XiJOF2Bydf001pKPQG/Yn5QZr+bsZf6 qXbzvIGMFnN+e0/BWwroVgEq076hqqiN5eroFAnaZfJaSW1KZhrfUY/8++E5FXOLKDEbmrSceJAC E6hcXWNmu+EH83u5t+3w78iod/haNSeFj236o6C4H4bZX/wZaTXzTHXNn6HZaBXMFGbClRk5OYQy tfvORDBdoDEeXYsJRlRK0uDGAj7W8SSQYrvYblvyk4V/7tQkf4JvaeKgy66ED23V+VBaeu7r984M SyuWOBSaPyVug19MaXL2IWwvFLI2cZHQxRwat8ttdmdRm+TI9b8R/hUFR3VhUFsnARETJGjFT9R5 kM4+I/GO/GooV0tdIgscLpPffFThXHlv4ivhyzkVtV5v//J2J4gNqsJ3JV0/W5lY4sYl9eIBzojK a9rZrmPBttrNGFzFF68I7TLEqGjWsNqYOaxkq1uVEOgzJLv2d1bcaHGIwQS8EqOTQDPQTIWqLHJB X7hsK/od8AMlB1kIye3zrdY1UTmB1Z09ZH/zghznxa8Aa509fzH1YDBNI34HUmx4u2lnbyNhxrSJ By668lGX8M6XUtlRQaXrOB3FSAAfCtKaYU0WAS1qPDQ9dl0chiNwsFDeYLldoCBlB/2XacD6oAg5 R5d8AgcaJ1JO/72h6pOAoGnZ0FyAEeTT2DBC7PIDXpCPQzcKjbt329bNxSab9FuCmBuA0zreZYPi TMuAwjHRpNl5wenttj1wVJCqWSrJ2+ztu4qlq6VOvYwi4KeqHpPxM3kQ1UkcTuN6McT5ocwNYwSJ dkEvzPFAGM0lp9j1j0axhUDDCHZzN1cBT9CE8lQz5zcoNsNOM5bhokjO9SGDiWHrCZ78qqwGMHIK wLXL72F7mW3iDiOqeqgCalnHCWuYViGuMnWZBd09VCjnir5/Rgk4I1h8zmxWg1tCzpykee0L5AkH nnh4LLubUnxAfpsSx9K2Xrxg5MSNmPRsekpeF+t1Tm1/M5Pu9RTu9OzkK9DGgmGUoOfNSf/z1N0R T/6VjbUXmooxQFv+GKQoee8GpHC75tliHuj017MAFM0y5dmJFZLVATwzkRBtsHzn6A1+pzgK2bBP FjF5MeHkv7385zF7LtZ3wQi7oMcL2zkRnEbH/Yp0sNUf1k44f3/MzpmH7xKjBuhqysspxfG2f/Er j84osFdw+PapltRadvU8/n3Zu0YYT2aj9Kr8Qc8odFjOJoG/s82v6wO64YeB4AmeWjMi6ZHMr5x8 28kGWyXghLMBlRoEBFXZGDGbaZT9MoxP9PMXNoIZPs+loTHWzqyxepjzGyP0nnSsbyjc+VWwUm+C Iox0e+gxybukao2sPXOwI1HiQ7IJacbd/sm6ZiXiHNid9yfZpZamMeEQY/Qo9nMACyygsn5HBby/ ONKIISQg5nVam74jojAv7yybgQhHPtVDn3E5nevQRoaIuk7UWZ1rp03cxpsYTy6SQ0S6ewznyOf/ 2EjkQbbyvCJNKqXnbuHt5p6hnbKTFUInqS6lLd5O9v1M1QV4h4XPF9mmJkbCxnwVO3P8aACxMSca fw/CJUHmXEGXPXExXawm+nBxioNVZlw5PpxCC9mCpaD7hSmMMI+G5ixqIxEym61eMDP7xbLqMj2n 0reu0GWKlFLFHcfF1yKJBm8WZU899VGjSxrFNRbhv9FWQCqRB3bs4d7wJI9lzrwk5AJJroc/nsNj TvMyewJfu9Pyj68OPLbJ9MXFRlCrpgyTK7gP5HV8SWpejDPrLCpB4WVeQ3am1rtGGjy8urmk6yZ4 11zdr3/umz5E89p4omgZ6sBouLf8bUg+I6EZT1UnCvqnzH90PJB2AYRz/aWWpIbDeqfr2aVYdiL/ AZ0ZjqAUJDmKr3R6O+bhT5GurfO6luDxjAsTiY8ms6Qs8R5+W8SwnuBcXevGKbLEyjce4lBVvamR W9VOdk4eOwMaZzT8LNmwhRIIdTtsOPqIoQjAJpz8n+9Jhw5mJt1MmddCwGRXU6ODaLyw5bzVk7ti MMb00TdTtNvDMdsbUoa/CO62AO8Fr1ev+GMpWga3gPOaP2mv7mVGydPcDodiTLkVwnfppwPRYqfQ GiGQhMiaNFdNsIMikBS08H/GzxWhJiPsjdcNlE/TWV5ex1hctxrMWfC7iBsRx5O8cTT8gftIfvvd VWn0tb+/oHid/5rhjPl7dYNg2tShe6n55+SB5XMR4yNUYrEM6VUG5ZSxURxvs1qwfNa2i0kHMCuo cGa+xffrccQUKJ98nzXCy7PsCXS7OHliuSfRcWo1esJjUGyDEPZkmrPh8Sv390d14OysA6uk2QO5 rcM4TvfgXITDBQ+1if41RdbzbBN/BlrTMbFAZSdv9yshmWpCIfuSgW71cR9kN+EuOyvC3KTUvE/f GQ5cb7EK8dl3d1DAk/Qj6naIPzb9JLlCPYYHMWG/IeZ+iAHHEkShnRrSZnxgwjfNvFgpikgd1Xx9 s9qKv42UzSPjhi7AkRe3XhKz2nLSNOJDZDVrHBd16dPLJDAAjR2mwiVKoqHOg6nxLBElXAUN4hBm 8faqMUpWNJCucGPMcPCS7RPui9PXjuMSG7vZ0Se8KnQ6TFxSKCP6RSld2rHc9oP4ILW5PaIIrx0Z l8OXvquUrj5Rztllkt3cq2NzLr7PaxhEUPSES2P6WZJgd472TGyvisIEJc5SImLgyVUoZNOwVmYw 45qVDmdc8Nj9zXbMnRymxjRjM/0I85xXF017pg5lfj5hB5Ws3BoCukpfgm0EDrZzBFK2jzp1HB8q IMgFlkOGqF54ARlQOZ+dVUwS9gkWDMFRP3PVL0cuk/aSfsON2fewMNb4OVdFoLFpjjxbksgBHRr5 qd70n5YuFSw7kC7rTrutL3xwwQcKPuqAVltK7jbmRsSt6HBr7ayFKdnWiDoKi+C2krEPGr0znn4E kVC5ImSeFw8b/yV09V52W+PuxGr871folIts9v424t5zRXZPM/7/LTcuBq6WvFadVAzvzWjfc73w T8wbl64g9QKd9uDx98hDBknJWiJQZacw3U21trYLh//F6LW74IShcADbk2duLB4eDIDf2Umacu+G mNH+dqE4GzJ4X/kIo+d1m9MZu8/ZO2TKh+jcSCQj7Bd3wZpekpMstESGqkiaART6NkBuINnxNokR f0AzumtgSY/G1gtidZSfm6wEuvCIrzkm+1KDQd6/f1/tcEeXGog3RWA8oktiVXjjDIBHr1BgTaEC WX5Skm5Q5G/hAwDQj4gMaV+lpj1infleQFX7jAyfZ9DQ9YIE40E6ORLUmLIlzMRccqfzTu1nLegt 6YSvrUiWo7S7FTX8dhNotZinxJWZ0HAL8jwLfWU0tcZaD4WLLifKdBV65+evNPyMDbhkqiRTVA91 n8rBxpkLU8jk1op8NKVi1G671GJo2ThbbV0IuR76Ql6BY3c6tjaVhdkxynij2t5q4WUjAChIrH8W Qz/wH9eRthib4TKbKXARDS7x1OvS1YcrC4RS2JOCSlOhINHYDXRqX4mGAxRyhcLoVF8v9qQycEVO yQTZFNyxmKzUucN0aOb45iN99iQo4BX16OZCg5WIGXINJQOmPACm9l52EqANjS/76L2UM9w2Vz57 oKBnmPT9LsoP+IduvpduJ4Z2f1ireZ13C+dR1aA/v2ZFE6j0/3PTz7rQtvoS0eW90HiyDj+cZM1C 22wa/nd2vVhu9B0lM3+XEfZNy+tA7oaCV9HiEuB263mNeYdD5jmX7n5Bax+mfwrIsJO47z8Wsum3 AH+Ia80b8lB01YZyao/1POPgWHPVeCFwLKiUTn8EbWVzc7FrBwh74Azac2rUwW7ViGjnvy//zYMB ysgJOvdL41joiAmw5VyMmoLop1tRDGHQpsiuXgvb6YaQPYkIG0PQyVF9jxAkjaEpZd1zUkD5EV6U j+A1kXnnp1CgNkwiG/PAfR5GhcG5Xd0xQXwJlq9zhtHXa0xbaRYHDw6i/po+X6AmiDKJby3FSM4U iwtsWhZGws+uotLbWzu+Empp+JStNXuVD5NH29bn74IG6rBfV0sfQ+DO/5GBESsgl0lCrMPlyju2 O69oXpkvBafz+7RAJRkQzp3NF6zb1OplORsCsiAs/JaO9yAKwhy5eZVvj61Ll6rByBc9gXIg8H/p 3HGsLHFawAvbjVDWOJW7kXenmUeGrLQGfAqyZhYwNdiGq3sCwxFzzY7aDYqgP6oqNKHrySjaxb9/ ew+Ptfeop2QbVYrFu6OglGHNLZExEoCXbJ6Ei5OClp8cdhylihlbhf3lZSpl0jOMcXGVztl+3LNu zUIiml3dgaY77hd1nfzWTQCIb3ESNSDrCBgKsQ1tBYoBKaGkoG2ZlfWwoumfZpIA4vRB1S8/XFx/ 5zXi2I3wKdXaufK0JYjsARkAgtASsGuk1Mby+HdD1IEWNq+gKNu2gGdUXeULQ2woZlfMTfcWkSg8 GnflD6ITLBN6/vGdvJUkLacxTp6C/5k5/gT5gDZKZSi4yhGtzDH7lstL1clr9kDTcSKDpUXZMNX8 XsKz+pXWiCBLmqhsFGo0aKYVaAep2BeE4Mkl0wnoKahKY5JwcGoGUkE3tA6KJ+uZnXLFfz5MHkZc 6PCvE66/sIaOYQ0Wwo7qT5nItMzty9ya9HM0K/T5gadZXnkzwtL13+xHGz+Z2xD+Hi+3gaxgttaP J96aAFFQCxvYV+XS896Dq6661Gy3P67x1kLjjUBRsW8ky7FHfrx389SdsA28GCvd5w7FU9vvUP1t p5FvvuFi0i82MX8sOJGUr2xijnDqmcjYQ1xsIu2IyC8DMYetgrCRZZo8HiBdc5OS8ZZSYoNtzvtb M3ruUKA4hzcDXGaXhupA2J3sFiPhatz8Ze8+yS2vL+97q+M8tsMuZ2qInVLusmOQnkMUPsYDsjSm x0qGETGAcMrqFWiuDgSAZ/ShgcBSxG6vHYc9RVwuyQ8y/Zgjb0+LhYejj+CHvDtYku34ctFWTa7L PeW/l/LWQPAuJlXlmPDkHtg3qvfRGKPH4K9mI+F4cU1GvlsKYNwJb0eybjLUqMtjbvi4/2q9GyIq t6GMC6cH9owkIYsqyFVGFTBkTHq683jW/EjatHTHyYjCLHIH6gOuAYTRmueOYyQ+QpiZlXjtgsMx DcCWkTGHvs1H+nD/OExwAKwcRnR8qNU0A//9Yqzl+l/9NCsvq3tDiw7vGf12iQE9kPkP6ze5Lg2C XPyHbyTaRQGYKwJaz8dn+SGrbDccciHJzKRZDMEoAuYpWH64JosdXjGuClYJ612yOv73XVpafOpf NxC9SIZweIEpISIg+PK++NnLT/i76VQp5XZFGbdTOmsi3AHuhCa15ppspLLh6kNqRBQKoQou1EAX YgKOsNRrk7CdB4D1OVkQ35/eD7LLyvGDJIsWBdPmNJqbWc9cb/zBBJgNyNzrnCBjavdUlyGB1nhw ifSbBHFy55cTyEFAqFAO9NP9SPAT2cZrKInwpAr91UjM0y1PXOtNXlaPig1wmCRm/hFYzMus3AXU y2kYufcDsYzaNe6ua88oreU0FVanfntJerUXURhyY5t41sICJYYXR4lSNyTIXFekEE19j37kAJtw WLWof+LFf5ZApQuLoZQzVOtc/9/HA0asYKTv/H/T74ie8NR4DZbqQpK+MRIZ8uN/0nws0LhzTo/c TojJ1JpnjX226bh5nKrmZ/scWqPd7R0x4XCSgdVTKLg8z48wq55ffm15191bj8kMWTJ5T/QuE9qO 0Qv8snoFkhqrUvGMxH8V5tsTh6L6OJqbpY23FyNB59zhsu40Eu3yLjDqKBWAQ/C+0PTLZJt2UAAM VHTMYS3dyqli4oHSO6DA6UnDf2GoFcwwKGr1lWtgdgVtRjSH45WJZ08r3O9wKJurIjshrNgzIoJZ 3eYeo1pCX7gdOnjmvdUdBZV+H+Yu9aQpDTnQ9xtovz1Mc4R83Ed4sEXrbgDJq54vlPBRsmpogDJq 8y3lk6+j7gPYbjKFIWF+qayhIxqX6xcXn8qFZ+wKrFtEra4E7k6yBvjBJESttROH1QKu2z3JR9st 3GM9pSnJtZwrH9vixBgrGA9AcQrR4bzEOJDGjmh+4UwHD7i/DNLXEzbs69d3lJjXmXutpdHajPqb bKSZRbXVptAudHp0MbvMfItduu4rqAmDn3N1csIpJHNf/g3rSEEh9QiX2HzzloKxHsXuR5hLEvuw fhRjTxcfRAKoGAFhXxSubn6YJyrCmme8uYBa9YGNfFXpAJnYa2AC0b9prrJQKiyadgWPJ2RKP3c2 ipYlqlWCzI+fBXL4R+aLzCKT4hZv6wMOuCgd90ns2PyQQ9Dd08RK+VCPFGqdhadCSVRBkcMDO2Mx fEL6ewe6AGbacCC2THKqSi6Hb/91tYcN/fQ8GMDjuHoKc6qW9UbEXaXEph8rxAdFMui4JsDiTEDp UvMwSWgBx7jp+4C9XqOPlQN3GSHepfaXC2uBt49LV20vMxhWFnMVP0rgf2Sq59/FVubjIvk5IN49 9sx2EjAfqwlUFK7DssJkD/eTTpZ+8gwF6mWMXUIsPuUtp49qXjMOlLOeeu7u9t9Z/M4LKi1DRU4e baHQnFy/cK35Xr8hGY90r8p0IGJFpVyc1ZbUS034bC2EZZye8iJ+O/yi9qtjNqw2aJ8ZEsVVFi1v 4Ns5yE9bZKwJdaJP/e46We4nMBmxdJIGu/C9CkO9sffrD1z3c1KoS1kEPV/1wv5SQ5qS8OObTGXb FznP+/TGjOkTYZNGZBB5VMwXF3hraN686FO0toiYRf1gDMSc1E8bv3ztHJbK9By8ZoYs3BAqQtOG tTJ/J8Mp+rxDYKt9TLhmhhOqZdDDzhIa0L6WRwgYFzd+DGTZfxwG3QYYCgIDqRb3aZrws+Q7rb1a KdoraTkSPkYwUeWi+CfOHneO+mj1NeKVtEce4C6y9XEEAMCYW63v2n+R/I8IUq4keG+6upwgOgk6 HAwVRA0+UkSUbTGEG4/TxU/k+BKyK1A2WezeQ3WHv5a+5rJF7SyGWa+TVRZ4NjrP2ZKKbxuaSfwP r7Qky+hHofAjVmSUqBFRweyfLR1OYefPJLuy2Pj8UUgH+wHjv6uFMFDH0t7GbyhKaTv9XQ6lLuRK N3vyBDfrSB+jBZIxkkYlKrnU2vA5hDRDkrFO2LDZnkJiRgfBAdRSPcRD/KqAqONedm5i7yHO1XfJ p/QF4P3untOjKwQNKXPR7yoBQxWqg6qUZL+Q/jJ7BeEGN6bh8oCK1YFeHjX6b9vejTG6Fk8gSI16 n+rT1E+GKxbDIY8a+tN+9KD7BakNl5JzBz1YZYPGx/qH1RwfPbuzF+4jmLWzA3LjuSx+ox8y4DoH 8HcLnwIIf3q5Yn6S6BR58sUC6c8/2dmZc5hDqwnOHGYkO18z+ZcfKtak3bfsacrJcHEHU0No+88j W2eyS2Iz1hv83Lae8D5l2T1JnICZcpFqu6pXxJFCNuOZhT5MBo06ijrHeMrxY+8595PvmexLjQRL 5j4RRZqUON/kMhrL94JOk4pcu5fOvgaaDalx30iwj5XL6TBe6TfFMSl0OYVs0tQvCWCfL0ULEagg QVlZzEdqmgv/2BTuUAKm023HnkxBMMjYQOqVyYH3IINe29wdtx9LaMuKKsMuKwVDIR9vWQd9Ccwt OIAyR0chLM8EqGCvecKj5yhZGWY2rcaEpXm3P+TZ/89YwaNkZjI3R5z0rXp9xPdmx/lMAqWGxiqK n1eT4ckPUV88/jn3jCHaZdCWeq0rgkT0TZpcbTf56MSVLi+YeA/iJ7ZohxzOOP77U1lXxIosUObe NnKSiVH2DaGH0uOdsYisSfCyVX1ZM7UEKLno0cu+Wdc82LObEuXU216jRWrsKVOb78YwWhdLDPTk D4aa708xU3OdvDRAQRheVPPBlX8g3sExTnJEsOI6DMgNqZ2bAa2cYsKQRwme9kFaKIQAR20GPDBg 1uHH5tm0inVLdelDysbDwteJgAiNIevNrjjAP4vimDOyQuAQ7kgV2pPpyVn8jj87nHE7PvGqbFkA WVoywOtd/7YaF/LNQ5JwXzUz0qZ9N2ACPWNnafBNdJHJtCI85xo6pTunQGMojutx5PEKN0+SfjWf +YrWmlu4hwuyetWvsk+oSHLa1zP8IccHnX1QlxT/hLtrD35kQ2T+nk+176X8RjeUJP6UkfZCKrIn ZjUu4PxZgamGGsIhVvHH4r1ePdhYWHdOUmGi8TqI3YtwXGGOzQv152mblOyNdFS4aDwAZcunODfv YGo+KYdsNq0HxAaBCny4RSjGReUj6bHy2YSlXvTmxrY1qJEovDU7QoSNbOnG3z/kNQqeaigVxMct gz4nkskpf+R4j6wDtQaistKWsOQJmmCLKGQ3KqEEFSE5t7ftFmOe3HLJh4ePAoOnrSy0hWI4dc5J 7gx1sIAMDdEEm+4wmHLJBLDxQeZmrA6pPLaefXQbkg/OC7ZDaXxJnCy+kk+ydY7bOigKx41VJXiT AQoQlwIEiDZJAQg1IjWNPH2lO+tG01ruwlS86IZuo0njiEhorHaz4xvJnCOdbuhzksyBUgHU9AXq QzjIkwrmdI4fz18QIKSZeI2+wwBoGPOirztLzIvr19pLiYtZH1iVImICIRzEuQdbhKH2/5Cvekpn UmTwcOux7KM9ondP6/XuwGrR1XqBwOxdIiqr6Xk/f8WTQYZotj/1BHB1Rg5cVfUDhx3qp/+9M4aH FlWmr6TQnfZTLN9EAisTbj2Ts19XJ0ENOTKO9ueQLMOFtE/ZyTcm/Rpo4NW9+JTGxXpeMWqh6OGE m5tEueTIDvzRzL5KYnqdus2nbzFtKvduTvA8Va5MGn+nIrqfdDuS9O2U+JPuME7MaHRHHqRK1gBq tn69MrOfHfSXcP57Ksz+75QTZ8x3xVefUiO2EmDN8RX4J5vUjEo1nLIIB8Mpccz+F/ztvvsjDr/u 3CcoRYaidJEI6widVMmQ+5w9CcYoOUzcyj+jsopCLePUHHzL1JahPFq6bUsHwF7ARtGFSflyfqu4 bnVTD4LkMbVHhMJxjHjXuxI0ZH+x6Rq/OZSSI9pTg5WxHxc71lWAs7Hjq8RsY6pPGYMjM3XMuiza J4BHdIsNz95BoUFKAfrJcUCgE99FlWTqjLiogWu4Z7J9fLuJpgw9UUsmM0vpy9MATeTRStlrMQp8 HPMQo+iGwm4oUJGl+zD5LANtmP0wCssyLY/StW8PwkN190sSRoMj/UTSl0uVM18MPp3gfvbn1/Xb uqlJwm7Ge5yaTLNUAJNiy+cYCumqJBsWqC3eTSxDyr/YBe54s5KUdwEtiEmDVYG+SzV975ekdmMq SLET97NydNBFeS8mZ3CiIn1q7WI2BUzlTwPOeGj2oB9yPvekRVKzYi2wAgFokUYPOGUPVVoPdw9r Yj+7+mlW6Fpybg2CcePU2L8ODOuiXnun1Il9zeBTOek2ZmEx6C5sWM5CUmUf5j2KzRWP7ldwkdon 6Ji4XU4JaL2aH84Se+5Wp6uLWMmnyv5PjsZDAxfeeKXIqfQOKohsPemGcYUHKOEBSyg1SuB7WPEk PXBbxx0OEc9VtrRyIZ8PTo7efLqCjHMK660jeltMAVv/kWA+y+OfedgefYT19TWFeGkHT9DySXUH xu9aKLp7KIWqLqeNrSjSTN4FLXsoMBwppNzcCISyfMXJvFYVh3dECsbck0jEleehtXuJ+RCzjLG4 aKp6IKXtAMxMIUNHaA8KoWsY34TV7PVHw/l/E0FvUs4TyIEMW/9K95n8bVbxvQ9ZXQBHzHP4gwqA nY29uXa1jpSbNgN/gS0Pc+KNThygh/1xX2HGIhg2B4Oh8qBhirRpuSj8vMzhQ1ifwr9IV3OcYkfE GqVgxJAqDNmRlVvf1SvCZYzex6EPwVVsMawGh646O/NyShT/b/89ZL+W8tH7P+C7C1OKESL65a+J JBbLdcmVebqjtGrgiUXA97ibTq/aVDx5U13YGxhhiAAFuAPEqf6JxrM66Tx0LXugHXd9eG2E8k11 FwpDzPdx8UVhz2D70BIZg1H3oAqiXbrj6qCZqZYxMhFhBaG/+zclFIJFjHXZAF5SAAUiDoqYTrQN mj6jAKLC+fgV84NslflEiouPdUf1v14EJEXqQLRe9qT9sUmGkQfTFocLPjXGSBOwy+SfgO6Tyrdr ZvAuWMjW0dBa9Hm9QOwYdLLVtSyuiCf1J8kOQcp7cfVxxMD5ObuL4gFIcDZZ8CBHY1ueDztOitiu yZY42nJ8JGuq/L4fL9+dxwrelr5eoVTsHeFO4oTOx4tnMycf9vUY4sDg8grXuhd1rTBwLaIVMcci FWVGZepmTpJQM1Gh6qRWQZ693Be7pEnbBZa3h63ta+PV/Uoa7VFpeQh/aSOLNc6TOhDrmwuTJoCE S5CdBTMyZBTLJSgwhjCihSQexOe4152v98uXucl4rDWLeuZXvS/NyYwiTQXiMqHlVMmopdWEfoEI vrPAiI/SzXxN7tbul1TAPJKmlUytlcE5oKEsdi6EPU904tQj/fGaAs1DN4tXAZwmhVeJ6sZMHOMJ KZ+wsbLink/jjcgKEgrdscwteoWFYFcjFI60PJYxK1A5deXq+d1dODvxKxfSPh3yRW5npla0/mZ8 1X08D49/RXPzhRQh4FEdAFDVnYxc4cMdI3xcVbLiSOuIXZwxkWGZ8B3T+mz3JPPX+KGONmE7+Udj V/FGpLaUobjoHh9t+utELgpk4MnbTbqZfetD08GI2VfArmBtF0xivWOyuoroyJbOpviemCZC2XaA 1s7vSI62LS6Xr1po270fv2wSx84zJEn+RUhRJhlpqWrvh3qQFGUka4GkI9LIoVbti0K5veQqYU0I MS1AX+CqJ4l2nu+h+RRyANnNFz2IcKkfpP6xuI0DFo79DAXTvvcafkV4yqmp+5hnf16lFs5SGwC5 Ziadav9tHA5uwMpaUKr1ShtKFrjFdwCf6HIsqx+5EcEPVDnB1HYJiMBV37nHh1htSEWvwpm8OS1Q W6kbNlRGpkvqYzmu9RmGS9vf+VxE5rI00154e6KUWnsDvxFvOikL1s17aX5GRe0NGsOE/Sr+7F35 jUPMAzIZB5dleyhSMzXUfUiV9FpTWIzU8HpxOcX5fneP0ssQasevrAYFGhzGLBFw4lDtjuRq+gXM XYzyb0ClL+U4e643lvoCeKf8nFvQA2MWinFE33xZyWtgLU+I8SKT8SPg7H7OB3JNON/8SwubX41J 5ZMlzXvaSfJ1mWiSoFumxKPKyLjJNb8fpsf3M9Nj4pRIejhriOj4KdS9neJJ+p/uiHtFDCPJ2opp mUBwfPqH5pvOzf7i+viHuQBfQHLcaJVIVODJBt8djcs9t6U+c1pe1MWF87DZTDkKn74M3i9xE45C 5Ne3290tH+fNAJiMUSgdsX/DqAoy9pwyvIR+8NXAmwcDGN22Qrjfe/ivqVoBNpGQRHgCjQueNixm Fk2w+dGj8KeJdW6HThbIFO4CwPZcSOXPc7tV7wsLcTMhl2TUSOHBdwlART6Q+GlkOg6gBLt7para G2hVQe4dgf9b0svnELrf7Z/p8KNkemm/kI18a8eMYjKDn3ujHm1/dMHV4jBnAwjHndBDsmcbbnTK 3CxtyEfmeCoBNDqZsIhK8wSManwAvIKqMIftDxGj6k6qhOX4SSTMtARVtBbWib6t1AOZNOdOz5HE i4ZkHuAATM5ZqRzVvgLCz89w1QBSrYniTZ7jR7bHc8P2BpFBCvrvc2QFSLqHH6X940HCqFw3E1Jo 7Kvpt5rZCY6XebIduWJRhTF0VH9I9o/uQneoY1tqlEkqK/fNAs8+6SOqHssDzQDI7E12gwNFRkQt EIJ5etstprPHP2AcPXnT/8eG5cqQEFtQCAjsf+i3aQi7GKTXqqTqDpsvrRjzcSrcth6DW8gVAgSW 62haoRohx3TjZijabsfZjg8I74BuSNC8G97pGnfCzcV2drtpQnsYYmhaiIe7r7oUMLTRncqYC75T RL9PNmPqN9bOGxq03DcROeTX48YZ+Zj1d2ZiC8aDJHKOTcC5E1sj17DQzJTRsryuIhTQtLkif1e7 bXbioHj8qZ5Uc+5FoRxQdOS+tsFFJcPb9g/wEEy74/K/w9PSfJomayIy7t5Yio/mJESuPHDiyuVU 4K7ILYbZBRarFp8WidLphuGoeUPQzfpgfArIZygLEZpsVdTOTkHsTKs47ukg3axTkh88exbKlO1B fvcyMr3v04qpyZvwGQWwX4hHsTD/5Mx9W8Uz1fndI1qY1X8GXmXd9ZKi1PGHwlcLeOEuIWa9ux6A LREqKnfT3xT6+u5V7fV2OtBtIW6KJPCWeARLXrqJBoOHlZiO3aW5J5yBlKgTXTWZjrn2+KgftLnn dN3Wt/I+kQpBVKLOOYs9u1+6LLUmHWmonAP/kox5eNTsryB4PXHH6pySg+8GnXOwujd3q/3Oefh0 Z6qJ26Ie4Ab5KxrKrOQ3FCM5TkBEfxag7IyzUmfh5BWgy5cvt9vl14R3qJjWB0toS4f6X0a1XXMU a4Kj+8cyBKw4R0c/Z6ATYVj+wF8rQljh6jrzZ4boAL63EFxqYfbM1nqIH4966hZxLcoj5elhq+li Ogxa0NZ4jpRvk19fZzPFPucaXM9ZHBd5fPLaPvAb70HA6nVZHceRGETdd99n40dzA42zC0yQlexD 8ASw56qN6iriZbTDypO5GQUYfVpvFaTcLR0bqao3Yr3RGfx8PETeUQC/rqOkbNSoG+l/a2lxkAC5 ksTS0zmLkIl/iIarMG81GalTueF1Te0JRKyy9l9D8HFFGwIYgFGWZIAMy+SKebhMfx9rg3R50YOk sJFCY1MZ9mN+KCKedQPTZ2KFlewS686UckH/kIEKkXOdqV/r9XHbejSovr6QXaR5txEcemKYIjpf saGGZeC4x44qrLwbg3B1h6BojIXabG56fB9V0BHIGplX0cIWydDrpfJbiPI5nsIIcN+u5qPQXchb B+cYkMnOpH8m6c5LJMHumo52eMJpZVGTtE7AM4OWNtaznGtf84hg0Y1JWP3mt3OFs+OUXv98mX/A CiU89o6uhstawOMLSNlUtNJIj8Fyo+TG7NkEKNz8bqbOWpdSjA3Xj9p73tiwoRSSaLTgbVfRgJY5 IrZPgUN/EdmCxlRLUhLGy0ffeKTgCKQs/WPMoqU5MZYREGimi6C6X6cJp1Dy3r9WHfB7Jms5SvQO zRObV1cmW4hefh4oD4Id8IWf0wbaaMovcy7pFM0JTT7i+ZDOuJ1zTIasjz8fApOPSF/o81UQINEP FT0vpo12eT+0Yu9v+rlKdj9wP0WqNrAz2qndS39bR9XVfysmjUdoTzWXTgDpqEAtW9PzYprIY3/8 /fKE/uAnSwlciCCV4E8THGHbJmf7UfEnn4TiujRasPbelEpDlYhZqAs/erXqxfLNJVyBGZcjGvBc Rqw5lp+PxwMWNmQFSxylLPVS2Ok9afHN7/lscGFZ2YUwwtOJRJ6da9HV6gXD2aNKPtP5lbtc2ObV yPxpCi5NJmjlP/HZzoD/86irK6qRLmOulVaB6U1K69n0meKcMdHYSi8I6CgzU1j3VU4IjePhkgAa 6Ls+C3ZfB4sE4DLW1f6qevvhEEmNMdMvZc9am6IS3bI+9J7KOEDLVvxBdxrOG62xnLo1R19qAipo XU3nAAQC6gOI5PcNNFGrFCLms3twEG60tqIlB3Qwd+qVZ2FPC1QtRAF5gn2Az+mmA3Nl00H1ph5o OYYTMCs9tx03nB4nF3TKzaxmSrz4Tm5sQBiR5YhwOvyc676kC7FMuo762AqFt2pe/PxvOaApqd9w OMlXO0SkIdYHhdLeDJoqDRJ/2XYsbrzFakaS29i9eA6aJ5qYtl4BF/I8jABT5egBkD4ymk/nHUHC NJ+q/x9YLeNEgDCOSajGi7k8sm6zDx8N0pPn2XL0JQbC/sWRpiBTSNExiy7otzdBGlxjPfQyqmdW APFWI6HaWvtuTbDeaknanCD0k2pdc6QwW/NOEg1H/Ek1NB7Ci1r04RnBoTS88ovx3Fuimp77F6Sl ZlzQfeuGQ+j/gbiYh+G/RBu5tnMGch34HU364Ic7D6jzmFBBs0WSTC4NuQ7NZfH/gmdO3Az7KgzY bDdGCRSSh36dzF4uhndZ2mh6PtH9tY1ONsLILI6skJJXuKcdQ1sLN6+OhMbrNPXBvppwfHEkRQSp BYH/+7hjH1c4HmjIG27Z6dGqsW+m9YKbI2ADQCm42I4qeC+ii9MS7d/Lof0ljQXVpPB4fBcY+558 Nl1CWK/23D7AUmDsi+CnJwdJkgpgpYlDTNcOr90lEj2L8vCYJF5KLMY6uLsfnTBjjCySBA8A618l s7C60BHf6A16m1nxUyXx4k6Rlur9Xb+U88x6WSypJJW7qw13AauFVJcQScCSQF4aRJCQYYfqdfmZ FUmLffDmkV3vklvVASdgKW33tIV1kERLiPWPISKcHam6uM1CXk5PnZ1OQ7nrS/m/so/di51aWrCD IMr8EQ773UzF++R1Fx4THjknG9OoUbb3Qub2xuyvvFl1Z1bVH4zggm27MmiMu01o5qeyny4mf0x2 GqNK45T6XnoRRx37qHVwZStNpJdH/f2c7Y7BOOTcyMc/S07nJG4lUVhcFAgdlnUVaWKMHgCXT6l1 KZgRpW9pIaGZJFCWGMVM5HM7PSVEvz2otOqHgR5PYnYxPkmWAjZK7uSVIIU5GafFWHMCHWfgxVT1 DNNL0Tq9LLh68QAciJdN0R1he8Iij3ajEh1uWj9OLvZSHFnIiszsNyQUoY4uVQQxyB3HtyHjo0AZ OtdBnneyskvkTlTts6yvIHaASdySDaidYAcdh+cmxZ8B0UbqzJ8f7KuOnLUeDd1UJAFr/GVFsEwB mgXEYKDoa9IzCOZBu7T3HHJ6GbcH/vPFSwMg+tqR1GibgdH4DNIOW+c/1EwCvR2YNkRlGtaDfEER hAF/7rL+/K50Wj09JK0EjagDQNztk6LFYugc2rZYeFGIRLDaG9Gk5peVZaq8oCVTEvX++YjWkNIz NAcJcr7YKj0e4U0wvP/W5v282gUasDZOs3aKq6v4+2Kjyf6kGNWWZY2pXoVPTQ+N5OFxAxf3LdBS 4GePFcvhlvYms7jsKPAqOf4dcQWEPBWZbAISRhDwEQRAxVWvkXjykW/tNVeP0v6c1DUES2dlKZpl QKmwCylnjE5QVqoRWjGi7wI1GemiUzlL3H1pKJwWZhbE2hLi/RPuTwccR4Kz/G1DePEjaJGsjgfX PCVoyGTHdHXvRk8cGGb7y91ZGBZGiZ1dWLds4hPlqbkELMVYXnux35bnzIZF6claLrAxAvuN2nPN jZCLxWpEW6GvywVDBVXa/1cVGfcgp0IuYrAxsIc1FT7cVquHL6qbgRfZG6w6I9Gus0rZXo8hLLOI E9myJcBtoaPgXGFSJ5ORGkopFXy7eB6Kr3fNU3TcqM8LtrQ/44M/HxqD/ZfRSuIPN8Gm2IfrkwRb YCZHkS8b4DFWmjHAyfIo0DzxwvWCKuO5uS3KK7KaRn9PkBeFmAk6Ox6dPrXLpatj5rYZteUnW3ib KDUrAXiIAyPtsQFCK1ElDqHBk+ER2oUZrLYcyiGBIgbuR/Ggfoq3PRElTFB7V3ECdS+Z7l7T9xBT ief5aHLqNmYweBWldF5wCjKiPpBFHIxBdDp7BFG9MeqWzS61x41STiqwpFMPe0zYWrOjroeLq1kV hzZZUf22u48fxC6Z8cvQ5zgXr/xA+mkhWoTyQXLbxcAoun41iG7teFzIVfdjQmmtD6TN1WUDSqG5 RHR3+Vtl/YlQrbszAFGsuiXVTS+qmDaq6VJlMC8/b+ihoznNY/QWz+5KG7LwQ8MxJGzoOBnH6ad8 Qx3B4LkBmoL6VvC3m1MMsyC/oZkLCXQTcC9pXiXKN4r1c3vzdFOtxBpzcjm/DNQs5YIV4nuH8Pla /wtAV7iva3WqybuJKWWM8LTXo1WLnCaYstrReNZagS+ze/Z6hQRWSad5oqVyQoqoJaZ4y/CbPUPP ypZYfko7dA8/I/fg3kKThKq3IBJwr+s4rV/E+fB8AQCp5Jz2OnXCEsphZBEW7sHVb10XXkONPkah Ff9B1p1CB5v95sM6jEx3z7ahHFSc1jRDvGGmIkI+90SBBRQ+5FSvBwfzUZLSu0fcZehyrikbQwUO cdgKArKFwB9L9v/G/qY+5hwjUWuBvqkz+TqApQg7uh1b4swrO/UFoyeS9td2fP/j9BDHYbYErwV8 PO6a5r27mXVW9WzJC4ZqwQRVL+YfMYbbbBCTjT28l7gIAZB9uSm2opqwsXLvBqN846PY1zMRwaf/ WN5J6mObzRHI/rEahUSxJKRtH+LRHsyYXdB4LhEbQrcCSPOBb6fwZOomyt453zyOgXStERqWXTwG lx534i/9/+7cI/bBNuy1kgBSRZoY7og+Sz9a4KoCnCxIisb0isdbPj2YXUAXX/m3gEL/06C1KHn8 pT9MbJKseTGPkzzyQooMej8S69yHhK6crk9JdfqXCQvQc/tyvVcEbE1u1QkqmQMLSn1aHc0prAkg ANa/Fp9kd6Ssqx+bpipiT4z6X/agtUMMj3j260Tatv5cV7J0qsu9RMjwQhePZhPrUoB+ewSkrpkm q2v4Z5hmqBU2p+zKfdVcQ1PLXb5DF4PdtoNsWw1LZr4cfpNINH48vx6HPaQMetd1mA1hMMDDHMed c0rRN9EU6Peni6gkcfLkENxtoqWQlm585Ne0PQfpKvckLRAx5H8XLqrsS3jFhwqITrChLWCgU/WA bKKO17i/kMdFfuAKNT9yQSw8UCH3xR3G+nEhE/kJhqEpuqf04aux2GEVz/ZKgprWOEJaeGze32FT OmXazlr6e3bofbncifa/HcocmhsBknVSFgD2GbOiY/oqYrAcF4WxDGdhZIrIjIVKbRxAXKKwNVMQ 90jjPjW/6agMUKrZO/ff0wDHk27vxa/VL4P8fEggqZrbsqZDD2+BiVDW/dkTZO5F/7bD3KYFRZm2 u2yy9le97IXsBmCwttckt1iuScTEPZzgjXF4qCsbmwcgknsabAXvfiSiOss2v7t7enEcq4ybYfd6 O0mNHf/5Q68bl3rurJGXKiGpFIDi2h9gH77bP0tfCDb1nJFaojFYGztYcLbwxRUCh8StanLQ7wwS 0HbNx407WJdGLmNZq3PbmuYWQi5aSq/l5857kv291uLHsVcgqz7lD/YlgcOkePajc75xbpTTtQLE StKe5KbVONIL8bLfpn67ML6T2is0omJoe+puPGsopqKhzqjnoaS3KUL/daj5bBS0i7T1LW79ALCl VlC9Hwdoj/i/CW2yXpTSk5U1C9p6dLYJWw+N1Sl1DMVH8WdRtuAe8Z7ZtxIeyB8xqsq2NRUi2gRC 1FVTIA7Bw3MbKoHbVRXyK109TWV2RLtl8m1ftkBNnBh3BjHx03uzRN/saR3P9n04DDIGebmjqqTk xK7bdtbhcire1c8aQlMdv+3x134+BO+L0hN0the1cNC4RUGLZyqfTPyiujUDha54XpQPfD8Z7AMp h2sa+qaSXR9ts9L42ldsxNgXX2xSvYPHZ7TpiaFZBxuSnVI4uIfe0KZb/gnRzPQC7JFYxzFkPpOU f9KlTre3yTRLp1idpEVCCJ1kl9t9LvFjxassQDCUSnqd20wGeK2531cFZAtpdaR8EXm3gLnpkign 2abK4y2Gwa5c/exE1YLqf+5iJSpD5wJKcCZ6nWDaW7BXq4KF+lvxipZssyBoLZbpOEj2p+2lA3Pr YxWgMP5S68RPKooDLqkeVRAnl+GUzV7pYBhxby6gv62cXAkV3wVHJJ+EnaIuBdGpbmw6Kg7q4Z2f GzkaCS7S8WBQsvv6JvpBmoLZAkdF6wfb67mt2mp5lVyYJMCP9/3e0gb4UAHz0ZBAI4HRxEL35d6P K19q+vfPxFcmpA+AuLzu4leXKWzIS7FvasKPiH/aHnKuuibT/U3jDX4s0pn74sAE1vHtFPA97hsV nc4UUzob8hxQeD6bJ5j50VAkMxixHqzzP4tAct63EPHlNkDSySWqLJ0pVdzm6v4JRRzIRiEkCdaL VTH80sVnWYTsMWkLZdigM4A/p5C/ljnKaSfm1kxK55njUv9UVfEiCfpNStk48VMmz9eZJZcFeFsO tyONMdx11u2oy7rYB6Gwwy4FsG9XUn9xd8aJG07FKA3duo3xMjZZ/OIeIszaZCZuW8iZpG6Cd39D FZrZHlpjrh2VTqCeyDEAwOuHBpVYooNFyiZ7HaXukIoTrP8/sH2UgUAKBYsHfjdswSDjkPOQ4kjE xDXZgEGZTZD9yObqxWfN01fwLTlsBfpC7CmsK0hbROHMzasPEuSv6wQ5wNngZjBF/DComA+w1VwB XQCE4+VEE9Fo8fflDeN2d/ymleL0cITNqnOZuw3ie48KkDbIQpDSRUUCpTNZgbjqDvLTygtVA5qf cBcBigLhDOVnb+NSVQHo6e38+z2JTGoEOvj+tAZfWnCxk9liHr+1WvHp7NujMeayLU/jpv2+Uw+s 74wXiXjCXzxOypG5pgCbIKIlup+M0vkcQG/2i7yuyapdm8dFUgzyQ+T90ofIWA98TVAOjIm6xHPH QTVZE+WYNNBQUZsFFOiBdswUe/V+W0C5/vAY+ZiiqBgQI1887stCA3SaJGfdk3rgdxCNBQ2lXEYy V7saAU7yArnqQkMVljnzripxOgppp8+57MmTEkuN2Qi+L2b9QJ4uF3yKlPlaDc+9JDQR7QgdDEuG VKTRJawXS3YZ0K7HO3T7FCg39UDqcdSSH2ajWKaaQlQc5JrcpNS4EPcQcjAPtv5xkoTFHdc+1c+H Efzt14A5GojLg12I1Apc8e0qvTBrQsLNUN7EMYOQ/kHqq/BOwT1gVVMEw9vPVPENLdmCP2w39bYh zfCSzncDXydD/OhHTC/v0d9APd75jb+Q3mtNPzo1alA/Ml7TdmwUZHFISfLNAl7CDNVoCWmwRjxm N3onp5UhGR/Ffo0F4X1wqXxAKi7xmAWzPxJXk+WXXkY54tpSuGRjyG2QsWBW0Yu35WrHA5Ms0Lvh I23bPd222gqLNBfzNZIeGUxg5bQ5ezn1VADb9D/aevBxBFvfFu0HJ7+OuJr5cd3qwiyXO+Nssob1 AL/2hFfj3fQm4gBC+/XUW4EsEModH+SUONfmBi7Eji7hiAw9WwakCfo3bb5Yxfni9qLcr2hGU2fV lU+jApYqHZQu8LUweY4zn2rquJJLGMdQ/ew2sSbT3+nvOuS0+/RKudAZ0zBZe6s3cM09EM5nyAOM w+6LWwZN+aiCR6fgxDr4LOIvqa5v/lxraNbDm0qbohNvIBIM8r4d+6oBxY9TeyUdJ7H3fpt3H/IK zMk7WZrY9WDTTg0shrVezDdIqY5+WhWCkrhQqdjtq6nkjjNn38oQp5x6VCWWpLjNn3g7QNEYbz8y pZoYZpkco8W1/Jxafztw4Hk7t1G17Iu3Fkt80P9VAKBHTBL1fjMdRZWKT7Md3spPKixTEzoTS+6G nYhvwo6ghQDMOBn9H4IY1/M+YeZr9Mcb/foRfmHiWXyPJUNW+iPXmFegwjOL3ClbuVxiurbtL2Ib soUzxZmspcKXw9Rk/HPRlQuqYGj6/0twS9wbYuMuEKlB9IhsX4sOavbH6ucbjOE0waathHDnX3tK S8yExFsSmCZYsZgecMJ6GLtSOAlwqQ0/f0dUz8yMeZL5LUvAxC3vCaKotlV1pkt9vkybUbib+lzv dOTf1hY/5rIChvq2wxwee46khi5xZ4qzWEKtehfzCOaB/sUbb02jP0nuCV4NeE045sBqKq8dgv1o QJrmnGZ4mIrobWTQfMJjSmNvIsqfy7kieDQ2NVTSOkID4e5VsVJiPj/5LO5pu1zayTZQlS0kK9Tp +QycN4K3vxROmZOQ0VevhsSNUKz9hE6i5YhMKr1cRH0SX1i87Imu4fpUbcOVwt8gw3VOU9Z7xpYy bMdb5Embv9xq158s15+Zy14oiX5e8f5WVXFvmxQmneCyI5q150WjW7X26EClgssGRyagFcB9ZLgN Q/YhSYD6MfI7s/iJZ+nEXJ919oRHWJ6WObGkHalDLTpzk6xzGHJAibjPfr7m+rpqnWoKFiEBv3oh ZUedKB6YQvVsDzLJexR+82OB2B0NkHd42GutcheGvSEvjE9aQofzwpsUD7jsVn2SDmiuGGIK7boz sxgSbOoBzDmfytELDOm6w9P4zkZA1NN3eiy7gvSzJO6nALX4G61Fh86FpfWQSfBu+Zdcp4GX7xv5 YO0h/4exgxsZSBqyBuuBj1hvBYAbAbanjyMx3uDtBLEEpwVTr5BbZFvHU053550fp05CPP9QG1JL fIHVGVwYYDr8b0xy/8uGGWDQ9bACtV5eUiDAnVDxLuYBeH4clBoOXFj+KYQ6+r1a4psWidPM22ZC 9fqJA+7MW9ldz5bd7kDoCysiDPDgk6+PQd17XogdajoG4N7vBHi0w+Xl1hnTuyoQ30d0x8CcEKMC yRXby8nGUGqxAo382ejmeeDrp+1mBryWxk7knXyrYHCWWqr9HIHulLIX7jLBT6+2sGDLW11oIo2F JShOkS8owAUP+6E5d1wUiuX6WJQlXpF1YUfxcqxHubxYox8gha2PA00Q1IcvgYzGwoM9RJfgiS2/ PV+HNo8//IGNMqNUa1F4TVCjffh3L8L8hzM0fecWQKR8hSH8sJZJKD6bvDHlzPP+vg2mX58FYN5d 5BU6x5t4MimWfCm8ThKIFfiXDyRYrLGVLc6X+mwYo1SQFRkeX/MPztiFzj/RlMXw15ArPkBir+yZ DNoLnae00G07xLjCs8aa4uJ29O25mBFXRu09lSmrEaNLBpnL5v60xaJ+sPGDQ+ig34Sro1UQm3w/ Pks+NJH+1diI3DLG24KVz9EqE9k/S6nz6WIyZNKYI3Klh20HBy3hRUnSqtDTv1zV3v9Vo9Ku+DgF f0epEhgp34+t4kdeyftg9jvMU+dYYBaHTo0SdNZLplXC9ZRkUzRrHHx5mIuqSIGM6+5jgE+a5Bdm mo2ZXfYJ2De/MEZwH2l1ujeS87LjiLAzgTynihfdGaNf264NLYgfofqFLkGaVicHhbyqcZ5dP4rO CK28CxBGF7I0GOCWICW+ANnaWLjPIQ/rLyQ7pcjtBM/UpYTCJyjwnx8dBJKo1Ayx03puRG4WPuZw nn5WT9UyCO3YsasU8HN1MmYBv6YsubrADfJx82GQQ/ybpEmV8/6zNGDXF1Zd4eKQi30PjEi3ScHS W4dAQ6g1xLecq7oQfqML5vsZ9WFTPCnqIA6lufMvDaENlMIfSF7l1Z/+B+ZZP0YXIRk+ZM3Rptyg 7SPza+OKhEoXKDPdEDB1INdrbLyD7TydE2ucHY7IFAFHCfuWAor2lUcqBU3lyG6hRsvf7sC0K8Vq pekCbgETxqRGq36r4tSUH6wayxaWxmLY/nAJX5cs9uzMn+shkGdZKPBgIMxJBALsCYWbcKajF+4l d/UwZdt7z8KhgTxsWRz49+YI5N0LYpmTakSg64Hke9I5K1o/JtmwoTIPTWViDLrzkC7ZR32Egzl2 diE2ViWn+LqvUx9cfzoO98+T9jszOGafJrrr2eN8j4PqggwWc+vDvF9rnlDLePpmLcPkWMwoNvxJ bnUMN1AYabC7j/K76L4S9RDI+Mecw6d9KtQ84vCFVIwEiKqer+QNcvzZwEuit5Kig4i6ESm0reEc Ns80TEOilcZ50zFnrkvJMylbDmJD1hQuQlJE5TWbirKodwmo1sfIZUZaks/D1GTKeur6hx4wKbOu pchmejAn5HtTCfT2lst07uEBR0JkqQD97Mpf9R2RROWUucrRxLJ8r1GslSWrwk/YsvHnE0g/oILe Su8Wj+xPhoY2VFa8khg2lCD26dYO8cA5azpTxjb+xVKI68YL9xPdnokxLuI5Mey++kEoYLuEvZs3 wCvHxztnei2VIe54wKN4V+L3Ir6GTOdC5gcK+xirn6kWzyT3ge0DYR+Aod7EwkbNshJTKNC/cJCN ksncz3tOL6CIgWiMWqATUUv8hrq/S/y30F+GX5cCMlm0P9wVOa6LvEfQGYZgCQh17U4OcDXq9IyM drIerUdAR6ZP/aTQ/W+9SILgROsEgtQBICINN/HVZeQUyaxpVRTTOPeKxOggCENwCq4OUFBteCvT IWES3KYy6HLng2F8fDsAD1EtxE+Ua27w5trylLK6pymHIghp2CpHeA3ZMaQs3hfUCeLs6Jk8Kuxf T9bCwSsWVrxokIMKFWejswVDGaXX/BqrdD54MGc1eF6wcdDaTKrR5o1igJjgvUQ9l7Jp6qsg7wRr FqFYTyfpv/2ZEq8mc6iMmSoMX/aZla3LrqYprZIv+ChOPmYGhGM/ti9vxTQMAloeGvfuFNE8M5Pr bzu+/nUOitUHab+49bGFmXSJLkqyTlcYRdnMX4ZC2aS1YRABs11e14xIHy/e8xL1GfZ4TMBcYzzC ngo3QZUc/nNNKsGPri1jfH1ET7WymGoQjw5DDPeq0xZ0xeqcwlnxLTcaavSuVYJuBI13DL1QPdSq FtOfYTvbzeXcP9x2Upm8bhK/20rixjXgnuLKjGPST2B/cOhYXilM3ygbzc+vfwnynwA9BR9JVtEw Fbva7NX2qoOngczC18RBZNxVNiyNw9bSjq3qLwAa6CNTVD4+2Le6WGdUtUs56aFgU1G1Fbli+bx3 6Ta5PjvZEg58NCpfVzTB8Yh+VOGctx5DltzQXAYpbwBxAhp2JzezWkf9+FhQxU2uCZUdFcN8B6ta 9B2Bvu8LwvrqdjGEIadX9D7FDFQ/V9GSd9aLzlXzjQ9i8MQOXW+ioSzkJ8RW06MgzPJrVMm5YNSY ftIB0PC3OL4YWNsQ4phEiQqM6okQYg/1vyGpb8mj9xVWbTALkmNBuPdsH0Nqmghu/rCPYA4RXGRv UB1YkCMhQEUs55sVpizqNqWkb45pPkrogIze50hrGWeCYOLYO482p00V19NIbbQFy/Jco8Q2Edlv l4GVL93DPqma3vc9QcwdeqJxQ0kmblwat4JhCRyyl+q3TzbM+oVkFcUMp9opCoezALvUi4pjbF6W ZvMvpzqGSKpODJvneTHdoRXTwWu3bn0ZKyXTY9oh4Sp7JsmvgBX1GZZAijTgFon3Vs4RqAlt7HzE 9tdqQjjkTuHEWkJhoK1k0hfnQWHTRTerzZp+wp4OVZ2XSGWKdTUhjlLAp8ddJ9XbECarUgxrQMLz 9K8GsGk8SqRa82IHXlJEtzCdKiE/5dpUnd0S8U4nEj9oyBK3gMGlT4K+VhWgpd/y5o9vSXQAs2Pb TA3k2T1kzoefyqzdNii/0tljsCN7Fgzn572BbzqiD5ETF5HDyuSztsGEOy3kXfTfcbpg/FVU0fW6 7UT41Rsb6tEyb4exnWtXG+yX1Y/m9ZmC0ei9SgfV91xixTixoKhtj8NLLgX43kzyk698BESSdXHg 8dff7wea3+fLG1ncXyqFZhZYvtbw3++ecQXbfbOcf9K3TUYv5uElOZgEZTgKZdFNae7niFmykbp1 uCKNQWM8mdz7aCuvCPwZSLPdJ3aQlbncMcgJw85o7GofFzLPgYCQnggGHTe0tw4nAq0+q8+gW8dj t5Ib4tnf24R/pfSDqnM/sRrz7VtqUR2tB4H+gAJp8d+SgwAum0Fg4aa1Q4TfcjFrlHlaR46ZvKln Tuxn/78/D8Kl28JzrYbJPuh77K5RLsrcWDOFRmGtb+1rLE4XLGI1mmDlEHpv1MNH9EEjhURfj5QX TOJh89ldR4jpNjE4thL7T61iHFepsVxLrtPKW8CZVtXDzT0JIK0bXbHexPrPhQmIequdLaNNXZsl FSjKkc/7bWqy37jhP0bUSmX0F2p6NUYW1D2KteQtFk2FyU9fvZv5gcAUj6WLJaGk8iCLFjr/qyNP klZnlqDMCKQ+v6l5VZllXyw4ufX/+cJyuR9M0aWPgnxTw9KtHZBvfjUcLHT4RttnvT5DIToa39Zv 7gA+zXktgs//9tC5BT2kuMz96B5Eh9jhKe1vkLCKyVPRY1L3uimKgwzjXn6n1aH/Tp+k9mRLXGiK zn0rrQhU+/8lHCEaisNthvM2F2fjmbYxbVuBA32L/7+hJ5G10vjo6w77BiyAL6dKVifQj0AYFCst xl8kCAI9bwG4AobnAFHfj1GZAwH0fybQ4SlYvC5jaCKFo2ajvtULRnMoZ2lHoovw9Kv8CMhPlynD P9h2LTox3oYxic0c095Y0hpMZm5T4bE9ubYWrVYJ4FJxwGLhXvFTfuFJxQF6jT5tEuf/oMU/Rio0 yXsrv2BfuDrm8268OdH565KDgZWWDxUjhPWcL4o28OPsTNuTXmGsInx5Xp2t+n28YGQ+SE6i/XeO ZMZu7bAhQgLr6Gyj4yPwV0/92L+7xSA3ldA/wH8P3F7cOtcKN5bNoF/0iBYMfPfrziABGvBeM5Ii HnDDNA20JL9xNuALB3LWlnnvspeYpuWYQUdO9Bv36Y1L1OAYzekwBjfqxiVEKvUlUfUy6KOxHzNL 8/LxhBgHd3lMyoOAUWmhTd+h3dOQYTqbZG//8TJALHWEQ+OCOQxBnFHkgVPq9FyYsjMrrh7ym9hl 25gy/6iRCbb2hvHdCRWisiCT+avBftFryJaLvhUkXbvnRtRFtxiulXR2fu4DAddKqx2gYoLczylt aqo/Z9/8sK8lvCCuC7F5P6pCSlkZtO5uI+1pKnc/aPHSals/WfnTHN6ReYyfVJYwnjRBey4uQu/Q JLvILLJhdcK7p/JP3/oPkAlrH1ltSA7pvumABfFx9riT2SNZBH2foCaXYxl6w9XQDw5Cdr4ehmFe m0FePHWmfiM2aGRvwcpOUy2E9x46iHXEBlTWSQ2LjOrDYeYsUvsTgQiwchmfn/7MyaMqUepz3Nha 45NKJwF1n6ryefQRxw8ZZZQ2A0BZAWz/7FHZhWaRrpC23wn0wxygwkjUmgov3+w1kpiWIlcUf4Ql kdPauHxFEgTuPSYvY6ew6B9AMpk7F+or0ZS9clmzpqDxqAvWPa/LOq3j4OTPvwD4bYlP828Ifx1V 71LdKUuRMhp+0GNN+TAO7RCbhWjuK1FSxoE2bygeV74uugPMBbRjZ0HnFEaVd6fvp+idogs4OUmE 901egdTLS32dizUpZ8EZ3CNOBNuJIGdQDU+4sq7v0GmGAJh/HnW4CtiaUo1ysS1jl/914g21loVL a7mJeEgL35PmB7zUHFMdQ/xgt2pXRdDyIVT8xTMDvacpVTC7vFOzALmq05jP6CQqatUTD4OO91If Xjc0O9PrxmMQSEpWZrUIc3c8Eb/x9O7pX2chFiz4t7hQ6VeZ/HmaZIsLsL9LwFblf4jD0zg44NFf rZjZUOJJDcgBStr7QeedSFZY3wV2lsO05ANzmopw6TTwQ79hnsnbfqpk0KKVQ5DH/+y2KqMixOG3 ZCnveCTn+uP10i78uxj+lChThihV4OJbGyl/ibVMm8uCqm388MQT3I5alM5TIl7vnOZGe+svdJX2 jf0ZgrP3tKMmPnoLb9AjBoa2xkwt9oh/zQ4E0GvStFGrCh+ppZCCkkyu++LEWza07y16u6+573rV 5Oo93lYBXF0VkZexTZBxvytK9r/6Eeq8r0c7rNh5wLk215HuqC+77FQm57lJ2KOemDVZfIno7g0K 0GyV53UGqkPhJ8mxnIR1CelknGJdbwQM32gMCH4m+RK94NpVy0c1GmxDUt57QBAe+ayoK5mN3Nhw 8H/M0/C6BVfSOAeY/ZHEo+nFrHyOkQRqXazhBAc7NRDWEohrnSxqpiNfqIBGsuGyQV6n30cQT7hb bDXHiad9A9vHe9Pt/ZHatDQmO2tJ5JEcmT8F6+ujQXH97wDg+0kjjuUYacE2fE1JRjdboPe4cSwu dwOQhLnzHxOYqGtH3j7Mm63/7j8d9GTi7dCJfuPolququsgNUWphE35fr7V85RaO1II7gjgbqN2C maV8xJOVXfdNjo7c4rQRDPG5qoDfu+QMdf/HMxdueirbjao/32c7R1q7CmixwkbOLwINLfUQwkWt SViRQDFnPIMiLluqyBrQvPq3Wp+OXnWaPcUcSdPxJmayMXLJbk7g3i4rBrxELwitRCIm9CAQ/Q/n 5zJO3X96wkfm1uLgt1hAgjVgTYJLUmh2B6qR5cu4iYmZW0Hv7w3Fco7Boxk2NJB+NSemZxLAfWmc ScJN8fAKZbNxf17Sv/rNe3NLLy9B1vBCFDwYvdnQ01jgbC4FIrKJj4U4HRGehI9cHhXIxgAo86Wn /0sAhHXr2cy7wt7PpfsNQf+Vk+h4xY5GhJ/7yQ5TpF48DjSY72YdIrK0RYPvH/SItTldKrog/7jt Mri5oVvWc10CyQZBOYKkBz3LY4CEfyrbzKyYeLT94obsA6HDjpu9ckcPfsTa0rAadpi/FO6bU6Zq /i6w3Uuvqh2MitwyonIDxaySgqDS+Dx22EnlnuaQAw8g7TZDqE00GYqTiBdPytdi6RaFCmdr4HoX TFOBWey1HJ0avX1llp411U92cLJn1rqjvhfWoD+Jp4OHqbA/ifD8EPamvk1Z5KuyklznhVkuMrES tGWSIDxo/F9eiUOZb+xzSkvVQ+PR46+D77f17kkCmgNEREZ6fom17sR0XSS8w/9MVZQ7YEgp8ieP hIanlesl/HX6WJX2dI8Ji3MCGTRRDA0ZWtv07MPJU4unWXQsAfMVuMq4eNCoEcjF1g7c6N4PqsGv epxv3jThnLGjBkmPJefJWBNxHDLZgAeZ64ySD7UEqyM8zo3mMzS3UK3ITm8l/ZqAD+/5GsoeJD3g /hVHmmdVGQ07mf7zSEWrTe4F5CXaTWdwdif0DgNGimsOM4owF5MV/JImpdSToSOUIheXSbtQVKHR 08T7FA3opHy0FXN53alXo40F+lF7foOZ+lyDrVHkZi8/ZKpmi5SL9deDFUNTxYslzF5g6St0mJ/4 HDe16t1mpSF++NyQj7oOyBvRBRy5JspcZd4apDCsLOQxuEcXIiGMJS3tt3WxEIb0RGShUShzOhZi d2nAQe24hQqhXfcjlNuSipq+8DMiD7MHMYkqRb/Q8KesmMn76hfgPvF/VSqe3RCh78R4NGyBGtt0 1SIBjU5g8teONxiksk1eEU1U1qzuezco52l2ZZ+sGr4KlZcCWCCqwyRNocNeRRu2VA+jXpZRlYv1 YkivLNm4ALAH5atGK4/iB+9vzuG7Fa9JD8M0TW7g/5MabmEnqxVFCe/nAMqj7REM0lW4z46GtkAM BS7bmGPuBHtGSlY97n3NeOo147WdWrk/YUpNKMHCH3g8tHntsBt8eZRlv2YFKQmGYh3RdBkti2qJ ZOO/5C3TStALh5gbhiGaRie5uZoDfyjJKBaWgpA3ty0uBS8Y4RKCD/37hYRNAeI5bqvkr9OUV6Dr JtuCQEu5762YPcDWCsKs6IOVQtfXQ9Ifvqj+POgbh/mzzC0JX8+SlHLozhwYTZHhmx96c/uslfsR mYveccn2l0Mrnd3PwGrlIuTttnBi0EImFsvxtFqd6rg7DxzovfyiICspJno7z9YEZ1OXK8D1RkYJ Xq4x6GO3YW2IULvAYsSRyQGlVBtEAXKeXRVNh1AqDjNu1ID+eVQaqV0Jq75Yld5O5AEYv5THmTu5 bgyyAOmLK41Dr9vKlc7bhKMqGXXl3Rski83KL1FcvRN9KCTlmRcRYL3+vKYw5QllxITSMe6/s5lv 6AsOlW4d3KzxQgUN96G61qgbzAlBSPzFrjLQX4m3gsNHaRLKLFf2l2xt3AkDyIUi1mug25amoSsm D8zLOBdhBLUCKklzzcm2iCzzVpfkPhcBhcJ8nYi6Lw+9x1kNQ6MDFtiva+RMHP7Lrq6bkRcD58N9 zxSEAmK/dOth1sP5Vf+Ou98StYaI9dqAqVUBxRdOZ5BL7YCK5KmRMtbeSStfVn1yrRmUH15dbUnU e0I+MKKwdugqnhEkh5HnlQ255fLji91vhigdigZsGMbLHlOocPdbgHAfH34hUrLnSbA7IhLA33Et LZBqihQ+Nfm38ZxgWvPAzbWV0iy2+qxJ6NRFcM0YrwgGKSfibTGYjfrUo9PSK2sJaVUmkjbu1pbt 0S+MGkSsmzFCTPYczEn+DrCqbtY5b+1VGxsAwODj8bogSkDdvlgB+dBS8EdvmGepSBbu8li58/4Q TPZ5NlGyMcGYsz0wKcZcFKvvAot6Rcw85pqckDGG0EfMlSB2ygLdcwlBNmwFYHsP/2vlYfFGHXxN H+D9rSx1vYQqhrly9zekpkyx2tuvMSqmwcbDdH9kyXP8ypasjn/eYcwj7koociaC5rfa13lsevcK n5LL+wpBPcZltSSFlimeSt0Iu3jIc/hBMsIX7ZdeOfRkVtZmtageYOl1iEW+fDVLDp1HPPC+DFrI p29yk76T1yD3aDrWqFGdqtPobs1XHeWjR6N7L1rdhRttVvR0SvNedYawLmIhvV23LlnAXb8bx8+4 hOwJFD1HfjhpIp7QnevRp8GGSFpPd8AbrhjJiOor7XYVGMeaClOPAx2WqbN6tJ61Ob1UJaZ+73L6 V+5jfuy6zedEjb0UVdA6zvjRyTyvYh/GXlJjIxy1r+uwWe1Pmd8uOqDZLlS8Tjgs0W0i7Odu3qtr kcmx0zH7xf9s0iIUUG357kPKZ7ZZ/ekDmpZJVVvv4O5V/wuLReGiFs1zclHg47P6sV/aRdYcJn/n +wh/K7kChM5us4YkcSnSqUgM6e0a2AepbyaiZRpoNrn4MZYcf65IB/bbqtxQIk5CPi86R6kybZak hd4CX6v2+eopeeKZFxh/IlV+aUHruXYnyXzXSXc6QbzTa2/khM+hdTYObSF2KvaehN1USPfbR2X0 eorCzu42C34iUpJAXm5bLZ2mmuJONEfgDdpN8l5s/Rd1NKUrsuMOtJ7NSY/1kQY3kRKPYwJK+pUr q0qbunvP2T4UT2zUufy5JODQepkoyNeIy7UMH0fUsECWindIP5Hpq/t+GjWcZSxLfJekw2TBYH+D RVi6NtUWL4+wqYzKiNB9gVPDHciQnlgjgCbEhtSkCu82EqHByz5LttpEIPtkcfoclp6UlYBYYPxQ MGvmEG83ityhEoobhYxjrzi/Gpn9IVAe1A1u+L8r7E/HErvENHtYTmWX4f3rbAEWeLhjthN29VZC C9Dtef3oqGfcq0rco41OcrArkb2y6miZcXopxkgOuZa8yOC3bjjhg1DiDlndMVa7B8qAS8Jn/SHR XBwLZGgdn2f68I41UUrdr31VPAlrrpec0MvDmIOMlYRMgoL6R6i1AxAQn2aREVZrcH7yO9k26EVm 59Loe9tj2kRL9fxyAUzt3QJ5TE/W+OTXzVTX09K9VaSrAr3rca4XhYGiu82ZQIC4tydcuiQF3DoQ uQWXk1hi9yhnR13FM3BAwzXw3RkwxGgq3VOYET0F5xvLDvzotfxJGQDgPyuOJxx0pYfyetoVQEf6 CaKmbWM2cCL6hONjOmfjz+HRMmKx+BAcWnX6zoKO41nRTzTuuuaZIiF4XvR0vANsNvWx/i4Z8VtM vX4wO7Fevp0NCuj/gp6EobpY0MIDlrWeI11Cu38xjETdrhojD8RoJeusnCqukXdu4aOnFg6nIAZ9 BOH/7hXjHB9N6jvQtJq91+lkxLu4bkH2kyaJnqHr7pXpci22HUNwKW/vW1RWEWyztXkfMxQ2Rv+F Hw/iuOWG1zUTIsk9vO6g6JSGEVMHfA7Osn20woQInJfXsbeCWzxeaGstVN8A9SFLu3cBeTqPblt+ GrB5ROoWfshwb5xydoBRmZVZRwuJdPS5nTC7LgmKMIbvzNvpWBapSkvGfuCGdF9WK9Vtq7GnbvGc WS8MCPDG2ym6J3q5UJwE/iY67Ix9nl1SfN6610ed6tYki9KWHdcmTSZ04L0y3BLD0CM0o9/EHn3t nj0oL0JdnSe+aKma6AiAfImH2MpRJJ5y1NTURsKRp6JnTkpz2FgU8H1gcibyuBt6J2i1STU4diFH xFqaM1isgHtEK5qy35q5i2Or6ACsOsnCxNw/8NRa+d/UOW5JrZWnfl5ow3FUIirXZBZB3sXusRJ2 CE7bnusRqQ42u/SUYo5D0hZF6rufy9BiTaWG4zK/lq1iBk4Rem3jSIrlNfZyLYi90w14CVaox6QZ 6CGtzQT9wVH7UWWzQBqyDK2KQB8v2KbhqaqvstDPNtxokONV380sezNWLzvWjp7kXMEhFM7y8EOd 1sUOWFdhDeVw4AOBFbW4k73XzPan7k4Io+uMt/b5ADy3pflXZyjvCEDlxE9v3+rXT98EzkZNkpQO HOsQ5xZYh8U0cG/4WQogVhCOhWl/z4l7zNHHTCm7FUhjY18oDARx62N96Z1CC1wMIPyhTPHQrck3 /YDqXOs3PWmdy6WmQPuR01DCnsnk1VK4x7l7zxkFYBkJ7+/RN+7ku5LMtztr/CpnrZBzAcA+n1EA ifaixL5HuNSwiH70EI/85P8eAOjiCVoICll1unCkPnugX5rhnRtmSUo2D/1/91xaQbZNDHD+JG9/ +AJj9x1ycMh8L7uzAh9PY0URP2jeTTp/eNHsfuQ1DMRh48FQFB3ejyie1GH5tc7LIshji4UUhpBn akLODFTpcU684fMj17pUDuu+ukpCE7SJuz/HYog2cn5GgcD5rwnkgjRqBIN7htCDymhgXpoezWEm 7f31VN7pq/kWvVyOo25fbLQcBBRiOdj627NUdrjwqhIYLqL/1PORiLx3b/4AhQJLAiSQ/nxD85Ex GOcxcW0GIhbOh9+b+AmfkcfeZ6yP6hw+FsrozQzCnWgxJ9ykxouczhk/8LHjX31iQmkUXmYpy02/ ujtKVcvCP2FPCmEPBDr5hj7M/2H2sMgRTff5BYqOlO14WID9jchRg9P0WKhhIrEyqKZWTjmXqerU QubE/QDuj1346SWj6tznLvVLq824X1Ssuvdkw5mUhNHt7Pdp86FDNlPFQziUXBD48pQOYY/yJ/Jg ktWkdyb3pWCD07JYesu6mnvOoEvR39p71fN1lImrDCrSzvopNZlxh4CqIi3FWYQ74nu1M7mOGL7A 6YnbClZHptw9/xj0jOZ+9Hwf3bUJ5ELGtkDJIZk4gT0EBBZSu6b5yxAqDM6rY//HJiPNjToKPTOQ KjbUj9WFQNuKsyvdR7WUTlONqws+VHYTxFbwxtYx2AdgecjHIHQmCZhtdb6ByJoe+ON/yTrJdbWi rJs+HmfdelNoeedFyQ/cMcDHJEaT7cn5uQxTDPPwUPHTWCjbqktINl8syTiHB+R7YC7eAF++Kb8B iefNyY4AkOAsmzN/ep/zyhcm2kyK8IDgcijobKStSJI5F9g6Ez+WQVUygCw9hBrvoEE4BjeWiuvf kPGON2ApkS7Pxwuc+MHT0aFn5tm4hfavM+fJZgI0QT92C+6VzsMXxeei9TDsZi0+NoqtA2igmzrZ 7WAfJkxTy7+fqLzgUIIIXCcceXNdKBNvq68jLm7I7FiQAftUqORlhUvW2SWwEjC4ZMuebzh4Pbdo k0ekwV3n4VG4m6HY3wPpXLvK4tEiGqLXcBdpk8c8ely9E6ddpcPtEXmOPUtjA9cDxLrhYld5poYx ZeuijkYJcXt35IpRwds+mJAjPy2fdMfFXQu/SsC1LksbL7INvGBetszs7ncaSm68Ysu7orxhmnr0 H/WC+L8HYsD7EHcJjAgZQmDkKVYDv7AGceSd7WfYIzrTXUaumGtWK/vML5/1xayhSMvdagb1jn+6 U0acJU5bClZEpDU/X1tiMoi85GK1jneJZr4CYD2qyZ7wI5nPvtR1GjvCx292fZEqN3XNw3QX1XV5 lbo3VHJ6WNP6O8Tc//3gv8Fyt/Ha+ckv3Ofm9rnVg8v7GMBmNu18bYT/FXNq/w1x++BTtYdeeXaq NFaVlYNuxAoDA8wqlyFbLJGz7ovJ397aIh6wX99OOrHB0DZoZrMo0IZlb0oMH2iziq3/uuNA7x6z hKY/Ayss7QgA082MyHykAEPwrcW2J51ZNk1y+VXGfSVAhg28vAzRNidAblF+vo5TzZteYiBdL1Yc Orp3k+K4vGQYd1V2C5VEtpFp/0achth2sclsOQ7Eck1PEJrK82OcmUIyUGZrbXGQadwrfQ5JY5/7 EYI4Wu/8HjW5dh0sqTVhSlNO4ByBBCuP8eHI5EJGvrJ89rNBYkMP0igiA/EGziIL7Zl0Cj6qBh0k AJwKEd4waRW7Zu/V4oKk/iANx6gluW988yN+Mo9+1bNHOsEUMpmvuSq6CwGLrul8n7mCMDIFWJM/ qVnpkg0YfKpy6YQJxtmAPiQlfM8D1ZpifVjitUr7MkNC1R3V1NxJQ9QDgnnfeDAVxk4CSvv6YMpt 7Jqj64WxVc/rzmGOg2xX8NKjVkkDFiIdU+fvj+Od0pTEHN5k3wNpSlUq3pbnK44YFCxMeKsTZiXc Nhp62PXUNT9qX7/wnZ7kE9c5QqGgpT6YEF1hRbj5GkAWxiGAfVc3Hqa3hIb4W4uWMtC++vA1k8gL iqYdnNqWiKdjMe1Q8fX8krTcZrru6TbyZvgKqnOUslXev4hTjAaStDYNajdjUQFuzdkvSb4Ig7sB +19s8bK/4F41HIGqhFXzjVDrul0YFOF3ApsLPJGwOr9b6t/z/JwwjX7F6lkkqp1XrCcmxEl6/Xik ztrmzyl9Ntbb6ai266kfpDZQ8w0dBetlZdAr139rU+cQyKAvQMrdbxK1SneboKinvq1rBiGCgck2 VooRJhT40M13E/W6DTeO6PIyKCntM7NmSNAFCWPEvIZMXHn8AYGZvqWTpOnSlJfOt/jz2YpDsB5l NMmLVPiVj7wU4gJjmxDs3ts8c+eE6U1MiXLjIUeGadjc+imldlzCg4Q4doQyTyxQE27XE9Hfthr3 okALlLF60ThhG4AXqqwvyW+AK4lwNb32hN7AWRs70wvy/jN7IiL0illdlIXg9NNE3KZx2lQL0sN7 XHWdbc9uReWSu/sjXDAwmcRcRSM4HE7SPex+PnCHTDIWm3pl151gKc2GOwekj9SwgUbpdho8hefB fBH1ekE/21pKpKr17D/3VDgD4ZFJN+y2inn15CP050tOq8QZxlO7LerT4DCG0sInaYGD7yWOZZka 1MF5HE/CLBoQUkUVq7ggH0P3HKfbdlgIx6wxzGCJzefnCMRXJIgE8wBZphneQW1tDJ2hqHaDyn+I +msYf20MAmbKR+W0lXaeSjoCx7W8iJGvPmDreP4qByKgM/MmNEzyCtyVq48G5u45Nx3+m/OzYoOo P5fQiwOeKawfGs6iTptDeqBB5VankeODxi+oiy41l4LQY1dQNBaDOiNzUKU1h2irg0ybeudS75S4 yZQUu1525Q14tlTiWIgGCkrgsPH+sTn2jP17KwyaxEvwhtoIrOGEy0HLaRH0HKKc+ydew32Zr31g SFeuSYD8npoUcniuRlinumeH2OkhKur9wyJl6FdDc9BeZXijgFnkKeh1tmwsk0ocPfKMogqXqj5X LyAelVEumEduz/FLrkRFfuAS1ACIUaPHGDnX8yemOIO6huKH6gseb4rdqoAyBIiVXv0//Iunb7nw yzdinjb0JS2eqehadxD/i+vKTkM7JXLRgCmkyjn+FD4ANamAoEzoDPB88GeHG0J+4WTKYgFjJobP qy8+Q4njQwGsR5FGXwLINXPYEnTB3TgrdK2m6tDZT6w+bEb1dLXhBbZIuUS/7YZKi88MCGGZczrc VyReDRg1uHb0n1gpn2L9ZpZztwMXmCH62vfoAsXoIetzTxCZdniejVHvhgYo88F8pgQKcRXuEAEk /8Fx2ExVli5Od4WKT3fpO3d0wy10UF+FO65DjU0fE9Bs8nRr+0cWQqugk3fEbizIWrDm4Kr2C3Jc Z8Q+rQ3enU2TTfgjLuMGNZk38/QcaUOVqyXIIy2JHIDKRfcl0Ywyjzk6/12Z0R669Q7oPGmbjksH Eb/0KwKXk7moF3Wh7/24XPYgSHebd4nJcaMYtDET58G41k6N2RagWL9VbQtLjtaBpf3MyCEcBGIY cyb9pLY2oOGXFIic2pA/xazRLyOMU10Cgj0bWZLj7ISBHmpWzKWqjajAarsLvak9vLbq3zkLoBJy NXNIOjlSY0zCBsfDQmly/JgRaWc21nHC83vJUYGMUwwyi8heGRLmPN745h4IF7kAKOG3pp8XVAp6 zQS8zM4pEcs/9cMs1a6rVI9ccJvBE4h+3ky30mI4mphTKziOxBq/ZBF6A3W1rnVLseL6D53KtUbG 4OrYMtTQ5ZErfxSA9aMPX5JIwZhTgWUZFfyx6R4jnhZ7tDtG/tzYiabB4tUNt7d86wMVC15JmL6k tqCQIMJ5HgkScWodk5FrbMrYLdoH59VFcPZZGTvnv4jFKWqKQosf4JNID2LvcMnTP1F1B2SfXiJH xKTNc97HGnSaLwUAJA0UoEEGXz6skc5bvglTch8oq4ss1XZ9wN+rqhiOrknqGh5VFt1PfmisW0pr stnBqY7a5s9po1eByBWgZkHUH9me1zCOCJR1FdkUk9Rnbk6/Z5rzlZwumllGTjZG3i6m3RPS03Wf rOwvaV1WIEEUwPwJlY84gzFk6fPVBTC0+aZOReLrW52qIvnRlKmk2ipd9NRkB0mqEGWFrglKEKIR jzMCfX/PcA0B6PflGorsNu19e8xSHzfl5SB09s4PzqRd4pU2wkWI9nwuvNw6NLUDeF2Bahpa4UgD 6bDNQ7qGRZ5IqfHYZPzPsNKr3UMkclziwts7Tqp40JC5cFNt9OFla242Omf6thoXYuYlW5q3wOIP hVg1cHOnvccALwSKQcxocT2vIaGkbMj+Q50Un7089vdhjpmjQd7Q3QKgAFPD1rcjjI7rx0sP7maT RphdFYPRmZSQTMxkrNl26u65I0oDPUvXDtWHG+r0kZU3igtKi7Mya+OpfkpgMh0GTdLQ9qIlVxdE gOLR3T6q2+PZpRg4gOZjAh3vwhOx+amcDBeHo20lPeSj/6hhkM0+FEtO+k98W+AjKHiyurDCdwQD t9b4f4oXI9qMaH7/Yc8Gsp2DByDVheNvXeVcAT08hUuipMDJ5mU7Xd6KcgszUX+UQ5xo0dsmQKoR gEf4bg1I9zLyj+V1pbtk6nXkv1Zoq9mxa65yIpzySCHVBpp2k1mtONXvRuGTzTGFJYTEclk0k+Fo JPq6KvzvCeB45UGznqmgwPrq2FOtFDsyrZGo++bav+8lHVjrjuG6q6FJjCHb1eGf7OYv7jDvKfQj tvKFq5p1JW3J69DWQcOrop89wrcrp+2e+TcE5wCc9egHYxzeabkcENRSmjG0DPfjoKnY4X0bTNIQ EiHz0pVJKLtUilTO7yGd9fDtk2hCAeHdPZwkrDaLnNMJAk3fecVJahBWb1g88Z8iNJXKkA6kY6Xn FC25r5Ni+wH0v+J6AIHIuwdSQ5RZ/42hYbqAKnmT4FUobsrp/0u+pNUR7DW24rR8LHI/1lZW39cz x8eI++BMPXC4IOKomOcAzYyCpnSggGUZJoB1+nofaDgakkpXIhsYNw54f3h+SpNVC/2xWIjnzSI7 xxV0zBXK1zpQd1G/obfBNsq2l7FXUidHBtxcdptw/wPDHBsRP3lQ4X9KskIzEtFm0zgcAqE0atI4 3/bPIzQOtskUAr5Qk+Y7Ms6duANQtY96mzyEKmQ9zGPXkGUxrnGeDxPxOnlYCZn7cw2G1BL/o0zd sGZTtSN+DE0gUDvBE3aRYu1Nh3cgpPEnJkR4z9fpl5Ci1JnpKKINGD3newZTZo+kAblUvXW81RwQ nY1PmabE705Si8tRkaamMbvgaPfJmXdZitA2ROEY/UtvLk7w2uD2FrmbFoZtIq3fgVyLdK06kY+U F8q7tn19zlU6+Jxq9nKf3vfl6jktmIYD8OAIa4ttfcOakOQHm5UOw3pHnQuOSWTEOpo16PhG6INq WGnw5OHkzoWui8M5tFxI6FgOAhS6NBG6RI5hw8B8Wah5H4KxYbXgl9kHM37RedSxpqcGN9+Xlpqg N0sxzzHXxI+yf8u3O3oxoy5J4gqAjEQH7Ovfbuf0Na3Aptv/BsyEh3G+xYYyCXoVGaRjRiqouw2R +Wfdn/j24wcOnvinBMvTd1pj7aWMraaY+7xWmZdnq7+FaoRzAHTNUetPYcbrZsORQuegcISCalnr S2fPGgfZCawCp/VIMbqTHqCKtoxvWMdwE1e6NzTf+tOC49JBA6QOzxhaCOPexGToVvuAleZxktyw zcECdMU5toY8qt+7LAWzZ9++50kfoIGHkm7PwrXJnsajmAlilZiEezcDHJJ8kLCXsZQyoRmoa7/U 2urH3N+swUWDnv4l6Cpxh1BNMcNBJpgfk1aS9Q6Psgf2RK2t893aMjob1PRu2s51P6loW7bk97GL b5e64wyFIf2VfMgbeD3oAJA8XX4Pqum72d9In+fO00yTlBFEwRVRXLpGBGc/CcQntlgEptya2zHS gB8mAHP6lWvgqi/ucqqqaQpvU4Nz5+swRD4Begb/uxhDoLV8kQJdwc9b9fHt90NV/wXGpHgnDCNF +QB+1FbWOxojd301FjtAVRFSahN8uTATqJA778k1oxWOHLVy7kTfuN1/PJv0IhoxlMO96Smjlai9 0jFgqip6dwxdM//bscu7JeEQsc1wbwD4sekP7Qq0lGBO6pVkBnZRwnsqK9CTo1PC9tz9UlPq7jiT TYWp9fSkYkcB3W2wSWjPqv8W0TfAXqwsSBZjV/BDZ0IVA76h/GKBVELTBb4J4FLbdXcFAubr8win iApzskYO1cPC/CCI4s2NcfsnEoqSZW0m1Gzt3++1odt1AuobPVbsET14siRAaMdkV+6lNo1FC9cW D0EbfrMYwg3LSS9N/CK5reFB99kqRblBRthTPyVbd5Hbnkk9xse50458x+pRUPnF8fRfg+uxdDKW q/7CtcjnL7WMshdOulqTJUHBDn+CIulbqMX8KK0jjIKUo6x2BMEKk+w9dWkfyzzrcEE2aAqww4od DELK/6SgD6W2bfD2aIQ9yZl9rGBkQNPS2bkxf39FHfDoOITNy3kE+oMpBNzD5VRvT0XH7f41l0wu 8MfI3Z1KPyZ2H/ZU/8i38rwh82M1u7Q5rszba+JONCk2kRBgIanT730ilRHBN/5v8RJkMRVgx3zm 53eYUixRE1QeesVN5VZ0/eDRkhfNn3zSbqyrZ+sLHo6ivkiRk2jq0Uiq03rToNP2Jy8/B9B61/NB 7s0kLMVFUuCQW2QERmzew1Cl4fryCYpDP5m/UhjN0mCnT2Dma0qBESd15AumdjxcyrRXxDpId749 SQmQV84OOJkQ2Vikbslm9/hgED3xdOV5htO0op9A/wHSFAjtejH5rRh1qxXIfs+R3pimVE7zWxhy oUR2LL/sYE5ogEnkdBkHuLIpvgo8RTcDAoiaRqx2FKqKlUp3RIwsrWH5HD9yBVY26kKznGJQgkTJ EnSIUUbJVX7/O5zdITCETo8YhhWVabMRt38RnYB64kf/8AUHssgf80IJtcWmXXk4s87N/AhwaEuG TlWDDyse6u37K9mxhPuqQe5d4/tNEwbpq8SQV2tpV7ghrXA2hJXObYiv6qvnZd9QXt+Lpi1rbwQW +JVPHq4ZGM6oajZbSAGURyITDmvnNSnRkzyOugYuIzmYUUBY3XRhvFnhRoMK0xN3PvoVLkz5+eIK G7t+eq1uMOy31oIiIR6V2PjPNJYz16zA1OUv3Ro/MyRRsoG/loU6zxc6/oXbPQ9IqXr6S2GiG6cK by7EFvi5vp2GH+KpNOZ62r+VpFr4DF40sZGgGchevsgXWYJtH45JLIiJyu+wOFT9VDvoMpsl4f0I kjMpGHNf0YIwY63uinM77mpsVDJNlcIf4Qt03lLmHSEIwtn7CO5FPQSiOxJOK1q7UyZN9K8PDe4H nfNGsHiCuXxFhbZv/bivH4fuWyvVP00B9ug6BF+RgQT3Dt53sOwyKsj8dTbfIo7th9iv/oHPn0D4 7jwAIzU1DS4mvUdPSD0WVg21HSyelkHtsVeJQVRwndy9t4UbzuIw/eRpNtcPNprkFPmQ6U/g7i9a OgMRMIPP8Uq4mvThifpznuLo3CYxbbTHhT6Yilt1FmkvYSWStGhne359qRrfOIdPfVl/gujE87M4 ZmW0ArSjsl1Ectcv21Yj3V4qjH8AXmOhV/Xo9ItA6pCJbvBZQnnk7nFp7yQHgMIU+9M3maPBYFpV +HtWoPwvCma1SKZgfoH6Eny+Lt0hMAwNJIEqeL6BCx8clLKR+KvlMPg8LGALB6Qpf2IFapUZm0uE ZWjXh1uOQmCX2JADrJcc3Oj2i70djCE+y5jFncM49vW7NZPaFrMU3xmc/6qHbVeSJBvRAmv9t+A8 9bDPtSFU12Pp9PXHchiHzPnObAlpaRIAw7FzfHdHzxZZWpxnP5JracPahP6edGZOOpXf8ZdA+TYu n//1HqfdCDUKTtr6MbLG8VSB1gh51rPu1S2Zx2rNZH5yqrFG1W60UVVROq0q/IzAD2IMGgk7CNhK jcgQtCwTGlwkVk/3xc/WDkv06Re9LrxHurNaNmucHDVtvCD1aE5M9sSlJHu5dFhd1HTYMXQr5dpD NtDydtAeWWqTVqIlvAFIEgmQptpxXG9VO3DM4bQGrQ5rG0sz4OCYNY4YH0JYGBpdU2WvFG1pnBYS NMEwgY/hPMFU4vMrGKKkM9/hRY/02bdJsJRLZwEDH0Mo6r/Lz1lrNHVfsc5bh6o7G+j/Xj+EXKco mZAd16/36NIMubEQgdLyzqp2ApS1I9MYR2WQ6vgMBvH+9VLjD0uVBVm7Tcz45EE3T78pwr3xXAk1 RCuH8ww3/NlO/UI7wUtnCo5CdoqrSFoG4+RnDjdWu7CkUOmilKqw7cNGUO3U59amE76kL+bNrkiA xthdf2uz3j+YaZj2MM49H+RDyp9sCLmbsNP58RjSlxIxukwze6n0v34sS47T7IdJkmIZLQPf6HKT lKC0ID90lWw50FpnZzsGBJL6IoyFz4qhS0rOvdjW0h9118BI1stlZFNGKA9q7cQUOfMfakqvQOYz 8OO+IBre+h6JvVS6wXLezEWXXISqnFBE1SyqH8CxC5wj3TCzVCg4ZR9c0KXa2JeAOnKyhuVq1szO Q0ZnuOOM5UAs1SliGLVuvcOFvT1je+LuvaAzhUIEidd5Ptj06D6ttyNJJOCQOE/UHFDN1IoTbRP4 vdfx5G6N58R7iF+000yqRBvpKKyY2JO5G/74jJzp/YEogaXB2TXJb93CsVdFa6bDubdsjbNabu0H 6v2FfqabdRYjQGy3g6bWZruCFOhMe+QFcrp58w86Fs/qLHPmWQG97qrOuwVTlUrLmcgr2TFHa9gL sUVAi3TuTJ4M4tyAlUgYFS9cbZ+4zFg6iwhxwAEIAdmnJCD2xt80XEaXb8rEdkL8jzFnXi561u3F 4CD3HAiYDKar66QXuOwkC/a2Ffr+eHg2Zz5D0O6PCz1AGIcTbeuVwh+9iZK4IvnyLbF+0Dj/4iHt zUR+YsTSBDLjUD5hHrZ/pFs8wSTDN6GZ9GoiRPhwlOa1AASZngIGKscW4ttX0R0zHCGhhJjmdnMS N0zsAOYEG0UL/DsskS3lZDNAsDFeX8rV95Y0UsZ5/B/K330IT/1cFvimGKAeYd+9gzzBvE1YEgw9 gCpvRnR9Cx+AqhFkRXnu7e9EN8q8tNtkQmeT2yhK1DK46NpI894viVquVRpvh602PxJG0J7tUpPB ZYMpfa0mZYy9yq74VakJAmopn3fmq5KFKrxcPeZFcu6vhvnllde2gSMG5yrANFLDvTigYUiti9If msJHumSXrY09QHINYxHgOABxLR3Dqe45pl2rZEtbOiGAnhF5oZK0tgI+wgyP/rZbcsUXsV8rMIIi F+RuiAb/v+x6hBMYEDyrZjTIDH5rL1/3M70vMYCYrezahUDqMslcbcfFf8oQRk1BJ8pHbRh/Cb6Z fBEFby1ge1SJHCDmmcPHsyeTXvV7i/xme/bS/HoYP1udHDUdXQV/xDWX859/uJ4h1C9dxwxu2Imn aJrcQ7TdQmGwEe7UTOCP2mhHZV2NgxS2CMp5mxIDXmRUXzA1dFpHVTmlMvilqu3v1ZmNMT/x4Ada 5LEh+2UqNfI2f8EyXO/pjJSEHXc10sApcTTZGTd5D4kbp1kom7dHxB+L7+kW+V6CenO4K9NxMDV1 Wob4WLoUV3bbsTDASHxB1MRjCM7Y7Vx5l1AeT+84YjVa69PwslswVf1k/4vQTQf7hWlDj0WnwJUT +0pK4sTFZHMvetxoEeZSuF4xTetliUE2pZsjdygF4wmuyHZ58mOTWQQul9r9OhMMZh4iAEq4epxY DQurc5fgNv4CBsC9rG/qsjHVsxNwozPEqUZbd3TBdD8JUu55yF3XFLi2zf71t1EhRxr9AHOOVka2 l+WkZWoZCtFAMYXgPyzFgDg+strDw3/sps4gmWqvP1Bx51ZLXbQPI4Bw/qAPihcrZOK3ZAFIJN0b JRG+5WKRGMtFn8fuTIhYq2KLycGeytih8Djqw9rYTPU4SgebeOnPWaqbIcfGxoZ85BLDt1l0bLPI cCLL1Jspg/Xc5RagIdEsiQrQfCaBAeA1cE19BlaGLQJ6t2SylxGuFl5Dj1ZDcBRMHQvHF55hECCw Aw8kIxO+Ea7MZ36ggHR5wXE2ScqKKk8VAl32V60pXVOYV6Wm3Gs0S99Lp3lWP7B1qbIZB/zrTIfc BFDX32LR5EdybJuSqEW1BbsxTIpYmCQRbWfygo+qJwjq5/U3GxkTEsoke9aNAtrp3dLUQ/+BpayZ bWvzNvYvCSJFV/hZTpZNK5xkULSjmWarmbQnh2Ya3YKo9CGlriN340iW8ozgwW3OC1mhwn4NeqTT coCPNZrfx7j67CIu5t5j/lr26KuN96eOYiJU9Wwc1MERTqJ9ZHSctmt/kprme7ffYihadiEsnhcu IOyXVwTwg+pXxtaLxOIp17MsDGrMV1K5yDvNcOYaK10hyOZuElld11/VQcpbeXM1BkPaKBXPGrpd Y/Oi6CAK7UQjEfoycAgFo1bHYPDFQi8SiNddWIhi+FZRxAzec0DYMCTen1pjy1xtbwzt8wnZcfX9 tBqK/SqTdhx/KRP+yAjnIuDRXrbd+n7/LjCa3IwxioPo2DSHf/IEfbJjHfT/BCStu4ND30iWZEwu RjrKR60+r7dFRbJOHv92ylEy317QcX52SENFkcJ0hhQ9U6A15JDTgCYSrwA46ScXSejx3gAxfmnh jXyKKtbEhCa+NrloAzaS5O6WRSNrwgFJ+BMaQncLHiA34ix+zzWfeyve2XXbtiYllwMNaRw9+oCn U0Nsn+6NvNSW68RwLxRuV07rQu10GAf634cGKIOikTNn/MgUgHVqY8XOXfE0G8Z3kLCqa8Nt+R11 OdObK+mt2UuBGjaffBqj8cXBCRMWNmfZEDseTd9uFeoSqzQbtMcaGhsqijQ+deYPjSfSCY1xgfJz nI+cyFqNf2m/DSD1ffQDCDQyrPy1WUsJXk/6v5JaUHmWrQpGc2xFSRHAi13NB0CcAZCN8pUHnJgr ew1G02Fd3vl5w5kRopsrNmYOJAnpT4HpipVAH3yK/DLEbRNfxK/7RSAplgqWF6/j8txgX35ZCr3X yPBONapNykD/7BmpP5/yfDs4Haq9HT7/AGUxZwYhTU9SlceiNhSJDlK3xGY+6z3x6+Nmqqa4sSF9 XZK4dadQxifI4YyMBE0d8V94CpcfqYlGsAp+ekildXn3ZtrpERKuyimqV38zr01a/DSky6/g1HJ0 iKuIgd4ydXo/sZ0XiWHzgUikS7cqv17KNHSxQMnSdoX+6O3Q8nA7ybBzmfCI619tLVDUTLpQzxlZ l8h4ISMoSYgqMPh78p/88MIuY4NvSpgWwDGlvLf+dEu/25JIHzaNB8pwPARWvoGPawxaawdYcu3O jalXnQfsNLt9R3Kq+I//OVwGdVFAnPKotqwkNkvN3XiFz8ckKxfhZ14/VTshpetg5q8M8H46CqZZ o3k+3t8JX3iUVsJNJqbosinocH1+SISUgbej0WIcZYejEnXIs6+CfUYlQ2mzlJFq5zs5fvqBkWdG wzTEi7LzNv/K6UBiu7yxBk69h0m5FoO3L1ZrBkxnz/3liyQSk6jJTmkHTa9063gOFP/IlF5Sk1wK Hwe3EehzHE4AlLAkpi3IAxzkwKdeb/S7+QGmKQVVvurwTGlg98/0U5B8wAzsTNiU39AExZHQSYQL azDy2WwbIBul9KAxSyGwG3+pcXZxfwPOfxSGigBUE1CNbDm14MBd8HS9+/helaw3Hph4HhoLeyU5 vqCCbJP0foDHtxOgCCcRYojyOraeMnOwdzcXkXYAJWC2mLMGW58eKWzmaq6AYuiJx9dDKI0eiwDC YKUvCUTrpSzJagBACy9BZ2yoARzRME6Pts0Blc7/UFwT42PORhq3H4l9WEUdVV1Z8IT1FVRMizeW Lb6LhhpHHLbym1hg/pn0pF0wXnNckog8Q6QrBVMaD36Zk0QufpzVJA/jCGqnyTPVHfA0bD7xf6O6 kjncH+IIp+hwgpLJUbgIz+MjNagH1GTbVw4umAbgjMPpXQ4Ue1biW5wEIOAw3EeJ8WBmF/Gp7y8k 17zvVUJomhbeN7STfUWCINafalKVWTStIss6hIfJUyVDwWpl29Va/bH327ZBK6rX7Oo8O8e+sAdn 7koWPYOtWSqEOk7k+3anJsx2OB5ScPQ4JEmqpxeMBK6QK8eHF5zrUNKw99n+es6i6e7YcRVKVuii 0VyB4AHlI4bqbAnxC80i+t7X8krNC7GmmfKuTtRTI40nlYkcTrJzEzJC+fG2o0kHgor+XdHKF60E m3BDiCswKNdd/LxrhtV0j2Rlg0iY4Q463akRdCrSTFr4vu09oJ1/h2T+h83sOZmRqvPha0ye/Byj XwLatfLPszaeUpFilRUkw8q7ODjb6hixE1WGfM/AWLizzwvxe4OaqV5uLxcokM+geqYZ1FhvANXk coMw+DNvlELHUcuJJgviEiIq59O7rtjD+xxfPsa7PaxK+9wCkkhfVXiu0FLoF0+tU+Ysi2Wt7FFP 1Oomua+Ce1Of8q7muYmYEiQrhvmlukD5gPpBbEdPf5PmXmR0T89Ffex0ci88cFbBJdr3AQ8RKTTn ydSxzfP/w8+ETrVw74z0tAhU9PUzA0J4lRjjEy0n7RzwEA60cSbcTEKLt9Vjmj8XP2b1xrBDZ1XI 87NCfmzEp6H/GmJ5N6+m/Wn515TSgN3uh9q3+hE+w1pv960v3SWg+1uTwXffY7lQKPdybLmo4cCj Gk5kGK/EAMMB21Iye1Dr+Y/ncK0Rkixrl5kjpPZjp6npPBts7eMVIGPa75vLmde7U4V+VE8oNy3f MoGbdAL1WYZwbIiYAL33OLvktTgfViXt583emy54HMqxdxDahjqKZaBJMVi6FevR6Og2cnGvcz0K 4lWiuO7Wv3bnQwePK04dmcfDJvMSWeZjtQmquvDF6aLSGUxbAO3VRoggmlC4oeOUyTYaDb1sy4NU fFsv2LRGZsCZTzL2kfvdHqCC0KhbfsqEp4zLOsfuyvC5WMoC/nXyzV9ZO0zUhjwR3LX5YTpGnnIS J8+HNEkb7SIxTd0dglOBTWwdvHV+41ZVi0jWgwk03W4oeAACvnBJ6F75CmjoWYsyBXacPXpFt3oq uknx3dMZp76tcHwr4Wu5aasW2scaVungWh3K37SDnQeeFHgQ7qZgm9cnxs5lOc1u9A3QZqsVfsA9 QR9WpT6fesoBOz+ubmqy435s7Gmu4St7WKk2Xcnm2m7hc6u6P7JMBT2HBHDIDWiBvuHS5sRoX9C7 wVs/jimyxxy8oG9G7iioPi8HanUD6gH8fzBzBzwXYC04IKptbB0YkBv6k5t5qhgF3J/BqLlCu995 0ihIuqJ46zk8Z1tbBBsOOKlidyC3wCkS7Zed9DLg3VmLmfBoPMTCLxEK+QcP3WAPdn22rvsesXLU hV+CShAAygZLlpT4W/0qbsa9OKdpNQb2+VBySBL+W393Rw5h5eFYFD9kmaMjQg3nV+Y4HSpGSnEB MBS6jehTrR76sChPOokQ8+6IH7rtZBUAKIcClfgiZoAe6+ZHM9AQ3zSaPP11h405ayvvVKFq8pZi Z2jvjQIze3dp9JoP5JJojPm3kHjQMXpkE2E9jPw8I4YtS9Wk7WjFIOr/vdUc2V+7srhKBkBbLYuJ OwP/GJd+T17TxJSB1F1Z9Ci3DhqR/aH9jYVdMKjMozN3ra3TPS7jWHjD8C25BWi9/rD0xjH4WLCi gGWbx+VIvOdCkkrQUXgXTvfXEjHCaOwFHYNZMDWfUmdKjMIUL3KhaH8dN7wrqBSsVFhXdtal8fpL Syr71nyDVGqDkJPUnwHczEtn3l0WmuEv35mqaRY99M9uwQ3VpWzzoKoBz8QtMzrcqN1rw4pUXHhL t2uNX0u4VPEpgFJiUP7HuUxXXHmxkkKcTnqAQ77djW76txQ/gIWUmN4Ckuz8B8VAjVztQgkr7rJA PUYfNVzBI50RLQFnuucjw2lVY2f3TpQw+R/UjLD+XqpopWr4vJkg91rfbLxvl/7zLIn9Fln1QjDN kBy0wQ8nDvmDXGL+9I+d7wuWrFy7GqOIlxk27CJHiE5Y6nwdM6OcAtkT1v0yCcsvop9ltlziVlW0 3n0nJ8Icf7QX85LVT4leFW1qcm2YsnNUGy14xBvjG5i/0QFDjrvuFqCFYsu75UDFcHH2CNlGdMtD dGfFxJ0SLqswZFCCEbhRJmgYNReUAb7QK/SPpfx5WCAZVVHNsVNh+KcO0K74IDKg3pR7xm5rAVXf 1joaAkkSOyven3YzxI+yxF5pY/AjpJYL3PEYoqcv3XCJCseXdxcaCSYKP4A5ZHkemYg0zwtLPuNL n44VrrWvCXdxF5wot8uuyFZzMEnwKy5ex9rPtfXT61vKNFENJcXhDHQ2ZRpxggRJC0KH3IjtAO/3 dfU+E+If6uu3LUHPN3f9sq+kiELQveLIv6BUpLcfIYewgG8jZDGcKZ+LRVjgPeHACJ2p4FJ2FON4 0Skm+J4tdJ4xQYz9wdGLM7S1hMklx3EgYTlfcYJkOzO2fB2g5dqmp3WfRCTsd9EkovxZweBEhEDK NwQcaWI2AG1BOZJggJ3klKBSfvLJw7dMHhzH8+jiOi9pfmQki90gaadJsYkybbKk7CM0PbWSLMCK YiaJLbfG30jhYOUzZbLCCyes+O47RGtF/kqPSeTP2bbgLVHcXwmSbm8QNjj2d7XHsOG4H03wra9w zAY/QBHMTvfNUvUGnFE7JULtn3OEQPo9PJGyGlijokIEaHCjMVkH+9oS8G3kH2ORAHvYIWlS0gtG ZwPxSU3R7DRns9xR6XrmAjZd/6ecfIl6Y/L4cLnPfaHEjrFzsgYhAY0YwWjT0osVpqb9vjKxVGlT 4Mo4hnrkdEsmzdHfZXGWhUXsmgoJ9v3v8WnkOcNHSELDxZKDojGAnFTjAhbZCnNZF3EnXm/kF4nA FjGO0AThreQSiM0RQtGQOa08mD0csADgEI0/EFRgthzfoB62/hL8BDd/Ig1gs1ynr2/Mw25+tUg/ RoVoHCgvPYtB0pOdK6xokCtnlRiOwoDMMHQK5VvyKj0nSnEd4C1EiT09HuuKU9/bSyC86S1lxLgG kOXh9kCVnusx2uElj/NwwXhdWO/UAVkwyAXeNIBu3+5HkVjJCyjqxe9zZ4YELVVywKfb11KR5Cop KKNkruhN09TYGmGdMHfTtFF8BFRYfxtWBP1XBuLj2nsAqF76e2X43HdegPpxRdc9RcG0jprZSOBS h7G0k16Purce01Btk6rmg7Gi4x+zhjGGh1MV0GOLkUvAF2U/0m3cQPxIGkkSN3bEGgyUBB1x+IWF jO7QdqwRIU3H1JpE00cxGYEpWKMzqjxemVZQaF4wOq6pLXradHYCIhFYRJfhqfCx6m2+05QTTjqk dqpITf7KnfO5sRkNqqWkdNHqNcza74M1RKyTIJbo8PQs284rzKlQA9o1QpHpY7rADV5qUo93crox yB+Ljl/eebmos+YycgbwsHAQmQMYwzDRIG1JPbwzgNhqjjY6yfISL5btR9h8osgMFtDizL1I4xxQ Zt8vBsz2fpNp8+OtQabG8r++L8swYYRZJOnwxFRmYCT+Z6fa4dPQFdFndYUfZOOd57hApfl9cSHk 5Rl43Hy2/thYwgoGNNf619toR5FdH77JymTDZh4M98xR+Wch4AojSkVDZpY+BfydEhxaRcKoH1VB Vb7jgKNM9+ISB5i+VIvrgn8jxj4LplpNH9iRbZrEe41ivfvAOvt2Jek5qjFQaCfQL0tShzAkGy4X tgFZ+/atNlK2tfZRlmkc52dlXJ0SlhYfzc9dDDdZ37awF5A7719fhoicMvFj2CKFc6xgx66viOiR LTBrVFvi2+NZAAUDjtX/n5OkfEj6ct0HxE7/Y9vBnbDW0/8PAiAyPcRKk8fI+lMn37Juh1u9X5Q5 jBP79iMBxJNIH/fZTlIMwZYtXIihCHrOTAtc4bOf+KiotqzOBSOIzEjoMA4kD6Jh/8S11/YIF+7X 9ULS4dVB+xo07h9K1VIiG0EnNQfK7c430Y9oICjJqaBnv1cAUgppISuj8c8k4xBzzo90VaprJVa9 vM1/EMZxp79UpSGzhMtXVCWWgTjs6MFJ9N+gx7mikBU0XkRmbffhYXAotGwYDf+mJJEq6oXZkM3Y 33D8PG90OdTYy/tYb9nPkpQTerKqwEIon3VJDR9zWZT4UiC0YxhoG50oLIsRWqhBDdzX0tz/EF/h 12BEhP5yiT9hDgixxFxFmjbNvLfjkrfn87svVVeoG44YkgVhZVGj+kNkGIv2CUw14OZtwTey0+Ln v80GUow5Em/TIF8A8UMIF37RKh/5EfElWYTmYYVeAw21TtAuhNbqvFl7wZzbGhWmUI4kgpqVUzie bvBBzuBlOM++qn1tNk9V5MIY9w5JgIaSQmrtkfwsgo6WbLzaEM5O/ia3d+cchuWB40VQPRg3st1S tAPPTaQ1YwB4po//wO/X3u6xJ7lPAGypPB6naLYY/96WpxG85B6pgWNREbkQuKCuu/6ZsrFs+KrJ Vc95d3F4/4UVoM53Um+Grn47j0G7RHbymogUGg+lxGzjEDXtHk/94vgzYqmC2nQeUR2VY2I/ibR9 UiuUAAZpTa0m6Bhy0Y0vjz+HKHgAXUODXOrA1/rlH6g2kT9qvVUNDdTciHla3PzTD+g/VcNqH0Um nlKrv6+ywM3aG8fIZnsWWiOh90UeYtGpe1CKnbrppUEh+TEUWA047h6/YONllMnoAo4vC2VGLyGf xBdNAkmVx1TRIrUbJsm4WTbtiTYyiV9qQg2b4BqCM9JG1U2C8OG+/SgXIhanIvr/yoNEt8dU+oBC PpBom4tu+hoaLvSCTtXD6ok7Z65p/aFK21Jyi00ZX0NhpS0dCcn+Kcu2XelaVgZBrqlozvEFktkk VyeG10qHg+5mpg55gtKAg1ia7fDV3CJOzrom6SbXawG1FyFJtJ6xZlihFMO0vK5TV7+UXi3OAEib MuzSRk2uQKYtphqzLVmyaVQIXgY2d5Depr68tGgukXBTeFUNxeJMVIjax3n4UFMR23NddGFOXHza ZJvwgwhHIUbA/YLSMvEXN7owWX7+4cvaQnzox+eyYC3RgUzQnhs3Aop7ulkRdOkfJW792YjBxnym 7kBttmnZxjt8PPFadS3Hd5OPXEQuFIFyFXE4X+EDYA/a6Mfaf1SeixXuAYqcFsrRMFSf5VC3UCnd 0pDhS7NxGyAtL65z2bVjmmUrpvTTZluTp5hJ6dwdwFrULZ3XqMq9ZINaqgXrfRuSLsAH3rDZ1SdI YE8jJD+wtdOk1XCY8EAIq7bTZ3LtBWjzpHU2LdmOZl1WCW3etvMY4YLtvLpLMqa0Cr/+Vkzf2T8f kw7tIu9bD/gXKHdwmyhl+6vT+og+pJOJQKIIBuNfYcHzEDqZ0vtLtlIKrcSuiJjm2+OUj2ZO/NLR 3BJxiCo3g8N7Pfcb+HmLP31raCiCAJBNJHOWOSK4Z+Fh3auSaOZ/NzAC9oJD8xjO0iWse0krDwcx 619M8BH80+V932j2IsGVcByzi300cSr05zDi7gDKxXzLbmNJEu46obe6ZlxYs6sya0LIKgAzgGAY Ebn7TVYUE7F2NFRlULk2h58MJP4Mg52QCrwtmzSbT0wChcsdiKZeTHo+5V2D8jcOGVzXRztPrLCR SE03IUBctCN0CCeb55fpZzVBXoi6LVC+kh4DD4FGd6PMmJ/VBvccwLL6FrSq66xiO+/Qtsf5wpE9 LRTKeRIxWDVupBj8coXjmjbr2AhSCLdhRbbPBMQ793RlDsfDmWzz3bpFlnI4LXBXat57NdOlrFdo YR4LGDsMmmvK6KT28npSJVja8jqvIGEKxYe6KnK5bubH2vOyC44VMWWV1YdCqG40DDbltqHr9o6d 0Q52xDsswLmEu4dany9M97SBHFJAfjzDt/bI/inrRPS0vJIXJVvUGAhXnVYYFSZlPWUsjgWrq0Vp MuG/9dwe7zGxBFZdRR2Ebk6A7L0yoMlrXLXsGUf9ZcNc7KBjd4OrGa8Sz4U5P3QOCEN9Bs4I7fmA 0W91F49pH7xZv9aw3CtJ0X2IpsvA7gVDrO3P0VQdOFbsNJkifC9MBfkGssCyzYt4GOZU3Zoev130 Uzz+LQ6bN65MwrC5OdesVjF6rN6yOMGdtYxy4++o5a4C2rqhA3zVlAhaIFS+uJMA/pmoWyztKjLN dPGopaAj99Z0/fvlou2Ua7TZAvvTqAiKArVjSeJoBXLnWV5ocXFmy0Xa7PVesQ7wGhfFEm7UfYl5 vgyhlNodmd5jWstmgCoMc4aikl7tAgWbyf/wIen8WtKds092uU0feGh19XACt/vPDOYIz5jVNRx8 l+visr0FNDiBQe8AxCUGOgDqLtOvrHzww7lxcbd1rRnRrML94sdglg9VOgQM1ujV+ReXM/GW0X+v 5+jmaBZj17AckCrUlA6uS8tE7eEwrO8Dau3XDWGQnWnIx6PkKi3QKjQpW7/39eAftD8tn32NOkH+ 52Cv+zQ4YxbMLvuFYwdUOULXp4r3Y/O8CilNBCW0NXP3k4Il40Ul9MYFp4FITOZTaUJEMTz/nL4p b0iFpnHi8cLNqSzZFdDw6HLl5eM5RUfb2fuICxGM5IIEqXp19xnXTXtN7pO99B0GLlCx3QK4v4OS IQQlE2SMTvMt4/LFJvb98AMrH67gC9zXi8Gg8Z7lafL0RFyv+xyoTKvRn4vGtLBQ4ZxYgCYZw1cX a0UCI0e1BGJ9h9nN96XPE/fI6i2OPUA5rzhOMXMd/8h8FnzD8QSOYLkHZXGF7BfluuEOCVYJNofT ppqV4d1RKJ/e0OvEnNLtN2fcDJVwH+sNDrlLYhZKvo7dHgX1Lz7x+FoRX7nTIl3LHDrE1DddUIN3 A5xIaFmumr6xlx1uKEWr+EqofevTGj9eNfkglKkK4LNOnEDvoLoECEph8hqpfr3ltg7F1h9ItRQI DufRAtjRrEEPXMT4NhTmlFUJJ4eDZMzno4cGU+JkevXItoNDbdkY2GmEuynHC6NhT9ksJYX5I3P/ dVBcSyGatXhu2Uiye6NRmua81nzHBZ0NmJJb0Txmdww1WGnqFx2H1aN7sh0sKLgvUtgfumJQrDpK 1I3JA/diziRgQjyplDP/MGQx9opEkPM5ZCnxkcE9y7ibhoyoErvI5I4aYojfSzM7KkaECJ9RC5FV 97FsbOBEyrAtdYid5ROn3xEMvF3e3o3ta/l6KBn02EHsJtGezHRHcX4cw96eqbvF5VTkaou828rJ iwLP2NC9AvdZQgSFK7X+NmK9aLOh0By29V9IcLRVOme2S+RcPt2vzXKZOV0AD5CEU41Wpzx+OHV/ lu4PRLHbuGPrJCzo4Sy0RKw6G6HDvSKEhQJVkC50rwH5h0E4JHSvDHQxVT5V1Q05GOzpA+OLGAOY udBKh8L4JVkfF5HoOSJaUKwMaPVTO3I34VplSSl3zOJTNRex1BEtLJfKPeQxtyrV/DuzsJLeyaDr QPxD63XFzJyWlIiovYGbQC2Qf/T9H5nqM7048dXXIVa1duTwiSjbag1xAfAyfiXlDDnPaERwXq8u dMEhUXjwCndLjrk7kLF5T0oUFtrcDXisEM5te9BR1RXYc0PGpeBeWKpacriFjcd17FQEu6HBoSR5 eQQYbjTcvhs605K3TWQPd8gzzXhBxlNBxAucaSoJ6A1bmZFeHx17SYQuhhjV3gy+3yxjTeUIF/dn dEXzLuPAY77HRR/15t5z6IUa8wGpNf5qo7lj3YaApZlXPHvidXy+J30zhshP2BgdwEboYtt0XkWo iPkSZ0kT+Dig3ldxYVg7jmJoC4Dov/+iusXsIRcRGwoz1koI+O8+Skutf66Lx8Q0Q77ISExraMXy ToI+f6nHQ9aMjc9Dp/O+7d2rmcXR+eLcbxmsasnt24WYOnKNpqEUYLJ9y+JDDz12ax0dXTPf9xiD yg8Fv6DBu0UvE6yWwoiB07iEYYQgawOpLP4Sg8/p7TRXl5h2cg0NRncdvy+EZmrCEnEHMt3c2AMT LSm68I2kn1nPasuI6QY3RdmS0VNCQ0yRw++3n2/CzjmJl+VpmBbDPzygXpfPwDs+YNV9JMIJPHcA x8MSNq4X4VHANPHaLHHQwjVX08h5Ccti2JeLOpaXMbSLbn9gjlojCf1Zt80GJYDk5Gm7XT1Fu2m7 VYXliYhbgjFrlJcqkKCkEr0dH++w7LLPhr4+yn4fNVov163SUTe4HsQtIBpfDmnyurSHxeyIxN7l oAFUsJ8cKHpST3xqtLmklI+ymfbNMl7eKqUNOidmg6qj2qyoAXW32NnRElbj9xqQ8xTrNVvVHlm5 XbqMfF/c6FD+J37KuApDk3ygU4MN2ro/dFpK1oSokNs3yilyp9tm77eYMKW7m581GMHVUnuxHib4 9HzO06MGPdxSTXqz0e1y4GLBjkVGRlt5XLRwhi91innvAw02MuWwcpqXZRdcGeeC5OKFv41r8r1Y R47pPFUG6OHJtw+PwnDtq4WLyNe9g3gSjiSgigcqs/dwBWrVl/ObOzN2GCupKvcQRPCAr8UTcwtO r7b4UTM4MoYbW2eDd4C93xa1qdE2dy5BFFtO88sScqfxOi9FvFaGFoS8hvQHrtfXhKGuJ1nNnb0o wW/LGRp7307EtHj5CXDLvodmkpA8T30nXQms+RnvAOAB2QN+hZCyih3lLN73t6JtDRsKUbqyd8eZ 3qIdbH9Q5+WyyXpqtOWPjGqHdwkrk8lnN5MTQMniMAHDYD/3L/RPvLZUWOBuC8CIkY95x+MYBE2O 2xmDxYw3c8yGxn1KpEcPZaQAXSx2MPx1MoxZ7/UcJvfOa6fO8qqdchIJRhvRdf6PZb6Tp2JCiFIO Pc/8141m8wCj94asz72kHLRCe7+fR03flXzYrDpiMHJ9pKYexMERQGzj7CxfuJ53t6u05+e1uspG mJ4boQsJqoXYRW/CHtg7WF718uzkxYE0KNfi99weSO6bDKjIOu7KxESuMomKfzpjU/Wyy0pfjj5a jjk5EUex9Okrf+KALV75NSMzDLGaPRrjhlomTYXPm0Hy9H7T+wAOYjTJsVUqCxgCo76K8frGo20x gKyZRlbRCJ5tq1/QmzJkgo0URadz+BQ2o63qkvNq478gKJpOQd9OSEXSdt+LfLO2jnqGG4mlRjNX y7POJRSV5txU0t7EP3h+qZzPftDkz6XHbwXvraaU8atkKY22LKiCLK3t2hdBeDpi4kYOVqC+159P mrz9Jpg3Gg7BwoDyzhmAVgVYWA5ba3njlcFeFDgatvt6aKJhuvpgtcUcirblJvG+2cKoaurK5INR fPKBSTDVupbedgaMqJC/xppG88mCPGG2bGf/zgQnDKdLxLlQMnPw9XwHyXgXzJpdax+TNpQnNZYR ibJCwmuMGQXDvjjxW4Z86pCc2O4X6JimxI7twFSIjExdVFBIMDjELS8QjT9s0FNGIUGpKQO/WF1N vuGcZlio7rOT+1MD8b6qYuNno31aVbaOVzX2lgFZaY6Sm158o5MKAaaJ5qiA3N8G5ED1fFwQZUjq UfwTzp9QZl1kc59cdMlmsGr4DI6JzCRd8Nk+YA901bKbIUS5AOnsg5sEjCcuXRl7tlFpePsdK2cz acazXJT7EQgoOVFNInSfnTMnPZAdnxmtPlgoWOhb5Yhx4wSVhmesny9lq4YsI6hR4HPm9yo/VoSt DgWvvJh64UNJn4z+FpmoLetU/G6FjjSAuKrO8ypKp6SFQS5sfMBfKlFuN59UKhazjIMoBxFwLYZI OFgyTVRU0Uq83D6ai2zN/kiL5xhVkXMiDKZd749yw9cSBV7xp2gsreIxrFNyTzWeUGx9B3ZuBerW 5OkgG0CqN3AHtOL2jO88g1rszoR9N6mA+Xh15lzUSYg+IsxhJHCOGgqHrnb0BezmO9c/S6KJOrsy 7nyG5RbYfhNxzs9ldRE6IgJA05IYxFOrKnnoqBuUrNcARW6LIVO+BR2FVkFpNTqH1PrC221YoscI sUuv1HuaWFgP6jEu3SAwYweFKQlcWGKsMiJWFAS2abe9J/4IDh4QFObo8lVnudJEDQWVGkUwBgBf gw05n8uHPhcB/sdZwm15+i1gsInyaPfXqYkoEy5db/GlLP4dEOFKu9YgfFtgvfOeYZ4cOihLcp/L ZxDFKxjbCbcWoX//JEEFIY2IuqPSvuusad7ZXNudhNm1iFE7SAL8Jdrlh/8mcbfNU6U9Kd5M132F gJq62850uDwzi657ano6rSXiy95+IftVDK4Nm6TEjxLtfYbE0Jv/Rt3a0l8OU1snBCWzUF3iBbPP MhxuQlg3PfZi/SrHRieDl5/XCjjQ3d6GU53H8DT3WlhOt4mxkwRJktMQKlLhuLaNYXUMDnBUmnrw QQy/57Z4GgBMBNFWXG85u+0SLWFbuFQJo7YcypIoiILi29H32hJuJuxPY3Se79x1eZ9c3C8RBPmA 8/2JZBv/8mXdYGFRT/cMUbd/ldEaat0dLkdVga64/ycu/pll0NjbNzRH7IEEa6gPmRLcaMhyYuah FB8rkKMg/CtXZ9ly7xS6SXbndRF12DmRrM0P3pmmQ3r0aPgkGVoZ2fD3jmAD9bMZYDIkm94YsW5Z WE16y6oIDbrA0HuLuza/+wzn52CX3zmXABohpeN8yOhtRum2us2osKeo1u12QwfBNw+zhPaD0Ntb U/mY/znEDKcjZpaaCqhPdg2/bEY4osVh3OxH3OkQhTrpuVHA+WNyipmh870KRXKHtcB9t8zMQ0xB bra5ufey4j/EGh/MFhJKrs/O09YP3m0+XGEU9fJOd8URqO4VXQB6JP/IbIy80rSE+3oiAYo64Nws 2MgFD4ei0ehR1OXRl3kQRMyCvhd5V9AnG8PBERoGIhtVh732jrsKM2ToYx9Vsl1s6g3isPkuKQKE +fegKab61D8Nu+/GVsvOiIqs40pDkUG3+Tx7FUaQNG4qkYtUUjuoZ/XPlkyuLnCpMY6DXhFEGTKN hJurV6Hde/YNCfAO2d4MMoX0DSAwwAEHyV60fMNBbutvzrdQWf5l0PxRsQi9scY7Rya7RlyN0AF5 278jV6tnP5Mo5efEUSkS34rruBhBVuWf85JSeGybskr2yY+NziDWeOC0QlpEmbaYti/FyU2BVIXk UYmLOvCdrkw/MIwl6zOYaMnilW+T49AaUXzMjXky9OaetV6uKxpWc0UlfN43tAWBJhJMDXiu7i4V xVAeH2fL/KC9YrTfbuoGMYTLrVUjTnRduEbiTJGaU7LIFPmUNjUy0Fj9k/6NRhJfk4snAH6/Adxe n/KaWVu9sSdh89c+zEkiefwUXmu8siD59za+o5Yqp0qeLj3Xo2drtXZdAnJu2iHxTJ+eiyPkvIK5 ZsXVg9uQjnZep+7zZMXZ+ghJIn5CGhaepAb5AXKeWPNQf6x98h8CEfDHr7rQ72h2lk0rheabaHLr 5q6E5pDUKmZzWCvLQ/pMnJ3TpbHccAgfV+RJQQpiaHwYFc8q69iN4Ky5vaaISd8e7/lPjJgg/mzF vxLa2NKW9WgSUBm0df2J07c7Q7a6VVsCIbH9ElpXNPl9C37nwz36aIQUgbnltRMCmUo1OR4/BTOJ rrb02UWPW4qjNBCSxU5L+tkFKUc9ptZ5A6Txp5mcVgppG0oM4llrqyGgIdDEkmXb0gLny3HNkUQ3 qLhf60Z8OZVTOmj5IzwThiu6fK5f/6D46o6XQklEQ6qZEaOmsMs9DAtrHRlxYpoOkz62NO/RSduu UgLjd9bNaKN1B4fVGn7VnQyKXWsJ3px6uq4qjJTgYxZ8d1t3cO5ZZvaCRSDS0ImU7bnusxXjaLff xBh50phs0i1aB+n625k77IFA0OXHeN4YDjcVExpak5x8RBap3YzxSKSurbnlST4ud2z6LF4RKXOi zMAWoPDwcYrHLnKze20Q3vrhHm5r+UVnhqpIS1TgmdxmZrvAjDB7h3S9d6p8ikOYHAxhQoJpBLfe +g1QOQKIRv7Y+e89AMFstpAy9QZ43HN8WiM95sW8ivMkq5sPk235mKknaAkqRiONi8Vv+zbrRYpa cLIsM0tIlLAo+aSKMckzbZm586thg5iIHruEUElUrk5+J5dOR8DNqzvulHY8pZwZQsdWMEhptY7j QuPkCJcAysvWDsnHXDkVry4EXkLEDbD/B3wpxePWyB9Vv1X1vKMALzfmrtdUg6ie/VSbly5VZCC9 H4/Lb7HATZb+sfu2yEVkuIHLj0CH+K/10wr2W0rtH0hh9wQRGi9DLBLXvqRs3HZV0LZYXcvr/V8t fVUhdvBno6S6vLq963NMxNkqe65bpIrtFghH9jmnuLpZgjhOKMzMTkmM3giEtLQzcO+Jv1fcXWJw 3uRFsaQgioTIchli7R2bgkchtSjqDgBCVCmSVW+xMH+b0b33+efOClh563fbs3apdgdfqTQB1ZvM aAdFDp9os4yh7clMrgLfzKjl8I1kssonB9DXF52tCOLi6nVD0r+8tNwOfQJu8fuS0xVXTam1zYtw dzBKh6l082o6p2PHCcsXKFxIA66n14nFV54T036ken0aCXE8Ue781xsFifm8mMF23Df3RtbzTUs8 fbx36cS7CRw4FOteuN7VuSgyjsDBUAphqRXx33xQCoNBu4Re9Jvwfw6qrkCRn/MHuQZkCltB+d/o 0+AGbVdKE3uYgFYhA6ABzxeyrhaYuUcKcA6L/Hf6Em6pEN5/hqObiW39zWUG2z05iAEf+9tHkKca wTe9+6Fj1tlIZcFLqoV7yolzAJiiNzpok5y9JcPWHfrIjn0EgLAiM4USoZwGv3LiOpAUu3PBFosG nFFFnfvFA8EM4qtKJglWvzNRBliy16kS1gFBvGmbYSFAZ81VW5ua8UTamQwfKqN9urPqna3pQQyi t/BGH4mq0IOE8uMarbKxUHIqRiidVxDTHWCBjxHbleUGvUzEbXARphyAd8mzDenUpHYSZXveQz9B 2BLO8t0Ab4pV1kCjNaoTakcU90/bU2hoXZvQ+H5xLsQ5JL+zWOu01xibdgpQSXkWAp3IhX7D4xO9 8QQ2wOvbJcG/bfi9fCzNCggkMPvwBXWrP85ENMDu3LbO/Lvow5bGgPzLUjFpcbft/ZDIOmotCvJr dkGQCMGOSLI1sXptves9Z6h4KYiLLJuy+GkIPhWSXVKji8HQcWoktChyNBXGY2npHW/T6uPFGqlz FBZbn2TVKdufUPuhJ80LJzyogjPloUhM8ZNR/02IyGI9erZflbvEj/1su+Zo2m0bKeMdKbBHZoLW b472IR0S2NKxTMHKEKjrN3Eiqd1acybylQxEigoB01khd/yuDhQdfC/NnLn80T7iEofL+htYfMhh w3aGwVMN8c30SwftaD5dqcqSwVZD14zz6T/yAm30iJWxTNU10px72nBzQUpLCUut5yvJMJOawdxF aq8MHLUNbDuWdYQnqAuncMtd337SXVrnCHTd2pYEb/FgklwdqHRPRHEmtin+Vy7eGTGjsBKvffGL LRz6lhnsD3hOod82vsqyU1AgRU67gOIWniY7VQc2G83lEiB1vQn+MEbeDXeUcMpweYobJUtFwWDf 0HieByk5d15HGHW/S2T/pvr7a6ZBB1Duw89eJ2fggKKuXL9tG2zHKn+6lNIPVleTwAWwED/3X8WO AR+FLvVQXP6E1o+vFfDcA3EjQml8yWjLyo933bfbRQSgjN7s0lbxYKQJXsHnPK17mkA7wBkifpfm PeTeYswh+4rvmZsTe60t376j65fG4pmZhH68jbrBgbDa3TFgXV/eQ1qgKQLlL7Zhhgj3wrM/TCRa XSf9+3NpgasGiWyz3ZAeRwupg8spMmXvao2B2wbAHcjX6nfJeAt/M4rB2iizJ8f8F5jr7Vm8/Aul P0arHfewSPpY/g6DR0Gr9fJWVf1rvao5YuPqLlLy1UaAvWoEomog10Oe0p0axOTy9g7K72i/Oi6j XwcRAHDuClbpuYQCY+9gwNNwXmvUCEDRHyN0rQgNcn85v/OWWqepq+ertr5Lnt7Mm+zDtqkwMSNa 3iFNlbFGCAOxFe1RM6i7Ay/ClbdrmHVImE7tMR+4XxfYOe91XEb0we/oOAxIdKHh/oCFB87K5vlv dTkvi3/Si6HSV+eCZuSnrzbCWF4gntoHe3W/RTo3giOTSAbnsp78dhdXsjNOTDqiwcDbPIFncZjH qD8kSqPkR/TSi4lkAlRweYTKK8aFtGcQo8mqaBRHdf8qiRN4oM97zoKMLHnk7so2T72bZWC9sM3c /iekM4Ff0PB4XUXVc1NJ3NISx/AcOIzP7NVx6Najn8IcR9c+Y2aLKeXBgWWU0ai21yYhPDwi8W83 n8qwEq2yalNluVrLSkk0JaQzfMUGBH98L3vF2nQoCBJMxPruoEnEWzgDPHM3NH20BAMUrfCP9Uai H2XdS/pFv+J2fG915YVwc0TCfHNGSVGPdh9IRO4NWnBAB+Tc9jzS1DG7R5nLwTgpi+NUsFVP843b gXOwphVCiOuc+ibynVJDRQcMYXWdF74XBz3RSv/dc4jUEHhlG5FwktOLL8JMS6zkqUf+njT/rXGZ YrOzvYAZoBRRA2hUw+7XV7gTU8iaBhRxGjyiHycNrdafkRVyhHD3wbnSDmcRiZdHNyvRwN/qQ+u6 NiLoeegFPMvdmDh9//1Qi5SVoczbsBxoYfJWvPZ5k5nx4LZSFZMItzz68gFqjYbZ6aoqgoHfIkqv bQ6tNQWPFJTkytA2hYp4hP3eKVY3Mv1mVC5M0H5vYQYTsw4BuowJxjk/4lVRVaCPzG0izVqRnl8Q qn2sHKy0oA1obDNvR9tZbgXnhMQ7SS6G58Pc6WWin8fTdVVO4wdbXn8wUEcKswaJyAsYxccAKxDJ uNjuw2E8R2iul+vb4FVEyPgBu8LIxGPE/xvlTAYQPLeHW9DJDw29wU5hrkZYSt9GPi0JN8sMvXaC iJ1vfcmDkh1N0sLrTEBEWqH4pbwwP5EyB/LnTRFXbaxjpYmiEH5vFvTdtWFgmaXMJmvkiN3tDeGJ z81VbI0SNmooJpDGq9v8fktWk4hufYOZfdHegHE/BR/2JIJFeYDgA7I9nC1QCCljaC0LuhR05NRU CtrOt9ddXT8y2XQD0V9uuZewHWHtv6GITF55xlalg9PjWa93U9n8lBshP37ep5GYURtCQKI7EIuA VIQzCDFw+bEo6ufQqr7swkrFI/WNvNnORylEf/u1SaAaD7V46dNxLh1i3ojX5W8JWyGM/0N3sg4C +e3ocIcSdU0/5H23fgO+HaGOKlGWLcq8RLiImhx6+Ih4qaawZt9hh2E5cgjCZ0R8jOKqx34X9N6v aIyQzt9HWOGIBP54m2mvEkUPa6Nke1YoUJES81o3GmfLarsjEPVk3tgctcqa7CIWL2B/ti0KRpU2 8tI/MRNn75gRglWx3jCSrfkGGDnhHLlGZg4Aq6ksEIIiWt3uQHmJ/ZVVd4HrHbtd2m1KRrjLo3mz rY4BOvBGwW/NLXM3dDl3s5INSpwa6zwKdgHs/x3RsB4SPOoI454DvK6IhsW/P44IQivj+RUxV27M szw/hmqWtgMjbCKCZ6vLd7CpRvhzsAacZLnytKnq4xElvrhvfyl3QlrOFG6ufHgnpq0cvaUNIbD6 7SikjBJTqvkpUkf9j3Ke3d5kM5fHlKGB5urqthbbjHlfYMCazd52c23sFwLjETbv8v0CApKMM0Q9 KTTUkYPmKvLtXmAAdFKensE4XiB2sShkSuLAqg3jMu8ROvVJZyfJKBgU3yoI5yfmmyiyV17g/Bpw /IoU5L6TAyoIaDZJ3rmPikNHdjrD8CUq5QwcCIfEkRk5LwSjC9fL1zqxAnqOJ1bG/5mBRl2iSRh6 b5T9BuzoEHOEmT95B0JLsPcVtlMpTlPRoHnjyBvD3tJBvy9mGyUrJx8QKr2q0pDNonh1J+Ey+GQi Hx1pknEf5/O1/0+Bwr2HuAWTnDz7Pl3GshCvpM4EoQTSO/NY/3IHCrYTKLQCodrFA1Hbab7FWeZ5 YmutjEUxV5+oyAEY/FFnHpQvL23wvPzYq0UO0ezMddKQW9MCMCY9oVLFSJLzESrinejF90zg/EnR 7NfAtSEioBVmjlGBl1iCTnVVLGx5JljWiZAdNvz2x26fnR5jUzcT5wM++/VKzwoZLmGCsLiWVfI7 9C8Pf5AMvmVHGV46ZVqgZIEfjMoajlqwHyLFMKWgJSuvEhxjyNyu6R8dR1DDqVniAcuv9GdODP7k t2Z+eqzumIV/dOTCA3D/0l4G09wAkMJwEtNBIdheu0FIPSbjKe6cnw7ITWbra0fkD30H5ck2UTog 7OVf621lrTYpqRpRpXoE8mbA+cFEeLL8xN+cVVxIflCm3dLQkaKXoVYHS1KKF3PYvAxd8mQ8tCZy Iy7CpiqF6DT4Mp4IFJMPnmUUblGeYhxC3Bg5U9SiJaBIQNS3DI4p+teAx2HwnE5pstwd61HhhgTt SqVRHlbDmLRDW6y+C2u6awVOxJRLI02UgME9Gd8ytmd70uy3huL1x7nR1hRFDON3bRmloX6KT9g7 TDZ+dnUGcIL/tVe0WyNuat2pGhuJ2ChmWI6Qz5yJtRAtzRqdB+ia8U+rvW36Jz6x2Q41RW1ZfUf9 pIhVh8MSbjpBYmVhmMlT1D+B7dcufu3PRT5wPXvPR90l0lTviMhWElfwTsxNYn0wfOJuLP1fnoXf SvmE0cbEcjYTM2KOgmNs/upK1F9ktlKDuRs5ZDQvN57WHNsuYaIVJzfG3yvL32i+gaT+jO+iv097 sdcaFLr7Lc02c04gR7ZwluhJJh2zqPU613kz+y0H+/om452rM7ps5FQVaNAU6jQGLq5PdwvSvpnK o+/DLPGd1GOnjsC8YiLH+4qQ4nCf88sTT3dW2HWVwYHsEFuvLp437cSrn2KiB/K3OsWJ32jZUUF9 E8kB44loC/q09Ub/If7X1fRcbExRa/xBQfmOuprIIGuK/z6wqQOCiBC1xjs9fs34gk8xNA8d7Uwu IAIF8sg3nRD/gFibVw+/8IJxpxQ1Wmm1BQyohuxLS5cGiDY5Ap9z4Az2r9+vnQ8vpeBC5pA+1n27 OFSe4aZ4XW2+bUeXn2hdS7El+dbOXRrvm8bflkXPjb9a7It3NB+MBabzjNAkN9U7k14mTgY3YwtF yUtZ3dv0ddhnTpEaQdG0bwpwmR2v5VUgpGkVzY0voLw1RiQR7x73d21Ni1Y9vVZNFYMVeVN7tuCn Xfpo0+K6JBS34YjzNOE+YeVI5mCK+qVYdSs3h7BEDeNtogXPxb29CzAiabGMtoAlDX2ah27+Hro2 416F9gkLPFaMMcJOGTHe2jZvimlwPCJgKFU2AmbAJOcKKVKCtbyiXYcp5StcbyqU1vuegO+klkec MGjYMbILaFfRSC1+V3s4CF4tlUTxSD9pKre0tAW6bEogEl4s+R48sldyjSYhhMY51O/Z9lQx0r9+ 4MvK4FDePtMaHdL0FJGi5sJzNRYYgfD9sf4sBF7c18bVZwfphLaOjF1ATYr7LVUTfiNwVz9Q8PFW 3C96tnDtY1faRZGQZiRQdNpxhN/KbGrqQjyyAYQWBpy21q1UpOe3Zj5RGOCQQh6RZnIRDyT5yok0 zqmayQoVLByzgJc5LBtVCc7A8QCtPjlbZJdMbRIIHpYuJm+ChHoi9O47bzXRODEV29NwDGYA85O8 7Vbe9rZSnP/VSwS8wvXmjTDXajenIwjP3e+YS6xA9lVidllDspyQaJqKG23eWKvGzfTUgq/c46cD f+qozfk/a/7lBVEF0yeOOrUMawoWZ9rOTpz/89lihdfBVEn46TV/aXdSGNstRR1MxmDQ/WCitr5I 8EkW04REL3ke4bD4thZX1Zxh43czd7W5O5LZ6vjTSLShU8oMMelobt0fyNicUsEgp0zo7afRl6mB 1GbEDf5F2c9eVndpiFNfKn4aR0toV/lHSiMLG+KYzUt8nMsPKdwKx5R2ygYua9IxjKeBMr5jNEOB Y2NMI6Y0zqsCGYqbhnlADH3pegaFhiQ/NuWHCRyULZFI8VONS4dduf4clU14wiz3JgV5LNNKIMlI STTy2ARaIBpAwpDdJScdbr1d6U3zSfAq5jkkvC2LkEGTb8HrzfzH1YV/omO0olfSEVXe9Qgx6hMT qZnQB7M/QKnlutkkuG5Mp+BHGNOZkJOm3wjDj07kkv6QNE2kbMC0mieJIv+qW4+q00oivXEP8Ks9 KUPdXhebW2UmiD+bDHD2JpqvjAeImgbEaqhekxWNyBnq2khqA17Ejb1/O9+E+Sqnt/c2s+HrHvqb nO5YPB1krg9cdatd7xyOSIk4YBA5nLtI/35KgXh2Hr/436mw3hl9CLGlURZreC7Y7BqLH3VekxZ1 1NonjrXwkj7cFfdK3UI/JFv9ZXrNc0AfdbJQytcr4Hh0eEMaQkCKtOsIr/Kcx83lB/HhX6kAldwi IrkHiPiHvAXJa0ZpT31pnhfQatE5Wew76TjErFV4flVBG9zPAX53BlAxAQ3rxkNWAZAV16t+xYXn ivJ1tGYbmgbv00VSYYvmsxEYaKcohcL0WXmPzCJYHJW5N3aZDcuftoMzmSc0lm+fD6coPxp9oUQu I1A+W9n6lOi2kGrmAeOKXuTMFyGRvxc+O3FN0PxwGg0NzF5UYLEqI6mGw3X5bBNQdg1u843WhJu/ bm2qlv7yC6gGRI5ffRfqmFxFMqz6PjpIlVeAYRjZR83ORB/0fI2ZqDGu+GOY5EfU08X3udvzJVi+ ZA23dnqehbIfzxlAR2AlI10JlDrcuacLgWeouubFmbB0wWcOJIr9n4JyggCfAGdz3/asFP3IDm1H 8kocPvoSQ4lA2e7H9K6RkFGlKShA3RnF00+qT3/zZWH/fN5Z2aiMuexHZOzedeyxaLQrsxW6GmJU yjSl1okVnWdyC1JoSCvHZKPqZ8+j17dhzcfn6YNTFOFQhSdUxDeoC0dVcGwpI/i90+f35/4CLyuF wgbj5MkfvUb88kUt6Ur6tEGr0GiIX9iIUUpyCcipiu1DEDbru5ae5brWr4fIoMEbN8FW5K9LmCLC N4l74aHGlzRt1qG94XUkLmVv6j94t1i96I1/TaETvZTxBJmnTbhx7LFoaWL+IiRvGZq9TSnWExf9 qhDUOMrdfW/X/pd6ahMils4JznDcXW/+djwgUPKGILOuvjmczMWnXyvlHYFBqQ17iTaer+1pVF7s gfVzlbNlEXSsKtVaKmWlGDQ+yBIDVl6Ku2tClSbPQAI6aYqQ9lmMpwnxMpZ39CptFkjJ9VtgVJEP eE7DNu2dhddpLSH6ygTzl5QABgmSK4DBo5ruf172YY7Hqlhj12dtvpjHc/SQGaHdQhjLkzphA8mT Ezt3wheND8AnMYpjjnWby5OitX6qUVScRMEJz+O6N/NJwitSPO37szi8jWc3S8Rcb1xkt9IOqb9i FX99G8B1iQdC0JPVw/UG3i0j2Fx/tc3QF2jrSE58oZWE5wjx37ajcxqA6q/MOBaby54gAoQeheHt ga48GtF339Sn2Ja3aGMdEVJo9Q4IdITMWRu5axxfOLdzJlVRTHrCEBqocFqWYP1tOdvCbkCSFMOK l5ReN24Yh9N7/AJ8HR0wxpDe02a2yogGEhH65bxa+adCsnQqNZ4l1uyytrUMj1YtvxPRGRO2V+3Y ij4TFGHpyGb8tfdCDr2KxLhE/Gwy8WKBk+Xvuno8tltv8GBKiS+2OdEpkdivkN6vE2Kqhg0AKypO HEZOm51QHdkNBFap92b/aAKjLVYO6LjGM4ZmSx8ZLcFIbgv8EuimVx37vx5k+cpr8RZMQkaayLZd Iyz3JrWJEibPIQuJlUzg8GMFirG69/bYCnu6qgpCNJrt6/u8u9vZEayDUn7xRTDGR4/dKqtTuUE0 R6cFbpjQn6edODTxnt19LBfo4+8o7rsFiHEPOXy/42IoxNP+14gG/z+6Ekui8TK4NYI4loRub/ya a2iwggQ1Z/1HzYLnn581ihM0GdAB75lXHTMI198iIo7JFBngyqm4IOkTawPpGl67gOx5dwl+SGKV TOmKHBUaiQcmFTssN/SqvdueJEwbedX9MghwXU8WAb10a1AtouOXk7mKKfGGclWLJ2k6SlEUKyqK IsmiEPg1GA43tAW1G7RtGRQ5vEW5k0OAga8fY/xqRcXRYALpL8gDQDyRdMhvhOsbElmMYRG98tgS x4wW9MNCcO6nMglpINeacWaGP+nRyXeu0JeFuOCYej8kHZk5TCxC16oO6gcbKUHRWsly6P9MpBPX DZLdTHZ+rFsA7kLZbqc4o+I9Gj4CiBiNrq8OnT+a0zRKhdEy9mOPsLhZjWk5LBFa4xlpL5zuQskK rP7CtppwoF6B+iqF2L/AVBeHlW2UstRjkBqKaOgHBxKxZWM6GyA/Da7Num58ClyTAgCd+spZBXJh JfXPeXwlFqT7Z+EkK1kTQb7lwJxdl8oor2Z8YVJVgVCKM+FC5o7Apeg9CeBccCCpguu1IhdEQ09t USlFPChsHkIAAYVShZbI8+k14V/SDphqcPcv/uyKzULdly//qO/zdf9vmxQPTSbtUr5bX2jir65K DBDn0L5WcR0zxq+vaz5O4npbZOE/fsaXWD9CUCBvfj4LQJIgoLnocD9fnCq9WGoOCbZstQ2eXMjG oRM/XVi6GEXQSzYe/5Mn5khwHHUP5JFYGAe/jj9ZiPVNVL9e5yi5hvgaGQPV5CMevU0yt8Ugnu1F 3/MDk6xgnZ0rXarbdamqX/v1A77bfriPpfqjmTYJmzLGt/izw97ovYXyBECYvr0xAmDTCQk/loOM VyAVINK3Cm9eBsrE8AyIokyuPATNpPQ07wCOUDCWKLQ1qefOZ0ja7DulKDsCrY4SWBhygdNjsSQc M8lZAJc0AM7BrIjhUBbJB8V5fmQMBol+HOS7lL4DlBkXTJgSEm065aj/SOe1YSjCDJrSwdn46BIO U3foz+H9VB6Sz+ht9JB5/iziBnNF4NXTZtc92LbPeIbEvwI3xgio34XR+JFbSadEchhOMSUl0R0x UQhgkcTa3eF7K9d4ceupa8P5gxggzTJWS4iQ3oi5knuoLkAVVwP205D22pcWSUoYprLkyh3nzSLd ckzpofH1/tWOxXZfDMxo6xYBfCIbRmOBAEWjtBswrUxdVlqPV1pCaDTCKRv6az2Ia3XD8/w655CF hISeuj/ABE8vIEBXh7YHQXYJ3UqCckO0tCWONofk0NvziKBoKOnTyuTFjpLTXB4+jViJvWFNgKGd 2OU2md2J0r2U1A0q+nfWTG/wRtGzcaPMc4oIw9XwOH34bVtcA+LWIbwYcbJHIiGb3vhHS8qSfVdB KOWWF1m4QUFC5q43EYpxH83Xhp+XRLicYvM90Fk/h5k+VWMdMHJEVLAoKPkdtPn9UakIiVfhkvuU YTmUth9TBz9txTJ2k0OoX9+Oe4+AD/P4TY+e9V1Dcnx59cSjKXC3NXpEmpHZdM0W1Ufd2FBwmrXU 5WhVenoVrSzRA4ue4GADPAZ0n5aj6s+j2MvlYYuf6bhrNsaxuDeBDMpB+ADMRp1eLCdOYBKyYCz2 +rnlp7rEC0fMbleqGJq27/E8omMtUQ1ZFQPwgVQ+4rHOCL+hf82Eppl8G1ua2AInwz50AOAmVnlg mkM3BtNxbpjpYxnnDWh4+AlTU/cpE7imGj6O7GBd1Ef6ccnACCsVTt6y1yIZC4CHo/+KncTKcfTz /SFhk2GMMNFKrmT2AMZvWYChP10EgGVAH8VnY9WsQdxtaEzUNl5HnApjGgl4xJLhvJuh1MA4mJsN ttbMZMpoRRl6RZMsLiJge2nFmbrQGJ7mAaZ079f4GczctdJD06fczdHwZT2pA/Vqhjsii3qqo8vJ 688NOSFeB18jLqb6iB75bAaPkFikzwKwymI83EyXEAaDNr0NflY5aKOCzcEHXDfh5NcM1jNwpg2J u9Ga8TQ2o5NzdMTntxPIQ1YWVtfW6Hh3m96b/GLerqUkMnHQ7rPAjaJUcb4h65+Xn+mta2/UjAbL cXYQfwZxlSxJzcwnhoUisM8/gRV81RY08Laf4aTXoQBsqnHLljcF69RXMt5dOhoGEeJPucI4xFwH r9Sibo3b5ZL/H468cuMpD7QF4/iT4Ltw96AoqLkw7ous+mWF8wboJW1/74eAitGYYbDYX3pLDqRR i09iH31Rf9JpLjzOsA7hs/gCMvPHQF/pHM2jKom3VuJ8Vv+1fg7NVVdmu+X5a+mjejuNcd9rvPLx T9nGdbsSQF4zODtkcUkh4xpslX1h+2F5lBhLQt30nD04if9NNM5Ht6Wca/AyPCVrsNYJB/TPs8v4 6v3h2pxlx2hXVcZizL5g2XzwlVBhgWLwfhsODIiHWhyM8m92WmLaEKR+7Ohi5POXNoKTCiG0yeU3 aQza5HEdYtcY+uylLMHoUQ05Ba5MYlsHKl0IQhm2RmCckqDCPILNce7g3hYk855IUlccUNMupNAO PFH/cq7WU8YqjImE51dVjPMtRce2LVbJNJ6Dq1QXI3ty/k0Bw/y6+YkI4wmZ0iPTnW30yzuS09WZ E9/GsbBUIK9tBrFZe8CKoH8qOZ1L3vYTu5tyQVBV7ZyJWIA/RJuWetV3X8KkxV6KicKvdiSoGAfr NUDwVIRN7WOYW3DfpIqZDqZB9ItffQ58iOrV0uS5ChXQxZSSulm54olpYo8KAi6IIUM6qybw1ZO4 TqQg0ysO/INNdhyk1FbORGDP9sslmT3QWRtB70ep+i+EDCLEVigm03hBLFgR8qSD5FWuAENDlJZA sm8trU4swNImn91/eLEzqyO9csc8RdNa222rMM4MPzHI4IWnmcFDU1cdI9VQnvsGjn6bmmhd/Awr O+XwEs/xPbdjkbW/gZHRk1x51RxjO4OdNKp8EvLW7JxU9p4z+eoNOOa0IxDA8Qain542GUyT9jkC NvBVNCPuaP9LiegnqA7IttV0emYXkvE2CQ365jWG0FZ4k0L8M2MznnMwDZAzC7K+xy5v3YF+NFvR 9XaZHLaRs2nUO0ZJlLErFbI/WVYY1IUC/aJxH6vy2x2wj0z6bUWZqVG9C9hH4fwbXU5U/KXmARB4 D3+C56oYlr/K+tD9a1Xqz5DEfS+PHufJj7sKhNx3EAM8LHNUqshZyUsnfgfD53HAim0CEXzq9EZn 5QxFa3mSiS9EH93bYWaVzqHzwZnloWN2MGpkdwx4XYaDlc8pPW8BK6C0+Y5C+x9URXClr5fWSZM8 9S2g7pV3BEmZx8/DTO7luHHduCod2FG40MUa8er1ynFx0HkMjAySOtdHrZEjrdPPrEU6wFn5RAsg A5ZrIYhpVSXSy2tjOs73I6YsjihwHA95MR4aLg9uYJjo3DKg7MfH+ezvdBIefUoxkE0cVHl89iCv pmNiJE8cXs4fFtUFqmVEXp1tY8Gac/gea1rBjsM9A9ycDFuPNuJ+1akHjw9YQds/6WfgfzWuyVRe LLyTLjZbE3K/XaiLZfawq+137wc+SbsLQ9XuCUNKN702f6OiTUW8oAL4JfY9LeaysVkqhm79bYKX FbDI/Hkzuovn6r35Y0Zm9NchRNJkkjxVEvUnWsZUFuuvW1D9SGoqlQJABBqZHnJ0O5l1y3eLjuDP +AngEgNXIrFkYC7TC45EXgWDc66kMC/c/bAy/m/4xYHE4eLCSU/bRWZ8vr/9O3Gn9V8GUq18pXiw QMQ6vyIdAVLNpFN24X6DcgvwtPsyuD0lDH6YEiJAba3/2NUel9fffBCQt2Ec0mS7m9KrGmv8/yYN vFUXxE8j04LHhS0EAOfEY8vdjZ2beZd+ZOCmCBayHuJfcPX/cw0tVzBRaGoLCD8u9QKei/eKIk6r Tr1ubdqKzqNtM6re6tvjkUtGct0XNMvuHDWsPOMOX7i99N8PFasPKnMBDL1ZNgOuVGGy60ANTy+x ROZ9HGwbSnfQgYfeeKjZOg1xp90kqHQsNe7U7UqK56oeT/zmm1yBsIyATscj56zn5H7NqUp4GnET CAAmFTilREYyLkO3LjT0r+lUfTSx/BvOkqiMKfpA1NljQwPMcn+sIGqwIv3Xb7ArTAon8na3YtCY WE5GkvxomG9cu7Lb9FhBLzBaZNm7OzC+TNQP60qt3gMUxx5kW/krh0a5r2CwiJYqz0xDx7H9Cg2q PKjXSDLBt4a4QcUTvoBwduv/h1eIqiGisMfNbi+hg/U/6Cpe+2S7h6kzf7EGvaepQ3SilCxLVVo5 dPhnrbJTZL+VybeuY8Ntcmy+mA+2FZUjzhUYJGtBNm4GCcktyOhXdYfWpN60A7FuTnITPz8q2NOU ElWyzgGIf/yO20sk7P+iAJ+GX1Lckipshch0M3xrci9KlcD9uzn8k5vIF5DyLZJJsubIHa8BHtdE XTe3V1zn9VXasbCRNguDF26GQiixWO/sdW10SvWtQL3S7hNPgT87j5ZpLAuCF/M1lGEAQjXLxcj0 ZaU+Yf2u10ZGPdcMC6GNs7Fp9/3ADS0Uhpwji7oNQL5LQhCVfZxryo3Vxl8GtKpg1HHCNPJQcuLw 1pQYG3T/ZKjiA86bBAQBURGvkMnvxrbkZfB5rudcg18+VutIuYhPIWb3W5UGKfEJpSETwE+GmjdE tyjPEkom3Pu+I2iwOY6UNXkNY7oLFPZLTz7/saSBWmkpcEccAeIjlZM1amDSk3gEMmr5I1VNfLaB VI63ZPLWFF/TT0/e3KHiexIPgRkkDqPTwbgMeq64feWwVBWqos8Cz4bEByFbWYQsDRaf5I5B0+40 i+MEkQUihlcRf/OczGl1AHIpOtho62w5d+NCWJdzz1AmhgGjpJ+/vpL6lWrLst9ICmdAJ6FJhCT5 84UgQL9JQL96XJhcDlZPFdyzB2EXJK2hDNURBZoD3O/ZPaRBCEU2D0bCcg6dIT1US/uIVsgylBl4 8/cofKMvyoqXt/TGS4c5nHMAKIDTMvmi0Rwiu7l001voWJYxl4VcRG68NgyMZN/MEDdO7I1Owgjf QRsi+X3vpM2Atngu9aBFFPeyk4dNs+NjNu2L88HLdB4ZtwLWFnQp2ollnm14yujGZ9kkTBrA3gO4 29hyRSiyk69z8VZ1OB6LzkebHzHm/CzvxCPtlEdDgX6y0FncCdcI0yaFbvTxjlXA9KcADmpafTc9 18/Z6HSyanW9ncZU0+OeW/3e6HCbFLKnCwvZX8KQP93VOFXjGzK6LOTvL+EAUbMm++qOQaQkGo3+ nfRYX+4yiMP+Wnxsym3Ku+AVwZadZ/Za6K1RKVdNHSkMxgGMrH4i78y1XiCnsBhcGceVp46Js7Pf 5DyxN3yO2Tg09LX9Ykncp+Qe3LIu9Bbt4GAs7+AXzyvdCfepVO4VYpRbczG37nrPS66QyXWsyJSb +uH8z38reLBUmwxU2vVcs5ictLGahL+ydvjpJSkzvmdRYw+KIlwmSD/6OsHU5DbJcoiJDQmYkAMv lgk9tb1/15GYOVWoDMsTSEFIoO/gS8j1xp2YcKa2OFUgXy+l9AqvuGlfEWHcU/F7dj8lJ9u4yAQU KWyj8ODlVpoCGHjl1iACjaxaaMifWqlN4VMLJo21ybE1q4hGRtfMVfXoiilHvul34nX9ZXkgwwlE O56GVdCsk0j0x++PPH2IA7HbhJ1ZU5ODDY2NItiwQeM07nrLp7IpyBcIhfwNZ94lss+KKhzL0Wz5 arsXKDN22oIzsxSjOgE6N5IhPdUhQeQKcNV53V97edzmwkJbnPruTAhEyYk/Z5jSl6yDar4vgy3o bA7ZedKAucIjx0ClP8+WHcJ7mYqc9PKZSU1yId8MhV6pylsl0DMTmAfuXQBWlSYtusOKPeuw1FLF mR78fKh1mT4lwNDBl4RlELaO07n1pF78vnmcOqd0eYS/EVOxNtEr2WEIOqs2QEfGNuZ1sEO3ByNG 2bVSDcfaMzZxmzbkm2LKmf7D2iNHyeIjPtHJ57oNeFRZhCE2DtfVf4RBZ1fQsH20s+LmgUS7LD7+ Jv/MpZ5YvnNRqRGly6atoGHPIVGJJ9lyuo4YzFBbGiBCfhKrlSzJnqK0nhPqIZSv7w8SsBNCY6aY 1kN/pHfssUcREDe1o66d5eCG1Tpe39aKBHC9cm6yWEBRtVSSGFqHYu+Wchlg3x+VNdgvKhCKU+d+ CS/oCW3cV0IHMlmU+qHGawRKKWkxUqc7KSBpQvyIChnY4Cg5/JHLnCWSMUv4BaWxGRkaJmbjLP+H 2Hq2oJvcAs+9hBVyQB0bTcsZQRPfhF1IEZKvCpnmT0Jt0LmVQ3TStLK3x71uURHHqBt0/vu1xIi+ ttdAj9bsx5KxWBXMJYMpafKnBXskZs6jH0lYJdJaQbB+LCtV0/zKFYeuvlj1WKfvx1b9Ot7lFwkj 1EgsM417PGA3jLTG2DwRwcm6CnCcuocdsTLwwO5Uyl3i1XxwURxRWx/SzhIctSc/7681aRkR9HQU 1OEs1AsLBR3VTXd1Xfz9z6Os0Sn6HnRtlUjS8+EMZEnsAr2Tk6I1anbFDYsT8h4LllG/0b4XM+pO jVHcbRMFpThRhprP8NQSpETNWC5UC/kGHWTXH3mZ1lTZc0aQ6AlVT9RVdImP8f20Oeh8xZTJ5ADX eZSGq938o0eodhgZTYwvMDXqFFe3ccHjldw75wasOX3FweD0oTSp641bnqnppxn8Tjues8tPH7l/ b2wUOvChK773gZ2Q1D73XSZCTNPIrZCWGtIUxa9PnidkXTk7PYgnNSWja8SSOkub0qlkDUuiKt3k WFDAHHKAoMvd/lrAP8LRuJ8nXccF15ZN/K16OJ30O2BWdtgkLMJi/KvNQ8389g3d3fkc2MT1X6nK 9uD/BAKoNAxK+4Sx2XM7I5jpd+tpn4mw0bPWcQN4EWBlPY4LmJ2zj4Skm42GYf9KP5Oc2I6W9Cp6 Jc7ih3oeZR1zokpC7qJweltdDjbCJhWIP2eskAIgzgV+mEipKVLMTvZrdtg9+/LaARcNiqHC1gMC P7R3m6tOGdkpB2UdfrobtlSauwItb631CLpoBznegSQgHQ4APNbLC7wpYNHIma/YfoFAQZmKvTHN iMk+tY0YG5TpoT5NVhoh1My6zmUDKOKGRxZqRXtPtyvC1kXYhwjBYUITo5UFvA6Jsd2NARCYfnq2 DQYwRUQmQxqvvo4pyUlM0M40aAXexqFsq6WSzEwL4rY/Y8NrCEV2hustA+donwL11tSCz4jj2JWw ZgYST+roDtuEVpGkPevFah1gy67aBgjir8MEtrY0AP2Fd0df/cZluYOl68oa4ppLCB5NMqkeBn6n 1VDeUiZxjjb2Fspy6ylKalr5cMu4npREVfNpUmaWf9VKw1eeJsAiFijgW/mVSTd6nvJGxSX70Y9y 2YecGI2zyuVm714771N5/5Mf/v2SY15HIhTToJWMyEH4JfU89skpvEZvH7jLqMFikfI/r+kOW814 dvlY1yyeIg0ECeB4TVaNN3XjJZfKtCLmoHbOUb/PIPYUbVzgLNzg7edYaLyovxx1TdtiP63KdZrY yvdCNJ2zWgcwcC2jFFw7Byt7qQFeuI7Mfofci3lUosW9LZ2A+v06rIsvVfJX3ODYJV0rGFSh+Hkx 4WcJ3Sp5JoivzdDbGVB0Q+bJZkgavoGTi6zFjjJyHLd3Q/oh6mpQOld3QXr1//iQktgPaDx2EPRi YjOpJ7KdAVFyDx0vDY1UURcLhwHPki5sfC/aK0+HOzey2k5rxhG30jq4kBqPXy6bSPIqGpbFBYSK L4f+oxhDI00F7jr07zqWx+S9WZMH6CCPTIRnZzdK+s+tl5GypUHtkQUxyG8VCddWsTXiCmBIBEJV vxwNsTxf/CAs/KXOq6OF83j7ANT2+mhzOfxRVPnMoyJNwFhXXb/pVVhjQDklrxi9lUzZJb+cRQeh QTltPN+e/JLLviE2xTWB+lcZw3UupWAoNzbAa99Jve8MauIC9uBddqCxRnHMOjMIgusQF3LGWAFm ztQd6emCrCdFFsYEwZ4J95JY1Y5z9qxYEM/6BPGIbQZj8I7In5uEe0BW4gEYrA2i9I1ZRdiqjkSx +B//rLhwghBKi5Jn+ZMM7/7nwds97yqgXS0G+0ObcvnnYFB5j0TTbxMoz4DOaRGt0av56OAIrr7J LV+YzDflScdaJplCKIkWoJ01ZHZNcmP1ZSzZyZCijXZzzTf5IFLw0nCHN0o9Bvyb69/bLvRsqKBX Jd3vmyAAkK2R2wJzvTdC39SDnw2dh10yscH5uZ4HYMduwa70LARD8uYA2LSP3xBBGYhwImdaSbAo aMhlLznqSRJDE3O82WLf2dhSQj/oOKPqsB0EL367mb1AtdvvcL7MZ9BQ3AWrTn9JlDohOx5qPHM4 IUFHeR6sz/VGrWLZxk2JMQdv6mZoHSouknAzc1qLKvB2G3ClretTUZQNkllLF+/sqqUpsLSoKpFm 4UgCEoL4KtUxvIvNq4HFUf5YjNg04j3DMU4v2VaL5II4seWGnwtz2yWsQ3e8+UCrw8Qf1s5gNkgv 9DVoFB5/VHCI+TLb1GPoMLu8TjuFmNa0fREJ3AsSMpN8I4IT9daJQpiqBn3VFIJCCcgBjru7A4j5 nHZwLQkbqeVusSqHbLSg6SBEJwMjY52OnIfHlncg8ibHWVWKpl9DprVaYNRtQMCUt5mhO/wCOdnv a+eQSexa4S7oZxqI0Y3uaST2Conk0431I/9CLwLs3MyW2ut23GsDdLXKmAf+9WryZLRIadoB/8yZ nGXeK7TuTcF4U6q21npznDoqJpq3ZFTKaeFCknrM5J+rDhOVHtrk/e9FeYV3lsH063mNaIlQCFnY GG7TJvApK+/hvAZG+xpUOs+tO8yPnDpAB/o0akH1Sucrrml09x+BwW1+PaAnWbc9mT9ZiPigADc5 XChNcbrKHNJ1aoJwtpG5nLw5gKTlmiaD+I9UxlyeZ1IZEZdnZjxFHJXzpYGajbxuo1u19a7WW5cw 3FJZgCMoFDuAsHmLzL6N4ypfHP/5cEpN4723gbOEaORQqvAOv+vmqs3rU80OSBG4eHNRXkdTBGRm 5XkhWwBKkAPlcBbq/3UyLWdpajCVnEHX83SeZlHKS7iW1jGCsNEaWnlT2i8wIK6I/RB2hyrIFM9P bLlrLi+GKmftGE4JqcYoh5HWj5D1R7bf7caS28APaDrj6BL238nUSynO0hI3ljeSiiXD4DeNWkyx dvHuE6zjEB4IGeqBsIWoejs8kbbcHFxDuI0Kaa81qJKaZW1iRjvdIjECO2/vVMqgLbIiqRSbPAxm j0KvMAQ7PoPWimqA7MXRn6ONhDz5SNcgR2Xk936Mf5fzaAH+51MrPQJEzjMqYKuQI1K80z00QBTN STDE+WrtrO5XiR11G04yKHQ5kiCCc3w+G7hK+N47BcOi5ZMWjKrOJejpoSGDWaVj2cnz4EOdXQVs MSc2lPiE7CXttEXzqBbDGVpcjTJFmnp/ZQdYa1wsuopKRdCLVxDCBoXoELg2PRKFbutNgQw7J7Bu FqjX4ABfrTQvLyoRvJuM8ub2Ra6Dw8i3fMGi4Qu6JbhTmf+CRSVjwQnLsHeayLcdN1QVZvBmZAAm LiOaU7mDKiswTDLBWRbLgptddNTYwawCXSKCKhJYrwx+JdsHfsvI7syG2MK0bCNpdnuoj2gIU1Nj 55zn9MLr2wFqTZWAHgpLHaNH6oNLyLFE5XsS5mSLdzguu/SUoIu80K5spwI7nz9eKx9wt0GpVvtS wpD0acHv0V1Cmyzey15+jU8g6yOtVcxQYGr33YzPxP5cOs2KFFci0euoGJIc7rOR58KZDAu2VgZE I76csPC7zjZ9FNTpc/2qow7A5LN1W/ChpFbcCpYGRwmh1FTnbBPPlET2Bxrbxdf64R2DjUD7nTvf gmoWnK+ZtmzM2kxEu3yx2K8YpudRh5jHkLWmNIBGOS6sxQHvIIG7fXeQrglAquibCfs4T/bCLri5 +tzBMTxQynornC30XAkpTDikql5FqnSlIIqlNWdo0FuKhp65O9JIMd9KZRSCpQCtwSxkBfH5LVsZ sELPFu9n2qMrWjTLFOmmkpNeFRq32A/22IyEa0dBAZngfnj0kzcFAYiCS47txijdVFCd26XIOPur oLVdoAd5XvUvQkNxKZRCiuHFUzTjTb8ziVjfpKYTEmWiqd7UN8FQCy/NnEX2/e6Pav5T9vyY8PcT nDa6spCybZiF/zxxY/f4yv5qWeoSpaZYFS/TQ7GuyNm+MjdWqQMpE2WoM8UoYmoUDxM5EA/hYFxM epc3iUrl6iXu0SbtGgBImMxxU64FXfgLOdRK3jGfPwENuLmzy3z8RNojIrrBZF9gkzGqBrLtKwdi fJp6x9i/nRQ8Fpio/fZRpyhKdCARe7bEORJnQ0vXSQVCGhrkryAndQQd4SiY68tgLimjPzQ5eFCh UWfoUzRUFzjEhRbSz4QqogxNGUpS6g3DKU/NP3gkRK8JQZQDVe1VIRRWzgZz/LOqoNOpqtwfZw0f HB3WGi/sO0TSYFtPuTJ+M4rMkvP00tMZejmYDlnrZPQn4wlbPY6L1PVWYRxU5O1+MPSYTy8CTzsY PVYRTa2gmY+ytT5H+kCpvReU2o4Js1U3OSTZC/2LWdcGYijGP5+fCiaKex1osRfjeBEQL5k4Z52I ZxUT7sA0V//6E5xU45wpuVTxU1iDr41rt0EVKUeIRCOxBKPzXRDk5AoLPcIOvl/WSfTU0xjm//Zy BjkIC6z/VIqAnIczt2VO0EdP7lVGS1/mTfVXjaXUY5u3fdW52KfPjl8NnVE2ee22831vtBJp1bNP 94G7iB8Cp5EzVQFsaN4hFbSvSUhOxBinSh10Cl1FAG++9mV+Cf/joWp7x+m2MbZ4dQS/U4sxA+Kj 54uR+G3uYFc7JXY+g351G8j/Le1jy8jPMYyzOG4h0H49KoghOsrvIiuf17WBncof/24q9VJmSusM 2UzaHSwVDPCjwQHbQBmn8P27xL1X1bTlLx+55MqbCtKYM2UrXUkebw1HExgyieAzvPDGOl11Rpa+ d7gWr+5i0eHft+wxywMWYyWD1Xmvak6Ba2W1fpgdAPm8LOi84oVIsv4/huDvg23N0qKoUV/NGziP ra3JcOQIItJIbn3hFyDgkG/mYHu2Iltelv5f2Gv6mgoSC1QxXHI0ZTUWjQ4S4b99J4grR6FzK9st 36rOEnqAOLaG7nbsRAFoOOUNEp3diE7VYWt1UYpkPOZhJ9lAMOluoCDdfmc6LMQ34h58/OyZcZYb MEfIz3jYZ2riW12ajF7ildy0WPUl4YiqzpHEDvEyg+rWGNP6ZfN0y1urvu4qjg6qG6gWSsr/dwmD ++b3jcfUr6Gey7BwcfQREJL6v7aZGlB+pwszEM2yc5dyAz61bpN+Gyx7FFy7N3ycIlDr3Ov3qXAa Vb/jwx6RRcjP2ahi1JqXZbrMn3syV0SidNPAXICzRkpgUcH0/u1Rbmkg9W0b6LAcAlCXEg/TV+d9 KNNp/dV0t0YwZv1CJnyemQ2A2DdXffxi5bRGIoWpXQDvkNaR5Y9NoLkc01BFKN7bwR8xPA/vYiCi OdaE1PtOEqFyI9hwMWcZzd5Uo+FgbxOYEaKrLaIWsX0/3C+eIOox2r/YN+k1k5vwy3bOvx3bGZi3 NC3KYvRt5DaUVHr/F7jsTEPn6heSUdO1VoNPOERSDRt9RvgNb9n05kWNPkSaqPZvXsdHuRo/y/3l 7aDcRzUgOmL+Ne3EvObJTVlnOtX4IgD5Rzrjli5EXhbopDp38BWC6XPJqjGRJQe0tMGJ3YNDMRU6 3DbXYqKuvNp3sj07Ax+sySijzmhCIgob928BXTg2RkZlenvmnwwgniLLpqn/Q9FJ8P7PLfPWiRh9 QieAmdej0vLoq4wIpBhUOmI+zgnREFzPRyk5FPeViiMmGlKXBfeNrnAvxqtKUTJFP2x8hDDvXHSX t0sZpwpez4kVEw9w+VIEKE3DjRPnFCCxJDi0DaZIcnwrTCci9OvZEQ9/nr6SBCRydLIjh/tCc0FS gO2W98vGIyHJdGrN0aGoVaD01eU+nXaMuEibl8UhWN3sP2p88cu/5CTUn4IuUTO1lzV/GGxqRMlq UuW/DoMuXT4b95TRx2heGHKM4ONu50PWP+dv9Qc3ZoWJEQcCeLdDm9Ei8MeGaRMWyOJ+R92gJD3n L3qi6/QKDMgEAem3QiEFyX0eFrKTBNSSwNPhsar2XLjx+6OL1ihyWf0GWAWRRJt5E0Mkdj8Udykf lfKnbIHdCZYldNmxaIQQQ2uNkyTXcKAC5AVqkWvEyVLwGjF0TT7uxAdiaDm/5cFnz4mzSi1gMmoi nHXVKF7fP5LR3ChFMrJ1hGzNE8YpPX6zNfCZcrXDEZxzrDQcamHcFpp3oWVPzUUkxzkPJYoxsz2/ c5eyp79/jtJkOzTMM9pEwKFi1sit+z73RdF254NXXdAl4wA7y0JiBEUlBbimrpaaOESWxvGk4iNM j9ERYLZMkaQZhu20/LwduSSNvuxil8l88SeLZ9MR+8KQj3O/GKVBg7MsXCRYKT6QKcOsr18UscLu wMHRKVH9XyB+IyFoE5DTHxhIqO4rCB/b9/DaFyU+iIU+9936qDxAIt62YF8wvzad74bh+HOXTBAN n8o0KeFoqMYGIoyYlFiM2753Rb5kDFRs/67zVzW2zawLV73p7iqKUWlKXj0uOKfFMzBgcOdwZ431 3Tk0TmNS5kfohUqulqBUltdpMONjzltwjRes5dq1WmFYahobn096urroA3XXmQKb0B9lhGExWD5b bt9kpXZapzvc50XG/PJWfF13xytj/8VjiVOfupYn7gf1YNpxCGdBXUA6xPjuYZW1VubWYN+YZDNR bUUSOYmydj1bQLDjkXkktIt1Ld3b3WWsC+GdNddmWOnKeNow9bMFuDTOxv4tMwFY240e2IJm6P9P Ez8bQpH0up8Ebz5NOg4mPhxUVhud/u1mkdn4C4oke9QA9yIE5gzKlMLm/7hPK12e7xcKElsQJzDF IxBhEIeWcAI0pRr02h3dkH1Nz25H+wPmTzWjQzmfYzp/UwC/gXhKXctgM/0ShAIoRaWTIaD54WxQ p4Kj3vtpDA83y2CRf0O6TZScK7BzFJqZqHuCVrRxHZsZlcqczHvbeHtkLZq6vY0bopwy0xuiyYPM +jgjBs4H4hsKbQKfxUNz69qYtCXsty1e11ZT21A4y/Vy8hFYqXyJCLIgQAq4MNjr0bq7qHNxtRS1 c80ZS79l0zqxoF4h8bK0qBGe6ACvVDrrZYRkyE4C02JSiYVzy5xt+R4IP7+QukhsVYQorFpH1DsF sTbbluoXi5Tk7pRSpCMikoF4JrHjYaZzB/qJG4s+yvrX/3l1FjqN8N4/aet+AbMGvOlaXe0hb5T7 jrvc2MD7zQtWIesBgWrapgygLDmnOW/FkNltveqGvYjRDDH41Cal6n2f3rpaZQdQYwFdrDqO1Ttp MSX3u6SUsr+NKrwEoyyEiF/tdM2igklrHZwStEOYVJKdSeqy3P7DDofWuTuUN7hVEBAmKqBxN+ad vm9CbXmiDE6b6JEwlU9j9qh7ZGSUSSlu0+Xd84ogBSoptYBFNPDah6CxZC1v/9504sFtBb2RepxI CtGpNRXBHaBsnncrNWQ1S/yxnKabYRn83aJLMpvr+azQh9rDGVHJbpnWeWZ6Jy3D/KnAc7h7Qp/K QEPa3QYcBCeIKXPO+VLgvWJ8sIWlgCJkgvpuzm7n/EwUwpT3+tci/d+OlEc0r4U3blTCLdjgltqV 7j7xEn1GxFugzvaeDwUJJEb7NGJNPqKW78s69AO5oXGiT8r8+OshrP0ikTLlvb7L462seOo0JD4H 5/37zxeCPLp7roSdpXry/bnuSC09rEe59CUesNa7cn3TQ5M+nxrOCPZdZYPDMNGlk3dAlDx9L8EO vpsPOm+m+pdwCAZ5k8DhBZYQJkswC7KkGariTxTG9YwE6hTXSWq0GRcjRf7Uqf3USuRStk3SPF8E BUp6HFT6fFSPwOLAZJLe+PWuaaodRSdlfddE18DEMxEgzTrPHrCAThNMP3uq4vVi4wJ+hDyuqONO uPULvGukp13eeBE39tvde/3H6Rm1sleEdJlcyIqOe4UD7rLFxGCpH05nMrs6fKnxhFyLJ+cCHtYp ygllZnrV2bDm4JuLMHopT1CU3SoOjNmHmhf0+WL+lH+uDKU4uRHDNTmcYMXPLYXDPnBkpDfGzuGV Mky1KrR+nXGwKvQ/9eErbqQCvoRHXUJVs/SDEY3oRCWB0RSUDR50c3Lmpw47heUlG3U28783MoZk e8h27dWglHC65G4QODZn02XLI5Ag8ukkJBK3HZ+jcvawyD8Ne7yxIE7AHpomYTC7L8eWIMNtY5zv enjWbvL0/mq2RMl0ekIp7kqThY5Ioi45wQLARW8/WMd49AsJdNtUXZKeqjRJL+IbGqr+xKVC7uPC pItMr6bi6O/VT6nojFWa+H1Fa65yK/4Y3YQ5f6rBB4Yw6L6D3hL1fKLt7YVU27IZ19bA8A8LzO+c tJllJKPD/RudwhLMcDcEtL/Gdn9sTpi9A9TSa6J8dsZpIO5yFG+llAx6plK5Lb8zXl3e7M0S2Nkk /FrBS/IOlEZBsBq9Fztswk8dMiPcb1UhNFGyZ8pXJd4T9TMzvw0X3J32R28PwlwqXoBIr81HWDLW Mtz4c01AdXVlDPXvKnZGXedhFhEWeTMZDoTFrn4QsIhYNNFeeQXEmMVm0SwDw2UeeA0Ft/ooHH9D bkvPLwe+41a+HyOUxsK+BKIm9TBDlyjffQ9d2OOKjZKbC+nqMbWKqxghqM/7y8ZkyVLz80iEuitE kcex5aRXM0jO3Jg74PkKQaf8QeLHgx6EkRX1BOVCqziJbM6ZrdsCxNhTtIBl/FaCchvEuBnkVnww A4UgeslhkXd+bPJr65+0qfrUjBNOdOSzbOuS4NlwVdgK5h4waCrO2mzIzCF/SAmwZ8+eIXf2zDsQ W5FNeycV6jfH3ryG43fHgzBd9nkB+eg8Bub4S41TdrLV5gjJUpbUBdNnxDIDu2dP6iJUi2qRfmzG c+M3J4utvfkezaQx0Och1fzIBWzQ5DhxivcU3NShFJIHvVhYQpBfyDkOP1ZVZ3PH2qwc2ua1xnBt V4mWEdx9ZvX2tC6Srdt+yC60sKBPhv81x68bgYYk6pMZH4sbPxt3xYApdx4RArHNs2Z/hHywyWhS a6RUVbL6ekI83avKPfPiej0CxRv154ZFvsVD6aNIh8e/aEmYhxJVQc6AAdrKHkvXKN/TTXrbOoYn lMEf4lxTm1EiYMoBEZ8W1+L9/TM2jczUA0hEIA0sPA5cQnoia2S7LdlhF7bo87deOVNa/w8mNgyh H58z3Xe58yU6YNg5ucuM22z9UhWyYjVBUHqlj2scr8e78x9pBcNp2mx0xrJt3a10825JWhTZYVrH YxEQJ6RlwDMYvj4a9IhkMZZMCBJAbUEnu9aWkHxEgD5V1PhnFFdE4mMABkhaRcuk2bhzUQQ1MTLN kCWkp5HB1b7EXQRDn4/hn5dAAnj46hpQBF92C6NatX150drgBnCi9wKlumq3UTRtszIDfoy1IFN1 ge7gSAv2MpS6i1yV8DyOy9UrnooND+BPjATA94kaOYwnBIYCYMt51rlq0nQdq3uUaGJuj7eeFUc9 Df1bkS/ZjoKrfh7p9T9RJtwyeGcP3fa2q7jsnHA8fF3w8s2uQJSa2aRXvUOaAU167bkXGEUq79Rl 1lSXu7YhdtiycHLPjnRb1sqJOw1pZScnyQizveLKayUfA+jzAVWpkhNaogf/+sbAYIXz4j+DDknE cF2Ge2r02UslvrDpekYfLqb8T2ot26TXyPDvAGXS/IWumSqIcUf+ytbX8ivmJJ36S2Gb3dO8r5UH faa17vEWslnLKZGP+zUf5/yIS9bQz123it0On5I/rvubil1lst8cNkYBg4zb06QRyNXFP0Epp8ai 8h/BEynY7zB/fQMcnf+VZbF8GmBy47NpFCey0Cr5oTq0UlfqFORuCsE5nH4YYuMm9C+ILjLW5MKo 7k/PXKlwZt+J+LtuqhmwKJ/+7FuoTlMRSd3jeDnrLc8ou05qV+QxKhebTqiKdob0DcU3wjb+tzqh qC9KSRnewzN6hfVvHFQ3o6J1JaVMFUUaeVqB65RKQO1qgXtnDr0pafd6eENpDbQKKMoIc8yXLiMa 4YfjHq7N0Dt00IwnCG60yzQG1/T7L0meAIcds+KUSz067lzBa0U8FH+mqiDQH07coA9AaO2DijfS fRLti/ApAWf26iDHwLEXSb3YHHvezzhwk+Hboo/lEZM+LoM5bcf9EwWsbjaxJSCBJ4KC5verJN+z XLqgvqoxG1n6kc+E633eB0Q/0nOuqM4fHLU7Ao8tgxbH6KyANeMJ/2WrzrZPq6BMUs5TY+w3Q928 82bvFVJ1Heuw4c79iszICpBUykny0wxkM9Ry6vZ7doaxcDesFL0Sorn/q9zH6s8Q2RGBSh33d0lA sjzKiq6EBkNIDdn6AqbDherrAIjPCd1QvpidjywuKTtyCvljo3qUyWkYuZjXm49YgiKE+JcnnhKo awvNDGWzOcuiuizej9j9FKNRveb+PHPtN0L9vMBddwgPO9kbKH/JZ5howu2uFmFbTy5gfOQndqOX PAVErt08+U68Gf+DitQXBvrYedIYPA38MW20M8rIbwGqqXG0Ugevz9nTafnZPID8cVvAx1NKxJJh yPBgfcJ6N3RmYOjbaQlEmEqddAGsQQGL1HLXLndIyVGz9VypaSWmhmEYnWuwliqO1v3Svl1uD8LY 5d+cnxfaflBwicGxuWDNcEQIluzmKYcKDSa1GNxiNk/WK1WSjoCuDvHR2Zd5pAUQ7oWleBV1TXwd rn2oyzCn5i4slXGRS238BmnZj5pAgeIb6/sWzqDaJknNpw8QbBHibToB/OsDjDWPqJvEVN2tk/sh /CNcyz/YuKu7sgCudw3ZKwtveD5lf0P+VsQUjOCTxB0ZHEjFmGJLgz+HaAFSC0GNtNn685jiiL6e q+Xg7KIzpa05kLE6fp0fyUXIB86m1E7zblt5aMYAabRB9RoBktGf3mz1z0siKVI3b8Aob/vrXAAj 37NDHKUeT1jbB3DcowQKVbczP3QYNMItknCinlJx850ALrzI0J0lwsULYUi/EfUVYr7MlToEieov gcob0YlGyt0Df+C5vWv/Xa/Y84evrz7qVYFiz9/zDjdcPllA0zVkIeE5QjEeHUtFWU1sq0Qw4Tgp BCrrudCCgfrUOVbN7S5E7v1XPn1k3hnlAU3qgI5b1foPgHRCuIZiboYpb+hduuoLQqtIpR3kS82d Nrtu4V1OQXd7Kkgt0SwCSZyihD0/l8utbwcVFVMbJLdMboePVRcoZ2bJd6bmPVtDa1fJ8aRXLaQE ZuZEt1hQt9FRKiIfsoH/w314SCc5eG6MW3TzbhIasuPiTGtSZTzLNYsnPeOepgfvMi5NmvfKogwc fzJ8D6YDxO2mzU34Z/tCnYfa6EVl/eCTX8neNQluQpJmyrFOcciB38YE707+OEIpg6TUaQFBg+nI uFaNiDK4FBj5STghElbeT/PTglcf9JGggQRplw6q5kd1MoBFWUhp+ajfq2behYCv3vii+6Maxdjx l8OrAAef8lD42bDeQ9ks12dLHz3EbtjAoIihoT5JnCZKG3MwYgh+1KZ2EVcfS2KUfNxCKqEysBgr QPpZmcoy1A81PDiYaApHMb6kNY7qBLcfQ8D4hz9qQu71CkvE4pFp2XifwF9MWeQX1czdV7YLwyux OrPAKeqynM4icNTIplF0b0JcIkaQ5iKmT1O8BF39BFn5vdskSyv+34f8Gxe5/R4NNKRTt1+XDA3G R9I1wiDRcUkeAgd1A+vSwICvuiBDbec5EdIYUzCAqTWrsKg1hMwTyxEr1DpP3dz2fOYEE1tMMZHI Ctkr2ptIA3WAUU2SeBnxcNtkBJC1U7TzF5lm6WetNlllI/9v7d0mLnHmJ+eeQoB6QmDk2eq3WzEj Gm7oqcmuP7lAkRf+zcMMexqVSrWzsVyH7A2ORlR0JlZkKTBASTMiSLoIqgDZt/Gij+0cmbrMdDET M4Y540HiI1tTVrRdKL1/Ub3S/9wGFL6uedPnwRBr9LQHAw1RbterF0QckkJA9Zgv2dDCiX5yDOXe f82SV+IB0fMYg8wokE5MVUrzrJoSaZKooJV65JLbRacgYYgHsjZJNtOx2i7zlXJoENMWzSRGegye l7QO9ls4OCxdXZVmA/QQQdxbGVAAIz7+HnC3ClswyvNbIWt/WvomFvEJKsj71xIG1w0QFxTBkGIm FYUEVYKXpxQe7fMDD7WEYDByifseih36yIzAgCinJCjAHWN3XMvFDBUcbwLf+VS5jK+vFMnlFCDL TuX7A626uswl+Fl9phN9YbO2zAWkZt4ctKGh/4ecvGA5N6d4zX1VsEJeAVYhmo2vEn1VxUWO5UCp 0/3REX6/OPo0JXfiDzXICnlGXIr0LWL7AlcUivFrfpbdVb23PlSlRc84OS+s9tXC+dKle46yxypC +QJZUwbJCzppc50NfXnJ0SRMXPbL/e9JoQvv4PYcChLZVbs/apB//jzWR6gc7xQOXaNh+4MjrQC2 laOBlKMZfgVrDU2m7/1GJbtGFkYNJb1sNXITNrItG6wqN00EYHgvdWJLMJjwnZNxUlA2nShwu0XS s2G+TuUXyzhzxtCpUdRM0Xgmy1CVjuRqyIZDWM1bLKWVzs7Mi1CyhvAb1RtU0teQ5Qy98KtdFm94 Zr6zAejdJ27w6qM9cgf/Ywo7Blb3dN7d1Q2afLvtJds9PMS+J58016StrDNIqlTEFAAd0k4LHXkJ gOWn0BzoWgWBqnCdfiiFfyYiO1nmQcuU6Y9KGOTP4P0UiuwyP6njMjynDXNqvZOfQv/I867lBrg7 1r+nLzXGVTZygwMo6xzaCmmepwjdxh3tTL11Nh+gOUOaY6TVgqsxXVGi2CkwD3Z9yETLGsFVCE6e 0rldoEghGotbTCknoB4Rdq/E/cqo0/TCwFG5AHZax04m2/8kpTYjTm7/6AAuhu4Zhj5bnvKihkAp 311zCAp6yhR2B8YYDVaogs5z2gTDgZbmi6C5ZHR1CqvbqDUukeH3tJqlppZF/RxuzGFbgcxU0KFW vJIxvwRIC6GeB7UTvBwpDOHDW24ENFMKsif9hjxyAHmtQPzrAsICBt5+TtNK1J9PUFpMDiZuWHkv i7Pvs1MBT/Oviw2DV6RUWq2rFQOZqWqbQGLscWvJ6ZckEOWq8M03t6N3epOVnMoxhkcxOblEsTSz 3gqdg2fOrlO/w9vx4cRG7f7tsBLkIW0dZ25/8i462r0U/xpAXsYTi8tAtkfkWT/l7QFla0H3J6Jo bD3an21L8cv+Yf9GQDP15ucQSLTPFjima87jCwwJhlQxRWPU6qIKkz1aWXf03GBoLoZLRhtGZd65 WRzpIaXk+RE70UOrJqjASYXMKSKWuiBCPLXKAbQDm4/nanBo7iQQVawAPmTKW0FHqy0roaygnR5I TYWYum50hBMm3yOFLI32KmTPEN9AdlyX6uJHLvsqSeLieUmvW8vV4nZ1h7+x8+I7693eHY2PrAV7 Ps0qk7+vHZeDcd8Y5zSMzNGAKcIduWdVrnLimS2gEXXliS08Ld8jL0TDDVrag8Iu9GT/27wm5vmn NYiW8vEPrjomXCEGDOvHFP7ZnrbHMsMoRcxs5QGNiLktLIvVz+Xm7vdjKHNRcwFfQZcvjEA981VO OGewsvHw9rmEfaCZgJgl1huP09CmRLL11NvdOkEUZcbRu6+9dr0us5MvZws8ageh06GE1S+YPOZq vviIJwfd+c8O6zmJEkmazg8oe6E65PTNUi/SjV+YT59j1KkgYM1TAhx6iEz5WA9eveqMTvWPTtYz Kpo5B01mEaqeDoy7e28UNnjPMBOBz5A9gYNLlaF4f/tJ+0/lC9gjY3TGJ45fT0GTQmGbG7eC4T1T Nr2Vqcbz+XL3QkP1bYID0V18Ekz0K91MwfFNu2CeOWX5Gyoai3sD4bSF1aUB6of7vWElmA3wfHun Zk/Cq6VrpUz5XDxL7eyFbMg+OVk+kotzNzMPpzc20+RVphDmVgfC1bCGm6tc6LzgaPZqp4N5nIhb HNIsmC99G5H5l+v8N7fCdPs3BKd3fWni0PFs7/VeT3wjI663jnI0ix1f7L0TKIrK+/xLiZKKBTy7 kdyKdj1UFjlbU+RevvUFtfZlUJFCCoEbYEIa0jt6cg97Z0tiRLHp/71gERINuQdKX4FuHWdGmDbP Zn59DXEGQTodhfKx4wpfk4rdulu4dG7RB5Qfs3W8e6ipSqU/N5pFfyKtcQioeriDEyc+d1aFwagm Io99QQJWC9wFUWH1rWNzrDhxxy38wG4sfYskQxMkpJHSRYDqv3Uq0T//rrvj7Crynz0d52TL+HFQ ARvUg0QZasWtnHxw7i1/IPN2CjTIFxhjb8xjsXDrqvgCtdExp50OmY/Nuo2ejRT+l4Abtc+kV5El H9Z/ylDyzvBEDonivDNpu4NqbHZNIc5dxYy8Vd1BWaQfjbLb0x+TWFpRiXP2c6hMReO4KraeXvd4 /snD7gobzLKxE8BRioHusVofhXSxrwFhoOXP4GfIP4XzWQ0FSKoIv6QXAZRapX9Sht41yfRL6HPG z81bskVmCOlP53M13x0CJoKS0JCw7Ov7WIR/SCdvZpcQNCyLJDy1ok//TcnPaUz4dG4e2HNzSYAB ZRjZE2hqNZXMnsmdIlSwCrdhAvfhsbdgEj/302nokQ6ZxrMzqJ3Hlt3HQzvT7Ih+Aj1+mAQGzTnC 9Oqi7CpuBvSRAKzIMmwABPuLh+CJTgg6BoAfPNJSWfD0mFf9goZOvGCIYAv2ae+DJ9ospUrWix+H 4DyOrZCL+DazM0w5wOMn4ZMaTGUAYmPeVbC0jxdhnTQfFupifGiy4nH+29XxVlVeXzH/nc/6TKMK hF5NSSraoBPk6h9IgdY8ce5xLQzJbkBo4LrBZvQ36jBl4DFo/8ucXegODGxvBrsAh6n04QE8jt7R 5+H3vfz8w7N8/i8w7ux6Qo5IRyfiAQbvHzcp//L1fIIUlkFXYRS6SCaU9F9eI3ET+KNjPtZ/gjxu ZCwVY5ugphNRN5FcD+JP/kOhekEby1sndI+7wiJx4l9tnq/cU27+SboVI6SttMHTaXQbipdpibME yhOnvEFGNCsuYGrUJTABhAJIf4Gw5SFR+4RXCm++jH4dhKhhu6DVYHMjpksYWCo/YoSvXa7qEFxt QR8GjyapwkkrLi39kZvvV54qCWdq7LJVOPME4IgSsLFSprJfrFhyFAow8bg0AiazzTN7aAAaEkJl QtFtQIQHI1D19QM+m6Ji0oDnFz2/f1DT6oo1Wlx1VYCYU5LfTH0KZ35KbObeITUWZXZeHG/lSr17 arb4RISfvxd6RA8u497cg5EEk3eT3iSr32ZvWpihVAlC/iums/2eaULduM21eyXg0gh6WCHbBbqA MJHsxIZb9b6v7FTpB/1+kULue9r1l2nS5DyDI37F9kE84ngcXDSgQ4lLS/ARF0O0dNG73oZD8RTg 01rMBGWh7gGkAJBkqfDIvvuRVJHkQqpqVUECEhXErFIOKfrJF2pgcfISlUduEEYq/iXLugyVYcNd NQpqV5iIp1OZD2wFrYg3NWqqh/rdsyoXpFTR5U8Cg4+6/DXpfz3zwOJqEXfykncj/wIRaHFmB2ag 8I/qoxynNb7USVPkLTOzTKyOkiG30cRk1NeBXkTvwd7m07YHZEdXqJ7r6GjSaB4Is7ZPJ08YQ5zS D3nMjB6CAi/++NHevFqNEeiKaxmoMjJ87kF2oS2n8WLHTRGPxdwHIbH0yinFjzQC/No2BDQAepXs mrdwr1lQ+9NG65fhR4AkD6dRoO8HeOJX42mV+GsR4jzUTsfp91soig4p5aU4/wjwJqyjmfmqzEMK KkoEUoY1NKPuTEsYbniA9TOr5EfiEidlGz0m5b9rhGhPXBmdw3VMnUls8n9ZcE2G8s4TJjOiGrVv durGqpInazcm2ju1veNNuOJVB8wEyfqSBAVI7XcqNz/zoZ+ZteWvE+lAQg6ISUzn1sYRTyrw5M2I c6pWeI8BRGjxbZpuFmbBIJvZ2Z9WMzk9Dvdrj0HbbIrwwstyLZoGM0yhWfr7LWiqDZ/MAVYSPJwZ 9BABMBEyWSGk6JZ1hIlB/W/qBM98urLFPZ/hv9+AOHVUzem8LX2JgDIsa4siGqcxSkrvmn5VFt6f eGO8mrsay8vh5Zs52Sw3AZHqKiWKX9w8k3V8gy8IzWaIPGArorAksBLy2zjzCZdh6fd1Btt2EzY5 VS3J4xQrsC9jd1b1fUL8edDe8VwZh8VXXeSTik8fEoRFN4bIUDs657pd63La/bevXhY0LMMIXRai f/Imd21/Br7ah1N9V+qj3QkO7x9eD+HkOUmR8NXSEdZMKVsJx9vsrBR2/JMwcBM59wVX0JSVxiKy cBOtlb+o7W5sN3qHhHgg0tVOAlmcpFC2qd0mblz5qO9PxIF2HRhmjSkzDcJl1dkXoYisi1AVkkI/ b2SIvrFVqiX4HPLdxXhO3EyeEi/HtkDWghh/i4XBASFCBqy6vFjNB6OO367zhruxz/N+qgx+0EWz kR97AeMdi5/kmva0diCAZd4je0PD2sAaMlXL5A2adJgiWKY2ahuV3vISZbX+vb5bDO8Ieczky826 rqRI5X7TtRCISIplnzHgLYZ4S+09UbzFTCMhjuKtuEgCO08nrvdxfV14SViaYHWdQc+8b5RPA3Vw vxnUV1roMEzdXW1+q3ZYkHmy9rTI/1zr0ggZkQwks3tWyVqFjnvw2rt4IngfPAL32tIY3O9HSFgh UnTBTEirgD+o8/KFQ9QdeYrRmUwQ80b5wltRJHJJhr0mNvnWcvcwzMViNLRBrs3AMpsCYWKbUwtk 9zjzSCt14hftNg/l70PGS3LBG2nT3KQTGx/jyM0D5PSb0aOHon+FbnKLJc+wMQgOmy8wOBwN025w CDr2ey0fgAyiZezeX2HxOiE3rrYGM7svD5ldjrOPZmrAVOtPyHG2RpIdfXse6ESNhLz/RPvCcmjA jpVJsE6fWLEJ61D9hudSF0Np8HjKCHacBBOh0zv9bkY0LOBRHDbslzeF0y/BnDzAClkDEolLjZEB ISp68yY2P9fFXLDtIoheESciZtVLpkT7jZ+QTSrBduFuPoFYAcUGtZztfaejS0pyc6jI6Zzg7bVu Nd2m63nUrpHNfOfZJZypTyvv8FMhCtISdoEagjUInR+aVKU7JrzwUCqPyByHvLCv6RVi+u4YLi68 WrI8XOfMgDHDZDlh4fLzJG9/KQ8gx2YwI0nDHt1KJZPQg4T7/RYPScBEHEQKyyS/0KdpYl/m56ap t3MqeGhUDoetzlb+r5nKjHzH/EJwXwpVYygstuRTJKFtGa6U7Os8x7xGoZ6pMVaeQVLGcW9I7FMU krRgu3Wi9NVGDfBT1puFf8cUvRSIOLeJISn0f+AVCtnJvnxol9Pbj1h/+kYPTTIeM2V7Io9/GPGc AuxLpudiOaBwDlpCBn0hioLv5Li15eIERux3p52sEm/9Y3K1OJq3I0FVZQBPh93HcYn4Ka7ZtJ94 W99COcUc/VWWn0viVE2cK+pp4bZD9G/k6t1/rM9de6/MzntyteICHEhQuBNfs4gmmjup8epx3L0j g4qBygWjMwYdH+P+jVsMBD/71KsZ+1VK8ct9KtVkxAcdTi2Bkb20BH3znnG3sI51Rd1Zh+y7hUll CqfqWkrn4r8AiEgIDDCLoVwCrc+6CNsqb3fi1YnXE5b3p0htkvtidonLs+ZolC35Jq4FDCbiIj6u zCvon0MUMNsstYI6mRP1dRmOFcH9Jhb0zP5xMgyUfVJLr2lPBKvpx+1UAwFC4Rq7tI86fRBBjbEN 9MhOSh6ovExIojA/5YLeWS5jGs7yNxOiBIzWVQaoJDunFQKtVg44DvgP9RMHXpT/XyLZIB7Sbevq fNrozqCMBMN7NpeP2ZEvEBfabXFrAUZaqK7p1fCqHy64gyOpiOSSAoJrKyhiY2t+fNqNuqknmNE2 s/2x3Jd/RlIbtdgumHhxmI1eZLECRkJe3wiWXsos9E+sGJJU7UV36UQl3wvKoCLaYQNTo6+Pxh/Q ukh0A+TnbB30OSpOkvmHtfl8OSZ52FU5pZokZoKs6f5i2j3Ne9ENj3F2HPgpdRXHmNfOe8RwLefA Xv4s4zh/KCLoPARoHI5hpI9ZxWW2aey6BX3Oh9N//WQ7DyRvcQ8fA8oMQj6Tq3mAVD//RJDkYCLK X0hWFNvuDgcnyaf5yHwRKVix4iV9HGcQ+oS7Fu8/3yQmrMWw4Heyhz3KoN1qwq1Lyx2rIRls8vXS /DrBbsuUZ4fUK4+4lurfJo4AaXCtGxH0MCnClKT9FXYAJzzpZbisQKk9B13dLMh5AMPN0reQtbbU /3ynFRP8SErqa5bE5awSa4QV6p8umDuq0sB7mOd9DlRE0bC17iCUYxx19EHmJQNW/flS1sIGEfxX 9rHqv8v+ssqQtItoY+9m/CE9Qugk7Dcw56NORliFig18+uki7W8HPjRcsjmi2p7REK6abh+TYc2U X5TMoYtjlDY//VqMlP3XfGrZ4JvSJuReHzYCP4mDvSdTxrrIq/RdJ8cibmLJ7IXwLFkjC1hWxBYD 9zZKFqlTbt7RmxTh7sKoj/B00IzvQJE1tNgh60Gd0NABnLF6SB4yStKFfCDySUyRBwAr5qYKb9/+ zfBBh1mA4n2pnOg6cV5lYMvuo8vpK2B5fVARMaFU3H1MWMRDLeEMIT7zWYJogSJ0qDQw4PNw5KLq YziW7m99yZxcM1wtE3mrOfrnRov3/7A7laCVEZnB9+D4ldQBpCInq/Fir8fIlq2P3xEBHDHbo8Zd SLMoaH9ivoEffuqbKLSCFDr9zOZYjFZMKE8/pujghQu/4DOXwdprSCtJzmrrpMSOFOoJiZxLGCj6 v4hfQXWIioPALW+8loJff8+8yhjBz0nbeaOY9eYTbeoJyEiM/ez20jf4bZ5UFU76SNkVu/GLfqix 1RyGLYzhygGzdSUrqwVuPsnozGEmphYuoFo0TJQ6CyEO1QX8VnBGDw8n5/+2DJgr9dsEXhNeWKxY bIe3W07MyqRsPp6EitmgGa71ccEQB1G+DgpaN8XTEmbVNRaEIs8a2gVIL5Izd5lXsqucq4J22JsT jj+ZfuEuIBNCN0FKIpzP/vdjDwo/4icKieAPz6OlInegaf9XKN7INXNzifQCOCpROznZDkspGMAZ 5TDLylsC1cbg38htaEyJHF28XTUtNUTZ8pa00KhnIrIf82pnBh/8ha96J7OEj44GcxGddz0ZxKQo EnT1iVTxX6Ii0hWGLLrYWZT81niou6VsC9K0d8Zq3jKefb7XZEJtYq2KI+khq1ZZ90BRQnMchiB2 32hfVB0tG3XNugY1v+noCxkQHe8/ARj06Y9W6TC9g8fZDhUM/y2JbO5jNG+D4yBztHCFZSAcx4cA EEWMXX9SyXLFS21QaSKvUuYGwOl4SVJ0uS1SiJDCrQ7hSfoTAFt+UA7WRc8WYOLGcKiJyrFxlJ1W u13siEFoDJ7sS/byw1pQALbalMsIxeUTUWBGoBOKEZ2D10Ov1vvra/p6XTKgEaG7ah9hmolRMnIa 6Jz772uC8qfT6NQMKykr+mwibD/vxsCdMfA0cD6jHm2wQOfA3qCjxfbGol/t2uh3GyuseJ/f81hR uXU9+DejX+xhNVJKCIuKZ1H/Tnwa+KUK0i+hW5xQUVjZnOzqXrksbfQYX2pLIKwGds0Gi0uKCeiO KVVqL2jO0+EIzsm3WVVQ3IZVA6ETQGxJkBHbBokJc1qSskO1mCvmb+gQRYdtRVuXD4N7gCRdHktQ DFCQm5FstzYpSkNHJGPyR3hjhPas/7imE/s9rf3YMmFkN8LKJ9osIff7JF5vsxJWEJHGNGmLqiw1 24MirADq3LkiTK1lwoGjqmwRxEU6kIBo5mHp9CFuoPrPsEhV55pz5+lhZ7HBkG4Qgr19fInum0kG CCWFkzBjoq9+SA97Why+hg7eR1UlTS0rmy5VFokt26zeuelWUxzoDpPmBnG/0JNg64jXrgTqbWV6 KCIOGo5sf41kLkOLgrLajPSyejAJKHHdX35Nz0lbNPYNaC3s+DltGJ9rx7oqlcXjoiM8vKDHlA4S y9U7iJnvJzztw7MHiaZzkRnaaGFXfmRgsZ5L3pSiubiYq5MsO4PJJpcQyx1ivNoWVKbZ5K3rDahF yW3Pmg4giOx2pgqot+sk3F2o/7PRJY2L4PvLClsLrYFy8+NTjTc+KOdUrOPDD0H5dPq/H43DfxVJ IkcMNu/Wtxd1tGVh3zsCrv7FGxpsVxlVELNPnYIc1+y3UQ8oGvC4nCvWlNcCWKyK0bT0FU/TGuoj nognIRjqa9kPuNF3h+92tTrSnUdTesjJSEPO9v9VZ9wzBsF+uNcPtA1C3indFyv5KIwFHBqznW02 8iAImlkq+EONv0zYg7kGhpiMI0fJy7Fscq7BkFQcSjCSQBs0z4S0Vf2L64De1H7hjNSKl4vBmfTl W6r2CAigs7Es6+IqEaFQZcug8HliduGl4Cv/4vTQKb1lmqMUmgPnqakBvJMOuQXbqFdeCAAkz/E5 M629pbNl3pGH2hFY8zEXHSHG9ZmS3/t7BIaT0AzBi2VjNTJtSQUCmOqNhihoeKFFCLgry2Zd4VCL 933V23kVowvrJYOXMTD05xA/tmEl6gZgs8Vxt4YIipkjDlwMv5vUu/lUc7d0dDIMWDnwLREDqPZK FtiKFv6qJGc2Zb9uBbTRV3gqNWe7TGjzAqvdMP6j9iNnglGu9JsBN+UfhC/DBGyFNENSUadmwwrT JvfF+bT0GdmydUcW8yM/fVMRIQybcDaGkySPdyRPGzcoQ3TWPEEZ3jBeHvVJX+PdVxfB/lQYaP68 oJEWOF0jU+pJlENnxwGf9mXRZxwtazwHKLItsQW1t+2HaYlXXNnWgiNI1TLKzrjAIKGDcB/lA6T+ C+NnXAeqebPjj+F8MTXMZsvTijzmnYLDQaHr6vVL0unlEKxE33N1dKp1vnREdG6po8eLILaUHMnm SnmE2xcfZiK9nRkUKYY4vMkA7JCvmRkL72yKK+ZtTi+WjoZwDzOoy8WbC40+OKu665TgVz/mMz+Q M5ZTWfntthiS/LY8erJpq1iTi8PlApSDfwdE13RaNuN1fkqG8SunBSLHU31H++qoEXS3BRxDmSH4 keXiUD+520Fs/M2u/sgFauEyvQoK/Ld1mLwnXjApdu962jMV1ePtzbyJQLrcz++nG+YmD1o1zoqc HPCB/suYgCExGc0R4+JQf8iD10ewQoJMlMzcjQ2upewiJTvBiEDS2Z4V462iNJ4W/NCNotazHTUY 18RTeSAcy/J0iCEDM9jqsECVfOruligL+NLS8FdF/zMr/gxiGI8AlmkDYZUL5Qbmv+GrU6GPcESg 4PaLX6I6FU7pbFxRf3NV9hNtdPHE0Ypq8TM6SpuQk70Zj2EHGRXTiV0ztoHGpz0PV1cUz2dj+A7u VlZUcMUieA6ypE4a+Z8cn9/VN6o0mXV/Hm7n4sIbvaxAvhnbgd99zZaaTKkCEJxXTxmAh0esDPWq +/ZSn/NlSXEjutP5fYEJKold+bJDShwXcUZUUiqFzDTiIpFV4H4UmL49GbHwW9/BLsz2VwY94k6M 4AVzp1CNzomLVwVKWe/+eETMWzvM0aHWHhuf02FdPNwFQveem1fg4qKVZH1gbvpVZCHUSSWH/MwE A1SbyVwRHZQ1WPvVmrRklT39lGtVn4rX/pTvfPnhq6JIvfwkiY3ucC7BiCKfLFzTKMwQTluf4esZ 4FyUxK19ktUM6BTeGtYs6bFCMzlyILqnRxXjMzJhdHUTShNmeps4DFn8b8a1nzAvCF9ZNmQwLkWQ Hb11GD/MnTc7lDlWHCEd3g7ymJSiT1MBZl28a95VQ+aRk0SNxrEEPSvFz698uyoGsih4KlInscVj eE3EdMFnJ8VaCf5FNKxzX1qkAYnDdyED0l6JZnuhAq5JpQWj6JF+Zma4BD2sBxlt8YjXgdgTFRX4 5ysfCeOcNeSfcrfkUeQl047TnLNNQ2nLYQ/VQ+WNMvYoGUuocdzA+ZLKpKCXj289I6OUg1/7AMCw 32WzPvok90VLj0ON0lTM95NupvFvYtbGXuSMsJvXZcdbg8B5v2gGSVqV11KewU42K87vvO1PPG8g 1vk4rogRne4FQ8uegp6TNHiZaL8SWsy14Lspi9s0qL55gIDJ4q0ZfFwaUO7i/+rYGqLV6U6D4sbK QuwiuEJfyOn2GhxN1InxpD4rsf5aMcH7nVn2yFne+XEDbasiHr1ajlLNGXsToIJ5A+ezMPI2eo/s 0iRb1cDkG9wUymutPahsYEqYe2X1ltLMqAIhpwpPntJI0dIq9wIR6kjsDKh2xqv7a6TxoXeMXvY7 gApJ8pHy8rNFZxNLr2QqKhZ6qzNdvyfD0m4qeBunWVufXBwLOSbuCqjowLprxDTxzNXJ3GjGJb4M S8eurDa8pUIdBnAYXoJI7dJWHKtwnRXown52Uot+JY1GglNU5A+Eb4Qqg9SdMEorsrJxS3EFBAzU E2z4z1QabCk5QcieBN1iLwkDFUYCEwVqCB7k2bTSUumduYYSRsopQXF8hYxOx+Qispim8hD1L0Tl p0gHD2SvNYRzNGJUEBvdTNVj3hxJ66o0OcSFbQxtOJ3qkg+3sdz+PZy5LY7SpZ1sQkNgFhcuGuO6 UL4dbR1KABjGoprJLFl89QkgYIRhbl+AQOYEZB+MNX5TUCyM8RRu7m6Z1hmRqy3I8d+0TXIsS4u4 3CqZjGTQ51xMUw9SaU+1jhKTFa2MjjIplAu1iL/ZCy/bc5rXT/fBVLHPSNqUe9wSmkfs+HOjLkhl 1qZdrkrwJ32as281R2Nj40gMT3RE7HyXwpbQ3ZxduppZwlskeKBZ+WAhnQrRm4NCdrSqmonqUcJb l+yDTN0G8eFPUx+clzQH2zR2it+J65SLirxAaadOhPDeHG6nZRN5JeFnWPsBMqASr75+gAd88xON hzDMXK7/giGOYitGCjnYL0sRl4mGDfEM+ZkFFDfl/UdoXFBGA5Kw+2vAiPJQeaAcRfMPhGNhM38L ZMTvaw5/qv9UBTBjgCxyO+wEw6/hTiVTMPIc6dUK/nGQsD5nuHHNgfsPKamDx7d7x/pmzGB/49S9 j5NACKohGnjNWg4xCtQ+0SxiUQzTq1Z3njkCGjqpB3sx3+CUN5DTRlupx3670TBSGgBphPGBq7HQ DrurUIGsebgI5JDrK+0zo9AZf4s78dpGZnkRwI5HxwD/rqzVXbghykuRCU3gzqdvxeeiEexmDMw0 XECW0InDd8uG8sUNxzZrCW7vxgq7gJUAvNRwl7m50B1QAwl7X0SA6vfs1hDD3cOnsGHU8XhDSoHS ALf92338qyYouYFZH/NkJJa44Q1uiTk0TFz4AJ0ILDjMl6mloJNT4CxXEFAyiV0/Jb+Cq5ub/00O l4gHCsXqiG9vP2pdMcvKt3XEsh1qoZU6isA6PUWniYKIyL0H62LObbTQLXVj84C15r4M4dn6iRJd /5qVWnC9SlVWK8Kdsv6TNYqh0G9LlKlTsDlCa4yNtckRoQ5aihv7B1okPc2JCGx6V44tw091QPx3 rwAnZu/ALdu+BUJJ3giBsHUUTfBXbhUp5WCJei2MBAxf53sPiDXUfpNcCioUm4IJNisjTn3RdM6p oznWRO4XcaIPLsRxwuN35LegvCtTZWUM8PV+K/QdZr/BN4FFwzMJHC44pe7VtbLpHFiER6ucr4lX sBmx8kz9vyqRu7hAbuvvKAxvqNjC61tZIGrh4EhwsSOP9djjxJWAlmhFhD5h37lUNezbx4m42u+D L/gO+0z1Omc7Tf2aU7QcCJm8vD7gQRNj7aApswhLbl3wq8UShq4wBqe8zjV7rkcXdPB/PgsFzvxH /0tUG6D27tRZaWUwYcV7lF5ZqJ7zhk/xEcppJCEDPa3WrC0P916ox41GJkOkCNfNVynlBSHiZmtr EBA2IWqtiBV9GBfSn+DWF9BY8a+PRAGHn/uquWnsTBzwinamXYjVvXtnm3RoX6wFFIc8GpQjsRQ+ fSJqF/TqFFJUnH0s1zNemfY0rOuB6Tp2tJy9T00B0IvH/16LqakillyADSHctRiGlanDyfuIGxc8 0Hb3LcfI9BW37kfrx2F+uPIkk3PCSL7NM0w360Q5aqPxHMgHC5Ij1LTW0cIDyoS0oZKgfgQe+vCu r/U/BsizDHvfMs5oTGInede81clKbcNuRS34tlAYGQq/FCNYT6PUTelcsdZlMcNKGMHcdjxGJ9N3 YMQOls1yEAhjluITC1HjmELlslyP2ZySMPs8o7mlLV65NowDetMICUX+wWe7QdODK0saMRNbNIKz 46q3LPD/VkyeERbE5M7KD9iRqoCM3B1t8/uyBKTm18vA67Mj46IyRkwquEe1hCUw5qpfH8XDlVD8 azx9m2pvyB4S6JJQM0wY0UvDn3cXCkyCTeq1jbZih281+dW/MFPE+DVuWjXnyLbm9X+A8bl7d+AG vVG5qa+OyRy23ZB2xVUs5cXLz4p23hq+FlNBLVSi0OddKyChmeGDlaZAI+NyXwJeiZfllOzquys+ XNxWHudUM3z2v4pEP3MNJtErRcFGpy73hzU6qWaMU1vdjRBTqG/iKU2zx5DhzUNyRrnoOHvLWLLO SgFQNsLYqUaKimM9Fsx9pS5EeZNCy2UqcTBoj6eRDbMU+tuD6PQE9ZKXI2xPXghkX+ufF1FN47F9 E4dHTfHIlcKxGL8XV4spEEsMHQ6oboIAZdaN7wD0lWEtN7WxgVDO6l9FJmvYgFUOtQVWWbf7HoaG myH4wuzRQzV81LZd21fDCWQ7xMoI2F53yyK/808rfnvN3Ae/HtLqQa1yaxgbhZOJG2X2nOfM5k45 fBnCZjlQzPuPbSHtg2u4HI0b2z1YZr4tEqxL73pXLfJq4xsyqHyjHmwT5hQIw0b9wOe2be0C4kwy mnvDnkbAfa6GnfHCDvvd188XlhkVLktXjLnFBZ2bF9EN2ufqop+5ymFyoTOfav7Wvwq+2SAiWNy3 2IO4MaYduvxBRVk/itMDCl2aPdqbXq3CZdCpxLwxP62/ARw6Yh8qMjQIruDC38siJnm5OgCF3PM+ jdtJRV3UwJcRhS/zPAxl5EnSOmIHZPifnS6UuvUJoumAeEXjg5LohZfMfBEafK7YMEJYdxlt6MwZ vAYK+TeWKcwiehVZxsU2H4wElRfvTapCJWlpCdqrkMTR4nTNdmh9oMTM2zW+s2DsDnm2OtQfsdwv lEgpohwpCaUe7Drp9ZzoWgrEWUyqFxgOE5uOkrvSmCdLWaCCOrOAOTKv1jkMQ9oQxfmZnMxkm4Rf w0YCsVI33z1NAsIENt4j98kWyy1/nZX3QDCj9Wp0HeteRKXWAx6Ue/4/haODIyKuAE20ThhchyTr cuBY7PlZrfrs+us6uHQHtzExzJVH8UTiN7k/JSEzEWDpo+kRMZqaJC6JYL7xozA1HTRgHaysQtZS PXJMKg6jGNuNuQn1pAjX1ikTAEbuo+FFuDFfQUHa4cmACdFajiYxs+CFEqxvVQ7JkUDYkdkK3QJj 0eY+2ven1y2VzGwa7jFRRtmOitYdxAXx6tJi2pPAthyU15J508Bv5o2dEZaTcwlioehy1nZD5Mdx Ute3taPvlfrezIulM8vDE9vXZeU/SocqP4kVuEVevifxB2dD0an6cJHlCJwiB79kOrFotzG+I6ro sY8xvMWf2ZqC/emUk0S4+nR4qiJEiukQFnOZaTtl/cBrOc9mvwQmhNeWYQ/fUL+y3j5xtXOw5+yG bIwAI1mo3aqPp6RQLTm2HCRTfMleVz5HceCD+oEHJNJYw0ec+0h+d/YrJA9EYGFJzn8BEdPgjicP Ar6f3RIWSAsX6SOQtRtlm2z2857VI3q3FqdvyEn9yLxLLrbTuvCr1XVOnL1gDLUUj92jCnq+zZPc oUIw3j0tnekQkk4XJJ4Yr4M5hIDUOwxA4GuepEWF9+7u8Z7hcJd2pK0n+2eojrPKu1Ai6gaHL9jD kMSSSqwPm2RnoMZ4UfAA343DqDB83MkUQc3aEeBJddgRbLx5eAGKSeu8q872DoMuMbrh5INPMHGp H62VOlNTj7SYW3ZrpwpU/xGV3UFaF8NIONyfK+/ggcQ0gPVwr8MHzOY1AnOFYRTySoQEcgO9/n6S huN+iMoWa2QKmiQDl7kSmsJV7Bh3Ypw/Y6UEKoiSY3iwZXY/eH/OWFXY6NAQinIFGI6/+UKbUw+v jm9X5LMo2VZVYqfrEzlJjIi0HC9Ofdf3At3ZAYKa8OaWM9njzZ82y3gFAteN/DEfqi32W5Fj+Gqv GZiG/SXI26LDHqd1nH7nn5NtzgiOe8E38wH8PwI0lzVayd+PHR0QsQ/ZQPzq7wV5vzn8586cvvrG SpVWEZUYQun5w+tkvvrmP2Ka4mpxyGOlNXS+DAnX++eOxV6m7Z5l1Yy6fIWs6NCIByfSXG3ONy6A BvsBHcnCK8Z5wVL2wtqye8MNsFnUBUc94bitrpQtUHSgnVlSqN3gsxtseWwJkY9NgZUTd0mn+OCf gzXAg+q5K9A4UABOiHdPHswguTOlqPhqokbWcloJW7QlyCpFznVngZnpAIPemcrKAX17yVRL+1m4 luaIcadozdg3DbZNpOQldR76uMQUKdURVog8DBhodMRiVCHZ3Zry5EbyFtWltO7r3BmVEeTgOOnf cwQ7HR0ZbmY2//sLlZtkhnDWIR9HhnxNu5EXPX0Ye459A0f9URgJynsSva26zQpq35aXaUHvIO8D 44EuKZUsFr9R6ZQFYzIl3akAQtoveSv7rPlkovCzWz7jAjFy8Mzy96E/hwl8UXS+TktfWtu088sh QeVUL+gm2UCQ2fgmKOt8xRFeo9OjqfjTL/LlyweV4OT1FoclclSrGy+vNibNavhLEboiiIMp/P1w 2T5Sxf3J14/6g9/paftkroSkfTeFdBFYZeLHTYrIkKoetyw9IXgkIeXN0l9NeccR5FZ06PZQ0/rG sykz7vSCQBDFfivj3uC9rajbAmz55/nWNXxeHjq8uxUdcPDJqjHDZK3VbF8sB2I9fkRuWikzG0iN cP/wcazGKDDkzvQGiS5D4XhGjFUJhZFXXqy8t0yopD7iKR038hnHg+xcTMpTc/OaB8GQjV3EbEij cVLDZ8h80j4A3wMQibSU3+kKBT57HXmXNXyx6RHQWAFIB3jaR3vDMetZNvwKwtbWhGZaxJxzOP3A 7OesOCBzw9yjY9983mOol/0HMH0iH42Wl35tcE2xCwPKxK/NORNHAweUjIP9j/9ssDsNRWGSzLv9 svBNA/aewpRSgNSpm4BkvkXF8YvGk/XQxhyC0C55t1WCYl4ca2XxZnz330z0z59VHkuLbOXgQgMV SiDQwSEP+9Iq2KU/sjivNL/JTyRLbuvkc8BhlmvdmotISCZM5/w64ArJgi6hHNqrlTrVK1mIbBPr e5XJ7cxdiQj7c69UuAENVfa2nRvgYCWXHbMlGa1cZ+z3vxbk24SozjVGMF3sHFSWspsMCRr0YYpL 5FS0x4/6yuTeooBiBcnZmjI8qCOvImYXfo/JTx8yj3jgfjWjXlVWwRxyU9RuWbNpstjRdU0mx5fh PByNBMDO+VDkCI/zMwVbTFSnQ5Z7nTua7y2vJFUTNlCRcECIBnzhGYv02SKL/JOd+ALVQtsDrQjz fRdJTdBNg6Hh03bdJgFCrjHeUc/Qrk2+OgE9OZ8PpiMs41zZdTo638gqdOLcQwtrrKj4CTptGesk SwaAhewh73R8dH1AThdArW6HUPEP+RsrjfrTtt9V9r5kM63H55V0FCtrBamr1lAp1b7u713tyOgm k2H0TC/aGeZPg0GFcx6+07ySPbbwLx7Lqb3K+gljRS6axkLjnk/1zgjxM1Ovv7uo6ffwZlnEEqzE E0qtJglX41a8CC2t112Rg7zKELrAYUzg+0njXfzq7pXo3XlP2ijHD+Brescy1eHdIpK1zzdvjKQo rwh5eU4y0xlJ9yVjaxjLzbF8I8fQIKuvSgSrQXKfosmj8B38gkFt7veJzu2WElJF6Pl6zuvfxm+X efnSoakMKi2xHrQo0xfz2JRTWucwMHtxiQQjwZCQuLqBwTe1JZfDWlS6JXdcz1g7iI30WdLdZR2a DdDe+f2pCYL4qST+cDTM5XL2noavcIV9qe9jkZqR6TP5ohN/i8XfEse4j/HHf/2CgO8rU/7HkzRU o77SJXTyGgCMXYe6f8RtJSzgH+IiDprVMHlh5dvQiXkjA8r21y9bspx2W7vJniwFTavrBPkJ7JPB 0ApaSdTJ3o0fjJ4GXFN7AuPFZowxZuOEyCyYIomyHGZBxKQn4KRLRrIQErERwLUWGAYevExioH2V bHvmzcjFavAeS7AdzrZMJW671rOutyc1Vsy2ef81aV5X2T+AtkO2Sfodzs5Gy6XFQTe7X5BtPcxh 9SSBd8TqiHJnoFRMZ5KlX3x1O18YWOmpfudJrkLlX87SBVSHyRKtvEY9CCwqKVtJCLHo/OEejsMe wUHCBAlhYWuh7GhPU7Jtdvqoz+s6VM/Wo3t4wCcJWDZLVoJcV5O3scP4iPRjQaZe8Afoj9gEkbWh eQMppKHaQ6YmUDxqXZ+2g17bXAz10QLUgq/7Cmjf/9adB5sFybHxClkSmtmhD1fsl96/EDjQQwcV QPoIRHfQ7o8Wrr0mdj5DPjwO40wojv/Jt/NF6ivg5vhLNLYFmfhRUkpK1TAkk4YpCxurZTzVpqt8 i9ytHHQE+B9sWtulCja3gac3EVjgnkgVq0HLx7hkNoqjT4x09/46EMZyCBcm20/1nztsEo9aWxDm gqjz8U3f7uVMoIYX4jXu+qnCUt8S9u4l9JBFnyiXOy5140tN6E1rl81ALC65CCsAYyGf24hpCH82 XBy4rFA/1kzjhNyQHfOrksVB4cAu1zcHJCfjPZJuyZMI1OmIaJO6vpD3DE7G9GuN6oVyzU2RLHs5 L9dzpcpkF8odKIOJqhNh4Z+87a0JBeYRQAmVzdqRB5UoHuI+mr6FVasrsUD1xOmU8VAvI2GouPNO fMvaee/aOIjl6KHaZDEzkngwbHbGcibCeDptFIv+4Ykqv6W/UUOWDcp3GzNndJ3gi/Pb5hjDioFx qSvtH4FEOmX74PKdK7pXFtmhI7HW5+Nfy3WTA4ThMZ8tcScleHg029c/VuzwlrpKPwamssQIre90 PiOxXw17pn/zgD+bDE5CB7Ak6ODXewYCHcPvDPE42Ja3aeCrZsrjLinr3Efzf4oro/P/vLM+JSuY 8O6I8zSCMmp7DzqzOE/xSEOpa8LlCxV2AZadSDGef0wOjJGbgsP4iE0+fhiI/cVS2iFqQjcWoPAA 5DSMIQBqsrLgjHLW3VYpecMvLCej8ue1DflViJ2DSq060JwfMnYo0SM1wcRVSML+NzlHppo4+vWL OWuD8f+45AyKyfjV64YJm3saYVQ+3T/DUk774IQDuZlFheM97cBXfF3XsbLe+SLGoRgN3SsGESzC Qc/X5mR1w9SMLUr1DSBiiHRhMzQUxmtUb+MEZewKcRSrCLn4m3gBNuaQncv6np5RqoMerqYP9xtb o0neBHjFncLaxSQKLx1vYEb6TvtlmZQAFx76S3N4+hGIkAWSbvK4GU+bMtiv7esiIjaEPqKdTvpf 2E/M/XLrRzEbulq42/sY1edzskqlpBUd66KXY1Z/kul73FYKuofZCxjPTAvIGqjiCmUkekBkwAEj NiW9OU0wEkYNgTGv4Y7oNtrjShvblBitBLm2eA3386uINVDdRWHj5fc6OkrAFMgfo53Gs5gsU76X 4l4TN1Xg2yyQEu163AZDTvQ5OJidg3IKJ/3HXRqPauyZSmmvFimO0GbJxT/bqHxT1aFnHaGyxnCm U9rQuVsIVsKsmI+wcFeJPiSFx89tAYDGhVdg5h163WE82VEyz4NTT1HXT4teamd2oY2uLw+JXEXG 7RpR0IDBr++gppX31c3W3yc4Q6V0BchPrskWGzf+srax5VvFAfhqkMAI9ozXzvsLbKxmzEibVQtc V0KQz9EvFndbEnloS9gjxzdzPjF7+U1ols0o10YZgq1xw6vdvOdMpqW7hGUAuHDfLvZlb+CM3jCY I0JCo2etKifwMcXgf9VxA3NMEfDLlRoSwsB+EbS/ZzSxycs1APpO/22awpK9m3SU4m5QWE5dfDRc CzYkpopHlKXXkEpMy9hvLqgo786rL6ituPh+hMTPrNaLv4x/DFXjl6jLdpPupkE1Aeilj9klLCSG BFOtDwh7l4F8clp2epbQhxml93BP41GlYY61PjtpEXzZg4Q1UCVZxf4NCy5qWct0jysMUko0UZXQ 2giRKC0MXa3Vvt0+qoLFJtk5xYLmTl8I4gVeRQSOKwcqj49ThimJMBhQeviW1ZxN400dOo9RGkYn TMNDEYRvP/QxAmTBKJm0C1tMkn8VbY2ySvZWSvhupuk+xcyk0zWYsTrPQoK1HXp9l1nD0G204QwN Mbd1evMlregYv3zcgC/surg/idsKpZB10niib7IHGfscLZx9rF0pGhuR74DS71fW8BZbYeXuHbgj hPXTfKSHCiveQHtUFPWSAY5BF5DdVjYHmdInn7pwmzdMV68UR2SgvRyMZOFHTT1l/6NXAu1RuhtL XKexphJk4QJizxm+UhS22IqtmRfIRWXaX3CYM25TsCIuNT0/lo3HcEyPMlTnePu4NPIT70wm8BI5 bs6obnmoOQKyQwmwayIMx19VbSf+sOeJEHf0ILeXrHBAf47ZxMqwgMKI0dZYzUMEwAma/6AhtOA6 LcYOaM9UaAQvyLygnM6GfhwsCDxETziXEKsrrw+yNA1jPQ0EPBWBwsR1eTJKp+LI+ej5+2uBTN8R gdkNT7LtszrorX+VcN/TXHxdy4SKTHmMHnU+Yx6XHSZ8QC/FY3FSpxj0egXVSYWrxjtPz1vtZsKB yAb/ljo9VfFf+IGK64glhoylv6CxkTayFTwXeawEImtIaG3biIRCI0r9q1/apX+qYfOWM1g9Sq4r 2ylbxyQ9L3VQd1kEZuE/oIOC/lCVfu4wwxHpHE8+0uqhm62u6cipd2Y76PdoNZw9uQsaMm2yrLDE iMoX+J8840NFP8UEPynTsCBBjdp+Vu2p8zTUskv0pzCfNRlh9bBtWwWDdav4NMJ/ypZiOP4UKNg1 pEbww4uaZst/hzp6A/WLnoCIYDywzSTiiuNc9KDbtq4W4cxC1eyouHfSxeyy9pk5f82YHRoGWoHD 1xguZVAEVjC4flnDRtUMLlJ1eLkX1oIB4ma8BxFYbgwzxjIflUZScftfXUa/Oui7dQ/pIk5Ltfnc KWZPTJFblAYBLir5I/rpQwo9mZQpyZKbMoUueyuifnc65j+FMCdDPrcoyTPlPnqRfDnpgiTQVsW5 dc/j6d3zJCH+17Eu+OxqWoQs3y63ie1vUwfqcEuPMkC7axGA+lzkifbUkReRTd2mFHXGVEE+nUaF nRm5GolEsU//zL0xzONKtJfFwbRi/Yd2OlsWjh6JJ+AB/nfI/lMVIuBBRZnNgzOFzpU5fTTLHLiB MgahI/CgtlI9OjjxwWFxJHC5IxTyn+y2TCpfR/as7Tb5hjrLrF7PEE3KuEzNR860iDEiXi28FJP0 ahHB5g+7m8KiU7A4c4VgBnTA7OZnO85J7kihZffl2D+eRAv8Xqd8dvDrNKG0uuxffB4NJjVsmKe2 N9sAwQn8koG+wU3cUy+PkQj8PPxGzfH+Ak22I2RGgXcv9Z4P3BgoCbILTwkq2/klQl8qUtaSmPQc xNODX8acxIhURphtrzz+/osNlXkGl7Z/BGMvb8hAIAEUAwE9tu/qAqRv/u0E0nE+eYT9zlT5mQgc 0LqyfwTNmQV3CNwp9nJHUQk28AWjGYXSGa6u32Qb77Dkmfu6YXSh5hRylI7qz13sZTPPtkxGhv8A hBqto0/M6EwbworwLxIulHFfNrl6ndjzRr2reYh6OQa5lC7ksXsdJCgLh08yCCn1eMwLK9rRkJf9 i72VNKE23R1sp/HSWGG4+yAVgWsSFKRA0oWFKMk30VBZu4FWegyDzahn0Z+CCn/TfOC66lVqwIa6 tCXp1UtGCM3ltolu9wzaIbCdv5VAjUXtX8Z/ZU0Hou0601f2dYWvFZOCncFzryGM8XI1LYSYPJ7A WC2Q1h+mW+DYkG4IfRY8Y+Oo7772knafO7cYr5tadTwYKxGf1V1KCcR/unF0YXs4dZ/S6YyulcGG dpP12FD3kXRb9P3fJskN8oCZP+Fg2KYAmhMNK54p1L1BtHUNPcsEhIFPR9z+AfWPaTpiaW5+G3Ms XXwZeU9Od/1O41MY2XNnDBvSKL78xexUR9mziEm6Pg3Xzb3yr+YI6MydNRVsrTDVLRQzZsA1FTLP 64Ywf6rMGKzB3ld0VN5XQlq2s95vJnKeRyCWYV6+RyvG/vk8CxkyTH2LgomwIXFv9Pp2inY31fWC 8tVC0E+jFXlegweBFBoVJ8BE56d6q3bNyr026F/1rYRxFr511T/sP+lOWYfg+BDhBZA3QElYilPi z7ER4ksmrhhPYZfYZDKx9bDdz6ES1LUr8zi72uj/opsTIqMm/QQX+WdGukyMEmXpZAlZ22QcKW+d PKWsagXSoLlJ5ugGTXPcCCv1mSrduW3yVJkTiwjz+WpJIRoo71pJViaiB9awqXan5scEl3ZanQpM CR35fWUBigmvSCtv5tNvT0LIWUO0SDNI8sF6wI48zAmITI3yNwCItxbJLm404YK+3kZ9Hz+mM+Cw 3qD+eds4LBxpOng+bYWBZ40VY+o5B369fcg1cBSic72zVUNqzrOfIvDlMbkLDSufiYR/IbeIc4UL bX2vNlyDLQqF5mlpZga7S5ALsqFo5qi2Orr+XR44NtuVztyXLuHMdqIiOY9SBuFN52tISFAKf5pc /oh1n4a0M1altcKp7YtCltQ1EzWoCdpPS2xLz6J+h6NQ7k/TwfKg9w0Tu1yVxzhvq8OEj7OdNIxq QEtoxWQTmNncAYUvTwHKUdgTFfGy7aKvtoPtX9wz6lO90UPuWlOGVkN6kJHNCiCL+daYpwk3eGjq 4MXO/CM2R6tSWc3al67uS9D+YJ2XINBT75ZNN2CR3SaACdIICngrclDeofnjuG2DPL0IDFldlxQm wKAJhsTRKjpsmRnwACDS4JwNDGwpqEMfJ8bq/+5cd981kSuKVDhoDNa1pz3vCl7lATqReltz9+kX mEnvZbJ3VyoJTZ2tUfXa4dSj80/oY5Mln4ttu6ogrvquZxoaTLfS2aWTO4vkMHJ7p+i/zQkywwmI E+Dl2aXFbCaHqzVevESK9iiYNP9aFXxeq8o7THzOJpaX8YITOXRPThKImbPBq8+1L0Art8oOBzrJ pt5b43+LoNhkR0IlHVYwEWvn5mFN2xWQAHhQS7hZG8oUyueQuVHJOt7FwyDMtH9+kwlw6KGo4YUH PG+LXtV0jjQlGz6RWQjCN0ZugSRDTTDYguzjI9T+8R5JYqAN7cxEbfIHHuEGJphQpeQDyAuy4FSW 6F8ylBt5P5PVY04M5vF0HjVj0nYVNpu+J739Gk5VfPt6HCVtR/w9MK/JEZ/wb6o+AcQZvUcn4ezu NjxS0gR3AWhWONel1kRptusHVVYhXenOAvRR1N0FRRnTuComf1yqCRw7iiMyZTup0S5ZXzWTqt8W py2kgKDLV0OU5ZPYSCXCzeQ7fusxRWggJzF/yTrmImxTz7QafqYB0Adqj0AWGoJ4usKzviyyUg8T rLvATlwooqarMGZ29VRcjhuF0im0j5MCCIj+3X/wFc8B3tZOea/dcAUnkWemEDD9WYajVoxprWLX qJUH9+zGS7tgEW9U+gcT8aPMAfgb04cV10beaboCv6pstt12PUI2rXCfjfBWaq19gxugf9qgKOQC dy3VKX3AEiadUJiB6vq9tee9M5WEGSDQ+2YHKC7zCXFH9BetT4dBtegXVXxs4UcCTPNBod+znaAp 7Aul3Ro5InSMgIy2E0s2xZB9bnK5Rt9c6nUQ4XqpXqV30ClTqmi7iNiL8jNZx1qkbXTqyERT2otI 4qI5E1jq5SONtinDc5OHr1ZgxFzRVL2aChOOyzIDqw4/w2ZqoC3cJ9APebmZJuroIvHQiNyNtYJ6 6TedE0ihRItYFavswAh1ZiyaCwsGYV8gtF9fLE0DHsQxrw35nIVdBlAFJ2wKMVPQ2JykuBpNiJX4 SyRAjP9S2Mpw7MHa6JNpU8PAY+jpf+Ci1dLUqh5xeMbqIgJFUexrT0Or0c9B200v0F563RU9NaRx GFBOK4ybVJeHuA6KNQ6zh3iz0zutkRqV0XFQmp7AhjVVGBqg/3h7F8zCXikrt9YQbsSbBqYL3Y1x jqbPRWtdSZTLz1qhgEsMgZV5P0mFgw3aX4wjDP8u1iP+YPadMZOHTNHpkwUtD6P7ar0e9wjMyO/k 2JynLCQSQ75G63SnOueQB+JboI7ZMrbZyFSuYVXrCN0BC6hxPZWVi3Q3uxJl1sgK8npOPveJltG6 oCxD217PxpsQm3IDQscTIxsQPZRVcx9rgFQx6VBFUuPr96SyWdJY6nKuaxDiOuC9k45T+arxaHie 5YvNpqNOQmXvnym0Dm/FuzCqjV3de1bBkMqKunLEM0QARaetCpVaw2RmdrdcPogtNMrzjaulfv69 0bOmVMF8atkMABmsm4Sd7u+kWyxNWGUjrNlH8PHX8JPNyCvCMZcSzqYCrSshi3qfdXyhdUYY9iWY K0WIK/gg6Pg/JV6OaUQkT+TPsHrS3zUoaSLFwdr2mFOj4YnPRvFRxQUYgYJYxGZ/CrA9+sTU/T21 vU+971o8U1soX3lbU/wki1bQfmmcF5I2GUsZR9oFUuE3whYWwje0hq/ko4HqbsjTRWczEplxdcr3 av/msnUHiUgxwUqkS5KL1ITJX0pQei+EKyM5AjoY+CbM+VTQYvJ+ZSRXG05Y46SkvhbajacUIQ7G OCSukhs+Eh+TVEWrSIOa8vxu0hfobZgjBr4x0ByaPFgzfIC1eM1mHMYzIqI1iBhnDPFlGiu89Abh VW2bk/8u7E6iB+nGosfPLhwgLZosmntllMPcwkqGHsnOVpRWtp/BuKB6FNw++Lk3toQ6cvgP+dRG Z3N4p0Hn7U6ntrjlkFiEK6wCJFvWTVr5f0uoxpbh91fQVEg2HCUH8NVbIml5jv1s+onnmKGEqUrn PMVtO5ApTcBlYSN+YhY22OKK/y77F3ENHHxKnErXPcqDYswPbWyuJY9AmqES18H+Sh+319L1+UJ5 lQrGvA73asepAiKopuOt2TYrGSPo6l+70BOhtE1NpDAL/UtspTdD/TEWUe94qgpLlAS6ug+RSknR v5BEyLaLXmzegi5okjdAfYxFuNS+Ddnro2P8gEK2ivUZocwXCSSpXAqZQ7SFDiFZLWfWN35QMBIA yqGP4Ktcjwk0xeV+0p2F3GvV9N8gA4yt4JFH2ZWd4zU2zlEhHYU4cBK/Xwdwci+3SumrdqhXBY/s Q7/e+R4DnNUBslPT4wyNniLKJIlwEzY6fnirFCk6wlpUD0pNkFYQPdMr1tE0l5qOi8tINKK0JDIb +hNF8EWHXZ8l8Ic9JUmgSPK6Az8H72V8giIg0Z+cfUZHXrp2ooia1Tvieou+EqmrQjKq2RSEy1Hs rbk3k94VUxSaIxhgRSXwNL58y61m2HUUtiV0sOPE+F3ira6ToZfOrDjyaFfNUVZZxva3KPfE96SL 06800pBqBCfpR0XmOU4xqo1FhD8UGCLkHh9DUq7JLFABMvbOoMS7qZibJNJJ09C4j5MLBuHspo9c 2GfNtfhFBXCd8RQ5DstJTfJ75itrbmxx70oK0rjCA7nVq9o4bSduHS9qv/5PKPXpqsIGa0KBcxhv j1/yUNr5Bg2VoIDCZv+0fkwLmBNJlOikhdUBKi3UzmJXuFD97VpsczLaDBSxbFmAOTvh5zgAiFRK CLd7J3Pg2AsmhbmUVMxnefFdsC1hMaEz44dNx3ojRxP+7Fg5mXid+HhQaHhIuGIRIN7c2LTbvmzB qzkCdH1eQSVAzqci7MM+4l8clOcA/7LPvdgIIAo0jo/eag02pk02Mil1avgbwV8idoZv3Vgg1eCq apkXbmm+2aLdgMGhl2EEL1jHyqN5Fv8JP3lxd++GVZixFUTX3jk/J8JGAObLG7saYhr0BuBJsO2w uYBHhFbjT+I6F+EZdEIOHhhOSpPG2EcauxZ4dC/bWjO1QqlCcioBntptevRkGNnhaMCuG7tGnJgq DvIE7hut+JAHlba24q4+i5JpsIGYVDrWcjoMp6p33cjFhUSbzl4mTs+KiCPRa0pKIXQtZ3uFJnG6 rRVLMoFJk32J2Ce3paK1JVjIJ8j15fJTDUSAJve9NW1WBhl9PaZsd95H8WmRcwaeN7WEMgQxhqOM QJkTQDad/zEO2bG73eZJIifwPwYLQTLSBTNJOCOxHOBOvd5zhQDjcOtljj1L8S7EroKtHiOWox1f 7Fc4Z897/7TvcihjoF/wUuLW9fuoedXzZN27ckTG4SfB/0jwLTK1TIjo/XQJD16waGMe5j1jkzB2 tS+eILvN96n+05iESAYhBAWENTSTShqvvbY0ZMPG1vpep++/zoftu+hnBduHIXujevDX8uvgEBQo CYGLr63GqOMzs8rhmq8ZM8qeVYy2MggyzlPwqysAElszGlSIDTxXLn10Hatge3swIU7R39xgZI/H t5jNvRbuuaQeaB36aZsdCAMXsevr+ihUSDyUntgpG2V/Ll9Qun1LQ5hZA0N8bPbWWf+pKwKUUanT ERQQEorz131T9D2u1MIluSOCRNY0MrtdhWMoKwzfbSh9m8dYHDOfcocf+JuH2SAzz2d3SShcHxGU M67tR0Rw6W3VLjlbRZ5L/Sazx+P88S9YgQFMF2pQ2jU2YeU6uyWe7mojLyJvfSwP4NlrnvccxA6/ 54TJaOch+g1nASpEtba0yEVstB0Y3Ug4m2UyBXwnjJegxFbA+AiIZMgYu90RCMl5+6qMQITINaHh E2VqCrxsVFAn6jDuRSQwSirhGdI/bvikZ0H3hrXOUG9B4jzwNJj53ycJJpzVczuTHE6wy/CLojqR n+UF55RMDPsAclR232D4TEtmGXjmUIUQNW78XS5UB/UoK5cQKikFtLRLKoCRll/MY2+X77Z+4qZs RUhRObDKCu12Oea9TBvyhi1xUbjRTNj+8iCAwPVCMUdTi3+bNca85XiXVQaHMkZNzv3mRYQ/U3me 578yExGOAteS5fyzhAZ3ewFAirbARo51U2UloUePua9R1gXguP0r12vH51XL59trX0XigKEuHQpb GV4TAku0JaQeUWrgPx9UaU2Y0rukyXVUDU841Nme+9oHBxKIPEEWyJrIxXiPEN13RLwSdaGXbIfZ TGEZgojxmAtcE4Ih9fiSLhKis3lmBI0+qb2BfuXJ3615a8d/mKI1wcqBQ0aI5bFgFq3rCTSQ1qlA 1YZB/Hh7Nnhrw39Lv+BrzA9VQbN9xoNlPyl1cQ0o6ZkoM5oFsBUB93iCj9SN133CLe1A5wmjvYyX AYwWXqUSCSfJTGmaeyhf/m69vCp5j/RSy47dVbAnnWLFMFC9h0xcDbfIIUW35Ln8pnDZyFXSZ8Kt wwsYFnH6aBRZff/qCHqdHPRKoYyDWQ1DV5KTKdSQ9CZaRgAyzm/l/NB5zD+oZWLCy9HPnogIzlC+ bAVx1hkQJDNUn2KCG9pQuB9pwZTEi6ddtD+TC6wHyWPTApAREeqBOjKZFYJu06f0h7RxigNDhEsb wi6LbV+wd3j/4jc2hubxC/qw7B1Se/ohnMDlCaKCNZiCOYFkelXmMpMCooOu8SO5BCGPFB6Kv8Ni 4rTyzcZPVF4MSBzfT7GnrbjbOERvsdCRzVsARSQkqN8EgW4mx55bQkNT7vFJa1akQ+wLO/HmZZ1o L7hM/FTI70XNGYbSRTSi+0aIc9INolxtwe/upqWvSbsBMICr6vkBh1Kc1VlcqN0T/QgnSzbBOEHm KkRcjgJLWVIDEZsuHAK5lIiQEH9E6Cm1/OMDnwm2Uk/FQNGD3Nnxs3pUw/sAZkAO0xAIidiCiOOj JEQPPE9mfsEP8m+gP9R71H9YUkeRrzUbMDK37IHtHODmKy/riWhel1UkUR0RGH+fNIetlv9fU8Wk P7N0So1oQ/HTmdp+p6WE0X0QfvUCVbK03pidfHsTaq1zcWL+eqTV0FosWcA9Sj+jXjzuRFPPzm+9 NTiRzJA6ZVrp0UOMcCjqFoo8LdzWgfYVNsAGVnwECJX2Tdo75xugyrvGeLUueMKH+5TiefIzBf0z nzJUHnCj/lGmQxs65lLvbygIjmGE8KuOlAD+QrMx8ZjXhXh5vpJ/pGc+UomO0CPjj61ItXzPKYpd SeXZJtlCkqctThV7LuWaMlfUJw21nPTOPrs+5sfsqQkOz99DVKqasL+4Sk14rf/+O+YVi453pvlj JfswvZ7lZSjwmdG5BvlJ2RKix/hSxRurVFjTWo4YNTJtBkRU+fonvYkg+Vg7YtOMyMcI7DEuHhet sLrgzCHwl35wfa3VMkQZnOyxXkCfOWZFbh/6gYkS+bB+4NNnKPUn8IPnAPtBpw0lcicj3zfciorc gqCNyJ1G4wSqyV+Q1cmYcKTi9op0wttX30I2CfECD6dSoLWUsP6UeRq7pGKl74GR5zZ+fI12z/fD VJ/V1bOWdQrOKP4+3LEp3pb8OHJsYfFSr1Gj/JHbDXZ52x0kRK536B2TKeIU0QRUgzrh9UV7hYZN gD3fYOj8eF+H0AkgXWj1anUkuXQvQIn0R891QeXwEEq9Xy+vLJvA2jUWx4en624Pw7OtXVJp3FT+ ry3v/7VVFFzQ4RGv4w1oK1HESyJPDAjFIECqzQKXY397ngzDr4WL+hxuzTl7F4kMQrUVWz8pYJBT eDeE38NRsygl0AbXIWX+UGX0SwDKSLtdCYvnsPh7Qplkut1SgWDP4CX6TX/DUu0e80to9Vfj22x7 6M0KEqQ9BGXYqxSfbhP8KJPoYQBJOpEthjpAM+U/8fWeJPYC7sPcNrrt0YMiMkUY4nKVoUA39bfh mObccM57rdqig1ruRkGjfDzJCU1sbVRaZJm0tSkXd8/yzHinX6cwPwrkN0N2xgUEXXk8kGhoc7xV 36AEIDi0wkXqDNUtu1iSBkoKXGRUEU5APe1EXEFyaydZocUwNLA+Z55YZHUFVyKwYx+QoycXJEGA Bjj6h8/WzCP/AfmRCgp3W/JGCAoByp9I6puDeOR8UlatqEEkoHsmwKtGx/TLBMKhw4OrH3ShBdHi ET6v7ymT8ouOCnvUBP8+XSiDXMJSwTB4Z3CC8UJspyu/cfvGPZId3y60J+VxwRw/SQu4c6kBRvM/ 1AIWHmjGVhomoYPsrDtNq16v69Hp+4XTdkU/BhSHsDmDMuG3h5WANsLIXRlZER0Jzh+OhrE4Sf2v MiqN1cvCfn/nKZVTyIx7rAwlSeS9JBwGs3bsoEXgYUqK5XvzgwlfgW21oBMebX0LbDZ9lew9yxVY /dcCTSJwYBOhU5GUGO+GKC8tlfUZafGPpauuInhpX4oG00LV3w266hgpy8OD2INFs8SG7H8XFYuD r0V+EmiAwgnxqvifDwUgM13+YXjUb7uP0M506oLBPpn8F1WNUeIMswZLPeqb09NpYL74l5ugyL+4 GCoNx37jFFqCQn25JuKhD/KXHctaevgC7L1WmoRYzOM94hEZE7ggNS2doqYukfVn/ZXbMWSpwRSW pC8KLwgeCX6kS2Zs6qRJjEhlGSzlFVauIckmvlOG+Inc9Dbbaj6iARUB0sGPRvg9Qc+zPb7pmTir 53ovmspz15ChRoSz0XSodX/HM/Rbq0+txSJMck9836XXFwFQvD6Zs1pTgylAZ8buvwyLbHvKHR5q B7XRj5igJxcnc/Ar2zR84Qu/08yVl65l3xiLzRzhKWYDvykgZLqZgNOt7dKn5eSPV39U8Hfjm8bi Y9viNM2RqxUx3ySueUNg4DGX9r+iZscyVawOc0jLpoEjfN2Yf4eGz8eCzm63qJrzGjTXdVwnejj3 3DqU5ca004Gjac7Ya5hDPkh/k+gekDMX3Az/9skk6AuS0Mt0/JJhVIQ3+RuvguUjcVZejX4i43Sk IQXpjyMbuJoVzPihM+rv2WhQtTFmedC8V7CAjdGdd2PIhsDhDt0xF07pIQF24vhSSL6OO/db3G4X LehnuJtM5O4i+Mt5KU2IBoQoMO7fUcNGoYjuRKQphzzvgvNC0MUgJsFaJkd93910IQS5+jjRU724 Bdp8srpDuWQMzFO/Ummkv55VAmVBn+KtMSBLed3MbDb6qHsUCYi4KZcdnCBtKf+/d+QknUZga1wG UIrHHoVYPlpPDhl6G7RckeTfBovTanIGXUun5WnxbpAsLAUVanTccL/BGNgBxAJEEbsB4Qwz0la/ QRLiZ8eWsdlmoSoGJ27g+LlyllaS+gYOKeNQe/RsKfqq9NLvVrPMoCz04hOKKXWrNa8ZA37kpsUd kW1eHDWKLXsoDO9qRX4dgor45KR20p6N/ySia2vwuyUZqLdJ3Vy6ApDWd1H0aXrGHGz8mePpHYpB nDXT1RJ7kVKT6icZrfXM4+KXxL2qiOJ+zoru6yIhOGAaQjkowbH7JhDCzi2Geb90o8HLdPlBsMWn plWhUeBQE4PFiTs2A1g27CgwtELssev+Mn+OppFRVwBCvkMXNXl2Szahy6KO7zPAZtgpt3Jl9UpV TLu6fzsBiLUgsBj65F/dE1HIulmQ7LuSJ81edZ4+jVcWUtZTNg9vESJ/vBQ0LSJmXE/JlOvL9sqJ 2G3/ZPKEzeEErIAx04tyO9qbl3XDs3g5I4m42zESsgO6w202Xk0nGba/Xs4X+G0xD2xF29KpPHMm Y31rFdiE7CgQMc+hb13bNCkg2uY3EiwCemhpm5oZ5x9+2z+iHpLUBeYlyTysQm8+eegXqVb4c80l aulApvaqmW5zH2kWABqdLVvrRqwfKudrxMFbl4NA+D0FBQIVZW95lLvroJokHBm2UarQLluUySza waCyMpi3lJVRXbqpTr5JY6x8QOgCUqdVvJt4tiQqo3JH1zCpX/x1SSfbIou85cw4jbItzfJBc5by UQBEFAX258pxQcF7s9yXfjfxz94azTtJhOHigCygszPDj7MUFTaZRA2CTCwnyYPk+mim1ml/oaVe IAG2FTgMF6zTRgULF5X2NEyIA8LtLTa5UktL3Vug5lLZUZx9A/4buky5viYWK2OR3u8uecBV/5Jx eC/4AwLr+mju+z9uUcwm1/Vi1fX6aBdU9rgGWolwBHQTJz5DD8OJcZ/sFjgA9IxgSPtc0GNWriOQ rLi853Yzd1kYYql3dmyUXH0EnJplSHohGPsI6HU36e/AcIaO4ZXLmqr5fk8pw4mi4OEa7mqG9Een FYeL8KVBCobRGIoyYiy5uVIrOn6KUVrYkIoR/3CMEhGJTYHnvPru9m5YDcN2O4LwCn/KOF5njW9g 6+KjScLKEWth/CIRA/DdwhEumFUWIJyNf8cjrHmPL7s8+lzn8GCCGGzPMWpIY/hhcG5U+vhyjZnv OLmmsr73cRgRolQq2zXqjSkLEk33hW3LK8RLT7E7fVvKt10FSRpfIOCP59mzvdEs9yw4l4vxPEAa zkSStpHj4T1Pu0IpweuDyVummsIONLQkZAO+gezWMBuXbfwKpUIrUoAXj7lbVcBh56fmOc3SnbpW 0A2ywZJboipVcIRDUGzkRjNtMwbOOo1vJpK6Mw0lvsiS3vo3l31q/eoZdLR6XadPhuxQgiIpmsBb v9R4xeXEhkVQDkYs8ni0vAGb93rxH7s77QCOs0fXMBGWpDFzia07nYbYGn0Pyo4MXFDj4ESsUBqY OxO1Uovwut4nwgnoZ2IjWzZL25dQAsrPaF6RkTCJowLNXNjwthTMoS3xhSyCCiZ5TOjWIfHsb1+w zUCz5J0+VotNr1DeGPg6g0l8zE7K7PXBYuiyyWhWNzP0P2Hhjfjn8ou9bbcWgBtCFsM74hvsckLO s79aupocOtBirTRV7bMm0vg1wDDf4YuVb5Vd9IN9P7kYIKaEucXvfaWi/S35SyAwyHAzAC5w9Ggs McHdTkjSglHQnRBxn2BlFrTWLQqYbUkBohHzQY6fsrISLmsQOVgJxHBfWAdY1fqZyOqx7vU1krfl bmhhPgOzcmsQ2oRTGGDseyMgs9fHCjtnPnUUu0OQ7g72YB/LzY7ckBScX1j71pRTeNXeKl+W52eE XzYw/wE+dz5izTEEVFYNgvO5fNRYEfpJoGXdPmWolh5+gwZw5ieZx85+Ug4nIeZoCwdSbld0flT0 zsIQRD7fqqcxeHZoLXKxOdkYa1ESubjY7vynaEbwZTbXydMHZqcDjCk+TWw9vjK75ViK+Waycxku ymQ1UI6YcgS7usFe4luisR7SVlwpZjAmJPNI+JKRlVPZid4UJh4yJo0WO3rWLxaKVK8XEHUPtLT5 0V+8gXQRCVa7Ev2IkcAoGiYIy+sCcpyTMjLvXzfQ5pHMQRQ8a900N79hwV1dkb7s3yypD/Cmz/DJ 4+EdCBe0/Y145HXMvlnsEQISuEjurDx+lQydqTYE1bDW6WPFIhPTDdwMiTF+a+RINvPq3NtAEfZr 7Ov3MTRmLnaBQZbw7vRGEFxGK1e16srLqs+fnEPhGj1AtbP9k2FPJNEnrGDDMdmZNn87LIQNF5nh OjGPEnThaJaVzBc/SC+2Z0WHAYE8AEuVkUlw1qy6y03uIC04m49r2/kQz8P4AdpmPxh2mfhl7WT3 XborkHJ+mC+C8InOtHfBCZw69Kv5j/B9zwZvnaLrqiFufuLdn1tBhYYifo+HS8RRZR3SnhwQE3Hg E9vJnkpaqb0gsyJlqltDO4mRybEbf5SVf2hB4mPJY8sqlsF25KQbm+8oneA7xqy004i8nubGCtdC CyZwXoFXS6fURGW293ZavDxdGkMfczK5D8+0lsvuNKXC4aZkj75FlwGWOEqTDvpoLJryEzZipt1L bJHA+e//fD3g4GKbMoVnNcUE7600RPPhMc6lCUEvZp/Fg2Fst4As2cgarlxo+ZxWw+9Nz6ybXtAV xs0jD3djDBEQqtXaAuo7xRZ6duza30/5pLI+vjBsD35ZZQxOzDLD9mBNchcSOBbQPHRXvBua203s wWaeX9p6nEjJreHUKw/LElFffp6YTBOy6PElASoIL/liIpp4y1LeO3dekk/fjp334+DTVQL1s9jF 5pNEoZgEzh1ZrL03cPBdFWmeURVRst77tsnoxXVA+ibAjdknUcJRrDCwBpOQopsakzx8olz2SGB/ 07rT+hhxaM2IiGz4bWB20nd4E3Hw1DLt3DlFhlGxquSH/69/jjOYbVc0mx60/pxZN5bHwtpJIQZD 9ZjV8k+rZOa3dCZE1Nk2yh60Xzd0Esz1S5o3bX7XEWqar2kq1bVE35A/vk2nRUaUEImmnaoQFXAC a+Ozuo00ToEanDlEDxb63HrMFb2Ezo1sDfAqVzEWr2zYqPRjWyD6Z+G+GnioXQYqR4BdBcFDngXW Fic1GYBlt2teLo/bZCoI531+sA4efnqrwVdIXOBXTW3ru0HqgkL8UK3uDIb4mnpeQwTD9UtDePhI XoGGRSlNwS+YaOpIVAcS6H68urvem/iUImmMuidHrobgcEsgllMPhyoCZ7hyHD45cfLRvV7kJmwq qu3PIkk4qehmnsjJ8j7/4mHnCueNPWHggYYotJVu2z7z0akIQR/zJ/RlInJSiH2kNiLuDgQSSOlP gXjn4UoRAj/zfsfoxAl/hUSTAvyQ7buux+9E1KWLr3YZFfDpaiGr2HUv9qt46FpkOe0VUmnInehA S5h3N2ya50W+N04TjWIJup8qU7h2OWLgRsfHbgN8D9GvW14BUQIFHPDcHFeIZYyPZtwS4DsNagoR z/VzFS8wXCmBO1I3EgP11rNF/dLeOkbs66CnKoUc8HVy5LI5UeYZuQfgmDUvYYCM4+T9jTfrOafv /mHjPGE1BT5VA6dYYzeuqNom6g4Mh4JKYaufR1yO64Wibgg8Ax+aLW9C+KSLrOwM+5YQnSG177Wh xfhMeiUHhGIHUKwvKz0NbF9qLQGILChM9It1OOEZxr8/sHiztjI3Vn0hTLYDXF0716YG8SjOp/ha J3hP74y2hIkcYML1kgfx9n5P8iiS/9XX1WH/cOjqs3Thzc0ZB/2fAtDdSMcSIDOQMr2mfUZ+HvdL 3BHvdk+25zgsGs7nVmc9+M7ntc33p0KZOEZt2t+olkAPl141ytqG1+iYPqlF9ARHfJoq6ftOywoI F1lpBn/GRkM9NB1gYsuVfJpqaqkWWLukZ+FNcmwlbAouwNcM49ceZZG1nKwgRmVkncNtzrW6aYnv mWgAkWDr7NJWaI96QTzTBQIVUtCFTvuSRhJgaqs5Y7pw64WqQ/CMMcOCdR/leENWCu8SfF75DZZh zNXZxZNmDyd/yqZaKKDhoUgsd0XDwLqUjqoX0pthx7JOWOQwMIU2TeIl2xs/gaBopSRwMv9JRJkx 5Pb1OlKUUygNJQO0s0ksiT0DKDv8CeSV4TUf2OZiCANog8d1ezoFaYaseUqdClOeZSIwUBZggkIc v7LVWlagO6pvmsd3qYvK1NJLdCkLFWs08ziLdNvea5OlaCpdcWpYVM8SOzhxvTnNsq5kcMDuiYul RSTSs9kuCrh5IvR99XJs7z8Sb7FaVKdGoQvOHjqXyWdz78uYYFY9v8epnsRqtc8bSsD0QFBcy73G xS5vhTn/hzcfVgLlcsMMhrdOsu+koQKlVtAW8cxBWe0IFQ5fRiIXS/p1hHpcl4ReDiZJfcJhB6z9 YA/hOyuTrEc9vYsY3i5s6yfhjLtn0P6FyBsaacR5251fT7VzszycoIRwkC/xX+5mqOFxq9+22FQu iR7s3UxyuSX52CzWgMejPGafZbqp9zn3oMbX8Hq+Q+KVsEHEutxYhYVSw0SlcZv9VEBmDohaFEkc 8FrrWkSWvQMQeeWGJc4a+qFTqjB9altnIPJMBdYTtCZmBQiK+lQMiV6jy4Il6i/bVR0Dopbu05j3 04wHGs2Pboa5lCtJ7399Wz+0Ymsln+9ItQX38P/466T5nDMrg153mnxxC13med5oFw9nBFTEnv7o Hkr9rtVDk4TPRrqC4s8tRNW3YT06aIiH+LrTMHU4JQNx1+t/o3f56QTK7QHCBVgRqr7lukCnWO5C LfRk9h869iNgk2RSvGpcvnjnMEaCqLJ+Dgk2HA5z9OjhQ85RciriZeuNvNR6qdzVF276v5HEPAVe cabvijc3TW1vdUs40VR1tYYI/alt9O/Jr+hLpHWJ/WWdKiM14Ttg4rGUo2gG8ezaFR6ZlUPO8NFe EcBDopvqseb7456LLYtszo1toVniccdt+vO7Ij30u+3h2SKWX31k2GuEypgdEBe6rhsJFY4ooksj RZY7/Ss2Md/gOVjcVW3Z7Iq6sYKT6Kzh5bSj3kapXmsn2neEh7SgD8l+jThDp1n0pExjy8/KVVlr duZZIvKUNRBltjrM4lbUOfshun/l7SULacjFE2E2D8uZZ+NyLseeSpvHao01fmspnDIeOv1v2Jim S1ud1cpzRY/jBAMni855+tl4l0JyMZ0lPgHE6ETLyOABQPfHqaADVijRKmWSFV+D5N098MKHuXKr R8ibK4S/ZMI0DkslwXL8eLURFGHB/4jICIsSNKjSCqf7kCv6nMPGBN5bVoudhhukKDDZQGEXB+sA Y6bpMvQAAALJ0uJSDNfH8ThLh489aiaECGrkI8LloCXusgXGaEMDk8uyM5TPwwOlN38QFbraXtCw cqd3Ysvq0LDhQC26pl52ECXAn7xsBBDVeb0D/h2e/6bzH9Re+b356emyarLFfvvXraUrnBXRQdXM Yt3/Nx3M4q6smjKN0FBnGSy05r+KeanOVpSH96Wxqyd802cKQPQezMe25a4gSLCKsJYHDU5t9joR TNv+JGn/vP9ttxhvwL0XjVuHRUQ3b8RY5noJ5z+/egAQ1urdqvcy/3qrfjzGPyJwotx6PaS0UENB FqESmo02/OzNdgUUIhua4+/24njlqfamdxjZNM8+zdP715DxaUwH73CIbfpmQ9jF9mOXQXPlmB8O FLYUyPhcTZOTwcJFEX9HKJrdXZlBYwPNOtoQ28p+0F3Qo5k1/K+KBdYUuuuPssyOK2v/nfXlb08+ un+eIwQNUdv+LZPcR80oqSdv1f9yu1BTLZeBgNZnBqme6i5cONKEtrDHEtq3Y014rce7UGB3LOWJ WCxNMbgBF/F4huPfma1BYVHPAgiqMSbBkq15NtnFKGehxIE96O70vvvRCU0fQ5Ip8QSAR2GsMf+O KUsfRF62Ms2HIJNbr5CBcO9N8XAXH+KKzMhXTpHB+fyqk5AmINYaNmRW4T0nB6C6P1HVawONPHzb V44BKNOGYyN5UaQ4UmW1cwJkCZhccDMoHmrxeda6j912jDao0C7kS2UWw54gUPYTjYsam/GxxhgL zhMe6V3892+9ctwdiVBmZIoLIV6v4So2+ZgNoZ/s17DBVdvoDP3TrgZ7JZu6KEse/Pg5nTPZ/yoE 4ZSGNAF6WbGyUFxnL0Sdb93wdmxOgKObClCcOfHU52bni0XY6YFWX7jP6LZd//8ZxyKcfB/bjnKD 4xu+/G/7XQf1qkxRU3Ar9JnMH6Co9bYAYRkRBmhCh8RkAHQ+Z/Y2GlWXqE4bwPSXrS0zaIW3bsd4 VeNFzsz9rm8E+ta5HYfMHgVytYIwVIfRu1y4I2UQmLaBjxPOqnFqEszml2VooUDTw0skKH1ZUBl5 dJ0wMyPV+4+3Nn8XADKFT2N5gjc3dWXIA/hAQB0xWuB5+o2YW3ZQuX/sIxDgV3CJTMJQS2CAa2Sv FYlO0oPc1A7wUcwP9phn1b0Q7LdYYG0LwcMeWHvtnLtC+iV+5OaErUoMWFxESTGeFrwK47wVz3Yd e1DPcqciTN8l5OHdUIWSCS/11be5qa9yoCSMnFlFeO4CreSRPYHmoWpBxyLPwFsn121clgSIR4Vl 0AJVSGzUe/CHOHQqPrAnzbg7wAPo9CToJqk9YEJiP7tuRqpOBgoBN/pyfMxLHFt+qYUTpyHlsHPn JxMfbwJX46scEhYlSkKJWesrSDfcjYkPSWmeJBqkfrgGgGUWXGGacx6GdmduT7W4nXW3c+Tdosx/ x9zJwI8/mA+Z/BhBskAAFz+0UbUIxlGcGPhBByiaPgKJpGhIkfCgvnFQxI1UmhelNCzlqlw+lBWp hkB+24zdsTk7+TYx9ZWFXfXSR+DjdkRCr60MW5VlFj9xsAYANzNLYQ2HF8pqY31KuPXcd11nuZd3 nZW7/55xulXdPJReLs/4uEO8I4SAr7mVCk2/Jx+5TdDwOT0Bbnv3XVwuDbvpPLVPdWs+11vslRpf O6YdUPLEKRSI8Ze4iZ1x1ZxCCF+0XtGq9v2GIl1ERlGMIu+s6VmNjlsq+0dMNYpjjBHXtzUcHJrk kWL0PipOf1Mitz5O/mD8VostsDRBhV6rTYTC6ITkXB9TajRJABkgqQWyIcvTJqilcj6Z25ZojBki GVn2l0dUOfO682Q3Ap+yYBpKZq6j4qyNlfsx5YLWsBFPFKs3BZss5/gcXOpagftJ05uIGS6QuU/G 5nkM322OjejZ22s3MgvhzD/EacffBKUPPhKR8cBMV+qdHAqe2KZaA610hYrNKrAVBicj8Xw6wA96 sZvtO3xbYauaycZBaxXWiJbg/Eu2NtzCIE7L0TlPM77RRDie4ZpgazU153JbkUdef1lst56ZopVm qetxDe85DclZSmeGJxlWfsH2XlQj65YMtRQV42QUZEcEVddtMgC1B8P+7wtCb0/X+sTA4aSzgQDc V85zCIrsq5CRTRAQfEdiW1K8VBoTZj7R4VypBT1LHoqlxFhMsDraarNcADRz158OG+EyQWqEBofV qepSQ8OP3AEBi9Yj7CtSnrsD/ilpEqqN+C8H7RIh6sYmf/WlvQXu3tWGfFFYw5vKhV6piJgVt2d1 P/aWXw38rkx0oQJaH/NA4RkNCErV8MR7fUlWPJrcE26ucu+9aXh5+2e1iC5GHROFF4NNuRh2BT1h 8xFXnSAH37xqqgv5Q9QIdcj2RwAAn7IsPLlLL4yXbf2QHVeTOcA6SUp52/GuIJq06BTxj+zbO748 fY/mFAb61QLD1xEhMJo1CvWXXUAYhVMmxzLOUwNJ1Ckg/+5I3ZF8PMlJUaQP9q7fEUKGsTYwDwD6 LHtZsfltoRrs0P0AOcxnoBNUWNj1xrwU/b8Z1ASIvIcNvSasBxlJ1EF3q59+5DfKFxV0PgRLxm9Q ZoLnIrVz5gmKw4qJTdD/rxc/+vLIe2XNyHLfGuOToC9JduugQlop6+NhPph9m75wF4TMaqM6P413 2UnXZ5EX3bZWUWHAN1fy7KHr+JYsPqnNu+ViQeB3m3fu3wjpAzvH8S8srJR7f3p6m7LADOjhKgRR 3w5ClyN/b9W0zLYS1QNmt40APFiMlD0PIRnUVU1/79ncaC8QZsD4L8EnhRbgivvorVWBeV+QYDVo LLvBmsxIljcbu3ILYWVPwF4JSXsXpaID+1FWa3l6K+dp+/RydxqNhmoyrGFpG/eaUK5ck1aegX5s bRkf9tDGGo7KVCLbfceYvK8xRjxR3j/icqyUwUZ19Y+JNplqiEUgnVUAwanEKNlEPOuawss9YLgR +ZDbHH2oesKrfYINmB0rVojeowOU58YlfhFDTDxeljp7faUnawCLgCUFCisItZbFVG1pn5aZsmWc y3uZ5lG4t1FUTYaxpFxhvLpa5H7gbShPfsSu/P2j2Drs3mbTOGQoV0f2arBFih/9k8jlJTk61k/0 9k5/EI3rbKxDqIqqEQMS3sPX3VIZ1+N938pzmDZ9EXY+454aAAAjLSJdBo7z+Z0T7KRUdJmLPOXC IHTFe7mkQjQdapQF5qf9me7vKdwUMNo5NQqfowHf3ruE71izqSmRgrXQrpzGEIjD4nyITkvg8/5c VIfv/X8Rj7cYjTow34HjFQyXmYIHWo4LolRcDwaIQuALMhdkDxJuBEYHqY8qGIOjtKySX+oxjZSx nsDL6CX9gBub8Nh5QmJx0TngnKF6CUIT+l7JsL4hXR98oDuVAxmh4KZmQ8n6BSLSBI0MhKuctJtS Jr5UHyFfN2H4CkmtAKkRTbiCiTbwjSXAncYgak2JJPK+yBvW0ZEtgvuoW0TjLTLamwEMae5Qs4I4 3N6kIHXp8GovT2udrZTmDeEWQewuQQubBZhkdOd7ds7tDUG+JpGkUBkAIGrJsZrTKem2Imnmr5d0 RRbGbefqI2FQMSupwV20S5OVnf5eXNU4voBQ0h4uFlyW9bymC+x1HqADiR23zqLPsZSwbUkyuqFE 1sFXV+QUZtFyni63PBczHb9vLfJa7XOLYrjj88x7e1nhEKI5Mqfkiar9EwGg+RnFOmT+UIXVylgw eF11hqSW+mMsHPwZfAVL5j7twZgvpZwIeDwYXNP8YpLJj4aTl6yXA2mvNPrV+wv7B2BZZqLsH2iL n3NBhN1+P6NOx1juFnVfjfPDLvjzAjmrG7+i/dDbZw980SMpqOFWLRI3o+q02YgNvVMU2GMKbgbo bO4uy5pJf8QLimHTgZ99FUybXdGv58hiJMAsmmtAHI8W8kfsgk/qtqLun/tzkbIxqyvWXLpuZAUf POGdzk5boBRHky7KEcjm4/q3mN7F7phCG8rJlS29AlyWMVtBx+cLslrw+mL1VCYd9sqsS59+Zp0h zUKXGEhrWio+VoDhXvtdWPg0pk4+aExnqv6BBEgYSlQ2/axzStl5nak/44UQA93blcbrO+Y10QxB Tlgr2ZryGF9o9N+holChRxeddn44e4tGsrdLvualy8qQpsd1c1ELKlQaD3cNDX79TYRL+nNh3cpq imVKhuKGlz5IaxU3qbdWVCSYXpUF0bY30iQY9UCMSZJqhYKYJTMR1YUqFo0wQJ6Br1s6ha333MaK tuwWT3W4K28IAd6ZUxxJWCC4LZswO/G8CPeNPp4MXdNAUGPz7D2K9ZjfTKMmcuyX+xCFKogSXd+4 jM9FkIZzW0w5HCY78dmkBGcjrPQX3gfyji6NF42K4M2H8No0n8oMIOa/J+kYawn4wgoDxO5DntmP bhfOcfEyt9ClE1keeRKOuhly14SqymHr2NbHI0TNNPEVskMq8Adtt6WMlatZsht47/w05L9g0u1e BeasCkgNVjHiHU2jTEFQzUhmJQQa3TpH53SJP4lV3SXB4LoLirOctC7ZXdtlh3jHvFs7+rSZR0kq J65PltzewdbPhg1sZvamRmVlrcweGzyNXljZeq9qb6cvG7h+mQqT7m74Jx/rDLF6fJubSc5qEESR 3tw3cC+CjqGhlcrVmUGlIChELyfVg3lgQptGTfPICQFrIw2QPqpeoP9XPxttD+ZSH7w8Nx07zi1Z +eJaG4vFl/fMnidlf6c5MAr4+JxZmLTp5bufIMyxUTqMgSdYKGX0zXiy9ZwPDhEZ1H6tFVGBI2Ld OskGWjeLaZQYsS8fNQizcmtn4PsnkNTBXSnOChDVAF2vXi54K2YbU9c2qafRXy+JbJ0z65HItZnp S9V/6uqnQKNrZpUrw+ZyhBQ3xH7rHFTaw60czVrocoitSq7xIXEXdK7Gjyde1In8koD3QcpseLM8 n9FBe0mOlZ03+trkzfF/lon/50Ysx2+bZMKsOKlt/CoG6JGbOWRy8VyI/zk2B2aApIJg+cjrdLej UInIhUGx3KXGCAzeTaIcDPxW0m1FfrJ/Mw/GHDdXwOa8BnvUmo5jxgwB+/OC6C2fwWb8gjKZeNbm ow9PTXN3mvS055FKkA54dRlDNBKtYnFmz0pOYrwO/pEPcKvSxlP+8uXuVasW+tRE9lunawlLUiWd E2oxyT2VZMi9C9WJQ4fv1CJ/6dJAqew14AZvF0mLHItmVUyNdnqCl8HuNVvmasqETHhxod8To86K UsQkXDRkteNiGLrP6pU5WaIglX7ZTjH7QNTWiBPL96YmU33inIiDTChWuKxKDD1Se5ZFEfMItQSr 10Ye7ULcl/cqQZ/W84ILaojx0enxBGA4AZNheA6QPMPKR0fFhZjKaDsik+GDJkvNwp/xcHnHoBoO 5aZCWnk/Qs4LSB7hOaBdJoegyxrJbVQYfUWLKdoXAMN1FNFWrB+6A4xYevW6amrVLaqsDxemfTFF b4WHeWYGStZoijyVFx3C8sYm+5PyybJHkxVXOdph8vL3FtV1b6gDtWo+A7DWqZWiCl+nxiJAEQmW jEk3ahnKjPEpB7w4vYkjS7deUCl9yc1mge5uB6H+4+JAXUmhkdPb5W84EqigrFFgwT08lh1RyygA hRRI85v8iRGRwMFanNVWnhuCwCRsHpX42oHLd/ozX9dHX9W4Dt7/kXRkPKKmnJJnAfSBJBvtVIBN 5sUEp44oR7gTLZgNaadIjvQ+OSA8iY4yrS12Rse7xrjIkX+IDHEe0r8Tgg2QNelFzIlis1SVg2Ag 3fbPvp7AOdSwgNN1XPmoiHZEAPwRY+Z+d2HsUL92Pu5Hod3atT67vZ7siP5Ab8MoK2Y3FlseJIP6 HnZThfFS5XeZW/5I1XPMJtJ9p795NbMpOj4l3AIuC88H5nNRwGPmknbF4ksg8/XxAvEXavDVC7zg 8rbHS6Gb0rsUVEvF5xl3xJlMNd8aiFbP/QMX5EjxeQ3F7JVEAZF4EMhLKOOpZNYU6uoV4pd15BU7 63wquRSb33DwMGHN5aSeQdLCUCxT029Y7NMhR+J+EBPfdXGg6UN+Nxs9KQio10QfWtvQkTE3RycL NdHKzZZV3gYn3R6CE3rGK/XGAjO1YytwnWB5dVF/dRab2YKeSoZQHJqSxsg/Ty+jhNtI2cTyD2BA wx7cUcDniK/5caBStQWlSZ97nFDC71d7/rxnBTg6OalwGoGvm8WnObrhE2moHA23knJc5ARzZHci LYq0HjuBxMFCumT9yMZA1vNHEqzbBRAuPGS3Q9mgazRhIN/4oFRD4b1Mr8QlTwmTCQYInc98XpG4 v5AuSeLUNpTVXbsZDRbRcgNm3msYtX0HyWR3ZLOcNo/BwKCpJCCzLyXLC6AEuKupjaralO14BPj/ YHIq7ePRJny3+yHnwWAdM9ah7etnraala6+oXvwPwODK08GOSj3YIzquFYX1T74PoxBcjSqYrwDS oAYjOptF7gyjMSEO7Xl6DZ9CChLHy21CkUwTzxavBc7lqXWhDMvGqN2cRkmr7OW3AK2TrFnVMD08 6DX0bIRhWrCVPkBzEIKivuXJ9CmtAfqzuCbr2L/kjjBnZbUHnHbZ4S1+40nfz6QcttGqn7RC5j90 H2Moop7xWST9B6ZyE6R5UVUQlOiSbmufmFmc9JyrMqII+UWrr+/kfW5/Dotfkxv16eEuBUz2ZHYu 5dHnEnBZcYt6b40/HG7W+EWdMXLhMuWNSXgSlOWewuVQnaC81EgRyiA5H+Cs+IKae8EeG8EFFg0O Kd699GIeaOLr1ZZcwX0YkU3b8WQqpikeOhWb4Dh4GAVjGwhs2Mx2ppKbPQeKEk+CEzJhex6lxd4A abl+T0recWkHZOrEA7mXXXPwcZ/gfT9IQywR/zrq+6em+Ds9amnRrw1YHrpmkoQvnNTXHd9b1cpP eszI4CDinGva7hqVaONEHQ+U3Xud3Yd5XkIAaAzIUPgzj4FAnT8uOW299ia8+o9oZedVNLYx7UAG Pn3em4tncDuLfFsXXmEsPKpDTtWsE7l4MhLESzqhvuJCyb3LEISqpPqwAOcWeHkuZ+VkLGISsE7G vCaIjfNhtCRN7fg9Q//IGJ5foTuUgJXLevKBt+MzL8knISSshad9NygyWhH0wF5VCZG0IK/0SFR+ IGT7vDremoDviP6r39v23w8nRFINfGJIMUS2BTc8v9tceifMP8pX2xPmhKnRf4Rv+s+RZsAnwx8F ngvIpHg/3n4ZXu6AcSAHhMPuTQEDHPKXIyRDOqHowrg5KF365PWnVsLcjfUNjw30ovENHYLDQxMu 6CTwzgXR1tDOaZN0CztNTaSOUr0IgsNL981NNfmjlii/IuHw5DJsY7dXJ2AuPSmr5ws+MD8SCMCt BDsn8W6LDW2D3KsDEqBXPKhSkT6d0CAaxaQPjZHwfrOzu/hAYdv1g5HUJVQAY6mm2/IxfIZIuZig 1xIQDdTOjFOy6PFfOuERmUHm3VjRIEx/Ke47bjQFVz6/OxFx3FQujG+/WlqGO2k9lJX/QIC64BUW T8Ql9vo9TIsAH5vOyWsujgu6bzjFe4Rh8EnonnyIw0re/FkH4/JIGQgamQSgTaBzgkW3SZ+CUezn i2x7Voj4xi4HGH3IQmmnflgsaX5Wn3sduBTXiR9eitnTO8S1Vcvp+km55ZneUBHXzAVVUVhiDpHx CNq4SFJPDPn5fQ2evnwcpiohELyWCo/EM+nfnAu1psXG3P+8ajnjjKjZTVSnC/EkTvIs0LgGdNkr NCJo10857vaCuNResQvR/ZpOMjFduMpGPKjHLANBKzR8k7rJoFLRIn//mgnRWac7SpK1E/LHDZ8y mbTcCj0px/jNllQboiH6ChIhcFFub3DMRxNH3P3e/fRY9AwfAhNrF24PX1GMZpnaDHZcNjubEw64 FjKhP5TKVGI18Q3l14IxYJff8S0iSAuOy+w0xfDQ2Ce0dJ4EwnM7WhArv8ViNRPasRmLFSJTGKZE wVNMEikaS0kS5RSVsUmIwDlkJ4zSQYEQpGaaoLkIDl/+gHyqc48fbtjnZFBCsYo4dlO0qYf0Fv6/ RQ+7rHe0eX4bpk6RCIDvkPI6DkBwEpFER7J2BICUma+noloPGvY9esWzeTmEfT7ekGLzBXxm6rwE 9Gt0ch0NK4aU4G3FOPYnF6WpezzDTemvDWgYOLoA91Qbm+t/57BGfWTEo+dvbAJuOtaWJKYs4qy1 yIZ4XJLsWrX0CH7I1fav5FElINGaaKKZQVqvdZvOiFuIrdabA+eGNgfFCbR4KPaWApL9s1dnIyZ+ dsV1ATOAT95WGT+bUnfNoecT3Ie547xQ6/wyoR6QStQNOhzslByU48R4JabbvUbvefBLSqXx2qbW El8bYcs3ZX7MA8P/M6RAkEtO2IapYBDe/AWXro9X0ei6ZDVD9lcqWOmUtsyuN8IO/ltOhYsmmYkA sOlCXxnrzAgoz2xymMhviff9v93qoEupkbDBWOWIiHagI/r2kC87h7ZDIj98YsuWRc/Ul/TnozkD 8DUHRF8ypVAFcfXiCG8OQs0UnwyY95RfvZI7/SnR7VB0/keE1GEMp7TUZTfini+0alNXBCvPYdKo kqQdjDmEYaIy4seQkHtxJtymgLaxkoGffE2TxIsypROmU0u/uxfXba7WG9wbw5YbDD6YoL2Ty1NZ qLerQlAn5f/sYKzLC7Iq0oTjmGAQyVBnuxKslZpGbWWWnCG2IMfzrVY4h/tK79d/1TgAirKfiODY b0ElqR75mqOKLjJTwf/RGaRTGCG9VPcGBx75GCJzKjYmkNkFqThbMDQngZicMZ2uNqIRTM3hHg+O JJufotmTKXiCKt/Fl4xLYptBJ83FZKtWT2IwgHsdi47JvDSGqzzpDdFAhZkvLKS6RFnDk91KDT5F 7n1n1HQySkeCitrrvZ72lKl1h7XRfd+xlnib0FqzW89F6orsxS2aOQmn0uicc7JxOHSBpUh2xa5S gUAlyts8YUC677RCa1O5a662ddu7u3wo3dB/KHaDf+lxH+GCNoT2KSw+OpxWKyHhdPfj2ek7PcuH PyviZeIZEmwsjW6IRLGbfwR0rq9qZLA0OGzOqwqlrryolcHalkidJNsilK4wnjJPdrvDRiGhFKiF irtSuciMEHJ4cX11k1HmrZBzVw0AL8oYlYcmQBM2Xdwd1dh7FoeaG6QOE9ccOl7MI/1+1/pv5rTJ M4mY5o0xatuadh+sZXbacmqmunYIhRMOTNUPNpYoOOYppFNg3JlCnLISFkjh+YUp6x+qx8cnX2Sy RQvBdLgx+PntpM1yzrFOlWJZDUypt9408veYRUQqQhFAlNMBh4MuaRBxZ2CAsVGP39zjdT6rSHUY QInKDDoqzpklGs4Yt58rtjFvm/laPqRK7lQ6LjEdn962tnqi9T02dABoAWMFSJMabmrrMR9h6JdZ baIsf+0imxsDjemtza7+HXj212gHiq3b3jpmab0PxVxmBZVFkh+/jReDmibYdUXEfqUFUHX0W9H8 XVG97G9+KarCjH6JYo3OsikFNjXTezkUd29Bee1+GzdHhysKMgl1AiYHrY8DiNJno4+DbyhWdOXR zjCI7ivRVnTh13UXlurVYSnIriuIax+b8/ZI+oYl3DW/Ma/WL1GmuJxY4nlqX2F+jjRQfBKhFhRD LR5tDvSw+tyd83yDsAY2ZsvquocBFLZQTUhlkr6xlPl4N4uf0+lh8AUYg/ESKt4o4eapnppm+X1O wd+R5kTc0pX6j1z1HIyTlo1ybkfRsP7GN4nieE4C91QWevV7HOwr/ETtU8UqC8yffOXVQwKxrKBg 6u56mCVn9yFcMdZmEyKDr7TCEGwp614k1dO440ochqL3gqQJXWfEPL0voXMNTRKMCklrUJ9jnp2Y ZDErOW8XNlfB8BCEYXVyBeoYy63ijBiAfU6TVUKZICiA9qMdHhI+QGHYqcKE1A7OQAwjIXIw57Jv dTeZ0PyDS5lA+EJZWfcY0g/2LzRecPx7mwOH9urXI1Y8RXBLIcsJMAadZYlTUjxQ1EoPXH1GLHWc wjRqcIN02qJTyHAM4251Qg/YiqMr9ELMuk3+fGdmMT6KV62n5kOZgdC23/B9I/jy+5WO9ex8Zp1q LnFeaR+Nto+KLGIFzwy/R4nLTcIsix2p8gcu+2CBZMtU1H9aq2SdQTDQ5xrjsyzik5xg6dHrQWOc gLMrLgGS6/iCcPi+xFWFzR+AgetWwXb7HLPUhv72tJrw6WA5ak/sRsl+W7Cf/fh8RWqK90K2vFVG w+gUNbdt22l8P/eRpspFvVk/T62TlF2lQqvzZWH6VH2XQiPIkYM2sHjwhLxJuREcDb3XbJyP8EQT htMQRcKRIZDQ4IfkO+v3cLOSKD1nFefv8hgK+l4GQLThZTKoU7w+/VJ1BUM4RTILRhGH7m1jDweC xSizhCCdXfRlSrhf/MITE1Xp/Jm/2hsENUygcpgpy6dfrPMcTLCCKgP4E62OrcAZcvAAulvYyxbL p+e3Sf0DWHHSS/DE8sc+VWnFVLlrKeDwpPFEfctBIRiWKK4hPm7qox/kt93jjqRIJFhSzhyt9K34 XgWf4cRfcYNBy99IKAFrGVQ8z7WFso4R6pG6CFMa5x/Um/v8VusiNkmjkCSZVBmokRSBTNY38Myc xofPLt3zYGgqSUscc6VmbwQ1T14shg2unSOHuJXzW2nvOVH0dITvf3bORWNq9r/EoRh5b6/TK2+G tQOKlMDs4tIn7pCaA2ogxwaPJVSbPDH1JwReK9H7gt8V3N/gLTBsSDpsODO8L+maAXa31vAoyH9U zoWaMjZ+3ZveFMG+xz5GsKAD28D9E9wp+P6t1qL2Tjja35x82vIeQUpbB1Zk0MN1Q3N/ALfLCRtb /kQ+w/BLSy2YFIh8Xfvy/pBNgp++ln9v11g8md8vVImg2/JfIbbWb33VCJz8vXQGeUemXXvzARCP Qt4yG1qBgQOhl+0TlPYXvQlG5jfpuAIYNHx6608uZWLrgp1UAR2Bs66YXos8AEPz/7tj1BumMxkT H5u3OYCygzHkPPdePdo3nHfyscjtPBA6dxSRT5U6uBS0EaE1368dV+gW7tMQ2ey6Sb6bL4MSWzor nre0TJWsPt0+ikkFcqNXluxCkOMtULT62cPK853gTDijLslfdtKTUnlc0MiilBnjpp2uFrU2czE+ Nfe+CrrZbeCddtiHL0DY1pFY9mNi3WYiUcBNAe2M4cyByyQ9CUPp3MMhgMvY+BrfwiVpryK2vXF7 c1MI9yx1RG6/guzAksCYcM0s0Iv2sd0EW2K14FZTeworXmR8eXqVu0cFvL6uuXLKXcLqe0qomkF7 6Y8KhbSoCDRIvWqN7n2aoH2k4Ubd7CmkL56eWZgYFa2xiGNP8A9kmY44L8eatu0ie72RzKaquuZL zY+uR0LZbe1/w51OCt9Cl/5Txm/wdn/YIN86pmQlTqCO/EEH8RypvQo3A8Ixqba1miS7rpciFMDK DR6YFZHYNpbo7SOVK/8y52agMprF66jy1WUdckyJoZUTixXkEnoSk2Mzrl4F3p1wI5uVuHUW6f49 OA5yFOOz1QYdSHQq8YKwJ5L0i8UxvO4lCm8zc2dCdq9xNuwuVkNcjmX8fIBXTtgaAfRJSCC/ghsx /Lieo5xIkuIC08hLuUbioqVDFMENrksg08E7XKS/tXRDFwMebm7n/Em3jcn/HcPjpXQ8NQb+hvKP NHwASQ++9tuXmXZMv6X0O/MTtxv+OF7+CAofVN8GRmkaA0SSBJpSBCzbdwD+BJ8yySpaJEfKeZ9J 9q1I7ogH1cvkELTeUkbscibB3Smf8A6dQEN+yOCSTVxLheWMt7PidhTI3t1sDFwCLQMNeVG1Vlh6 r5uOj/oV+zxQr+JB0lVbG7XKxY1b5lsQpENwyi3/nvrZRRCz/hMaJ6V9kmTodMcAhJajjEd3PYtm WJfGFTAqYllejHIhs08gREB2iRvdfMfHgktHeFdbGW1ED9PK76izDipzPvzknpP2kGW0G8rc2rFp agefETobzoNLqUQF91Zq2THSF7ImsG8o/C645+4Y1DCHbjZGjRG5h0/4jRfSQYPACnu8VhntAZTU yY/YJXoBMAOZ02+TJWpLnLL+1k7T8vG9fNqjGzAulp9HQLYYsod5IN58YDZ0jII1nMB/lvNbXP+Q RkO0EbihBCD38ydQfnln3VmGnKdxreBl3zoF+14fXzc0As6uZOpm30xc6j1BiLylUFYgMa8YIGQf POP/iuH4PkOs8ecwAS8v9/WOopwIssTwL2sfEv8iN53MRh0JFpX25fTJ2qIxIDLFgiTUuLdBT1Vg JD5BdB3ECktspvUtZtlEIuslnbzPRoL8kPeo++WeJ3ApII/tycsjVHHT1WczjousYIucnB8Mpp3J QMUMOAkmHqJx1y7VA9G/uuvZHowp79fOaD+MT5l/Oce6u8ZO8XNmzVrNxQCJPHYRPgKxZP/W0zZe tI0irBvQDKTaf/xohr+gIepcb29+5zQZeL2dQJTqPIRmutoyMVbajWPfptKOlyHEufdCRRG/teqy I+xFY//FrYmMZW82XeSeO/NVEfmFIKf1TEqCwLZhlQSXDv3m9SLW3HZ1eSdaO2gegud5sfIfEBsq jxGdI7Bggs8SPggTXEn8zDyTeU/W/F9+eVGFpRGiDeU5Qj5FFQwvvpKttyuIQJxNhok1pA9UfRw8 sk8KDM3EjzTBT1zzWMnLdW7PxqlfbxbFxEXZOBPCW24YMIeVQI+b/xczPJWk9giYb8eWNRF+pCKa BXtlBcKrQEzdSrw= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block ZKfhb/O/9O3VzkC+hly9Up//iISdFC8YLIu67vmyKlWgV1Pf8EzbRLDK3TSnns4WnXzXBxd6auT6 9kRLDkexZw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WNX0rESjuf4ZMUvrCSC442STmckkuzY2Klwe6dQiJgprXrNJ0TmsOIUVbjc3gtQ7JltCLHAWieTl JHgvpCg/08nNzlPvNWQe6G98wEobIfjdpn9K/mfVZxoWFB7gawr3PiJb1zpfctEy9K54h5WHIhE4 gXqgNeo3abi4A/4Xgso= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block DOffJFs0Jb92js0LY37MWmwF8XoLxqZXl8s3/t/XXbU24Iz/NQfN1cselANiDjz5Gqm27Mhhgbs6 hMJB0FopfxaPHG0vlYbJuKBda4zTe7HPvrzKloNyea4MmBFXq/NDNwGSCJHTlx7X8d9gThLFvnKi talWtBae3ueX8DTMTSGGQFmmX3lOAJY+qkgYLIY/LMwxqzu0HxmcyM27QmIYvmpaE4pQlK3e3gnW i5Ny6TsJxccVPDKz4evshrZvUeNF0rAU1sZ9MsqP1Q1Zs8ewF81KJtWifMbHw9ZY5N7WBFbO5ayb EsQDrzhzQwX2H8OCFlgml84eOCkkpaD4qA4teQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 04xaq6kclgwCilULQ5P2I+3QCSL6jg4h7DZx6pOJu6WqEQtFEz6X5LSPDQzySC6sJPks+240TbWr 3Wx3VUGXtRrf6BX8b2IEAlXrcxTzSkV0XcK9D6LhHcytJKbM/KPJRADFFg46Yzgic4cpu6njUZhI Bx2KebSgh81iqZ5YNuA= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ln38ZB6MqP3Rw5EV5/o985jWb+3b+f4xlalBLdtOi3ayMCsvWXNzL41f4TFJaIzsZkGl1OsSRm/6 vH/XzAmjIN21G80/uLwsz3zDvDYG13rGz7+ddwKWRQ0gpexUr1lviD2yUFaZzZaTYfUR/lKbdzNB oT7/qFq5aH8RNIIegATwhv9ZbDbeGavhyEGGDR5PEDZzyXb+ZXYvWkGnI841KV7JmsWK0sGPrCRI fJwvqoreG85m4uZsoSdZTNg0mx31LaJYp0r81mqVNHhUo4J8JOilF9PssM5gKsZoQqAg3e9/wgn6 7/wvS6whjyDN04qKJ9ST+IixdBQZ4cHz+BB+yg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 280736) `protect data_block 0wtkqiMjuv1uhsO001olhMN7bXgjJp9mkIXLO3CJJXP9/TU3wMWhIVFG1quPtW4Ah4/bVsUZakH+ 9nVKwtrcPAp/hNHZ+tzRb0SYylVi0ftP2Txzb9DyTkV/sjt7/Ue4zJOy9BjR0ecdD95t9NgAhk58 bWe35TDnenNpBSh4SU7cq+tEYrZw68w1bNQacAe3tt/6X/iY6DGZOdYdE7ZlBSVmiqF9bQyYqPHu gTqTgBnnlbdoGtRO4+Mn17DEeIkeFPEnVPdW1QawB5T5dwwb9M1E2DyCtgRosfZotlWVD38YGhS0 ypd485Haf8GtZa/zawdU2xQBBRq7L5627n4fwyFcV/bRBLdjmwkgydzmW0hwpUc/E80D4s6MLuLq QKjaKqhetz0jQ2ltjtDfaEtoK8pRzPuGsvRbge3kEad4ewsEQ2suPapY4JZhCH4JrXCY/RDroSb1 N79NYt+7M50wLrmcNxWjmyWU3TYQ84ceNw7dFQCd4dfP36XR5QWKs3kcmOqXN2N9sSakXmsY5JGd xvzUH+gwNOjj0QDDL/XfjTN9BY9mCvu5Mq+YpCnI0MQXaEjOEfJwviBrDZh1zkSL7m+GhRcVAER6 3vpKLChMUb36YwjqxJqjFwKgwBQBwrSRIVVivU2JGRVQGSyK54vpfoYD6W0zwKUiPFl8Swy4ZD1O GM/B/rsPHL9Ic/bTIPj5D/YbZ1FPQBMVyVy9xexyZ9LHLjDi3hcbJspNhtIdfNkLmNSkB/IvcHP0 kMdsPpPvvwDU79TFbbhJptBWAoCaqi+z/n+MXxSvUqQXlhKPt2VtlwiYKlB0+cKf6LkCFnhVKR67 dlyhZVhZtAR+2GKxkN2iGsxQSahnLmiDr0FZshvE1fQJoTMr1RW63/tIu1RPbnmh/bDTfzxodHLo 7DHzzhIeJSAKaLx1Os7LQFyfeSTVl4+VklQ7anY3dSZnbxuapGaJr9C//rD8/ddz1X+fZSbDsbMZ A89pug469w+1gsbA2o7T+4fc/HQxLvL5oBm6d0QmTk2tJu4txszSMWV2VZDWYd2RUsvLF+zUhaev 5IhI9yeLee4d4kTR8hfbegvpqr0HX7d9xRMClhDSrB4akaDy+c6QQbVxMxxOH6dIvscHOfj5Or90 rHkyztQ8nyztC1ZfTX1ieb+Ts/c/OXcR0fKGk/Unz1+bx6gr1ZPrKrQm9+uBGt4vOkhCLLZ3eo6L iAV6YE0qQxEO0nADG6fp5c8PIHAPG0VZZ88n6O7LoiHlxkWI1WEGNmdFO48hyyR9VVDmeeoHlxSt cJ7KOxMWRi6HB2pGqpETPqzRI0tgmTOMEx1Fw2HYEMNA2sRxdNkLHQo3crCQAhnZUPLKuJjq2fqm hgtEAvY3gX3WigYG8Bt7rkU8nRuxDZyHweXDQ/RiTBtKyWoQUdvq5vxqFAtTfQaCGakUlDVZt2oM g1JVTaILHuMRTufjExj7lNNsp1iFUQZ73fjQqMfjxExVBnbrJgTix+XhLS0sLlEr/Vg9VLRqsXiz eeqfzpjS0B1d3yYRMW8Y4Qg2J02IPvrgpRmLtezgvl6vwAu06fYt9kmW8g+8w1nf0dhJMm6px7qX XqGnllMuLWWuLvihQGJ6h0yaOi/5N6SZgmADCbPHSXpqghVr50p+LVX3C2/hgATwbzDm33/0kLoY dyktvVQDf+04IPF2WvyO/OGOij+7PBqwBWQtH0pJ5Ng6RBDHqCnVLoZA9PLKROYWekDhSYY4xEOM qFsx2JT3uoB/4CS2pRMusC/xbbCu6+6ylIPYqr4pTgC0C+XO52pzm+sGyhPQQaJFAUUMHIBZGqUo 1vn+//pvvicE6ctcyzM5fxjFQFcavyRiSl3Q+WT5CXJlVmy4ae8t7e/nQqlQXQIbj8xsL8p/vNen mKKQYrOA5vm5NXriVGeq8SMz9e+mvETG9DZ2dHZ0xB2Rw+UbDuFS8HBwTWC6DAzvyssPr37Imq/r Sv4fpydAqcPj8MRad5pdsVr9ZtAP/xNTUWT1e6mGFIYDfDwvnyd9Xv1xfuI8o4nciO9Zpj7FF888 l0k2PMuU4ZC3HOUqeUNr//tFKrSW7paRutnwr5vFu98WRa9J0NDVINrIhV7qGTpOsTaW70kGBPlW giX2DUD8a7btKMH0i0igakEeUNXHyBzrI4WWbYpy0N1waJup6fYNYPxqTlzvT18PpPL9r83ZUNMM gigvGj58dXfHD95dACbmhgCt6vjM6/sP8RcbloZH5CcE+8Nb234qH5dqn43ktsCt283Mi6qBmjAv l8pKHjblVBjdDUd1dowXcaFwjwhtwH7D8mvEFy//AEAq4xcun0QLd981yNEux8j04H8HX/XkC6Nw 5obuXBxr/skOCiQgFcl8UvZ4s7OAfqcg2Z6JahRS77bi4wfNbgG0S+iBnZ8yqrcvGcAAZpSc7kPJ a65EyXg6L83AAzteIMlse5DKB76sZlLUDlaXKDF9fcVr3lWwhnXEKuHGnOJ6luPnZa9KjAg/MxHD sNoS/zMQ6fpAdsecenZyiDJFkX0D11/ECoIOfzHa03Di7hwjfhRaMmYaFsliZPsuteQ5VQO8oZFJ atW5LS/M7L24cO51WDnkMojHO8ShJDj/FfBktQNiULuZfG/3X1IYH1UTGkFEfdpynRa6FR8wFjKK WBFxK3PyWhP5zzlFQMImM7FvJaEhyN9bugGm80JCSPbOxnYYxscqj7FTxE6TWUUpuffdLYSK//Lz 7GzcOD1bFbJPGxr7VLNM/E/oU3z6J6y2izNHUzeK4uDs0LSLMQ/umEc2P8mxO6swVUJ/GILyA4N1 eNcJGrZeY1zDAtWMehP4MMvAwxcsbhZRxxg04yV71DxjFygL5kcie5w4K/mMfZ4pFsEOUXz3SuST 0FZ4owzAIRF+mxSQigcBTr0lhqB8omIrrLHuioWiTPlBkQ2iUcp8y7iDWT/7sjiat1a21ZcLlLCq FbbZbvJ/P6FoTHIlywmV28tfJ3anyiJKw2VUaDOB+UIvKrWHWXoukvgQj97mNdpb4pzkX84/Mo+9 v4QwCCW6D892Q3O/xzZELlLMsrDjTWa3U3c/nrPV/cEl70Xk3hfXmp53aNuLg6xiy8LXK9IUamIM a/qNtw4prpidlAhVrj3uAbelhuZYVnMmzB/2wIG/13fFNd22XEgxU67oXqoIb9icxqhVCTEhUJ3r dMVVNKPZhgsEvt7F3p15v1SIW6gkQk7dQBslzMe9D979O2K6AqUUBXk6yq6uK9OyqlMpq59xNkNG 7zhV+a4TXwCDlm30tg61YWewY7tdM0ShbMk2UeaKI/KkRCeFOXUERv0u0g1OvWrQi2vRfbmX6or5 TCUmQI9ksnhfJqoWoTD4HKoq8FkYAfX26zbX9GxgpTk24woU0O1iXyVOb1h93WkNg3xJAnJ6lG8U p6sD9UIjXBj9JECQqWaHLTBNo/BsZhI04rmTRWrN4MSGbvUiKdaQY0Po2/rWvf/HueERH11kw9ML b4oglitZxxUR5pLFAxxuAwKDIxDzWLE4+BwLxSnIo6PXAQAz/yYXVf+AyxE/gbIwdEDcs+/fa5WK kc8mMVEfVt3CMf9+wBU58GCtfUI4Axg/UXzAjlnunM71b0u2FOjSumID4d9QSym81lqmluZE8J8z ejlIgb1axStGjhnQtQmG/mak5c/hP1US5PVrH9nVrxy9ocQKXO5cLbXUyILFaHweoSfEMMV+TPR0 JmuZax0Nxj8yiM8hbvTSEgEGjJGaCxBCv9lXtA9KRJ8+HuOvdjPimUvET4fvC2GJOL3tr8TqK+Sn 3ZXuXiIF8qcThtzBYH1/laE+M+jmKqWGBzUAxdcqEAFf+hhOMY7fk7E7L/VfrBHkQe+TSGQKKNgH 5NQQJNjzErXF1uX7ExbUC6hqSm5+cxgBMHMplUv+xl9XY2rt+NhvFrfqZMk1UInfBKgt5v5RmBQV V1Ga4cgAD94wxjoGeToKfGLj+b9Xe1AlWrYjrsjeh8PfXIrQaDyvbqK7ke82TTX53AxLJrVochUU LwPWfSvZCdN6ShjohfspIzMjTuok4Wy0S9BeQx356qChxU1sZGuQ+DAO6fecUjXuXRrPM2pj122y LLJP+dxlxA0yAgRUH4Q5mnj0tsinkCtzH2MCo+uqxRycZv2BRs68ClFWDTi3iSmZ8LyOGX6CDCDs IA6g2VO2C2Uv6FxsGrAy+uyiajnQcp+eH/RSly2NPtc/iHAQqjiRpwAX9NslRIrgIc336U5G+kci SwZHnVoGxgFP9+7am7yZJ5B8Y1uAeQMrSyZOlVSY5iHMHWGIHpYo80hzI9fpTK4rlLf5IZziWBqM V/mERx4/WBTgJuoUX7YcZ4LSOxYlNCgezla82bRZ9kIe5ebh1s9DV/GfNbQ7u4hL5hvC8MLVZ89Y kkjw/28B2+veeYAQElNRx1ka08PA8ZjgKrPecFJGFyNwltMXNztPK5+tepHbSNF+T2OS4aeJilc8 9Y4CyITuRzvqGp8CxuAZSjfSq8Kp5Esz9RJwsziO/0bkdaWemoWnkbYfCh0/GlmQP3l6tREna0hb 3t1XnLwRoPYEfRGKiD73hez8CFUMpeI9BiF4HlknGNlhqLRbPteRPKD7J4u4rVBEgtaG/mAAhY2W HMOY4VB7u8qHmRtS4ZNqJVOcNbx5evtKkDuqhv2xBhPw3Te6Md9PCh2zfyg0jO5TbG+eibbZLBvL UQFP8vz6yZYg4aFfw1aBRRq3gtMDrlUjRgXJ6weygioZnPpEE01xi9O8xledd5DhTAW6dhlXQLsY X0NDL19c0MkfJYF2IaywGfr4ctYcuYMqhO+B0ZLcFz6d1B0RcjJEjxZIHYETMUbgH2n7L0YOWZeg oLplevntrD7qDfDC91zXmrymJhkxBSzgti538kkoyvgNt8Ner1MhaS5ab3suWAgrSPsv5ckn9tLK Mt/SbekadIixSMVWTDhAPBW1hFnnkcp8DXSgxD4tJmXFpeAFZmgqieBqMVw9YQSi4bNj9jB6dkv1 eDT6yLavtJsR4uSDpYRX1P3GMolxJNGKbaW8lD67tps9eNoOOHNDzUMN4PO08ETJDbbeZfWobLvb RaGgGGvXBn/rCJ8Dpy8nGME1JIYfa91+IAC3ipGrottWb6HK12988WqlvuKABNL3grpU889i9ku4 I+54K8Gg/SeQQVGcJZDrFr7XatMZbXKOj0IOblDYL6aL5nmdSsVnHqGDgZ2cPViRJbbfib4f5Br/ Zzv71md3qswPusROPiQfYTAejUE5/q4PtoGNpt7jWWFs6bkwSfjk5E/JfI7nvNKMJphJoKMRu5aB DS76a+wXeLRj23F4Nbiu+pYFcdemUZ8WMnVCnX1gDjl6TNSldbcLaz4LaQde5Nrp1Efnrp8EuIdQ pVvjAtRnzFj4rzZLKJ4rrMV0h7PkIjHf18K4Vh7puXGc6OFAi2sH41Kx0QesswwgbqAyIvCERv/K 6n0GbLIl1hrqk9/ltLf9CknNHaYodov6mGML8JSZku/YcCy6YIXO30R8YtOXIEp528+b9AxO7Hpy 7kU+8/JJ6jWtd5uqu2deGCjvkMAlY+PM8rZwYZuntgb0feQBrnx4c8M5wJL2pQ9JoloAHP86/bWo nJilP0Noky7014Gz2ugihln+V2f+y480axjmDB1LoD0mjRr9i0WbseLCIBUecdIueELhPGvvdYz+ Id8BTtmfXbq51u2RkazOO3rS+OR9hqd2lhtMdQsv/yZwNgLCfSHkVFP1WnPF+kLosut+5GL2q1SI reGlOd9FpJJTtTgaCN49pD8yMm+fvjN6uehaxsC6OjEFImhfBIYrCAOQJokGY6BK7DD87YSOUrcN 8xTOMi22zWQRTvwG32J3XGWTpjOemlnuTfdY8iJfvQRNVhIwew7Pj4wbxajK2dwYC6QTiVFHrLl3 tVfU/qe0TFPsmbPf9Xiyvuk8UxhcKmWCD6979XE/upDvdJHk84bfdMXCwXSUB6TlSRj+xz8zPXE+ B3E29aw/+xooBhaJQZoIJ/47E3FrcF5x71EH4NWatelTQdkaK/Ambm9YtEtxpHKSPD6kigcIeMxI AEz89y4a4ZYXA4FvEj41DxIPD/OSK9E8RRDZVJ+xrClAS8YeRX94ufdSGATs3nivPMi5abmog1+S 5AB7yyjv56Vygu+DYteU/9iU/kGwmTfuG+c91V+lWNCz0XF56HU1ME8evgE785tL3lUYplGXTcIi e5QQ9WaSKwm9qkSU5UzzqVcZrtGjqFgEnZN9iT704nyTbABOSO0BOuCku1131SaUyPGYwVPA8nsl HhQg1ofbWsbL41mQXG+TyE2u2pF5T0Z4fhR1p92PVQWFlhfKMTUqXZ6oj61kJgWaWrHlhAxIvo9e lBrGy0b7ZTwJHSe3/RiNMJ+RmYGRZaFLk2zdK0pCfqkGpUDWXiNNCrCjexU0WpLy0w94kdITVazU 7nHP70WFhUVdziMj+vU1LeY4LDg1X2EYRNpPAjh6Wy7EsBBMX0LUGJDssStAka5CYD0ud32/ssAK MF2fe6s7NpiYP7fEGxHEOCy+OVsUWE1vrm7Rg4+hX+KmHVYu25vqkf8iJjOzf7UnmYbAfZDm0ejM wP5eyxG/5Tw/HleQZij4jEcejM0jI4WDIT0AzZK4LJ1Oqir0tngzgi3s160GvooJd0kDXO1LK3kd Gns7yTILm+TiMX0sbKMat1Dx2QuKCaxmTNCzXyatbHDStT+CK7fJu+ovD35wgXu7K+nhtw//Paz6 ueo91qTlSTRL1UV8ULEVAzNq2AHVaezBWVNzWfAIs1C4bucDfg+5y0OTjbQTzNDalEyl+jxgCYBi gTi78kxUgmuOu/t3Yqiyn5IUExJ9D3eh5iQ8N/Ci0f1ECeaenDVV4wbNYmQ5xdkZlF3/PLR37+V2 gtMuDJcQQMUKvLWAYBJLb2waUMMZmwMJxFjavgnQpHlMYSktBwX5dofg6rzHda1A3An4T/DD/1vP e9Q5menJguld5MBhOFVxWOweUnay2L3hDdLD/PEP4xpnyt96OLLxTLnThn6fCi9NKmO5UHaug4Lv X5yE4r1VE6KzGv17ujpjkyNfL/G8Orivw8kUfOogF2eU0NWASpQZ8Bhf8P3jcHJLLnSDHE4QlqGM sXeyZ3xy7VPZIoHBnr5CE/AXoy4rqQHg0xPdg6/KXCTkvTche9mEdG9mdJ14/ibRdRTTufU2hKRF LhMPp0lrMF+tWaKK/sHe8JauxSo0AoCK9FcaNSn0F4X3uTSwIhX2lJMzdXRLXFWAcjCWLjAlOF1i yTCkt87usMePyY2Je1ZBW18yi5F+yfneObEW+8RQ4BnnzTkT4H8XWWCU9pAqZDZUiMMX1f2TdQmu hnMZgKOFrw2LwutOBlsZxqEJrfIRyFP1OqZSdic/LiMOu5k8s1DcohExXChuVmci5D6UcXp3r0CP Ert2FFi9Z94xXnQi00qC1K9dDsLCWi4p65Gc8Gy5Y4gJnjYlvtbI0R53Bvuq9M68ptXks5kOWKmf qeUthzHup7dalgenH8IiMnNC8fQNcUaXk1dUiI8Kg5lApSyTIHPELZDxtw6YwIcqJJiluFXKouOe WvZg3qt02hb3Y524VXT+WxiDaykAeuuYpoCIgXyGfms6E6vlbdcRUcCRYZE/752h7LtQ7ajrH/MP HSPyJZtCjOqAJzvbAahcj7LO2aHBYfE1cP1vUG6Bl/T5YlzFBJrHEXAtyo+uEgGncZhPBDO9IZWm bL52wFGyQMQ2u16WFdRnixHCg4G7tmdUnzOvnoYbDwgeCUpkWkKfNtTKLVn7JqCSTAelve+NQmrV 1v8/ccTFWVHdnDJWLXcqfh9P576aNZOaINlN1hXNnlqpx84U5KQh5fXmlTnSeCdIDrxWOCEcMto1 5GiVl+KO7PpNfHRHqX1p3LPhkH4ILUe9yVfLhNTOpuTZTiDm1VKXKLMJwt5PP4Dvm6IL3hocevaa mE3CDhseIFQEERwfkzWaZe0YBAsB6hCDhjZBbs5tnHdMEVhCQ7MYFvAPD+AhGjtSVhFdKFT650lj H0De7DoDC40b+qwdZv2l4uk9WyhKO7Wbjsy7x7VJBAJmCbT6wGwH9hjIAmmxrYNpYtQreSqgY2en OGolShTKaJj2BdG5tl8UlCJ7RqqhoXqpaqvDZjNpqjswIz76wptAEWzvflBXKiV+CSc3QLU9hSGT ZyxRAhMIW/8KUcN1jY9k7OJjyjBQxthUEatDZ9UvcQ4UnZ9tsURQ/VdBlUJgwgNpP4NO4cY9vZPF ZUOlFo83Q6LJC6p+ZAmAkJahjm2dHRWPDuvRmjAlk3w3AaWa+VjZ8Xs4kR/zWNydpPtx61HJvdy9 yPOMFaNBYbkX92KKKdkrIOh9NZggwA4PF5HEm47MLFBnIlAqS/dtACxO6uDclNogjXjq2kxQkj/f EbvoiWZ/NW48IZyHr01Fc+PmMviN4kZVrPUVvnujyYQJf/B/rRwEX3KmfpQ9gohKx9CZ5w5rJ46n qbWNox4vf8gkJ1/XrjVaZZYtWIamCzJIJmCoEjrK/ZCuua+lAo9BB8jZls13aV0BXaZMbWMCdNPS MkzYBH1XzjOpxbfTU6hlKrjTM9RG57aHAqBDttWHw1C+QF3dgC1fugWvVxeNV9slF4ed5Ku9YrYW gInajy1e3jnlZ0IFEqsKE+L3mk37k3+zXktkYcicsJ29aVZ2d4WfTCMI6/v6jfkuiWYZ7gkKqj/V WKTUGaYpKjVzaZ2l1Gm+hsl/+1Hu0pbxMbz6f9BZaNU4Cdur9uhPHfh1bS1bCVNW8v36qshGyDRW XpcRWdray/8MFIqQeYuiqEzMZoOOAYGtzTQ4j7mV9s3I0llILOcgn79D5JEKsV1BNTXk5xVOjQlQ fdgAmOYm5U4ymwxuSJ+/sjPZnuzcJ4bsZVKzUYsjeipDogRAWQMxKIe0K/H2ojK4cmZL2l0SmHo8 1opgvi6bO51vlYQWgMF6GjwdsL+xjTLYrme2SKRatFKE93PlpOcQYiQ+mQn+N5fErVysee+5uEzA Y1YsBROsabh5cNT0xfrk3zykbsHzAh/tV5QKe20YdbmLMBODPPTEdsuRdB72bRBVt3bKzDLFaKyM tQK4eZuasLs88W/07LRhxHtfCEwAkvKYrUt5AxkkGkbnNEOSN3oQ7Z9LvBKg/C3NEgc12a2WnAxz z0vkSQl+Mp5IRk1DSQ4UQHCD5lJZSw2BP08BT1OfKzAdkkKJKujMw1O76+cUx+oWq//uXOBwQGEs jID9VDQKBxenIRvR3r0gsPTqhCNj1BSmtPtl9Ew/a7c9t40+PdeOVJaOwC6uwhn0vMfYE2zAafeI 4GUEco+aTvmJiqGx1chZCkMeDKzWyTIIkHsACfUhYYA9suQC7LRf0BgRltAT2uSxiJSzb4eOlBws +kBRPuK0QF92Drqy5LA/YeW6XcoJh1N6DcFa4/tNv1eqLKbUj/M2NNP1a0/nhCf6wohlYFvUr2WD zWnwHgGmoEfpm5hmdfZZJfFlJFxPrRQChRxiN6B3OT+BXaeBaqvhAgajHyRtW9GkGd7KyIO3YxD4 ggqbW76avnqawqldAS3Z4U3D2cMK4PmJXLPPXksMt+cnW4IUW1uFSc9b730w28lUJyJ+n5cN8Ik1 b+u/OeBucWGATCEhxpjfV50P3BW/9xvvS2WjRiW0PdZlW1XItK1a2+Gcr7fYSYaJaDkKgQf5hOm7 ZTKduVZBi3GrfMsdmFvSyo6PrQfXrXEbkH0taIP7u94z6XavU2e7thPxy2FJpqM7LCWWeBPlWOrT Wr8rQhTof8f1WC3/PQipJGUH0uH7jrVrMC1mF8m0WggjbZlMfcvj9cFTRHgFTsaFBBjUJHZpy8Pw PnnX43lxYCltHBuCj6zCS4FbyUoHgq9hMcXtrcuS/tfP+szaeXtsEY51lss/R2Zz0uhC+kj//3Jv AxTorKbzVp/JeOmUj8HU4b+kkZw+qqE7uGy0YQDIFCJ1B9A0ZgqnclILd/Pcg/EYc26joaDW36hE JoNb1+v5JsVb9UmseXRB4egxk1OIINJyH59D+6cP4LfCkailHxzkFlNBvIlRnRL7ll5kNqrli7mC A1jm/UZJb/HOUDcHtW/gcMqCIELo0QqDsLGEh8XLdyu/xTSGRDcAyckBQtjb348ZvWNpayi/YCKZ 3hliB32of3t+nqFNx03UymNs5SsOBQWcB0mMSHbvafWsY3Zrd659oJo2maDB/rlIdGEPmLhK1TPu WdRbO+Px33nlZURyRFxf4lZevmG/o3jToHH86mN3E5G1YDGDCai3pe71nI8VIM6KKzdPLuLJ1EMc sBYEjTfRMbCWMal9UDia6A1wsEdxERcf88nid/fWYMo1YTrGXjIgEH/626NJefY6DiCptFMuj2fS poV0jB6oVDV7Mikt+x0uL9pcutt6LDVdJmmoJRBbQoo8Ew/vtBQ89G15qY74TXAaL2Z0AwBo5X/d SN8Qd8L+9Ow5wc1eHp072Ajsc1yK/ATOilJAZvFpJtXZczyHd6C2ddi6yd+BNfwQ66eywjb4tRUT j3Z9YBhbV7O4J4vUJWTx9AS7fVcZytd4EOdkn1iQ9nkQVhSp8jlrFtbn8j/oOUhcxbwPaVGwqNCn B1/guI7F9emuo65yuRUgx/uXbe0lDp4XiCHAWve9VF/Z6mb+tQawYJ3lo5EBoCEoVCPHnisMY5ma BMqz106paBO0/9fvwwHaekbTvMSwOr+o10Pauj1uBJftoAY/fLDiKFj+lBzbdHWevXPLJr+o/nOB SxLJ7o/mKTCL6YZ8My75Ei5acGsVel04DVX2TunqpF9h1HGbdyMrJ8s4fltuEPktNFEfjZW+LcKc egfETVc78rWDU3SLsjpQ+TEs0JslG692uyq8ppi8FWuuQVhH4e9ibiei5KmZvBbuVWfQrSRTc9on BmkO/77gL6HPR/HqQLhrISqI0Z3IPmhjOAgNXi8cehyqqiRuqFLZJ7Urk8cDfFyHOAcydPtrZoGi Ti7P+DoorZ6k9xPNF+JtkgdHf7KK8BYngpmdXWexG/fyzu31i934CWwiNk64en/aXjssB2A6e8N9 5QeA92NLr/Mm4k8N/HBGNam4H25TJKvSiTUHHIdhb4N8PNwpUBSdGqezO1fd8A/2ZlYQfeSlX5jO dPlOFVjay1GsMoeDTfUicqZwffp2UiuybJOU3/8qFc71cP7PVMN+JdCxxNryWy1s6SbNO2iwcLXW HlDwIHWPQkPovQJgO4sTr+Ds8Nnl9OxHkL5lTIymzTwfLezwke1ICcPV6j3ej//IHUE5HT9S73JL PYmjMi9pMA3JicG7s7YvUTPfjkSPy/7q4GDuWkEdpnVgICX4e00jY2EuDOlfC3+NupLRGmkH63eN PdlM7Py6jhLRiAC7UHWnj9+sRZA/lklhQIqTks9icTuocVKPotEE/YjaQ5RoTz3iDvnnRiAOemvJ AepP0PEKx5W49CMpEstG97dGMixqX8Nr30tGwp89TLKmW1/pbs223Qngs5x3ydp7rBx6alLWJ2TA cFD56WWcfcl0eGPB3YFons1wxLQ18wp1fZMvo6fan4H8vIQBZdshxa6xWOmUscwvekxQ3NWbSE1c 5eN/fKx+0DIVLjkxcZn1SXb/VyOdWYT6cd0csjcwPEtpePfZnwWMigd7kw/JUYcGXNyr17Qqvo6i P5EkNaQNmZANDlnP1NnZCUHMq0e7r2Av93DMvPCO5A6hgV0AFgGi0mOa9Q0QmST1TY28GpK+TiDt Wm/EVAxrzw4hIeLZKnOW/5pgDylt9SRYc9eaWIN8zBNkMfKa122pt8l+qoRMAlzDl8cR2TmaR/qn afamLTAY2ynYGqmrFBsDRRPee/EE5Zl81ZGU/UaNeRoksIpq5o8QzqBx+nmtOvEJY9ZDXUbtR6ez 5Fas+TSAs7xfOZViahUgny8VePSIX0EV5VHu3PJzhosNNL9db/l8OF+FxKETn24ImeuOxf6W3Aup LmhjNZclKC9HSoCAgkxVm9wjROUOAb0v3HSur6sO7LIzJWq2M54nVMQf7s7wpW78m3WgEcPv7rkM meqNXDTj3CHzKqTsJgwkQnlmPGaahWrGC6jQLf073d7Ur4gh5bmabTabLnkneKvZZP1aeycid5Xy EeHFnp49J/+7utRkK1R8Uaf/c1/R0vUn+VR8VbwtLL4Dv2ldCmKMhEyqcm2JkCMO3Md1+oYNzq7P knYnhHAz1k/L1Z0IBKI3vkSNsFZts8bPpxZxom153xf1VSk5Rimk8n8hr+YhAwrvJ6ddCFw2TfwG dKjl917nbFSXurV2az93LkJWWClTo6Zp673nR8ppiG0wN0ffy9pi4i5nC8sSvaHbD8oE65PooXYM xKpnjzTR4IAlAyEbvldIkyOBGoPPjy5h0BhgeAdSj0QMZYv+BFQHOy52QhTkQH73XvweSHK7+LJl wT6gQ52UJ/mBUA9q6OiHczpvZdNUBIu7+K3bd3DjZmr5b23NLhmf1ZdVy5SgXeY2yC64yDX81gXQ JpIQBYpNEXivnEOJ8IbTIyi5nKq1qTyYFahcHc6wMY66P1xpunKier3AdeTuOf0AdoPyc8DhBh+K f8BptXVXLbl5hRZ+gM0xCz0KdFHD81XgwprPGPU8G6SpO7k8qrppEWR01v92IPPX2b1BWFWmVzAx Eac7Sf4AEw8wi7UO+Fo69OrfK34Y+TV58zKtBJHYi3IDyNxAcEmNxw1b6OPn+XiDL/VC/2eFGVi1 sKoRbkP82WPLaoi9rZ9DnbTQLr9wW9boTigmsOBN4Pmb4JgfGcOXClfD94RDogf8FrMS83zMpwFD Z4niReor45r3Bu3RvDxrlzwoOaMykxI3wmvfOUCt4kTLEDrMA+hLz4GRxU585A7ufnEGjWmubm67 1HDDqOHEpYUuuUIiai9SynAb5nVv6Jr6N0LJs1hSVciiDVuSYC6W8n44Qr9tTCv0RGoNo0umHlVw CVJi1AnkX4fBZ/rcz1rYEdg04JJbRBBao/WihNtQp9e87koYZmjM+Sm55op1HNYRRaCRjx20Hr+k 862k1qqSn1jihgWbQYZV/G3rwNTceXByo8CiYgTCXObD7iOqxFJ/+IlOkfiC3mQGML3vJWYuHney qj078XoWUCPkEEhm7OTeqfGpdiw7kNS9h/xk6m3ACan5+4Pv4MIcer3LGOZm0IMQXPtE193dbR66 VOQAa1AF95gw/ZplRyg3i9VnOabsmQjoHwIvlT3eCUMBHiimS3LnMaRQGUSBLaXmUXlUlthGagfN C7RW2Yj1GDPEEaxm1sVOU/Gwvsn5uK0288gWhBlNwt3jkw8PogMN7Y6y5oahkX3g6SKk9yjlFVAi PQkcWz4qWXZIOIQSrXVwYHfGY0+VGCfuysy7F+ixP4DZSjWVfCDKoard/s+1lRBrfqmkb8M/scJ2 D+SZY3LRTOW9MqPn475SxOV93h14qTROkt66uLd3LdolHKYS2wz/oSSOL//BV7HH9GhF32pZ4H2L O7EBP82dcNexNouI/txNKgJe0LxZr5IL+VTn8asSC9HQuMB6vpwUat6GvhxzC94p2ZshSI0NX30G KDOGrkGMW3M01AIh0SfHB9I5rTJ5OM04gAGVMVxcDmXcUpdiUXW7bZCGBNlyH+mpY+heyIJIJeaz +5Vp9jURJlwcFMz7uOvWL8EVg/iV4M6UqNULy7LtPwbs/7WIUco46FJJeIQNQ/gjUmYTD+WEzNaO rc/0i6jzlHu9zlk29tQ1mhDrBuJ9H60dx7o4EZxHcNByYdruRGSHTV7SxfQfFRyHDFvn80o2a20s wvucmdVmcg5HhGNGgCl+KpEkuCCStV7QUdlnvdd7NXxoTG/J/edGZmAa9ROHAl7FbMe0W5E7q+kd /Py+HgrkO2/7akXA0GVnVZBzv6On5vQpSV3rPqkDeay39sKcWXWTTJN2bgPpQvvukkvvYDS4Mrh7 D9LUuxCoSGftudwnsH61BjI1EdZP5GpbWQHAQEGRqZQv51w5SyeR9vENaT8fo0H4x4vrm+zjeWgJ 0XzEa3LNYDMWRABoGxj5p5mRNQpYimLjAcFwb/zNkzeRhsB/Q3w2PfcAKips80ez/QmEp0FPZzIr NBHi08GHmBQkGSsmdKttqzeABRAIESkel2UKkyd4y5hzJMfd5cBUyWXZtexXrVwPlDm/D8t32Fd1 YWJvuNLMFgGrH3E9el6gJ19nK8lIwYYRQFcCKB3Xp+AIAwxK7lmplUDrYDpRicAqu8Oz617a3R2a uCQjx7l07fPrVIKxn3i9vAnSww0hpMOyJaEhKXnI6vg6tlBj3ZWnmilw1qMQJfTHptjeeGFZcoLr jN0Sxfg8BdEKdsBLskUWC/4k5qflT4028SvWT8Vy5ihFn4Um4xN5ME818NsRaZmAB0UJXPcai0OS 666nuQcMSymOf5L/ivnGL5L+ahpkhO89KQMp9p3QRFFrQ8992Bs1d1JiHNnXdpbtZFWrHgp+TX33 W64FMPNOzaFdGAaVOUazBypUQ5z0p9ekvrmgAUAOkFZWTPYCJDmcjOvYUOfnDoCSf0iIuWqzTgjo XCfPcHgpiBs98AR9L7YbI2gCqM+Gos5DNlf58+PVGNx+t4by+mx41KwtI8UwpQ2quzxmdCMSN1hJ UBEbtmiu35vrI2nHv3L38Ub0UzAJbUTAuVH1Vz5flqK3lY0ZNyWT6CPZi2DjvvqcPUIdAWrXaZVz j3yfqfTmfSL1PLLWJ7enP27G3Z81nrD5xcG9hNtyXKY0UpSDlv7a1+hduQ47X8YwvUOu1rLCF02A +Gct6oBa8ZeeZNQ48BU9FZGmxrzb51t+XDniQJHspu6W07USCDDSCZqqoHfKDI91SkMislrg5R28 hSNqPtLysXhG6qyoX2BmpyyCMCgy9zBjmXLFduRIKaJPEqgWxSO9MfO49r+K4cNsRGKTRx1U/doP 9CFnUZmoNcEN3JtcpGvy13+vJ98yjJ/fcGetYhmKDQ4qx+B30TDdp9HRu7QE3lclCVTQcXjTolI6 42rfEYt2ipbhbJmWTU9Qf9qNk9aJRB+KaTUbdRngZ7qHkEp4xecthWtvj2mE26CfjO3bMZldVJJf jEV+yuoLjDwDdgnCUjaZKL1yLGKxD7SNrFIO7YsmPWlpkjntXGiMux9e5Aj9JTAHrkc9Pk/BLtSC /IiPHwj1znUhDlDVCFEOh3qOiK8auZn9rrz7/LKlc2TnmOP3J/LcPhRD41grZ9cTynLYmgg+3K9W j1L0YyIAAbO+yFQV7mLA1xnHheEGlp4COILxvuzloK9z5ofNkIg4rboF+t+kcgMvXiZrB3M3tvp/ qXgW6HkFhQFujl2AOJ8TD8Cd/wH2dqf1hOcTTE6giogpWEJ1nWh5+GQGj6/q36xrlGhmooMIwyMc A7Niv9/WLwdXf7RJopR5D2gn5N+pQRf+yyaH6ng8fAlrTq1CZ4fhwUzBsnyRA96PnRhKix+d/nHB su75iJj68L9tdctytkvsnW5Yi9Fk1QH1hWUwy9HNlZ8RBm9hpI/doIVa9zoy8WqB2Ydwzrgqs61U v9pEAkjBJD+ZXOwl9FmpcpC1pmsLWu9WNsowqF0hb029Ymes7qUj0g9LIdd4h64PknSyphCIX160 Q1LR45hYgtiDkDM7Eff/P3KB1wDvwEH1IsJPjJD5iGcKrzSwEne91x42DmWdyH1yWSe4eeQheG7t KUoHGjK18WxthmmTu1dB+ap/zNYxoHN1iSbLi4qCyc3FeQbRUXDy4KcuFzx+60u+Qe387Nd2wjjU keyDKgt9bVkrZjECHizgI/d5wweCWMCQCNI6j96KFtOjIjJeuIhpbztd7McnhFT6A3/PSthb7dAW UIs/fHMcnemJsSdUmTBZeXq5/DcoHfocb9v/eez6WiaHkJTC7dwbaPstF0Z5ljz/lRqEaoetw382 BcgldpJgoDQPevrGEdN1kJn4zBEta/CbMMT/sweii1WYIMBXjoZyUWTWIsB9tvOMLL5q5qGsb3m0 WjQoACckomU7ikX9ABJOGGtIdpiyiNAW69JeQCKAZu6JFhPP2F7FHHaxfqAlvHOEiv/ilBggk+c0 TOB1rQNmHc7K/yvKa2KHJZ+JtWoJzMlVO1wxtgCg8mEmqsaQeA5EydJEaR7eeQQaRnPhy/vjHA9T PLZCWW8qsHusvR/RDnHJ07FJf8sAdOfs8bSWBwXsU43YayAQG8tWtoLxwWCXqb2Ei3RHhnApcK+L bpc2wtvCZcx0mcxlsqVDg2FwdDSdfO8JqcjbX+yJfBKbMhWJU3q3jsc8HNViyhVIEY373bwxxbV2 QFV37OKx3UVBUk0NbaO2+5E1Z0EpQ5kvaFuQyvlkXzab07fUag2Ye9S0C7PmKQc3+O8KqgnbN0q9 +e7JdUXcHLUC6LbH6s5/PZY5aJ+uJfFCyugSVGoe51L5f5XfcE5qp0OmsmZyud9q79efsu37xMiC Rc0BB5ML7TdcZv/8rOnsb/xgXRS2Xa+Uw/4PGYVFGc01/Scm8rZCFaerW+zsmPOeiUWgQz/ZqfOd g1XAJ0OUSMGEfZhQRAfj6FYz5ceBhbcHthqE83m8+Ysd8vRoq0GJ8NXlz2VmmN1qidxOMMXkunhr qv7ZIC7JEd1zwoGEz32wj1Bos2bnGFAFkq4673W6idGsSQ0Y6jyYuPTOqrplGfPN1ZXQ1zA8/ljq 5b8DO1YxOfC6y3Uu8Wd+TEDIWG5Zlil6QgpOj/d1U2ycws+tN+dulGRZnW4JH91uyIOwPUZ1ZybG cuWAqYQj/RJMegi8jDzkkZsl0fWoYUrYtHI7QqWsPLJtQCoLyZLviTLbWaAh9AQUi0nGzCeEmlNF gnS6yO4h+jvTIuazSPZUgeedsb/8uNH8S1rsk2cORhg2Te28zprFrByLAlaD0JaCTYhD2rQfe083 pF7IzQeWTrfNZjHDEaE2z+xKOM5AVg0mfAGWX5U5sgEI64fBvVWOV1zYIGdGG0KadSzP9DSmFjwV MP43AKI0SSfPS9M0n0OwY5X7pcB0RcavcayX55lxDe0hquKOZ2prdxxlorW3qrY0nn2YX6wNLM0S yasFh6PRhKwHeKCGRQhKNQsmR7PjsOY0evRAxVB30R0hcV7BgKdlMIMZ8GUo0S/OEdwfwBhfTli4 EbGJn7GkSSHnEjtFE1bz/Aa8PmfV6AH5DQaVZWl1JiPuySbMk9Qp9xuk2M4CZB4t9fRaf7UarsaI yIQwg0fpKdnVsQe32rcgOgiU2X0Wv1BCXAMdYSr0J2I7Hyn0dgcXGjEXs0cm9P0s9ohmKV1bjf2H M2zTv5Ug2yqoUef8yjOdFnD1l718a6WG3AXTHvY3SItEgV9WAasauJDc/LLPbBqKyiCAJuCBjMpk MHpifQ0GsW/M+cPjXXDgMd3HVYAAJHYcRZsCj/Z3vIIoBF+ffGHShqrkrdcWT6fSbZvguS65rWu0 8uY3Y/5VNRsH25kFjarA/i76SqtC+CClRvIz4svRFLMxKCUqe7VFHXszWkHQ9xdEDb5XCKcnz0ac sWfkxxdgTnxKBC3qf8qIXEjEjw4lQgyUxflyYq8TlSHJMFhj/EpR1BFLWf79M/u/uR84ypxcJF4Z pUfuIXJCtcoXRoT8TR3ieuer2NmnkpuovvW1c9o8LBF76E0EUfPQqb0y3qXH1ULw9Tv5Pmzaug4b tpopapxGc8me3+KkQCf5AauYU7ew/8QPHCvkebLhKCX6yQCcBpNg5vm1A4KJMbruq7QlzytFlohm nZpPsLIG+XpnMaPw56phzu8IVHKQHNqLxWq3dwjX7ViF4HvAfQwTsvNXp4NoLDzhKSqxb1COfzWb EG0WrsEJTqrK0v+JO0SpyZITQ9ivC5+HJKYPAqMun0eEzgKf2zoJ/v4O87FvUbXM2/0O9lLMQrcL d/ais4D2+B7IOS/U6x+vSPePgLkn5A2goEmIWlXVU4JNnPTcHTWqIAZywcOLl2N1el0iAocg8tho qMEQGoyh57lhOwxbgGB0GATA0VXUr5Gd9RXM2UrPPazMnh9+Vgt7Z1ckaXmwKjKDjxM3r/jg/O6D QOKbPvz+TSNg6zGDV/fNnObFhhKDwV1cOuF44/hPoBBbnA11ZlIB4QtpNmV/X7/uYKQHcS4+UcpB LkejcVeLqfDxPOqvDK/AAPICpSmXxkutLAarnWf63sgpZIWCeorWF7lXtcB0tgWrSqmsnzMY3SaM IZS7kgz38sEnW3BewUXGWAtZt7mJX129aD/SV8QzghuEPa3VeFxRpMorDiz5Ym5NmIYe+zO4uf4P l5hJdB706/Pe2Yr7xMijJtKKfhD98JUR7v2I1U2bYM7JIUuKE2coUfYga77VLGlbl517fI+ugZ45 IxyWZ6fGKCW58QxIlgCn6rLN8jtGMZNEc/Y45y28YxTbF0GEF+DUGeZ0p98gCdErcWepfzDhy68b vH2eLEh/KFUCGVI17P6DrKTSpuliObF/ldN56fq607MhLOzu3NlZg11CnP7ADKTxDTHmbe2gxFqW X82X0iE43HJeOjctFWlkXpx5+gp8G8HdSSLp699PkHkw4oC3hGvj1qi9mLlo/uiaU5AfzTvsIH0J 54jIigiT8SbhxxPow9zWEpqGDiq1RjEVbnvhpjwDN5Ti8y9zNLOXTexzFmP6GpXRnjMRRze28Dnz lBue33R7TMMgmS9BFvjd5UHqBUX8g/UI9dmDE+XoUu22C0XW2vSp5CcdeWqTdXM/2ftu+gX70oZf zLw4dCi+mqRRdMcYJyZL0JlhTIsFGYwkFrIUrmmgexs/gbKfdphQvHJIsgkPkzacp7PycTxbW2tc a09v0mCHkX23hAwQXxMz4mlGQXZGIXJdSQ41byPZgbjNw/xCWxsWyIhL5Ps7btGnza0eT6dnT0Jh rUpp+vKLBABVa9OKNUdGPqWmXD4zlLP1QJleM74xObojLxOyZHQLrvrQ+91jBq9cBT2to4SlVvO3 4QRIfG0kvLRKzWFduFEKb3XU42XJ2CyEEMHDQC2ZmU0Znsd9Bey+76744JIukmeN1JMLVaGs7u/f Mqj3L+kkZZlQigcbNMKDyyff+huiYfED9VlpqSJVdmZV2qB9RtK+A2Hmazwpe4KllntWzrVA1Nnr AjDHtIh9fkMjsWVXbE/V4aXMZCdG0m4rSP/hboo/keTFDCDmXHFxu9eRkSj0W5zNaQECDcCSIMXX wDtT+CmIV8Y4VjOym6j63VYr1BLFIvfaSgKl7cNxC3O1xSgZB4X/pUYVLuLwyIHHOzP3X/zS/HYX 8F+/gdXpHlN4KNpg9oR8zYzRxXYRk0AAduaHEr6CV5g9BQi3+kizMA98EFyqwJ6290o8rzojbUcD zXd7GifIYHf4OI52zErYOLdFrqMRwhd7Z3bzXILhny4v0j35tCEKzcmiRVZBM/3WfCHKpZmfuItZ RxkCz3eShYuc+ggPjdIPC77vhX4gHGAZFM5I3ewpASXEK5dW62qWH0JIE+coc3iaDOHfWfBYcjMb cEiTVig+EdWwm1I7IJpqyXlAZv1T7yxSEGBIeE9k8fZ4le66aTyB30UwDs7EFrGxS1bYmeShjQvR rMkdgahXY3Q+T4MltrUGQaDwOLn89F3/1oq/abipp4j8hhHofTbg8pF0LLRrDX5mX1omBL6ApuoZ CDuFmz0zq7lm1XTjzm6QBEAimtMJl4vOh3fPw6iEVJaTLZQhKN34UDbPpQAjti3laAmf9lHOgjda 39ohgMXFzc637mHQr0s/wzOHsOUQxp6LhRgJZU3wUnndqFxp9hJ6rjhMtunsCiPRAAen5OvQ0xou iAItMFKfaunBpQ+8QbicM4LPiiTywxbaFrNin1J363O0FLEjYCkWd2kLFyrRLBIDIgWqzq1h5Ufh hLN3ZDpcyHFJyCqDCDELTmExtk9pV6RtREZfR2hsmrHWaqHtDmi6bLDu24zO/DrleVO9Um4XPy7B 9f75+qij1ucRqB31T1vl4T/UoQu/yCcBL1zO2emqrx78LtZ+ikkE+Y7aVWy/7cOLUL+TATEA24VX cRoSHNZFrQARL3psysCrADfQ8RXv9HJPh0Epuliwx4SBGXzkaxMWGJdrX7/qEARk3xfvAowAnCud 4YUF8LzLWPNEcJQ4TvXcTq06bcULWXAn3MuVPVHTmqcP7VbxzUyfYpHRPCiR+GXRYu031o5FIOl9 nplHflZlWeocMHTXlv/Ucl764SNc7q+TbdC+U72rTOUpwNN26cJNTXlrRl8D+QeSc5jrpb9yvOD0 0n3d5EoQKPnGZwcw4F6jUrYajmLn3PGg7h/Qt4Z8xZxD/8rcEOqMjqc4+7S39xR/fyB56N1fqlQ+ f10yGdSMMgAUVCITVRxgyYySwvZoQjldqAaTlf0eb01WR1FL24wFddffWUbfr/cS5w8MqDGnbJod wAdlAw0Qbfx3K7TUj5F9PxJ0AW9lkM2jDHhZDVJkQbQlzXiAYwfuGE5BCqeYZpdyBUmg0IKyzO3Z /IEKsPWGCUMs3tVKujX525pOVH2v81Eumse4YsS/GYb4o6KqtJyeqAcmEuCx2yPWmJQhlnO0oOQf 5Kk3jV1lWlHsW8tgqYluRvp/PJI4v6Gee7y1My7E4yLF9GJUMIGDpz+PGYslH+jzD5K6uLNwahlc b42WrmU/b2VRBk7VO/0+N+CDRz7Oshu7qHCJhOSnjudbvw75ULmHqSGb54ZAR/RlnVywksCT9Lmd vkfZhW7GLflA6TU4TMy446wum5h9xlV/JEWuFDtd5XYlhPeRAkgzOeqPr+5+HdPx+OUGN/X3ZFia U7G7FDlGoMyHl/dtsTJP84mWjnG/mKJLIAKiJ/pEiig+WdmurZcCfpHI1AxWqe90672KS0kjfASA MaAJEM2spdPGZAGaZkme7GS7kkpgiaXErzszyFejRI/AX5Da19bt5cMHEZTMwIOrPQwboe88YdDX yQHIddJAdP2/CNUvBpBitqlRduw6jdCSt3FUmUeEPTc1NDiNT8nlabEg8DV/rpJ29JfJBdpym+hi fczr4RZ/RdjicgZCkwL0nlENCbzbuG0AdC3t4wbqmLZ12l7e8MnOqiH6BIVLWzlSYgRncKoSuqQ5 80AFvA5XU0pcATbD2T8gzC/GB9Cnun3PceM7lEgO2oxcOxv3qzo7/X9kOYabJ4lvnNPiSZ/XhbPp mNXl2gNITD6d2vQ+vTve9UWRjH7RsqT+LFKNAWM+so2uwdktOITyf8o4Kjeeq3U9Dh/NTY9x26ZB aaUU1sJqPL9cq9JW1IcnQePSIATaUEyARzgbFvOcWCT0Tw4d8L0vqi80M7HOvsL0mURGLUgGWHjJ +ugtsfpEX5T4zx+KDstu6JziYU6ygX4hHEa7LTLkV30F5YqbSYWkJLNNCQ3g5FoL6jM6PrCI93oS MrOHE/p7r2n9KFjnyuINEUVp1MJNx0oUgI6jG/xvSLW+wLM3H4aGtMPB5wW2fU7gD8R76Xbl31pL SHuY/sXrquIK6YOypjnN7tOim5Hr/LooNOuuZIAtVqdtUd4CPOe7xzrMRwPNMS/XP4MFAG2jQ1WW deI6E7QMQWKa+U/nD0eH9Y+BI72VWtTZ/xXvFfcRATJTHeDmAS99cCgStQJ4PQBqb7KIoBHBQG/i UldOXVw8OJ5khRrqqalmZqIIYPO7nT+7oPHKwL2jACNp8ROvAQvDo2f53hiJ0zbL+nRczzSz10HM +X47Xu9pmU6Nn1nn5aVBZJY+bIZ8UcXcjyrlROFwVzxKFsiGWe8hqBqXt6hx8Gb3bwU5OOl5g4oU Sk9ek5DM7C6hQ9E7Akc1J8jpYVCa4ii2GvZfkqiFKVQNG+kTx3mG6eHWSw4DxvVm36RkMMG0SO0u 1Hv50MUcWaste4eeBqV4FeSajdmfaOrAlZKXqgb8DWK6ZcFNN6H0sEwOICX3abvwABVTbnxgiByq fL3sFK4JwbTqQAdWVd1yFLj9HTs33ySf5LXiPXkF5+9Kr/bSTfypWr4KWgEfzdDjPc+LbH7/VMHA gdwKe77U2Mkq37LQEES60GG6OOF4UD5OtAHWeEHsITke2DNxtU5oxicIwa+Hh1GYynjba9wMYoYe iCoWC6BmejdnS1AIRgctHd2c9QJnwFSLZnqY9b1DAR9zgYifymBQPgwWWzwclIej/H9CritJiwp9 Zz+pn3nH/lmwer4nXCttXlk+FOgUzmBcY23wUreg6PQHyjSyMku0IzpRw4ILbqGDvgajoKNcrT+Z FavWzH121TG8TuJfOGEcN6qVZnSKCPAfa6EQs8GGpCtvA64nPgu2lZetE02iF9+UhaqA/S8uTaXe zCs6RsQUGv+yncA34a6ePJs22icYCINxkHDcCDLx47vHcPh2YV+sS+9qAA54qwd/31PfPHvzZjr2 IMsByACOo5TtmfMLQEwlYjO1DMCFyben3GJwINTk6JYCV8uXxQMJFBA4p/x35oUJKk8VfXeyK80j NdUjtcgsD3MLzzjfsFJoO/T9XPrWbfJFCQZDAOOhSe5ojQssRKoj5faxxqd6ZjCwIOcHotkQcSKl 3l75cc2klD0OZT3gX1JQBo1aI9wEPxDo5uLzuEJohZG+EjdXrDQGR4j2NUL07oYdKTyWjL5k68jz lLsf/Tmfbf5y7pPf6I0QxoxgZp1tmTfvgD3PV9HX/HPZ3nyo4qXw1aayPRT4Z6+QGXw/n5aoLvG7 KSG+uCnm5hb/M+0FnwSi+IWV5abPVKbjEorEKiTFMcY5UN3ibjMMwht75EQ9oM/PEJrrdFvJSgfk d3yLEjjNU8XaGWvepVbwbNESxxHIySQOkDsWDl9AbSxRrb9cfd6pNd6scdQhvsT3vZTJ3bAZGLso uq7L05rVqjswic6NQ1aXprX6A5ui0aHuScYvbw3xUpvMr+XBVZjQXQ822dX85U8s7Eev9DuFq2tg MqfSBjRSGdcVgswun3qQNoVynKASKDngZf/W7jY81Ef17L/OOulxxded5XWmie0NZaNeoNQD4dy+ wNCh20mORJhsJrYisxtqBxRDtIdd8dnPsz2wnVP+FAXxWYryActi/O7KOcHl4ttTOkP3suhHgSJB 70kmDaMuq9odoqxf9MK/I1ZiI2H13/szQzQ54AsN5jccXfq1H/JBhcOUu8drbbgXKBaxMDua+Kau cFAaXViiN2W9kkCfnpB6EnZZ5ZhX/ksNWb8q0U8+jZ0ef5K3nJWO6XU0pFLWIJtVadSS15tVfTPu 4tthHUmiI3tSjqGaqypjDegNN4+BatT3vBZWW7qV8FA69LUGv7I4vJ1lMIrvwbi5BePdMPBj8dS9 dQf1Fr2TczhF3TgHpQRYup5gMN84b/ramt5/ylBOh3Qwf9I1335rZv3ZoyD42Vl7KzkbcH1+YbTO YmrNk2QCISm2qDXHUPxx+3bstbfMtnfLVeG09nNlHfp+pDVy+x8Q+Dqj5/0tI+w0s8zzHEnI/OJb bo4vZ1Sn8OSZzEQf+63AL5vVC6rvJhKFDcu2Uu2LAHyxd+2sT9BG6863RSfl8d3B2dMr6dK8GGM5 ZIgoM4lRAZcZ6CnsGIOkE7hYyPC7iHHe6ny3S/1c2CgyGK7kj9oEsFlD9IsFiYAdh+qz16cniV0O t5K6nCFa2Ik77t2JVHLGrj3WNz5W9PYmjnQjkToxOOcPkFnIZWayxenKS3e66+D3nI6e6w8USn4c 1T2n2z43b/HmWwefktYr/wDeWgjzbtm6IawTPgyYkSanPBYL02wmYL61ADNgm8c13gW5QPHJX5Ub 92ykU55v/Ldnb9cq3wjGl3lo/DB5gJAOdXwRmvIzGauqz6YkolQAKwffcqc1/kAJZmbuCoJ5Zh+i eOsjmdIzHHdsPRPtDoxKVFUe5It+tT421ZDZLsSscBFXP6zbKLaVm7PoRi2bjYtojqOJAdnuS089 w1awwkCUAnRWPt4+T/KBfuSLRAJNdHCSQFW3Efw7qKrqc9wWu+d6m2noE2p5bz64hYN79iB4dKrH mbvB/fnhl3IrzKzsEQf6+SMoQOF+nPVu0fO/b3oQtmY3/op9GM5Y6iUosJgmCONcCCQEtwYU3xgA c1LKGEqKlr5ox0PbbEciXK7rOYy4Qp52ksOcKckiwr5ORqEYjaeXSsRuN3aaxNSNow7zECXhl8zy ncDNttaQ3tRmn8Of9BcO5VSFOGUttPl/JGfxxoPKxEEq2Aw7w/OQOed66RP/wwlGGdvo+r+xtNc7 zlEsH2LjAk0VrUXH/7592gtmhLEj+VJARy8rTS3WlWgX6WFF1DcPN5FTP9Cr/xIw41f5fxnS1ARs 0E/zO1jHKqnKOB924ND6nBFo+evb9/3UJ5DWQ9uq6EFJT7svGT+2BBXkStX3FWZkt6vsrxuAM0tK 53b9NUBAQ7j/ZXBQaPfk+r2RseRUZ6ip5xDuiISp5i2UnuMAgdYlrvw/rsxBW227LohVH4z8IOMF KNp9Z5Ag6yuaO79ukg+TAipk+v469sph+PH6ZAGsjIxwWQjJm7LaH1oXPPIgJVIYArF+6MzoucFq m5dhr05np9DoN3ju5QLz4yvV3qIGSuo9PXiQww690SkBPu28/9Z/Q5DdUm0gkYsEJNsLRcf2b7ua quUWwSlL3OYxytgHkvMYKLywbjZQdmoQ4vaKp56b4OxMd64RnxgHtroyQU3x8eRCGv+02pm3z7e0 KgCmkx5jAIpWxi3M6ElETbKnGWmC/NoKU8H1nFrEK+oweBEVeN872LO4zSSvKGBX5V7Wh+ry1zlm khCTtV/noyUYgqg3sL/VcnopCkzVzfSRu6L2UCtM2GLODI7muVmZsTZ2qQ01CDUN7KmwQ+E9kUal inUPcK48lHI+KpvBDsQuALyF5Vd8YkPgYHoG1444ZQZlxaX1x89DVuicIP/xkmPfXzlkGBFLfrLW vKDroKdXVfGZZctkLo0q1IrI5Q6zf9eyEUhQquKcThcobHHDDSGMgMZ7Xd7B40y2D/XlUfeAFvcL uAjeVONsdi1Nsoq6pB0SoPBL/ITffEUyS4cVobOL003ngcOc8ODOn4jPaP7OiRb6/njLDuxOOOJ5 wyddbT8RW3w9VbZec48Xv9gtwQIvUbBAbT9GxLIoqsXy8IJzIr0hdT4i+18h644SX+QOkOGflZzW AjwIAqKHLnRekcKnQ89GJd5CQJd4Z6LF0gQHki9ykn6wxzHp0GFWGUEQKQk84yisxggsqjvLmiih wTq5cpBirBRIfPkVRqP+Q75lvYHAfqW1hIhHS0eRQAhG18IcRi8pCNJTacZVwGojKXuBbdMEd9VJ Pm+9zmaHrwA2L4pQEGKw8MpLNVUdIdw3PIywG6XBgBvHRb1zux/jsCfjffPU25d8dPoVRmR5siAY FG8Vdwgte0sKFh2CGr0rn6AKBUkBZ7E5R834o1SrAeI0jibk1dsQ26akhbXOBccniO1v+Gj2EHwy T8agFtETWF58dIEnxwVDngGCq/J5f8vWvYHlZO40Hy6NmfO4HL9mNIlwzEp5Sfnc2BTvdYUxUiTb GZIJ5z3CMStMAykkqkLQOjWshO23+fAIqW9Fm3dS5Gmh9ErP3BosoU1o8J0+sgZYuhe1c6pdJ/1g yRsh66oaw0pUhF9sKRKUOVDfSYSXZQXyET0L9TdPUmpRVMEFVJvvG9wudiSHLEL5zFtPLCvxi3VK uoELeaizA6UN6wH8OaGswNT+TdrISyKt/o1sJSUVpadTgzGwz6+vgwYnp4tPflD2eO+aUNHU2dih BieQgvxRWIkSvaLkEGrK5fIR8bzz0eeY74TLKxpGpcRqPlmW1LSUR7hduAREkaK44gmc5MGonYQC my1ZHdhPpqPvJGPsbOQBoBdKLVyAoIfotN3JRb7Kd9hZNQO1nbTA0KdpX8IkZNAh0ipKVP+TOSPz JpF8icyD9K/B/wIWSNMB1mHVQZYWF6wgASK+MWW/IlBZWmPE+kf1l7NyirUSMXINx0kAi25b/EPM NE3FerwWvWkgNkMYo5OabMHhGEQWCVzPjwsxARxeZVt595cFCZZNMnXYVy7BloYudAUWGfBF/P+M lHkwSTRyWd0kly/mc7Eo9LOuDDPgWa9H9iT5QQnirQgrWgpz0i++ZYz1WlAc1lDWPD1CPDp9mYie c+T7c4NaN/AYAGiFTYNGezUvc4EpX+TFNXkEVGas0QvuZ8sxOj+Kw984ABsqlIM55KRyvl8K5hb8 qswdlTrPngP/0IzxfBKIKkM9oqVoRAHuaQ/fNdyAnNGQYFofFf9RRnlTRLtFg1Gg81SnsxgLLDwu vUOZI0QTthpTQm/e+cERI2GzZxtJ0ZmklVJLLpMok5fzXFxB8KMv69IJCMFIiQHQGY2U6xb1Ubx8 bYjoOEBWzzhalaDBc7PgvdrAigKOBCF9aWIi6GBTME2g9pBaQ5pJ0tCVueDShVQWXy+v2iPn8Nd9 p3CqXIiPL2c/GUTLRxCKakKJ0M87SJHn/2Y2LbdyBtT3rlBTT1vu3DcQoEO9NNUUyTFEFN+By5sW 9+siIeaEinUXWuLRau0SzdmwxidnjXy+ayvsd6ZLcSNSBcYI8IMGTbZzqXKsC9R1oJPOCthXRyTT ikqJGYeuYOkuodsnap8LWPOnJW88lLWMZPVphMJ8t+IVqKzlO9SpM6TOJg1v+9cnVWl2q/M0l7tp Cq7OQvM8f6Uh3UQFWn6IY1OUT+jJl/FqpF5IWiLiPF2BwV+/l7NqVTS5PepXaIZKcWzqj+bSb6nr cIAzV05TkPMQLzoOUf25j4WwnBgk+Z06VpTPWXUB7n/8WzS7kPiw5wbQEGMPP0zNXi90IRsl3CWM Ci6UzQeorp302THruM/Hucq7OpWEz0ebm0Wql6nxyKUDUPADcpaPlZBNoNNGuRnd2zKWPS2aLpyr QKPKw47UH9dE2PwJ1vPCuUdHpOLhkkLEQUmXafHYcBa2ZchwvIidv/HajrxGVa3/TDJxgWpZNCJ5 oq6PAHjkDN6ZezMsTKs3vzjy1vgDcLrOJcAYT9yfCa9UGHI5VBG7/4elhgFTMLBX7X0QVUp6B3I3 R/e+Qq/rw5665UzODJSEoEEAx6jV2H5AZ4wlv0VqG6898OPVOP7DC2RttxvFel1IkgHFHXPLLBfF xLTvwZGQ97PrTNryq00DkoqSSMG6iKAfPYYMBql6/i6pColaZn2yC5erYEO4SiGIJda59KNuY9FB TWrLSNttsS554Lv6q4mA6U/rxC7pPVFQHWrgRJAdCpmfSl/4YPJyPWYrbGKApxE5ZrJVEuYjDr5t Zql/UUVyo6ajahU3KaCfnusjf/nJRKYnW2OUnLrW1t3Dr0m0ZiWs26ZdG0LpTahwtBcUFPyTO7UK Fhsy8BKMwQwbpTXrmm7kHCyGJM2QjWadjpwpi4/JudfI8+NVHPZyATqrsxBXdIwn/yTbdyPGfYh5 eocDjU1PGeWdpS35kPrMOM57er3J83XENi1kvzcyT4gMnw6XCNCrbzMf5DGMoRDm3mNlIV82gQt5 hfqFcFb24uqLmtpgKIl55WMS7HXUz/cu2YVrX4xgFH96TLpmCqkdASnFHb1+4OytgLULLi74ar4g 99cuTQHwrFyvEvCmJVWziQ8RpWxCFf6ymxzyT/pLcnbuHXKyyNhKx/4Z1CfdlR5PrpShgJNq2uSD LIhTAwPLQ6cgoL4+6EMu2vRGRSX1i/gLxuMPBPBkFidFme3NCBhr851+b3ZNChcQeJ0kns0Ym6g7 EIfoFU5LNlkDVDIWMR+c45jrO76E31+t677ABztCNH3Vvu9fzHg13L4cR+GyMVEV3cAfgaYZ8kbz T9FBB22fGpcdmmtr7ZR3qd+RWsK+/DDwE6Py6bHpQv8X0Tv/hoUHQx44xr+27jq0PPVkLk2nGtcW pX8/zCP4ZiS3O1bUEvMEyMeEH2tXGrX/IH0adBK5RGWczv/SgnZ7z5tZhgX2qbKJoSY04rCUfYhb OtOJxgBSYqF0qn1SL1YGk4N1z4wETxsjTtaoSPxHn9Dfh3B4VvWu3y4/YoaDJm9KqJHUMrzKtfTf rNT3aMx05j0vd6p6eImdp6qOcauaRFwCb73dVkLbcUe2ligeg8w+/UBXU8v6fIF5pLi5CxyBU8wm 2Ir8fnQHCP6rItyYOlMDrkdemIHFAGpRnmeyOHxGuW+GnJ5eO3/E/12it2usR0RYJUCjg8DONhn0 lx0SnSNWynQWOpSzZ1k5gd8W4ly1uAdPHUJHmvbxcvXfqr91/IpZmifnXoFYigq+i3vmRcxqWGrZ NIqLfQiaw84PkhnvXO/CWWhYe+8e0hoNbfdVunDuNaUU2855qfFX5T8oyQ+LlOWXDv2Qu+q3uq6B FwPrkohMgi9O4pEW4imusKlhnxrFeiU2FsDKK4pRO1+r0gtsNilByjI9bM5/alBbx3oh2eq5N/u2 dIbQpSH5vwGlp7y6iAfTT/JX2WcGyVbyfkqLuwAjxejcurasQvzmSsv7c8ATY0KUpNa72mRFag4G epBtO07bdqpPFnM0eQaOineWwkEDlE4vNIlVLfAv7pxZUuK05CQw9uoaPj1T8cPratwFZnH51dM9 4LhPnkyQKbp6GsFeJz3nwejNkzvSfYSNUqxC1otoRdr/r2SuGW29b39FspAzvQ+TrNZH3+Yr8Hjd vj5vrtvmLS1yQw24RkjtskrW9OhBli5CKp9Dxw/gfm6bQueJs98QE1+kXSQ9ZDLOPT7Vj5R/8Q4T gUrL/Xij6ZL4eeR4scA1cOFJYKqTUNFiL4IXMg9Y5D5kk2IZhwfWLRBv+3MdHh9KhLqELcAgggAq sWX7gBPcCwKRYzOcPzsB5l+uHkptgRo19Xtj+LJJ86HmklxKpb/DLl3bO+VTnPw7dcnqelEYW0ii KSn7Il6Nc5DVOYCQqmueeEz0CEABgS2G/9e2UFckfG9JJgSvyHajYbLhqhrtC1Nlbq92HuN6x/9U oC4BEQ85ZV4GFwHjdUo77orCDViX46p3ECqww0VPthjk1ASWQLdgWDlBNYlFaNDW5mAn8+Tkn6YX hH79vHrEbUTaW8EG6S/DrVrlNPfs5sjNAAYqn6e//DubfocskpIGBElFLrHlHQncSttfe5kL477S MCQzMR33chRb2+T+897QEHjZ8BwUqlLwdJ1Wlw9/j0OJvC7Z3J56Tt0FkIflyYtq3cBN7ZZAE6Z3 xWCm1Qssk23VO4Vs6efA7dAcZJlpNwqgA6gyJjtc8CmOh0JvIhxf/tdOOsagTT6UtrQY2bWtv9fR 7NcfgJP/++Fx2fIISAQJ2cCOhTUJ4IYpYg/dr2WmT+e9tPjtpZ09+XCc5VCe8q/VwkaXPInsqF9H CBaqewZIo0kEbceSu44lPOLuJDdQ+p2xA2DOW6vVXyiqHx5W193jBoSu5fQxh8vfXEwhzCd/rp57 Xr13o9mlAGWwGx12oyCN0oGCMkQoHUR8g3D1uBav4WEPdsk3dgiim3u5cHCZx7697E9sUgChDX9G odqR6cf0uN5B1fnfxk3d9RHWKnPpFuFlgwoZq8LNnExnc80JJH/um0nCSqRwDaOQChNnOinqxfce Xc8+2hI7haElL6MB0vuI4GOlZt1Vj6RtSVZFYdBQzCbNIxwrPqZXr0BiLR83CfYN3GMY+i9zRlOu Mv4+f1Y8RMxEYz88IZBzKPKaqGaNrvPrEAuPoMfcjQHIQgHeZrsojmQiJo90NWSAWlRR6tTwzFm2 vthNpX1ra6MiVH7NH/n36M28coIK48g+kV0+5iLYZKI0GdEwYGTH5pD2LxFnOLAT9FOYD2jbV5DD HV0xQ5Xf8+cvPX04ehs5V6C6Ps4vod8VorYbYiwIctkpwtpHBLcqjuYAZ68nfVouQyMvWfQDdJpu Tvson1iFlUVZ/ok5iacHWM7LHFPTznuKB4TGGmO6sYaVrIJkOOiePGNQVyTCwUkEVAoyLlhZ7ej0 xGh62PJskOlhWjqThQ5SmbpUrhVYcmmgew1vqbo2WGXlhzPjoufMgQV3D/xYGES6f/s2PHdsIxsY zQ8+WxEvX1EYKaIyIllBE7TCA3FlSCb/wvghFQp9dhzNFYejIMBGvq6JxaICViS4NS71Ja1CiklX xuvNe2xMceH608T9uQNzkFzI/8BxW/lR82uUt1QLYjMmVSBvWhRrV+N8+5Buc5OOFh9oUnqs+qAa TF4kQgOGBixDyTHjINNjuWWLkVoP2PnpMovJgqB4YWdQpyYpMrzRxyFX7EMG0WTU40wLEk6EyuXe gXOwHaEHye7n01n7LMmppaKlSC/Gh4FsW39ynnTfS5FbogVdBUkVPrzx7+1jERFx3mON4aiRmujz SHQ8wfT5hKp2Me1LW5EqfeY7kdKRGQddzS16Pwq+d4PQcPUpEYMrJ5JiqMu1pzQUpPz7FvZ/CAQo OfgpichGaGEP/Ajjf/OyNwUYqNCWxp0e8Kx0cPBO042/YlTuySzlj9Cyu0NaG+hjEUrM6AVWLe9m B1ZSRaAM4hkXhQTPzmESUu6oGn3sFpAkKlY6SpO09JP9ZNOm3I3UgDuQRNh0yWNcbOOk7/RqW6f8 ss5igVXamDKPXTds0b07bgNxl+Z4314wrIOIdjfpfmz1VKix7d/8qeMkIMsxmuf3rx0wU8gzpJyb EvAt0BaShHBQ/WDTxG20vknsMkQ2BIj7vzoPHerv9ZaSvh82ia8sfLS5oxZ7FD6hpt0jQghBQrw1 rT/eCi00O/nHq+R34oiyh79AmPpv2zUbtiUvOX+xtmB5SXy8L53Roh0PScrAJfumiwPYw1mOS7cD 4KEeVJ2NCJc3798ctHBVn6c6bT0sxdV7f/cYSeUELmIzx6LoPxX8PQEwNpbEqtg6VOol9YlHxMcz rQ36ZPSkWx5/iOHwm+XGFvRCRCPX9P8ANaUu5MeQaQM2mseEfN+5ym8z4Kfmz+c5R5PK3wI2kB/I 7JGc7ZWXX+hBKQlvv5YzrJy8S/4t+3yNe+fioenMIooMHVu5YZXQO3QyYMfS6mu2cPlKrKK9BaJW /j+4nSmKNaHkW6VaLfQ8nY22qhZQblz6il3VwVn90jkH5apYaglnNcppmmsOmIYS+OziA3bucQjF 25brsPk5fnLxkwRq3552ZCqmPRvClxByq2HEKn0veWlz8XAgh3F1l2zA3yPsmRUWPaI6CCpPa78P bP+Pf3l9meoA0ok70dFz2nNzYYOZrQGkL6ovz6JTQGOTwunfZt8suX9qTUQ16Iz9o02F3UUK10cA iK6rSQ0fdfXpLQZ6W+FiHAbrSoVS4ob8R0sQaX6iaEqH5Xb+GnnuBv7yuQdqGDLHjY7k7D87aAqU l5XoH+X2bjD0V+mHNDPJ/yylQUBwBLsoJFgrGML9KO/aU0uicUL8f+4GRdIzYsL0gS4U/ReI4IAx szN7v5OfUafjwxqnzrbKH1jRhjGYsHTDiUUXW8CtofgmW0mO/0PI7fCHF6tj5trVJXiZE1/8au8R EuBc+93/zcWbLhajv+2KKNndEIgNhOa0egeMzWK+CcmKYedkdh+c+88/Qk7F7Nt8YT5vSvlbK9bd vj/L32RxH6w4UkN+mRUyv4/aVHyDbuig4kExulp95yq20IGK7WSt4MHlS4X5e25OqEAjc7UHK8Lv hENk2945dYjP0nSi5ZEh+pdsN/Vt+HRzBvcK6TodJt1QZ4A0XKw7WQ0pvE0wVco5lES6vxpTZtP7 nqTL/MGx6gjaX3SzwBP4Nl7800Qtpndjri0qMA7ipw8EG+g7YXGmltxAZTuPnGVekgZLebUApZzM Rmh290mZV9+U/kFo0AtJ4iPdj0/ijusuBTkcotaBKxnZ1vu3T79EU4Nnz85bIq/8CCYy4hEM4vWK PARed+eJ4zWEIuS6r2uee7oyqtCxg0Inczpvv8LTmbtyW9OSdUM6urTSU6sJLFJnGA9LT7B0D6m2 Kqt/MDh7Va/OH4TWSur+1CwlcPrwg7aIWaN7l6mU0eGV7AW3mSKI9JUQSXMbgKFtIlXtTTY6Ay4R 1zGhxQS20mIWxuNdWUBQa9XTpISwqisJO8/kqWeBj+5t7Pig3PeeqNLu8PpMQNr4wrXo3fYKk+qZ KiS+B9Z3UIBWFR2VnpAz9QQlHxspc1mbzctuz81rnymiFKDFscjWinsuDWmHfFg7cqLQE5b6ND1E 6KOF1ASp/AGM4deMJ+WwwtEIuzznR0svXdETONY0VSkwXbpyd49k7JMl4a4teYihojB28K+RtGcR b0OXWAXGh/eiHmsDnRzDT84xfereEgnv2KMcUPYUO+utKEokga1ReBd90nt3HZ4RN5yCZTijh9Cs dbhbn9rhBq7UQjN5Fzb8qLMYfNbzZP7TdYW25J+I9+UZStMxbrO5SngBw3gn/zrKB7wvETkK4x+F uvhdSkNh2Jpfagejem2z2WtQEAs02cuKYACx7m8mP7q+/7IB+Ighsvna1C1lbi27a0K51TMG6ko5 7cxdG+QIuSn6MQ14Ejt44bEBhaHf8Hwe6Pw0YgNSsWitPnw0hf0nVHCHUzqyvQVwsw7sXwy2JMZs 7bcs5ebYtkQywh4AQRLTQbqtMQ88HEYyMwpFwUc8aGopF7wX3zO0Znj9MQtEG6UeICx8qsRRAWk/ 6iGpw9i+NHW34mLxjBxjIsTjn7bMW17YUT4TAQjgULTerEKwSwRwm1ANd77bSpQep7c2vqfk6FJZ pZhYrkI4T5cL470rFNlDN8RzIpBvYnvtPc29FzQkbxaK52xClkjc7nu6yWXGHLTf9bRSw9H8h/Rw gkAIRDWZhoJamocWaH9HSYLqXEyrhMFnMPS/BXciYNXvP3W9LU4srqRH35zNoqBmWwDwB5XVWn0n xOO1jqCmQKH/ja07fW7QzijliN2vNFDj8lOGrLfdUpes2jVCPCeFcQtWkQsCUSCEDb7OukWpnWVJ rYirthtJSZqgh3d2HXealX3JD6CUHf25mjew+ChqU6H7lCj99Ody5A3KI0nLGuQAw6yp3X3S6q4Y kF6aBTUIkyTyea0l2kap1r4xcX/IOVqdI6EzluV92fsRv5l7itiRrUbPFHobs8ijYg9M2spUED8v rTJYIrws6eOUlbfj6Uv1bkKQdYdRO+9RfyqrsZvF5MH6v0G3u8ijx3AbcvTMAmF9y3/YbHWbGxk4 zOwFkLc1wy6Bxbp8wrRC7+GXmmzpovGguUyTROfEd2OnV1DhXpnH7SxryeRYxddnhAHp74I3tFhz AbA53ZmCptFAavx/jwxLSFRApbLk2tXAgSKatwj6Lf4FDo/IjU7bcIqyJay5idWIClfw09o7dGvv S4OFiJ9pC++ZyM4eUpiC5q6AH7+YWKa3oF0cPZMi9rY4go9zAJIdEEOrJwqy5W9m2f3O5Nuck6Tf D5b6S+nyZx4kqithvH0faO+z3tsfC3DS+cKbdYqo3uFh/6R4NPKGKwj5SRwVJEsLSruWc4vb9wU/ lZ8biKsgFim20eiMc8ODTcLbgVMWNJ/E8zBD0VxTnar0p/0AnP43CRZNi89u4UQBTZGYGvyrMzVa XGtSuG+ox7ftIVgZ0Y5i9a95O/qv55NvNUhLTAfaP1h361V/M5KbvzPzXfwnG51O/msb9+tVWBae H2BZ/UBfSyrRnxvBgypJc6QMaoPK7Pg4ClXPFuDHY+pZwud0UGbGKnOfWGuQBqv1EAVU5wIcGRWx dxK0RCqxFKy4lXIAhZ5cULLvIeGGnXgSaYq+aP0pseJrUO2z8KeGV2HctndjpDCl0qVDplgoTm5F e3cFeyQNMv6Gw1uBl6/83O0M3VdRQONW9SXkTrif/2hXLBcGU5LkbT5s/3E2NPGG5mP2+r0uGb8D 1sagXAveXP1yDjv4mCkWTO+Qsj4Z7jdstY3JPYYWqrl0+mNMSZwCfE3UTc9z9SJQN+9A48TJQNgX rCEQiJ5qJE5j1CPNdoQtPCMF+2MqoxAdLXmB5bPqmUJOKpSqPuQ3xBgMxOX820uu0BWb0zBLm4Vk ozwwPE1u4tps0PhlqYpYSQyyIp6qh4dM6By/k5243Ph6au/7Tm5Xh+I09GByf32mjSrD56yechXC KiNvfapvf0K4AsqcYmF9sn4cFOHrGZuY0Bx/L2kn13NbBPnKMK9+shX8BuJ6pgba7MF94o3Y5S0p uVQBV9KSBxRhMlgacXce3OWBD3TEH0+DVyzeK6y3obdGbhxzqMMYHnC03QTrAeJFHdd8sbSmQ5d6 /AB3IanjE2Az5UeoFGMyufzMK2ihvFGjau7CcQXZ1Gzu/8KhcPE34GOzNBXcrz/boP0iCNWJ6FzA v/2GUJMepao3gDG2GuzUKzIYDP4AxRf9W/jV2l3Xb/KnpR/kvLezQ586+6vu/w9yEdlbZc6oAwSd fd1lM4i4n5qfuNTLvLWcmO5bmNA+N+N4Wcu6iRIhYpmCn8xQP09QR8T1FUN2XX4tP+Ox3Zh6t6tQ JxTYuR7kJ5JL52CJ99SPBml03waMF3aZUALPyvrkoFtkJOanUfb8RxWais+ST9XRxQ67O7QT3A0E 74TaXxGSgEKuhFI2cZL6MJC3tf4Wi5iVXpowsLv7vPDaQqpyjVMPePE7NCfCsFJxvVvpYARrAWhQ wGcBCbRt+uSgv0l4GoCfMfgU9ATza2wLI6AOg0hhvd44C9YdpIdmvUInBdU/nYdimFl3UFl9XNrN H/nENBaujLTsIZE2hKQSz771Q0MWGIX4nernSY8H9Sio3cfXk1Yi1f051PVu10c9j9OA0UMKKAXB g831CJpvcwliFIHzUJz1HYF8eljFzEfesLyUvbBDJ9oVBmWQ74kh9jL0cr+gD03pZ68dc9ql134w nH9s6d5RZv6sx90vkzuGSWCniGjEsqJS638pfRDI+JBvo5Mrzv/alIf0gXaqESbfeJ5utlLWUdCS MDcGPoYtrehdbAn5GqmhXhdl5O609wCEMnsVfaxpJav677P3paJrrNpyhFpMXwDObzyD57kaD2Y+ AeFaTBLsPl/sye3FGqNltgkED2E08r4m+avB84Tzs5Bf5oMbHYPwXgx1A3hYVuzMo4UZbfNDqgQg Lkx/4F1m5inTznNX2FQLPGQoO3rzdyhFFvMMS2NCG2hQeSUtquyDnSSS/vpFDmr3b8owTn0ikajj JWxjEfobe9VmlNmSVz8I87Ol2Qi1pbj+sI6NFgw58coMQ343PN0IZjSeRJObZEBuIh2gkCqJ1P5B Lvwv78BMVXsptbxAknmZBVT3Kc1Godpg0MSV8Tx7psQmWC47O532UZBdGndbVAdP2QVWZkdaO3bv Bqv9T+IoYyvQqc+ER5xWiIhSHQeO+DmeMv38DxZl2bW4o7uoFqEzNj0GUzzRPupYigH3MJcFnGGz pujXjeDT2ltvKMztuFNtWHMh6SLbaI2rM4xNFm9lcJ+XBGPquSlKKnu4WG2S9ERu7nVecmKKt83R MJFCnrr57mj+/Y3wHrdu/PJgl4hxIi9IX7+da9Xtzhe6Gn7qhn3OYo6Ot/Xfc60qimJrFcJreF4Q P3zBQmB3ccF9aHM3OHyMRrUMUERSRRdafMxqiHvdL2dn8pmTApYHjPDJgY9plZc0ubBmPDgLKvBq mQjGRMMYots1u2H9QdAb1cwEFRPJcRnqt1hgAvrw6qF/cWzA5bU8u8Y0aqfPJlCnpMXC9yDHUPsX iOkJrySE3CDG28FmgLdePLlHIfphuBda5mQn6Mt8BKstTOBZU5VT2DqEUniRXW/+z/0AuLAF1jkr pEzrbQXtcSCrkCbrEjJEFAL3h5q79fkasAUUkMGdVNz4wDsX8DcuyARGrlZWhHFeVixRPWzXLlwA rytP8LyOW1JM4IdzSETjoYbCBmfmW6agcNvf+o0gqpVuGEKJiviKU/hVSFvSgzMUOQc4kKxb9z4t g+rTELCJ25RfJlpCK2Jg6iguCtn9xIWrfrvQsk6/kHbkNQErDOOk+JY8CuCnREp+HLe9ucF6Mo/X uVvUPnuCxtvXBK9vwGf0Z2EG9S8v8BGjpoRwwCMBj/dLgiydTEmrY3Z/qpegHGOuaKxqZFUthdAn ldChh97egqj/wj4krVU0LqeFuctq9pu7yXzk5uMIGC1KacAH8njdLk5V55nEk89Uk1ZgsuKoYtSK BWgznK94o6eu2HAcSORFn02WBytAgUwvCnZUjJaiWOLgd4C6pRGPJ/GRSl1hTZydcu2X0G4o5s+m MAYkjPunSl4DCJQS6fXcyhOKmQrVL3HMxG+kUNVvoXSxQayV3/LiNr19d1ZB+onMDP4j+9LIkM8R QudIZPJdjZ+JVdbTDZc6IgkOxWD0Q6vvztLO+AKVF+sLnsGHDMSFC37+PdMzED1N5dmcfNuTeIEN mzmlP+xmooBjl5nCJ8T+ZJSauz4lpuVYR5q9+GXHT5/79wek3W5+wZg+hV1pqVTrQF6V92eAPR55 FdBxiIHwXRIDW7GKKw2RPauGWTvrAqVkSKn63jPaoKmYKeOC4bdzXZGRUacEwcN9eShsgV8XNf4C PwMcJ2nIYHeKspJx8Yr68dyOHz2vx2yd9wd3kiLurBrAqCNbWlErL2LTPr9FRgOdXHCQzxxX0ohB BcHRwuBkezKRZ9itQCfMkGHqE0csbHPhz/M3K4swpBxKXNEtZJSmiVA7geU0NzGsXRZuyHcrqkPr OA4I6EfQ6zPHMisWXj1mCzB61KK5pNnizFCC+U6GqIBo10ahd2F0pwS2fy51aHaBwzmkQfYXcQGo MNGzym1jg7FUoW1lmXSqFvLkpt6ZnakHrt62vC0g1leNL7ttTYwLIMUAM8JHS7P6TbdLLT3Lti+A cKx7YAMEixArFbgKTUSaFS+3ZVRyPlI3fxAPLndsk6ZYNR49i3+NplbX9mgakml2DPRZvfbcge0C Eks5OgUeGqwxwKjoX/1DX7TpBPXJkW0gxBlBa+Tc9Y+JIc05WSX9Yngg/dj6B1RbhChrtl0dI2b4 nQmb6nX9nb/PQ8qNxDityib7MxlUYqxzIWisoLWhVWqWuQ1zIKmo26XKTQuwWXibPTFU1giPfuTI 2uiV0s4qmU0o5JG098WJLDY/dVphaOswK9gDYth58swJP87W8abJfuWL4W0jL4yk5iywpKMHO3c1 RM5VsmtCHaAlPlyRhdbn5RWa7TyUPgwmOD63A0ZZ/JUCCPLVnF+gisM9z10CzcPUd8sQYQ2r3gJb iyQd7XBEbySzIz5/m8D0E7O4g8YBh0uRbqqkYr6v14zsPrWAxD20XJ1ii33dM2xR6lCQEB3LtJy6 U8wyucnnNEjD8C7dlYW6QqPCQ8kiUHDV6ACjsHotH5LnfpEBJ8aumhBZ5RINEskhQh8yxjJLC2YX shSFX+U5kW2Ca6GwW3YNNq8Y95q8NVduXVK/iiVqlCSHBkHbVkJH0nbBSrWETR//V3s5fPvnfa9D v8DiDQBFawIIg5ufXrHW5oLiFqe8wtCoi38MWYkCCJp+0/+OWhjgMlkhyJ1OCV3X4yQl3AuchwBA QMGbOSldolc+yso0esfzYZdopVUIi3aYHgRpeUyml7GhZQpRs8wzcIKVk3h0+I/KKcWeItT4y4w3 sTZXLUNK6xzNqIIPNIbANIQIC8iKsLTfZkBjh9lgPxEvqWPO8vOf/0MuajWSt+L3rIg5yZ9d7mi4 ALhkZTLJe1J50DmSVx2FHla1M/UcWPnUvsvGnN0vSAM4g0YSdqLTFNODVTuE8FGpsBFXa2TWxqJ7 di0l1wHMqPydBudVKpthWQJt8q86bkCJa6vMF12UWODjYSEHH0ZHTn5Jc5gCIx7y4iybJ+/QE1WQ zYIx5aLX4Ruq6o9ihWB3BNf08K5Lk85XwEQIgV8w2X3dXCmOGTrMhF64suiK71fCxEeFXFv2Y6i4 WeB7qZXKdflK5ZX6YhGlgUZtjDUHO4VO8edOQ+EguVf5TxTr/k3SlZCNn6cTZnJL70fPj6fzVkN5 voJZLXdkw0k/dsmDygWTr0sh8IsnGIsBvgueb+xRoZ+IHiHy6VBRzMXU7f4ywgCsAQjWEZZ0mzzE fUQ5Pw6AmB8ao4GEQKPxY+g0/dC6bSQ5LQDDFjqO7OD4HdMGv2FZtcqCQOSYxrrMfSOMggW9AUnp IBqh9f5HT8ga6G+m7wzhFsLgpj0jHifHr3HF9YbM969D7XwZdHqycP6SGiOXYR9DYR8JDSKJq3sQ yHXRQPScMip2FjaRSRsql5FiaDkBImHwB1BUODQL4VzDK5av4w6+y86T5kyzTSvJXylCaa5RKhGT yD/dgUR6HJyBMizqgX0x031RSayh6VQnNUC476VFFDuWnRkxphAfWEf3Rq2CT3Gmx7MCoYISLv7o jyDJjzoNEuSkNgfz5LgOXdSuDbU3NjRzrkxxeo5h/D6tgWtmJ2pbnHaJ882nA7KZPxfWYzCqF47P KMQ0Wb8eUnvG+2SDOeVWzxyQze3GG+bo6gRPFLr9Q2MSG4mbfJ4dfvXUhFon13HNH/4eDkK9iKBT fwvf4VDO15bs/DWEFvYJ/NNaiju3vVIwBt6ovX3xw3uieVqRE6L2RGFzP/pefNiskPIUJKLiLjyt 5d6Awns8WgrLhaLNoNdpACzYtbJqX8qJ78RZPuyC4vSIbl7XdAoBohbJPfKxkQmaQWlkSS2JgwDw fNWIK19I5pLWnPoTHmGD/IEYbhHFDNSvFqWKtuEKInEfxu5LjrzHkydp66/zm8+AAF0zTgDVAoYw z3SRnFFttXlfsytMFj73EOXDM2vuYCsyyEbWCahjZ3Ukh3hdLTMwQZTonUycvQidSd9/kBCVpk7m GA0qE4d7cn/WGNFCXCSd3KffAIfkl6b9m8sn8YPKFbyqMMRRHn04+Oxcgi3ULLg0KgJEqsBlu4pw hFtaahviRz0fQGnDWJI0sQlY11GHcSHSKRZOodppJdXMUYYTb2h3TiR4JgwOHFWlX0+Bj6nrrgaK 7bTCmXDda0vzBnoI3m0IxgHGe0X9g3/Zg6BHiGSQ5067dU4GxRdvNCREGP1t1zJGPp4DicG0K4ES cXEXZrgNBwKQyLlKTWBjHw9/G1gL00OSac6msGhqYz5OK3pldxUB9FRCwIU6ULAATNd86XMNokGz elG3vzMkTl084mlEPEwvcuCix/qzl3WxrGF4MkFT80ZedA2OLSzoG4XTl0ksvt3N6CK9eCs7JbBv gS6skpJufBeEIHj3bql6Y6eRsh5l6JqystIkZk4eqXGqQ2RWCDrLPBSeAFmmG9cpa1ge8J7oejqP iyNEwmJ+pY0v5wtJsQ6oFOBX50gqFS+uvBIv2B0AkEWXnzZMaI8w5H6zs2MGlbuLOiUKq4FDoxRh pTSS1NAXfJk7FSoDQl68l55Skkm2n0Q478pWuhifBAXm3t5onQduXKv/aU3zUPlaa+qsYSv6YGbg ZV8vFqbbetQLWGltGux1Y1hWdJLMwJ0BIi9so0TOnozs4F27oCOQ3cxmspZCp69PfM5xhT7V4Lct q7IHkNpGo5KQ5WIDhbs4O3QJraXSs4VG6uOQ5gfryeQTkhPljyMHTDLzZ+f4ZE22E0QCra3MOHAE VplHwSWhmBHFjnKSkHLr8HO3u3/nhVGWw+xsRcDND1yHWge9t9nkRu3VUOa5p7lRR5A4q0XEW+J7 dQbvTaDMz6ylt5EON+KY+xNKnk4ujqQpd5IpIMPB+QTJt72tlrHmLtLV7io4sHJQLW3V/SSl3ri7 8O+7wWjaIfSRCr/cfrfc+kR6YkkP/71Tuuq+t6jhlelrrzA+/MdH5YjzraJtNb2hGwY+yPt+Y5H3 f0P56KP3D/CbG+OC3v/Jo6UbXbPdvzx2ci1i6QLgzbRR9JrjIqlP/V+LRV2sppcMYlVhzL2JYVOe FaKI0jjxWSy/m1lqfHjoCenPaL5d5hK9eS0nOjjhxBbvBx7aFUxriUye89gm5vuOeITyaShyawgb XEusKWmOxjk7/lLUkBj5A7qt0JNa+Wjgg5l7IAkYxqRpHkwYbKTJ/U5IrEi7dquYCt0QToKICYyZ jMj1t6mmchdMjLFwOOBoQlShLWqnuHi76XMzm3GroAfxmHjmDB4s/GjVmOooqp/wksnGUdKcSoi2 ZSGnfH1qDy09Zhj1+xsjzm7iIXA9FtGRM4MbJGdTT0/pWOELhxZ2mt+Yy/UtUlQ0OUt8PCdv0vs9 U/n+lduakMWB2vJJWjqoNHeEXfnbMVV976o+vMu8OpLsMlMLnr1DbkaMDizYPTPcXm2/4HFkJlvZ lxiAmbmKZmv5+rwQlFGXly6Pe0+TKxWFC/zdfwa9po/iaee42jxRUIzExijDnhp+Z8WkCXSqhB08 P3WNEWDaCSUJ4moxg5TzNQqkpQCoF9Ebsk7gmdFxEHl6gFA7gjNQfZ+FG9Qi/TOzPkktgu231Pc8 u4xwactptVfol8H86m0o9w75Qz7v7b00EKJ4B0uwSUMyt61CeLxXtVe4vmbX9BqFaGMRJQy3Gb9a A+z2R0/9qxzJZJJCGsXNfm04Tt/06FuHImygyX53t8yobF8H6ZMY8vcu0TSUW7xK9OQ6rBhU/8az PrVUfm1kCyb6zz3YqqW/BdHRNax7hqsxNltJZ5KGCKoCTXTf4xGMFKo/fQ3BlRXwn0kPtMJadOco /cN8kFUvwaW/+BLEW7AgHegAi32Snv+Jhs6F2DkOVJCAmA9IWE/hAWYMcugu+F+IHeRikP+xKqCY vXLfeXhJGGLR+sb22Wj8sHmtFAwrU0OIfY4uBLXp9pjQsQXj6n5VztHqBTUKTpPvepcaBloiislO bz8NeePUAmDxs91Qx8K1HBlvU3Ypvw+wo95CVJUof1LifEiv/IFE6uIzp6pFnNgRIUkzJ6ggVne8 UkY24a6+hzni466dLMzhoOoCUepAIALIEjjPqcQJK+Jymcv/KVCTaVCzPhT84AFWXcwO+/5mtLcr GlbQlOKT3E1iWGkQ85deNv+RZMgcavuWugUjH/qeNsLod9qBD5N7DxU6T5PDy7ejXgb6W3y2IwCv 2AFybpD+Y/RDulhffq1wAXBZIXrGQG7djJKVUP7ZmlqX84+xKOsoqT2ziLJc6fJSEbZ3PV7nBITL VnS9aZ5OHzYBRhKTr4ylfmFY5Tu8+eC2T4UUlS2xtRr3kFVx9P05wzgQKgz1yMsdpITQMPLxNXhA 4c+u2jz0y9wn/RuQxBn4FhZOPIezpc8iWd7R7ug4Lgs0jmMbaM5eciqJtfOfyVLBXXpNfdgAlHHU dlyf9N6AZFgBol/7xCJXAwG1Zkc5gBXzqFa1JiUsiaCx06I5bs6niaoTXkbr038kaYhPMA5vWrby aExnEBFniYb9IlXgnPPV+YBUvKiK6KXmcsN7kj0OWSLREW8Lrwm2H03iWMymeyq5vKYQJPlH0jo7 ISnwn6hCgcfTHCpkm4xytHYjfp2pnhz/WpTxYcZhoyx5MtHD6YfxXqGRB088mVuPPHR4Bqp5DClm 3vGJfSUesH6m5DSP/uY7cio7foSk5K58gKaUUabOJHeeJZsbHFn/zvQX7C4GGN43YAkVPpgpKfA0 qfE3XnEUwo8WwNoaJlbODkKyhKibwGkgKYzn3DDmvbiGiOA4nYleAii5RLOVjfY4RFuUHcRNDSMr tHAvKD2z4l21bX9h+7MtYKLYGwNWkroMvf0Ww8Y5uh1Y5FSFBxQm3rH9g7/Ku1FM1TSkDGkLs4K+ nafgl5hI0aYZY2ws3R2cMSgFcGLroox4qQbx2uPS+2zOg5ou2mal6So9E9eaqnfL2ZkX6ogGvhWr M6kn7bv9sYV3V07PCLld1EJsPQyPPWRzdl0qzT1ayuZNVMqOBrli3/8dwmsU08L69nsxYcvCYAon GslXHs2LOReH+0dNw+TAckjKZq/1rhRpqqQuvXq2xlqSV/VukAN3d/YNi8ZK8KsdQmIUcO612Tce uEALtdseOIuAwOQ5ng3eR01cJfcxltT7XjasT7/ThL+VFKXngkgnYSYhpo11+jN1uZrKHMGIQPqY kfMjsR5XHyP0AtLQdtyWrrXz/F0syjR2cGFNWo5bWL702M4N3WeA3hPiiUOn6w+CqG5YkxB8jgHj KfOkAJv2mpcVcmVtgjpw3L04af1nLhN6d3feyfNbbpIBeBhrnWVLeUvvAfwrPUQ5jlQDwXDAd+vr rECssuM2NOMPp7vrfMbnGTgtOLDLIfHC2OYi7gmUqifgb0YBeyql+Glo3R5qBvwdfvzeHzkt2aBS EOzBGc/wULX4uM3Ju9xOFe8Qj+S+eaD7nPqn1ssPUqN53jlcbk3PtNXLPe9LuMGM4bUUpEHy4DOK +HbiSxH8Iurrg/hgYVFUn07lhE7ipSKOp+zv/jwhe6QLUo3nLASFnHxDsQidX1osOk0MFBK4ivjg pcG/+MW2vH+OFcvAxI1varbDX+Q85K1Dnp5qgTnWnE2lxtYCvwjhoermxmZX9yfAH1SkSgqnCEeY /MWxiJ90qny7Oqs1J9geKeyY1qCD6RaEhn/I79K1JbkqiioKZQmwgQfhoZ2iNbfbYCRaKhoZgXdS DiGv14ns7y4a9deDE9AvbJxqEa0y3H8JOrl/4NX7dhGjb/kDHB8585CphAybi6KPUdPtA9n6CkFM ENQITRpxTC16sdGiyrCQjTyhyp820zuOcGE5uBeoZ/eKR9P2O83BmPzZk+epVozr0PIvXOKxYHt/ POk9FY6VBywYFSNxYsCyTkG5bDtEzFzL/FP1mQx5juVF+iya7qEhcLJnMo3kWGDqJkWLyHe7jeIA TMMiiTd+PNzcdduT2PRm1OdkGNIPIIIeiFSD6zTMGxf+7cWQNmglJGsrDjQT+kgSKnlUCyivFqOl aEyHDwsukM9l9rw2wrH/pQC8yaY5uYlpNv6HX6hdo8QXRT29gjaftNsdCwZGqM6v0oA18uW24Y/U m/ebscDVMe/+fNm41H5t14SN1ERXOyxhm2JqDbsh0IVwX5stprZOPHtITlQJBkN01L7KFvWnW0BD BH1z+n38ukz69sE/PGGT/nhhep+st9t9u4AWy1w8+OjzsCmEowdZ9j0onSLR7FTEWPEouUDr8utK Zj/40ifRPkZAUUeijx8hmPdSY9IhWunXpUTKxbwJp3k5s4m4yp46AAAZPoMI2jPins+r/u3ehSQi xCrrFjm7igIgNIygPN47cdMhLN/zeg3AJATcylE1eOaWw8xvq9KrzNuiH0KWahmu8c/7TVvbNTaw Ue+y4ibnsW4D0l7aeO0TmBSVo+lA5/+DPdbQISQrfpzuVbDlpuzqMDecvYCTP8oM4Tkfl27JbHCQ Mkegq5dQ3wo3qJAsT6/Lh3eeY18g2bxIXmBi9nkYMWoUiUiJ1KpNZ+Ud5InTUbFNW2CSPl2GVxWq 4SaI7lMlEqCcT01khZ1gpCgJ1LjwjtAloGVXnk2gqe5r9/lzAX68Qua8LwFaOLTei9EodUHZpg6G whKJtYM/S8C+/An/f2zfKt3kHdxcsA6CdOLqUrjgE1tGWxc3uz9B5eOOh4LZciGkDtKey/h+4mYo x/18gVQTLwRzPRqH77dRkPJLMi63TseFkhAXrpoxtmzrKqbOycPS9eZDK3TrpDAV2oliukl5vzKo UZJJCU7TDwJgK8wJJyPajofq79xUPUtqz0hmYqG/30nTCrXxWok/rBOABIBx3r8msDIUalikds3w WXibmOgr4aSpDPeIwNyksaSPAWsA4FmxSc7rIRJdErs7/Yk1K6LKkhnJO78Wc39w8aXR7tD0eUGo Tmc+Ih3OqF6LLNOWE9sw3vaH7LhZ9FdjyuxLETMUPJGfhTGWNf3s/R68rrIv9adfAmSjr/qo9CLn DzqHxiXhXtie4GXlqPcXjySocZKqLTnn4C9JneQHA+gp56AMsECg/+DlIOVuufSmVmliE1Rwgyba PjCTJpLUTCcuuBch4FVqu24+ZfQtway9d+UjnAFeG/CC+Ojfayvltq6jzIagPeoN1K+7VpKG4ene CORv2EN+KtJTLJMqqq0utZHwdrWGacIsBVp8DTUZtP+WV1UyrYYoLSRjWvEuUV4M+udUDFXfhAZh fWQOUaNywcCRLGmjiizLmQzFXUGm9IWOfsOJhRczD0iSlWau9ILC4t/cfsx/AFtRo7ngp9FqXNMk zBPmnUD5JRThFde5hLfuIWsu2kPFxGXRnrptFy0MjhSgXbuWGnvV9z6rgt1cRrxiDliBhPIGVHNN LyNN52fbZEPj2tpHmos42aYd27xSpa6RrQkjRFkasybB448MkSMwSgYsEOMoi0S2HBtCCcU2hDDC FxK/qxZkS2dYHEXDm++O8F5NSPy7S8+bwImYoBIf3XB9ldCiEgXgswplekyXdDm+YJ35Y5e7TaXv jLlRwltRHgmSiX/kDOgDxjv6bJzIfuEltVjrNiAhLq1QodISRl06h1/rrzU/vgS8Hdo916HZKyuG oLEUoz9jYCoLM2X4j7GHMW3LIpg5tZ0Xr0qepteG2XO3FOyapoXXt35wTLerW+XBo2gYAYbKrRkv ruTF5xT8MkaFjILEFCqa4TQUFQwbLSUVkrGjdGHUe6O8zT95AgIhEvVTezTbmWqJ+JbLduybC68H BirFSPjJMJ8D7dVIp9OhlU8mWUO2ZYMB2D/z/43zvYHQCVpVTDoNuPngI4+IfhQ/TPSIWj3/FwBz aysFvaqc5DDfizhy8f6rctfqV3T+jzkJXhQr2SH1sFZQMN/Ctj+DPmoM4gdsikwKGhr3uQ+HRWwZ A+/yvsRKeUVYwnf7lIeq2e9bLVNjiUIQaE11aWpJ5GWY0XB4+PUzc+cJ/Jrwfem6aUrQ9tbx2ZIr hYMOnLZKc5PuNhzgpRAJaUh70urIqT64yBOnl3HZbva8FQV3HcrtQa7T1opE84IE5bQtMv2iJkgI 1z+/0rSYTxVohf21bih4KX0ZtFAX2ne2K5N9HgMPmCAL20FusIVzPv16ZqtxGR2ExkCEcAtVfC3L F2YvunIFnFZo6fOC4++eKc1uWWUvvXDPgXnnrsSIUu8stSnvWG5/0/TYasUbCa5TXGALXN06dVt8 VEE5CkG2U8XLK/yYnFO6csJT2jIU67FxJt5laZf1iSlBM0nY0SpS2JoGoU5BwQsB27Zn8DXOjjpp BRfndQ6F3yYFZkMu0tlhUSflCYMnsKPrw4ZGjT26lKaRlWO5cdCTFajkIUuumOUhXdq2iYDp/yye 7eRBErm97voOhsCebl4fq0D6DpYyZfKEDh0D8WuUh1XLdHQopvrEGor3Xe51n5qbpOi0TIa/AYY/ JI93LwkPyCrscH5opqp+WiP3dq0oTVXiUwvE3BLBGzMbaXJEj+JrvLipv8Fm8VvAB+F+5B5/g3U9 sFh2djJC3e78/fT1M2xWuFVbcWMnVL9So3c+AhbgAagoDHoSw23EnfkaY7Yx4IQubrv83wiMrprM A++/o7GA/FoFin8mjiV4Aw8GidzI/0hnFVCVOxVkZ5wtzPczVY4pI0xdUXsf8C8NVGWP9qqkd1wJ KOffb87rtWPfsQRsN4XGuSv9PHXX5xzMqy7EghhqOb8nxYPNpFryxOyzOR69syekhDRE62UsW4jB PEGyylj4TuKj4iVGUdjgFaKUWz65cOOEIKHznpz9uGnpT+mnCF1Wob9gGDFcNgXT5Ql5fVCQSmBp MDFRbCdRtsjgl+pHjzSFWRy1BMZaOHueMIhzYMqP1VNKpm4xQJvpet3SI0RY/ngE882c9xuLPWTC eoLWcBtlBsO8lBJT1sap8tx+fjbiSUxmARJ7XLZKxACpIndBTh+3gIouEEgGAbFg5DOJ/uJFCy6c C2yhB33C1ixSzO+LPPi/CMxt5XWOiHr1wx5CNhH681WLNgn3Vdn3wVy3HwcyTxpQcMfy4mUqd+/S 53RP4KoC/5M54xU/cogIeIi5FnwanF42O5HPyR/H00t3WEBY9isrmks0M1c2DLs99XeP5omjZBEH 6rystc3NQ107ladBmEOIUqjhvG8KtxTYPEH628239j/idHpiZibelzaaimrZ+DYvwptaFIabrClu UbxOUsKaYfhtg45O0w55Sto/orCj2nHX3MFXVLYsjKI1RNfIIvQbE2ab9QJdhTdgAoq+99so/NPX 5jn17RPU7jKd+uhmQUPaTWvdOG4BE9qBkkvUZekbfhWv2R5diA5hiYFAUXUY89Tvowr1jNTTOz3X 7i5r2JczNzFYefwFlLK9zu73V/5hJ38FnREZbnghVxACpGBQ7tQqBgxUnQ/QRIZcNdj+BwHgK8MJ VeBxCk7uju1Y1fOj5PWD7/Q06w7i3H0D2goiw6BA0OraziClYnO3PziD5/cXQGFC+V1rW17tuODs CSJo4xYAcgk4j7xMwc6Dnbhj2CCOlYdPcq9mDxpvoOeIsubgalrLWipbda98OK6a0G0f5EU/soF8 alaSUvAaZMBm4mdyqCdpnXp0yteRMy+hEW2B6a0DPIJIQV6lRNxztvtn1F15g8dYozW+xcRF5I9d moejH+9FvfAnj8y9ePb125s4igNNh0FZmPWgUXzyHx0Fgc6LvUvy8VdX4irmJ1lxrwniCYnQtwVE Tiikk86/O3aqWFGXfEIShDVZbvOSNbGE7tdeL+3mYz25siR/WYOGDEkavO5LTk62ZiakzLAsHFrX dpAFk3pZnXut/rSclmjh/yg614KIYyAFTd+OvNJijlDyAfTbIF4FASd286AVgTg7zccGZ4J+oEPU i7dCDNcPk6YKeOoPJUmmh59u1eNjUN0qoSYPrPVgFYp9RjkgfGJVOdfDfh0xr36Nehg0Qo4Xrvl7 QFWu+IxsYNnOnFPV5DmFrC5Uesw5UEnhKTYFlhP7ePHijL8QSLCLiyAxg43ubG0pI4RumrEvzQgS thOnJDZkadhfq/VjK60t8zBqaHOaHSh9DD6Prx0rTlmPPDL62GSWU31i+eDcsrtRtH3cHiMikbip P/kCU3/mwcG1/P2/OhAd58oNLH0mLzMZRIKJHRPKr+s1gKjQET/BJxaoRvYAeCNi3NOqcBIligf5 2X1esXxtIHf4iR3QORr/VEeh9ckj6/mxgWVy0Q0z0Bby5/mHI7+21glWQ1QMSjpHvq4dMtjgU25a 96+0sAzy8cdiTt8Dg+XCnFzd4HukqM0LNLhKN9WN5uBpDoAYE5THrKSyjUFCn8Uj/l2UDjRE+4VN rr9zY+C3wCTxQSuC6QPlIzWHuuLDkAYh+180jTgL5IA07za2dQjAxC1m6PLzfkmpVaUtn5QkbE8d yTSpDn8WWYqF1ByB3FgdpKwiRIqLNgojT5OssiyVK/WUxB9yXF6LUtmaYRZw9LBg4k766lI6MtgM fgnzJrYqX4XOI5vug36xJ/1KvUUvRsV7zAS9WP5yivPPZH6CzJJQTsLtNZq54l+bn1ZP4c2Z2w79 rxqF2IGHW/KzHXi6Y54m4/X/jQs0ShUT6t7BG9IiLwNk6vqDbGC1J+jIJAaNu6lqp9fNudw24mbr HyV2Y3UMu/07hn49FYECkCZDB7FAE8nOQqmLck7SH3jVUxlUjbpDm5S5x//FzgJiEmTO1w3zq+W6 rH68KK3YQYEx8Fu1FTEtbjQ4NuasRDQuMPDuKmBiuMIn9o7SKFrhbPGvNEGrw9iIYLIGNYgbeO+v RR3WBOQ0qPI2d+N9H132JETM6solYaJCNzchVcxEGodZfIacEVqaNYun7dAns1+n5lcPz22RApLn +yIt5DKqcqp7sjQ+NPtz62D18gQ5ZjFKmnwsQDkGb4mC1I/N1d2iDxV9qn7LC/U0om5s5i9P8e4q Vr4sRBwg7iHCNKD2xlEvfYafd49mHSFQitNr7UNvsHvW6i9KN/llf84CxJL7VsV4Kd6x7DKJ2GXH JolYbwb7ECbuvRvKAHeKOPuKTckU1tsi85GcmNfYwkfi31pC18WhFpuXRuSAHNmJzx63SlJOEz0/ o68eJjFJwMzukkCkyJjNEmVpTzXy2yZ5N3T1QOYGezgDUPuvHIRLlqgNTRGcdSO9VTaGxE//lEcN pe/S1+sQ+RAVkx+Y71qT8m28y64/1mD4Rth5WoGaT09vdp2ymDCidIkQWrqd7VyITB08Yfx1RANK boOvEBNwKYHOu+USj7g6L/Dq6tnAD91oDH2M9UxNKhH/Mq6oKITRE6vd737RhCb8AWFz8avAsEp3 DqtWN15Du5xfQtEnbknyV5Pmw4A+jIm6KNcCaVnWc4VZV8S2nqoM2MHb0d00jJZ21DYvR70/XmXx F45PdwDsyTDxCf6brXviyIQNOR/uCIFaXx4sfIB5qSBwuWP6xlJD7Tzv7GB2DoC6Mfd9o7M3vkom mJgnSO2ToC9bC+pq1hLR885cJTa0jlnt8SVDN+UUeqU8WYQsz/AuC2qfjMJnSvFegQhcdGP4fTIE TPJT4INMRXt6aiG/dshvK+JQRvEulz6BT5pVsMvfmRUvJj3QdGNJBge3eFR3RTAW0FA8C2RHwOt/ eFQFU17WfbbDN0S3b+kyXtb3VWAYXPp0bNzAY7oW/u4rWZmHStkaNpewNH5BeNab01qfJDqbhZnK gN05QDOlJwX6NCrXraVQPwhAzpPFURf7aoe+a2pb9f4UOgYLZDYr9ceCWvlKzLZoMZI6xO6sCyaL lFC8aaIwzgxRhfg901kCfMTLCBxr6veoc9H8XGWgbeTn/sVPIkm87XkpXYwsEcmapK5K48x55t1X hLfZN35JXhf2WgOQ6fvOOeygLXbO5fHUIaP3oga18S1HqPldV2UCebCJ4FK8uNqO/ZLLHqqx/5qP bQwDIxQcm2Vkr1cPTUJQCVmRcVHuwN6awVYAw+1sm/sLpHiCUA+3UVsii/z/Jyd8oZXEpqIC/WW4 UbaCFaAGU8AgmrZtZsF6VVTtFzpY7s3CbehPk4wtFJhbXN+Au9pShrQkESnjToqwj5YB0eRSR14B HAoMKKOTGKxuDOvZk9zJnm3FOiCOlMiDXuTMyM1pZA5Ir7IUuyM5u9MTWDjZwcK121iA4uuqqL4A ny6Rm8IX3Kxx7J4yVAzmAh7izUeYghP+SjEZfSxHnvvK0Ceow1j5+KkjOtChrKu3jKlv5n2LT1k6 FDMOgLZvj7dlpKwSELKFNLw6Il2xyH+GiIby2V4tKJj7Gs35n74p6KDTe8RHsCA7GmRTZK9kqrW2 jVwadGO8ZxMQ6r9J3G7b/8hZlNMYFvncXFLwlmDYXLaNXqvhxh1FQjybn26NIM8NCPCNKGD0IiqX xVCB76s9BkijrpORSjiau6nLAhEZnbCFmqZXM7JCfxDTmm/ICgBM5tJk4+U75TZ6egKbhaT7+Giq wcKKPBBRzksej+F0n41FItl5guChGvuTqFi+IpnkPZhgJuDHatDVAU1abn8yb6vYh8Gr3f6wg5d0 KMp5gKjBohzasC7xaB0gIRQPvT7ow+cCP36SqIAxdWnoPRRwixGniwLun2vUzzxl5V89K6vVse8c iITBh1uK8C83aGMNUbu0qmlvU3pgF20uCcGp58iNNwJh5x8BbJw409mIDoqysOTPzXdvO63WkLaE qYaY669T6I2kfbqUzdS11mCRE/gBHRJ6eYnuT+WwYcSfrcgpe4kjI+40Nxy07/cep9crWwfqF+JF ew+DhqP+JmjriiKy1T7xjQVTOm6GK1x/Ww8AKvh1VR+AzlEQ+C6SAXCvSXVBsFCQsBc+0xCGcp65 6fCTFPeTmtxKdKrBX/rVPaIyTASYjHHs5ckcduu+StPH7nHH3dAawq9g867DPA+Z/1qXHH5is+Vv Q79pM9qnecTRf1m/SXYLsB22EH85KmXUFgjYrCe9o28lKXbskDJIN4TFUNFa6NU6qshvTuUZ7nAD YolyOYKcZoMpLNiPwcF/IPK4v4KxjeGLq5+UzZmJj/+eS2D04kCXnaUhva3bg2ENazf0MClp+ArR KQ/GjTkdtJiNSOZkfSsGrZXQVpcHkS7NlMU/08U0nnlKMo9kB3SYZJ3O+79+TAs7iC3LyS1sa5sJ AScwwWgymHC45IjHQXBiQeN8CpgoVN4k0bxnkZKvhG1YVglYhwdiaHsr6kdRjA1/CD0Y+Ner3aqE ZoBc1u4uNmXtK/rRBsrO7bu1R6l8oZKpVvLd/OKULhRCbFSiDjF5m0Wxl5qFwXiTA6jze2JTs7az s0yzvM5qYVfRPpnWJFL/sZamGxB3CjOGFSj6ddZ+rn1G7oBi0c6Wm/6GpSpEmrddPW1jOAQMflua jFCtfen8F8x08TP4RD4v9Z9C6w5nOc5WCwazIilb46dYg+Bk6H21OQUTtg1giAx1k1wcACGy56LP QjAb69fcw7Nuk1xYexai5UjZYnOpAzdEhvdJ+0iASdbyHtkedAMWe+Q8T2nC8k1knyMTQ6OojEMy VBwsZEwnnLxsOpfwKXfaoSe0Vj/GyYPP1Kq6LDI4O90VJ9IJOYBRp7P6XCPX50dGOGaG7GDZ9Kh4 xEB8H5YyRSWEHULiw/5MZHTtsaATy8Lp0j8D3+NHGo+4Ed65GAdv/v5h8IPpWnLgRoHT5AaXeU+n E8Q4eA8LIdK14EIYLDNx2s45kXeVev7oQtYmq0JN4ikjhaa7OYwDd2ifvYVfhYiyD0N20me/PlfL EUDb9WNH7NrrIRlfwicXKd4AjugpNRvhnrMBXrga+0QFSpeF7fh07qTUrfDXpFP4DualZYzJ3xyN Gkxjo3Ip8nftxeydjfwhDqoccAaOzm1H77/C40W8F+6z3UQVyD5FfCbsqoD81Q0kHgWpdQ4Jg2mq 5VdGAxBPT835FPTP4YJ0z0wQ+YaaYcovjWvOQr7CNt922wY9wqrPXrxmMNtQsHfICxZIBPpeCdji IEgatwa+jy+RsI9L805C78leKbvmSqPRo+AgA8FHRVQ2wgAbsV4VokMIhuduI0OYj5WLDP8cq23R x+fXPg7h1/275os06vK25aci5Iyj06ATwme5ipKVKqUNacTAvWwKRxFHPg2/Gbmqu9SlWWJI9ppd XvIdwFSK1p37iBHzWHOoffo63DNcuwitRWu1pAsFXCtxLYMtvAymA+kKUGN0mkH694KmYf4LU3Y7 0UI7ZkXFrZ07PSEZl4PYPHFghwJC/Yg3wzHN7wXVN3qWVDzSWOVXkq7p+esuiWyAphS8nRJuWU/F jd87k3XxFf/U1mubWLWHsRKiIbMZHCxa9hPB4TPh58ypn4UA25ko4eaRTgM/lCIjw66vaCK5nG9h 14Cte4P9E3vukWAFDAsSryPy+UI+wS0npmVVpVm7RWmB8ZueCxiw3f9xkbf+R4faXG5H5NEzdE79 ndL1ndEACtlvJd+FbboS7p1CsDB3PXfTYsYKOt96knRGdOmEr2xLkxxbT4h67342a6hFG8GyJPX7 FT1xJ+YhsCce1xBS5t+EdLN4SLN+It/Yh4Ma71pJbza2gGxYAtG0DKQRa71hVfCitwwhUY4+vYLv bBH9Oi+oWCZjTHvV4bbli4dBgnf6L7N4qX+HTA0+h1AyZOhcI38AKA9+wEL8EMTwqqw79B/b7yV3 aJjQFY6FnTPcnUF4Ew3tNTHuJRHpUs50oCQc/7yR+8nZS82V3jdJjNL3JYArPZelRxg7oLeu87tr mmiQt2bOawZ/qsy02UnTWjTnIuPn9s6OKm6WTz5ZZ2aXhpCc90QgNwtf6dqLXAtHqWFS/tamrFdp nQF318f6cKmdzX2BR3vAeIlGfuXl0ZwFGv9nGLQ9nNAPmJ4fsOecY/mGQsDpJrzcTLxmaaGV/Yin aOqLTiiP5sm0J5lpK28kGiDS5IER0z091OIHeM8tN9SwK/jQvN/PfgXeViDpRnsq8eR7u08Q6KR6 a3BQZ7fauFhplJ228liLJmvtAaocOUnG6An7tGBpVY/9c9x4WLwWpeqejLjBNKxJNSsn0Jirey5K w5YdWwd3ubIsMoWh41w9ie/ifLvhpVfS41oIxipuSlc5Y174yO3vW+6MKoJaSbglC+TToTk6+xry 09ltfNXgNtpjhocNnvGA5bOLoPlHaeU24Vh39v9sEBdWaPpQVG59GnFmRB0oGCNjhHlOOyg/okaB mRO7YPNVjq31FYprqE60naOCeTX+guyKIpuBzPfjGZxFHve1JROccHzMY+IPFxOOeMO0NGSTxI77 jgF6ax47/tVE79YmmIDyu2AAF16MbXStvHeKgwuiSFwebFzZTadND3ABvPcDrw/HhCFr7quqriXn z9Kjno5OUlyyvw3hl3JtcBK/PJeoF4LITxMJRstPaQgMg1Pj8O+u0gg85B1j+y7/Gpl1aQFiHjB1 THzS/3CDbuUvU/dC5EooVcrbSTbO8MVrN9o7QsK7BCP7l11qFeJJrKVofyRVCD2dlzVZSdC3nX0F 0Zgrbq4o1DmqHHpg7wdAdtTMvMoyHe/lKP4pmfg6xpLBorIr2Cr/lBvzM2HuThd6cXsinfoBVKhi Ab89OgUnWlOuj1Q9dhYc++ImLAA+aJi8dkkzJz2uoaQlRw0vL7fpc10GnPgg9kmuijroFE93RuRm SrBGk6wn8zcSSpymBmTGHJ7/RFDahJC57d9p6R3ksX3Q4D1sqWWX8nEqmmwPv7jMSZLrWczJzaqw Z4jrtXXtcXiKI1Zg9Yy6QVOKQtw7ovP3OujOsATX+jZDXI8Ga44xt3VmnZI+52HSehh7xmXTDD5N So2CpilL9dQ+O9B20LKmuN4RQ3JmCWOV5W/RydErVrNgMHH/Sq+bEWzjcLt5mK4c0PSmjIobScZe hBGvMWgxrYY+CWDppyfFQj620gcA5gfPa5NPq6ZXRBU4+7odhBCIWL2laInJeUpXEUSZU0cp5m29 GodyUqKXz0QPqp5HVq3B6g4ApEDsMcZ51VNcy91WNRBMUSxcHBTXPPtT6pYGL4A0wZpOoX5R84nD C3GCxLCek+OVDYiqThMBKoAxE2qd//YlMuNGYlv9FtIq+b2b2cdt+p8ffTRXZtDsJArsPuhnD3qR ZPXXMHyq2AkZ9i8gcG3tQK00mwilJ/x+FjzZIhgP2Uf2FXpiLVuHEvQ7BBt91r1ZYKX4ZTp53xAd no2Oe3Hh9KZy98fRBIAYels0s33/HKNpoThQkeJ5yChrjGuUmbY0ZYMFrjDoD1qZHcWJX/hMMEPZ y3gSZs2UW3/FCy+wXtZ/GMcGHjuQuxk1CfivL0coQQJn0vi2jxyPBhxTC/e/qmMOCseUH6CPm92z tJ5G0R5qZEhXVyuCfLrj6sWqO5tlcsMyfPaJ2OjueHbbWtKDjxgY5BTilryZBHylMQ2wE9ObQyq8 +8A7cuWPXIMla3CDuOovB1LgxpBK4w+PoZO6I08PPJ8zSeYxl9EIv/NcdJIlnVnwz5V/5c3d7K+k PDg5rAhO6wVJRykySC++Q2mZFpuR4YUyGO5KjbmwmMa1j49SpEV6DklcNtwWoat1U6+mWKsCf7ti hVXbt2AomxNg1YzwR5RVM/QRGkV7hEGTG8oFVqUr+ifxOfUOkwaPdtHLyd3mQ1DJKW1NMLxXdBvA 6Eq8icjWPpm3urPMM/tvN7JwYRWpTpFw7487n9qzP79Uc6Ew9a1iOu8l/S18SvUcTJJJoQE4c4A3 BKrUAXIu8/pMaMIju1xWCIqcqqnzlz/t4zKfBbqX+9gygzJwkE9vXYQOAscgVfVp/TDYVPMtJem3 pv1WgHDO92cLpbP+p2KuIFpGQqZe991kp2JB26r9MXC/ZoGv5HRgdsAqcNThz6D1sVSTkRFTBixH NZyNJGAsyAYWxJn9lE8gyRBoNKJJ6xl3UMCV1eLxZPtl80MOeMlJlc3P0Nf5EBYZ0OhTzJ/UA7lL ZLoeFP/epFwW8NsCkB/yBm26Djtu4buDJnYLjAL3G28wagOKS1LktDRymKdq6BpVjAJdLRMhx9oS 6+hnglSGYXdtid9DQZ4zK+1HWUQVa+pofDP+N/vHVdKU9IaNCO7BKrs7pmM9d1B0meaD9O+CmRMQ fmFAxnqYwOoTu79JKdhbCxZdTFGT4i9I3uNFW5Xj7KNXO6TfM6LumrPRja1IRO+PSyQ3x+k8RXxX UtnCRmQ1lJBx5ZFUhs70IMW3UeVPOYASVzYWiHhuAVjc0pJo39RSKv27osGQ3uTJKGmyNO37TjNw x7vxBiREydv6LGzMBi5P7IQJC8tm5NdhJarNV7nH8kV79/NCYBeQLuJUMgpwCrqprbTPJCWngePX YiYeiOo7hgj7Ig/s9CHaRQmvrGTH0Q8RdskZ/pGLvuKiYUCvZkDilsDovxvtujSDxF8/spH13Cpy q6B9829kvSNjLPiTtuyz8FRIbdXVgtleJEpRJVS7MZKAixsF2lOrARFr2pKNaQ7VU3+1MFT9M2O7 9J61fqiDXEUZOtxodtd9GEAWo68H+81+djK+sR8T7y8kkjGZfDeuSiIHVIcPjHvpyfphk15y/shn zIT/fMdWUPTypA+h8AQilHm8gh+zrx04bLNjVgpseUoY+jN+YWW0wxQkQTU6qIbH0pshHC3mi5jL Kw9mSL3i6L+GyAxLl+r8rB9X8u2V7s0uq/xON+kpP0t1KM0BeS5/Wjhcwzq3RemGl57d1ZJIwEhu 0tfcTFLOAYa7eh9ID9WBy0sN2+uVJbJHgsDYXJmq3DldvemqgHcqfaoCrz2yHgYwEyqnyyBZerTx lGviEcfpEfSt22Y/VFNs1bm4ceU+UpkDERPrnCPPVa2ktHbz5DBVb9zQe+lKOm9TbaTU484ZXPGM D2WN5LdFQVBMr4SNeIY8wCrclC6Zz4PCipwM1PtxXVbJz1pYaX9skQWEEwT6xORLkenbr76tIMs/ lqoTkQ7Wzkyz6K8jJfFei5WxQZ1eenPr56TnqMx7KhYEAAe3201CM1R0wySpBwBePVMaVKXtqdm4 JLwYnoWesWhmuWWL/qvUp4jWGI+X5jsMhftfPjcphsnFZKL6m7JeoJ8rKbYEGpagVphIFqeNKmI7 wGo+b11vSMs2Dd3kTDDGBg7+6zpDxBHJEyxnXnVkKcgXOMaGI25nvRTO1UkA82G5edFhViks98Wj f0BjtflMEex4B9XFDQ+qXEIS58dZfERh9/maohE4Q7jPu3hNkptMIiOB/ixKTbd6x0F7rnsXjiVL /V1BhaTxK3fjVAmhYduRng1rmHcj/pHHSW4gGfeq6aJDtE+/OraFJ5+LN9loyBgz6HyXwOcsnxNq SP8MByu77POXYPo8pg1glCiieLl/F/3OPaWyX38FKDTs2O0ISQNrFmLMdJft+NhUI4zBRdTJ+kn2 44nCzZH+0XAU7XIn+ZciBT2VXTiLGa76JZ4COYkJC2u6Wikkf1aIG0r5gbBet+fjqIYArJ+ld6Yw UIJA/a5KGayGJ+gw05aBEvrlGBDaHOHOAzVs3X/5iRWHZaZBpe2fpzuvbn9qDEbZmN9wFEDxHZI5 EZ7dhP/l69O0Bt2YYQ0f+cir9NbKkwKT1yllSqlxNItHXlb7BhqEfHPlqavjXkA2/1UIq3HEvvlA FATjbBWsl2uMOOIY4+M1dnnbOhe6dIFQbw4lcoPoJjKoJNiBAOzGg9LJYjm2cce8t7jJ281haOG1 aJYRyl4HMnvzEZ718no1QFn6HKChql0CHy5z59grsf9Qn54rhQBX568nt+cx8zwBp1yenfXhPO9g /JFX2xf59kg9ClJRbj2fXQwybhaNB2fepi/jtn3U2xw7OFXLIuh60uzrUnuVQR2nTMKBDG3MbId3 QBTJ6opKqHsLy6JR4XdTcJI1VqNu+cakIj3kSs2DGBE9BWAMNtQWXqVyBNHOJ0Rb5LH/ijVjBjAs q7GtrdDY8dN8LZVWhroFwGZ+N3lrSWyqvTtN+mXwjzzszBZKYvvOyHbvYJ9gsCvrPmmmg8IryldH qrWh/aeHsPg0Dtj27yvCGT/Vna05tCkVvEnQn3VXpjImZTnUKkmbCDQX92lsSdvqTLFOnbDatTCo Lcdad6DZpiaSKYpX1EJMz8iwKnBfRr3sHPomRLvHsGcuLT91coDU6mc1higBp3is9RFzcPqTr+kA DbvuDBc+pKq6foQPsFttEFwZK78jrBUg0PbHiX8h4V469t1loGTsFIMMy8udIpoQ7AAvkYU4+lGO IPxlAi4Qqb1eWdQfgRlLGJqOOTohOy/UNxS3YH0hkDwEHdR6RTRIqpw54cp8FtdbIIfUacwqB60U yaM4FUODqp2qDs/yCX89B43jR98Tbby2cKO6I/F1r+Uo3MeZTKhn9JjcyjgrSNYUyrtbWi19AUmp v8/r4y28V/7haN1Fw/GayfBwS1mKcJ4TviXvraU5homJryAgm69aVBQc8Qz0XbkxMbtP23VT0Rv5 VAA9uwHppebnQzIeFqOiI1YF95PfsNMPby/vghXsucTrZe32pFPPxthpo/YEKxehtyACA4yfXaJC qAdP6BrPioqP51fmi26VKbzsbTovHaQ2rvRBpoaQsiA13plqKLcGbpW9Jz+WUTyV+QF7lRYuckGx sfDZ92UcHZEjvnXoV31S7uUu26Dh/RdkA2cKfgTnidf/Uj5idNDSQQNPZ+EN5aLy/XIxxHM4Q4mA 2g0inZS9gyVwF+xuPSYHEoIQvNI5MMula3u46C6CNYyBAmFiXF0M2BQzur94S4dRw4KX3dDU/HfJ b313BytmjHiaBtpqHUYSRvy5DSnz6rh22Ne43TMtf0yhceHGkmb4sZ/oU7HMkLemtmAsiYIygVVC dQxW3axY/Ruh1QfY6NhumaqNKMERAM/BjQQjnlQm0sRqVcFz0481xYYUde7/YpY6a9H6MTin64N/ cg/AXEsf3cL+gVWKGQWTpxBsSuwR8dcnUl/xziKlI36+dNWxFuyx1uAIcxBZL6LA1FpHGpHSKl6k xFN3NWOgczoJyofQj8jx2JC1H+bHiA11Pv/mkkTS++yTtBJhR0i6m3rOSkbPtpKya250tJfgIztO B75t5pfdRTze8VOgLQ7I6hlINSXvdPWbeZ1SUldUJGuD1abYS0MbgHGHIv6jJf+u2cpmMtspOTWb +whwIeTXmHl5vtKFSRe+Kmtn1WveEYCEhnn/x4r9dt6IcUn2j6uP2RJt5mYeel/BzXGAurYbjgUj XP/cCR+0C/DaGA4HfzeGs8CU6KUzyvO2o7gVq848vxKCUmSts2rq14upTbJ0vSIGlQwkBUm8+ANM axdDcq/yALgKG1klyEImSwFMztO5aZsfHcmP/iTQmvM6xtG8GZrtVx8Y0K06L5japR8+NHeiZqW1 zxd1UgswAGAjnkiZhvVX5VKxY+rSla4n1m4DYVi/2tJhJzEV4ek33LoS9b065HRJg7yU8PO9z6Po SA6UlipMpZ160vwcHGEOfnkpSwtLLIpSC8jWAtxHMB0gAz9drgA//nmZC10aAvB3FQtcTV0rWJya Ddkis3dBxjO6j6dUHJbM7RPOH19boegee1chmjgB9BXVsJmcH9wliw5yNDuR8h6ATdbvPPqE9llC UPa/zya2fcylKulBAoOE0Jqn+UgqmSaA90aVntdr6+XxG4yHgoM8eSqYlrVogp8H9hEGaiv626lL EzNZl9lSukTf9hBYeQ3HCOs/esg5NHO7l4Fj+5cr7poCQl9vmdo4+skSk6R2S67388+RgCL7CfxA LWbfsoJhGJ3uOsOzpqmFEdoBtJR41qDcbS/0R/M5UhEyztbSSEbOSakP7QPqd67/WamowwmISvIG Lst01Qd2epz1EPmXTodfrdXNXoEu/ahv0fYqoay/QttbKDyq+AsXwG9nLX2dLC5IbZmJXKrnvvaE rDgWFziL58g8zXS8sM58wjlHIJI/dA55Uk037H4KXkbh6NiMPS7Xli+XHS8CdyKGdeYyTrrcrmqe J3AE/d0japtbwtcVDt/yADY5DG5WwJMaAa1woCq/cPFWlvogYRFdDuCRDwC+mfN68nhjVQchibvW fIJrBKksM7pvxzRB/ZLrsxuXtcNRHjYX5L68ufX3qp6UaPXxFvS+fn7J9+0Ann3xlM1qDSzRPc8O T/+TftFj1JjWmqOlSRYSZO56q3/5yTwP/nDCvJN6fDpWHsbGHSe4wC6IPv0qbNL7uf2WBsSVWR1z GFaGgwxcTnpCQxgo7+UGT1OGovWoNHBf/VKsZOPavfJNcIK/xXz/jE26jV3jC+T33a6yLjZQCx7C D1rI3MEZuLE718gsUhltXGepNsOWf+SIahL3VSFNNZjuAEm1Lw9ujbYVaEr9DZPctNgtlxmB098V uvRhYfmYMEDOCf79dAz+L4kdIQV5W4AjPMApNorQOnncBZzN5axarwxjCTy44sw/whgscmWp95Pk Dvz2Kxus2U7IiPrxdwluioj3HSG9oaWO/KzWGtoyXwvJ/ZziVvIGilQb5oM9VIIo1YDD3KG/2fXI QE8l+LrXoX/gRqMHV7XEaUzTGLoeOgqbnORwxbwOLlLsUokE5KerUNDyVCZ0Ef5uc8GPsXi+GBB5 KT4BRAoVd/b61Q6YYuU2mqKITnkoimt5fA/PW8CtxXQ7Avgh4TADfWIPC14K7H5roc4J2PX3IjFo KWR7yJDFbOVwsnKIoy/HTOhj+EtifHgIlfa4bepPtev5rrRTMENy7tY7VoQ8oC3H9+U5dnIl69r+ y/yVhfJcsJYOdvP5PgKMbCCm8jkUig7Kkf3LMHQVQn+s/FpUD4+S2YDx0oXux2X7tOMdBBbxTbFs ruMA5pmRFng1REt5v+5ifbP3v92eRZcmiFL42hQWW2nH3vsJ+4stOnXveqVCCq+7XePWxyAAonPX N2iBPE3maMBONCoGMhVEplbrE9nIIGReWwO9263hapkk5oA8xgdoIF0GmmUUmQiSYrnZYkpkhCFb jNdJjvfVullfyIGi9A0Oqk81zpaq22zFQlez6s6jb7fDi4LwOPrMlf+r0ubhDtUQ07ZmdQ87mMGz 4Ldg04YjG6n6hLVYcEZaEHQUk8VxBOAapKdcR9efJ9fxL8GyaqtDgHxIQqwoOlfSUUY4eXk1t23Y mr4/v172h86VCYBKeUtP05a70LQrZ5c2gsN9GE3gEVtBd7EPDgdmU2H2uIrtdG1O0t//s3/Xg4Bu hv2lVliOe7jsXDLWcU89t+r9h1+JdB9uLKvJs+3kunWqfoFxWedh7myB6dYCBQTUkMNBtpVx4rN2 QqnrAcSW0IxjilYpLfTVegxRlFkx67pUbRcPgqdWZnwsA2/p6i3cOdnYAQK6XLCUelxVJ3VTI6ye 5dSUBg7LCW6aXqwVtFy70RISovHhAXrv6oG5tuA28147SsAK/+8OIY10FdLneqt8/5p+tgUmMPF5 EeYPUuwWKhMmmz1MhSW0arDvjuxZgzbs607PjsHzFjLywYJt2nnGxQEAYoeUktHJ2cPyt//C71vg DrFXkBWzpyYkDGGn/ocsrNZ6aS+cWHbcS8zORRWexxvK1s7OvWHnXCb+vlAr5Rop1WPf6pTmrUNb Fqrey44nwA9ymKNaPq6mMpn7GBP8fxGWm8wfLOM7O9Yv/kPhqIoFsPg4yu+2/y1hGyBZplBx87xf 7PUFhEcCMOmFu6CqD4kdJ9u+ppmepzFsAFvzYlpXTvQsvyp+023T07vsQ5B1Gef+f2UKqFWVXNn4 LV96xl5JW47Ureului96Oo1v/Q7KM+58Jphxy2EoThghtbwtbTMJiDzQUYD6oguRoL6zae7//tv5 JvX/29WldnoGJ2ru/IP8FGtFZBErchhhBAM3G9v3lNoVF2G0jR76jKD0F0hUMTAC9kwsrZgz5tPI Mg6kOsegkTuYRChBzbXcnSDtBWLXmYNeg1US6QKrPPaLvhndAPRaMMOtd9jd7M7sS5dxJDQNf04m QfLfne/7P9iccriY5S9egSgFkCMtriECkgsOcGJDWCGH42LcIEl0o6gtnWCRLIVPh3VLIi7Yw/6e KGYLoxCgkUVvGHDf0g04FnwVMoMMIIRFbzRJAAwkQ7pxvqFqCshuEV6wUPskO6HnL2E6Xq71mVF9 tRzQJP/J8CPpLvPEVcWu2rbmZP+mQTOTP3T7vxdzkfzF4GMkuD+ZNA5WzTRWUwPNRFuIctaQxyZk Ld274hAoJCiFrR4ttLosZTSzE3oIecWmlyq2TDzgKF08CjT3NXphsyzVoASohKruJXct/OgS3GLF slcbvbrhmmm9GQKVnPBf3hQ90olcSaMNsoxUctCZgNfZIt0AELTp7IfFRCnUFZvUx0qdTGqAzDS/ e5RW1wDmCvh3/UnhGHiSs+qYjxo1r3zvtM/BCRsrlKmzZsu88kFmbtJOmg7ahWNEr4oAIGm0UK1I h4krocXJlBw2KUUSfl3Bfr7QYWuV9uMteXdg1LtcjaIKt8X1MHJrhcpV8ZgpxVueDVX8lFPUtdAl y+awsaPHzPKammzl+FmbzDxuLxgPTykhVUfwPlpWniUzOk5i2+2548udOlPMzRxclNPilTVjPIwh KSCwj3ZUJmJuokXPaqOXnoYslh1OGdVR0JyllGt65Hem4ItjLSnV4wikOkK1zc1FD7GxSSWvQolO Jj7CfkSC4bYYfyvwovh/biNtO2OWiwISqV86hP2WdiZ62kl/igg3Ziv3NS0ynKOzM3JcPIzaLr0+ yBfWtxOHRyH0n0+E7hDkYpop19BhHeicgpN1x17cx8/MxCthENOKSvVPl2S0vXwpOXAF3BtEqPoR d0QZV+4UrPsPd4Wkppuhr12ldhBpSgomuLQfUdFm6nXWMk6reXLstXzcAXQ5U7YmEfw/BcTII1rE i+E0glEJ3SznseVccp3qgae1JGngTtY5YlvdItEshEp5pu7C+KC/H/9lPCzAiry+YrpwtgTrqtoq gpplf5HKpXOKlzYukkEuo9ftsPKAbRfuKr2us5vt/gbASAekLJsL83i410mLlDrKzoCjPq1YRr9C GZMJIzVfVOSPD3PTiLTWm2Y5xov9Tad/pAjg7I0GSkigtdemRAk84jh7vxXD3CiROy2ahWM0aYcJ /W47E1tgC1OSxFOjeaN9BaBsM/qm6KrM3/bmTL4oza6ZT+lwDAxJfmSI5eUeW4R0tliyaLt4rISr 1vIqurk0PwD+XZN5htmgMNoNG3Vcl4yqprMOwg+GlBHJl4lzaqm4T5hwFtBe1pWSRx9UiwhnXqIA HslDEz4R70WZyCSc98QkPYRSHlvrBDWHkU+uaasik4oesPldUDF3ZwhcVNM8J1Zi+4TCjFvTjmLm DputKtqdOVRkchv2/OruS8pJHdIw9Y236GvV4/lccn5T2tyrCuG19lOj417tQ1eCFiU5ruwqHFf6 osPWuJqFT0kABIFh/W84baUslUefGBuNV8NnpVl4OczzgTw4n8LSQBqJHsFJw0rOJIr3nn4wlT7q 2VA53PwsJYAYCiEqPvsxA9YasAzf/E/8+8K66Gq1GWVtPvfidKNQdGRRRki3GEiunoYAhvlsQgtP 132eU8rXSRsHYToV+nfK0Z9ZKHCBZJBNKyWCV8xBjD5/jMtq1OieVn3uOidkQPrT4gOgvriFnp7j p3hTKIyuTqLfEuem1/oFEHZQhMmFH9+Az1zo+CTLPiEb+Pai8E5cPb5wj3yoiPNrV6pYt01kI2fT WlNMmRVVUHowKTFTEXMI1gvIiw1Ziidlraj9dj8T+7+QI0OH80YKJbffC28hLusqLQ/ZJ79D+u69 VnzJ6/5hXxZ6QsKYPTCR99945j/vkfCex7crcCP96IKekhi70MVZJLZrzY9ki7Qhc26Iuxn1I/dI zoveeGu2zwQ5FXroe/yjsrwZtwDtpoiI1/9+gpS9vvdjkuSv9tgcogy64YVFVWbsSd1po3JPDAb8 H/p2Ham+nkySMJtZTU/ZfhbTINFw+TGDrJPuRgUC+SR8oYl3IiViAztGI8lTw4+lT3ZjTLLKNS6s hUdUKit94rY4PNaA8yLmQnIj4q+ZhJJjgObOIqbklFGjeuXnLP2nBaCCSTNcQqinJzo5PqkLvG2/ dWqUN5Ip8HvJWaIYxJz59ov6YRQkdJeQnSg91ifqtjAO8raxfY/jggHHTkSwIj6Zx5XS2AwbCbR4 AnY3JAbYVVk19+us3nBeg9ebCe7Jc2rXPUS54CfdsB8dcUzT5qk4fycupVSldo7/FZrUrGTfqxQ9 yWdUtrWMNLSdBUHlr95Jpj8EGw26MeXoab/MuFwMXNdUj5nZ7EO/z+uzyQEn6jN2Po1+V3sFJsbG KoQethSiaJGZVVQ4Qb0xbU33hglVOgN/TJH8rKXZlp5dBQ+g6OSanzjkPc5wRjZ+cOROviT5APAa XWkVSIZCvtNvwTKWFBUN8vw24YWR3Lv3JVysSG5zb+BM9QVmsWql+DOQVnaczbmkSuTR2do6eqdD OmBnamYcxiBeAt5zkwTrrPqJEFRm7K2BpZoUCQ8EXRyi1o6bu8hO60IsNbGC6WqbyVkpJi9K86oW +PWOmUCQNd4onXZ7bI/CSC+OFxL5cILJx+CkpjihjX9S2zh77LEys3DXJW0Wx4lGLhBRMNaG84Xe bV4AOBUyUH0/MBJ0q/fhaAwfJyOlQjRan/qMyImBlZgbZNC737pbRKvRWn0pvVTq3+RfjFdNM6nM DrrZI+jm4H2rAPl1EkRKntHfRAhIqypeaMhxCY4NQZWV4VHn4/Humc1uw4Mtzs0lh0Nhch/m8Ocd 2oZZ2Skl5NYm0DpXWIoRnADP2pL+kvN56YNI9rDEXR5gQwaagL8e/RVQapNoMfr34Jp732ibio4l ShjI3QYMaI+OKH13tmyGvR5RDegphvp/i+6fQkG7J+gm0N2HKSxD1lYh9CgvMWhkdcxarr6tMxVJ zJrPAr56x+sIRl0bcwBxZe9brTq6twT/utX4t998qe1hJpjunSxlT4/AtLwWidksqS8tMikrFhfL J88tPubzEw++gyGD7hWDHHHGJXHOLVfaeBEo7aJFc3pvyrtgtGZlgwyYjE1MD5ibFzGqC1nYzNKx AsVNdyptgfLkm6T4JvlyEhK0O+0xWcJMSZpNPvsn31754WjGe4HUd160PwnbJN6BMdDEopseSyTD U6xBhLUMgUorbuEi8zRCTtUhaIqvGn5SqWlk58dMOX3wnir4qgl+pzbaVp3b95rok7kHOE3TWh1e T9vzG0H9DP0zMlXYJeKGFiFXiBEwE90q0uBrTag+nxXF44ptXer7KY7IGzQcBV1wULhpmDy7j9/N Mf+orrlkrQMLE5cD73q4pzZrsiDYPnQhEK6Fp2+d5jtgzEEFq/uxj/HwMg+uq1t7jJzQoTbHeJzj aASe15iHZGCx0Z/j94l5wfnH/17WCiEVXPmdN3SPhK3lP0d5t0RlniwtvfX5G1onk9WrtoAXpMRX LeS/TFQn2pmRpIEq2RN3EYZEaHvqOl/8Zax8Wmc0xcpJcnziiqUPUSjWtyDLLTmVaV6mdwXGjQ7T Mzt3DJ0nHZ6xly1pkZz4+Y6tsGaLwhO0VrUmeS6hXwcheNyFaOHuukc9BjnIckVald/zCxZia+zI zBPW4OFyuegfqrHbCGSVbdG9j1/2EkUUUrB84ZJzsVF1h/VMFHjQWJq1RncKGRXb6wEfysKYcV9v wJkyGappgRf0etrHfYXKZUDC+UnsEWODTQMSq4AJZdfvi4x5MhEqsYIxyme5GPRY6k78N6IOcO5z MS5AE/Qm9730rc36bC8ZFKmwucpgTBPo3jmxbyuV/8vXGgqf/47kiZcZ3hbxDy9EaNY9p6ewhNg0 ppi4irkiIzxMumcpAE0JK9g1rRkSq6p114iy36LZS0oTPPzJRajGrzjfQzKyxfLDpY+oQruzRKNR xmxuXPsAbLqPVLP0MY6JS/m7Tb3g+A+YMJeF/YRWq1xT3nYOzpbK05IalKnBBG8xeAWBIMLSuZ21 MqmJLXg/MPDfAOe5lEdOt/Vg6yEQ7Ncc8dhrCzqJglk8qOm1S778VZ9KhZYoNWTjvvNW/UjwjtWT dx58clIjDrCwqwH+RsieavDwY968KHN/Dtsq6BAB4THAnl/QfGwoYqa5fqhhrlPRoRh+TGpPcQ8Q CaHsLqQrZHEN7A0aYjZd7uSBGyOUTWP07AHZ/+l2DYZyHBdLNUuQgMYiH5m7RiTpwN66Hzo9Si08 TMkv7TZJ5+WIGSgvPKKupjVyZpvdGctjy2o/RdcdsFzyx0g/uWZ7QbhKv7e70xnuldEnHHZ8UgKv 9OSTmvoM2kBHz6QqcQ6THwHHYfZjcsswbk/QPF28T9MOWbgW9bR7aYfKmnjI8C7+E/ojoapiMX9h 87Q/EZn0YG/tF9nDxFq+TogS9osDZB7ZO+TbMcEH+tQbbZE68HsThowRPNDgTlnZsJPm5HWaA9EG ZEgFWfwxZfXZYENQC4jMJaAwpS3vq9uO53g6whJsgaABgElauN1etP01Nsh9qXW2h2bSL6SG/v8j I2fcg6fWpC+hU7KYtyip+in64onqQKJWxTgJFbtClCDk0qge4gnWV+Zc8WIbCkAcheUNFIfqlJz9 MfBYD2678RVN0/cNlwMNQjxuvTpvz6wGa05rkEuTaFeydT57IJxN+4dyEW9WJvR10neY2LO8gpkH nXCsJoV0r5Gszrn2GenUx06mvTKaJP9mB4LH9zNVPg5iLw3GbzOoCUYwXudrxmCmjjAhFd3G42Oq TUd3bSwze8Xc5c5TxCKVGqc/pxKmN0C8q8+sVa/TJ3LphfIZ0ytjAscGhCKtF+f7mKnpd/Zc2ijI yhAGXoz39XiHhfKDPz0PuTnnuUk3CRG2eQTNdLKLR3VxIc4V1Fl4CaDHu6nzmfA1DGMrXHOjfaJJ fKlzkGVe6vn0DOFbjIhO2YEGvd7dWKU+7HdZDcgljue8VaNnwP4BwAXk6xzy4OfI7w8iK87M28hV hToqvVx0J8zQbFsk4a4x5ci9gGCxez7Lw8jJ0ogxhd7NzWpXeH7gTnEQxpthRx6eKRgllY5TNvd0 Yk5eMrDC5NUVgYyk1TCJnMOBQLMrkUZcj+x7hJjv9XtAWHHnWgCE2G6H35MRi1Tum1nICUwERyC4 7YynluaYYPCwT7hbioxrQEZJ0NwPn2YV6Sm73nbKB00cWaR3lvSnbpor7dqV3U+Ow3WMc3G0OPcq HZjURhP5nnjfULsRVqbD9ajVtwyj2CfWl24skcVHbC/KrbtKCwIl0vv+OiKsfpVGkzAZtZHVJUzm O6gZK/7yleOjIinbpPhXR/YGv7jaPsp6qbhqXG7mAlE59uZDNWzjS9xqTAOXtOJN91eYcDAmXXX6 SYRTaz8UVaX2epkaJr8SCCj5LrqqXn4SZXdZhYsHrMI7GKidWQjVcS+qsMz/fENMkEbtdPFU8PQv pIok7MmMmzJ9bra7OrHTkjT1YW8S0MS1zTgdreyW6eWjq/GYTRm2XXVj6YBUhmcxOJetare4whCT lduSK+In3sPosAE9164s1gbRm245ogCSliuuMo8DKQ/3dukLl9CJ1PUCCUa1GPsb3GxcS48eClwj GoqXRdYy4eQSHqV9rTRdTTlVDI0csOX23XCqhipJE9zvM4kAHHIxSrJUulgoRXREBvVLPPm4Ni+1 Hg2JHphOs/M5JTCcWIQzgjJXxvFRNrGlC7miJVN9Wf3ahkeh4g2QhSEoDJbief396+/Rzrkg1+uW +GISeB/kHYZ/ZpB/9YUJlByu5v+p2aTpswn0XidDJT9TWaX6n/GBFLKPLfCFD9f/mThY0Bi4m+Z4 8f8zpttCHcNdbJmK3Pbr/M4uc9W4c2j0Ew9nstJTY5TbaV1HRqk35RhY94+8epzoy/d7Bss2ekmF 6dw18pXCIIiKAt271nzZfSPiRj53d1saVtJikEgZxRYsO/0vM/lslZWWa13yv0KlCDFIkZ0Q4chm T9uvUAUm+LaU72UfwTybud4rEsoOmUge8LTxXv9SdGrBFnMy5jZGkuLM7U9n990YXuLbcNrCSfHL rZrZDm8o9P9c668+m6DYdKLK4x+dMowpSnUgu+AUAzKtFooQy4ExGzBOy/MzMmVVy9ChPyPc8Mgf PaFACYOD16eq0rRV/PNgVdjgfte15bSppkZMHmBieFpkgtqqwmk2pX77u/vPqChO4Nao1jL7RBlD mNXeI8EPGmqhJhU0W/Vz2A8YNnTI/+jJ6MZSJ2SW1a8LVjg3W2z8GozTSxLIXFvOQWhC9nQfsdp9 hbVZ08mEHAOjFaMWL9LsfBGbSCEdDEUrY2ecLaACrtY1OTAsc3wmJ38zx7dyvPcN8tGW+2c3sked mJT/+NzNZTSd+QzIMmQ61ly4ofaStPOoxEtaNvmSnCkwNg4sdjb0eWnTWIMaDpRGe0gDG9GRpgUT qtpi0ARpKlSH6YEDOkXjXdh9FY1pi5MDyFrwvg0qV0HRDpuOLY7NgAH4YcDmTxjeprcb/85FZ0G8 QNTGZ3o+w/4vnLK+mCJZlpRplfZwPzWdO4MbEy3Kmifl94sqIfYGLU9ITHUpVvyXTfOuw7EJiFgr +rSrBkcv3jW7MCMFN4PF09q2XnCkGGXAeA4tdtyaxTvbnSQSdHCoP70uIrf97NnVDVX9codkVIf/ WhBk3VxOfrRFWXNJEiMoY1qkb5pLBhrYVUFalv2bZ14tbCgukLoJwlptE+rdAlmrajtD8ULa79dU fMXcaTZNuZtvrmbDK9HXFzKpYv9oyyHoWlmVZ9WgEbi9EBJvRcG/uZeU3N5y+hr8jR/FvDyKhcDx +FmZMqWNW6Xm0iA86FCdIffTEEunSCPQAGNyHsY8JaLrHiQG1cwYpIi60buAlqO3lssnNqGMIplZ xKC1cCoYOMnNLJtf+L8F5Cfzo3eR4I6MYPHT8QzSKszbPSJX9M124QnainPFjB6s8GNqibGO7n5s y+43YUJhucUhbYWOM4sTOSkkUPJ9ICrrrhSkd9th8Iunwn//pxHS1rMI/gi4qbyxfqy4+ejq552C 3e7EDbpaPdynXgqQ72TeNcei8lmeHqM9ynpH2iOlfKBk+u8gNYwikLGM4kLRetT3i2SRd/8w1sxU 81gH9yoqWB5mXKQShoNc3VfhmuDzK+L7k2KSdCIovPge5anihYYtjXwIhUGMO8xXz9qmE2VXXCEm 8KJqhAKEAtMROVQ2OGrkC8HEZG7S2YIzrspwia2oRhYabmpGGpqcsMHsox2GFDGsEJhh2z0TGj/3 1+zfYWlChEwxAxLcYGBjFl54VynnhmdrOqp+M0shCLtTqE0GEZvAs7FCNEGJHP6p4amxfI+mQS58 mYaFrVprEPuhGFL143nK8bCeGV7I1HsdO5fkmu/EZsMOKJ/cHNMXNrr7pKLWeT0VcBb6Bqod4fxF K/mK0e6D1CAeBIavp0cWJhpx+FFaLEYgiJrrCFZbd5tRNaEkPcZPwJdCmQufUbKWSIhDdisagi6e hpym2q5XbBnvDNMW807IbkwEEsp6NB46wqfY8ofZwklFvjcXHEcIAxOLvgbryZYiOyqe0au3g/Y8 KS4TNrOZTW3jJxh40+o8P2QOG0dxFL3jIfCW2nkYVOLs6a+f8uwFw7/KptT9qP9QXRbYiV3M6OT2 J3m80UaJtREVIe6Mk+DD1dScXUdf4jbAXb4bWj0IimIil6LB3KGKnOoIerR+xRQBTQaYZ1jlkulI J42JalNrjxQpu6uEjDjZ05SbtD/ay9nzLu3r8LoTnUzaBNsZMufxOUZxo9A23ERh1g0bU4IeMDsW fn+pF1qftnh4pgm1X+qEb+XXwLRk7ygc+eRlbaWyxdts9yi3RUS2tiYcAGTn4fZUdkOdH/N8J/lB /YTRzkfJjF8frIsTJyrqAvThDiewiHGN4qNt4npU31fO7hEL6KwJp7PpAT5uuc58ZMVTiT9QmdFK ihgVKIIzPYdvsUoTsOBSrsVssm7YVZq1h/zVaIFVjxz7z7FUZIKYzHz/sNV2gQzvVu7VvZmER3nr V1AqEhGl75t1pT0Emkstq9Q90XNmEUWmFwschdlboPKUsIT5YN5g5kYMlXud477pgEUzj0L/26bj RBX3CkB31Mql17oz6cxkk1CiCUHlfk78timQMFJ4cCV8AS06ypIynUvvPgeQeVthdlfr1bcA186f /XbvKbykfUMPojxxl9yhs5c43v9Vkru62IWRMfcYj8B78Onf7nbh8biWecfSNPO77MYAiw/Vsdw9 CvoFM3IUg7epEjZAKZLYu4rhkUBfrI3vAWu69Ol/nxy6NWtwKY0pf9sRKZ6EwGWAEBjPdniI1C1s 8gPmshHYUgpZg4O0Fogmlincq5ZWMAcwM/queKIj3sIL65I/c5vtYCaAlQRq/U7d9iMh6+eMuP1O 4pAHuFup+4ttYwll3AZt2fts3FM5IGKjEHYH/TddCCUB2hW46dV+2M8u24KTmryxDeeFjlPc/NkT FwhF7kpqX6r2VCMhxawwWR9qTky5cKcSO+A9l+02cPkjzXmKiXP5gCyOyX7/3qViYS1AsNS3I8oV nnPab1BHfMZbb10ue6CO6mikaPT5SILNkEvCYCRLGk//loH1Oj7t4UAXgqk2WMjXZHK2A4NuBRFb r+4ZhsVt6KFTp/SL0veNyLSNhsH/2o9DvV9UJHZqIL8gRMx2LhP3aA6vfdFHpFX1OvwFoqD/jT9N 0olf7so+b1B//8Jaqg4cKwQ9rDIYTzeYvSBGynj3op1Y20S2u9CzIptJRFTC3AqpnkNfSCZs1uvD C6ErN6h2AkdkbVbHkAyESCRzs1ucrRXixW/YAopECbYSHfLJOOypfr7612K33RkRrPUu67Iffo7B 7zhDDsKmn91C7rWwL34KCpc/N/aCbwXg6HjRzIzV1Vq4TbhrDkca3fAFtAdZInvQUt1i2zKepAUo yNX5rD8stcgfLh5QessxkBf0HIjyXkF7xFbRS9lvOVlvvqurTayyctpmbfCrVE7KxhhOA6IweAoT CIDMg/W0nlMdkqkcAb0+f7pjzo94n3AKp1iOKoeCPzNU0kCO+FY8VmV7BnfNDtPcxYMumwH+NEmL oa42+CEFxG0f30K3FzkwEDJ8pXJNRuOp+YZqhT3LBYNhoKJ/R/RfKSE2zmZw3PhxEebimOIPAUvh B/7i/MPNsflFu6RpL5+DX2r/1gUVqa94J1hSgDGCO7AfFtcEhlF0FzKvD9zcS6UCPDkbMim3c/6M OXSCk+4knv/XYXg8WNaEnZmnV3ekJvj9tk9M6jVQhHjPVJz8iKtTYMOmMW6TGPj3KF7hgImg9fY0 xqeXRCIcdZc1vuGQTCeekBbMYR5Z12ipZmQ322xPNxNnfzQwuD9p2ZuAehGmeI0AJlH7YIy0tVke 2yHlFZPSAHNAbxLAz0sf1mVuQpwFaZk8E7ZEHHXNiQN4h0AXHSZ2DGWPnCzf3OXbBjhL0lF1JNle L/LnjzKbJG/2H6iQriRl6tNB6DrLUdmCSSUuj+LDelQg4d/9hkilgFs8rxb+ozWn0ggjDdRAQkEl oo2d3o5OWZkv1ngAa3yqIsmZswbaGLzLOh6sGOTZjQEsTjRKrBuyIpYYAPEL3QxYsbzzl1I4CzWr 5NaV1Pg8rUNR8aYbAnvTcg/0UXTP5v8FwcaEmJPGxRKTGNE9dTaZXyvVnLOb5ock7oYr29LHyCNZ 67GN8Penk/KObj1E3ZMfiR5oama3Q3ilnh6jB4E06GeDDJXm8t7BReO39cPtMJdohCMq0YWYt+NN Vm4yufVvgCq0lEdMityN1+OxCekKiuvHhd1+VSf7nZUOpHpL52XmGhYd5YOor5Npkn/sMa3406tV 4gnaGLYBst7GpEpYb2mos8XSqmPc0PFTbCDI2RRunv4He8rq3sQ3PcxxIkGK5ivKZDbypD1n4Or6 fB1+nerAZ/Bigi7Mu00pX6d5HZiUfVT/qXhvNYGXG9Sx4ITgm7w7xc84YOUPA9N3cZhi1JRlH4Uq NJi+XHcKR6n2t1Ayk2KWHuAy6QQToQvpi1GJ990eaNTfS2v258HxnefA2AYsWTf52uk7it+C1bD3 Xigk3vrJlwPVwi2W32pbnYUqZvKIUj/MQg8ufDX4Clg4OFys0u001aLR+moORCBU1S7hUxdmT1f8 +3xk06rlMvXzuOXxkjIddCkRPYDpBrIOWaVFYktOn/fE2edsIPSKkz88lW/RYSqZpDMbZ1hxVItK 2RbZu+18O2zBkzYgbrYTAFETCNLxA/ce2b1KPuT6OGunzfbHTY1EUnQIuDLZiimL6jIcDkrcQ6uC 1r+4vKy7Atbgqadn/OcWHIJKy3XCa4NoKIdtj1SKNVNSdHfREIiXRVfQlEFkH+kO5tSgSPKjON7M MFDWZ/fzrOXVDJdU2+HN05J6pF9YIXbtDwVR2ofGyI8QjVofOiFsogfNsIwCZoE/uprn7Dg2xbik w0ftQMueOIo9YlHFJEms52N2vVedHHCsXGwteZ8zkcI8ng4KwcNLuwAj0vczD+AbQ36OsV67861u jhIsbhRpaj3wP+7NuXigrI942QHFFR64vY1pvSr9kdsQmdw18WiCmaGX3ewdezOkZidAmZ3Ac1Z0 CDeM2bEkStGPV8hppeOr78dKQMcDscm9eD1fkORabZC7h27Mfy45uxRHvb36qWhGU7FqQi+//nu1 ZsM/pkivAvp4/QDrnCSH4CGD00ZmLHm0M3b4hDlUySUBoAguRvktnDB1g+sLq4nZI0kE00AolAN/ 7HCQbBpuvkZ3KPz5jzfqmj+Ir1peVSgboj7bn49bI0QVx6boNIeryp/MxyWvRFQFksf3Ycum9k+T ew2CPu0OLWkZvh8F3iEisomKAHO3uhN7Bg8L81flF9CcROf26pm6a+u0ZyuGgHLmO8BjZ7qEyH0F B7NYTjuSRKST3gLRmWavwilgFzYlyhLN/iowlEu/R5c1K7lXyAJ8ZWD2pEk8B1ctlvEhlEjbJO7l Dda8NwSl0JSf1dgO35QEMMypP0ow0dPYJurJttdb3TmwjZTEwli0AfREO9DkYrJYVcBipc0eotMd UCMhE8cr4P4uH4+lWbmRGoKag04ZVj3r6ZkLw0TV6XGdWY0ySkLnJVv/CXG2Jn3bIGlf77JyfFUv PjqSUMZ81kc5bsZsyxnRrJZ07fc0RSZD/f5LzAZF+6hQ0nXOhyDtXOI1KEwOV68aRgrl3l88BWpX x4zEieUyjeNsDznrwjdbsQvdoPaZqR8OUw7qWGSc0ZdkKK/d9/1piZoRVNyEgh9IVoE8n4lCYktv RLLVXA27zmrGw2GdBfcL8aftqVz4JaYjih1Zs5qGIbs4gr6P7hHTpXFOUHttHmBwAcgZSi6+kyiX T+bZCgmRd/hD/qFu5M/CHZvsdVr2I4aq0WBrYDaer6PZ+4P0E5T2+5jGKuIFwAQet/anuvDogGHL ylTs9jOYpD8kdTQsD37KuT0gMkDebCaRV5IIw21QoLXf75kYDRmx2xqENe6esK/szDKUtbAXJ+L1 f5kJgCnt7FFthYQT/IpcNd99JhG5BOznPuQZ0gG90k93eyJUiIQWni6/INDhUO8McQy4WFHjgYla UC19d2m+gegTUJq1tP0LoXI2B6bNtlURqoBtDTxXX3jQ+KS0WzkUFa5KAnkw1AZaCeKnIowC740R zdHIoGxrMvbaS8apLeuz9peshR30KhyQmnL0sHvT3RWoaFZgabl6jEq5isE4YEMLP+EVWvZEhkE3 htNtrrwXDbbblZ2hy1BHiepCochagoz+ZcYeG9cNcmlK8odN/F+MnVVgsWmSOM2MVEBJlu6GiMX1 Zct009KFekdUGLz1XKC4KE9JJ1Uf2FfIh283Ds20V+uCMF6jt3cQwYUwdzf9AAiWg6CbxKK7AuI2 qhP8WpohaPvBJ6FfZ1pSini3y+EL6w/1hEEikJtM/IKW9/nwcLQWTTZq8nDNxhmZHATkg45TaAtS Cp+YjkCsCdKuZ3NmDPQgP/XuV/5ABqAdr4/kP0KxmzcyqbEY/ty1Ox88XbTtizmVxohp591lWG/q yKcMMyRmgROg8r/3kDOFUYO07JjVECVyRcmsvH+ArHN+M+AY1XeG4c0diKKLFjmDqlyyXLttm+Zl OyMUwzaP+zp+CQ03VBkDV+HlQhUKYcimSN7IAvfCbEps8pj+nArOH5v2GhyXDOp9dzpw0+eq1dei rEMNJNDq8qKNPd4AvPbyp4fK0E8Wdoy//fQltEKp85TmK85teur08kjrgEldeG3hwj2WDiAru8xo G0NvQVmEyofL+IV969A/eyvDms7y7ZBdcrhLYTo7OWNHnagbsOlbnWgi8HBJ9Sc4sEii6jdEvwT0 QdMhEd/50IXpB1M60U8/XEarei2O+A6lj2WKD8Z5VVjOxFBtmHaBRkFfrs80Kgii4Ez8Y5PJi7uk fLE6cFPQ5D8FCvt4U3r4JsFtftMofxZyg5lYPcSIeGSMh+koeqznk5SrGbY8SP3EhoNrB4a9R5/U a4sKPSHd+XbpOwvyVmvSmNm2cncbcsCok21O/VIyosCoBFsvteORkH22HeNZiZvMFPCiv88TyuMM PqCV6PY2ydzYL+m+5X4cZexFKy3s4WN8FqxIkpr850Em+xyl3o1joqVdDdlbke4PEgNJG7CPQFLU OAVGLV+UsRt4Xm52hhW+jvbfww5/YDXvWWzY+n7fKczrQgEzl91/iC2C5ndYgVyUz1Pb6PBW8EZg XMJ+p95G9sPCST8FK3Lwrk57xVfWNVDgowdG0ndan10mqLNCgFyDumZULsgcp4n7LkksO7ZrZkWb UacW3UyiPifaPT09Z1+3TT/IlqOzWBT7j/0sGJuPlsmr8LD4z7Nxbo2QfJg/i+PPL9Hj+73D5sRM DbOMO1igz3fwVmSveGwFUghbMpSFuCHO1i9bB7V62X8E2eqjkIgK6d3RtJ9TvcUyp5dLZsA+32j/ XCMp2NRHqQL2rYMZBOc1tH0E5HIVIEbKg+Pwyt6yF4K3TkgSoiUrR+dYgP26lFPgEVmyrH5f6CaI 1S5JOVm8SBqoVe1Mo2vh8FGuuQoOQXB6GeSnT5NADyvwIHtGIuXM8JS5Zqibo8UH6XDZeL8HPWDz DqVuiXZl0BNLblokbgqOY4fzasI9v43rXISWjGdKRwpfsk8jFKk8XM5mAD2rS8K/IQzCO4lFRAOa A3XQfhhIOzVwITHqFnJqv5HR7yq+7Nk3OM8+TFKcD0lJij4c3Ddk706xTKUmdE+sdabdAfVqgVVz nusyNzGjWUFm01PFaG/iIwOdXhC4gH2rmYWGH0bLmxM30tA2D+4T+bHuvEacU8nrwXMWtBkfgqL5 qDWuLN82D0GRm4vEV+xC8+CgPC+j9d6eSVe2V0aarVfGUmir1nMj5mbGfamHRucVnnNnJ/Y9Al26 K1fnxG1M9FyjvHW0SXIfBSz9hrziFYQiCM3tXOwt/hCgdWZc/UGsCFN3eJilQBmhi+mZ+ufH82Dq huKd8HhyCNPCsU6dGj9F5xSoNgpamS2NxIptQt9MJ+A3lAcVz+vQeZiSb7DNLQL8H8jFj5lGUtPb nR6vGKIWT+KUVV05C2giKC0EdT9wTrtKEmW971cbsiL1GAVVCaxleBOuh1bBe2gFKy0cb+JkhQLZ jvhKryQZqkmhnJaUH8m7F7okYZhpwAjPPI0W+oF3dGNc/kE8D0AADExTqrvRojnA7hHKfAAFiq4B w+5nlgVsEJz7WwOZOiAEFs5yOqR2Amh6LjQacYhkS8nez26tqcE/Gs8d/VkRjKgBYiLXJ7WJrwBf rPGylic0S4RqsxsV97T1cbfgZsfv9hOUhJkRFqUg7H3QaSO5wGg6+wLv/eKME/8PA9x1H0UZxut5 w0jgaM4748UG8wamk7ZmqYTh33f0wy9iMTuogVTnoYfyppOKCf5ztxF0V/6ACk5l37KhEp5hgDNq vxoSi0NpwvocJ+ftjvryoJ39MnxxNKKBGrfSDxl8l8fhkl/I5syH7WnzC8xhVtEWDGoqCqcO+3Mi kUOA0rmK+sBhaYYlPJBNAvMn39t1bmdcv2Z7DOsMoLtWW1lSkAiW/7vIW2xLYGDYyWuL/xgUJCQl 7WKE3Yp1hg4ZOjSEMED1/bVghG0vkcWLh5SiOAX/PwMRz/4a4yu+DwP4rL7fSkWOxwXHMZkbF16W PjBMT4mb18f0e2D/XrjRtWLh4R9WHLjsNmvAKHsmIob0G0BUqbdnU7ti7KW47Ajelxxy7Hta6z3m laOJt3/6FE9e5zpZDsy7zXdo20HXq2nAISeQjE51g7J+g5hJjq8F0UOlDpf99RvWCQtNHY8Ga1XB uN6303FWtgeVRBexcE7WDbdGpiOk11fkFmU3bvGz9Qp/G4nP4YNH/UurO43iGj4v/LMqvaS4Azi0 oujyY1pMyMm8AXvHZeXtYJGu0DBLPtVOeJGHu3LZ/2SQfqDkvgX3AFffg0gkZhAaNPNluNtM8j3p M0p/HEHcZ9wdEgyO2u1h8uc/FoUNv9fPNIOJzvZbrnPuBYBrM7BFyoiEmKIz51YDP1kNByGWCzHK 7Ro0Q4tllB2PGB0qqCJjRA9uYpemGTYny7B2yAv19j2G9SEN3NdWcnIMto6iJd4Bkmzfx43UCJP4 5rtlaIiA3y2RUzA/VPLNU7W40RDVCdy+fd1XmO8d0bVFweTA7zbGMmlt/Iqraoj79fhzCxZjEJ6t GJZTlvMiteOgJh2XxdhimxGwwiXqnG/YGC1Yc5lP5go3Wlw2RNUq8swI1Owivo9s1YZhJ+FAaCJb CaUPRdK2wwNEBfoP15388iUhUUdAr1yTm1xKx/ZMjmhR+y5j3Jg2uNj8wag8AEXOkl4nc+sPQzaa VkunqfAsb1p40DD1Ljo0wa/U1s6AtQpG2KnH33DOYO23iI5jqZPVVEUWLpEPrvzOE0fKzqYaG9Fs uxrp+blPOLJoy3zirD8i1VpCH9J3NrPaMfAw3s/hXd28uTiD0APcJKWu3R4ASj+nhFf/WU/KUu3m V2TqDToZSdp73vRp3RRD2l9GHzAES/eTBSVNMDl29YVb5gGRORtgn7aG8iULTX26DJH7OGmGQKOi g7AzDGc8OGUA6yZjkVazrm0hy2bJBZHuRrU+2Ax0gjamTDtq5p6movKaq1d/1AfnFD/BeX6l+uzx ypltO315q6ngMUqph4KFmOooTGMv3kkUKQuKfLwfZ0636kW+GNoujkviN2lAOB5PtawFwxkxVh/p zdcMis8JgbCI9XOzN8gCfaKTLN5v3O2UonxshYRx+blxfmvw3b+pN+XGdAGXHec22vqIWTsvphaD 52E8S854an5tel2HN5pONs/Dt9sDvT99BN3uPq/qMWviRaB+p/UxOoKF8YuLQSuOeVlnK+HXas6l 8+hrrV3NKXXxfdqe6i1KJEkZKlr0dusCS+nd+L7MoApPFBInB6b/13LI0penA/uqEKJTXgnp5O5d dR+CMXcGWMd6izv8nPHCgudPpFoVyd0BhNpqD5UZY3Ug1TdhrEEx7Mj/ZkyADKbsWeU7NDallJ8R g3vDkmQBaVo2LPmCvdrZgbDJL9I6B2F0W6JSkyOoM3UwX5fxhHTggDfKadU/WR3bWhLSRoaf4Eyu v3Csh0hrtQOaVLSWVR2p9MZQ2iqEAddq1et+rT/vXbSIs/ACxgX3SKJp78yCL/Vza2NCicSwrwW3 lPv5+EEJ4ne41Q9m2Ye+hTSkPA+3hP2rbHQRTcoqmWUo4cYKHXl7vV+TR6Ty6zAndGS2xvecRV+N ncI48Yx0Dojf+hoPSArufx/OStllTDhIoLYxLpzSFaCvunbr48Fhyu3EmTqiLWxv1wgVWfnOFgYR C05GGLNF7Ok2IGMJT3SY+cyjeabAXxOG00e8JloNfpCm9Ckdbsc6inTVVux6siX7YeV3Wej5Css+ NWx3vpziphEgNbiTzUW3JpqdByLoii2BbYz+/QaF83CMGVdKqhcJ1kad6QhIbNe+e8VwbhobnUll +iiXt1VabmcDfFYc8z8Mx+sUlE9nIdQ7a5UUqeFvDhALT7049Z8vr2ThCP2u8C1uuDEXCX4QpS6C 1qEHJwBhaCkOVkZ7M8um09rsidsTWGYYTsbIvstk999kocFkkO1KjXduhVc1iO40foTeq7VY0M8d xxG/J1uwSd2QM4ZeZz7mgWd4IW+xZN8Sbldhlp7mok2h950A8RbnmK7/t5w74BRynMKLjl82b+0w V2dI4JLBxIeG+2V0SFzMJM2Ko7sU6iDiOmX1MhI6p2p8eRZfJXPoZiVmmWtUOq3hiQYejrgadd6P kGZRFPy9FHFgGm9ng+rHIsiezLg9C7z/+yqfWWcV2H2JHT3wVFbZaZNXrLuiHDqUGV45IxZscHNe bsfFiq3bNFq+YseOitbh8feTbQ6wbhlZIM71ZSntnDbgFlYV1dUMBftnDwuv3NS195izr1as/dT/ BoZjoiCDH7HQ5n3JLtsCmTdfSKSmuWvprJ0ElP/doWZmbdOWct1KtKoAdjMNGRcCE0XiAFuxbmqd XWXIzTX5gKwtFnWS3EpoCRx+Ikecy0+1ck+qOY/yQ7TUcCcSBaC3Qj36LgmiEX2II6dWMs5kJIje U5Tk+/KS5HaMRvAikysgyjk1givBm8ucHVf2lwOJMzdh33A2SXERxzPnUruHkYzKFLpKO+gRe27b gi1rVm/JXfCNgifcHDW6KJbUYDiU5DVCJbVx3hmvCBlzEblXvcIli7W58bG52P9kWb+T1oGoCBkx iQQHB0ny4JoNIXOymwdwY0GaozIMtsWBFCwsHaYWd9d4Ae8XoL6I4JFqqi6CZ5OJeJMNougLjwh6 VDa6SsTcaogvJygYOu2OKchfS71pECAeZQUUfIJilH0+UgBhqnv8gyiFxw7xECm/PqGvJBIsleRj 7KuZXnGIKNE6nGJL/dU94qp/BDHoq+BpnOChJv4a4obVbVHLjOQiDTBmKTo3Am3e7DXMG9VWNYTp e04GpNL1WloLGzskow6sP/T1xoPJUYARohZS0I3L0Z1pMfXh+uhG0zHcXckrPu+MVyjNYnk1SpYk zsWO7fQkojFY8KiEATiLeFz4uaYnyUYfqhFEsaRdrF64akJ7E7GcBMS6iCbwwftHadJzaNopfGZ/ Lebj3RUJT829MF5CajQC8AqNZaMVCJ7/Z37MFcoxwcYLxMvcex/0tcP+Rw0YtXv79q0nbLtNffAO dGb/a2KCVq2OgX2o0Kh0mKw/Ufd72XlLLX7dNMSdUiBy/Pz2A52dQ0rX5b4yOTQGXzdzWrXZgIPm huGlXQOZVscnj7Uil7uSFLGbeP2AGbADMBJ16NXxyfirUXWxWQSJui6GJTTUdcfY/LtnEon3EuXh 7QHihtcH+PJugXewBHTE9TW6ZmHDgEJ8hBGIpKSnAKtGVUp1rNHds57H8ekoXcGwXR02gweamt3u +RsEz/r5PWW0WorIg+Y99+z4wLLNtw49NdoiD7F47ffNfyoNlbEuxEWjgla7er96nl+BBhe/bM55 tuLqSx525Z6qB0k4FhdzT79OGL5msIsMTuy6AD2AQ4mBUfisiZXA4NaCNWPc9zTSsNkxx8NXCcNI naGqQgn1cvw4gHv9wMPNvQMlttW9nFxH2eLBSc7ctLlHDUd/1GKJ7IrYx3FBp6/NJBtGa9SqJj2a A5DOwvSt0rw/IZDy1sVvhyjlGRos2hgav6hwBfE9ihNmu2EN8pIp3bCdv2xKDNxwe0No0CYZjVxI 7I4+BZCMxrYC2Tq9Pj/dwE3XK1jXkqzcc7UU7NdeZZUEx0oxPNnN48T5Z2RFX1+4rWQKv03OKbkt OgRrQJFP93SzRe0+O3oS04sVw6H1uh0X18BhE0Tx04Gcvvurcf+33xiC0ZJJGOACATA+HbO45NVI HQDNKKu7eHjX7kmmvilQ6XlakLt3G3gUTTdCFNsodgVXQQ8Vg3xH9/UQOuRImN0nxTILH+qenlUj 9150gdm7uPkV6kUUIeDDJ4aHIPv/QY7jMCv0Y0ds+hqSUlmIkzlgfOHJphIOi1fzfWim7QYuRjjZ g6Wy70fop/FCLE8BntxT20JteGm/U5enWidYxtBa9HYhGcsXd/mN1kDVPuj6iutP84joTMOVgwuP 2XA+BkquVgvggxz4Gw5SpUZvFdzWzQKfxgbwwyBXnCp0nqqOI7HmYgO18wa3pHOpI7Nqv/sOxtxH 9/u4Cb8jqgKbG4BX4iqo/kpUNqNKtsPa5aKzSs+KYjG2EDZR2SsIoqTD2jqmH4z5NBGVzNp7gxYq Vje8sklphr/Ygbv+PVXxhZq7PNZNhvtwcjp27CyeobwaEd8B4EZSL5T8iTF+DCkKbNNd5Mg6FJks tPuC45KI0PGvBpzthG9txky9FIavAHDAf3+iiRooY46D/9wtm2xbOAHEjcj7qb2blsGjofT/JCxF dUcuX7S/HRMvcIzK6EXN9dnyiZF0Dao3oFffoiNpjhu7eRgHMJ67sC5AyGIjwJJ98c0a+OwveRGQ GK7KPZCQeHlRCj5ovJsUEQPEEt8HKaI46GYgBcWYNmtkrNUrrdDmIBX947pWkvVrtW3oiyLwmtRt XzwgvjPLdzLLIxfqtqZ6rGiyMAqfK+P3BQW/Yctko132KNdK+bjUnvCTi6lABDO9EJr8Jlj9CPU8 +ZKtXRy0Yshn84aGfQC7jiKBxgMlojQ7QHKZ18gvm+rqkqc8vB8/kiWnhLLGA7jiboE9xTLszQOD 5N1j0hAVL/QrkBZuaBtPAb7xx3IJrjHSITxrkFF1/xRDBC/VjkcBm+NsXbbRjT99tzJN+2WtDC9l QPELCKWsSc9oifwGOUST0B7Z4RCZp001oZNtzJUXcuTL9ub50j8u7xYFoJNxXF9eH71t9tsMuw/B 9QfloKhVe8JkyTClirdBqBMyr3k+TxHcb677bi2yCyIy9HHVTEgqtl67rrfkNG9nUWr2GmAWl7n8 TtkdVlAoRNnz9DxnyGrkT5w6XBrUD5GsAtmFahq49++ANKsPrXp6IAmeHpNWO806YP9Yz/DdGbWn 1jqMcgd8EX46PXTlUTflkOq9+/MLeam3dDv9v/35UrdCKDMoQA+HY+AGdB2VElxUeCwesX82NfWG P8r9/Y32mQ6dybqjs839VOH1AOKrazN1jIm1+dPjCanfXkziLCJsIw/HhUcdCRvRlB4y8flBeTxM knqP3gL8Rssvb+n4toW+IzN+oPsURlqm6UYNrjvpadnrpTrb0L3FDZiwa7v3sHc3FitTJQSkEhNu oPyi22Fq4O9kqwmsyTGok4XP9I0jT7UDQWjZ3tmf+vOeLD0kNvCg2Pdp58ho9L7YNsektMkQRZaL ds6oFPB7rgNliNQUqrCiRNP/igk4tUyFeRw1vLVzsqhsRptpQFc7Iv1B5Lf1LVFi0fv0D9JGTDOv ArCYrE+piv1DRH0k+bnARrnaUQ2VRFsnwJLEyKNe/kWQoYR4YtDjJs9R+dZaQzJ7U20fboNdKzul WhMNCUjSa+osMaoywqd6OBgfo4KFhpnrqeiV2EFl0cGkRPwTDkCTtcPXjxGfCAE/Gt086ni46MYR fOY7A4XMrv9cdNh9DctpCosvvxx7W9rHNncnMFevYfelj1NfgmqnLcs8ykr0UeoeXULaKcXvb+ub nt98KEKu8NDOCFmr/2iFkgkGFxyEA0ZeMi6hOAUMjTHsbPghjOLdJDZVAPzvUqv2uqp9hPMmPV46 QZfwIyQ90Ktef/RJMzKez1GtHKvoeDEbfkbgzxmmmBrYfi7EvSQziG1kjZKvZbamuX+ROthFHow2 gMR618uqwwEex2HbitCCyQZSD1TZiexGuAMnLesjQsFFuQyEShrryoWMlkc9O0tD6RvlNTBPu2BB vsVKTrJlwYYH4NN1PiRcEtaKQ2DqzmjAcJcB39mSvYtzv+KxYHfKqSOpVbIULYpjQI6JEJhYwrUH rr3o2q09UAE7h0V3EBoK3WvVKAquRJ1Ex82cujbNyQD43HdMWrjcfNAgxBTDo18BcNPRVMySb0Qu I9Cn3exw42LnPupBM7qlGn/sE5gLtru12sdNLapPozQjO7MAj10kfx0zGtO/mn0boNc+dZgEwWdN kPuks0tazpMklPs4/vtaf8R/ceydT9odMXwOSxMX0N2v1YCAdXo5empax8h4es4Y+FL0wGnrP2Tt Dr0yfYde4lzuYBtQIRO+E+5mxnL37xVh4wUCBpF/KoR2CpnSQxUjol+MbizKe2CgU4Lr0L8fQpA2 C7v3i/IhIbRv8EJAUjSash8kqEDX1Zd0gvHflxnGDl+p5TzLANFZ2OwbCqrXmOgOk5GMOJZWZ2sz YtRj2Mi3e3YCH9y0MYDZW+1W+iPxVA8vXn4GqbuRV+yHEj3Feui2p5MtIGn6T4MTXa45AhyqAPMc P2Cf+4FCwSabqZLjaZ2frymBSD3jnqz12e6+IVX0n5TxB9xgAnhT+0CrP+xccBRbEuyZKni67Os7 hqn6UF+nhGSWd/kWjh04+pcXzpSqjaZSE/VRb0QYcKZSrn1SeDRDS6M6T44sA3ZI6AoUmCzLiEIc 2esEy8T1//VLYC1O13851iaEVyZyMEm9Qe/TNmZO8cM3OLkJwz9ZDA2SnDrTEaq7ty9RjDSR+o21 5NC5B/bYsfGixJ4Vzl3qkQ/s1jBtb2b9fSBtFgusVyUzWykGROZMd+ZBbhaEerlCgLya+DBTzUXf QLK+n8L0lXnJa7ZsvAYPLIIvSYMBR+cq/LI1LjAPdMaqvkUXNBQjOoceUo3DzkKqTNuAWPy+eYZo /o6bS8GppssVnB23xEfDAsuuy1A9xCvUjErNqxQh/jzPt5DnC+ifGnXVFSE/iLiXNAd6/dMAJDMe +N7xL9ytrwivuYBbJOLsJr1Bhi2gEHDv9SWI1hmM6WmuOVGJtV08p1pVg3jmNXrrZhLoTi8Y+oLh dQ5b2qCicBhshCrQu/zvHF6wNzYp6tTFMGHIiuVWwIdldcOdQSoq1Zt1U0pP7e2EW2X54RBVYVOH fkRg45yKRzNprDWzTj/fem8gEPvTXZZuF+A26itbM0m8i7vn2sQtSHC4XeDYk1OMuC3FI/P9JXHQ 2lFdJTxdbMQhmBtir0gFTF9xfy0pN1uC1KOLmJHLNcGqTOhQBUNoPg23mcyZkQ6AGpwrLHfGBhzz HKW+JfREpwg09N010PQ31ePwxDCtcyyBI1Vzrd4NBk1VStl5ZDV8EEppvD/C9kKfmWNJ9P4TnIXO vGBjJ+hPHlIhkHRNVrLcnc3fUg+bceZC9p8eTJV1y6LhMsNs7qKU4/yJunkCLJoyWiDdd1ghNhCY DJiKyZFGgeeOZkwemEbAU7cYBsnvUSw9ioVzPqZ2oJj+Maa3XXPppIbgmtRRI2YRHEf64PNy0Esx fGgcdLn//mM7eGczDRE0v51KmktetQEIHJq4Qfye3PIJ+Jz1ERwvfi/Xtk8f7bVcz3RbmER7XtQ3 2vP++H29Rwm8pv6LCP2YuwSSuBBEqay+6t8ZEUJ3gnVYjKGQ8RxzKjFrnwomBTVrDfN+6OUj3Od4 1MUPXvVh7aEbw0RvdYYkDBV65vfRgbvinnQ+6iAGdnMDmKirltaTYDZrCddBhL/dpGUAQNrd2+WM iD/2IgfVCYPlThZwu+dSJshzdDW2HpPLHXOelp+fNkG0KcnqFkTOg/TbeTnZmOFASK4j1EmTJh4P UMIsliNG5nhcJNLw6AL8tBE5VHfrFPCZgVFPwc9Dw/P88vty1OOrE1w/fEFtScRNZedrGGuT4HgS Y61jUES1zvKyi/mfeWa5zcreH6r5tyG5q9zOkswghvrvx3TssezwcLl+dzfWmsOD0a8Sp3XszPfx KWSvWk1LGxf0GgGHqVcFhxzCTCEIMrjs3WfpVyaAoHvNwgdB9BO4Zm6ex5ng8j1TzagQRJ76ribt byF9lGBpSaG5Eg1v9nJ0jJnzPiU2vdoYttRjj//CdFzmvKIVqft7V5zf0d6Nfvk70w5jhLRcTser XC/WVPne0b7BO+qapT0PPiMRN+at+JnFPvuYyA582tV2r6vKZrRmQe9hXw8NWepojBnPsGQDP2mQ w5XaccB6SiOgOoksnHf9BuzyNBGAfTSUC4e3ifbsHPb65J8+HjPXnhUmoL0Bcc39CPzvPJzAhWh6 tiE4f/py4eNaydjHQ14vc/gSGpSI3zy+V1gPlmy4mdsbVxnDzMFtZ6mwBSE2E21r+IYdkJhSC0iv aVBhZbWf9M9Iqbs5sPCeSWxhUZdOjZWVUCW7T3zF/HreKvR+U1Gd/rKInTfoAeC6BUyl/bG5vsm6 u+XpdjJZGfYIYVvxxvsmoyhKPehktJuQePfvWYDq3IxgY1yUd8zXknH71m5TykICwmgZmePKKfER zyrzMb+O3dln6K79MxE1357T+jysA58fYtoo3fDUYsUQE6eKVtxXU2iSl9AUpZAMYmcfYJeyinsN h/2QQSqLkyXy23LnINy2rKvvTxjws0Z/O0WxvZKFYKcIycXKMjscG2IyZDZf/HZ1BF61iNpOHql4 n5taCj39DBTX/wKN0CRhe3of7P8nB1HJU2ZSoGP/6YXknhplzttUr9itXi81FFkY1vLB/3i9CaXl ujNUdoXCGIQC8L217+lnRHGROOCVpIXxLPfqnmhSJBb1g4Qu/0gyO4IvJTVLv7p/mPdFttiKpy1f ieL9e7/sxtSJJ2+EIBoaD01zcM4PQ3KyKPZCY40x1ZNwHYMKTaxxo8sJD2sZZQhkYzdNGtUvdTIi HKuYIVm2lQnjno/Tpe0KO9sq721gfyysWP3ujQkID+6CBWN8sCFG9Vteccc6ksAQzBcCQvEPXPKn ZFLtgDzr40g8qQ+H+KKZfYr5JDtInRZfSlkdCin4xewBaYmLEBTRfeiTC90xPBymjGJiAbu0ntn8 df7vCFPa4lnj2ZIG/zyJ50082pltSRYmw4jtBgNxNKwKBtwPrlu8mYoFFyIud+q8InUh9GWOuU5Y JFW7Ykzj4jBasfncXabJYmHDxWYoUuh8ODZUrox2IKtn2jFVWWlbm+wvpy4XGzz47MXh80Mv0+rn 9WqqXTrMWs3Zb0CF7yLGKGSAezisMLbKWgKjVo57Mb6G6dQxKPDjvu3vlWmuy1eGxXJqeROQKydo s/iv3+18yQl7EFhAbWEGpzTgZtObyOD5bboA7l1LFWO8sPo2pmUefb44mRaY+uKBZtNoGywRJ9x2 uQdnTvjTBtWtac3MjPSA/1oLuwC2m8/bpuj56Lv2tXbL7bnfTjRjsWuuLUSH1kcgKuwZWVsDADsr x2+0kLPv6OIqqOrzZ3g75lh0FJT673yfXbEbWb/aZeeov0Jy+mn26PP8hkQIuWKfPsNQ/mdjMfYu hzevxb9v3f6vJS1SgYl+cViosSyhOFlNsRjPEH235EiM2Vy6S2zodA0aVqejWqpnYwFbAj1tHBmt I/kX7sV34q3Zr+UapI1yFMr8rkpsfO7yPjz9Pop9i67tDpldZ/PShBjJrRBME4b6a6WCRiAAksEP AjSuopLJFwC0a/TiuQ/QcJIqm0AjjiMTmNyIhym+RYISyU4eGNHwzJ2sCxWAwkf23mc0BMIDIXgV ilBKwzfNg+W5+UigLHlLhbfxL1n9VsU2QqB2/znRqKr4Gu8kYzW+mXK6etQmWfZFe3AzKyB9snP8 sDwEM0IjBkI9RAHPpkn1LBbbHRX06bKWtewaLh4dPo3UjAAZepPSVM46i6YaFg0DHhAMLlxExbFW oYkUyVl0vXTSWWI2yI5vWcdgW75QfLhV8JgzH/adYpaDS0L86uPvtAK6N77YOXToJWlwjMerX4jF D5Oo29cpMJ/U4y/YNHhZBqjPmjWsO7G3tnPcAHhOv44mFHD3hq1x6bLxy1UnLDbuV655AKsH3cNq Fe+sAStekd5PID1eUh8Kuq/KPedyON7Iy79YB9zPJYnr+IZ6GAE/bRA+dtc/OcCh9WMVsSeUIbQg Zqq/4VfTIjcCIK0Q1HT2rVk30xe2/ej20fSBAsY8agfDNMycKAxM7131DHWgjbXXLhWhX52KwXCP kTVrYzwi8NLXsVIPrxIGrKtN1WujRPuWXUtdu+Sx7Q/9N5SAMbcAkb3AiJxx21Q64f1lr8/liNNb MoKI71ebVWxHRgTe9uIFhCa7K1L8huBmbexCdMp00/RIvzT6Z6LhMXQ6y3df87E+0Ncdv5ZqUGRk Xdr1XumCyOZwnzJTzRwC10V8lkSmh+oCg5AVAXKyyxrGygyHnnQ/rngPZRjzY8XQ3gWTHdgm+SxQ +DMsqKvAsA/v6oYe7zC2YCxMOQvEnUnrPKpHHv8A3ECz7CzgcRBwS6eMJRKiX0m+53ZyoOSWndOz cU6Qg/ztdNyDIr0F2v/GAXhw7KkBhcOYlVxdEZFMyPCLZ0rtykBkqGCEE5Wzx1mK0txrKC6oCkKS EuXMW6MxQVrqUPsCziDw5OHIlJU4E17wKgIQn0yBNvZgXQ4UYRDhdG6vVFpcl/7dn2BpwG1cphOV jbNlKevPOcNmGM7RdapyBm6icSJSobPNxhXPtW4YXtG43n9DLMHZtuwxu4kx476VUKpRtMR4tJmR l87oeo7DK6Uxm+0LY024AcJsID+0a/Z4RioAkc818J2PnylTYSGefdIjj+Zl8ua7xuq5Cbn8p/rv xupXd0FrTVQu/gYh/4GkBycn63CNNyjtBrcNh8T7M5bTsB5Mia0MgfLJqAb7So5LGLp2gRP41rSe 1RE0P7wEsa9wCjdOGxyQWlvF7rN2K9xGRhwUpdoeqFePVgOq6SlFXhKdF18kjwmLq6FrVb2+T9vY e/bHTS6HmJhd+0HHd3o0FILb7iFqqcjkVZPCKH52X+iflS99hNj8McN+nfzoqlY9pbh98PkUYfHR Jmt5IG1+sv/CdcNjbz5V994vrnRcLOc2Nn4Z5uiJ0SJuBhclEyOGCtnHzg/HZjc3vKjf+6BA4ayZ UWPZwsZ8DwY5sitSgvKRYOOrJ7AwzAaMAAXoxfBwbfqHI9dcjdlhRGxkZmsC/g60ddCAKNTVe3F8 3WxLz1hsmE8rVK/arJueRDIaVqwj3yEQpmOk05wzptoflWrbkiirYCRUBhPK9YKL0FFKPIswQdwq DoIlTaE2bTtVjeIsa0enH9Z9SE2nXKpIFhNJorEl+GSxkn91muATQCcaYZ40uC/VqKLp1/nHSIjZ Uklqe5iy0xDPjzTgn2x6kscVzCTylb8r/BB/qfVwZqoCr8U0fPmXQHmuCgCcFbbqbR7I2gbjc32h 0iMX8+uqKYyOPnCU1cZzxsGUIXkxzuh+6f/1MFC5txxUGZ7Qs/iWTBv77MKnaI0jYguwkHkmL6WE 63DK6/Qb6XwIghABuoBOrUw+fuwpS4qsmF6VyLiSmjelLb/p7c7Rfp/LIlC3I2prPHge+Hfg+AnH 2dqdBqfPcVr+iCWlGLy+EDgamliMc5W/Kt9EiJfft1pRtrYdZjJrnhkghck47jR06aqqQ2JbRufY z9LdJMaJDFfxV3qRNMPuDoGhB/zLemwQ4siRYCigqpWdfVOpsZ6IiZMm+n8aRnSxNOme7u72bZJZ 2nslcpvafTti2Se4lu7Fi6pUogOq6/P7Ymc73rW1hgGCAJKKv0aduPFbfniNV3O1qM6eN1ZKvZpe WRRO2cV+h3gzQUMAkR1eLZJEdWUE9DyG1UiFNrUSUVrKy/DPlA3591BKlvqPQz6NdTmkO90jYoI1 LIBeAe9Uh0OJEjRv+xOXG/mpe81lV1PC8q0EDVZH1yeTcbq8t2vLomr+yNjDzUhbT6LUFTM14ESx 2+tASKEZK81PM4E3d0xNRkArtXfwPWtTzUYoIdTrr35dWhD/zDT6fRDRm7923ghMNFskd6WQDPxn e3MFlAyP350kta9xGXsbZuO9Sewud4lLxbfdpAf3OaFVqgpNp1ppRBXEIVqkqzGZOcHnzXP5+AWo 5uVi6tRHo3zy9hxXXyKwBmaGasXK/jOTbgbhsOCiekH9atiAVDCGubRr5p0A2xu1yGYZrqDcVk3b VlwjKPS78L1uZUKSxMds7RjMclCExr+gS4zeh6/wGIrB0WiBjwTELBpM5CglvQqa5JOrKngEyjlT Dmr0O3QM1vO4zr5bNFrc7SF0gpJS+k0HuW7q5A8zb3q8Z7CVNnvNKxN/pTQ9rz4qBQKxvihtOVF+ PlEjFTgMgjSWFUm+wgkm/lnm6Gf9NXo/BBtcp+Z+25nBAoSlfIsHDDJTkNEJqUc80QrNR+bqFgCf 7w4AQGeK4BRwj4yMGocCndnCim/vE2T4Wt4OaKWVXqFBi6UsPCSz0EIgGlj+M8AJk7ek3/TqFgm9 GosE0xdjubBmGqi5WRbv+HplEuw84m36hT6BGJJ6Vsw8VhURF1OHlkBI4Fc9md7rVV6we7DJ9Znx BHfx/xWtGdBG93Q2mIP7DPDgp4pl04UopiiJJ3Mt/cXa/qcphfsD9mzfjwO4TJZIHXPP3EFz1hpN o+2fRxRm+Xj6s1u8sT/rhrMfn0hgp/ratTcBtp9k1Yf4j4oP82p/npXD5UIuF2f4B4F/qVKYGR8h 4SYRK1W0mUbD4FwZO3BxWEZHiBp55TUnE9NGdTGBlD8q/fpmG20tCwXq/ACTQMPdVjX/MosyuTEc 6Q3utt0SsVEFHoQlwrvvbk+FzrYoIweqceXH7H3u7wz2yrb25lMfjpK0MMWlcxg6ElyC6aow2mJE T/PZIMfZPlrJyQt1OjzYXMWn2UyW4R6LG19b/BZPs2tg100W83CTmHfxRni5+smNDhOl15hcNRRJ ACylk0uGNjSoU/2KAvvrdzAKEBw4+m16SBSeMLa1EH5U85lejlLSDQkIEsgEgbGoN0Nvu5LodhGb 5Cs5hCvdJitK3crqwty3IKkuMEzaYl6zDdX7puJWWfhP7FPVDLP/2QmUIpO0qWnsTmo4wDy1uWGm 0NGB520tXS2iEnX/aHoktnVMtQ1nhkadBF/jHpuZIC9AHNN6ZReE8LdiJdb/Ax++maYTk6ZSNgBP DnMzXFP+qqu0IC7fb6hxon19W+SuDhKz4eV1wVDVjcirYveJiqPABAsMH+/1Hwg2W9me1ugRcFme vZVkofmUBJBZzxdSha0wbmF9pVnt9C3D+KgDyShA4qO6/gOmx2XGwKzMzBtcOxmPyzsUsjEt5h2t RjJKE/tl9SP/ZrLbIzLOZbpbXrFNaMxcO/Ry46hY9p5PIKxQw5tvC2s/HMjsQDprtZagEvPvQMAJ qpTr+bun+7eeq0l8AMNfre/IDcWojUkkC2tkq/iXbue3tyfG81HMjiLc4c5LjpHlettbhR0Mtl7/ 36oMK9rAy9L8yi+zg+h1Q20FjqmuYEzHg/KJSUhfyYKOiKtfnh6G8WDj/K1lz+f8choZJua+U1lC ve6KSXBzp9hsmWq2nMfOLFVAE037D8S8yVsU30PGy4Am/pTC3lYxZkU9P2BfIUnIwtupFaJxMmoQ KQZXYd2DmuD0GAAtT589Twkx2NLVXbgXnWh6qxiUerGKFn1rl764hTuCG1w4OmulhmDPHMxVcdjz a70fS2JEU98zigBl9Qscp9mPHYWvcspoWQ/dYdGoZFPA08LxMV5J9tRsESXWxyVUdWqE0dLJiDRr mRgmGKEmT7Nm61Bhpp2T4MLwxBVOrx4o+jLudNEU3LK2maaFgoskbKxBkQJp4Ni+T0h3/oj4zQY+ nFLDwmYmN8jPmBs9yfEuwCaVQKJhqwvz7FovSMaRGQ47Jtx/oOECg4SLwQ1R3B8vMw1SmuCW6ZSV LSEkt4eQ79uvV/LVydoCtj6rquXxwb7TJa8FD6DvmdsNJLxBDLRXgGMKfZx5HXhSGsjPcFWMYsIy UVYvlCP+XsDa0C9yPEOF3g321EK+vNkrZYZgPEdEb1G5UpSziX4qGopOnFWuqR5jafgJ9nqF1IzR bjWq3o31Tr0t/LIEvax/pESjOT/mPV5556YKYT+BNNBRc4HN25jZB1EDX/3MMcaAUu+ExWulZKk6 WYN2NR8tg+hNh7KMb6VcHuIEwoA1ZXjtWgixeb7jL2gIfRvJOQPfO0A1lo0BFhFe1eXhDHnehDK+ rQrF1010gp/nEt9sXxWTnxThouxhZejbtZd+WA4KkaEfsU1af2/ckN5Wf0zBr4lCRyPXQuvMDr7y 0D9u5D1AqVYd0e+2euw03Vlvs3sialGJMw8LPvu4mLQ95G4wRBtyPtqiCLxl/UEzGwRAT4ltIXNG /bAD1bd0Z8sQES66ICQ/2gKcvqwFTaJFQxMPTHw13Fyeoqe2VsrEu2w/VClha++gfLEjaIRlSfIB 2lp5UMHN9feTDrJA4e8HgVUOzrCppUIe1l50Pt+J3MQuK9MdXVO0yvqCAByXJE3lNOJ/7rRzNPXN YKnSC1H7BnTw95gUE6Beh0IP2TBUsd/hpzSipjTzNAmGeSYTTO6ZzFzXJkdtx3xKYsOJnPDe9VVQ CAWPphgXq2zMkJl2Iv7UP8/72PNUcuUpbvQC0XPBmW8vWslCVzqxumCHzlTRGTU1IRA9HbXddc1x IbwY4JPs3hthZ9Ypt5zeDHNtLCqp8ubkFKPjI6VfW5HvV4BrDEce+NWhE4mvxpzhOZafgmHHN1t9 4ZRP/kRMAi2Ji/4xZbyuFLbFigwWSIEN+cmeclgFD2/uweR5ezIZQwAzjnXY5H1mNpK7N5gbU8nF CteK83XRLK40rXGhF6dHS+iViHJVTYBd1ggEQUQPNA8iHARk/jgqNuFl3Ue4YWOwHbzRRlFyv4pn 2cz82q8qMT8Nrv1woPhh8Yo+QkQndPO2b4SmJZ58JIysON3FwmQqM633x675j7DlHCl+2tcFrvHx 9aOxKAXcKhtBgSmi3NJF1qqcJXGYZTYeAuxmTw80wewlblHG7c0mSJ1NEkSVuM1vmy7pIKon62Yj M79uhleC/gRJhAOHwWVTqu13WmcfG6HWBjC04L8jzLA/rmxpckgUBYgfAfChCLneyKs7fl3DJRyN uroEJko24AtjPQPQh1DsZdHKLbvsQOnw4Z/nNTfquJmeX8GKbXT8Hc2gmQ9o5If6V5xrUVxHlLur eWeFuyDZip27vuo9HZUCbrbS3hKTRQZNovQfz9Bl/yR3ioDwGKzKyzcm+nT9nunXYK5Vd4ySjH4H pGcWZ1e+iVko38Kgfj0aN3Aq5r1zUFNgphDt42jI9hLCTFwhbi/1CxZT10Baac7k/7NBgDdwpdBl xIbG1OOounS9LtUc+lHN4JXxlj+hBsDwcIxzc0qkdlz8Al1BhvDdLggKfRLFjJ5tWRcrihCLvmRt S7a57oamacCI28OUix58qKed4QZez3yoCl9UzP6dGVdDX+a/jDl14CS+fbQ3fOPzb7aGmxxy4Mdf kD79KkpjQ0pRgUGpuQTs0su+Fq0kPgMiajRRhgTw6deAuOYKG5aUt31rfcJ+zYkvKuyYZgvRoJ7Y XHN6XBOr/ugYXKSgrj5tErj8w6BHFfCA7U1EoP0LaaTAl+zdi+eB2BKUzPJcgfqfQbrLWXffKNEm cWm388LHgtGk4s9Vufd9GCzFbv/11qDI0m71bkzg96ffJ64dI+zChl7QCHBfiay7NHd993WCtnjZ Ds5mbMZO4iqxPxzzj0oaBvJYECBkQqkjOpQudJCASIcwGmIMaNJ0yXr1uxH8vxCCcUwRfxPviMG6 AxKuavuP/XPgandYZpNU5g2fa5qbVodwOj5AgDQGfXW5JbYPD81fUtKPDOpiGhajHBEQnWliTlCq VLSa+M42T9du41QDQu6mp6gZU3Is8cJ8kcRDWdZHnd+YuVkb472QUrDlSVFjIMuR/ROiSSjB+Bpe U6RquPemLTUlY7uBxU0MRnzyI6YGy+b7XeMOnWMQOsyhLbUIz4eUMVEJrs6AuDHVS0iZlDSHWpYy AWTcPPlhLdiUWLi/1wSFdk89QmhyPfHuHOBfeIW4S7Uc+VXapvlZIuj88cOB/VhXdpcqJKCO6k5g y4ZXu2Q3RFRTSgaq0ACQgWXIdZfuotyl70d9emerpLuoSNfvX6UkWnXKJPM/xDNHYA9rOSWoYIZ9 c3cmDfXXPzkqAdwWePZohr6DRZPz5nS828qrXl/SJRq2inyAmMkGgHlQf29s8uMSFqstyEHfAQlz C0DTNDAgcVBmLIBlzIuFfB4hZk8tsE0nbM0F4ebQCTlLeWAcaOF19XQwfJnnuk0dXaj9FJ8gr+Or A3tNI+28FFv233Wc263Qj70WjZKDbE+k7mdHUdTTdzGXhIQDwq1ktVDGRes2DQWVM5k3pKY+To7M ZsWt8Pz8KS4OXnleJv6BkMLrfrytorsFbH7mo5S55CobbDbGylfDCA0UfEieGOLzov+X9EejGGDY jr/OqdOLCQTOASrVZcyl4wDXT4tGwC2VtZqEYUXPrZAG0mf0G8qI7JCP3RizUZJM7/Cx3ZolUshO wcl7JDlq/BKKYIPXiVKK/ZchFCNlaPcLAOqGKGQEeiOHio/JsOUAfSIJg5v1daWDKOujUAY8JEh+ rpLMg5ioyxk3QMih3J8t8mUpEO4LUEwGHilKiN4bcFykogcv4WggKUg1B7ughtEB4HuGEvKTN3xh oqT368e/7tjIPI5MQFu8Rnc7h2vx2DeONx5Flnb2xaaF6RdWCixuOQj/YbFuoetKlPnja182LGez ocBlfsT+l+myQE8o8bVFSFjIG/yY3f+h0LqvGgzNFHdfjtcSifEMwpkwafwQrMYmDWFKkFkHBl/P QI5sTzW7ef2GYajXiH8bI8BR765Jmu1poBTnWN/RWirQEbGusqHe9Q8rfgwzm8oqlSfoIywR8/tk CmxLCdL1DdVCrRMwKHhzzd5K21kX2v6xcFLhyyHEb2ZXExZWDvh43qc6kjyIIvDsGBgvZBRdPvat /f6/MxHl+ukCbp+HRr22e1K/seir795P9Jz2oeCKv1LNbLafnQ1Qa/LVnZs9b88mMnXqktLrnxKg 8oJU8OcdyjbDZV8M+9hX4oQ3PXULYEtudknl7hTGIo2RT5LkNeDz0LHTlOJPX7rnHM2lhlKE217a u3B3ljBACXoaSPx3cKTaSddFJzDZTtVrJCMwr6rEr+/vvzO3wNdTt/Qc3ukJBsQtDE4r643VCqSS Xj+f6TnrdgSNbEZpo21Bj753DNgaD17OC4UXZXLwBNE8ZclIpn/zewTVLc8HYaYE7l/0ZvfZuI/J 9XKa0SXgXs5F0vrHimWPVP3EBeTkyR4NNLoFIzT/aBP8FTILAWDNIvo/3GXb3/uoy/R5sVFeOvRd KjMOv3NCzpKVnvAkUrW+tmajqyGpILfJtPdzwd3YKnIHkGJll59o8E35wjX5NpIw9Yhk3dHLln8Q elP351Vd7v2VxxcsyxGOzghro43i5rLT/JAfC7uZVuFOw24rPrt/D02TOKDAtJwcBVTJSM9RLNzW qadjLDM5d3aL7+CmmalCMWLocmNwb4PPBF3oS4YKXiYcDegiuaCYpH3VlYJKzWgSUNw7wcoP7MjL wr/qxaMpix6PVpfiqkc5/sgU/yAzTg6IfsGgE5UjY/Ilt8Kzha2Ob4tH0StVWwIgOTyW9JuEj5tg L7pJp9V9NrVEBPnHdl0lAGjZgr1W1jZ4OHgcS3rC29PvCe+5tXN1eAqL/N3eTeekBOrjlJejMts3 2my88SMnZdtN7kUhObNS6ZjpGNWh35/ZhHH9JPAhYA2R2z835YY2CqQ4v4MSJWUuYxutbjtJFKjI +cT6u+kn7KEQTaY5wV5BOnlhaSYyjXvG566hKglAFfqN4bYBSvznkJ3etUZOPuRWuLW6k5hBev5P ImVGIyEBSpW8sOcXxTfGfZNtP7ZKsUq/YSgnuoTuIn7IlUoP1iITmmCO8m67/XeCo9FsFk2opxJu NKdnUjGi+kGL9uGIRBEdM31dIiyUJ47nRFXLyVDfke/8WULpL4uPisnrhpfh1WM8EwjBopc9ZGhq nA7YP9I3wP/jS7DY53qCygQilJ204zKgBVka1j/04JggLP1AMCLVc3y5h5nb3V69eTjTBp+xFTu3 +U4C9Oi9URxTh1WUI2WGkZr7X02z9IuzcsoYdX60UkpBSIhaMB8u/VtJdbWB2rXzMpbdNNVTbAnG wD88pZPSYMXUY/IJjfjRgtBhFdSCrANPXDKc85YyA82Sww12wAJxO8TqHNmO1i+A+qFGrJWJjHMe cts1j5pT3hUqmRi9YKyuNOKeXlpPO2sr5JVWNAuE+qKubJvH4QGtWmwpWZyEDCrAfqXJpAqiGJOo 4dPDDmaFt53ffjgrkYsHgBTxbMkxJSvHIgBRRFGZF6GyYQDtdVI+96Z+Dd6aYaZggzBqGwoCXCYc xbEA3OaxctXVb1XKERNCxIherpIKU7tKgZ8cPK35EDUE46GgkbeSbN90b6f3H9oU3VrLoB5RqXW9 GtJje6KsYQteRjZFiGsk2l6obYI75afFGMK7xWplVP4IlxIsKzwdj9mbyHbG03NHxfroN8QUAnK3 wS4xL4ukqaIHPjk87xNPqm0HNdDPbWM+aJLxXfzsy40dMkMm6OvoC7WipKqB4OwkCr1PKELByzoU JOWabflSMuYufYPyw2l2D5IHQpzxmjlSXQRO7XrMD6nb2mptnk2OrAgS4UzkxnG4SBkwYwU1gmnP 0r3+2qo9D8fEsu/QZaya3pnN3sMzrUc5w4yW00fvcvT/PVs3cMLmNHo2GLNu5QEkBBy2a3eR/c8d TELuJqUgxz99YidXN+BCoMvVl01zi29Fc0uGWu2kyXlWpVm/qa9E6LAraLFEC2k68TqMBdDrpzWs 5c+QJIP29lp0AEAyTt+2ME65Y5Tctva3VpGcztg420Q3JGxDtVmJbPZRKmLQ0xDi4/GQ4imPI6Th vtM+wQYKFHryFVC8hwu28Y4rb/MIPiDoS00NQkH/8JrCxegGCJjowtwAoeRmveOVMn1zQxUUQelx t6H+GowbJEnpzZvQLH3opVhXnYjTCWW8nFKUGfl+MP+UHQr+ODqT26zt13LOvCL5Du54J/6ts6B4 b74U1NLIQz2za8KX8w/MQXpcbRlXyf3CwgklvnfOUGiACupDiJ1DhN5E+HkYq8OTSyVxGlv/mcOK gmMTBkL3LAx7Q4bSiX68y6RsoZRkMkqBkCJdYBu/QXFhNc2yieWJ9p6ePO+Y37yWIFEhkkdsWTfB 8hRq/vaoYkKv/J1kd+W2m4wL2UCDwwD090Wp8vjQCEo1TG3swxVPabgQOs8mXHDuu8Ek9PFTWlju ndRL2k6TOo9R+BmIdgewIAkPDIfGYz7RFKFgu4IjEaft2WY4UwSnPfOO9KHYIkZBfzwOtd+29NfI jxYhv+J3hyFI/2lYrw4JOLadcHaw0dj8C4HDwlbBabMWvZmm0vDErJ2VBHT/Pdy6QE51Uf7SACi9 gYNKkVwt1/qGGc5EN0SxM3GGX1FVb9nS9bzgEEspEG7iVTKfahcp3heeRO6d27ZyqVgPCpWHFqRB ygwBK2erD46hURW2yd0ge7MNVGmVGMd1VhGPN8kglXQAsoOXPs51SCZyjrtPcA6/BCNmBs4JjdNh g3SkUYBCqIDtrTWDl2VYRaKft2qP6Hr4DcP0A7XVFmDw/Yik5iFpERDhuO/2NJ35oAlY8dgkqhtC pS15Lkpp/Ba1adO8MOfDK30XgOE5+AXlHUVAAFUGKU+hScmx9XrxAi78UDjWqzdalRDsykrEXgF7 uVk9femjSX7mALeAc5otyAqwwGTX2t6dVPUitBkUyjzm1sMCfwGJsSN+38uh3Y6f1hJppuOUEHha qAqerW3IXPF2X9i5RmIpdkMuYZ0UTVs6gIFjoM2x+Atubd50OoV8CB564RDWwghuKWwsoFx+g422 9z0ifJq5YoZRTTOr6+OVezwQuocCU/oG+yxH7AB+WZSd0OYrQ1NX731l0V4JSYswm1LwoBgUfy14 d0m+2qxy8wTO/KmZqqCq3QsJRxDeH+9D+YLyZ7vukXxXH5DgT42nY8bXDFro3ah93za7QXq8P6u7 jzgVRdBHy0voaygpW+V3V9pJPW6aOX9lXaiG6pVG4OCz8UgfCHYWs22LuvqNEQcy+z6FSGBzD31P x0GqspmOUiISKbF76YZbKP2MY50MaQf2agEVuRuH1VsiZe0CPu7tSByEoH65CAGeFzYEmk2eQXml w+D92r1RRUEelBSw3wTkR2vHacp5QLcSWNUNMuK3EAY4QjW4yTk32iqc12o2AVmpNTndZg+p7tCQ EhwKL7IA5r74MkSqUiSvZHqPeqhU1zy7VIPi34SUurWuE8YBdbQPn3bkgXRTmlugmWT5wmglzQL9 vXHrvqVDlMVusBInjL4LREH8HTCv10HNyWNC3sZr5NB5N2Z2Q0iYdZ5KCgq56hsfF6EHbQYKCnI/ eNz66wscvXuNBZqpfPgRR1sDl1mXnez33+R8BXyFqTl5QcqcGQmz0VbOlRY32q5iP9e32yOw/Y/g vFA9owaRBBGwqMQNk72hYuhA7teDEQrzPEWYfZWxfI8JxumBtgeBdKJX9Fho6R27IUjsjZLrrW2L JJBsJJtanMwSF6vlPnlQVMUQxv8fjxSeVuqHYj3Xbik3IQHrBZyyMQUK+BpB/LcJ9r0f736IT4bN Nd/oWWL9vBdh5XBynSrC/imTJpDaEFoinAzaYjEPD2J+90odkBcJ0O8+MmXU/DYnCJd79BhwODQJ r6WOIyfCqXR/F7p0ACInWpXbfKeyL1sRGbFqsW8l3CW3zeM8QmBcFsBp5nYsYyY+fEvYy4gSCTFe VhASdBX7q37drX28l0zoevwVYgPJXpbdHVKqvinAuTBAPfMEY/GGixLiHpab6kaN0xNdE6ZEo9NA 5ncXo+1r8rlhfcw6H64Vly61Nr9XbXUtH3QGfMnoEiKHRKOm+B2Yj50b0GTU+oQLYmUHvxZz+d9t 09o1o+oti/HaaI+FtZymBvGxmrtBn6nIDAgju9HNTy4CuL/dD6rRfVV0RAPc62faQSG/E8dt49bL +dkAlPb10VzOcDLIqaPWMY0BHeari+cegh/ijlbj41d3kOpGRWTwYOlfH9fumQZZUeUDcEbt02dg AHRqGjmmk2xFYpapABSarFL4o/GGUze//Gk6PKs/OLSs710zKxZsqyQCq1tRQ5QZ5Bf9pTrGRjL4 QUycZJ/K6c/yDrU6dbXu1zDxO1/pZBpT07ZziFG3ya0vWND/Q2PC5HW4ecp7Fnvvsxh2RY2lLUbm Mwdm2J1kh+G+g24H+U022dqmnfINTM0Vy8E/A4icZw9P24IR9hEnE3RJmtdjyLfyP0W7DzBICsS8 tyRF9FAbfSfHSaMY2EDfetMq/wUkTqi1P2Qk65/CdPLmyn6zzgKbtxAqu6CFDitbRABTh7tW+F4o 9vthlypJXmfVtma9+nMOs5LlxqKw0qgb62+I3gcOT4T6cUnXSOAUcRD7Zdb0acKiShMFFl5Ik86+ pk0yoGaoa25TOUEgGAszAMuVFHY5c9OD1e9aa6pfbEp52CRBaQMt1TPD3r+GjbI/m0z13QirqLSW 6AMIeSiPQ46wLf81vM81QaCsb5Q2hvPVB5JBh+POl9M9ad7YKkQZc4KjFQt9okt/tLdt1JdeTQft +t2X1h331R6cwizlxaNszVJYopzpu1tZn8koud71c4oQ7vnuEJNR1RDTzHlp0ohjnskmu4DkFnOD kbK5aStr1hSTbg1ljX1dvyK4rS2AgVU1SbJQHPdih2OFKc3LIfUKQ05CjB5H4h5deZ7Fwt4c4dT+ Z1B8LFWJsadmT8oxpR/ogOSY9efMpA9vuQJYsGQ/w+gJegz/mr73f00EKFqUpyEGnqkAURFwygux WOEsyqPkMYeYC9gjI4N/+xmsn/Osniwrgy6NqF+rsymVQyW3lBApITOeOF23KZRLd3XeKWVXAY8l 8p5SMgxWTCeW9a7a3BG66qAuTVudjVEaNDUF7vc2g9HsUYamMsytzTuuevN0+3DTJIlzhvuahZ0D 1KcLUx0hRXC/Pfv3M18IOZ8kON6IgMVsxZaoOo6MZ00g3M5vgW3HEQ1s6ABV3H3b65Pw29/6DSgT eUGtGqRXKlqDlN7iH7kgHtQk7ZlWD7vHTHO4xBBnnzlNqREQCsAdwCTStlxSLAyixD6CUTZ1MsAK wn5KAI2aqd2mVJLaPAHS+bdlVsY2wuBzjfF/VkVvyds0Whj7SKnNSzhpNvprmeXvdhjEbAKgRYv+ dVH/ZQOumt7ahRFAY7fZcKBsD2IeIfUliJUmVEyEU6cUi5j3iggPOYCj69nSejhYkX1n9GAmsGXB GbJVJg9Z0uYk5pGX8jE/S5d3TPqqjAxrKv1zW5im1hxB2OdgQSGAsSX6xdbMV/DP+Yrgsp6oKGB3 ZYz1ZQkZMGrM/v3G6KwQ8Z28KQFu/1hIKpMMGKNIgu7Mffm6FTe6795lrwJiMh04UZD530YIXdFx vCdWwW7BuRChYNikhFHyw+TBrMslL1PGp9sucxTXujY5DEmUAPR1e3K9ELxnlEJENkrV98ZU2UIZ IMttgarDGiDH3E9ewMM9VoxlCa+UUw8oS2LjREUbSuie7sbMLdZ5gmpYkjZmbVPLbRdHCGg2xgR0 Cknq5LMVoFMMZrvZXc3D8rxE59/O2beFI3Yxd+N0qmOt7+Cj+2Tw9FEbdSKcch686g7AGIBncBEB 7PQZtD1VtyR0TYCOX56TAKYSV27wemBXlZTknd9H+OinsBKwHQkJxvgWYpzAICxBtUdPSxGAR4c7 3GS+AwTotcsG5DXK14jGqLOPzqANqhPhqp5YOjhKcxvs7xLKHH6CTFUku0yB36Zq2+d8WprhO6Mq phZzDti7NsTjNSqwnvjolwxkaX48Em9gr+7IqBzvFK16ndnzcgfao/2aKpg9l5KecIMbkgcuxJFy i/5fCUSFlTsvrGvyHQneW/fyshPMo3vXXYhsWlkuz0ft3py7BjRbLkEzpN4X5batRwPGl1KcinhN +Kl/siSh8eYNWbzSSs8pMUFnCU78BgOX4Xkhdla3EANWJp1qbSyGmJ2FuJFZCqlnAfP0dERnxtn0 hqFujOKaDZzS0I63CJG0UolQO7Bhn0WgCCpyS+NU+1ZFXqa1MAmxIFx0VtYtPSLfv9DluIFTQ85E qw3QhTmrnhbmFRC9ONFGETpYVmfNk0JAeVZoMDsJhulNz3b3AeoGQXMGIkI+QFy7vWK73zPVgtqX HqWEFS5jbHaOm+0QNexUthvtKWJ3ySvtR3TqvkzyDunmQq6XgbyUliI2xd03V5roF5Gqpz09MudY PLvnsxSAM/iJrbqx5LGZC/UyyOa8ugQX8lGymGyJMnUau7kY5L/6SAhtG6wgVmtzOj03yTjW9q5A WwPRfVJW93o0DeZxbN5Lveuzbbxsn2YaHMBLv48pzo6CiDL1ES/XKdF1AATq1uQj21dRcxcre06M IcPYlUTlo5Y4TamzRMOMVPHKZJoPoOJRoF6MZSi68arSG4mqgM+3/uS/4nTV7DsOLuGKrKxigC34 wBjKwlZdUHCXWoZbSRoXzUJ0wRgZjab+KlrGykVr+PTp3H0g/PhH/7pRGaSiM5btgAXy8QgaEmGO 6MonetOeHIut85/w1MMYEAzt3IU11DAFS7ZqglnhkW64vqoESf58/R5nigy7rOhLG03o1wjG2+gd epIPULbrEipv04XexkiL6+dVvC44bAzGI9mfYAyp88nVgF2CU5qCvGzDCWhc072pxUm330QqBmtD gxaZEsMVTaB857cgmBX7v5b6v8vWayJ72moL9s4bcGhZbTfU5r+IwMjm1+5Uy+toN9k1G+YwJyHL 2GoNahKyY/Qao+W7Fn0EaSsBAGc0gA5TymuNuzroK7VASJr4P4Ots5f5EMmuotF1UF8iADOBMJ6l Yoy5Qx5cmxjygDWo/LDzgnIm3ASEgkE3HGDsmh13SCLQF1b9FiRkYZKCfYKIwDiO8zlScGFqMbZb Hyw42mCWeTA2J9i4T8PQtYJvHJpHr94av7Ri3S387lAOX/ErpZEXUlURPi2JZHIEjZwV0FucHnQb TjSE1e5uzVuH53ReowlNckw0hyH/x9S/bxhe+bmNMgtxPCKMyEq/otvPSO8ynWZT5E8oQ9eRanDt Bttbvb5TpYGJZP/bosuiaqoIlKkySDI2xASb8pt+4Cr/JLG1RiRM2YmAGtZZlavda/LIPPLEuhWi Ks5a6NCamOaHEbChHNBIzgQAeLy6LKiH8WH5+1yiMmeHaK+sueNOlETqdXlkPpCIS/xFCskWtyZ6 7h7hFJbHbabC3RiY9sKCnjO4dau7oauEdIwABW46Zb+1eD/YqENr8MKxY4EEqRkX7QLJ4i/RmkIe zD8tDTqz21JzvevfLvis156hRQtgxlOUQbOe/jXplSGqh4c0fZpTdLaBjqqUQZjvLtDLnX/BqFmw lFBOr24hUvgn4v92yq4XCaPdsjDXt35vbqi1ruXiGmQDlfZ9CHRqdjiXCVVsCs6iEhWpWdotiQxx rdPSZxLukjd+76Bi5angLmlf9raHgys8yjFypsVSifUSYhfHSY1PJSdjodPkhGHHycqcsMAP+Oos wXNwHQSggzooMbEfpHRit95uK71ugpMT6iYLY1sybzoaJq3D6+VE2ouh/Ts3RZ5iqcVOaeWC10Wb wrtiH1wpHGMBgVe1uVBmoVvu8dpk/2S7P/4AyXYR1N4uaIbQuVxKOVTNXakPbEpNPWm4v1JxNUgt FsoWuum7dKtJ4OFDQmFXoUZxRvWFaau8+dIq60Nm9Q7QH2uXTsxcv0iNm2SHR27IyYoNE2PM1Hr8 UYtAOKQ4NmoT78TEHWOqSeoGbK9mU8N394hpfZgbJKlwgKbbLeoW4xX1rNJpBFcScdgFQoXBcMs3 e3DqeAZ/xLyDOLctahSGSn5KliLvcKtqYBMj5SI3zDnZiHDJM6P0kg4XrwShllGNks7NGnOng8pE uy/pEpn9hxSO//PmY2RiE97j6oyVFbGaYbo4FJRtIO5NtpiB577sYH8NvWPPQOL8m9qX/A703ArU rd1MZCiPIJDm4zbykRnjYzUfLaiPPT+InqlH5BMqvEtcM5QzQT6biJ1WDnIF43CaPJ/KEiQ6orQX wIy8xLBi/2Od0XuIgTVVaKVFjKmCT94T+CE0YhUc0l/jKCJeoiyH7dfIFesAZfaIHU6SdwQm7zNW LJgL/YbFojcnj6KlduHa73p2Y2vDDyJzifoolMJSoDORY9irFm/GaGfPpkK/6dD2/EzpzAQar85h iHUcBXGcVkUBRwsKSB4qt8z8koOFFvENu4+TnfmG/OL+YIaEBU1vEmk7NtgTz8pNLT28d44xM1zi VrbKNa0zetEg/5hqIL7pjMyO9KcD+ksF0sNxbpbRti/F+kSPuNJGF4PXmTBuYV/CPxtTJCmi2dFp LJCGTlAXY4wR/OC23MeVjmYl54SsUeedF9ps7EtBSaKA8xeW8PStygb37XfB+N0QMr1OIDsV2n3s NcMTLilPKby0ILjPWuQ1Jcycp0tWvOoh+Hl+IoMT8l1h4QHIU1lLkvrdY2eSU6uUhbKcCFEH5l5t /YV//SfXHTsxWOb9htv2XsTtdHTz+Pg2YF8g6/LdFPL/akGwUhFzrso2heQDeFSOwCzAjasUszXA sG1WQqg0IjWAOcBQ0jtph0Q4iTSRvTeJDApk7cqtDlY5kizVYvQa1Vm5xvcf2aw6HwjPh8lGno5Y 5opuIsb+v1D3UoFJU9jR6qSwOJt+WpriR+HK1Uue+SLv3JiWk3IEF1kfLFjzfX5FfFYBTI0VL6cp T/YM37FF1TqgfL8eCtaJK/PfA2D51G8f23Ii7tQM4rVb59FygfW2e2FEu8o36V96XzSidsBGen2G CCLvpyPQZ8SX2GpETA2GL6t58vFqKOFNOEWOt1OyK7b1PsiaK4R9obA1HmCGk5dArJGQsx8e1TTq 1msQxZWupQEY3vZ8qVrsYfJkJv6jAKEq+NxgDgAbTOhMg6xvvxqzLLWV2Wuma/n35PrRwIFZ86M6 DkN8JxFKR0ABKw9UDIkfPgQp3bRGDOTJsK/jbWxvnTbKdMs3RXy9Nq9RM6f5/4PlAQz/Rrxrg5Fs PihsL8pIyIwaFRmKjESZtbCxJ1Yvz+eRSEnxBVyXp3IGhngQ9DDg/XuwHw9vH9Qq4PBM0RizMoA9 /vaNfAKbkC2C6kyuaunK1t8EUYyfg+6mUsCPa2fAaVvKlgcASiHdUFfMqN4Iww+MMI7OUiOn81ke r0JDLfEvU56jKEWTSgSq8JL+OoNOrc0Qu9YtSJJxh6lu5NYoeLL5znPBMPJpuJBpjKWspmY8lNfW wP4n9sGl8ONESrc+lBqqGWm2mQ96lylFmNvjW6o46uMGdZPC46GwyTmWZhLnmBXgeDAPt9oGNb85 WZgXNNuIDarO6wlBZaUZEanBtYObDJX7Hb8yRj815t4aS1zK/IPeu/43C/GzG8vFUEnkZXSfSVZ8 UZWH4NcTbsJhTVzz71nasdH6CwNeJoqGF08eU83/ltN/8whkZgkwuLyIVrClO1SSmRpzGWyuxkeq Xi3WxeoPeUSiRfex33iZ8DC8dIbpoZT6kg0HD1T5Zn8H+5GI0M49UJhQQrtlYAPBhk5LI7BGuXY9 GkoQOEP/SthWycYtH7heUHf32qIIsrRMYAsubNqXFy5B6MTnP/iCIvB73520X779W/ZO7NMCk8wX qknAlxbQtCWUoUnOpAeerf7r6itLnw8VuSqjGA+neh/cx9MKw5il4U6A7lRdmQDYZu3EbsBy9eWi dUEZkOn595k2KKIOIbN0Y7NzVvmisqBgQi5Y2+gO4Lx8NYCiw6KBQERVU4R7Xaje81GP7HRqzVAa kkZrgXY4Ivl4P3U0MbO2KZzti06qmpOlsUg+39efuxl49DC3IwZ3BHuNaLdblb7L7G3MU7dPFZJU s7mM37fk6UK5PeT0jXeB4snhsNq2XUN+215mgK2PI2S9gmmqkfv6AdPwovwwyxFV9k2CDV9zuWbw 82uWyNAtcGDtcnJsdrIbIuFeGhtQMukURDNjlBMYiJg4k3aZPLdye5O9tKJpKSqZ0XnJc6QBv0kH NIMYw53+pJDH+DC8lRB2pOuqMs1bwBrpnzDIQIJqEr7+aMx3H8vyVJhpubVQjNcdq1paETUwiucX 0hFwy2uqbR+AUJ2FienWS35D5eZOHznMxkm18jFCu9NcjwJeu1ILs8dBIjyN1+iVPS1X7Onmnejv 31g6vnMGcP4cPaajRHaxcWspL+HMdan1XXF4e6/GctMwSZgInTBcQojS+OwoLQ5kQpsMZNmQFfz8 FvbgLK3oalKfZB2wN/djKwdRxHAHRSm+rdA5AyrSSGiRT/f7fk6ywKy+kUHnkHo7GL3Pnt3O3y8L CfEGMP1EATmckiwVydxRVDzeULAhE6UohXQEIONqsXI9Snj4DH1DG3I2tM9OB85NOYSTWoJd4jwu lL3H8DnYRVP7ynrkBTc9lgd9HWBYsNrKfYOFaTU12fxsSpNXTicyFy6vOuhU58aiEBL/FRC9LnXa 5N1xFqmFMnrH7LJfjTY77mPH3cq8SROXtfXrORuoSFeRFufa5j1f+Ksv7CoLQAMWgWkZu8JQlznz u8l2mQbG+Ax5qr7uxx4/574ZYc/O48hjQNj3IXzIeAdKAmGgDU9i2ubDy0uzXYWrZThciXjo2XFD pKedydzEFEEuMhjz58ZAVoSyDemvDB2HE+uofdPJvTyXBtoBh6y35Jd87iTZa8EBSm1CZJ9CdA7d 2uZvd9g+dKwcbVMUdUaEEqQ39GBJCvgyT9ALa1cgfAhN2aZLfx4BbhKt5ZpPcaBUUt7M/ZMwIMN/ 6MliXD/zvMzTcRw/EA9a4VkEN5rIJ9aIf/Vdx9yjDs/Bt/dm1KImSXj57/uNPPASKYaOJUgj6Rul 6DAKES6hz73lmoQkecVLijuFYy6Ewc23rb2YU/McMfYa1GcfNlRbZtOSalcgfk+CSdYHiNSVPBy/ EIuNPCX42dyMBhQVriHJs6BkXsoLp8IlbMnsOLu1b2edGtQN23e/HBMNrs2jKN3BuAvalRV+hk8v ELjCyeWjpZdNHggRp4C+I5mDslPvuhR9x1th7fM3qCKsQzURRRJUpQslMk3zJQoqd8ZMWAZF5Ezb rOFqXbhNlbRc6KhF6KpiaEOZbbWkeZ6yWZtWhSG+yX5dhKU7pQyy3GroTiR21RHgxH75tNIAMhF2 nW6wywo81YIqykmhMntFWddBO2j++/qVTGmNeiud79alc2sBNAKxWbDR/rJrlEPzE7EzohcLOPpT Br2e1inYd+ObAcCLFBkbXMa0zAAUWQ5Zb4B5/jZWKbFL78JP4HUwgHEgE/RbR+stR8FTz8TRC6+t 8P21m3uHwBMbr0Ueh0bOexgSraTRCyRiLR60VIW7aITixMycYOcZisxKqzgQlOllyGXPUch2dZEA 49lpJu1ebTzlIznqC4uvrj6tvSCdzA8ad/kVhAnNQEaHUhCicNj0yGHNIzTsq8wRG1MmzVIm92c0 uMTFc/FMabl5gJKPO/6vOTRjzfliZ73cNUT7ox6A0eR0mxZG8QuKhaH3zfYhg/ZecAOkguyYykbo /h1sptiLLxxJU4V+LC/1Uti3936YhspVKzh51J9fdoEdVqFA7xibxaFP6a9wkYzqw4iY/CKgL1qp eUVZxjZE7T++S5PgbZyBs7z5SBnUk0EmUGUlKkwPR9f2i7Y7XubReNsyGjljE0VJtahjAtCDFWTg pxVYtyhkTTMl+mweA+R9rRveVz/Fsk4RNm41e5cIDW+E93Qf0BG1SmTk2PvSxh7dhvL/1Vk/HUMA TCA7FMFQSHgo3L22Mhc2e9rtOE5s1w45Gpu4fFMBdqWY0g+6IZcIYsu+rdW8JHXIfREkTSrP0HMv lghIWPJfRrlOrxDxDYrvKghs7NGSgqMypQICsAbk3Cvim4CxmCR5wAK+H2v2grdQK2CxzmqQFIfo OrxWX3pRLbgSLt++KSDOUfU7MuxLF0tl0XA//sFB+J8yuHL5c8DvErHJzV46QmYnWMm/Jt66Ul6C sAwvmX9PT/YKgYT2nCwHcrKVgGTveRJDhVvhxfre9W2eBaBrA3wj/73fPDrtKYhq0jVeEFP4dA/3 RPnN8c916UeTEEEUUmqCTjhl2Fr6JhOzp7RbYEivluW8m6Se2wFLmwI9aPSF94tgPgWO3b6Wxg5V vzPcheMQokP3bwR6xEDAPH4bhtYSlQ7cJFpCMZpUWa0BKyEs4/c9HRmoKGbxWdYTmza5i7V1Rx+E zgMMP6Fqiv19bUiWTUHJoW4vhKIHWAaWWsNzbdvmGUq+i8n8EFYw9kpNltkZQ+dwJYkkO99KWb0k RyT961nksx0AhnlW7Qvj05eutYPG0v50ul5rXVIznfrdSdQZvW9+pSppar5AEmYJjMNpUNg7qNzD J1v0GrvNlKogOPgr4pp/MQNHQF7nReVie363xUFY0j7ZHEt27bNC8uLBs98x9B+Y4UiyAbLAvxkd seDJxoWKjNDboD18KmTGAlSrmH/OqNs6rc3UYdnuEgT7VKaiFB+OebMge3Obbtc7GcOn+Qp340W9 +enVprk6td1Nwsc9d1FS/rLcXkuXtunAT/XXJsKBKAnU+0mn+mkNITFakOu9+PRPqezB07LJPg+I YdXx9xh4INOiFGL5S5J23X22A/wg1cm7h+Qh4PivYn3DcYE7/GRi6RnmJHYJKmQ3Dd6SuP67A7e5 BVkL6pFX6ZMEUOAPEOX96l+EAOWdLHB7QKYQbmvyLMVwx00xFhp7h0LsFulkwDzJwmk6kG2tAIMD nyVsU7kdyWjfpugEyOb4H9CvbkKVjmxOl328qHwYih0Yk2VgbHeu/RM/1sf1PYY1IH8VZ6IK7K0v xQI4gvV7EX8hgDDVtzd6FmgFCQwhur/ts1iylr1guj0z80p+PYAdrG41TyuTA7n7W3QERGscVfAw vFdH86197ic8Q4VILs1VwPtFXJYj5tSBwFwNlzI0zg4/DfYHGQNxvU0KAnofvYXgFMYuYuPCyPr+ 7BsxZ/DrvAxFbwPGviPW57WC6Te9fWhIdrqElYgGtF2nmPOl5uaPcm8Llzy8pcuLLjJ7VWLvySEw hWlOQaOPB0fb213GBkVcAprbUPVxvxwjyHTYS7H9dT/Nn89lyBTQgksarcY9ae6DPRdB3p0xKP2M fN5ESxYEA+TfM4MZpzN5aw43DwhlA7AAJMT9JRiLCk0GPFhMnXjjrcRNatdqG5d0tlp1paFPKbUq VwuEdhZVWUxDAufJJtp0AeAnHS4kixtZ9GK2hj8gCjX9WzRzFceyVJiUSfyUpylweGtlvJtcLRnQ eDr60E/0gtw7slc6tyyhDyK2PyuYI1FA9CU8e/Czp1XR2ZHuRYS4yoN1bNVYNlnv4j3ehxyqHdFs WEaNdyn3o0stZhbA1Z/eFJRx3UaAVcO9+5kpzKKXhePUN4+f+ddKluEeRWOKKjqPjVm9ZfqSfDXg GJiEuybM0UK1ilKwnKhN3IiaAbahGxe46g4+ioo0joTldf1+5Q5pbCiQS1h0omjiuis2y2SqogoB t+3knfTCY0rfEt6FivWmIwhBGowcl84OX0rCpZX8dlAxyXjA9AbQJvOehQTBPaK1UZFJGYCIQ9eB gRBgsnjUEgxUTT5Djxng9OAYAOZ6i3MS67N4dCyD4VM8AxEHFQowLebugyAbBaN4Ka6LXyQr/hD4 SlcofIi6BjRrOd0G/Z59gsvqEFe8GB8X7wj/BOiXc6V4iT1QEUPSRd/4dvWXMREfBKDVmtrERzbN 01HWZeVtMtTdaIbKam2guwGAjFv3XzQVYrp0Jb24LqNdUDj7AZFAu6mDY6tvcbg52NsU3/2xjDRq 4nvp4ulG2+zQ2nnAeAk6gecQds47mZr4nksTiES2petvxd7YDWvsVXXIBlpMKEkq9+EdrJMqOlaj 2cuN7MXQwi5x89RVTe2W42sjYOkI9Syf19kS0FfNPXQKPExRRBSXZAjia8Gs6URtcz+HywWNRpS8 8uRrL19icfghGBKxHcJd0FzqDTdPH5HG7kxLQNMNjVb6Zp3I7rp4fRaMc44WFZ0L2Bb3NAv0hv+B 0/KCUpJny9S7gP1lYYarbJjwOJ/odIM7RjKPFcM5Zv59oBU6JGxHfvXOvH/z9vN+OAcsm1qx8w84 XdHOze/k+IJ9ZpsPyThfO8lQY11Q1nC7StVEXJtVgaPNzf5MVNkHSm/ca7bp4rMUMbxDwqmDNmpC oDcw3qD5S2Wx5yevfpDypw5axIybhSfC5Dm5Eyyc0yRRCaTKB90q749Y1pZmNRhCKXUsTZyLu4LF 7QIetJjonrI5+w1cEL56rP5Bwwr2HrzYv/PFh2vhQpT7KZFi/zYAURzJm+w4UvGwx+PjfX+PffP0 XEGwLQFg47PAjqz7ouGjEjCPcJ4bd/IlDYiBNRJB8Gudr38u/qmhKycfY+QcrKdPmVzI1rPG9wXZ S7ebdHF21IbYoSc8vunlnKQu3Eg0TAcAY9cfQtxxxlnEF5lSXP1PDq6rustFvKpDi80aB0AkjHaa hgH0LpnIOFwsAe+g7iEHeaW2g6K7FvtdDXh1TtjbhRNQa8inWYSSAFHKyS2o+hR+RsIjPkhfcRq7 s2pmMYkp18cUrpoaFjg30JmuO5q6df7TsUPZ+lSjOaDEpvxG5dLT/ydei/Rn4mB/vappwFYSTo5I ycnvVeruE2IIFGtFUDZzi7j07dBy7zsDp5pjSvnPfdTGTT9nLDNvlwTh0jJWoGxnWLEQNNcN3nut 7zyuNzrSRiSa7Y8UEntfDR4gh0DFfZTj2ePs+YfX3P1omDOoEH4B6yZVUP27vmWWgyajI0VFBp8S DrqIn/J6+IoIcmW72tbqzMlhPvsahVCBnu+U4CmFvVI+TlFhxJzRw5G3DbHfU+HxdJ7xH8SaEAiS zqqCMX3jpe0/PtOaacrQPIpEoVXZdXD8krMjHLOWpBViDmzefWvsUXNCAwe4DoS2E0l1fBboElnv ro5kNi1ZnSdsPTwrWM8xxEG/h4gkgwqlDavILpG2iaGFUtvmwbj3DTWg3MD9eeBnX0gOx6kuk5Ri 0GMFyatwE1m9Ln3PBvna8c/KLz8+K4DY4qnZnmrSi1kxI3pf0OoWTPqVJaiILOT0msbJXVR0dYna amFpQCyGsRo27Aij2TjT7AGl3H5i68SIYkZogks3zWii5D5opd8jbJMRhPGQeLG2mw9Y0mY+Cq6s +oQuxwoksBCmCB1T34+wIZfPzg2ZDn1MiFmfwYy8WUeW+4tVPCq38kq1CwNGUsLaexVrMbv7Vepf QPOcSxKa7Obi25U4omXztLtTXtCB5ci5cUIcn4X2U5oIaJwErJbdU35AYen4EOlrY+61M6iKx9a0 7I6gU13i9/cyyRmgdJyPTxH7rVGNTwH1uFjh9DFm9p+9AH3Uz3lic/taPQr5aokPLcTRuLkNy4GD YRKeWgC61EOLFaCiIKAZO86wIU0Kzfna2YLmc6rK4359zFt+xL6eqrV7IrGRNsUpyJ+TQIhENJRL m4gRqbWzHI4OH8nweTtJIazmug07+8gYwGTM9/XDvBcWHlycRX9XYJwTxs/hX7GM2kzEROpCef1E FPqiqgSuw+F9z/Sq1tm64WxFHKe9k9G/bs64VWmrWr60PWAGbNkVr9pozoh2NCttuA1vE6+Uh7u3 oQUpSFQAYE0jCBNMWmRg3QtBr/MOcn4+nm9Vdq5ddh+CUHdg5ES1NHkHbDD6acme8WtaYZNEvrSn EequHdaeDZ/M2YJNKgKTmRDSzEAnRrq/QHtu4Y5R7KVw7s+I4jA3fko+x2xWu20ROpcXXRBBQMhh YAJHtItphHr57aS0PeQJyJ1IKH34ZrtfU1sNELROW5zuWHb6pyBwEj2v4zX3L5Bnv9WftMMu9Aqv wkXtwCgkg365cfA5K18VyiALNiB5XC5SzvvWksgDCfZqcRNOw6JmjxT6S7s5w35nhsZNCYqoKVSx ARy85X1aSij9Xrkt2GoPTU6yJCK0c7uCFQ9Yh/lghfRmdOqJZglt182Yp3du1YhVRrppl5DwE87Q PYS69TTV1IINilEK22Mbc5sdkK4a2jD8GcCqfg/ZFauNl/HTyiD42K3hjEa4ffcjmlrCr7qpPeky k2zYrKAUX0m7naEf/Y5aUb8dQB/TgxPV1n1FDTm91yXTiXaI+6q9HcEcw8OpWQ/ZV/hbyd161vbZ L1D0NJgb29tYJegQKpaLF5Bt9EBnDOBqUrS9/L7K70d5FIH/nsXWRiDW2LmyLc3ZO2q1uG8fyRNw Mbxy7vGBr3Ddc6ABYl8XQ6QKnvNDwMQMqXANsHqAyejm1B9Er5Wh53rcb7BP1QfE3k1rAXLlUDxM d54a8ei1SF2QwoeFvUEySOFIJn2y6kS4KJAQpxCSgzlms4IGrHDeI5LN2qdM/YVp6yglEGmz4Y+e vaBH+eXGOfZzHgQsBxkQGhTnS3I1Qts3EKmI8iGZS5sjYiCamAhyzj6fTuHqfBBIr9eKGFel8A3Z WELFgHuLlE2g6zo1pkaaoG4NCGycm1mldNszMe6eo/IhUjpIq4yj3bocArlKd2UitomL0h/BsaQ1 RzTdFkdbXqhCnkY4Js2xX2WzcxladIzyIbTELsSrDuNNt/EJ6EmtchTZ/5lM8JiXk3u0T0HeutIu oodyu8xTkhB/P4qYhEOdZQ3mYvKAcbAIyFkdy7lFOIYHRjaypYd9uJwtYeLwuqxKQ3HIz3WRrPzt 6iIGSWUOwvM0bJRRBEOm9H/DshJCg3KaHZ4KR7MIn3R0/lg0LYqaTGdVx6XwgCfd4COezD3WDFG2 OaQTf8r76DzFa723rXBsbYqU2k7iTv9aCAIAjzuXc4PVnQTWZQ2kKA4rsbg1YIQidOIkIzRm6q+x wo9+xagG9RiFxTWz/cWA4Tfhtd76voy6lUAnCtM9QSpJhzMAX8OTPPVf9GV+SKd9OvA+xiBC0Abp yLCjkX1N6KYp/PLOTaiznD/kUjeZfuYrywktTHvs+4/eY3HbxeXLRMv4EvIprzhoPpjDC3xyeLPZ qwHK87aK+pM6Vbu2JRaE/RkZkF7SiXOf9mZloB+xAFhS6l1AVD/ouhv7TRb3YYRbeqOL9o1EZdh2 XgWo706hd38OYRThUbrxcBIRwfqcelgSO+UCsulqTUVtTrNIBl9rdBiSTH6jRm2K6saQe30LQ0i7 v6MxAJUFpi86jMo5aDKAROIPZoKOCH6sCkHDzLtgJEJbVK1HuV+ObGno8PyaV+I1qtI6yWaE6SL7 mNizv3m7HIIDMa9gnXBlbEgNTZYfYWK100/UCnamVhtyZLaUAvBqZ/sh2SLdWocfDe1p2otVwlzn d2T4pxjSFZouHKX+CTJwVrRrUIJNAh4jJfATM+Z49Wbr6fuo8sUp7GOpWvGAWCVkBfja57Q4ihxm iHpmAZtfgKX/kaUOcz79Vfg8eW1CJfrvCSpFPYv/ey8q3N3jxQ3CebjtkXZZn7j4g5X96Hq6vraO wLCoghQulUV+52TjV9m5gh1ueFw+HPcOHVQp5Ue1tQUcH8CqGtgHJLhx5WCG8w7RzbTCXZ3+/6sr DwbAgAFQwsOI/U9SEvTwlOfDgQiSS1VcdkcNZ3yHE7gxKtHCwG3Iq37aQz+FvphKZAAvcF2HdWaD d2837vaUmT8jVK7Imm37kSEDhWiX7WddlZK1bdD2YTX/cUap+9pVLbQhuiLwoCwtemA9VFjf1bc0 OGvqXiRLCOZ/yH227FsaFCv990Sp4rzLVcrNmTaXQ15UOewBjzJstYMXNkv20b0NSAnlaTrwIlfT 3rLInXkFpIeiXh2hjDZ96RTJW/wITX7qLZ59Ar3WVJ11HFlrlsUkRK2P41GrW/awKeZsRiVMhb7b XOSblo+g3dHYUgxvpJX/1zhfSqknNXm3LMGzsmp3ccwxRDRRhWGDuLWP07KWf9rXsbj5JFFZfbj0 7dFxoJdBi5k1dCEwPIanauGfFAkO2DrGjyeCEZUPrGbcjxHME9frpmtQsAZw9LVczwyW9K8rfL4+ HJ8WJMxKEBSATGHgRx+ByO++sQ4xf5akBVkL1dJZFTQSdhkRYF4y77B1JmzmBEvxTuNSWFDQeJmu kGQQ+pY2xdgjxFewjAFTlRv9vlqcDO2nGHS20dV/DxPjG9MYkOmW917GUrmhqXfPbBt9Gjc2Z872 VsUpWPcPBmK5HxbHlSJ+DyiDgEqXkp+JT1oc+nhntuc3PDP/9aXMNHxHbIlMcg1AZr/8Tyxz6P1i /IDLWBY6QILrwbzLkGlqCc+DGyozSCqa3uWztjDi1XBodOnb4Oy2JiPHdbD9raM8ZRvJtT12DXsu Kqvc8ssKilbzQnvvlojrJkBz3rJckIcmmuhOMt5kMGzHS2TxErghVBsbyI41n1SobuPb5vgbLgDK QqPOffp8G5l+P7WfMKT363KkREsEMevYMrhIQLQZpP4F+/uqT5SIz1dkb5snUcbqCWKREe0gVnJl zUIb9cNYma9LeRg4YxcLcFg9anW18ONqhlN3C/MrJuH2yKYgXwOtvIp87WwrHMcDBHmC+3AVKgGX XpUGLqTe1r8yEEuevRPsqA4rullgVKJfrIIGXJmnfnSqx3yxi3oSGcm1CJO5Wn3j+9KX49eYK8C0 KHjpthNYF4undzt3+IFupaz1/iH267aTy/qEaNzvc8zWnXqF1Kb6XTJlodfUOS7mKE6uDRcHTehv y2ruOpTRHZlUWSb9939FwgoCpi8innuU7fV2IVqVB08gYTHSFeur6N8TCDOsAst6rB0qhpWGUryX 2TK/LvDEQAoZm4WQjhG5UK0UECAC8dLHhpqFbjRLLJB9odWvIrSRGBFFmqeuYHcOTu8sFUswKuC5 UeyqA62F2u5KtJt9y7Cwik9yxsQtuuRRdcOZ9nv4CI3FpW7006enyRQogrPpOqSnrYwxvbCYg1kE CB1gyKBT1DeqP0eh/6bi9W3CIUhmBMPClMaEueInaXX4GLPWpr/1U/pzuWzwSxfzOyZX5JRJI/2D h8uBIV4j5scBWxBWXBQhQ7sVhDMX967350m7dYUZ5TIDhTDhvHcqKK4pwCnH1VEtmSMy92yyxMT5 nfGvZd6ur9kiqJ4z26ZVet9lCBpfzO0+XLapcjuF4n0VyBMgy3Y4lR0yd13q0yHJrY4+Rg+HGMkN MEEO8S3FFkBBT3L1hUIAdEAB7BOu+4O/Xm6INcdYPGXwEdU9T3LLBXh0B8mmQuPwTPLFPBML032L gJmPTJwm1pI3NI7Jo0RzVnUPPmW1psTROCuzyg6BqK8zawrPYjfXmgjvD0YA4GQdHvtgWBwuAuW8 BeoBplXF6hgwyljQS+tvcsEy7cT8s9BjBksyLqVbcf7rt/w+sXUHNngqqmbT3oK3AE5agAtrp+vz 70s07AWre2s5oiPFrR8E/YYJ7SrkSy3hl8y/0uWoS/sNlAJk4nfuqI4EvE3ZbE1RbJLHWfQevMWS fG5FF9W8VbieIo0tiwp7tGTqROH23R196aZlyY6JeaSi/w+yh6ZOsVFLiNJthZkFoneNaIFYU35Y oC4oTKbRyryKFYYn8VMZGjIcVf+iai+gTBYx1drpoDq0nZE43NFmi9LGju3PLiS4w0gTWBHNkV9T NoJ9Er5ALiUaX4L79HX7TbebBu4HTRPCxjQ14UOiC0/iYqquQeivR07XUohlJPBEO1Ib8CJxI6Fg e7L9ror+lcvZWLZn+OSTG02aKs5yvjqmv2f1iaDWxz9FZqsnZCRgQKrLigcsY8iMAbGNBSDPJX+3 F2RaKImooOzWrzTcIUg3iv4rNomsO5ECGV264n4lypi1a7spzBBxsfsVU5jXq/BSNWxjt5YbAhmQ UYp1U6CdFFhto1o5R+5CARIOCVP10KhAAuZzPBvwXoad2BLUP/bZc2+O4vsafKPumVUnAm44Sy4R ywZv17tacXhQirBbVAF9HPrubcBgE3fNVmhGbSJQjRZrqdAFG8Ul5FLUxefsdQuLZUqXowBJSTxU zdkXg0+Y1ZO5yJwdT0G8UzOuW80mqorebHrK+hWCxsFPVDo7CbkxxZFR4vzta5yJTLOUd9aWzhBD 9hGiKaFmYs+NU5Vvk2LfAf/Cg/kmy235ksGu+j3VT5sk/Xm2D3ky8ufs5OMKTChgpa6j6Z0jMomx saUnI8HbDwYMnYMbOHrmT5A8Ql4Pd0xCZUsCQ3T4JJmBoWq+jDDUmWr5cmYzOl8kAVd0qcmYB8UL fhH9gi8swmwwkweiBf27yEyGfGbnrB3xSClaITVdP08jKXjK3JJ2fffs/KOrkV5YaUSbZsKZnjFf PhSvKIB9ar7/UzIMWyHqfrRgXQiW3H4fE9k5Lxpmg3kvQW1X2k48+fGgm/k7a3xKe6VFVDejnD10 pfgbMmtj9H/CrRIh9Ykk1Uq2l9VEoCUIqnFwa1Z1gfZysHezNuboCN4PnxUC7Dea7w8t8EFtkq46 q4IpJtwYUyFAn8gBGfolDdWmA9XluSUA26q+C7VSMvbnfzE8UPDbdGvZ/zB81YACvBrVJ+riRvZf iUjo6Yt1kyD5Kuc5s+YZxltMPhcsN7H6j77ydi+qVMh1g8yf5ViR1n+yDaJRG2c3wYBzW6vpHNOx tmSnkt6jwTFj7VBsyZEdNDyz6phU8fbGR9sO3h/QClbrm5Fci7KmFJoRtSx/BvLu2WnOLuQaHst5 EovLgsHV+ONxtzjmsABVaRuHeFXDF4FG1uacQTdd9j0SlJY8UA9/uFcijZxSOCN0Yc8y38dFGm9K kkCFTmJkV3xdIs7ClG1zBB842+nPHevXRPjkM03G88hN+nPUlnGDFuGUqAa/BHsZFXpgEtIVB2Al eSHIMrr0hUpIE4EcLaL9yw/q/6QsCqxNsaglfc18bINrq9cJWZZpD3vUEdW9Tc2PyvicLOpnvinv Qz9ltB01tPfY5hopILv5D6822nFJ9RO4mVrbQ1+UjmtgUy6w07YgVG6tVy7JWd4JYv2YDjdPQ79U iiP76PrfXrNHmAwng0cMvQ3c7+42Q1jioduAwdxknCyODcAKdylPrLmBKS4F6TDRNPHKq5qYMvLa eoEYJrGfMKZs6mcM5rdCtj/b69+Ey/jgqTVg0eFglCNQQRHJvOrRCtc+e32nMSgNqvIW4pFNJ5er BdpF8RMHzm/LjTs8oK9t+wlzFFaCJ1f+SjGxwfv5nF67RGfz1CESobEzmOR86D0QfdId+gfio1gU d7xkTJVAiJihD3JqCdTm7kDvvgXokwvCgJUCiMwmSNvBGL4R7Y1lA0gJ3qp4QjTaE1lAjJA/X3K7 FUpZrNArl4ZjNlfsy+dI6m0Ebb/1GDdVToIjWNtrovhiCx6c64cZ58Y19vvkjzrPcbMF9HdxWIFq C5x8jXKDO5sf8Z5iGsnt2VxGE9XRLo8c8GtwoSMnVuWwYvK4m5u7oxdaEPverPGWsJuT7HsosCAh QeW3+TuOBA79Jw4sjipkiCMz7c0IZBwqeKdPJP6vueP0rJ2WZ/7y42Ln1YPWjy9X+zTTpTNPaLkH rbD8Vk4gDJ2vwMxLK5BqRKmCHilKtLKOjGxen9l94AB7lXiUWJeZBk1fTjyL4tfiExay3iCbPHMr U94OYDwZT+T2lZo4IIokxpyPmdohhg4KQzAtp7Vsp9BcfZ23ilYTYQdL/GyYvbVaCM37g3nETxAQ ZMF/oBQ9phqtgCxgYN3T0HdJl5emVW9zV8qfL54n5FriXYZHVo3Mb7yJCvwK6yo3EI+2KNy/eomD 4lOigbpOwBA2iXb6H+MSJzaBVrnVapMkJ6gyYyB0qwBTvzeB6+gwqr1v6aFfeuWTfp8jG9k9Jr9i E21pKHDXZ0V4JjIah/useUGgvWpGCpObbqvhaqI7cIu6yq/k5+tHJOkglkHrDFtKKBnH1WiqT3dW vVXdFXuoPDh8y+iim52N4xEvi0KeRn5n9Qk5SivaHC4vorBNPP3/SPHAtcBhnZ+7HtPfnU29HQ/M xP927dwkT+8Dl8QEWesTiVU1QSxUw+F3Md8G3hQuLEGdQ5uO9UPwT/HLDBcCYQ5FTOslL+GX1LRr pog7ZKr6RdgHnC4ViY8ySKQBVc/w/I7zSjdkXUguRz1PLL/QutRlii8yS1P0ICL2dfle17i0aUOZ p05YmZyTqtpACjxCWZIIPrRXSfKCwUNqicXHG9i9DmyeE7AfCJeLUjCiyG5DJ3CRzi9FL+/xrhXX +B4wiN9Xnmm0/avJysIEurhAnpZfzRlGxNzTY3rrFEVrzYhGc+U2HwFjcGlUnkhb5ub2a0OQ4ALZ mypnJcdtkvkW93W7I1wwKPul+c3Qkhjw60J5/W3bqt5q1PnfaZJeyFuGX5FwTcu48FlpdnOuyv+j B0+B8e+I8t7k67/f57I9PwJjRa9lDtO2gwSPeLgd12HY5AwyD23NIM1+UumOpF3sk2gpAY2AdkqO Y40GBa5GKqWk9xlnwDOfbLNPUP7Ge7RAqDGVmMNh5kMp8J8UDg9Cxl4SHwqCY+c1kfjfaXcRUFKh vz2DecdaKTr18YPiEkeO1Kz4Y0igNV4adg51BOfUjpHWcTS7cj1vnw3b655trrCcq7wYAS7oAcIT l4P3ZW5BHB5+nrq4NfVz663NmA2/0Jri90q6QPCh2IZSkFt4qEyNEgMu01DCJ6kL2o0xFBHJXEUE Dsh0Nj4oL7VY/c8LRz1c8LLxtPWWQRgF412jppp1U4ABb2z4a41qPX0pIKTJl7s57VBmwm2MyrEm 8gMz6qsJXwrHa3YihB/zmTJRAeeYfYvTdtT2WMfBz2QHxVt4lwzrvLB7i2iIQnrB4ksJ0MhMK3B9 VpwSRYxOVm2rLfXeCPtRGIUA6kkab4w1hbUwAED0RnoRitSBGTY0ppsaMo7jNqdXwI/Jfnf3Gs9t Ce9E+RuyneBNoCK/ftG9uHTR0hQ5PdS6RsIeowPT/bD2luXv7QchQctLfqUxrOZuZbZwixp3gGtE yN6JZCi7MaTvELe8T0805KLf63KHfTYBE48/ASKdyCmOzbJCogNhWmOf5vGlK+IEVR1hgI3d3r1z s+2hDy0vm/1CJ0H2DEe34f1v0bZoLJqRUdF40I7/uNUfbF96jl9OopF1pY8x7LryGYWQQAQZhYQ5 z5S1I2ilqtLG8leG/l2jLknZialuXSwKE404cX3BhHDlOy2CyeO9ypZpUqHzQqDbVnQQCVFmbZSR D/6O60zyyAgdjV06q9hy0kNWFbjM2Jc4apMOj5JNrGvFtBbV25NKCEK/2BKaNuc6CEiQbqbyAJm4 qsS+sw8y/05IGfOQyb0PTJU2pV0aaU3Ly5DkbY8eiaNFFlLHFQXlMoYAq30tX42xH1ASUMpzayoZ nRPod3IiocSYmpAqBiGZF1hzjn8d/mMtZCRYkY3o5mYbCK4wh/Us3sgc9jhuW7DNDmQHYCt2cF/A HdAddC+1VvGqvB6SC7BS+KXpAFnDByEcAEN4OLQyAklEl211V2+oRzlieoU1NoMx7ud7d4rXZlOu AHDyta2Bj8d+7y/4kIA6xjB/UArr0f3fvVHrs3aasnYob5mr/eAJs2J9Bccx6LS43OjyqPMYngnT AtqgNa0ZzEIZApXk13qVaPMzhXabdoHxChhbVtKIYY5QsDtrRKSvGOKQnxL/fV1JgptLrHhz+xfp j+cBkI+hscoe1Wjr0vuZFA7QvhpUMsogL0oLAETgVljODXCVQvzOxDnJJ19Xg6ATSrXMLUwS/ZRG 0vydz34cMJiB3NkT2DFLTfSf3/QEivj+cMekb+vD2AXXOxz9hgl7bXvAVWJVyuIBEMjs8KqMxFfU IE4RmQ7ZoJmBOZe578lT7t0Oq2t2PfYWaFu9afvr4Z5dTINnNOU1XRXxTNvdLAGsTA6ac4+SvhOT 1eIjdhqLM9KzPZW5S6qWqzEV0+gmD9bDt7ahBJIgiaUMKaEdZ+Zek/WkzQskvrmtmjoS2sKuHLEG 31F97FEOExRdTq+f96QXEzoYXWXohzSEt37gHmnXVXEGdSyLy4KAykUDnCTeIC0QE0yICO3lBIFf zhDs9xvsrnewUmTTmH0S3sgJY0hjuOSCLR6sy43gdF5MuNBUePhyYKzKsvwEmlXOXtMdP7ehPXWt R46LqlDYjYv5qpNvZ59olRj3iSH5huYKzfYHOk4LkOJf77kL8hbKeWi2FJIZ4voI2IHh65EfZd1S y3N80oyYjQ5iBZmOkIR85YVRmVo3fdAkiWBYM0QfR6CesEm013I9qqQI5SDOhxXAfYTonUOZohcQ DlhjnVdMClfgJO7IG7duB8fR8W8uDwcy6xAzcurdv27K+zgTKXuLQUyI3hXV/3hKLniuQ1vGFcYK JuU2gpti+b/aX9PJMrj9fHJ1g9l02e6KqVcD06lEgWRID3wU0akObB7h0kOBu4loXz3K84/DIkBf Rt46b3sb5dQfK6uPV+PDd+Pbg2EhqUtOJ6sgZAM3a4eNyof/RoLlsfNfuN5sV17mu/gdiMwoXKL9 ilQ8t9ihf5JmH4UXK5UZFXbWkziLTMQjM2GpUqV3SZYe4AqP8wWIRW6TYUQ0lN3yi6jhPOGPDBQv GCyZ5jZ3i0geyeSv3ftOSP77ToIASOffwwUvf3KJcVqPrWE7Zl4hTXa97dbJGpGbWZtNcVdPg40Z CFkl1TttBYnut38ehnKD7GSDcLgelBJkMoYfAn0f5Fd0o4KUAvwtquj4v5bZo3iEqP0/df543BkY fvpf6lt06VfEKuM40vuJskWhkFn9/EdbjUlX6IWBy5SRL0mL16g7yDi8Qt/leO2rR4qT4Zxk1TaS H4U338vTchyBZjx/B+LPXWyXrnA5F8Dgl59kfXIJXvLkpQBiCGBhinm2otwM6PC9x/9KgzQE8h+9 dtxM7fcSPpe7iT0JVSMJJCiyqDjer0wCThHYt0HHmJNF1n8HsH2la4Q+qw1cXCBr7v1rMqpEeEsh GdSSnVUtCP7Yvu4r1q0ZXAlyuBeHlwIsq/X92KU5Vu+Qgbq3zDKhLz/6zZk8nleaF6QUWA3d1dau G5y+0uoyCqJ9/uhblnqFOv+ZUBtWj8+SgFiqHT+ftioEbNT5oEfN8sdIk/4h4Az6c2Mmhk3TWQNn +ufoZEXyE4VHV/MDC+xTgeBSbW02daJL2Ea0slBg0sh8vrze7v6x2bxBcu+VTfyD0s5124ogO+Bf rBhyiT+pMbbuYVsVsL9070qc+5MANYBADJYFgM8yFhPwrT2jNKdqdV7oJbu777/3/ZBRT+o1e6LJ vJuUPp/YPIPzh/0bLfqMxP5dNoL42LRiOafE09/t9HtaoEOR8bGC/A6RC0HMl+yypvgHIGyRffz1 rGL774DB8e+ODjywuYwwdeGmRrUcFH5d1FEk/mdMqV7bTHNDzJCJf+kBKKEXBc+zhbhgcfCtJUlS 8QqnW/s60on7PfXvlWZPOtLoQBAEnDYcdCtIqZs4BVrp0PKLSlqpID+JRDIfPh0bdvvDfnPZRcYw 8G6GhMmzWhy4kyXGdVnTedI8AQdp9M4XZexrwB97b1LRnJnrZCthKTFKWtxvvubSNGQCiY9XeQHV Z7JHjjnZUYt3xmuFR3f8ZSVjtqv/AXgzg3+5ZjfWVGcPrbQEZfBewiHE5I3HSiLB5upsfkkKqE8b cg5a2a/cPg/X/MJScZGJpELYTjAEqozn7EHlhdEOMvbMvdj3YhFxy/BOvBnT9Kqe/Jdg/CzeePCv KHV873hkScuJ7s/E0fE/WxW9mgPenxavxNPaZTUxaG1PG8KmvBohfnwmM/biVqPRvRRmqxcZEq7J YvZHQe7vsb/mFUdvyme1QnvFV6Ex4CO1105Vklp0uPJNkYXD2pqiORNklvE34T16+MLixsQlrWkw 21bdpUe3DTH1LyiT4wnfFELRCUw/4hLOwI66unpKszE+T3QnzAvz49i3LvvNCnwOWZHGfMrAWqJr gZqEcV5lX7lSbAUMGZaFRoA7Rzox7z3AeUGjuqwguaY5RLqY2pnuam6tQBNRIhr/xpg+uV56F77e u67j6+zWM2lft5AFQLujWH5xmSrB/qjFh70GNFYTPfRgX4sNt9brSDQoK7J1KeahAFBX5lPIW8l0 j4VMw5jl2qm7SFjRxi38pqkEXW4FJzf4n94PIiIfPLYRyRL+naEz2MI8W8d1pCHsbRc5nqvhY5sw stqfOTEtzFBghi1Biaw7qTjbUhFbN1dBrI0IKpMFAK8wCJIvMd7s8a0v7q/KzVNmbmqGoti/Jd4x Yg7e3Uper3M/Jihva4LKi+rmAbS7XT3qLTz4MVkcjCC7l0KT45uvXaW6X6Nxu2k5OtAhNceFa9v/ cP+hCThoBrMWwC6bsDYsrV7BrAhCsWu9WGlqT1ygO0tp2iwx6hHRcV2EaqNNDzLQA4xb+vkVRrdU qYhGj9NDUw9eAIDH7rN7ULMj5y/XRDyEarLJiCtHdfxbAZDNDBAmxrb0fEevzOUzNv69iwu/Z4Ht 3I+hNBk1zWg+IDoug2CCeHbUSDuuPDqTMQMvRtGeANsQT0SBCJR7nT0GuqaqAM+8LzXl6htFAQph VurbwRQff54qHGBfg8BNsG/yp2Hng9AkbXEEwBVLPtfEeUn184zxRst7UGvC3Jxf2T2TqjI9b9+s 6g3dEw+wklp/WLxx9MuVy9NIPGm9pmDC2MVZDs9Rr9Fr93L+OLHBUKYptFX0Cyj1cSqaR0x5NJP+ sdH+J0v7zIUsPmwS2DP+uRgpgOiY0718/ulz1dS1E2RdGTwzGAQ6qo2X+uv7eQpd2YYIPHY5Z6R+ myAYAH8vPU+0y9w7ijI+f0h7/bLKFiUGmNcMDG31riSjHZ/+bw0O7WX5jtEpNfVU6xHtE9zYbofq oDBWJuLoWF35XUqLsSqhYWUQrHsMNutWrB/kgXn4CKGco4Wz9cqDTQGECBybZNXkxXXj2eZZe7bZ HxYB0tP0Cu5VA8Ul0u9BJk9n7v5bnQDVv4I9rkUosuo0iaBX7foc6TCTe10wrf3dhGFbtFq62roO c+gvxBC15pOOsfN8Exjz87Dfd4mmF+dDLL7m1N/OMPwPli7iunsojCqH/LJyNUmSg40llLqDz2f8 PD+0Zf1g+7psnsw1kWJZbT/qdews5/uOh8FbPZdrMRIxbkwAyCp5BMGqjBo0yQK/KfwYM6/HBi2k iVHZmygY9Gn5hWBkhELquZ6SGUKhwZAbsaL/tENJSaHjXGqbdnmGFwTz+sw6nq8ox/K28+DQj7os nSeOjsy9dmaqkhSvTSgt4K80oXUWOo7Nbp4SFTg7E6a3U0IqJhZ+oIX/28NMqQgu1afNE5DuNSN/ bCLHHD3kwHW+wF1KR28S3oNO1rQK/IEE4N6uV3Y7ywHVR5FrrPyqo32y+ii76xRLM89DVUAGHRuR t/RuUSGiFIC6MGfy7y33hN2dzcORfJ+Ci7GQ6GcoIwrNOcQI68LicdQG/ayaLNBvAvXsNqyeBoRJ 0TAKmNKjIkt5tCdMwJrMw9O7csXDjEUEV4IlbxGZj1yV+nMaCqzawgoWWjHVhvCpw3HR0zkiFbgn V3a/2m0/FB/EzRBzZDsfcs4+H/4kC/D0br206XZzgCmxAzUW1PSyB38gZZZv19Ok6/L4Kt0RqxqL oaPQbSGTsu1uGICKABhhFytnty8wjVPs98/qGTSjIr/gAJj2+3ibu9sUSy5WP6s6Xy6pjkWCccVd ExOk5Fo0ee38KnNXiI7UXvZIntuIUcjLG6bwWPoUXeX6xUNsbfoM7lKz8BZqfNQRXIX1lxnl0MHX D/+9ISO966tI/HTr0rOJeV56FwpWTVcTB1/3FUunUBIXg8xK8ZH8e1ia/tOQOyuD2LomavNXUbt0 fKH3yALpG8QQl9/BJsPBFUHvRKOoYk2pQb09TS3JBgTy+R+BafzdQ4Mp/8DRbwBvcso6Wf2+jUQe Q/0Aqnhmc6G9Jw0jL4fV7PLH87nXSO9BdynUCuvHCqI8BPUo8Q8IG4TM7zWcBAbF2OZ99J+OlAgs ZG2g1VjAvbH0EoQM2WhtlQDNL/OR+wOx6TgTJL9YI7YZo+mjWHGc6KxY9zpH2dYaxjztLIDpVwjJ 9Atg5X3eINZfxqMngEo6nJ8BLC5FSiX74HuLtq1lq3Hz6/8tgbA3ew9tRLM+bBde+eBh6y0Do8NK Oj5c1N/5N19fKeOdgSeBbHesHDaLqi9P+3Vdp25sF/8WnaSlj62Z3Q8v0w52291LBGfakwGLMqiM VGYAQSNU6pZkAgS0Vdeiit3MaJ9Kdq0SPvcVEtQ/JQ4BBlf5VRLvIggkkDOpO0KDHfymTMXSa2RI sXHgj+uut8JZO3l+4f3KdksdOzPyMQoneWWbnv3Ya/sCEnTxDBKCPdC6jpameml7HC4Z029ropyt cQY5EqqTtV8OVKLeY7eAKNpR3KvikE4MscLErHt1sD0/u+a4d++HdbrIazPPXwUMJFwKbFvkv47C vSX6Wf+w7fDIgZsQtP9eO8xbPA9BJ8vaL43KaxbY/2kevGSYOiJ64zUSaYi/QvXpewgHk7FAijkQ uEvfc1I6dG2rTKlL4MBRr2JcRcV0XbEa2mc5LWGdBKbaBHwIzQKYrUZNvwEGtLi9FSH17bhsmz9q 9dNYhUXGIFfqTFPy2br8j3Bqwo05I2AGupOw3UZbz7h7mDOPm9xg+Nbs+4QpkQRaHsqdFN3S3fUz DwkpVYdc24f2SFXc1p84G474QD03LCJfZNKCYyfg5T7Ne7AJG/DWWaxvwi9eQn98gFCjSlEIVzcS Zxu+dG2GK6rZj27ZB+KN3iKmxvD5ZsTw+y94yZyXTNWTxIFjsx2nArslujPW2s5Fe/7fNv2Db7az KPMjVrO4j5447YPWVgaLUCATKIfYEYn+jlYodwshVMAK+6joc+K2Oyp66dyxsYnObllfu0CHLgyI 84WQhjVPn+l7U232LYo9Xn/XvWyqTWeAZ6yfRQ5avNUi4WIF8Z59VfBkdFoTLfQ3BKfvXpwwNPow X/1WE+dnwYHKCNvN0j0vHpp+1Q81t9/Bydm0eoqExtRNJ21Sj+dKvyHJCT6NsSz1X6n5q9DJC09l 593wlO2MIp6c1R6AIsH1NQyeQZaJwUrZu3YU/ejZkxjcUNgHMML2yrKCIVXVKi8PwZKhMIyZ1lC8 N9wzWBBG0d6eg3XNFnFLFEcEW87P2rcVFLbA3EpLSjji7GT6sIk2+QZ1bBsrDgV2i3N+G5YxpMpE fUWeQrXsH2YDCJSdYIpntkrBxWbtqBI/hiRMApnStg9Nvvt1cSPZExgbjaHCy2qbTEgYyLiPWyNQ 19Yfxjy3R+SkRzCvzaq9GmjwGXN/5gDToJvqRutKShJmXdYSIAlovCpb8eFcQDnPoigpJ0W4iOM1 qAMF6HzAMJjPm+xUk23h86eiKthJvKSyl4uz/3OIcYXRtTBFzjSgm1gkVCSlKZNciu2owywS5n49 Jka0rJ05YkeDBz8X0PfqgCcmgAzsFqed06EH9PP9ceh8I4yt0EcSVFQwg/55iowg2m+gSMxt8Lxv z8bO+/MYH3iNtNB3F+Ieiim4q/XjWdhFIIk2o7+K63IZ46dqxrOy3YAQKcAdMI7cehi92LLZW3ae IySX9ErTrItW9DJaEJWahcDqBLMJaqUxXdxBLctD5czwFHFsuBGtNzDF3bPEEdENgam1iE2Ir6fr wJPqw0zG2wiJwTSLBbZuEXwYohcb/00WZenWdlS+17hph1qajid+L/phC1uFXQuG1W3gha/t12QO tG939tqRAwpxouUJUByA0RFNCtG9GFEyeUaY1hEvTlAHmKaGIw+IJxIxYFBCbQ0rHBf4bkjTy+IP dv0HSEPd7gmGS26cOYcNScK/yy36JA+YHgTA436PRnv9ex52Ej48BaE2Jb6iws+BXYLxug0FCDll jHEX5WK7FlSm8uX91GBmukNa7+FFgoY1ANS7WmFWwktlkGv1qDqtIMbjSaW6QV7HmCGn0mo+cNcu +dy68/OAHOUs/eMpoZwv5cxOS9oMOzm1XH2QS0S6TBVZ9/aE6diihKH1oHujufUqtYV+Bsszs8Lt /BUK5eQbxT/ZND7dUQMPL4IT1jtMfqLwVGwAIThkODxB2JMx77fSb1lb3RX+2tspsQL58dqRg2Sg qiDZo8si2MML+yLUfVHN+CKP4KA3uvOnO+aX2NRKZUcBkf2sHk4cfXf1MlMbpQ+/r61EFrIc3HtT r5kcPeUT3xGAM2VJ4AmuK2jku8sCXHx6/4XHhjOO5j/2cIkHQ0hVzQli1n8vdK563QQZge6ZO9+m 33jVNuVqrDYUgb0ttLZxYUw3OJxzGMmLpSehCYlpV10dFy6MiAB63bdpQNTkXqXMVth7511G/cPP tMJEWEfEQJ5ePFnABOPh9AvrOfh3YEgMT7dJjGP9D2McWwEe8cIcZXamN5QGVPlomVZU7QVloiZW Q1eyihEbdU2895PVML1kyBBAI6ZGVb5EMW9Ua0bYZuKbViJaHYAvBtKBUeRGX0k7upRbaZ1X5huF D4en/aJ7GgnLqB04vEoPmZUMJcYrkTwpmnLqFtV5sEjfjgWINNdUae+JFDYUALzyJTRQFEqJNIqf +zbfM0F563ofYSdYiO4lCuAW7p/+JlZQzspWPFyJ/AuEPmAIFGNh13KFcEj6uQzwIG0MFGop5nPe TxpedSYGqqM6gChBparEjKl18WHhb66kP9b3rDB7nH3XY+MW/l9C/KWKqTsKFkekdUhiH0HTkqi9 2wNpIDExBillj0O3yvaqmI1kR3I7e9KGjkOGObWl0FMyGuhaOEQQHEbcRQTqjyXdDib/K6s6mtXX mOsKhc5gghjhJJ/i6uIeYEymUjH8tS7BUjT49RYBWrP5KkteBcfhuiIry80MW+PQaqbfWSiBmXlr LSpHnNWizbrhsiwNEL2Dq0fUSwyCNDVT+iytuyKsymqa/4mgxkWkdNfm5OC3wstt/OG+t8n6YXA1 O8rAMw7Tx/EIpVShepRkDSEQ3yrMQqEsvpbgJoFxsX1HLgCg+yPTkzB80zIc2lxor1NfoZT6OggF +5TJHLNSbG7F7LjaaWzbqGbZlUx3hNN4p8A7Iux2GgdR2uYWqf84r/WhwKTnNIHANGFm1+dRqhKr 1dp5gmPTewYqh/1Uz4ZjZVGCOGA9ZLFPqU2SKhhXmRNOUx3ZPQY8a5IwoYrE2UVtjVUOGQeOhBb/ 4wJOg6bf5h+iGKAFsPeHvHScMLS8i5U8RD6EC5r024dFqRFH8cVUNK+kPkoNlFMPr/mG5Pq7mllo F1v0UVRMARBmbViTvtkgWhqdPgHHFyJpwOB1Yk5i4OZQabH9EyKHbg4seCoi5zNUGuZ9OHARAUYq McqAozHSoFUiYB5cO/53zyqWNudQqJOjjpKsNJ98dhRtaGaiU66onKqHTup8njs5PMax6XMfZHsl kk1/ldofRTjHj9nGZdjiMkoSRG+ep811/DWFYzflsCW+ci7MoRwyIGEtTDDaFBVbUp9uM30Gn/Qg H5Gxe9nPqlFpIBEZ95waLrMKJXGMhHqKDX4ykkfEA1AhZZtzB1CtLDGI3wt1ryyTx8AwxPyaz4bP 4Kje7guJm4iqZONiVotWlxT1IdoBI9emQ4N9E+XVJdvK4b7OY/0pfY8SncMBA5cdthYJfF/04qZJ WqhWjButFK1qvMMTxiO1dvbUZYYQ4ncpPptHvxbsVEWUCeV4gdaW//hdavTT9UGu2PXFJHTiyY0a QXVT2A1V+hOXV8g/iKhpBSBXEVoMAeDOo85kAc2S6qoczs6y6st7oQ81L5eiYvfaycfC7qf33x9K OouB6g40xk8qsX15SXzCK8IswVPcuwgMKvkUC5S5t11iqZJyLRzbcKrf6C1T/HIsPRKTWAMhMQdH VyGqtplHfiQNB/wuDxlUZ4uueYId3/qT3rmmGNbl4P0207zHwYwy8SAY6giQkpcFZ+X6riuC3Yq/ /PQKtW9lqjXSoxEYDCM2G0HNW7SESFI1sbQFu5gxhaHH8Bc2cQid8/aIUDjSsRe2w8iOUvHbCTo+ S19KHY8rRMXHnq3x+htmq2tqoWWM6ukfBDoFXNcriTFC17XKh3C3ux8J7G7B3B0SRPCsd9pCzVYE k03kaAhzSndJRsfS91Yor+QQXrAcVvAqgSsym4uaRxD1E7HKQVlrULrVDeX8UHT//GNGUvWXY+xY Soa+OLMX7pa0iBIPG5nFFUuzSxI1guzZXIHyJ795vqkZ3ScaBu/s3ig1eicH5gWeQvuhK02u+pNX P29zkXr50z0AmJzSPHFd22zbnGpBTbJSXEKCSxj9mBoRpObUfvM27kOomRaR2oktGHBgWIQ64XD4 qatiqCMuNwvAptVE1Uzy3zjyD+b80tdQFA4Hav7aM8xpqG2l4VMh6vbW8ayb51Xoqb5G814X6IX9 sejvVbE0MspIM80lQPmIV7lU/JhZhL6gNmYc3rAwSldx2s5wtxlNzUmEZXOpwD2bM2HR+iTLtbQJ dfuBqGLpDdBFAbpCjHxMFElkaTeB5j6zMOiMn2u5feXob7LArpQ2t5JDg2bh/r6StyAYOgzCuvxb K5vbY7dRPEdM+tizaYPMuUejfef5DaP8EcVF7tpDf3Lrx/ALcMU5Lb6zNqiXJs6fdzRpf5MgR78O yU1afZWLFtpuTuqnUsvpmGsa/4AsZvRVVuzg8kfHiEUbhV+bVMtHeM4d1Le3pchEOmBj8UKMQwyY irrN1gJ9oeqZmL1PUdnq904Dzvhju8/iG+N0d0c1RVP2NboiEOLHQgxwJ/MPBnKPZvpwxxGfINx5 sd5kM0QgG5eZ5XLBk6Uewvh+fmaCQfQRFj+vhHSwYSZ5Rm0KpuqpjBUNoQB2VSpEr0FQBB7ncgd8 bFm48nhhr8lU54yvc+X8viaj9/yMBFayGrojVNE9Jbm7pfdmTnktxAYmY/13VCpW4iVI1IVDCW4g vJ+SvPe5NkVCF9zZvQpTZl72OnvOt+XARdCt8BwXzIeF9j/ew3cqwcH7FqJRrirjFK12EzvhSZqM tcCp1bL2Y89S2D09KdED2ZqRWdkeTfu4DQWrPixM+RVfHqqQo1nAutQTKnWfYH5U2wwO3AjCkCeQ 3qPMOn324WDQ/26gUNImltmMvPNrjP9GuZXM3vibMBvIefyL2++Xt5ivymLu0GcWEidq4uOn4mtW W3m+0+MXRjhh5vR/WdLoDEIiX7yzx2qoxiKSJBPRMnnQdRMaUVPnizA+EdUn8e+zittzXVNxfoJs UoShqyHpd2H/6t97BoDpy4ou4klJc5B1ICipayIH6dbmIXAcbeNzuoonZeN4JLfwMVX+OJ13d497 D13vw7kO9TqpObO25ME2Jb4PP9r4dTEb/TkyjCamULBLieCSjkc4wMHerLNzzidd8GbZpJSy7HHO bfPL5G610Hoomy2+EBQViFa4U4OUdVwjdx5djENtL4e2IzPE5k3stUS5KqT2T9/7tZj0hl5cE2hZ hFXj7cOBhA29ikpY4PJty9fEuaSOWmcPVRqDuaSAjugOa5juYK8cmYkOv9JKNL4Ldv0egUFytMsH FB57xAByCgN+JhWZI7YhRRF2ihStSmiOPws4C31zpdSI8PQr/3HG9lMXp3KMowKr5fJyUhSoOZYu h9B+KNzTzme5aqMK4tmFWNzmRNr7SCri+lAx5IlmbOvwdF7ft8vtUmnyJyo8ghc1Az7ap/IfYBAV bBZR8IbJ6tXmS5SndxKB4C1U7QOsd5epeKGXZi9Q6pp3hbBWKS4Rn8aANK8J5jdIfrJoCgb9KZfP MXAPfF17Vq5UqsHFDJDex5ey6PY3k5MYwcwNbn26yRoV1QZDttuplmdo6z3kd1dNK7XSGcGy8MxZ d6JYLZwbdnQRpAQGuNTjxcCGod7ou8EB6XIG//3CSx3wmTZ0Agonef1T1bQ3E5jNYYvCvnWydlB4 B9mG+fEQCJKAyd/nPBLX5kP9lVq09u9qisiBWUBI0c0nCDD6Zo+A8EkmUGfEuExh0VmTTU1t/3/V NnjI4vVlM1BUX2D/bYHRwyaniD9dc7PNrGPWJTd2TVDnOkQxARx+VFGfPmde+qNfbULlWs4b3YsJ kNugyAB2YLTvQthet5B+yle2Pi7MiZNBwRY2iKuQn3cMxT0v4RMo2cYnWENco8sm82hkzQkmobEs aR4Lf5FszK+I1dN9WD1zCXBYuIDUQ577b8zraHNJcpZZBbV+22CMggaPBzW9MgKr9xOqFPjCtRJw sNyd4Vo7eLMhUM0tpN4fkXnzYY5lfNrWiA7Y54TeBFqNTxuGbPA/U0k5ra5YVHxJtc75wiD0uE4H sPvbeHVquiAqGikWxYidBPE03yk+sP6dZ0NBIwSAR4hsFSYeA19U+fjpBEclH9aOPNPffJ/rEW1A 94B8N/iCSO/U7SsIj8yfJRhPD0Af5s3jWBc+prCSSIcG6fuyMfqHVksbzbgF/jF8591x4rfmcO2q mHQOFtoiDFZ3fGDSLA/So6EG+2EReIYzyFGHlnTBq0W21gIlNDWKJwrYiNIpfW/hj6WrSNWz0sZC eZc6Fo5/ktF7Zq0OoUzpQgDJNb/v9DMjWcMXnrrJSKhxKDoolsphmFl3OcAmdxNuSHucerioPyir GTofiWVtV9E9A+Z3brkQM3uLLqexiN5nVzPyulomTWHbEr2B8dA6yvE+4FSrlw0BE4ttiGBmnQdF Kz3Rawil57VvHstonVbe6klxyxhVQoQIy2Qiwlh3BPfpJy319luGx/v2BQMmt6/dyMeMg01hkBMK O1zPoAds0YkfOfN6VqThg75mx3yfZjPkoGs+W0QWszm6cpqOXUtAlM07tMU1T3nncxaMfi2bDp9D gb4yhmBoy/rWopz/1hDuBN3ev7yaeZxPUZAD8VEkq2TK/cKsrWAOd6OsG3ogfBIN2K6CS31Jt4sx nQhA+RJeWqAC/8kTW/k99woBNLAVfDaRcJumkgEZ/yiWT/cqQkPfj/Uz5wUL18s2TL24S7gyxpbJ 563Fda1OafaACPnt7k7Nc2LVGdbh4fJcUWx7tjyxIYG7ipQ1cRSSmDaEIZmUu9A3oMTUp+Ls0jKZ 1tgI1Ilh4Xkgz5Na4QIBAho62Ke/FsnZhWGoTY8ZEwJmcPQBjaCFPEpKkiVvfMSw+hDcxzWooHR1 ntcb22Jz22inHRe+14leWL00jx7jj00gLOJ1rN4AnXge6TF0iXJVEbi7SqMMr635KRqruibsI/51 vULyz6Z3cn7Q4yoq3IAxXI9A90JxPE3egRphlKuCLTWYY8Z8Qbgdtm4sH1QmvUoJnM/3uObpLv+T DeYLlhKGKfVML/AtT+ZULv9u0869rS369zx+F15VoBFZ86jRzo0L6tWCEkVpG0t96gdPwg8v4HFD 7j4iOPPLbEAJvKPU1g47k/+Ocyp6IIL43iPH6MeBjdh+jkVLN5gPrxp7TkdLHjUvSRUo94+azli8 D40oIFitPn9uYTLfxjNP2HJBcZ7OjHfMJCvB+zAQlW6XNETHxyPVdT0KyC+UPH29SD6IfKMIZe9m 91PFIRfNxicK3mpCQ1jPGzGqBQdKVkOsND4weJ3wrmTvisOp42WJc6R+GuhhU06lswoDiiVxGku8 3YvjtoDnKBSDf4qub3y5+1TwWSzD7b12ohJUHKt4YwI+I4DN+8j32PC04iJZ40hgzZk/ZczTd1ox WQVjXpvLAtMYMQnhwByD+BhHb/y+0Qax7vwnOPTz98xqrWGeJASTdNSGiWL4aypI7BSaLxclWvkk B9IfjBm5sSVZVjwEB3VhnRTzgguskRseb1I2G+WOhjV0W9dv9K2VJodK++Nm6/1gJ/3djlLAIV8g eLotYiFTNQJkLh/IcjTzd4JlpzkXK0j5A5JuTZLjz1hkDFfu9/sFzQh4AS9PNezG/ySCqkrJxm+R D8cyy8JVoJKh51dNrAaVikeoksVcD/C8B5sg8Gxlao58kAAaviisMcYu7AzDpjhNv0MhMk94I++i Te7wOg/BJrdcn+s6kyV/UblMTX3K6TVrEQb0glvcK/BKq67P57d7RmVZfMlXdkvGGbtKCgN8fazS sGgX0RORqoJT+D+EWBb9QFuSlngwZow9cR6qJDQwuXfqSl7+NUaqrsc/Lyl0GNvha/yHGIm5urFO 4jxsf4W4aAnzmkQDfcqlM0ZI+mcgJaOa3OCpt7KnC+UfMePoa7mJ5//iITT/fKhIDfK1cGMiBScm ZGkBO16t2kZlPeNyobEHQMhjdS114Gu0Vvw/0QtYGcc+0bl4cNsEvv1JWMs5Ijpubb8zn5UNufBh RoPqvoQpqHTzCDEMgL+5IMBLFbJ74M3oQdfWoL/UqW4/fxInwM1gIsNjQ5sTD4Qm7Zvl+Wtgrdzp m0CCFTnRWSHzRBHc+J6JN85r5kC+rdpl7m+194opWdJmbX/tGA/te9fNyQ7hLQEX2z0my1UTbPU9 XREMEEo0DFyV2xP6hJioBnIm5ICFLTl6WT58fgU6UgZNJNXDET6Zxenr9JMYWNJZlQ7uf6Ct+2CF D5FJJ16i7IsvixIjiybFsLGMRCllLBJZszxorleSeQrYnTD2gNqC2pkfcGMQmO1qjbdIvjEBxEAu qY9G9EUExPnC+qM6L5QXM4kuzRF3eAhmyMTAngWrkbVP8bOiXVVhMnEro6mJR+k+WBc1qHSe1+Wn sQb+QAhkeHgsQADJ53q2r9FgGtUfcwJr7HPpyXOZHFTLNiBdzFHKOE6yeo6rkBkWf5atN82LCM8G 90Hw0v7iqE/3IP8UOZGezSSdFDWFqwsuFg1yw6vbTVMqEL8Qcj7JEt6kZ/P7+msWycqWUWPANyYn QcgOXoZ+qqgLiHWWFGMbjTAPaaY4QsadfJqzweQsPoKbclNBZObkiREjcicIG/gkJ+P9fB8BZ+rp xgDdEW6o9F8t/iov963zL3vG306jh3NR1cwxY1/miP7OynuR2moXAH3NEzY5Y7e/2hTo/ad5K6wh 7PTf6bVDYSe3GV71/Du/lT2Fg/M8kRF++S+Ib8/HWyfdSrzwj1HppVtpVHAEmI6RXDtKBTv5quai d+n1F/aEzmfsyhZYj8MqQ5Tb45cDaSutQ8BbBNFXVdZ30i4s8F+prc1Xt8eVtkkUKoyBVFOZtrKV KZsH/AgRsheSJ3/91XBC/jbSmLMq3U49Nkd4Xd67YzLeiGgbFASdn2Jv6kIo+Fguzvrdnb9IYkqt MIc3iA32/rfjbG9tNYQy4avV3PeagLNX5J5kcpQFFGiB7B2G+yBio095Das5YZYJyv1YbsZPgR7Q Tiyc8VeHOieRDMr/4VG/b5bKA3L49PnTm3YzESvCmKdqRFbLpXcc5ksMUWmAkBH/MnC12vo/spZ9 9yG7EBWApqsPmrdpFpUI++naiH5fRB3ia6p45niPcnoeC88Dp7AnSmwXTHZw37tk/DboHY8/mJ8C PJuX6I6qTPNLl8oSfy7XOx5UnXGTBh5gy9bsfNjr8MvAPQxUAm0RfAhW72lo6HGUg20rm8PICzok n5QVe/MEMl+2PH4j0XX3NCiMgvfTOIer84mnqAhWSu3CMIyXjadGVJir6uFDH3kUkkgW0/wB0SMg Vu8B2ETzftq0/UVtESoYuLzSz4cbcHCgpbCjy0BMspzVNSn04cmjAOAFf8HM53iaPUsX1X010IGO GTqkf4Vsw/3tYfNoySjFzeRg/eU3sBuwijIiqHr/JB0R4bs3Vtc97iYvLOIAGnZpyZritwRenHdX 5YmgtJRiinI0gyjQu+9VX4xtmAlS682cgUD1TUgrtBlCXL8eK29vpE0pOUHNqLHNGQYBs9P0iZ/A RE3pOzycKLcIAIHLPcCyzu847O39Hjwr75c/2ZV+mdn6zAJbVs7AQghnCOQXFPSL2Zc2EE6KDHdq /vV1bAe6qFiDvxHFQWSktZM8o8JrlaPF3nv8kpGwUOHUi+2MxjipjkqhuKwweh+cR7lm8m/wxml8 O/x7TqqdjWOBmkL03WCbs5funMA3Rr1pmFV0yTIPopK/UhWbJg7hP/dly9viMpCZ7U5Cr/Y4ZO2o 2eLcTMzozvQ5ZEnB1sXlgJbClHZdKR/gVazYkKI1nSq96qGjoxAUU2X3U2DXt5HsECYQ5Wy8mk6v u4CR6LzsgKLdUtiKSxYBZvdwTOFCA7yGh5Dk3MCv+vPKwzzISBaoUvEx9KJtjUDDN7d07IL4bf4d qe/npNTDFzkd6dTIJBIu1C1VTKlekom9+NbRMzeCXT+MgNvCbjBnIKI9KJ/cgvZxtrev6doldrQ4 AMyy9WDc1TmZTdd/S9s0a1JhjvKsMZVtx2kM0vIiia83ugyhnlVn8KHROqQbl7qCuQjuGcAGvB3q xbUQex9BVc7f+SM0RrnIro4h+eLwB1dpVQ/OyYK+EuviPt/icw5fFwGujd0+YoMJVNUm+KBe+BRW 1g8xOWTHWpX5Dt66M13G571FWk58GNQmkxDDhCoPe2GONEf8w7nKpeJcOKBAkXs6panhTDsYjUuq Eh+LgaTjeRpOexGWi0zYtkXUSmWs+GQpCR2mnddPGxSoJy9ysM466xxixmeRoGa2E8pqNwXAgnop uLECpcWgk06ceTJ0Mvtd3uVfhWrJbUHnQNLecfPF2h0T2A7PAivcWFzuFalBVIupDuXS+SST3J0q YkJ7S3HiuEuVsxo85UwH2PkbXVtfc9rLgnvk5JP3tSeStg5VdZxKZ088EQubAsaA2wD2ILumXT6v xmcGO6+69dNE5ig9QLUkdL91sJRiG5/IWuiB0ILA9xQ22AWEWd7mc6/wkz4JTsX9yKONr+DAehjn sacJ9GuYCk5VHS5PoKeyQ07bZAK7J5prUkJw6ZmOCl7RnIdonrjdtmenpTshkxIVNe9hKXYKHMce iEE2jb47ycd/r2mS+rpQX0UqmJY+PJxx1/4XVblzMJHrXoYXLFAUlwQO9F9qQBnNQsdp+aPg2x65 WUqpw0oCEZUTGlVHeIvWE9sJoOrYPtn6hf0zscdOX1IpW1vx9lrSTh32p1BLBp13KBocs2gCtdyz eNKDq+6+J+70oCiZI3Jnp6aURewVdOWfA433Zsas7gnNOcttW/j966i4tP/h/RdKGWN6vRzNq2nX aU9pL1UNh5suFD5H863phlEdwnJ63K2XljrjgXKgCW8zTEoozdVJVCOhCtPr3awTqrQeE6Ejq7wJ FpNwTMIAx86y/QeiC49kXXdNejP1EPNAXrtvunqew3lQIpmoDlnbqtiKdJhA9MpxBpIW6oa6pv2m d9ZUG6N65g5mbkE563ma83LG3rmARCp02rOWGJE0PEGtA3nETNZsq9Q5Q7/mZm7mJwWO14btmVkY 8UPYQpF01JNlwqMZ1Y5Sc4sXSYBhC3YEa1iSkVbVb2T94Gqhq6hbaaQojrK8Sszz95r6t1stzRkt qQcyzgO8iwgKB4SROfn7vA2RjtntXNKFGtBrXyiJr8RijjQUMp8/9mE7GXthmicXtelJsxBUQ3Cr PCxyKBIINYvC0yeQgRDF5d1FwjcXHTl/h19yWa3eTq3/iR8V+q9n5+kzA1pcBhyRPFmKjWqlr2dO x7EV/7Gl/JZ0TYiEzL7cw+T99F016TwXwGpFOG4QJLuQhnEQJUYOgzNbdJDjEA/SqFeB+gNaD2zT erbYRk+8s/I2Yne9viEAPyZmoXgmlo/fn9QezGvTDHMqVR5RpgeUvga0SuqLMLYExgGecS83dmTT rDWGA2wxPKBVv7QuOjwKII+Yn3HmTmDecKT9U/Itp0LUbqKlZsd4CwR0BxOL4SnrheqrOU0Dz547 bPMQnUvGSOLMiBxZzWR03ZwnmaVBG4PRtOQBu2sH8yj2TTDGvmT8/5ffHxTZ+MHhUifTQP86kh5c Vkde1t7UdiCxRSwRhCu1pfJhUv3EWnmx35Qb749dO/uLrzNSPX1xWtB9D3Hu9GWqIak/bRwNjDj2 36SuJbIicaCpWzSGnQPeR+K5juUQ3DOtTb16eM03b8QsZLBELfpJKfcdXjXSjQlWArPfdToYl2su VuZW1UAx2YE5UMxxibJXQk841ObfsoDhCPHANeA+dZcMyd0HUIp7kkN9VcG5hfujy7P+0FlJ/Rec tcYDgOtSnMf+R1Db5I13/YDUludSAlrYzLImNSlrvJT07T08KrlueFgf0fkKrg3m5LPjn94FQkq1 A7Mim4T/wTPLre5/+0QbgpTwZhmMRfdjR8z6VpqCGEu9trN2QJUHR1FRPCfgdKM52xnlK8BFoStM cft5MQnGlX8jHxkxbjnE2zQWxomPt1b/GaNZFU+/MJ4Z/Z89/agL1y17chGqHrmlkjpxA2VGUMGW c3tk1xKS8aQ4NhfS4s/O3ZIJcqASsAC7s2UdpdFseDKHw5GTm2yBOgdFbi7j+DqaxjDLEBZG4cTK BzTI7cI3SRcV7lu7QbbH+aMHJD7BCygcuf+lbjLQgvQ31Eowmh0vHbFQ7Z53ibXP+xzy325TCYCp ku+kjQI6mQTu5TukbFcDNdGSISNKrPlqHUrMUHwk0RobAbHYjOmfpAFJZVBnPE0gCr63rAU1w+G8 B/rbH3Xhv9My2orBURiSazAnlQtlQxHFF+USL0RG+Q6iGsqG5ygtCAeG0xRjedPQCNZs6mRieYY8 9EIVhJ0NThOD8oi2NFBZoEaMD6HiF0IFCyQD5QF+iKjVmhiGDSZSlz9KPEkRENN50jS5SjEBOCm0 TtcRd4ibJj+waCzKjAwClFaWEf9ErkED+VLSAYJBUcDl4391EBrTj4aj4C4QxDPI2im+gw3gS0zq Hb1+9emIeoqa+cKSezMNMmzr6V91GBfRm0EVOA+jlZk+NrZbmf6idxCLr1mtBatJAY92V16stgfm w/sNQt+ubXazBU0U3aoB8my2EYn2eGAYsugphoMLXMVUJOsWy44BYOzoD7cLnuudg82wAH032aY3 6mQ3OhQ8zygTlTaHd/ZotGwSxIiq7Fy3xzEwvHhU/ntQLLYs6ENwNQOIsg+HrbBk7sU2cQUhtHzP SP7S5YTX8OiVnPHAm5VyQ66GhWd503SqBDwJg5gocwjSzIIF8wSLxRAvT9TFh9O7UwiNyxXpVkKU kwen7SzSkmaS236yAop9LZPrJjZH4rGEuPrRo9Rq9fhpwwMErEtZUuuK4z6/QhPVFkXvbrM6sy75 b43hZeXI7jqa7wzC+tHBYjqXi5x3YrS5e4OaMtLPQuoQXU+V+U8qdnW4nyjj1eQ4s0duIDTg7e8Q 5s3uCT9YUS3wm+t8ARtOqpFO1kEGQasuJR88PtAx7RoJJYazAgaQjdAdYikX/65woViZDRGNcPKf cWFY1FjROcfRHDA+qR4LDuIgmyhn/vTHkE6vDpmtqFAFMu2MZPKJq2lbbRLBM2Tuaz11ubnuH/ty idmMcuYuWTA2a/q7rt18yHtg/HrrwO8nBGXG7dXdd1a0emdzqJjIKMHq6NR+WBlFjScIYw8wAOvQ IHC1g5f40GK2MMQ3mTDHRGodcS1R1UPbcGFNq/xl6RYfEtV43U9GamZGuuf/rb+DSGPg6i7LJ8hn /uDDj780bznBt4cA4yMgLoiJ6Lx06gMeYyxYrOOInL5cBUp3ecfWQJrvkqYOGh/Uw0U1/ZWqaXl2 yo1mbOUCQwsbyytr1TAL8YOoHl71N3+LPaORZZ4cWIjdo8Dre8H1m5RezVdIAzVA+MRxf1YEDYQK oaAh0gD4qa4f4ZG/+tXIxjyWQmibbyLUqt/hOD1+JQZFiU0tcr70A/NNsQriUZM72rhCvHmuchlT fh9619153yWy/c0q0mdIAJ3cCq312iDpcwTL96tlQi9hmHjAM0FcIqPxPW5n8jyXsfCmKG4Xwgwi TQgmRJD5LyOCfL/fg3g4qG0i3/23dNQnAiNt6zTKPluBVV6HGDIc5chcnya7QFDLv32G5l7Mr+b/ YQtNRU2GbSnaIYI08JaVx9JvnnRUoqMyTye/hr/fhLj8aRK3xs2O4UgXc40VKD/XyMXFioAbY0Mb jcVIVcW3Uucu+XqFAUb+ipvtXAUy4A76HHjpZ3qVQc9pq0vVZwNroB9aeV5lTzk0pEH1BLTmCZHj fENHjlK6RF1LHrq6v9dzEt5s2z4gPPxaaHq4kJ9Jl9Y9B9WPq4w+1ZW3bF3pgwy2GINCS5NNXLHN LmaE4GChqlP4IRTl9/72Q8dpD3urxD7Y5ndl1j8oBYebB1JX4HvPliLkWcrfgHMDBnQvkLfpCW0x e9MXEL4f2cIpgZT1LWTiPko04wINdopdx0mxk2j3HLLZPaxxRDFFvb1bOEfudUpL/Obqs0ep/TxP Zk8sHyLFZ0S7H9c9WEBvBpDm3DaEDN1x1VPLkcVmuwjDpHLgrCg8ZON8FRS8vbg8XG7PdWBcMD/S AaG2SIlDrCklUzKANAYzM/QsIJ6QYME1Yp149OL06M+v3yzkG3nVdbx8qCLc8wcW1JyDqapCC4rA BwczrxnGmnhyM+BslwDqhDvx1JGRIqnvgfC+d75FSt2DjEcs/oL9vHeOC2kttfMmIDsi94n0fd8Z xEbvQlGkSpSpN8LOAfJz+dbPBfciO1ONb3s9k56u04618PP8V3NAxlvA3IYD8W8qy0t89KZaHt77 iVBd1nBjcp2KQa7xHdL2782txcqjHXUcyEgLXSY10ePBiPQbJoSmMG7UnlgLui0XHkgFO4HIHrNu AP9W5LtrxBWHzFfVVf6Rw+m9WSov1YS59O2l5TSxod6a5xGO/m+2CKd2FIhk7T4A1HKYNxQH29HM Wqq7Y6nGFyr5v0M2tqQXJLyNWt14RlXtUkP781+wdgAxYgbgjo/Q1N0QfT2/XTAcNkf1Zki/Rdez mCUii9+yaMWBJidfCpU+mlll34nS08g5TVG9PsSmIAeaGmo3IqvX9JNcuytRq8Nx8yVzxMVnGUqW Apd/RZPy2sNbOeZrZZ6dyssD86Wk0DyMLghHer+PbTdRA3St3Sn5pEjYQhd0ChxUxrgLSqHAX4sO AQqxkgcofIQwCyn2zW44xsu+3JDiV5Ujj3PfzCy+gd7bEU2arpPYb/LPEfeQiwlGkZCZth961lsF yRMI1j9atZKtcHiKcP/l0yF3sOG9gJHvjQKrk4XhGTVPaOkdBZMe/Gf2UNDdsVWy63psXNQxJ6iJ hufm+CrrHDDc15aEQyHCsGqb1O+SSBEqyw39cXXWUE0a7sNlsIXiJuz0jbHGZ5RdbujkCLPJFkqx JRyoo+zDnV/94mmdjE9PhgHLz+3kqKmqD2eVXt1HZWN1+R6z3zHv8K7f7JrR26U2mwFEwu1/CfAU g2De0ueTUirCRmOtijA4EAxMA7LZdasMeYNqcfj+RpdbeD6cDHJqgGDYQ2qj5idOBJYItBg6hLO1 Kc9W/YSNoOT6McQiaS/c0ACQQedGsqVvEbFIKjy9Cfob5dp11K1ETqsD32x9E0NRSrwtz3prmF0i SsRnuN6gV0l+PZRcepiW/IQrmw+Y5J//63isiGRCrX2zf2GG0bbx+v9JqwDBWGYUXxoREDxJwrRN l73XV8X79ZfF2XsGmzEhezWIRiu3F3N1+JUt3yEcJZ8mzbZmgOQqxl3B2s8mRtAWDI7Cbyif1vrx xAS6pjuZlNaOwDuEwj8FNy3YlBsSdSZ/k5xVbMzMFRMd+J55YqyDwfZAy1L9y51yurb7h4wFZ2oo XS8CqzXbZKY4PDNo9VCIWgb/XkNxHIBKZioJ49Er4j8/iQxFffbQGQm9oXdaNChUyjGRJynXMATP wRFr2y3YlSynem+iG0/SnM9FtBZWDamsSXd3FAF649frpC/hSXtCl9QKTCl/Q+iP1xkUSbIO/LxL hVRtwBFtReDiy6KrJ7b3iO7tbe/Ml8+8m0J5yGO03o7oq1JfMplkvUVOq7gi5JjdmLNcI4/tBR3a C/O5QKdi+b8UFVfraEiu8bXhpUW7NVTKEJPewUMXhOjcqbrKUigT6SnRMOpAIdaQI6VstcKtOAFo n+CzxvT2TKCM1AVGzDNhwH41bFcEwfMIVorOXKtgkZnOwrbzGVUU9bicUTL3Uq7j5Gcx/0JDFLcG L6uSE5padX1S9zYpr5vLxYOV4yhB9t/z6TrIrD830OEKwxriDm4jgCmucMCcHvjJ1LqlV8xXg/40 hEOyQ/V0/2zxqnco8dESYVGWT712M+DjojoLFiY9uVL8OqTwn918lmJWdKxoJiieOwn57LrhVlYY kreLGfdcWhHqd6QVr2PKLg7imelgADxmMesFk1VkYLtixjnwJgdM2I73CVYHBmVHR0KoZH6t2mmN c/Yfc9odJJBNrmWoJ82bUIvVrQYPYGWGEktjO+Ws27bcEa6aw8angIG9uPRN/mSawcbWeMriW6Nw eSUXAcSNMIMODd0zZ1rh6JAGV/dRxj/OILps6wp7lREybXsY0RFkUYIGeX4GCqbgT6PuT8VLhFwe +zpoFvWVECehhTy+hh9+XEXNrXHNFfHhVDSizS9fMfacts5X+iRKZRo69cC6PrWzvZkwbuzPMWYu 1lfrv+9rmR+ACSz5sn6IVvFd19fhrpTwJta6wzJK3GwlhhrY/7OFfkzTK1Gi9ARqFbJzTCwZTv4S 06tjCcQKorbRZdHjLViaOh8Bb96B6U0qtlT+j72MNJ40rKQrQ7IM8rIVdfOOQZBUBKm7osztONKV 9qN2v5MuvGKjovUHlqpb91Woa4+MKa6ZwbFiX0RQ58G8Xh55RMcu5JXAovUfxI+C0HTvx5xaP8WW rBcAJv7gJe58NHRUaOoUTYAtG6oOofxKPb29Ft6hkgdHOLhIkZ61ID4RAg7ukU9MKfGGNuM1j+8j VbXDbkMzl4M0GlWV59rVXdLt0vBN+uc9gY3ncI6PrSUlo4jAyGt/qI0tz7iuQjRw7THWPQU+iZ6l swWmf6hIe/JgBopWOb7GbQS++kt2Jk57vZMHCg7ZAfWkL3i+mgDEw2pkik93Mu5ftfOMfCiM9HNJ k5beMNYqxD9QaXNtIJKhFIQNgzC9qewbEGzibfzqtTM+Vw9gGyD2dMiBm63WyHtv7O8UBr4m+KTb WdiBv2KcY8oGR2U/CnenqKrsX0acL7hCHQd8f6xdlGxTenPwy/lhWjGIT0LBpXWY3C0o8gQtjp2z 0XPVZOye6hscf7t20D8adyTT9YW9nH7igJxLfVc/FRseZ5OWz9onw3uRF9ky8vTUAZEy83Rl6ZjV zsuI5qrxJ17akL8+S7CrW/y9r2tsxed6jqoDSBlZNKjQquyfGFA9yZU+iXT12dK8cAbyzo42EeQB tiaMyZ99kTGh+7EpHSUpI9imR4ZATmBo86qqieR0KDLKJIDn0YlSEZ7wHT5AU+xxHlo/gmn2dtRc slrHWhhNYyRfr4bfAXuH9fsMMR6BxzhwIOsVU4WJUemRhM7xyoX4FVH6IvuseT4rmgiPYMMNr8JR A+JNhvb8h+1ZczogymZXaL04rmS78XWzvv15aFiIXa+gSig7jUSl4uoSN2OJL5BtjWlrR0jqdPxi wwluNTY++PvvmcwPdADivuvEx2B2HPz+/vgoUSO9N+tMtGJqhPp+wwFY9QQuRqkTq84H4GZIYDxw vbP8EvvSMMNrijqqQBu5tyPeYSPNrO34zBdr2FGuh1CwiiEdN4VqMwrR8rZ9vsJN8ioL+UkVE2KJ orApIDY2RQZYxZcf9Rpd/qCRHpxIH1oSxBM2LQRKpHvNeYmOHvI6pIZeUxHicaCpfrzkSwxUElmw Ror9TlHM/6sUlCrTFgwTXMX0CszZrDQ97bmerZv4yNFBojefiB2Zj/sfHWbtFsFqNk4ckFD0hDg4 fMaO6I90ag26hcRJWIIjDrS2AlFAvec/evZWHkbRQgZxP7hOuZjpR3pVjPqSGn7SC8BmfnxEedqB RnmMwX35KbqT25HzP0Sepf7c2hvTzSqPJIXa9fMx4T0CSn+ANs91MCEQJ+4tjqx6rZkm0H9b7fGA ti98bb5UNqdLS/aQuOwo1qhBoWI8GX9Chs5EsX1KReCo/yqQQbhVXEODzS6TPC1NqSzsrVFdB3dM lg8STGMHAPmMmmEv+MnbynPAqwbJMV8VxxMMaBC5vjRknk9YACikSIgk3BsYhze+X4ZXrCIyPi4Z 7LDamLZwoFl08r0h4rpzM43m/NBTE1a5k56lHa0wrD4jedRkiDiu9EQf33ov1ryeLMWEkYKDUHl9 dZhcrIWUilCrl5f0xuT31PKLcWBCQrw4npEYudwUvihpdYON/mWwcEj2J4xN1NFduJrLwhn3bxNy yq/nYXMa5SGo+QnCWrTKLFeALX0QzBKtuh5HhYH5oA6hufXHJXWDrNhXXx6xTsfrznCVu6G2hWT3 gnuf+TKj8AIg8TZxyEHFT01/zb41N3l7njsl3I3toaBG0xyrk84aqLIATZHqBHvRInzwX1XHlUmV 6cLLC2oWrZr8z14+waSNdIHdccaMbgp1xD7w6EKzvtHzyAE8Y6whWV65MqWT5vG2Mke1L4EvKfhL 66kbWL2+/bdKUfywvEhAb7RVpvsGU53ZH2bBa15PyjOBaVDEfceb1ohPMmkEAnRJTr1Ab6IMwTEq E2rOxsOtLVPAmRVQLfSxDsqwvxx8lcGElIwmxo/MCtSTl4IfSAw/nqONrs9RZ5f2t5Yd0q2fnHJ7 +sQ5UCnzDvxuMlGfsNzwe5WtkGR3YQUXG9YPb8Gx1BPfAjDd0vPGucwTaSdlzz7epGx5QW9MI0bd j9+IzN2yx1ivJHO5paj/o60dpOquY3DlYYTVEk7Py1t1BJSkhVZFmJ/Gn6xBSzOle2kEUtvC+8U9 UMnaWBOdHIZmzS3BRd2EQ5W/1hfnmNh7RP+JjoCZtkyRzUKYkcVa0wyVKM7INJKWSvhnsRb9+Xzg RYkIkdjSKRlfEtTtWOuHuBTGrRsKz6+L/nSRQghbRVaYzD3sivcA00Gfa2Hv9hsp/SrLBCbJoQVc nOmtWw8FI+amDnAToQTiB3OyqTZ2EI3ChfQoyJJuaswA8mZHtWWg1rruOHLsuBr5f0xJo4qcjZDX gKsMxhO5VFyNu7bSp2hBQLvnRvDgo+YmPHG3ZE/KaSUHzHCjduQBa47qv4ui6kQGL8bMMOu7QdQx B7ZKa7+MsF0LSdu6+j+XW6ZlRtCltjajajpqDDAu8zBbtw01CMraDDduZeVv75zy0P7iefEqPXvd wwxShZsQmb6u1MuRU6aHpp+rHO/hw69x+yg6tZhGpH30EU7Yp5JjcnpHWfuOhptuv0BLqGnZkMKC XN4c/ibdrIuW2vk7E5J0AcSlVxa3qwYDBl7QL3dr3y8h5ZFOUMozdh9Kdj48JT1HB0HxlAFUIS2n uOHQwyj11QsSH0iD9R/OCdHDm7PXrO/J8+sn1DZMMA97aQ37gkjyKVJVtalmxv7PKoipe8heiYtx jROZHj2OiyxHDEkt07DrrNJPtRr68NkU7vrwbIybC8IvvlH9DeMR+Xnsh+YM/qkT0w+JE+WRBimR V/fWOEqwNypCKOJhllUKAp/+iygLosqYWbKX7O03eyt6xNee4/E490/5OHSN73QSmkE44isc/bmo 2JH6A82DnxjHIwI8g8+4CezOxhhzjnmHHqIMN7K3S/3mDI5yjPKvzdc2JzbsXEGOoBOa/WJs6Qjy /InArUyfGHQOM8hdRKmAy2EuDDx2p4H32Yn4TTRZ08RTVQ2SdpJgxz0B+fweMQw4yFMheixI4/QK hSzb8+7SDdeI92dT0Lt1Z9z09Wu7UBbO1tYq4jR/1MkvXWTAMCE+dtMN/wQOsrH0dC1ll9m19b2B acR5d3P1aazSWgt34sYjrkU4SK3LBsr1g7LkBfPDguagL0sBoGzqL7Sw6fSCHNyDBEi1LY9ZosdN GJa4cEWntKfcHL7NrSRpHYaVxwS/kf+0Kq/172OpdvqbPJq+TyjkzMQJstvBlC5dvpsNYOWOTnGx h/JqUhPmGUmG3bT6lFNZow+L5MN5YrxzESTiTiqTmvdVUmQJhTDmxQkdfL/3MXgtLwF278F4C4jA CIle/J5e6/+jyogFO/BKUZA0YkqPfa6TbXF02DsybJwgRm5HOjPcVuj/LbEn0TlP9ifQB681V6ND 9YdRLWsfzBpU1wjFxFpzSWpS4WzFgvOgY2S8eIrsMlYsMwxpmtyCNLknmV8BZlVk3DQFlxBoQnMR qP0fEBkixx9MNjz0VUwsKJ8YtLgp3BEyHzJIVyERMJGlG6VndrxfHPxS2hn3sm4QwBF60c0sMNEY hYhGVFrExJRM4ktj5F84r4oymqMd5CsJRc96XQtZidQL65pMLP/nfDUeZLvrycAMZU8xBRPhRJVB 7dgVmM19DXv5j5Y+flcLjhUa0aTCMqdx0+/MXC3jDZox4lbvmimp+iyPfD//g/4w2CCxiMwpl9RP olBibOZ2Iy8zKx8h4Ay0/E1YrKAvjEzsA5JTs+WQU98pzsNbGa4kvEt1zzWMYr+ZJ8Qq6eIY3YFz c5qu6XWEghmddE8vhjrxt3pbyDg5flbQYM+59xbNLdXnLxG9lGq+6XQMvEsbllJufeEKN5T2rvJI oScnwa6LQAN8ORt7JCZcB+ktOvRsA7MGSKglgZjHK+IhUc2lp0ksrQbq5TgmWcjPhRYSaaCLnBek N7rBNiN5l0kWFPwcEbQGEL55aJMCvU2f9wwb/2CCL4DArczgrd5of78g1qhxQpbHAecsIbzVPP2v N4YtIXkE+bSMdBNMQfsGWhm0V14QyyfOTsdhVkpZQxOpWDVq7SAcClcBPr/qEwQt5N5ceYa8dlCU IOh5+xoz4yRDsUEPCFkyVzJvENB+1hw+Pe0jIkERVQDb8+2B/Uls6DIMJp2ZPKfc//1d6aKseo45 v+OFhGsT6fYXLq60MQpvc6Uw5XZCDMCjMJ5t+7apEM1PxLYFxmaGndIl6z3dgS9QtgMD4arEJ7U7 tmnr2r5Nq7vakLMttwBYyouccIDfR6FpXKAJSZ4B1PKj7+ZlwRMJ1N+0Jq8m++wat8uJszRkBVSb L5upO3WAAe7/lJkc3dl78b0lG03Q/KTqu9rUflcxLVD2xRwc8lVN7jGG8u9OOcRiEMqwKa/0Pyne pqiAdci+ZzcWhTaQJyvcm0Ki297Y/igdJFla16RmeUhp5E/x/luZlFG+3yhCMtoGMGpCChLnDY9t 3mYRuIS+AuSJFQM+Ofw3e1mai4CLpPhuNMm3ARRYBwSEuyRYilbfkklkPOnkgcL9cC/j9KCwkLhy 4m4qSzncnPV9vyUg6iwmCGDgczj+T5ygSmkmmkrmYzsSC9oEtS4aba5on0lDVY6FwTFwRpan7ueT xHPiDpfvpjwWF7S8o8XmaSFAL1VdAJ7/a5uHk01D4st7IJ8d+1MJOcJGCRsO7iBNX3dXqegdkU/i aSE6saE2Ozz6lQaNeC/l4hfQX+M84/WZdVc85ntVjhO4KHvat0Mm2R54r/eCVIEG5UmXNAi0nA/C IxwErCOUsUXfH10yBxStBjFwjwodLyys7KeRt4DA47xJC1g1uFFPYuErs2JSqBwCrb2ZdCc7/6Ij TP+L6x8Hc3qf2pYS9YrQQOfPbxbACgPwSCXukE79llwBcsmFk3MAxoP/UTpsHUWPirq73bxfa/Fb wnc/D3wQBOwZHI/rYbSyPTUXbfTbCA9IkKoBaiX/WdjUo8GOAUVQNMcS5skaKZ4qi+4p1ldnWEaP Sih8+mXBXwv/36+5BI0Sx31MusIuQfs63lN6a/0mwFhGl2cG4mhUOWCrGvMjrxp9wzntt8msY1Kx CHG4bnLTUZmmsBV4VBJKOfSqcs85KQ/V007aakGnUQgTULrjSG1zQ97pEClPtZBeqxcADGxE3NJ3 XssS7EBC3Wbwk4d6g1oUW8946Ld5nXg15B4aU/KeC5mEuH4R+j+d/y2SJK5nxUJnOr3pKQuN5rkl q3P4ZwUyozDfvFfv3jKV4Bu+pNDyMhRHyCZ5sQm5Kb1WNoVRM38wy/oCHsXRkdMWj8j8Akuxewto 3Y1UdY9+gAZftvwc8hF+Tn9JeRQIuX5+TZtkLrvaEe7TupaLXzpdYX1oywnY3IKXSR39A2lXdCkQ GvlJovUVumj1vYCiWwFJadl0ii0KQKD6J7hNotS4qDf8YnQeUVneo+kVwc2goaojYn/r/ZuPdE8c N1rDk+OZnuGjuPfM1WDN00gdWVBj44KE4staKqkcpz9+K0RLSd6x7bKF1mN9bZZCloHaDjgrffhP wernSQT/+luQdqH/+Y+NT/rT8AP95UPR1c+ywjuVfqs1cStUbxuasjBpqsQX71EaM9tNkUSW5gd1 EIYrw6piMWSmcOdHfm/P590S6NWzHJd5JsCbJ1tY9N2jIYXBKJf4BkqSESQZ1Wp1TQusO5fWSPdy Cm+altQoxxvlWwwV0zLNx/HmcuMZHgIrZ+NQXc3/M1eHiLGBabRmNo5HEsclC+kVtHjQVGeVFLDz Gs1Dj778wFCbylDeReTbK1ISvAEs3wzooTvWznKeHzEpfD02xuke71423tQ8Auw1Kg/YZ/lMQwfr 5NSB5X23slpqlWDiSVXiLP+ICUBbCvEO3TFWcfsZCEE6ivbsixgB6s8MT8DRpYtRBSIlo23U6DHa UKNObeLG/XovTShRdET5FjOvv3bpwlFTCUdr2nIEAKDD2LHPRJwoNIDEmOwJREI+UegjLOnkLf8X YA7bNIdMF+hYRYsBo7UXMMCGhhTZ7HfQX3ABJtRcWmmhoZvp+3ercNMLHU2GdVCIaiYdwHfOQ6Zy ndkHERr3YFI8SKwpNj7Nusy/F3GKkAS/TkEGfZ3rNupuVz0oTLqdH2zvZLBV59D29LBZjsHUKbXa nnwdQkcTSHIqnYSX0NJpJh6LX46XRNQpMebHs8FdQ0BY0QcOkyt3vGvY+kkUjfW8ww4L7wWmVZAj YpXNsHy/t95ll7GzdrpFkqcEyb0f/zm02M0dMusm7K+9iA5UdUqLJyQFaELeOLD3y1eMWeuzeAuR vX8PzB9F1KRfH3F2TOC6Rmml19ndxJQ49Y8RVd1jHUt5HsrQ9UkU8K+ZYnhWG+e9vB5rU7lyScjC moxkFh1zYWQOwPa6I1oRmXKZ7lx9JVQ2U63AUzhXUo19ZVvm6s80VOMlMBczlxazb7Skh5vbbAH8 vXHPwvxiNKJTt1UylvPdnkOUCPL7kfcmXifLu7dB6nZteh/MDETIGt99F0qFBrf2vBgNHtqDDbjH Bpf2xr7xFFmH/HXItJDVw8bCUyw2uJ7yRe0LAlP0eAvjEdcpzfcgOgBa/TC12lt+zNOiNQgAZjQP rQRHplLybfYdUjWC1GeQCQIAHQO/6pjbmLhSOJTuQv4bzwNmpj4ybIUGRgzLsVypHANMvvnxSgzb oq6jKQUK/UiiT09I+1ZRYUciQpAIea0tfVSaYI1U+xEOurWgoi68q7E2h6C6VY0X3PwWp54Ch0fs lHoWCDrumNwHWsUi/s743g72ou7ca7IxLbcC1yDJIyVRrKw4AXN4ggZB9GO+hgWrfJi+6Cfco4+6 yzECS9ie1kecyejotlandJv76RUrvl5FnNbkHZfaueToiCLB871FPw3vCfJfMOJ+7d4GSxQirOvv hdBv0VZKpR9fmwWu2hH/PQ90MeHAy3vOE48MVElieCoqpNEn4E8mwddq5VbHK9wvCUHRqVU3P6tX vXpLZKzBcgcH4hlj/1ok0w6csCq7a9lB09oyZodyjxt5AcpUM5uJQCXbSDiHX1Vr50PuDQeM/VQ0 QLTESPZO56Y5ytnz1oyiclZTqI01yRaGFFvkxa6g831y2pJcHyNgfTsoVfT3leG7u/np0QaAkP6H U57STkj9gSMXq+/d1yg79w59busXeNhUWruCMG1JMaZvEWh2x4l2erCV8SVb8uKEKpvL833NW7hp 2+MtCTZFMXRPPeAaC3nT4O82Gjz7RM4scySbnq8amLN23OlOu8dWeZhyNB72tUAYJFQlRJZqFVNT PTVsoX7DcgQn0OJFvHTrsmbTbcyOs54Op6BW4O/q2DB3CuT50MB15sOr3cjBU8bEGszbhkKAuao1 ngbvaK3p5flK7xM9XStmra0Q35EpvCsogR5ULUge+p3gfU+6DTwKIq2xMZYkuXiBKEsF9cf+Dtcc n5x8J2l3TcbpRfBdpkxKCghZgfAONSpCQ9OKfaGqFwSGE9y68nOfc5OHpUq7NEJMlI3UT87T+pQl mk1VZc8YFZtJHcPjNjnkUXN+0PrfR6cAUEj6ik+ZumGcJlpAkrjbrVAsGbvgK7XDf4NihudooVA0 ngfiCKsBLn5K2k7RB4AxrYPEAwUh5rPWPoIP1zh13r/75Pca94qoABRBqfcsMNQLJswxxNJcxB8Q s6Yq7nir7S2Y7Mu0aX6NjOyhqouNW/jyjAuQBj06euchx4Cl86bhN97EhFPafAuuoTpHQziDDpH2 ENSq29QVVhC8Mhii0Wg/69EmVLxmXFoQtXqQfcfwdbJF47zpinO8APwP097yJpPt9DVBK47Im4Z1 jXD5PN4kAABVRkJt1cctwruCjxmn5Tl3nuUsSXPsMloj22JZUezbr2Z3M365Kcc6zK1CLqQBjcCz 0GKCNHzes2qzkVpLPG2ZZW0t3OdjpySfhWdcFwb6zoi7EQZSaMIBT6Cbg1rdvNazATYE+Ji/o0RL 1wlvX/OWImPDLSWgnuccV1RmZWn1JEhK84kEJRRLqioyA5Pft3smbEnYDqrcDiG5s2iQTCoH6iJA eRdjaaJscdQgsRrdgUGijI9VPsrX9P+NaIaW1fV2h4u2JodYF4Ir5ja+1LlqDS56j0zfX1A2Jec2 Vwr24ZoM++82OfZHvWZz/LVq96pvo43YxtFC0dn1oPFu2lKABAA+GsHJvSJ9rBafDBtzAJBov4UC Icxec8wtThO8vj8A3pJ4deBoyN5Lymz5LPlf+F/REFe8H/9vrkkuN0XyMhx186XXBy2LgfxGHnVF QwKf136hMzftvyFYiUfr60Uqiux130Qv0XpArjXC86QBYsRaE7GyLL9lyNM5NxG7y+vxFJTIf2nw 20eEixVRbFxRLVlXOXOvEUYK2DKVf2dlhLMgtnyLoWt5tPN5GLWTF4VHX94fwMwGU+vIa4d0l1eu 9L0DKv7soa2CvSszUIhrQTE61OmwYvczv7O8p6IzId/HtKQuW0GZn2T+2qYn9lwf7yl85tCGDN6a udGAr0QeWpiTLpq0E7YI0VsfTEBpIvHJbj5RVyFJ26fLK/45j4aUn4N+RJzbvktEWqvB0Hv3VYce nv4Gd3Q9CKvfgKgFrXx3pgcg5/dhGRfYhI3utQncu068Ws7suj7eFitkmT4WPagPkEbxl2+zuJ2u wh8ddLwAc+SL7aCMhb0U06qiEjOakX9oH5C+yRXchsDTD1Bs0UGH7wtPwqEasKRsUtVj193qHHOb dugBR87QosKRshpbxBNE3EFgOh2lK9lkZTnWeUrHvTE7xs3464EL7gIUyHgou4PcZc9HrMMO9Ne8 xpi6XStUxl32S4SEUkAx8l2OgnYLLbsfE5s69WxVhHGIDX7iFYwZ8cfj9zI5t9U2CdTXimAbkI8y aEG/FZou9NeVuSfN2+00XNrNzXcsatPe0OzYwheNnBLBASEkfm3TQENllL/gkQ07FoaFQtl9k/1w Si01dv+ShSmqwz07ZS9bUBO2KxG8hh74yrEQcvT/9pq3OYY6YEuORorUmgMFNHim6phScpd0D3/e RH6yc08ubbt7E95qCqYaHcqbQdpEKHAEVzBSRbeCh/CAKA2FUpawKmSdIkYOY9dXq9uOvh3eVKpb AHx3bfiDxMwAcOtwqUuNvu8bqRqq5rfykw7dho1WNRdL7ywF2qKbwHu+JH6J73i1FIEUUFQFGX2V TNbqqPmMK6/D3tJFHdvuEoQRLoj048AdY0u/gyqIhUeWtwFgn13SJCv5OyknoeQ2++FXN+B+j/A5 iRWU8SBG/Z+pp2NF4ekUutptnM3FHltghaIhPD54cwRyztdP8sLYyl1zk/EgTYsvWIu/VJZumDOz TpIT/e5CKHNdvPG5EHC1nxDZAnGRxKBzU4J+5tKt/uE9JL1Mj7y6+jrZpUzC5DqK7Gbp6+gS9gpk GMDk6edu02WpEheHzK03sVxo7Vc0fFMWarZZ2Tddt8vd7AgR4sWbIBPBoa/rek2nnZ4zbqZIZaTo 98AMjFJ8Sb469rqHOpS5Xs9GaezybAOo7VHsppQnkQ2ZVoVhcE53Hnku1RzFfEoqtGhUiOVPU9IE CqM9uXCf4neNJ3EyXBeHgCTqYb1OZuCE8izGM47Qt4rWDCzX84HDJn3tvxTf0JII7xs9WGRjB2CK UzABDu9sBAqtxLD1OkG3uUXfawD7oKsoD2k1zBpZQD2I0NDQ/Q3rf8wZRGK0UfrqYOhHaWTU4bYV TddmnW7LCYSxkUvjTcnwqNFZ0FKYxjc86zm33/a/jqerh93xaQe9N94iZMQlrqGA7QR4vOZ4Stcy ZJZhkupVZLXFNutmBFpGIfPy+SpFl3Tnz240Fz37P2iPXlk88BVEjMWEFz51zBHn8QgO+p+5QIli mzLCbc+4ABDksFUobJUXISVI8PVIA/EfCrVMKBQtIbU9M40DaMhtItHZIYUf5IgOtyaKABmlBc2A LB0YBsCxeZC21Cvq9DVNniI1yesJz4g3iHZ1Dnk4MgxqzXJQqONZ0RZTxl+Cfo6jpnl37nL3P6ni J5BYgKKQlK9KgtveTvaN5PbbRuac+8pULz+zQv6d5vgI/kFIUhTYiAYI6PQIpo50pAZgXEeLyFvw U2fEV85IezrV4PtrzMzkyi/weBXxRVShN4H46peM57HH3Rtbot3Yd5sfqji4jZtipMrC1b+WLW0Q fuEAdwswCSsImbU2YrwhTcDvyuD9n4qdNX8v6pJThNnjKDgEOMk1mIgAHEn3llyIxsHtBBZy3mPG /9T/f1KZZzyCYk81o/oaB6j6SBMlfcYkgclfg0kgbzUvPKNM3m+pWYS+qgFZh9/5gNGTzKGE4K+V bz/AP7nU+r/gIvSh7ULmirKf18tHNBnXHjyMyEuf3i5+l7pDUJFB/JYfEdQ4cpdooJJZZSqn1xU5 CAtd87pBbjM2ONYjRhbOzI+PinvxgI58F94YgCv0uVo3uy4RGUayU5RxagETcbT6Z7nqwH5YIrJd R0VOtl698cNHnERxgPvzEnzkMwc7WvBJ8M92wBREaNwE8xjmBVgOFg56h+gZtitNIL8Mb5h2W6wI dGzNuOazGNlk2R+fnJHm78DhB2c+TeP9qxjnP4uPinzDsehzfwL2JBHFepzskR5SixMEzuZKem1f 61aBD5LdLJl/TJI7C3peKAjDGwpnWGl5htKES52THb7nbxdvjEnheLpf3p/ojwmxTk56SqoqnDiW 7bUPfAWFrPFabJamYAvQAVtcj7T5WjkOELZZwJYyibIayaCCxRkOFG+rxh7PDsGeEgqmSbCcDZbj DaOnZedBQdnP+iuRh8JsWbjaN2tXcJiMM8aq6Ex86OpLY4F0mABo7BsuLk1oCrjeI0rkgXmafC6Y 65Tz/6wb+XGOKEdhNUmOe/4QZ1bINy8MVgAKB6e3ZR9ywsXIjpgqlYdweXHrBlRlZQbY/j2u4Dvg +zDYxbrDB1Cf7FCt/KCugGBG+hmLW7c01Iam1lRr9cJMhzyiLQJo4nY+L+saYJkuXvCix2zov9FL Ecc52mw5SmNIVM2n+SW8UbryUJ8yknZZJzat0X7/GZWUAEl0YcPXNrqArhnSKfyMAcdiG0OoO7N/ ZPfhWHmbVLn0VcyqJce7OxZzqEPbt6HifphJo6axSnoYT6V+stHcgixoEj3R6h79FUViueiJtibo jHsd1+wwoc+gNiASPdHSDURXVXccLjpy5WYLUoFlicSPfGgf46qxLZKP+wnDUOf1zTFHedRS45g+ 8bLfzK8QMsLUW4HW+XgwdZM766goieJgzQuKneogqXLdVRUkS6wMYNuf1AvvrzaqaehmcFBcjlw5 UDmOBwgaE+QKnBZzIWWF/Zxh+n6T7JzDAdggZx6RtTkel9xGM0plNNFHaZ6hoV3eqaB2BXR9xTI0 v6hgT57+VZvt/Aho1cKN1GdQ8czWSZ7dXXeMqPOuLmO6XGoKzTLDP5wjSKnwWzQnKm6w8dKHUJsT M6p9kKdGEDJ1gSvWU8vVKgDOfQYMt+8XOpVGJn5wNxaUPjPcBxwVmDYJeq9pYWdSy7d4ztkglGzk kbi7kodQoOPwC6+zayKDfrMMcpuU3K3NTp2NDrwfcKEbOjLmzhl6r7nnviLUT7VMpuGKCQ8+y8+R fQikzOYjjaPHQgl704TUgM7U9cMusMhL3tvCy7R9hNJGxpS6ed2USBEipxrUU8xtqzg6l8QEPapi a0jybCg7E6hrGKj7dZZnACH91QhDIe70+3pz3jrRbGd6ozZHo1qpHM+IZ6Dzer+NL4vyh274gzzF MNfW/t9yLVvKDYZlQdhZfl4v854czCSJ8L+wi2baawQmWwYUP+dr4H+dU89rR7bljQ+PJfg5qaRe 9TfSRAIx7o2Eo6K9Lcr3ccjbzBPuisXbfMtXLghImdGlUhArQXdfXYx4udIFGzYbPZQJk/ffxDDu VVTycMVMzJp6+XkCrbjokPDGrbtdmUn6KVIL3vWPc5GGSzsYwP68oBVz/DjDMq/u1Fy1FspYRmSq g+z56+Qw6Yh551OaxtUMEAv53Q7jZl3nSXxot6JGHN23+6VQ5YzCcdC/zZbqpgtkZ1FP4XqeDTym ivixKzePJrY9Df9IMBABfI3EkBvJL213mjaIjyYijH1fUvH9K54M0K0qg6vOoTLcXD8wkowsS0WO qSayGEgPHeYHAxxzxgmRqFbyhWaU/S6J2MIhy5z6vysmb2165w+8AXm/GW1aPemlSxXu5qodhJzf VFzbkdsnlJEVPAqtKsy5kBs4doUQ+qaNIqvt1joc+e9bqlumzh9eDPCDKs71F4/ei7gtUX1hheu2 uCTrCkN1odRJBX+62d7O2MbOAZN5Try++UfPy16/dK1GadJF5JLZVAnY6+/ZRxKJcnKkX7aQDVbl QsQwG1gtVzJR9FQg7MoINrnUK1to8c3MnESFh6Qh2iLNH4vJf2X4eTkzD6xGMR4s4q+/TICCllvj UEHVu33Q8LulydSumBcZHtiayjEDi+LQNq0M8ZX+0END5q/gR96/1ufJcL6ksv1LCJt4+wxgCdvS aEnll0xmuPWrrGjNn03qZgjj8k9DewZcoGEDpG12g4N5MzGtaSDrU6lPOpN4BtefwQsZdH55d1Ba rXQ2eraEy1U0gwNBHc9Cxrq4FOJYSHVA3/Yrh4rz7YMDJsqd208t4klEttm0/OqtBoUyvOsL197v T5nf5Z+fgv03WR/3EJ3SESl6nRMaGXye5Yo6LuAP4u1guRCwstUe6DX/kH1EiTIxvJCJkgUvHrZj ijs2i1QGf/kKGvbwfG1gKUJLA3Kmv0zsH7ccIpEDe8kgIZyOPp/mK74htyAB24eWPfmIK+5ygmS5 uiWKTvYBWu09MvP5WPq+ROkEG0jNf1TjvMMugremyY7Hh25sNCXjyRzhEqRYxcuq2OwSzE3ZVGTi gTnp1xq2pyzE0ITa331Co2HCGyac/cwUL2mu9L48jFyLM6IiwE1hXQll5x9HMJSPgPFTv9ZJRcd0 dwdgPVhgDmDtfNsC1QslwkjqYE0XbQ01JR1P9rMVsBA290jyxgEArqH+iySvU1i61B4ICp8huh9y OBRjJMlL1HEO8qwv+bJDDLPiz7G8Rbwp1my60nvm8OPYT804RHWG3SGqfZsx9YALH21RuVZbKboN LFhzn50vd1toKFxK7GsZIG7F4+MurNZUvz+qoT2w9Ea230YZdellDByawo7enlh5GydvXSvuCuMm XbHhoG1A1uaf2DiQxYpUrj2asf2C4xfiZRWqm1MlvkjWVd2QRodYEryPwICYXAz6zeH9xnxFbESk xrQt7WJKeGfMuoLeVtaiOQluBmgdZjlVR14K2tI/WcRwQAiGKK2twQQbt9ylfQJCu8TzV8JTDCSr OSpDcm1o1BShH4EYNpL6s68RsfXl5bV6rtd7V7JUh2vFryualkOvTenVMRl689Z4JjTbofSYZLIE yLCjFgYXNTlbr/Ij/eobwD9UrHoh9AWe3u/mH1bgW4KoTl4v4qic0U47xQu4yNK90iDoPZe+t3ve 9TiUA8Fi9RoWrJIQF5NqrCjDrHpFxgJg0xgLK9NY0daheN+GIz9uPdUT1uwabUIOxqJLgaCzUIpa wDci7dgk+ZozPTzZktDfFFiP0A2wQzJNZHJGmlhOpa/FsSAxKCmq5eNuzNMNwWqIbzIuRO20y3Uh i9x9ZliLOYbuDzG8mElWH1KIsS4MJ3RyTg7f8LkTiee5o/m0xeSZIZOn/XgKkAlLUshs/Ksb0hUO LanJaEGy6IJBDIL/6am5ktDUziFH3yE4Sg+4dwX15P2rsvvZXH9GI9vW7YrYEo83HO7/yyC9WgfA 8QEQC9PRgW6h9wSQ9tu7l4tBEZ0qiIh82F7vQ3joIvDNTjrarmxbiLOWbv4IXg3FS/Lkhydx9w96 LRnadyFWCFXQ0U0a0SxtD+o9VYTvhG19lrNEkJKYtWQwp6X8ld0WHLp0PfS+IxrUnRyjJC8q+QDw sIYRvc6Pv/9vt9Krgx3gdV4vGEMBBPeWu5Spdrf05vlb7xpFqaYWdBfslbF2Y2q2MPC5EzNyqMVM s1QRdYx2/8iiTejP3QSUZ4zYzTneFE6gkzRyjhbXUopNvVrpLFPnF7BolmneH1tZ3c+/M3TD/H+D CvwnvCKjrCj3DTNgLcniCKi4jxPd4nn4Ii8rmMMq7axhstAwxupltxZ14rE9uU8dRCT2Y42HArzL 4eR6P1S5S1b6cYkqgqF90KZxpBHUwFkYlkfVhdfQPdNashTjZYs7SUyqlFbxLiDul5aQMYwfnRND CM52XWAc3BV/Ilb1bXexAAmAx/MsVHDxdVYa+drYsUYnlo9MCH99DNa7bug8+MOKBx61c3gzyXDz 8iy+Sz1aTF/Wv1EZNzhsxKb2GxBnat/F3hCUBSCGozjMG+cmgfNse4RfNUUQwyzPEtcG/vgJ8S1s YxR5qy4kUKmkzXFJlOqyAIMYzJGuMkjheyttqo74Ie/sV+DJdJnIMY3bvAjvskr9hBzoRiu31wy6 r+BsQ298xT6oFEPcL9r/blHOFfdbIWaqDjGnD8Hj5NTcrsbbrvgW/RUYZA6D8iXFY0u762AT0qCw iqtcVAEBfqYTYRr1N2HAfmhorhUU9TYIuD/0icKlG5mTPOBOxXWZXRSQMYmJOn8pCiVz3A4jhy3L 6R2JyT8uCor5x2SewJ5kkGouxFrnD2o3UwffMcLJgsVF1jj+kKnHcajv3UoMf1Ga6+FoccOj9XHs BRaJrSZFO0uPxoI5vhcbdkrlVPXq5M0vVgsBRbj1PluyKcXhNgDMv9sauqz3xpUYEAuBVLU5XsPD rI3XFBu+LkDSvr0rcrpR8LYqL1zGQUzMZG/sY9IgU3Hq93rypMhvN/80dLrHRUz5yAEGbX+hzHFZ Yt4xFW+tNPwh6XKiZUSsxnRdNhFnEqr2qL0zDW/1CkCY93hsH7MqRvJSfCgBnI38kJYk9DYuCSR1 kZSM3o7ac3JL0coklTbdlnObqTSX4E5vyPbTd6ovr1yhynelUxujqObNJsJXngQHT99n3uCVgwGM 2fckGrRYqgFlmG4UAs/EnBKZ8nD236XovkZzv+ZL16R6S9NTAfVyWjomK/tJ26fJHOYLfK6PFc6q eEcEODj5MSIhFg0BNlDCsznR6PgyawpKP2E+Fx/uScTv04+1/KybJR85dFDOnKnSSExc8aCfuYWJ /wAYqeKZbEUDhKLAZnIwedcnVRI1N6cT8ASdxk32rDOFst+2IPSyQ4u3yKjMjXQ5A6FQVa6XLp5y A8fgf+P7Y5DTsnS7YxGNlHVAnRORR7u43sez0Y0w0DaPXBInY4w3G7j6qJBdB2nmexOzw6FQa1tN uCXXugpUY4+hStOrWbecYD1UHC6QdA89QS6fJ8P1uDiUdRc0tVrkoC/uCp1DDi12Owb6xLP2qCGf Uz2nRwPcu60EkI7x7DIpEgXNjBzYnMe+c5Cy8EjLV6LNEgbXbu3eJwMTqYqAc6xlPBlJ/joonsxd njtrMQunV1GiekHeyWwG6C3MZXle6JlgHUtvIF6AGedDv2aSzuAKtiyII+usE61hdRipZjyLB3yB 0y8fGuMYuBMx0JZeSURFCv+zfcY0L4kNLAVbjknDHTLwPYhcjlTri9ws5dU2xWFuag9Y6wAt8TmE jUi3KIpywEBQ9MTeNykO7KzTMF2JxexTPEWCvRA5MlvqTBFYjXJ73UoLoGlFalzoP0C99Azu5N4o mbJvSNZM7dqT7NeqL1m7MxzmN3qUuw08/n8AoydvZVovRghfcoeYS+qgdbZWtot5W06tq2TNcrzl KJtdEAan7mdx0Wz6+wiYf/s6YMypxrKmjt70RBfkfKWEUQOKzJG334HcVy+nMUqLyVcn4QrQ39ra Uxa6ISWOR8yrmajFFjOOnKQIC+VlF83TYljRtEd/6UtV10mEBnPcLJsjseKNvpNS2DOfB1Zp/jpV z0ewjAGow3juxuWtFNax+uZqww0VLLyCamvb4orxB2NHzbZV7xML1JPWrClF2P34Um/UMMmMgvka 7R4K43mcPV9amD0Cs4RUN4HNbLoiI/scEVg/Cz/go/zKYuuLcwXVefjK1X8ijnMDi5+p/TJk0QyN 8KwOpvZttGONrVg78MRzalocw9TmWepLTrGwkheupdsGM47gz6ZKjum/YjkVzTUU/LHuTrMSb6dj UtbdZmJkNUIcBw+ac4MM8sft6T16Xjh6PCDFcJITNv06TrIAWWAf0Ib/Mfgj4Q1XCXxYPXmgdVlg hzg4ihd6Ofv/p2/ieSCa29kWraJg7JFrgCMwlCtZQHB1A9NHvv17yOnrth0QXwolOGCokWV1vCOP vz5YZ15RhCgpPoNLdfPCW4enWUe9ywgoSNCEEgp4oMFt/cKGPjdoXX/pGgTnxxYlgMsIYc3JQEiF XmJVqLiqaVH+//M51pqSUQvti+qadx/lygARgk27+fOg6o7Lo5Fq9AY4IF4v4xReI+byD4WXIm9W VQmP/dq61exn/dsNJu7GwF+hk0ywRVCwefb/BQWPrm7XwzM/hgT8S0Z3djhl8aRUuG9EI9+RGzay OjwKjngnXI6HFctY7Z7V52mQouw+s9t8HQ4wzl2Znvc0FPS+XAbLUwf1xrrZed+cIzV3iNpU4KBK K/7R8NEUTNLd+Ry8w7pxCWhhDatoQkH9UDISnLA+tfL4IVZh8DEKTyPhmlXPijSy4FC0XmY6Cpd6 4YBt5AHrvx8bX2eWFFG+qj4qMPDayfIyqBAgZvyAY4oqU0UFjd0+2rq2h8QGGYt3bthQ5F0nXzXA FX083tAj3R0gj1jsxooPaZoHi9HwGZcbrVOpXELY+OXqTq4EMVBb6cweEBTYGfx9sZReoF7Df5BK o+UZ5DDfJDFL2+vY4c1eOmC5+LwVTV4bDHtgpDnUSEgoRg+43tYusQ/fugILHv8tCu/Q/hzhp0Yu zk+b45CB4Y/0b2gZRVskNMrZEpEEm7yUlmsQ63phpm6XOpXFxBL52EoUteM73dpYCY9a4B0RSCo9 qvTYNPqxHCl8BghiTuFgfhtT9PrGpZ1UelHXwF1jeSRWjliTXLgsHijltUT2EwjLEL+WCaX9cumH +oGBlGEPAWCFiOuC6YjeSDyK0OdNr3lzBdNwTmZC3/pUjx+CAPXfCEzhrUGvjUDT1K5dQy4NVQMk XznuCtQVwymCY6mo33kPvGFIOLSn+A1Ny2s2trE1e0LbfHzKSw5TNgUzBusF5/P0E+nHQjI47FVt V81WmeJZQ9Bjkysu1V3w6ZpwSWb2ZSSjn3zRAdAb9HjtMIh7TQtFQjEBLHcCSO0IS/lXTTHT9whs 1BXtZNJo0K4HTYtN5iZGyTTcwLQTtHXVecjPe5GVAy+GTGUTOCylyHOf7QDUZWMMfb7SZNMDcg45 mTUC+5wivWWS4zvYKn30cM1xjpk/q56hwMs0cMOlOpgVcXRfw0zBK8wyT+QmmSv4yvulKOFPkTyv LY8xiGVUIopraklFkDDICWn/RDICMqBFLGpqHoq+ocarjIljNxHuMxZb7DiVPTw7ADmQCbDB90xI 7AuKCi5jKp4ePQQw3sZteqcfgw9hKNRAl6OAwCUJPwKlrdXAieh6lu5uRBRR1SgpNyIG1jYtgKcz Bqlm+RcCrPfcPycekyfU2v9dNupKgpHHJW+pyOf8J/ScIJpDNpamUTd/kzzrNbbVMsLTCS2ZI2d6 54StwXHg948ndlq0KyEbldUIigOhv7b8S38uy/KTeqNnQ7/nTjv/0+wB5Y32TXttVG7WVhmXiBv/ Erek35WaPhaTf0+mKpjskSucVWPzuYm9S4vzlcPeFVXJ7eTGZonLQUTnbjjzMz/GRhwq1nsNfyvq G7zwCqYaBelplT9LWNRIi7Qwwbl4ZVm8gDtUVMLx/vI25PpUhiqaUW2bh7kon3Dm8ERrVdeUPByy zSIoDZwOUThcPTtT0ucky6ThSaLUdNHPK9lqW/K+e7PEMNiJ4qUqnscziD7s/ZDB7+697bmM4ZzP XHh8acEsc2VCdhkCiOP+biA8SUu9vpM7eexaWth4Fit1jIFxRKhLn62Z7kdfTcb0FtU1GZpgiaYa DlTNP6igPN/kcRZOQ5HGHBEBfOIak1G0b6QYzNYcuHZ5I6YmlNrVuE+oNEAYtVl/Qv7UZBQwjQvq yrIB8zieisNJYBBjrgsHKOPNs+m+qUeuo3rWQVlAxzaERdqvvls1VZ2ZxiV6vE9ZfqfDUqExI/Uy z5DDZ5GSS3Bd5HyasuvGz3qWX37qi5w2gnvv5Wh/2aqXSf8jKE1RrvTfvF9eRYN6+cxYDfes+jZC KT08G5mAE5YfniHZk9f4lqe+WkinxWU6JFQkj2GrzEr2U/zBNeCLZNdt+8MACzNTBWzPYpP1De9+ Ta+dqTwufiyTethxx5/us/tvfZv0gTHM0TieQiLbTMVlVfT9MrfPf7hSKe6aSeCo8zwVe7pv/rgi ABfKi8Q0iOdTKiBYm5hRzWQMMZDJtY7TGtbqBonUt342TPpZCX2GpcP0CsHDo5xwtF1rTpxzKynh WU+C1/07r/DUUcsfnCybYvmbFbOP6mhFKcvI7/0QvH6UBEe7TNR+2MEHqaW4NUQqzySMhRblN0Rr IN79JPu/iCtiy+PrmBRBYJIvOHKSE6NZg2Jwo7g890HznCRUCi3H6FhvC/2rs6MsyTUsPoMQsDqt bGlTUXJwzuaVIcWEoXzd1wlylk5Sxk59kw9eTdND1uyAOQcivcqiAl6765XCg3wGlDdxhmVkiR1I N2q6Eu8U30aTeBN433PfRxTq7bLeF0t6ck5eCdA1xE/bJqIXxNk/jFlXwh7LeGil4rkWJ12Hus++ eDtAulkF2RGz0nBb/q5t6hRmDws+TcTVgxov42Uamc1vv/TY2wZHY/pmXJuBNnZ1SEbmuKkk8qMp IydBC91IOg9Ds1h9ixYpxqnymnWTkgWyPNOBg2utmYlUoXucnev8cwD0qVPBDTwdRNbetEc+mGbY wSyHuV6YS7LjMtMS3ujchTmi3iMm+CinhTN5NGuiCRpyD4oVseZbRM6PxcbeG342I70DxF58tnfo rZVsBGyS5qaR7vHQXWXPqOzZ5i+iM9GXwAywzICAmoInlm7EMe5OKd4GNCUByv5QfCTOks0osgYV M8FCQ7tFONfhq07auLBRUBDC9dcedpIo3kgOiCjO/64qrHx0MsOpSU9WinzH/0KpifupfABluyh+ 6Yfp3RiuLljIeaj4jwG8PJDILPEZCDAE/uHNfS7iinsnzHMtwfgohehCvFCHAV6326jcYbpw8jbV tPLSCESECVBSwhXkqgyFRCm8YxHeZbGwhttxfP6uiLzN7/uJYMBZQeVWh2GXvNDk8fDh4hUU2bRP m6kvgTDihJXOErS3Kh71ONTAQMuLmWNB+14H8pIdQudmC9WmPJooq7YZkofgMnC6l2QAgv3uo3G3 cccbND3HW7dM6JohU9xEOwvKX1IYr2Cpiyrmd2hjkXEmkNZJLhdvmf2MaJb/Nb1VEE1PZeDAjn8E R+pwBnEvdhYPqAk4/q3n72qI6jdTUYIwbUfY3mbZaBIOwoQGz91kEk+3SAquua4aAOa/bTwur4z+ 0VnojiFt8MBz1bH1HnYWB3E7A/I2ezD3N5w1VvYivRBG4qSqrzRufVSLk8GuENyzoWXVKTMxuaiT sIb5uknn7cXdc8uGzRsCh+t8Fw8nHQPshgGMxJF0bo6u2l+/QEAujEGRhd8Oo7Pa/4FLLkPPewHJ tlhCFYG1D+R7oC7l7FmYddQXXLjJkbkTBzBT5Z8EJS4DUyMA1LxiuyGc2NvNLSfHkGEPr/49xlxg JqyGi2JwoLLP/bQswL3YR4FYkAurO/1WA9cVSvJ4YQ1XbNNpScp9NCiJO2w5qc3KaHS6KRiiKkjf pHNFzRb6JNeiBk1anio0di8AK2T3Ux4RpHs3zjESziulf5KtLi/qQ1sVmQ+LT+99uzIWM+J5DVVV ZeOyzfGUr6sOV4DIWylL9W9fY4dRa99qCIwOUGIKSmAAg64DzOb2wFsbDeOjGyXPbmxQCXuQEk6X YHsfXQWzg4cHaq4FZ2joFYVZqu1mnoQR8AW3MpDk3kau9BwrfrTd2b4F+toAvQ3LNyIlfArTLeqF PxK4KiDpZLiS+cgmUubIN3fE5cPSwXslWq4NAxexTWIHS4vXgtA5bg/LSTbrzrMDYLEkbtSFOHxG IdwfjtsTRrvtrVE7WIU9yqarTgYZJpY5O/Ta9ttESALsycl1EJAUWcJK4b8Lk+av0xlAbZslVR8X xWpOuVVRok9HEkomz8hJ0clFRTeiONMPmb/rHoZq62eBV28oyqS5q684GTWqUQStaonN3Ush6QXG A/grlxpf9ozLZmPRJEdqM2sc2F65rWK2ftP8NLU93uouTKzNXycaNMvf7yNkUfx1VgCrluYRZ1lM a28Z7pYuJtFcrTJkwCHPNbMyNVRtbmbpBJqKrBlmQH8M9V+PI3XGlfkLww1wa21XST4+NFooqDrm +AN+O661cF8rAwO/SIPkGXz+JvVFcJSY4CCt5IMHKco/aEt+l9wRoqO1GKZ81XLOz30Nipynjv3v EdPrxKrgJqzGtvfl0H9CTbaUiodGZnxSFz5v50FeKFjeb5TPbUHuELIUGw/yMFG3XvBFeICKny/M MR+vMqm6kJul6ifYCyQoNhGYGhhEU3UH3S4WT0RRUvh6KbfE4FuS20OO5iZk67cQhOEnzrUdgw/g 7FfCeErVKvm4nxTn9PgW8VK3Np47J1O6b++MSdPuQsIwfIQjJTwWzmcDX32Veiwo/p3IT9BNfFO+ 0WWtyn88S1cYQ/nWXg2R/AdovBDj9ZAsFmbtCb6iWp+1PIR6GrFYmoZM1cyfvrcGk30jb4dnbV3O bYXttWMMWCCDTsQJPXsT4xkd9oTiBM7ZRF+bSt3cXAyqigapkmh1/zvwZIUiWnaKMFvP2ShBh78g 8JGF8MV/aukk2OSVSZ8/qLC6biSf2b+ZhcIsw9UDaC5l5heSIZu7UxeZHdQEn4TIuHfyMygYRgPc 8V5KWU89O3wx+ia18E1SjgehFLI6r2hVp1ABasoEnXG0Bru2/rNNSQA+zD28tI2iNFlMujR4yikD uELT0CBIEncmI/iNSHTqd3w8x7gjxysJq7ZX0buXTcXMSTkSYYWSm2RLI7iqc9RE+Gq2SqFSTuxD fRu/C+d1gqz0EGKOB45VR4EHoP85BpVlnQ0aSiZXDV1wJ09mzbUomTPO5Pe+POTeIWP7L4VquuRC 4/nKEu7IeIcGbzBS5xt4Wav7IXFGMjAe/Ne9A87rNOmRlxTuIA2OTf8u7hiP0n0K/3QunymyxsmN bHi8RvmDwyXG1XiOCzY7TTavztAajJuqMirMlKdKMO/HF8uWiq8ieyWwMnTwKHyycqcgawwJxvtY wfwKLDtvZKonArWDsnpMRbR8bShGI3tLpG3XkAnqoKOz4YwxfChN/pNoqDPijl6w9VVv+JbUNQYH S64cUB0M8QHjM36SI9Pgp9yNlLTkL2bEiLHpeN2UaijLnEjVoNhsvZIDFvVtEUwScOfPn7xifCTy rJZfNsmdOqJV4ovxG1G48eNDvg5P9FSV0qP/7kg4foEL1CpdHeDnpfvXHHDH8uyXefx+uDv8Hg3M DEx5iyrQ4jhJsNPw9iKmOhk1ZPqAB8Oqmy+fEQIpGQCyFlv4SH2LU8Trwy8+ZVwzQz4UtwVzMGHz J+J2vku+f6yiLOshI3XpTwBIWdjCFiWThJt0PogpIPxe2VL3gKtX+nX89CWZyd8sZA+Ikj+LCExe CCxpExljtDIL9X4Zy5DxAdrF1rffdrVE5CJ0p5SnOLEayghKUD4xJZBBSf700BeH+mXSLkxlmeUk y3yoWB16Hh5vuVVXIYI+hFfHoJFiabCsEisN1TmeUIb9UANgrQVmecKHZ+xruhwawjEMdmyumYrT B2p5ZecrKJ4tT0rAr2hkCOzKOtek2CesemNYSvQejTsRDDiN7snATT/KAXdGyqBNTfPSXaZ/vrdE 5NKIw0YXYpPBSFsuwrnkLKZWphZNJxLOnfAk1krxZAx/f44I9Sy2ML3wD8JURQjjaVR+DdfdtkaA C747DnjaTYtXEwP8ldxeW7KdnLkN+Kna3n9zxbxp08UPiz5r2P9+t7iBmCJAEvrsQO8xYF+BsEp1 fik5bxok3MdbHGp+8+LV9DMgXhXeWDtrtrPFzMj2GjPfb1ddSb5kzQju8lHSkCra9q2QR2mf6gYy BmZrRctZ3hC1iK/n3Fb7hW6xWoS5YUkvvq161Xcfmr8bKbTxfjks5crgOkSUaBpbQ2yyLxnJzGb+ 99ZiuaTs4NP5fHdXsy6xFXtE9QNMOrYBabzeJME+Hr2s5fGsyVyq0pEbutW6MxPRVbkZU6QWWMYp /qx0TNNTtZ4p4II7RX2dspaTGuogvv3t6QsF/i/cgR+NdK5L9eXd/azmDfsbGiB8hM8Gr+NuV3pU 16pNBHiigi280b7Grj9S1TkOtM3dhiALACoHXekLwyjJFKIVZgO6YL2IFfepJBOlyOyUTOhCsFjA toFtc7rXzpPDFHYG96idSx/IwF3huFsDfI+OvbC1SLI6fNPmnu13VmcHvgFiftH0PjrEYpfSQGb+ g3Hpsh7GxKsPKwDsBs4NpFt6+nyYzZnPE1awYgrM1HUpzzs8CzS/gJpDFxE7qM8cBCoILwNSzgUG I1lRvIAMl3aBy3NMVzXfhowV4rQHqbxTgrOH3eQr4CnI7gsUECj+gLSoR1uK7G5u+W4IFN5Bt95M bYjQQhzA39XMtpH7kpKtBAr7703OUl4bgOumX2bhSK+tZRVhiHdVls+HQBct1uAjSoR/LdGktRmB 5aRIp3t9xBDWZFwloS8vmy/LXmDTwtcITzgZ2DTlsRN+OwdJafR154ecvjGJrCTPAtkswqEmA+dN 0l4exs3G2fyGV2fx38XM+gH64SKakgy5i6TYM78CcoPI98NkYBB6MG5z+pOCofjJKqNACHLpzx6b iCrSn31Cqy6KiaMnTaJR6YowmBJa5Qv39i5qqqcNg+WegJyFECutXNw3uBqtaQvMwHW8w7hWrcxj PQNVmU2LT/GzsmCQFZ43QO4aPgV8+BIQQlNDrNLhmtMFesJdNr4bexfF3HmoVIPdD5wmfH3Yo0I5 sA52HVpAaTziF2CFIwaCohuN+9Qjp9RvJzVlTYJd9aVU8Q4GhXv5DlyZmJMgHEeQZ5/WLmfyjdw9 lrJ3zFKVJUZthDUW4s1K4NokM4zMfcko1Vfn7qmSwKiB4VlcJwoE09mbGfEya0J2/FL7JYLUOboN JoXZIQ+CGbJavZCAz0GKRIerXcwp/zL/0wglmVf1dkzJ0TvLHxqlhm75Oce3GZIOaltcgrCFaX+n gm21fLqZ1D0Cok2USLKkIDXnr4R78bO3usO4bPUtwe/pyis+fasbEPCRN3twI4sd1AR5hexMOPMR jJFQFrf60oxzu0+2ScJQICYC+3jgt678HV8zEV2zMpEE1I7Ml5P5Gt9OcNZZYIz3I5QYpxJdQE2i wUDaixDfkgNsSnU7rMrLN6H4v2T7CjTNYk494vkp/mjzDQhuVyl+FqnR1vOkjzgoZp+y6I/sSi9d iiOityjdaDwyZC/tRNceRKVP4/mdKwx0IWm6hwzbk5gt2ULEnQxKOvJjnDYihQLNCvbswG4FAiTu uoSAYOIJSIUMZIQMC84pYZTCSbQ9eOPBMm/TrOT86CXlaA5bjKKf17AoxcDxYN0w72mFipLCDdtF Opvnk3kuuwPR4O2mDEGOP+4UwztyvGUpo1icL/gE8L1D8Wb2lXVBDfE1CL2L0co6Om0f8jSE+ABB 8of1Pdlmf9s16OPo1dZjqkLx9FRYMFvUgvaWg9rCV0GS53Bw5UTZ54lG4XRwpymDJXXt+BYFfUb4 PoNdzmRFYUjXbxuxdai3H+34Lw4hkKs+tVZS43JyILSPyvZxj7Rj4WMokfkGY92sFxxF0xgr1TeP mojsFHjO/zJVwgppgIXraO6Z5OUso/4IEXZL8knvi3oFgZSRjGwd6bqiDI2YRx1b7OXnFGzR7znj Iot2dImjt+2K1Rb9SyM9PO5Eoz64jhxeZdP0RtE9PMHwX67RAS+Z3v8cWSHONgtni7zGDidM7w/u xoOFT35t8e0M83cs/vdlzR4eTVJQ+PbrWI7rp25R9KKPdOklDR3GZGiXEhqacAobvKkdFJfPXrq9 f4rRGULii+Wp5dDqACJC12T/2mSsTyw0BoKpuHiCp4yVw/O9Lyr1ott8QeXw5NR75kS5A9RB1KMU JBWRC2VuoIJpEsw32tmLf4PjdPOuddRgwNK91UtZsP9WDMSnicQCfG0cMGtx9E6efy3nS5x/EVdF PmHwlf40oNjjkOGNUr33+1FowxoIx6RxTIWaUPYT6QeMfdUNLuQzs2btaUJkjp6dFI7NbnZxm+8E PxtfLR21gGAV8rjPxwZ6JTebqdxmlTd9IXgXv2adyWKvHBXDwLgcGTBS6PTbqUITydfPupcgYfK8 IhoyzQ8E6zggjzCDyV3adex8Aq2/LLFxvahdjyuMPBVWRsf9BSaYz3MMv9xSB5J8ze9UKM6TCiQ0 mRQyNgSgR6AoGBC6e03Lz2o9pvPXg+U+om4lraXe3qyv8iO0Plg3/22RY86pVpxLpsulsCnt0LXa 9FH0H0jRrgotSsatZrP0psBJ7G/e9Ihsda9b3xIDpzaNqjCLNFcCmcj7IZMdQEXb9LpctoAszons O8i0+JeO2+3OQviE5qAjf55T9/MYOuBPFQ2kAunOGxmcmbIjWWekolllK26aPaJE10uME/wkcj4i jauoQrAkokzcO5Wl4ce8wMXStHPK2hM84lnvX+10z62Hm5YDmX2S4joBKNFShybHnbG2VNPKbsuO VxQjdHdGlmOqOVOMp/mB0XIezWyNx/sGUrsabDd7i979UPqtAT+l0NLBFMXmuNdrbaMDRvoO1B+K j7JCSe1hPGnV+SWE8Kyup/9B1bleC71trBkSFchYzsSfSWI/sEbkPKBjnupE0uvgGTc5J/N5Jc++ QCzeMn8oISkH6Y+/WKIkxYHfjdC/5cLmUpiOPAoJuq5XHTGyPV36h9L8TyKjRMpmPBqy2wmP0NHo y8k464TWxT+tUNf8CD+2NYfCsWt7p+/XCiCR9EsKR9uFq56FvCZKM3GeOGITgpzf2RbjsAw/00J3 iXrBnOkvxvJfg8U1rPDk0R0o/G3AvrCVPUp92m1BP5t/xGt8wJ+MzD6jWG2IVD9QC+ciNWyTl4h3 gGxuudAcgmSw3fpt75pkd6KgGO4Qwa/QfO+0Q+mBr6xQv/10bQWzedBfANh7VBKmq51fg12/nCNT dl3Qfajr9THkGswdSfQpuyUvXSzP06sWUWiDzyOqdQwfttraUsDUxR30LRxuh5r5hdSx0Rrn34lf DxWQiqUz35OCmkwF24AjIwJOBM+l1BGa3Cpgi/0MjxXPPMWujd5S5h8NTO3k4eI+S+s3hJukSBhk rNs08KtrZex1wjM9EXaiQbpyrDWZBnBLuKOyG0MQH2n1q5ppXbmkDt0s+HgFBSNQBlIwpKAQRmrr t3lKM+zp1dFRkvOQtaNFPqSJvBydreazh+z76pcA0Cw3QB+f2BkL0w4yV77I0VTf68DxnlSAQe9Y Ie7hv2Wp90hephYUfylML/F/qP5cLja9xXyXympbz9B/URQ8gQ6VCOIzp3VhbW0POXeWTo/K49tg /dOBNgMocC6+XqyDalNffHd10CB4mkgj8pRurLbiknnhx3Z6DtiVv/JEWwQtVyB6g287XGiRMZO0 3uAr6ObHL65S1h2LKX0KvsbzjJUqPgPCrz663QmA+thCSrcTaqINQeBVAVX11kZTRZehW0yFg504 wb/xjexJEC3eMKLO0w2JmTak4W18ij0S9hZDrlNxzMrYEqVFFjy074x9x1bXzYU3g9D3jUkHhl9m Y3ljj0kSaHo16vg9NqyBsWtp/vH96QiCX5nsnp4gSiMeA2hyCQVVUG0NhsDkVXdci1KVN81lU2L2 ZPHBmh/G2xCMlZDySZGeRrSw5CkS2xZ0dHnmaOaskgJ/dl9MBf1SjjMQ16m9lFE1p0Sp31UoWbmB 1xF7T25Ck70Oz76VoqeacGLKacEumRsPe2+tV4Wry5A8d+bOeEc9O5RB27BOarUfb0UZyj6T0Wor LdbssNCvmCt22ilV2FwD8dWxdgXve0AeXCQ52s/jcFyQc/c0M2diNbHiErDPnRPjcvViqeqV0RXD 1TFCohpaAZ4LI4K5GFHPlxm8XDCpFWdnuwd7XXH+jRHdHBceF+7n4O+moDlBj+3usFciGs52EgQ7 1ZvGEv3eTnFZ45qgYzc8n5/Fsh0W46sJu3pYyYoSgMWMsKaOhcEwi9EGwJfuCIoOAabgfSwK5QUH sMVw29+Wlr+fdcndVq/7WiGvJB15QzDquw4BnYNxkx5zQs1YU1DfiPbYqUCAUwQR0mDjtfPiDUHT Pj9QxMoff98c9GJDHJLQyF1cLX+NHZmtZ23OwIhwD+aR3bapXHIHtTcpS56tL0t/PVUBuOn9/H2V x61OQ7uZQeWsuU+TsoHmsG4cvH6tz08U0Ff8RZgzjWckkhv+48nRquTCIeBiaiHMdvVzN4xZaban qqt5VDh0O5GFKLIQeJDUnpfvkglGAwnI2zMoV3jLPFI/o4A5qL5pFxhCQcPzhElPg6rUEaqK/2sf XBuqsUTANQgomID70p5D3qKGQd8KbNvV7EdqdchxOvSgWUgvLXpl3yvbDPQ8mGOBQEvC7YYdRyEH sDkPK7E4r7VuXMxi7fXdELKitC1JEJDBOifp9CKQwzk5UxOzCDnOjw7W/JvGhPw7xvYJaS5yEXtn /kv9ru+hpQC7KaWy91rsicvOZZYKz0iCDKB2JHVd5uTzOkYU/HbCMqxa7sQxHQuiAth5yELW9pj1 fnPrx3e82OMkp0XAMLMODyQCd51CIN475u0dfJgKbGA5HQizfWmd8iqY0XhSamw9tpG5/6019gIx C+6Yyll3aiRDIXvZ9Qrpr+YRFJZAyoFv95YU7rEhUAnDnEe8kmAITohi7lTYWaH5kvLCg5HPeubx MZJZ+wQV6LMRc7lyWYviQvLlZvJ8dung7OBWY51FDf53NuAzm+plC7QCk5X1WYsYLkVbPZqeUJyo 44YZ9kHE/0sy/55t1Qk+JxS7WiYZiR9Fqwtqs+2tp789zooK2Rekjo4+im/98AVvMXX5mmTL7oFB EnZRyUofhOl6Sc309EjNrFRbBCqK1EgsGriK90ricade84VtjFWTRb5Oj9otGxcdhKSPYZMJUIKy brIHsBTfGDsD80CfjnpA8GXlfQ0KIskTM/02MVKhlP8oZZCFfP52OGf/ovijXxf22C+dC2tIsAPn W00I0IV9wY7J33QPS1DlMdelfRU9+pREpnkdvmaG7N0sXOW0xXlorpV2wWRhw5TlKWckIWe3BMdi tggfHT+cLcqKpxLxEZomMutqQw5aiULsQD4zQFuv/qp5V2MORH43tpJjopA9rgKdNYsHSUN+Xw5r zxgk3rmkqhBD2s50y5a0dELuMFHXC9PbSzb61FQRyUzpgPK5xawCh4RnWWCkVA6wX/VSzpCdknba w/YNQk1TLKx1AmkVo2pPDoP1kzFDOVuuFljC51wFQB0Thh1SQWaqjqYRzLnIWORxC/RAI9RIibmS s53jqqN36MKFi7Z/abVcxM0gN7SQcOXj4dNP6lnRQVZQucvUgLGnv6Ch9zHTHgMkEC4J6F3kyIhn 9jNkePcWKMonZpFwvBRJZx+xMct70KstoaXDTQ2xoBNj7q6mmj49kWoQBNhTdRKkYUvVR29G+s9v FGuGlCXUDuWZo4QuF67d05jWH/U0X2Rm2lV7rgS4Fbn4ZakmHYNhd4QEOhwwzP1b/oEU5XZvAgbH 2ZNCFO0vasU7NKgS5ac9HJYC+yUxeyjKSw5LK/pUj5hQLNQQz+w2Hrue/CYE+1ZcMxl4UgRmgMLm x0WWqr0HoscEMCEMMTAcUrsDSlPjV2FVim4eqZz1dx2PPlTBvD0ulUn9YwAU45p2NLYqO+UWzuPf YTm6+TXhch93xuX8xDqD2PYHPkZ9T3agKqKiei3DkKV2VF6ar2tndDWQctyrZo/iospyZNyBG4IE 6q81DINovoJvt1T/1LRbeLBlqBsrtsloKstCwolN8Y+3GO4K9oI+xjR/SyDfV+g//w8r1gUB1nIH KLd5BKtYOw4yFFM4Rad+B//vqr/4HLGzO3yT9Mb95NtdR3N/cRROvXiu89/oKxUCZ4/RvhkBki2l nEs/uGvA81HA3yzyn8OWwiAuWf3HuhIEJmJmh7SCmyxMwPy5crgo8Mtrb+NnrVaD7qf2WMjIgu+D y+XP7djh2KQU5JelrcnXbmrVijioyoD+QBTJ3v5hSWyyZbCaRbNoPC6Ng/IhYoS/k/bFy9UA+cdo UrtYAttfaW3dCXSE1pFhOU+z/K00LWY2jbVtIp54WokipJxX0YBdVdRBRWK0BtKm80BlVswLSC1F yzwWbSZCaIm+p43/omCv4K+h0svYz+gmM/p5zKUqeMkG3Ljl8GxKoAb7zwyk9Z1O1DoqStSQSZon OtRqNf4PLXSp2nZR3Tb1cW46bqaPtIaI4ykfbkUW/4I7TdZo4bJqHVNUz6R6Woke40+sJWCdghG5 oaZCivrqOTg8HeriO/7ccEYCQNsY9a+rmUEWd95D9ZhGTC7I9kitV8+h4++HWdn1jW1845807itD rlA0ujYx4AP0QDXqTQyXLoTBGEK3Hgx9x46etQywwnwWAiuktUavziFspMjHxkIQfJJgaJOIIub5 psNRf4hf7mI1cZYgZGdaLcZyXVI0xneV/UIbkO9BvcjMGQL8hit+WRfHWn4d9B9eKX5sNiJJ+JPm 6yH6xiEi56WSfxKTZ/QF9VDGCKaSDiViQQPULR7WbUYcFvZeBE+6Kgrr88FBioHjGXEP+JJWLNgh 8VXSgjdzQYCp55F/6TrFXITKC3ZnMBXC+ZaSapV2HyC2TJ0JfEtT5DMGvDylVPJ5rLwFzrj6oFaL HCA+92a9M4Kf9N996Hoq8FvuTKvCs8DipHXKoAFiWfhlqHf/rIUrkiaruwyZSiYzsTi9Cy8VP8sD Os1JQxyFp6ySQACcFIkgXMZCweVfNrRUwtp8Lcq0CKv5MF6SNMicN7vbM8l8aLcEuzsrZpaIsxbf 8xv+e4Ih/JPGAfNCkCX0Qp11bBaZB7Aa+1xkZ+2IonJqnzH3DJHgd661LpPrcmyPPQdJq8utl/Hf LfXZUegwo8nZcww6rIvmWR3Qpg6GD7qedppxp+HZIzl/YORvDvp/QriYOAiTefh28ArBbrrSEpA3 btZKHRt2y8XRUTul4peQuLdZdrW1ITbARE8o8Sxg9XAUG7GuKrjSvutQEtQ7L2DM5F+7nsnOum88 /toy20ay9gGTEuFUMMaqJuk3dquhUsYndxofdMCtepLgSccdYz0CUasYS6zL8wOw7HXjxRhzwb5k MRamJBvSxVfzQfxc31Sh24RlIdU0CxkyTc4qnyS7BCJ/aEaU+b+j9/tCoC4sPd+YUDzSHMoBtxlw IIC2pi8of+JASmpG6/VOkb7XViwRETh1xOqy8pL/JxdEK0ObGdPuHEkAojeidEJqQVqiNU93WdsY 12zMre5zGdXIApTJLMo1A/17PL55Twdb90fw6omsVU9EJezH44dyMIrhnp1stzNCgk+hJCfPWP6n rsy8jls2xlt80uJhtrOeQhGlBR39vwYCph4plFu6STXC5hR0bpsAy5olKXvqLFODyQH3jlYYys6E exBFBxUdRRvqvy3jcYCsGhGVfDtJT8L+ZcXZusVFYgvzKsZ/p8vm2ArXfuzIEyr+vBvAJ9btq9zy dnMam51G40aNZa7X5FbA1CpiRoGYu+k6AeGaDAQa7dXdoaEOgdd4GTc05OVM1JaMhwInnP7ju3Hg IZcRasiaCjhvdfIRUVy8QqfHFbg7Hwjoaahs3/IseeM8BCqs92d+hmojIhX965n3jC0ZBmJjQnxe Vjrg47M6l9btxQHqcjeJ7XdtKQypLNpW1Y+QLRTDtRFV4NQZFFTY6qWuhQLM4iNLtXGZeZMbsW+Q R+bgI8tRURKaqT6iZx4EwViYrmM5qbPW0FuZ9zGZ60nOl6WG2zrzh2o/WIRsbITMayEFTTPt0c1l axIk90tAuvfRcX3fQZrLC4mr2OblWhdbeTt12l6KYcfEnW+0UoGhHMXBiiTRiZSCWgRsbXZh2y7Z vsjMlirYvp3nKXXeygCAiilhdgePE7x6saOqlmBEZzgVFwolBZ93f4FPa3IjA77XK4CwLl46wFXH nyXo2RfRIQqW0XF8R1UvRc338r1iZNz98lIiGXb3KAnlqs8eBE9IGc6b5ZevG4g6I5smPPiNvM+6 ZrtQUWL+gkNiWYBf0OQQC8CNYFnI3OtB6fSV3US/0Iu0eHUrCigDM5x8LUv61P92/MBottf04AJ4 D7BRM/Q4KCzjZ9DUJToh867i4HCDc5v6lF+FrO2Kof1b6Tf+X8S5JU77uiS0c+CVxX40yfd4U0PC eJQfuglHkZlbZ9nvr2rRuaE54s0Xl8qt0w7InsG8rMakTwd4QbrWoNPwzSnskySHYQOXNQPp5oLS HNAfoelvUc8nLJ2RNxt8Bsz/bILXbebs+qMzLJ8uDzc7N8EoG2kPJZFbxsZ4qluSbDi/jA1y/vXn gElSTcLi8qRV/TgShAsiW84rAOgY6lYn20m9nSRvszhCgTMjhQkBrMZcWaEdQAxrHucN9TgCcdSP 8lutF3i93mm1OxvnPLzv7QV7CBIw5SDhhtsMYpdSuZcv+pps/8rpNfDtwQTdmU2v3J1O9Ti42Ge9 bj6oRFnzMMukpJv/vw3hqcGwyulST8VWCsjdpuolDL+A9UhmfjWsuuVTPizz7u7R1cgGMDmZZoE5 E0riGNMX78AVKJLGl2rIltukl18dbaiKi3L3RwkM6SPlg7IqMrGDwwYNU2BPGDP8I7AO/Lm1qfhT gJykwcZDTEp2XJ4nrbFxOjZdvPYMPNBRik6b6X0uquA9+x+OUm5pjAjNlTpiNwj7xM8cpUUYsTq8 mjmA4Rc1rzfmwNmlKEaXBFVvUbshSZuQsvLlrkw3cIwTePYW5TlmGqzJqApGL5eysXj6Spy8zWHM DNZ2Z1REotKu6adNg3l/XKSTeXCHKIIWArJu0QoZH9twbCb7v07SYpA0mTII3VhvAOQS3K7yXywx 21GgUJUv2EjqhpWmMwVP8nRWOAn4SuJ3kG+cr20IoU8TAuNWHCokwU+olPORs0SihKV29uKrzjvz NQURPXepnkJHfhXNxM0EZAniafu4yWxTUUgUrT9FL5ChwMo4ahTK2edjWbNeJ7Bj9gvXlDIMmRpt d2pPo7K6/hU357xZ0hFckjEYWmwNi/v29b/t05/yheALWCHVaw2Aj8NwdmAdgfS+B14eruvwfoIb 67GDlDCZZ2rH4Az6daUkQJZC24J85L79LYHJCkl/ctAKNz5U5f7KanmtE6ooiy2V//QnaIB0sVGV WMQKC1w5ct+Kj1UN6/kUR41uROe+7BZ13NSUuA3Bz9W18cB2uUW6iTj7N5pR5nnyl29MovgJmRmm 31qVyuPpzAMUi3AYTvy/mnxFJlTbK56gsdvpE8wjLyD0QfRZCSIMsWum1Ja5owLpCus7aKChxMfq TMZhRTKuWLb7IRd6QgJjSNG2Oi3qLqFLNHTbitNos6Pf2Pp7cqYekvyIHgsz8317fBmNFkWZxsSO XrCOOegUNCHiz97gqwmuc557rS7Bhh4vs7kKGHMP4JLJec+QYaBOPqM4XwCL13szi0OF9DpE9lrG cZAzHUo9mBNDkXh8tzqhtr5mwd0pS+pKFvyNHwauh5ebKWTM+fxfDzsYRYtQm1HfcV7K1F9sFJkh HGDQvhP9jJFUxcOZ0b+1kDefx/17UmBYcJDiBx84XZmKc7OJtLHRUdEQTD4CYONKA455H7SNJqQy kpunjYaBGXXyhaw8whde5ibovSp0j1vwLn91K9EYXYStK5LnMV1uxEoTk5Br7u8bRfwjJqv9pagn Tk4O9f0vr1r4TFBwGTNyYuY/tBT+kvWlMoAfbFATiVLJMBKUZrMauiwpXbJKgZxN9//MRXpi9iKW 0UI9i19wKucViOwCsTIhNyjTY4OaEeobbJzfKaJKE88LWK8E4F4kIo7B93Jpqv8qcVr22QvWMLQ4 fKZ3TAstPGzMHRZkXaHxa7dO8E63RPNnY06JRUgtsXYh83PDlxNyqGkmVp/xU0PhF7L88Tv9ygAb RPi13wpyIOpqC2GHkolNAD0iSkTbz0Ymppd2AglLEFd2x1P69XbFySCIo3kdO6oco5rKHBLuz7Wt bNaX2f1GLzXkz67plab8TorK1WCBGowBrkz7Uelu1OrLU/pH9+FYGkgNxZyBzbogotHY6mRDmPyx wyrNd9Ji3z23qvf9uBR8EyFTc6F/7IqAQfccXoWhuR467BQxbmPY4Khd20rNKNh2I6MR/enAGR9e swOvMshIfrX0Hp1qTiq9dCjqQ2Cz8DzJo7Dj/QE5gWS7INhsBvf+x/zaY+q8lfP6DOxHAdfVyNqv frx3rVsNmS1WAHNdISzwpyc5OLbUMobbwtpQJrz2m2V1bx9v/DT4qyYSZFgfWs6fzbuXqwRNzxmD MA4toy85/QClag8mbfT7vxXXio9txnmGt+Tmntoj4wy72uRbZt9GHDvfLsOUKN6sEKsLewDBuGQf g+PTMk2sIIjiYnHxgW0ioR5s/HeK09/E1TUpOLF462HjyDx+BL1a9MYB2NpCgGfOoZ7pUbs+kUrZ cSY4UoJbVgpuIFzleLaBPVvRNfKEgT17zDtajVZcvuK3k5ckz5RzwSKV0Ydz9Q5zsvW51UH74xxp 5ECFdqI3KK05OsCnR32ueoIJHpMgGWi6WYFi34I6bT2yRlmxRdaZ62besoFmD4PJyxMNKWx1nimm ghIH9fusAew7WLV5gOLKp+sh3eKO7PmcLAh52GOCkwxiTwXH35SX4n47u5tWDrYSfqQsV5Mh54K6 YjeIcqy3ZFLWwE70cuoSFdYMx5n//Ax0ZtMtd9mJ/qK5yjjJbEXs4s+MrwwPs6FFf5mybKz50HdC ntnBHqbkol1i0nTFPR7kgk7ybtESDd3lEfGXFqm/iRdLF4M4MMMFnRci9HjaSMTcoWBFkPGJC5AK LUfYvnDlG6YnPwqmc++HDenpcsucstmSHI93VMxu1kZoxdgYxrHZJbZqf6NnYW+PgYPt08kxIz9u lXckkkDQy3F/wZrsNRZ8/VPPGviCxcn+IcCNKo1jv5sJvxVh1P/U1zXQCpbCGm/4yZiwoNcmnvz+ ZbFU2tRbVKZv8XNSdrM9TKTR8pPAJagaAxPIHqXDkyhzRng50JpDwdakhq9YKB2T7v5u4j1lSnlF kEZDFGbEAYj0gLjkCVR514p+eA833v+Hm9mUkK4cG4Bd0XIipETZAjFPDLScxhX/zji6sLhcSPGC cw1Xkz2b549H3BE+TbfFw/vSU4oUvPuqnqgGriPhXI8GmIosZJDexgP6A1PoGOQjZwQcezy6dnPp Q4AiLrc6S3GInPehsiERnDZoSg+spdnOeN1cD94Z9tNvoloTXaW/oOcRmMROZLEFwAcDqhNg9OtK YJEso3fbVo14GpdEz/A9tSSjBBJz2wTIZxcQaTkT4Ecr5p09FOmY6YdHQCg+Dyy5UadezXmFyh/g WEOKV7OfIcHp8IA+ZSnpc11N2JalgFaSQUHBcjafGqE1ZjVNE8hx29/DeVTMHru1uVT7GrZHDXY1 J0MphmsHNtTIR5Yf823USM4hFA6OrDYMqiRvMaUxJfyGZpkiJXPhfPdoYbUmeeadZdZUU87w4QXb S24GfaItFdM45zHGFpmI4MQKr3sYg6AGJA9i2iDfjYpFQItFH9Gph3gx7C9AlNsSOS2lGZaqP6s3 FZ1wFpWPuK9RPjCTZaGFpxwAXwFXnL/fzOk3pW7xmGUEwrmmFFhwYoAKno+RlamniKO5geU+nP/c 3xgDjf2qq5oiTtd9CiyNjxg7bDnEBHhL0oJPRyG5wdNDS9Hfvi8MZDzs8jLfXvxMk7Y49bmUttdu R/tVz92oCgWVUm6BVV3Yws++DCgqzZ7l21dDnE+x+AKiH/pQweVlqZ3GXBnQ8jzHqLyiRrSCv/6o Igu99eDFKPClEq1YfIOKESZLqt6gu8jqWRqfGU4UzefxQzEVObF076nOMtsR9JoREi45nKu/+7DI UxlyhBqWK28KJRpHjY7sIv1zFQE2aTgJ2NcPnmf+yUAQwhvPYYyhTO81rfHaf8hBfFlzY0B0Pefk +VvXsOjmXhmF7Rr+TB5p7ATLSzEDdWhAdZBOvTVQUqCkaiMXN1YjNAcz+TqVK0BlTVwx0N+oXboQ 6KWQLCRMeqWNzBpDefrhgmVDE3Wt4wuQ4Z5nMBLn4+Y2sewVVZA9y8cMEc3lKM3j/2BINU+iF0sX CgfRweEauS/KEnRWyN2tlr9JxcUygWpGJj59dTCVOhhn634vSrkGc5r8H8WYEKLT2y2C0n7Fkelt gfrq4Dy2BEMJfvlUum1ryxOYF0BZQq5vs4rYyBZZ4T1O731WZoHHE1lqrZyio18DYO0uuZXFvijk Ln3DAHHMjltm2j/6eOHqd+2hNF8gGEbuee3BJevCVKvqWXEDVsP1NxXGCbA8ei3EAaabgsA0er5e N3ZDQiFaicHg/BJqliDF7sO8UmCwvQsF0QA4fDurGmlD8UoQn1KkAxDEoC0CG2MYsGWxwK3d1Ev2 q04j3s1EEjykDK8+dvxXNos7/McMEWGIAA2sLAYeGiUx+SWyGzY+Nb5+S8G0eftEpgvgA9tGrGj6 7KI1o0dQKA9wY0MA9EiNM/xnkTx0zT6JgBdTw5N85QTznLRML50rwtgvyLGms+aQ0tQZ1o+oFerH jYjagYwlynC/y7N5ctvoiDP7zI5GVqAtR+BNOcvKw/b33sKH7JiF0UYUaiwIE8SFhZBsUCU3j611 7TMyVpYrxHCJEs1Q4VDwECONba2Xh8c7r4aPWaa5fMGUo2L5T5iEl60RwAsq6TlwtLaLCQfLKqde qdlsJKSAFCWt42wwEy18XdOuEod8OfrC/ZejQNHJFxfT39AwJ57vsHxL1tvTuD9DlBVIUYfP0if0 jXF1rAnn2WxJ9kyLeBJ0vhmPem9G4PA5qve6XeK0FHR5LPlzAYc/4raWDWu4LnCppih005+vj9q4 RRKtKFkFwXYH075f9KMP6rK4/Jd09UFbxjafhnAQD/+H6EOG5TOxkw7N3iHLhJHIy5JhBSjzTftG xIwIqHdidevZn51BAG+e6WFU7GHVKpJNVftp4EEKi1eUzOernORVBGDEBCCRFmnDwlcYem6W+7s/ iagl+jNeEEtvn5GSVK51ybLFAvD/JIfY9Edpz3QJchOfMwASgVca+84TjCX9alZI6etOa59m4AAG l477gkoIFUx1IvdwhTD8I2wsQ7w0e1odX2+XBlAH7BHC9bVqQ1/GXXRbm+Y15zfTHFZNFvXD4Qhm +HX7dV6/iibyiTOWakToiw8fvf8mz+AnfUMzi+QTuYEcLoP62Pui0XItHekLgRZiIIgg2T/VK4IL R2rGuzoVmHtYmyL37wkzgCcm8pSca7WR1L2cgpcwvEiIcYYw7LMMYAfOrjvtKJ4wXQxzd8D9562a FoDcV3hmTxkECX0BVPneKPnLA6m7gk37q8uyUQrGdfM8vEbDMpG86TtJAuDBymi5UN3+RWxLz4ni 4cz7akzUrd+tMzxwqJ748vy97NwbwBWYVTooqENntU6X0UGLDHxvPxic5undx2V6TTaOrB4ns+PT 9tyIpGncvhv+Sljwb/GLb3kHBDkz+EfUvk05pWBBQZIB3MFfeWA9GE0Jnx2cjYJKlj+g4WbLEngf Qwp9PwcO7+OyBGWzZZXezWiY8vkwCjfcUbrKu1fbLyZHi4gqeoyvKtnT1TlMdiGqeHCr07V/n881 kNVS1kEyZqXkubiAY+XYIjP4+xKuaeIASmQjGKUopqR+yBJEEzQcATIk+MFLXPViGiudNJInowTQ z+S+uVrXj4mCZNC0li5eGcWZcXZK2tEV2FuXTKg3tEUat0rBhFypLbyfcZ23HBrVFOOd6XHXijX4 sH2nfBZxeuL32ThKlC86r6AuJaPAdnAKpjyocI6lZi9Zu8Wl65wZxJXAEjRfRBRmXeGeFXO+HzeR OQOdTYJ++v852bkVcNAwAso9ukRThMcb3VWD5VYGg7DCJflZ20IassOBcRJJCREWc9m0e9hWHitd x2aSrmovMuRFR0AzeIbxevM6l5lErlR4h4CNFwc5O6fE9DmbITeoN8Ci0UyLnSkR7FFcIEhkrSt0 bNRyJKjTAXOPf2SP8CXxN/j6ZipJsxYkasBYRisrgaSo8fRa5n91T08CqX6ls4v3HkJwxXvprtXt 4Cnq4b4bw3wZKBzFJ5P9EittsNVimY6YIhMd9rWOaiRmvRVGUR4mDu/use8sDZzDH+6tOO610dK8 Mxrkmi1A1yZKO7/dB6yYjtavrXkyn7oq1xvw1pY2bLmqwhE58k1Kn6qDufRQ0AGgzvsufXVLg2da qNAUhRSnkW5D1BlHqmjK5Bom0nToS9zriWZ/YOD29oxVyJ/vIIqG7mKnICxW/5SIEAu6HloniPZJ epyetVkUQTVq+LsdzbO+OymSBHcscG5D7KZjlvTCykrWebxRiUmRd6SLcQm3DkxWK53XDFb1eCK/ /vNENj3c3xMrF73RgG2Vex3yP9+rhJZ+sE0xIHxQ6CDhKf8q8jt6izbdX2fbBZOPobbE0oNfbb5a 91aj1OGpLc9k6p9urDvJizZVGJKlYJmNJbL6uqwtKfF3DMCvWB3IVvodysDqzV7tw2W3HDnZFy6O uWfdAaXegecdlPDUgQLKRlMVPXwtxo+cjjKI8SkTxKDBXeG+GNMQzcEguiWO67M0HTgvPMYTnnVM Az/7fM+Y5/ch66hf6AqkHxcMaTe4FzpEakuxSco3bqPD7Vtk6yhSXxiW30iqr9nXsiKrpKFHjWCw anmIb2xCse87MTlmUIp013iBVX4fcPztxn7+Fj+VImyGuCJc0eFk352/xCafURLPMSU8JzL0TL8Y oW76xWMhL72tSLmCpwooO+o28u8SIU2x91rHM/UcI5FVszGnVZFh5z+DjnVZASY6k2mTXMOQvoUY i8qJBLUv+uU7HpRNHXFFZGmI6HBUQlh7z04g0WRa0i15lCpXOqMLpCKv4c0yYetAehbVmt3WlMTo iE117ZqN6diVzOdYeZRHXvSlaxxl0Ikwkog9HjIqfnTX+Du5hf7KfhdXe9XWQcdN+G9FYC9PCv64 dvzuopAJP1Rw9h3eG+mLGDWm6QZF113z0yshi3Vh+ttz9OKra7v4egM9tMBh0YcQfsOqmUwDXV73 /9bnY5bz6kpx/Zw7rPhiy39RyzAk5up3UhNeVaBnBBqFw32xZKAWW3kJ13Gwz6V4Uv8/P1dcAKgD t5Jbe5T669+Nuid6SAMqmhglLfFGoPbd2BuhZX7mkb1Fv9rtF+xbMdTZQAr4GTAhZr6Ardbgc2h9 o21fOa/rQV/KbCf4pbOX2VcM0pvenaPFmy+WMJGiFSZIHN6vUrrfbjT3x+juL/+dn9d0NDN6xcTH lgNR8mXXWsSnKjRaWSb7MD2smDY36PC/rQDwD0SzPyoWFXWypMszYQ0J2s/izgrwWnF/v70+S4v4 RWgAAXtxNiUgB1vKygLiUjEhB3gVSh4K3zpDPO7+TjMtwsxLPK1o+8P8iau1iJDdOywShTL8Z0k9 XldLHazNnEfCTmSsLf5Ukr82H4dq9pMG7KW4o1FHa/prCAFtvDVQb1HfcTG9z/N5oiN+iXj3xuL/ ZJkw0p5HlyaTonX7XCKQFQ5X3Z1nsJ3yHae7693cIlPcHoPN3fNbthnz14v9axh2MkvMMYjKH0J2 ymoDh9+TMT6AzEJFiPQU9OpW6vA1q8kNFC86u+5rtlrixCJVwz1XnEBWOWi29B7U6BKGiFgQam1w 6uL9wML3bb8hY/51/KZ0knD6+ZJs4CVSlyVMSgAsmzIS9OWDb7jtmCpvgkHC88z6wypCXGPNVg+w ojwJ4lj3XJlBF59j7C2nyHBfuO6PqzGp7PvOuNu2Rh+mRe1qROPxbPdT5YemP5WasGNQhdk2cWa4 6wGqk4YVsIwzJMcfeqTA0gbEbKqvp4Z5DJEFgE5Ixc5YOaCcpn+dSXlNKZH3Ge38nyDFai+y07lk CdxE9CEM1a9W8ZH6k8CpHDVf63BwEADOTbFBoXR4Lwd5EyTbM3Olk+DDYljtIHa+vQgmDjw5cANS ZqlQpvRXFpbIIOOVmeMRRuBnO9wKQ3RVFn0QYl6+lDs0sULTkfX5hHtqY0e5zTXhj6jq5II5iQv5 Cfp9krHm7ND1MRTepuezqPAD+fq45FmjhmYInPi68orsxDPSXAmZYuWz+N9yAr5zQzGiDcpSaQGB NsfJ4SY4cRIkuBlrJqpauF/jHkdzbERb2CTcIHxW+mZyqFMjWL2zXbL69gOzE/Jjd5loL8FrP79S NurZenmLa1EzubdqeznvfVJiG3gamGeGBC7Cn5J7lYEAJtBiPNQxoD7I0qncAjYwz1dJvSXxX1Q5 o6xJXINKyro/GAi+R45ubsDlWOQDYysL0rjQ3CRsRwdgYVzegKje4DNT397OUPlBe5cbE5csxIdc vlzdwy5j6d/cJYaliKbE1arS6eKH+rJ1v1EgTV42dtTfZdevtl71nrUEVwgyEheTxR6cLqQt66El 7YrIf69xnS8jm4Nel0t7bLWYoARKDa6d0knaqwmaXHxBS/IXpxjpugQO065FGwxwjlEH7drFl1Aw 9M9B2FJDLyprkl2QAN6NBHbSnuMP5I6bVhIrD2nqfQTkSO6YntEi7ic5R+7AxCKGFYewHi6FF8G6 QiiuzPeWgP/48XcbQhZabWrZx9t9YNmBhXI/8jcU+Ks9YcXevgCSeroMEbwCI3Thq72uLcqwXL0+ SN91pY4E1IfqqcmrOyF9bf+/uSn1K9JFd7OLSzxBoAJFUckfRVifn9Uo/6sPWPUqDtpwOZ3ndWez elG62Ti70wvDEnWLH/vRYw931iEhd4bcpf6Gvl6/X0IcFPH3rmKstLgJpg81egcnhQ3RBosfhZyw JQyMBWxuxvm10ZCdz1orb/Cspz+KeRkbw5JoFKMny3jPliraMzrhX8PwsvTE3sBYGtRI3wO41hDh GFcgAqTQITJ6lyH3V47WTOP4gao1MOYVYFEM/IdWytaXNKMaOV0FBollLmoOrGpuCVgJIwwSqybY 9R/Nc0s2seK9Vgd9b9wcVhVRRYQ3nHbVdGYbKnZKXBDzYH+BPfwqiR4mZ1sQEVjE3lG12x3LM3dp 8JHe9AY20OP8AMySXTYd5cWet0ItUMaLiezId/dYbYbxDt612mBYmaZ1+Hix62sGCD2XwnpkyZXZ h8MFU9pO8q9vOZ8Dg2mOBT9OWh2hN7qbply7He2qiGJ6GL0wpc3pulTTARkRfAxs9MyjLDfnlsTM l07tkebEsKEUzFjgETZCWHhBoUAxyMms/dNT/naSQT7yDd9pJ/hbA+bmjYufqlircbmwIa2O8wvm B3/tiKBlnP1VU+PvTFOx6wOyEWqnTyq0ScehV6ouBcQ21PlIFaJj8Hc+Zi4K9yHhOMuYTWA8g4Mo cMAm5gwiHDVDzJzDD7dkPK7xkN/vwwfgoysBxkV+Ar6YgTbP9UVmzc0hFrTiJcDDJ8ZHWr4uYOaz R18mGYY40tilVOltLuV4wWEqmmLKVHjGrG1S+yUlgVhHDpERNA5NIEZiChCiCrCYTQYolg9pQ4vx ECCMfm23Qn5pcrCrJ1rs7R9bit20XBKFXBJZIQtXjizQ2ljDzXkZPIrnXWR4c+2O+sysuq5vlnu8 iK+XV75dbprxUs7rG+DfrVUc7TLRSQQlVezzuF8fgghtpjV61Cu9F6XKhr4WxVcL1ESu7DdbjTxb 8CmzQhmVW2uWGJQdvHa7lBPvJBc4ZqaoAyY/JoYdwmo5aXnaYkVKl2KfIXxRqSmy7G+r0wHGRua9 gL9q8eRATL1aGq2q3jbkD0TpurEhnm2+kmSru1v0bDBlaXwSXRdck6rfDDbkx641z8YamdpywnPj dFaKhp5ABHD+hdvUBIY1J1ktbEL6H2zIpF4FzOrY/guNBEbfLeRCjoPwqL5l0/0gTFJlT48iFzL5 Hp/QpE3bTJAMDStAzhjYWrBe5fofR08q0D4RpcxYX31F6i+6vIMOh1makd/SryGDSfP6vSt/R3im /J5nBe4ki+CyPQxYDe7XBn/hEpVIAQI6YsiFOiJpTZ6hPn/vOsh8vOUmG84WJCOsWQaYQOd/JINf pKb2xrk52ZumqzJ3BCWETJfjzQCl9UL7sC2rLMt7tV6lCVBSB1l+glWhxD0MefewVQ+9K0yDmspb +j8qT5jv7NZigM9c2Dw7/pQribUK0F7lElljv4XjPWiPd8UI6YA3e/CFn4V6Kem4ycxqPxwBc5MY QZkj9z++vc7X7B2aK9Yv1S2MSv4nCqJvOpqoffrXGQjf5p4C85xeKgIQe6ohJRz/NIfwL23IYq7H gzQUGShstIe4xGjJ4jE6k5OhH17ldtgV9ohytVGTqLdiRUaWvGRISpvmm81p40WFX3BjULfcR/zV T/GUaJlWorIguY1N0vdpMtTpIXRzTO+Y622X2k3miwVYoYXO6mzuAZtQyeJE/Hc6hejgVe7rrk2o zR4GeAXHUoszT10H7luxEwDk92WZIfC6RgOhMvRRhlQdQwX6h+F5XsGOhdMVYT6b/hR/jtACW0ks TYa0WxA4C5/o7jlWu0xTG/jH4rIJxlWcG4QLM59Prl2DkDSzfo6/ROdPLG5V1xZsNA12lovkz+wy uKSIkVyqroRj31iHoK/+rvTcrq7dFIyjKnKY3rstJ/sNJZ7ELKM5hsLHkiAv7ypaC3kCaleGCWdU A8rF5tk6rscU6cEKlMxvsNrjFrtqNBepLiKO8PvjCcx//ACoJsZ/JNnEBhICKZYq1aOFMWUcdWDP n0opHbxvzYMBexConwkuPYfViL+HRotOAz7fIRZDK29ywLM6ItXyKwsMWZjL3kC2hKALUmT7i03b m+H7UojIt8UXPOMaMop4Im9yoWvgdzew/fOnkxtesbFXrpt3zQXHJu675Cxpl/kUWg5gkZ3sQMHB URUL37vKLD9G1yRKzNsosAslEtPOf5rJi0RpnWHFqO3Mt1ap1W7INf24JPX2iYeKTSHUs3d+jAMb QBpCLGEbH79AMrxcJxio+qsutyiI2VRYZEv6HjGvN8uIPV60jFKzMRhAQZ0eBpRpOlQ4EA2Rsf1v qzO049ZkXqVo9c1eEcx6YPajq7BTQVseueB+kANWsSb+Z8Y87RS+TBCHGcdjeYzJcDMzdtc2qE/+ 5ULa3hudPcevxAlvp8zctHWZc2aWTG6XSxXpsX1yw1SUts/tB5D0Y+ZN85LPB2zbgucmM6JOyDsB wyJo4N7NJ3s6RTfxJPa9yh6U/fLS3s+MYFCjNo+zTvZvsbETHdSU0ZHd7MekWvAWxX9kE0hlKndk BmtPzIOw6UI83bnVbsoUBYpHOEraHtCS4ZNAyw+3WDgzM7/ApekEEtStGlSAhQ8g2Z/7PZXxTkeQ SWJiX3HwmtcznsQ5wt8voIxdfxf+6aMTBMCRHnpeJvE/kZue0d+7YAANeLZ/nibDYTh7U/dUaNz9 rjMn56FFF82Ya9Hm+tWjgNB7e8ePqjTnPOzaNnpUb/6Ksopcprwb6uzlyJUVccUKhDMI799PSPx9 IkYr+AorWm5Ae6zPtEPC4MdmYgmloqy3Xc8KCW+i6TZOMA/wmfWxSrKjE8zP+xu3uEdBl6WDyXEG p4/R8gzvPC3ZRF4aQiXlMcdZ71fEswmdqSvjn7yGnYYYCQH7RyKGKCBLqNBUXXXXpRBfYrxitSDz 2XpQY20BX3GAAMGUhHF4RqahIMfNpqKoEhJZFFLHpSDcRyLMKiaSU+Hi4TVOBO4ax9vCmDm4y3x7 GI30d2n9TsZUDNWDKSGP5nyhxkE1iwyFYjluoXr9CQU7jSU4gURl8r8r3itQDzwVCLyU493h7Xxk aiRfckKQh8Hfpd3AqAcKOZ3DDCJ7lBl8GMINd9DLW6eI0PEVCWC1blS0Cqc/Ni9zMP8XP0ZsBCql K+Gs6HdjwdTPHmgWcTPK9CyGtkdZRVdjAbZNvO9Ipojxqfo9oxdYNliuS6wPtX485481c62NNZIe FEaqarwZoBXmNRFUFyVpR9V+d8IBcPHt/RqrftuiUK9WfPHwlwtHycv5vVNnq2+Gsc03AkF5AH2v vY4YbV/JVTI7GaQ662I6N3Fph1HE+M4UzcVsMvK9om/couoEvBKio0g3z8QXRjMRtvxzQtrcHWaf FpdYNS9y04MJ18y7lnFFBAu3xPUpnQd/cRGgS5vO99/1dmeZPQODdxHend/eSxKXuePfG6otI3N1 B3z+OSFNbYYtr3wqO2Vnjrj0xcxoaTkKbkD5ZL8zO4omi+Dys1KyrlXns1atVGKSWrCebYOSN9mz Uc2oGG+4fBXxaSPhxqAMS8/Yp1XEZTbB47e6HiByAPuS2Y1//i8bl7jZghRLlb4YoeegRw37VtD1 X2bdfuiOI+ASRxA3TT7gjekyZ7UiI8Ln58jf3LO++0Ko9nMbLpw2aiuD66fyArUZQ5T306ZpxPlY U2xAP2vCp7uy+swcyAm71XhLnF4MNzz6h5M6hNUDsuRY7TpSlJaqF6P3uSHQPfMnyxfXnwwKRqdz G/RVzLxLxpnEz21F7oyCcFAGsrTznKmPchvvPbJvfJ7WQeRLoH9na/34N6KWFaT9QTt0THezW/If dllS3EKwAEXAtI+upbiqdBH9N09i4Y6wJysXLU0bdtgKB6/U9Aor6YDYRaYiF2QeixBd0hEc4ftE V9ffkIefmGScIz6O76x/ffq6XFAe6/OFYvMybQA43SuduXIyHWQviPPgUxjU14j7niML+E/42at4 Y9DfUq0fUzyve9NUv5gDqT73NmmZIdEA2KDhEE7la4t8JOFiOwpEsZMqgzR3S2H0yQ9QT+rkfpgg x4Eoyp3NbtomGw24YQeoPTkH6bD4tMjs1WcZO6hvHDnizYEYzL0zPy7l99XjfO6M8boMBwgi8I22 o4Ixb15E43hndLedGBHKCeA2D0272RrBwXLOLRxDrI2kXmI0GumSAhHtsaB4t/mlbPfRTguPEnFV 7kDUWKzgH3Gu72BME4T1axsbRwN2EMtHKXPqaVpSWq/THKg+wOdaOkEKBFdpNaB61wgLhWl50tTP oMi26HtJXrxd16OYhtHGbI3wxdYCpSW9HkrqgSd2I5fRzD+q+f3ihC10TISz3MJ72p1D7o5renIo IoUW8+pZg+MJJI9H7Lzs2Kt9jcjLc6yP7+QrsEyJaFCDg4vUovlRNBaUqZ3MderY9PpuvL55iJK+ JYdT6WURtGx4ZCm+M08rIgFP3tgJ+GhL4boz2yzuVCh1ASngDRbwLPgJve1vu7lRg4VQcOWR/bLW vmCXKqZc9hSX2blpuPpdda5B4WT7R9masRadT6Lyy7cx12v1T3BnCBi+u49RCIoaTAD2HbO9xnpL yKR0P7RwDP+Gk2yTaWjWQpIeFwudZpWW/CFz9poMZ28otr/cCGkU3nBFydYYItT46ZWXkI38yTD/ /2Gt1lTFqV9LmFiOIFNpy/GACSuQZRT/jYDdVQP+XVgivTJthOqiamMJS7gsXrgwmoiGPYfDnH8o 6FOdUYCM9iJ1Oaz6UndXWpbJfDi68FJjLt67uuYWnQpm96uFxDLQNpnE8709tMdPVIbbTQRAywww T0vv3QXhC+UA9Cmkz+2MCgPyw6+T/RzEeZ6MS+Or8MhjPgt6VfxmNbBrXmdoYnyVigLXsTtQilsU CjTpidcamjWb3nM9RQJuAYn6LBnt29Kd9ENkitdH9qT/FX75Sr1pbuv7Ymu+xVN/TSeRX5+xFpiZ /gEZF+SOfERwPp94CNStq++gOfvmC9T4YBN4nqoQPn7/2imYu4/FYIhZ46AVk5PUQcXvs7IMvhAi zE1Ja8IX0lXSc+bobePfpDarwyGyRF54/qSEkZBCujiBqZlMmt7rkrniV5SZt8yuhbh/dyBoPBNv YRIjO78Qbs6P+t/Pwfk+8xO0j8Btwtyj4LZ03Qcf7RhyNN0G9VkQSalkwpiZh8I0CR0VEcjAE2wU fGrzmEH8fFQVmM/D3zBZkNYH6Ga+4ofUsmXp9YR7J6Ja9FbX9XflH2ZdxLn4RZ5zF0Aj2A1FYLao hvHpKmKkJF8Q6Nmcu96ciKxxO6hv4vCPrBqwEu4hwI3+tsDxq8Ntw2xbbM0IUvGo83FBQvGaBvKv EsjvG9h0aAwFVTdhc+DudtOYdcNpGN7tUbWGrbYwog15VkMWr3WGMOLLzzbaOb4TcfX4wKF5nbjo 6uB5IRh5MlEjLFArDF9wb3EBPCrP/5p+6axcEui05ybRFn4N0mkDuDY54xOxvK0gVm616kYkNQiN tveZC5B/b2KyQMKHhyTptwDTOybQuGCRXdxqmt+8KD2gyEG+W4pNkRipjh6/cL8WwQQ1VjPtUU0Z D9hYBdzIWyzs57faz3wzw5wcZ4nIjowcBO4Zv8YhsvGE/NsZXroRMSOG4nf9sm9kPSlAYzYZm/A3 F8ADHt/IzWrh4WJEqsWNpL5+OWkv7Qirbk1QKSxio8XJe3gzRqmb81KI2tZM5hrp32vJJ0ABGOMq vMHY1V6v4lkR0huKjzzDnAHedTYcL76DEPAtMtQv7jS68b+KuYzmE7ny6fGo/3OYlHm2OM+tb5o5 HOjkm8XBX8J5uKPIpcNXaOT46DiClGVA4zf8H2Zz+IR0tZL/R1DuSYqBUOjyaT9b5MNe7c32LZJI +HKKInIC4OGLxr28D0AX9SgpgEIAhXFiQ6cGJPn8+Hrua3QA0c/VYv8c0aCQzp8yguur2fXTr8i6 BNR0ZNSIr0dGuFeJ0FLpcnvdeF0g3dWm0VzxJosC2zU2WkPzt9TOT9sQH1cYFw2av02LadFyTxLA mOY6/JGRrpV7KPsAKmbr6T1Z7KM0oWUoEHXV7oLAyFRK09XjHq+kcLYGzcUKLk04Bn5ugVY7lVdh m2cg8gnD4uHZID7b0nhldYMAF8b53rVY+TKNoYU+heVKBzlxtgAopWn9pjVqtVoO1it58/t9/p6j vdM32efcezoKVb5LN88DTA3WAhPs2A4jRZCtIpps+Nuoe9nK8m0Gz2tjaAbRuLunuOw343L9GRKb 1vO97hV+QFixnQXOt2L94vx/JL3/OMIfWU0jFxLfQsujJO9TbqUpI3D/eUx/iTAM86HnRDCxisIH ZyTRnz1lX+gXORlDqlK7OYJUsgCpmdG2oje39tu+cSe2JYsAimfgcPURR/qRIy+R2YPpzp33WUzx /aMw8lAdA9lRb66nzynhhh91kcOTYYS1Q9FETPlFTzPn+JGenHGHFQLhV5UgqWOEuacg+eczK66p mvGULfrD2inqJJnp8YO/YzeXB80J9kXkYVwsA5IzokjN9uQmDf6qCynbiyR/q8Ip1uu6dbPrzklp MBbVUi5oMGDJe7kYwh9Z6aJoOxbEZj3k3wm1I4LmLHkJpvC6S5/9scH/O0x1fYRetsPKX2twEF0y /Jd3gN4t7u/2+n0jpMpY25t0eBh3n4LWEsRsVPOXCGEWlXcted5Nz26eR6JGK1Us00Hq3CWdUUUX tk3YZSXzEWQoMXtBt+JTrBNPuKgCe/e/0nX00oMxoFv0FVG7ObEjWgwRHS6WE9p6QcnomradRGtx kqCbbnRVBqxz5Mf8cFTvpXjEdEYe3Axx53i34Za7hXi4g0C99nfejxnCqNa0Ln2uvJSJfDnKG8XN V+mNGPnkCE4GjAafVUFyfxwZJzZMg7zGJy9KMrK+T5FraUslQvtOi/DIB80m2u3zyK6Ml25WKviL 8EhruySyogyXl6gu2P83jHlfWG53MsIIUUBnaENzCZnDvzhINL5I+wanrALh3QOcLGifGTXqh4cv X1SqTG1N2mD543yxn6rv67Td/g9o8Un5RIIwRfHOVWLO4yEJYd4NyHtksphJLaLogB6TsTC+nFbI 8a1rmn2ChIB62qzuQRXAzKScBRlXasNCuIeFHCohSNQXP6d2/PNV2KaIsFcRc2Rfva5+vrflRYHm XzZQSs370usHQakj5ujl/vt6qZALQoxx82X9hK2LohtD4RAgIqZpevIC9xZTGFOKQZCM6WADMLO9 Sy/MUsVYHmSNZA75iP2m+unTeIcCeXhRQwNUnChJGwjM/X+lx0nDtFwX3ICrXe8Opc5UTLnPG4yL uFPUuveh4i0LfpSU71o8s8jJIQrRxYn6XWv9KwuFwYOf1uiVLgSrqiK8Mm6qT+9rnEyFX/eMFWIt hrRM+v9IgrSafiqGANLJOqVOP7vMtRWF6tF39qfh0xYV4/nrLSadoEV6MPt8LwNdwdyc0/IHf6zR D4UHlqrsQEyl/J0YG0tuFiR19tnXKdQ/nrCE/FGRFx+URVkWFzEEaKvTjkNKrsccMS+jz3o+5B0d m4tQyw3L3OXLAw4K3jmYbnSUH115rcjHdouHOhMLj5zRROFxXdqxI+fFnb0bkBSrUJaI6nJVropo B3ISgI9pLymWdcR4/SUFy9eR7KLsv3DpaVHkTc6l2LA9CKxtgbKYPtDFIYrVu937sYfils1RP0F7 1dzJsrERTn1zQ2B/fR+04zstK1lOmGHfZOltCjv2iifTND7x2yHFJ7Hf98DFFd1Pr+gbSeEQTm+/ mJ13UHOpxkEWVGBwen99gmv2bID2R5qfdga56dU4Yef6wx1BJsgWagM7/Dc9YW4qJD4YadmDSDp3 JAkLSqvVxG6CEITaGUOPStWJgCUP2FTlee1dO3P7RTqqIPPiH64OLuGjuO1nKjN2LY9aYGB3TGlU oPrthJl/hWGjH+cPnqQCKalFV55sM+wm1cO5tM/IahiIRjfGGYoluoWsycu3C/vJz47/RzQ+TGJs gd3ZuJR9IIPdCu96tI5RDyQJ41mkd9l9dSBoKOYavc1qG6koJ9E6SBP7jJdR+J4lgMbbe10Rr058 iaM3GzXg2cMGiQO6a8J6YEr6d0+TUMI9KzMEIiENL9ntcvd+3w+8P0vy/Xkp/l7O9ViTS22TLHMz SvLPi9myMfprOfbfbBSZq/pXnoBzWi4Ur6laM4pZ9n219SfRzTByxLzYNBOcOSEywBjBozuUZpRj gYrV/cHBFSiEciblkk1UjK3wqhi5OPnJPTFCAeDbqEKiCG+nkndduyrWx53g5Rp/hqcFlM0d3RGK FqB4nVivLl7rNfqKz9H1pKyaXhT9FZnFLsmHBe/8fZ+G4kv0251zSDhcB2mHxf2ulDZlHU+lSzOr IDYUEFNLTlHpxL8OUsn48Q5QO3ppHfKEWLuOC5KGjJ6QhwYqVaHGKJzAwl65xmomN469AQBV+8Pe ZjDFUAs9ZlPWTa0VaeLAR9n0NRCeVIGP3Mu3odAQjUQU4T5f/M/y7uKHMPA9hTIHUiVY36EPoXeo QqLtmNCrKZpMrSUaYxwY2wGMszd3HBM6Kmy29NkSTzvIy0lNmxH7EtCH4Bm2CCG5HI+AgICns2OF DAwSDm4YEm/T1fePyp1CoWzfD3J6K0Wz1KfRf27q1UNDpp3xEQwookWSRp5F29mMJT8sdH8xbdY3 I2z8YGjzdZP0u9wRrALqjzKFog6FNYdGZMYz32ZQ66AZFUrtpDUeflJzcp0DiKrNT6l5hjaMMqY2 06aYOPtiHcJ1WVrGi3wLthO1xM6O3P6T59WC7zK5LPTr7QPsaMiBs8Oz2O8BPBvZU9LSY2d2v3Hb BOofWfJmEo0sEY4K+qU5U/a/TK60KJUJohJ5+f8eZZzNErGFqdFHYZaezwwLsmDYNG7+kTjfi23E 6TXPNnrcL7Q3MU65kQZek+3EJB8KaH6snhplJwo/5MaKjP7bbGsCRLKYORxwpXGnIS4By2U0QRUM xqLYu1UvDOmLotrHFC3oHa4LmFYoOTYRD3O6H2iHKhFvByN8Lhwq5lrAvEsL6SKgUzA4IF30DMbN zaQ8jtE2hXmXZGUomypNf7J2oqwM5YCwoJnmgCCgJ4EMXxKmcoFL+KTde4617vmcr4ZHKnjy2FMk z/ZqxLLNus9nYcqs91REgmBs0NOzk2Jj874cH6manYSRBQ+3xKpsPlk650nLU3pu5G/zDgd7J9GB 1E1SMNIwfZ68SWeU8ARIV/UywTIEY7o0wQJA2Hz/gNRd0JEtj7TiOLcgZc8GJzKztdZABAE9T+n5 eszuf6T9V4ibar2y20NtN45pJH/RwznzvbgoI+pcbqTWavEfez+GT0e+p1+BiDYfKMmzPRafN0fY S4DKxzpjhSt4pCsgOw8k1WvUFuhN1DmkBATSz6WONUuRx3o3ZrTQbhyy1LErUrmS4bRvRwZQza8N kg6JCnbzbDaSMq+0L+ZQbPEaSr3GNO1KAgk4G4zYfwQXMBqs9AzUDUeM7HrSvXxngMMKQT8+jmWH iNSt1kZSp38E9youRWnLQTiinWt1pvvDX0RH67iMUsoabghzr9bN/wYpAXEtYUXsbY7IT0QghYWJ 0gIbHL6qg3XAd9TjC2sRJuFCrIilEEgVnIGITvTOc+Ffz+3MJfygml6MyO50LnNObFfQIiSHJMap nmUA+Bj+kvMgqrAGKENmNsjMljB6Brlnf5vxONS8qn/8OeVD4bpn0UkyUA1Q5VthjN0rp4znjaX9 v1BcYydhf0+i67mqvvHyu/1IV2bT7LteUVgGJc7qWYtvldjfIcHHOJw40OLonzsx2amdUoBswH+G LPCpdKa74zgAqBGrzf+/jGAbNWui+41mfJLThQZ7csVb4T1ZnSI4wuuRKKrBwIfmnNfdQGMp1wIh 8QvYJOCkQ/ext47r1+yhpvXWC8Hm5ueVafBnjXu7DYEb/z79BnsKCVyH3X0b4G0P3W92+wEgyVTR HiejHjBA0J2lHMjiiKaUvpnbink/+U+0ZfZ1O1oc2Lb9QaENfSmR8tCUH5nDTZPbI2pD9vx9gQu5 0OaD1BuvHymyu+Qa3JqoKtZLydl01+BFzBb6V4Ab20Qj+Xv5XCSJuJF77+VahABZ3ZkaNUMXVaCL i19poOdST8ngR2MHuYJ0EStOW+MgLIKh9vWj+bgD/xxDrxookpKFKvTFW6maf3zsEicGkzb7wLjQ CxzqVYFzBacIAR7zalpy4fEK3/6/j3uRNHfztbwRhGvcs0y6xlbL6+iJ9QeuZXBZBJ/YtolWM7rf vvuFSvf17jT6RXyFDgDiPjkAv4oQURpOyRq/M3mn6a91V2RKO8cM4gr1DVLspNqs/5UV90jw+9Ah JknqbnF7NifvDl5/q8tILOrePux2OEd0zp9wMH9XO7aOKVSV/plwZW9xlub8rC/pLJpSISPZ8xL9 yFqtD3mrXzypKaQdYEJQRFgiopDrkCkp2qLxPa6YGdObOIs+Zp+W03q8/FdI4F8FPnm+F9r9WtkW 9PL5sbmXgZwOo9zlEYmLceq8ENoWLFHRE9RHbNrOtW0F9I8VQ/fT1nPNIG3eYTya/T3H62kvL1vm PPH9rItxrtH4rkHx7tzi6RA+fSLUTVR+8tgn7/A4edK6lXQ4zTjGLvPiDwDo1I2V44bqbcvISAWa oMiguQ51yw0KIUQcsIBB2vF3ASMRS/+DTlR9DzJTdQZwmqSy0FTuCS09KhrUcxc5NlpX12PhgOdN ELQUibI/Qy/Ljvcn2at8vSainbL6wBu7ihPWHwGzbEXqwg+zDQadodh7o32YHhKfpKVEPp8+ynVP f2AHxjzqD3zO3u7rhjvOXk+O8O29KlBdTV7F0ZNRxb3D7PfFhs5y2y6rYqqjBfsEi5habyVG5VJE mdLd9Bsh8l1iYPqZ6powhdGwgkF+eYk0NscKG3pJ91zVNDgV3lmgsLqsz3MWHSqg3k5vFQHzjc+x 7PzreRrsCdNCWEs1Dml1OSBteHbI1M4EZ2TPBk1FHQzidDTLDaUXQJSZGOu+7+a6bNKhmJc4363j fCTHwSQFIfSXnwU6tv/vsqLzX3cI9hRsKYL6lpXTApyRf9bht9ZORdrlXu9MXmes4LV2q5/BkW4K Hu+X2SCaQutbYXqAQmEeggKM6oLeHlaZY/N/rnQ73WBwZN5WupbFb6MADPHWe+Ly7/5pqQWTnFnc 0sJD0WzWLa96gHvGQbPgIruoa03tLv0Fk6NatsbYOnenq/qNMoWiiGHb0a4B+3fGEAHOUKQM2Iqk 82Lr4qrR56Iws+mqAv3+fcRBEQRH1ZX6dW24i1f+HFOf3uiNJ6glLvbWfaSffldyBsc/k/VZacp2 FevdVTfNs4hAynpV2houNtns+4X7sL5M232i0vkd6AKYl9yvRq9n9l1ZmfWVhH92LYBE5fCeKAji Si+KDljn5X5PwyA9Ffm5hJ8KRxjAmgOxxvseMxQGjNyxpALm5Wts/z6zd0UL1qEWTMlmANicI8yb 4mV9mVbKjr2TeCzW/11ROAuLGQz3n9UZdc7wz9CoHdgOgQVe4EPHmZzw/KB4LdLbBcJoBxhrZ/ox JwQCnxD27gFMxQOJriWOQfoQYlIeoZIz1s2+R6ZC5vWlBLJeHGx/dQJy46eU05oEc9PZYFt1LMC1 bwivUmyBi3/G07QIHup9fvguIfBW+ucej/q3P3fB+Mj9Xg19ilhxatAAnPuNqUrYBNWbhrOWbhig vfb7de3x/GBfbk+cNF/P31q0isyPRJC8GJEN0NEnDWWR69Z3hwpjkAwoRwBjYdnt/sxrSf9jh6E7 XEw0tmeOPHu0LoI54kNn0UkVmDoMpnOviDIylq4tMno227ybD/N03ZERHsfx+bAfgDmDF/muusHL e7e4PMwsINsBca8VsLbEzpuYPJZsQlIwjxI0lzl6Km75cchhdtpiiK4EK9szhU/Ki9c/uU2VnhEk xrO3BmzztYmIEQb9gmG50d/zTXV1vRwSrZ9z0A+aI2wfRxbz+fHaJmIG+xOYEd6Zzb+O8RHYTkFk Js+BT9TW8ZEUzb8rYXKEE2Zl7Mv9ldk6QGNdh8rSIDdyY5MyE5xXRsdA07atihml98lpIq+aMNkK O/xHPfDY8zEjXJZ1gkI9sTHkEG4EYmdBMK615IuALJsMvVVecPpwyfj4WESY21+TilHekpDaUR66 pxa/AZaGn752EHceVIrEef4rrAZ8BiCrq1IN64gevZtjJOKGo59IBNHmzJYbf/pdJiy8C7TGHgy/ +qpGH5gIQB+eVmJLSE3PSZ3EsvHtv5+PY3D1Iige1EqErfk/2+XdfZa3s0VW0arJKahLVZ+3Yh3Z s+ocWa10X66NjGuJBzxtkcSsLrJQoqO+KSLoVOxTht1h8uzyD2KPp4ejLUqczzRmPbUTPtxpDLQO jclHdWdq5lOjtwRMkr/HOwL+qL/HaRWc+8Z25n8w7C0BZ0JHB0DaqZh1uKQhzN6yWS8+tCryngCl LulWET7umJ7nUP//jBRh6XNLdumR37bhlLd+Ot41gImY+MWFFxI6CjOsD6kep4vLOFDYZgcLstYh n2QurSN8LZr2W6SfPkxdymEKYTuyL4QdqDv+S+Xi/TgHM+I9KyJhaCuMcE0KQ1j4hUlOJyR6+xr8 7zsQYcKdjxj/zmIPhx8hX4LcXcPohSixpHpUsC65fOobozfHHpD9gKVMSNhlQZyi436LD7QWYGOW 6X/GKqG//YgSuvrN6OXLnUNkqZYFQiwgwT8qK3KVQm7n8eMkpN1b32tVkudV+0qUeQHI3OtmxeHg kNkWmljb6PhWP1b43f5qCX4KcR2ptpNtjdm16rXq2lYz+iSmocemqzv9F+rVyq4k+tdoguKRxKiH i1tFAfofG0lEfUpNQaQkido29tJS5jhTN7k7xbkwJfEJ5kAmPczplmC/H2WwViCbhamEkosXYOP5 J/4iLJ3g5T5q+vugt8P6I/k7U1k/MegRGaHXWJveXM1ZuEaFwanK8iwMhGbTV0NKNc1A+z7kbwbo lhWzYaLTmShgAXvxj7jq+S1ixSuAhdMjB1fo9ALCYgrAppY2z2T/oW314Nm0M62BM+wmSXjbF9jU FF5pijjl6QbBfYkjFXAbxUQHTbdmA6VG6auAyKouHR6mGeQiCqwl6PH5OAlCqFziFh6+56ISELJf JGyuSGC+6nbZHCFVjB1u6X9SZRE3JZrw99+cXd9zKT9czgsaq4drwpxZ+ScKmBqX1UkhDMvb06OF VsNH4CtMfvug1lofqedN7CIb5JqX851gyz+5YH6g6P9GSWJbb/Od0Zs+bkXEWr6f0TfeVhcbW0ug 606bzSDTV+UDl7d3Y/mHv3DgVvirBR9Ls5Fjn4uPxQmA3iUCJaTeZYeMoSnDgYmr/w57vjuOJhz/ Bn52KJqGOZQCiJHV8Bs5/wwQgvSWgRTDOGYKDHxy8wU8tOhbzcsvihjNbr/iB/J0pLcSrmGl8aJT HWqYx90bpde6D0xjKsolJwLxVAlqKhb9wFlwBKQImhVLw92e2xdisFdYHT5NYylgpoQ/gIR4WbkH T/h+nOUoN9odtafnXWKckOLINTctGRNNA7vTf2NKIDNrigtTszMo1B28C2Lx7Z3QGzCaaOTH0jOI B5iAsoPhm1nvxm0LJHOuZhkdWco3ELqCPSqHcOfB39NKcDPbCgkZzOzQ5j1zaMMAVrdZ9LMqCUhq qrDagRAZrQzY+U22VMyTVHDqbPEpvd8R8urkfhwt0vlWoKdLzzW70mbPfOISLfkMjGOP8IBjCZmk ritxru4WtHkN0yQRBXfp2aU+GcDDidEG00IwXic/PbDl1ZyyJmRcGHsScTll/zaknCGqspRux7Zk 9ynCSPcM/AKcYHLAZ8PrqsqVn/aVnPwgIzjMtfQ2Oyq14NZMGIoZNxUiW3sa00/uz9kKBr+q0Qh5 XSAm3r+JJ+6MrwssQVy7SzY9gHzc7Lsb3/dVxS7f2+d/2NvJl5KEUzxdIOppJOADmiPq01mmHOnv yv0A/8VKE68jHj/SR+QW8zMJcpTfiUmeTFSoi5PiIWMakhvsO/LjDras44sBP2a7REOP09jxEEaM MNej/ozvCIczeyW3TdxDiR7+DlNWcgCtpNgj+AMrElGn/3FqOyL5F2BxYfYPKTM+tSY0QkKqwldB p+7Ioc66rJvxWLHN2iRyEAuSqlR1AXcgVjBsOTgrvtBSoLGeFhR32n6N2xE2yh9UpuW3xXXwBMOu M3D7GMQ1iC9M8/lKcfhdNIMhwnhM9tOKuA4ZvxdB6nxDrNeDVTq7vqnqWfEVBeO7po6mlrTYB3kj bWlOajy0L9TsA/kViFyTHXMN/syxUkgzV+C77E48v+DVPEn9KrTPNDEnS6qYV/hPrVtRHw35/gzI 4CllEuG2EOU1GaCwLwPuJbPv3+oCqIJ4M0saOfbuheN2U4IyvpcsA1QJDd3Y9vqPmWbwf+4Ra7C3 OvtLinUCASLkj4zHrlN79So2/84KP//VHoygNmpb0teCWO0gig218VnKeuvKTx3rgDLxdZ8V6r4a Qfie+azsB48P31/dbkrsyqcHaCcCf5opnHWw/2fMKm9SysqNMmTCl6J+bCe1yewzdMNgwSh7zCJt 31XJT47CLMsJiGoQsTvviNFrAFcg3lo69LJ/1+ral0sqlYirAFCB86II0A4S3Lo3v9iXSOPd5A4Y FY44AyK72k3/b3BhDAyf2It+jUJApVZ+MJFAOXe1xNY1zKm6bQvhwaJXoOKyJzjkslcf8eqHVV1Y 9d98XjmAN+pas0D78eCiJvE4sl26VVA7mA4qt4sC4HcRqdLnmuOAanPJ7ObHueHTiah4lM9Jhcwy pSIsf4WfpOqf8+oRHX1v+fcSlztmlK8glSqYAx5YWG8DCnLNKSRxXbUm44/TW/ABh6ujXLA7z24M KM+bSTLhKa7mpq8sK86VcbFTpU9Y/l2ZhTACuY7iegSD5ugZoO2lODtWgSNB/RqrAEbMksbAcYWd SJ4ifbQOdv2ZoFnvvfMIXNEllT49tYLGD6nLH6O/AHFQ5DzjSKUzi32VIZoZvdYamZq1ro0w0OGL ZnO+ozOaiYX6j1Ip0Rhg0umVIj4qnbnv3XasYjzq8LQTLm/IXN2sBlxmLtP2T34H7aK06l3EqSM1 QCc0el9tr8n0wwSWVZzsxkxOy50dQ0iO5SxFfb1lG2IeScwGc9pWEppky5Nbrb46EGZgyzJGWmAC pBCEFcgD4Zmuy0oMW5HGrbfPbneimOPVrOS1+xh3BItlbyEDt1x4q4sHmCUXqSfnxNnp9ggIrjJj kD1pcUyIUJ3puzzBa/5rwb/U/Um+YDnVFX+57aXU1HMLWCOTm0aDJw6sZGvClq/2lBJfBkTAOsXO 4smpoAaTSTB1jiwPwV3pKSGn/hBu/y5tpZEZIYu+IQTxCoD2XdSGZ5opAGQf/PIQTJmuXJXrAyqG 21C6FhazJb8Mef928CM8pYLq07fg6O8yyKgA6WKmWeOVhyh/Xv4Ds87Wct4gPcnoYNq5S23HEcyB Rq9qk5y74jtPMhIzUmcpnwvsJ7FymsYW8wipnz81Ynyemj/Cl1b/T1gGKL1guYsZlsMLYhhJvflP S4vA+4T9mpwVCH+n7tbOiVsTywghGq/K1zk3waiSl45otemtVaiD0mUrg2VCSoOBXyQd+HtOAYxU R2yRyaJBaNXjwps6n2wGgof3+w+vmbRy1A6+SXAITLd0deUr1g/aZJOzTLkpOsmfThHtHKfbV7Bo 0ZlrlwHG4ulvy2V7sZU6oFKbMVE0fq5vZocWHY8xBZ7F4kSGC6FM2MI+LpQXc8dazWEXuGirRC1v gTpZmLDNVxH71a8UGh928rYPR6dWegANhyeHAQJOLUiZzt+wsnfPle0UQujPlnDdyCTim8UWZzo0 eiTPeUay7Cf2NZQKrMZxx0Ta/aEXm1k9PLcfWQ97edSDF9LZGFjC93ZLD47EU3I6XTaZrBVf+FRI J4YCx3vyAQJ4PT+Gb9T7J8JM4CTDYH/JBojnQTjqajaC0xYHadSMl5uBZHXtWMjRjklrR5FfIeQ4 yeTaXc/rXxikWSu4AndEi8C9IwdHB4Mb28kBjUmibm+dnAwkwtR7+1KonyMucxy7FHx6VSGnOr/q 3HRj4yCcqeP37F7Jrc0zL4mcmm6TqZWAQ0qIfcwRM9lG/TFDvSXRa0KqD/ru1fI93YeRYAK3M18t zWnsKqfjO8WJMo1CCrPrcotT32+u8RS3U2UBSW1TDuwN30+WI9wN+Jy7CnqbOEPz4m8PgjDaizHj vTvGwCTiw1Nd+qaYbfl7F69YwmmryVsdWVbBD/P3RYdJkxGYZQpuSG6o692DzrdpgKaircHJVf80 w7wG4k/pMqiZBx2ygTlKLJ5CAtsA7f4JuBFeL2xu7pOdBpYzpmpsEoWwcK0ad8PwV3idLpT8dXI+ N9W209rnzJL5wmcSsQJ7okCPUSDI+0kAz3JpecHyJialF7noFL4aVcuT77ChtaIeaJ9rSKot3fFj 0wmL0bnLK9AwRZQhydoVefvpFreQcmHZJVoWzb+KOh8uSPCfpVD9eB1Bn0Nm+mzEuICHxFnegv1L jH/XoXPjJT/69MtN0szvm4J7L3JdOy/gik7Qspa1qpeF3flqvynzz4JQ34DhzvbeEB2PFe1mjczr TnsgkEhOfIqiEr0o7SKdpsk5NIN8q86S8G0BMHKpKDTPuvkbY3ISHX8LoWilU8fwaGBREmZ4/+eB cLNCCD+ePshdgjCWBo6lCPxEOJ8vlS1v7d7ImiA6GnAVKYuq0tKOdyXRB0qjPGXl5dJEI8TnaDFb tRJC3mLGmbYQXeWZqPJ+LHUWnxxUonBMVPJ3J65ZmMyPoOIC3Sbuit1ka/FfJjLUzMF0X865wWQq ZJ9Enfb/pxiszlnhYWxziuA6tuJtnqBvjUpxo4LLP/s/7dhH3YrYTRqx0E2sH6S9Tlx84FGeyTCL FRa4DcXjedUnDhwlwlgsYGw/g3ECDRA1vK5LU5j48NHeMTCt5CSs1y3U2bF8vlHJhLjVlfv3Ieee aciodqBlgceanrLwar/KhD3URbkctmbQyPa+LcazvdSoqZPI5tCGcRyzkjsojpzJgmB4BG0PkmNu MfW6gI8rHkPaz/rQzkaJVJdkSbNEQSdc8QuzeugkhJNbaulBvP5KNdRptBb8Zk5UzHqTtto1pB0p Pd43bDy51l6cmHfT5BpglvHMX55zqnBYeoA8sJMnWwwkadnI0aGORiPDI5+yxgrIWumO4iJESMgy U6d8sh80AsC73/HhFbKwa3rsGavHtCyGiVA9R7mb/8k8PzU2GpTzmD0cpJxMrA65h2JPjFqtT/tb OYGGOUA8E8v5vucm+d5xyM1/BVIcpjrjerffEvjcCpBngeyud/QNN8O7PIpiWDzML2KshqAw6/7B rrQqZq8L3NvmPpk8F3/B4ktSA1wraXa3VYfXg3/dY5/C5r0s3dRrZKiDQ5KxtXQRazR6ZQnwntQH qF09LdYP/EDRsvz8aVLW7Ngcj5vshWcOoIX+b3gvbVzOEG3p1j2gykDNLF2sYBrF16fELMTW+4nN kK7WKMvUkBk4inVXCt+m3Te4VA64z4TwiINcRdwurloD6aVPQ/7KxECz3y708QXPCBhn1W4j6KMa kt86dVr9cD7mPmo4WdC8prwnKVzW3rSvAhLJ9qAHE/7P2xQmY0ht6gM/VMcuQxt0/jo1gxl6uzU/ F1VCn59M2P4qttFD9yyrYGctLbIVCMYLJqgnSqWIwz3tXM8KINaDJVN3Vp7t5VdVc6Yf93zuwdX1 XH7YBKQMKwJ7jzhlEK/+/P5xP3cC0H3UtvSnGxBWSGobHhZ2tcd6Nqn1DUNCnWkf47U18KYHszOa ESnJFr1Gu43jF7YBNN2PplochpxR20TNKfYMCJckPacQXzhSvYAVtutnofDPvCc87mGas4eK02to wsaGz9i5BLpBzoTFzYr7GSyYvu9a1WEzq8zNRKC44W5/2OH5QV9Ng55mBK5Bd9YER+cV25wwAGb2 jxSVsmpFMY1c7i2W+/fFpjxVTPPRFMTkV+hTmEw9B8YLzm7uVibSVMKILYJlOLpeeqlhOx95uS1j tulglmlJtdHxeYveivYksKgUVDE0B1xO7affu9tT9Jl+CiuaR+kOJ48Pyd65s3LIgsWTJ9FlzXMx R7VjUjhSBb9smcFnsFA0ndVG+av9ZtIORAkbB1Eb4i25PFROFFETi3mKKPL6r04UwvbbmQU/6XBF 5VaVcPOyR0Jj0arlF4HC5Wbkr4+8eAheBxx9+cn215sbarZTHwqRdMbBII+0P8UeDcEPwkFoKqUU eYI/U6e3FkDL7LHc8KHYrYCX+IugzrlaBJHDXaE0F8nJiqxtmsAiomCT0jsZKkSO/etUqZSSuiAS +jVR1JDOqsSyq32ynjcNN6GXr6EGxyUE/8v/X0T7uKy9xomI7CScFT6czlJSHj3PNxOSONO7TOjx 2DGZiPVL2Lh6tf2a48Pnw87F6Hzjzmhs9zPJ7sYjz5gdDQmcOQx8TRtMu+zyL3PCYmU2/QxsZtvM qz+eYwvAy2cmgjyaSXpkRilptQ5NpWhbyveE5MZtho/DH25vxHDFQLG0UEdLaxtQuAmVS2Clr4+f QG2dj4HV2DtKbLVS9GsavG5XaLcEJVa1KKcxMSrRM0xRBVjtNVNubZKiq6/zN7BWPjQ5DOS9Ew6N Kaq0lr+e2zDt9tPdoejhcxVn+3Z/NM6vpi6kwHuMsdK3KR/t8lw/h7yzjMtFTu+JTp0KskHJySVN vXvQcRFLQ/vfwWcHDj7lMOm0sU08L9G0aGl4Gsqb67KbUzk3IkRlHGd4D+ovEnAji+7ZmY9zH9dv rPfZyG8UB0tdn0AgKP1r/3mKesMOQFdy0DVcIZqiJuIx6Apwu3oso9yTzQShPK/D0TSnajHzQDSe XWU/YIobSDw0U2E9gpQZqPVTy4Vt+8RA/ByQbkJ4EQSX1Q6sh67EEo0sRzBjmVVAVdEx36x8uT0j H8bIoAzg0KC6z6hNqpTgY2DLsK6q0ML+VZ2Lsaf8vLI6EDK64uypDPmzwe9CoFi6R8P/1WXJG6v2 OiVSTASACh4pf5nQ6SXllNr9yd0L15rHQp9S/jDQlIVgzcRKGkMkY5nM3JCzYcp65HKLP+fYJ6on GbaYHLVnhZHOTPSAIL6Hx4VzK9/RwWOb/kQak3kGpeaK0yFT8uAZ094gQyeIjdPruSLEkUGHPSP2 uhRIM4ID52hYDMkhvf4qUCgtfz8QZ0HDIPp3um7bnlfQ2v3QF0xCU5uvvbw7UIdcdLJDfH7tpmso A0/wKIKc5k3roqjmf5qpMt3jjNBQuBj4S659PDArQVqtCyWo9OVSXjWBtepsGosz59IRm7v9Bjfi lIqZdZa+yYi3WM9u3MpORCYX3ph8uw9CSwMkorlPZ+aQlKvg2E8HZm6gER3QZLc+35+4LwPuMk/+ UmxqidTFkiYsyg2MFZpBQtV+8wIArjXayk85s/aVH3LcOcCvz/ROqw+zPjnyFeCl3eCiEWbrUUrB xx3xeswFGlyveVG/b/U5wUI3XvZ6wBrweLf2w6u3DFlLpjEfjKRaSPHMhQWSXkgCgPAftqHvAhlr eEi2zr3ZmeHJ++Gj8SmKn6Ks/p9160dqFVSuD3SQFv4lg3WJH2d7O1ZAN5JPSMMsBTEAL6EbJa4X uCvpiHnH6HZVfTZ8SkQhpCEMbHQdwsLwuSek2qJdRak4n02G62t3H0aSKUIpgvn8mH3Dq0AOUbsn A5FJ1dcQdzx3ojwqTyQLzfP8xSTsG7UM8oP+rAhZWmqcN0HuyowvPcACv6bkC+KeyVGVnN2SvlZo P6fvttbQ9duWtl9Y65Plgo2oaEznJWObOtcr94a3WljTBVkONjhTNhhukruvuZnqmbcRlBJ/JQK3 lezHrPMkIpW7uiSSH0GiIif1XYGbX8HsO1jIgHD+erqWAEbUIlTTxpPgUQvwZ0BWe0NQQzR5fwLv JorE5qWLCyclWuq+xOw1o3sMzdPEqPBP3mrE0KNt8kzdAWT/ugobxAOuRarGs0B/CKvUBncfBg0G nEjVgBxTO4KSAbWhYI3jhrINZyj4qkl1BN+5F4Pvd1bkeOnZyiuYIfCF4BvqAkVSz//JuhOh+i3A b2odaDEL0iH0AzXtgxxPxlTv9GBlhOKeNax2oaZuMSCR8QVo6xoZKMxhfyFY2VdCLCmrQwjPcB2B rIz3DDthryWqjHytYiZb2uP2d8ACC78kEj2+O141YiBXO6GQ8FEbLDwYKOQ2DjaWHi9EvUqlm4KH kjKekRLBgIdN0ydzUJ8/dNL1gsv9AnZTIvHNYaDAOGCg/yeLxWIYu5XhImKk2lgR9p9ZMLVLbEZv JXZE+G5MshxQfEr/poXo/rqyHtDorNL6GLgH+LyBEN0oQnKWaWu2OvyGQ8iomnOASCcEmfp2vDvz kDB20n3zwFlP0KfLliUysG4FLUMPof73SgsxY7cHaFqeuQaQ6myl7fNJdmtEefaFYzJujOA9+eKT h2GCHiiKTR4IUPUS7uCa1z7F8GLvNo+8KTdaJ17HcRLPnRSQELcOiIQ/CT1fY9irI9TTmTefGz0A ZSGYVs7Ju5sJkDE3WP32y8zP44e8Tb8fOczM99GlWNTqjD0hwCVwGwe+MQTFHs55g6FjS0m9Cf5O quPfo1oNWgatUy+/omibitiv0ETunFxaJG1GUJBmPBhl1PKwZjzqkdyfY6pmRkO0wcRJ0MWAg6Vm Y8jZ7xHi5qWx9r28bwWjIdbILlYXpJs3fFsVv5LRXs6HrBCqZp3/5rizQxf7umI/AcI0Oz4YFAm0 JtHnylQdJY5DYG+olelyXAkGE8y2WV8Y/whYAeBAUe0kZgLdDJY9b34tWKGKcqvPD2gTIxel6xX0 MJa1pewYSh6jkUwsIpMeOdCZscuf2GN4/H2EQPomTNaNFJNpTl4b7Er+OcvC8lOTIiuKvZFNH7Z3 fYjZ18RLN1cQnLd6uJ8x061gNDpFDbAxrqISeW4oGyVMZUHNTWJb5wQXg/Sbxdl+hJ+NmxFjK3a9 Bat4B6uJAzuveNHoV6EIQvHuKVyECnI+h6QsqVbu/KkVh8/lzO9+AU0NswocQWcYOb443Gx1b9M5 cYcJDA3JE5xkm68MUvFy+5Ev5tZniQyQvywKyqChOKMP8IAN9AIsrsCgTpHqTOgRGqLiK/TY0zzA uZS46sZhiO4fID0bPfy6VIAAm4WvHlVcqY5VI7POxb3xCA8WlRCQ8i0zO6Mx7kw1+/7oSO5dZlVZ DhTVFnK4bhnBQzz91vwVZzkVMKYaarK/hMQVppmKKVj0J0HTNohN18qqZVqxYQbY+vAZIi1AvP4N hNDOTGt1GOQhEzH22xB309+J8ygnx+K+3AED+Tg0je86qGhJ5cSD++FBU1mIA+7/mYf4OYLTEW+3 JvGPhN9Im/B7sfVJLESMb5J2Z5sRZOXMhEG1F6HVLeKqO4SQguNqhrvGxR8aEU2O0sytBQ5sMuN2 9biqBoKfLXg28xPmViHJEwt5nK+PgBfQIBKkjoqg1htZaG9UN9HHveNlNjzIQ+0AhkIy1fqdSKn/ tNSgSLbSyFNKFC6pzoFWch/Elitph+z037RGsglBbFLXKIsXOj6dSDmRvHu6dpqLZiOf/KDs5jTJ IeW8GZJ8xjWdZgLoH5WtG8lYMcEWfAFD/O/Gw0dVF7Y9oric67EZdMFYuOJzEmpF1rGFYI3DTOP+ NfYqrJkZqA9AiE5VsRF0Ca0qA8yUlGA1Ml6VWYke2FFINnwotFtl6iECOZ8+dcUVlQ9bX1h7vAKT fmRM/MgCatt6ZPtjG9/YlnDgrzYbaN8qrRJAmgKgz4zHRsYA7dxFNQF1lGE5X/4ASmXyBpgapzqu 0t+rp9hyJNvsugkJ8tKKAgQJjFL9S7ycekAJjHuDTaKkpkgLC8YwpV3fDtTjq2Jr8RaAFjQY9KZK NqDeFAmy4xCVFEjTvGQHl2zEJziqFwLpuFTGsEFIxFPzk+83TkVBYGHvYJt+qvkrCDesMLsO0lOm q34fsqYQRw4cDO+jfAPfoNDGjzoIWskvNThiGN7DvHwd2sAWEpZYIwKSDy8aG2aUtZw9VuBHQ0ND gYknQmKc7Yw3SGJBCS+UPNtfW/WiEZ9UgX+UQjz/5h7jvtMxo4Z37DhOZr1Q+pJXOj4SdEMHjeWl pYsrqqGWyaXM/qyUkEknVcoLCfzChD7GqUcFdU2JjHOmlmIUeeGP/cVB0x+mD1xXRIfyaDwOgFcz HmD/3MMj7WuQgZxMG/sJuOEMiyOWnc6lhLVyuPUbgXUhZGySlpVv2pUQfNPWpuGUaNV6WmvAJkty gbKorPq06eIPhPnkOMpeqpE6rNg1DoIaApNR4AkQA1HHnVnzPPJiqb86Fjf0IJ2eeJtmq6BEXiGA zv/fCXbt1GQ7uXq8HfXOsUsizEULiD0pf4KquUEoxEqQcg5Sv97n09RdVLGbqrHhjoUXkUFUTE+k RAKORHUPzFRVDFbJRDvIPqw3Lzi/e6QvrgNKsyVkfVrJWMCEq9NSdBAhxI77wZURThunSx73Ftda ZHGiBpzSbuh2Mjch3d6mblesD8p8bN//SgpVClNdYg74JayVpiozO/PatnW9Skzpy8Yj49vbuOXI fCBUy6NXrt3tA16FrM0/xP9RDuGlt/nKhwz8AROBt6baq5yJhG/AHbNzWpeuQuymtjQlPVj7/MxN k9JANGnByh7uFIPyiqc7Wli9qOKmB/wFNHs1OWGnUVrvlU68YXohLR1PDcwLFNbx7QQYs/+rVQd8 hQd/eNlEH1VN2OUuDxfuedfRSRVGHI9jTB3MGtTDGMN8oXN29oqCfDBtw3f4Skjqj6wZPDNYByY+ DV/VqDqW5htRfgAwMqR4oTDSiZsv/9AEalHFlHBigwR9AtSAFcovSoTEBuybQKxn25Iqu2tDZUgj +DK+kZ6LmQ+qTy2jZzZ5v5+BMysSH6ODexbBjyEJgOdIGWGskd3i/Cjn0YqBSVsTn2RUNIuVS7sT i6jwC3yQKln5ISe14tJEOrvo+pnivdBaZLfj39V1stCrBfIzxyGTZ7R+TyTRQPLKe4E2YqMHV9ix zItvW+aXwjChtM2MjCXrFoolELVXBoskvg8wV2O4n3yR/UgWqcCCNz03cpRIF7ZPKtGA4Vhjrawi Op3wghK/xeK9yuPKzB9T/64E69GRpIL2F9SPQ5mpIVAN1JXas3lXFlRt8FTLZDj3tYD7hMC6+9eL lJQfTnReWESmW4dhHsYcrtC+Eh+3M9aaJY+ha7tr9tMQsqG6ve05E/1VOVBChGQ+HnpkhvZBN+1o SnqSU9SJQWUWf84WE84i/7gxUNe65bTk2D0B0nCOgvug+XrlYLMV2hhmUMo84vIB8zphnoXjlp1b 51u+iNXsUexg0qHlR5jyP8O9nIts2NzDBCP61GnZsdC3uAd5tQm1BR6VEEZP5D1eweO6OxQw6nZZ a3aeZJZucH2LoY87HeUiACEshexDQygLXR6Q1S7AI3w+4SGy2pk0UIxmwZc1XkiRy5lK0u6pQG4/ kXAfdzbJT6T+2U6menwzdauENfkchvum1jQlRBCsqy1NlYC1oK8vag1CgeR0PGcj0c36TUCOpL1v fM3U9QUXIBo9xalPZMuR0h8DDNI6hDBRr+sAnqwySLOWolwoeZXj49X3d1eR9Cx2D9J1W4z/zfte XUHIceH6hReqokmyX+nXGHBldcdLqYZCKxkU0cj8OAhqLxgpvdVD+SSa2pdsxhAICMzPePbDWtWt 2t4PPXisKJsr2f2hqX8JcAKWVpR8He+FsrqV9EVCCf8wu5Ljk+KmhwgUp+Vjun+NQZPf6J3AjQ/e qrrdEUVUezYeHxF9hQcxy4E2dmjLQaTbry0ZNVXcgqrrRd0P1Fd4EmsjozA5P/FMdVJqHjS+Dx5c f87/lbyPrUHfxRl5qV9jRtqffKT2tZqICYujXuZHXI6mAkRA4J2uje7j/NA9avcN5ZzoOKeb89mi 5ahzAw6cNC10X5paqbYDEgbifKTntKruFIuNyZcPY1x0d4aqG07enCSw78wPJLYq3fP3z1DCJKUc QpCQ6u6oizt+EvYvU8lH9Px8Nc6Yd0Yw2EoXhDC84WAdf/T+UKCjPUNMQUjynZGTcohtek2OGeta y9Y+4yht2hIKPUY1b+dodDi0QeZDTJIlpeXHJzdwz4am95j1BdLO7gcJuwNeXmtBfdW23DivAd5y wsos7S+AtdE4jced8c+bYuXNoTLiCqbI04cFRXtSqUCIMsX09cQaFbmtP2SrTIfUFBZ8J4X/+L/7 0pdsduVomf3tErKNFzU9freltjXdvM3+s55zz+2fbhvCK0oU2bLWoztyT+Ey/0ZWlytFYhBvR0ds sso7aSJfrLk7lVldcZxktu3ENS0s+yJ0zDfQ0WnePbYZsdaMxXUTmdrAQ/3P19dWtJIvhGvXtENG Zp0ds2CxjocQOnMQOC7e4Z6nuZnCE83Ak1xbHjBqdJDWCX7n/3YbecNPvbhhDL3OVsgnM82BDSRF +prVnutOkTgkkz6tk92aawsXw1dgj8ofbbnzjqHpBm29u7++1rAURZ3NbC0DOQ9JK3Q3sw31Kw1r TmmGD4RpVGXvlpuDlz6H3O8d9/SMoqTeom5cIa1vr2d0Xm7Yz29vqS5NwIdgtokl6BELa1J3mwch IL9wlvwiswKYzZLLtOnvMUxDt9lj6j6zqcHYRdx0rYwptxeUd3VLGG9PmV/yE0aIFPz3sN+UHGQF f1CfoTZC547n2FU4cGnS8V8f72iXUnsYOX52K0i+/VThRBedQ7XXKDld+eeubcRuuVYcP8ZDn/io PCQrv8QP6I9e28zCEBsS6T8LTpr33TeRV+oRk3zZS4JBIRu+HBjjTLZqJ29v+hGfrHqkwdla9NVh OuW5QNlZ/iuQtly1AIJtI7Tgys2UHtATUEoGk8fxuqGdQkBWZFSZOcTPHeb3LyCW9iY9c4jgHTJU mgxDqCC6ndjt5TbSUkx85qM3iog2YAxNvBNxUF+8hdESYraivxgeaFSnpA3xlQsXHcbEQ0DwVl8e NCfxlS8bxGjnb1JpQO5iJaFOF9Pwssu5H37EecJ7l3BgMzVcJfRnPYUjglHrsOG/SmfyRcWmSSX+ zp5nEmc59VoOYtLwKxVQRvT7LUPojjtLwtvXDKmRJ640z9HuXeci0sPPfqqun/E9rXE6PR9JJH2e 9ygUK7KigN4zFRtX3YFfsQSGFnvBYlX+5YDpwftqNZ6sHwOFW0/+xfjuB4ZwxlHtSJFgWx1C5C/0 1r3K9Blow1rnHOgk1UvawWl5TUcS65MtWOCznoR+Axpw8kkBo07xuSdC7uNm1pcxJvFnIIUUPysI of6Tk6bU7fOYxPE1fjnySreD6BQ5NA/0DqlvdEV14KqOXnFSvmz1NqDH1G55CGW/awkfhF1EzfdZ efGdSyHzgXEO1TMk+1ojQtgOQ/rVm70niLgDE14LaxYNFI8geamtrDMsGt2p1AkpeLlaq0wEO+Er czbrLJNQRwrV2xZoPEyodsXAHUK2QmCk4IVna1XzMdizweXmOm0b5Pa64MDNwjlvZoj+cB4LN/td 6NNmJ0arlLuNjS5nXg2L8YXT5JiAy12oxOoD9h564WV/pWpOj0jOzHcjOTdWO2pHDHKRH721y+rw +5CTLvmL527XqiOqm1oo1ghKD6vMdXEjgChKXx4zvsOtnqIIbx8aI3CE/UzxVQsHP4KE0S3RAt70 97IHdLyOLZDdR04XhWgwkWzck4Es8aDNa2WGzwS5ErXGnbLOuSOaUFUGuZk2MuE0bdclMtIFLfPx bQIh3mvKYz7U0uavCPBeIx5tl7lgevZHNVFS3qqsTjJIUeyZk5DXmH8r4vYTi+8I9V4SQxOK8xZL YLRNoh5EMl5cQe+J2XjgGb27c19R9tmsupkQOYFssztBDrL528dC4Y9cneXXXY/59Atl8yKmSPkc 5t1MatkiEXmH313losKcAEJ//WWdmYzs2DYeZFq6HrFvov8rctR5OcosNIuJXAQ4/LCuNwpWITRl K7HbtYc4rD63DZ2Kr+Da1tdw5Ed0QJsWEyvhd6xAvcdqCseNFLMLsdTPEpzlYv8olSPsN7R7sTgb dAz611FElhQ3wqpT4cOR5v/76uKEx8q95E/7PZusqR/uz9wXy9dGMM3+VDYQiohMN5ueuev7QpW8 a3vGNdC1MybOCOpWeKjymKLgSgD95FpWX2CGKITrZzt1kVHU68RzggDal7Oo+OwqDLVFunDo57lG pYZkDC//LN+uXsiYqH+pTPVgMp8qEdxkX+60jNHugeynnv6LcSBFo8jOQFfzkUIklCoCIFnukRdQ lW3I1PlnnjDhS/8fvtcpCQe7TuARYkSSdbwWn1eQNEbhGrS1C/yhRlg7r6URyrb0bUToHfiawkmZ C4U9r419WmCAR2fsUiof/83c94BXwxrUrW7W+DGPZzWBlHk+Dd2gXZB9thNDy1q98Xqdc5A62c59 V2mxg+snPDDdxfMe7Up90Vow8TvSHSRpbiZG/Ctlgl2XViekB1ifb0XJXb2eACPkZiZUnzVISVaM YaHEYK2F5BSTth8r+omHeL4EKCz7KduoWHhtF8SoSl+DveSiHswBBKt+YTQDsvZ/2Yfac0GoVyda 68ni8xuDBOPUd3pULGMTsqv+l6Gic4zVtHKycoYlmwLHRO/YMfm3hFoazlgvsTwMSVs1nuN3q3fp duWkNzblpVUWKpO56QEuric4Idk+1301ysE93BnmAPnmVNxFkLx7i861+K97lI3JzoTKD3p43IZb JifEzZz6A74R+OzSGxEbMD5KKqJfyeWcmbDKO5uj1H18wEL4BxHbZ1ifrROFOifDYLNcfaGEgUdu GBqjjFGyEsfOAp5QY6IJl6WJVncX0IOxP+qA/lumWVZHcDMnuwcNVS2AVtKCQt194xZ6Gzg7ZQQc vYvm0Auc2g1iVXrySSrwUKOdWsIkX3mIxWzXSL7y75yJkeGNROEeBqsRFeP7sZ8OTk8A5/ahGCB9 00lHIztRqnPD6/zbIGQmEdqq+4c9XBOnotFEYIH/5Nu50zJARN+J9aXuzJqzbHKnQNQgFVN6/VaA sFqrV+ClG2micMYN2/v9nlaNuW1DE349TwbT+NwEo13A6wOI6vsz1ujFtySM8ZVfO0WOXA3c4YgZ Tb8Woc0Sn2OpkYqWEVUAlHZglY+YdFwXffVCubBaDcDriXhVwnMXnLut66W9XrhufBlgW266WOa6 K8KVrHPImHMbIu4G+ohhCEIwb/0qhP7+luwJZ590PMnfB+SzGGS0ECfuuUqV+6lbj8rFe1NGg5nT znNsLmpGsgNHgoB9E1d4BSLWlxIri3EwzjwOEPNvY1hTea6VVAhKbz/TgWqtWywlylZ6mZvd9sdQ o1Hg7ftAKTw7n7otnV3M3aVkb63pHKckstlhHuYxXZMWEfKx1wIaHdA0YTZNR13SPiUA4AIDHMEe yiSKE+FdP/pOAAVGGsFUIRnoIUUqM8XRBLp7OrbvBjQ+zqpvQuDyUIq4eqeTcLIHDc64gLjhryKv SYPada80HH6/tNclkBiHJA5hpzewUjXLmW7WCzIVFd6CQsZWWPrkeh1s69L/BHdaDEbs1OQSu4eH zO68elSLPGFnW0k67FjGa4Cny7Vki4x8lH4dbxA5+mjLzMU5Q/rt0MoSBDCr2dFAI4+PeeOXmYMr 37Kkcum8VQpMXGkZqRkcU5M+Kbt+UJ2AEUY9QnSx+m1aiT7DAr83EmQ0tjm9QklkprgDq0wlV5u0 AV2FngrsryG4+qrDZ3gkqx/BTv3mPQI5BUqT5hq7DXHnA0cBOncAlKHKNnTuxCS7oUrOcue/2VAD U6SodpByUQX0562WGnGP9rEU5hj4Z1mJEyegf9GyTCsymmHqEkP+mmAufFlYD4gc9/AmuXeU1mTF i9sNnBxke9eVI+IPSDnux8Dh7oE7dafujPLGcphC9WTylioAtgTfwkxiuku9k1wYzNBG70VE+CxL dphYpajqrJNO8FTaT4MlWsYw3Nx9R4CTQmLNMvUiDSmxZpxJ5+d/u3H5BLq1VRUGqtWHru9hUC/n 6I4vYFAfAtWo9EHYphlk36M1b3ebJdEkunYsZyxTzCRCznjr/cDLIRmp3E/dYsCCOtAr5ZI6a+Ss plUKLAaERWlIsyceT2CRMu0jC+5Fys5uwb7AuZ9jGThArjVNFer37mllJ4PqGX+wBttIN4Nj2SRf XCdEyq/8VQr7gbyYR3z0WvdVmr4SnTlCZpwDIC4Bo5WFDf5gWF5UJvr0B7XKIZ5cSPLKxdLknQUv hfQFIpHvtDuglXQv3aJ+uGhvymi9jws6XGw1B8KlhPfxv2oPn7oAFoOURLm+kU84USx27MC3nB5v CRyJQxIlRb7Se1h2sF+Jo7EqXFDPtkwnayKALBgKoEIC92R4V7kFIi337n36UQasa5gXm2k7ydnW axAea5qpX6x9uwmTauY2UGwxmCyGI3byvYn+hGBqle843sYbycI8O7qocAoD4dTxU5jmFXT+wPJZ V6dM+c19A4naXUFP7pCzgDtNpEUK2mUzASQhPFdN8OZPF7zpQyAUhUaFuT6/zJ6E901spHH9wQkS rw/8azCgxXO3XI+pdSeyzyy1MMnqRZsRkoTALmnZGmNZkOfrWsVyLJgWau8sfKCycG0C/1eQLuZl RM7LxEnd7D+jQJOQCla0cFrkMiD8K1VTKGMlCS8SYk9yeKsEmilpb4dG5dlPVotHAJKbnMT2Njsw gfg7HLuVwiSnX0uQYwVJkp2uF8pJih7qELSIwLpGiS2uf2gYp/2y8oqoVImMunh8S6DmkUNug9+V I4Zj7p2Mi09GhOgdCzloPtuw3uZK6pOMKGg0boZAScWOTe0u/UyCSIN3Sb5GiD7R6dL427gWuysK bD75ox8YwgkUgr6M8/a+70YnjmEFa2fCVoJwnmiRI23tWKMsCVL71RXzX5U8HmVPlOx3nsAb0NIs iVaCyIEia9fd0YnTmFXqfaIM3Gkklsu9bkvJIjlwCc4lEbDNp7hthkI6DZl04ROp2o0uJC1E1UeV 4BE4LbhMdwO2a0plCS6QGykUN8/ioyGpMaBuVL3zc1m791SMSxKVJHvJQ+kVzyDkBLxeBgH6kd3O 2UKd/hHgQQxlsMAS4ytd8mXqQKDn97qwi7WG2HWQRXIe/n9IiZLrMGjcg9VRcTNWdEjwzvDkWdVN ReIP9WMQEpUCFmo8avvT4cvg1fY1QCX4l4S/J3HnK9J9aw45moaY8fCkik+1waM+mH0WLIjV3gId oSedVkoKCoVRXhl068/nh+OFPB0aTAjJfh691I0CwG1vTNOH5S0S6c2ABBgjFsBa5mlQA9fxQaLr inayMU2i1BEr2Lf44A3ex3H8Klhf7MOpBKo038MfEuJlYhPU/S1Xwb0EYfmq+suvXZEuJBQ3cG84 DwVUNAUBoMddhffNtlZtzN4tII+ES0bkdHhMv+GmF6eBFhyyhC1o4stUHb1C33XVQ/c9sCePxhsC e7JfchPsVxPk63qGko+jU/mPSAl3aI6oa1zj8+zTRC3oRVuBzylTXl8z1+cenOjIJOf5oYnfDdrh 00U8skSXRA7ZbFFFQZIBGtAO4BSQjLtVLinQ9F9o2w1wHfOSnoE7NyY3dKNlEOgh+0dRZLuGZXnR S3K7Qv+eywp8VNWnie0iXhOtIFExYYEvBQue5EmNEu0JQACogg8weglHtOkyPU3yMLcWy0QKhxbP XEfu8fV256OHRdwpgQGmTug46X7yGgzWfEGON0dz1oz4yBoRskGrJ4Ez5C9CgLULi4beqVY9xOJn y2RpuhhuIOiQE2Ks3DkSBrETQfHOJt/7QOes3CBnCAQMO2b0hbheN71ZvUEmPw8ySw8/IEyarzXy n4YCf70RAnH2d7yu2GJYzC4LqLZRquDKJc4pp5wjGX2tdD1K0dg2QM75+8jA3VXS/n46gkeSOYR9 MIIjPN23sueNaXspIvRQoYprDbHeVRHLotECC5LdIdnpQz8HqY7aaZQIhLtAbNL3b4q6O/RVJc4G DATItpTdnn/epiX03s+bYCjqJtwzSEoIGvRU2k3j3Z9Ix6qH4Yz6LdSPstAd2QilIAx7ZDtUwNlO 8c0w5GU1u/trUDGbhha5sr07TDwpP3VpKJ6GTULgz5DHTosbTCTAQ3Kz3B6KQBYtIQaeFPBS77GV BSmN1poacGkbpOqTHAUFJDLhsaQQbueVy042KP+RzuVX//memFYRMaaXePSTDlxaMa7wgoOzVeAA V1ERQtLgKAuwZ20nrjFrG8Y5Zzn31UYkO4EPJ8KwhhKa2SwmlhNB5xwJ5alymJxZrPqQT8Q3m9X+ ckH2pUm9ZXjnj0i858tAdEJCRAiOdT+/h9/w9tQFp55s2sjrlDeBX9likjMcZeI413dQlbLBB44G k3S2U0BmfCxRHzzJLEk4IiBSV87HeKXF2Z7SKshtNV8xydnMcMFcCrteo1HoIjA7WyQKdZd16tDN Otyu3pk1+RvoSdoPFjySVmq2+EzPjU0VHLhjh5+05iNP2YfA+158/gb3Eqpc0SDFbHyIaEDSKfV9 E3fstequwZric1G0nGcZycaMe0rsGWZxBoGHbMx0s95bKkdPePwjm6wjkmh7ohWLhJd2MOrAnVOZ 6RfuALW+sDUbmSFd3YnNkiW0Lna94CxdlBp1Nj72q89zKhRm5jc5hdNsSjI1WCFkeXm2N49NKBw1 sgCSR/QB/ztoVlp8D+N873a/VD2xt46uW+Kik2F3kGVq55xHQALqChspSvd9BNCqu6YsZLWOkRZc F845HRLhRdaFP3jrxn7YI8HX2k1tkJryB32/qM5xKfdMBHH4Ux+QV5JC8NY8k7hpbqKVwXUBriLJ QmzYt6s6zZFuJWl7f43onpIbamM12U6v7TrZ7xnep3VNSXWADCbTqHIeZuEQV9gJ1knFdhNFzgby J9/CU4XkMf25GRuLonOzi25lsr1fEapUeaPBlvQpzFmNyRP6NTjh1uJFSrCXqlP2M9jmSUVyKQUT TwEDfBIA+GrkmyUWRrHjnO/hGJkpLmps80VuGyXWIR41w3XWVwqcgTD6pBgxIZ6J3YsvshhV8Q7l HrdHHB00ZCZ2jsYK9uQ95VLohiuaarqKe4aVAX/RTXzLXl/T03e94n7ES7flQY96NMia/GoV92tT J41l5SsP+KniBWH5zdIiWcCZi7/DZqLP2EUY8E0vCSkIu51f2ZPNwArkq1kfodoskLdLk2D8aFaY JRc5RKbK3mTySrZkyvuapxJz6YiV8iWhbwdIVnKGcTcNNxSETuQr0BhfSaj7T6nRrl4ogAZbmS2Z N2VF1efkN+tHoOiFSYg0xRqAl7SmiH9KoD92nH6B+T9j0lcJRgqr7j/gU40+r8NCYtBsWKkv2IfU N2RUAeLPhMxXgw+iI4n14Ah/5dXvfW/qFC1KR7R8CcZeyLWZFlKqpgMf4JlSX9EGvPYq8Z5MVzlJ vZEbnT7eoaxyp3DWurOzKEpTDiZ+rAtm+Lex60ZwYfH9YzsDvuBs/ywYe47uaXEBS8Ce4PkUtG/G eWf2WWY70Bx1huYAVfM9aS3sGpYBENMaBT7nCC3xQBC5IDDU75Qgx2XSNoY29z5eWxxJkJWU4B0T pXFVChC/PB3n1ovAYf7rWOWUCyvobtr7SCq62aqdBdBTaTTeylEaoSSz7N3ND8OXeRWTh7R5VTBN y4psDsW/wFa/Om/VRwZvdF5w79zQKGVNbIPmyyzIaUPb3mT9Hc5Sbo1diyrwNH7t9P2Yd2MXJJrJ +p7nqkqlMGtdu14DrQMa2vD8B1o3b3NJ6zhTIpINyyqGJfwUUU9hz5+Hq+ZhmuZz5uYbT1U4yJ7y G/lwwFScWtDjLwlz72ATv+fLOXkle0UmmwPgks2Bwvsj+VxxqF7CCHcEsoHrwNsNYmJLcGR3SX4v EqLwtYMfyQZvfyWF0cGWttJDrQEKLGiC5nZHgZJpiDSPxCaJc7mspx0FdyzmEWvboQEeOQuYejDF H2Wy7cOEWffQQObHLvCoVusb1lCEb5fYxuzUEojj6y5/MYB8W2BdKtF8+SxKGcksPh8j5oRzi2jW 974Hw1vXn4CkAZa908p7d/16Uek2AysKptf83kO4hbId3QnnU5JwKQJdLYkD1eSKelSH1Lnx4gdc BRFOmENALpDZITmXJsNCl1ohTAGJdfqaUZbKOZdCXhIh/pPII0PJklmLs9J6v6D28ivHxBcOeDDK 38+Hvhg7Y3HhuLS/bwjZgyc+xhENZICBFHHaSp08NYKFfkurUu9uBmI8hmzN0uiu7CA4P52Buntm HnNl2y5VqsqeDry2bMFgiZAeQVlaagur1TskFCnMrzh0c11YqLYP7kC8dyW1JYCJB69cIK3R1gO6 xoXEjgkI8mFNkC81Ajnn7GuMdWxqI6yPNo972UdsuSRplm2ddG8F7Vmsf9t9my3n4IIM/EP2wrB1 x+xwsdwY0JOrVaLOkkhnYXPIoN6PuhFGd9SQqGYsvHvoO6WDXxG0YN3z0Zws42cqncZZ0uERAQGV I4Ea2YZLMBLvWoyzUmOJPX+gge3mcG+pFOnM2M2wJ666z4dB+lOHryCQijTiYpxhbiYm6LrYiVXq 348OWoN2i94k7Ibw6CUJHW51p9oUgsgaC2d1O+NNGzA2711HbTcM36B1UARVIPTNb5GZ+SflqoWV t4W43q8uxFzW6Hjy0MC6RtFSZH75LOhC1GmMaTIaGZn+ZniAK8E4Dbb9mWp8nhPWeiijFdKzvCFe YOkt3zaQ79Pjer1qXnX1untBDto/Vaj+EinukEGKy0Ein9KvWotVJwAlxyGrn+bHGi+F/e6sJaVt MSJvRg4JAfjS/hX2/E5cxlNzBl/8kwz7Puy8RBRYkXmYwCwj2a886VjAXuvumbg8O2jCXTkvTter E/vr3yO1YNMxvOJlJZTlgVbOz7CzyjzmHFlSi8OjnqAl1bbZvjPAVMWY6oOlS1nseDKN2lxxoF2K kFuISRr69tQKVObXcGboziHr0WfB96sFiVjlt7Vc8fWy2LJFBmbdauQ2rPp1PDq5alS+XWMEpLUv /i6guuYRXrmuXsJZ9uVqr9v60S7lJoUQ+v4QbmFPNJhGhkrpP55gSIBhsW5I2jJvXQHTqpi4VJ2O O7oJsxW2XIZylzIsJDkOEDRvPBUbBR+/VGbBvRUosqM+svgRgrUZWP2vVhIoKiiiGwTwFnYIdSD+ 9V5E/HKYffIMqTRXCtttQ1bpTM55I7Cmcs0Nl1TcVj6EZ8C+ONnN/h17JBLKlSeHuO6Kf7V1kMqo yISZCx0d3sZ2hZHfUmnlG5xDqTHXcqigyUY3l8h4S9QnD9RxSe2xWN8snDDBAoMUdRE9uRUGHWRX EKiKyg78mJPRfzslH6jIJMAHO1e6pieUC5T0gKW94gEye97yKig48kySp1U6KTcBMcN2XPfJJYaO jfvnZ8JGSoIgRCxAba1Mwh2fcldCcHm/h0YxviTpFz9WQ56J86abtgPV5MG7dWK0CI1TfViGrhHU 0nCa+22EBQ0e0FeDxX2dj2An2gNxMSjp9Unk1oyaeokN2O+7gNRfCeAF+iw+HEJj1zHF7DBS6X5D ncVexuYS5DyI4Q5XkfKBHP3kpsJySuNkCbjJG6bQ+KHhqs10k/kXh1/XPDV31q5r1bfM4b7qIINW DnuSStwo4Jz91fdr9wtNI2lwwYWjyC/NT7XT3sQvaQVCdoPK0SnKXV20OAvksMjcpJNHGlazEIER PF8kFeVgsjaBvx/+MrY/iU8JHxZrkRSmDwvH+HLU+QFrYjZCxyYLaXsEDUQRnAvrSYfM7KmGLpOQ tccP71xIN/o/ApctpCOq/zzMFp3UWkei3/9XAw86SMv6eoDTuD272Sl+7z/Eb18sW466EyjYcx7S lX/yNxaLk1D5Jzasbnvk/T0qcfd0mVvWW+vugjpRlbyHqQ4PVsWX66LsUeWtLJD0vbYc42m0GW5h EBDaLHqh03AL289g+SbPDlgwkI8ZiHjbh2u0FDxpaLr0ZoEUBG+bdMo5He6ETikudp84L2RnYGmE V9CZtw8w7G88mvkSpheoE2zL/WY4RyJE7Gzua81yZ4zMYslpp53gahEvGFpbu7JU8mk0vuLc5FZo xT6JvFboUb/WBa/qtsIzN9hec55JSfhneqgRs0ZMdC4g1rfGVsMUknZBo7uZBPXDvOrf0t2hieVT pEWcq0CIxdvwkAQsQQrHc6FhR+g5hHjFRDjgHZa4jphjygA+cWwRTGaXWOLQgozQ79IhXpzXb12G NCyusGdNlyjhE3MZZhkxPf59FsPEIdZsCNsLF7oPaIf1pGmy+GNBs/j44mM1p5FoZonejr26bP/h Idj/PfgnR6Vkz+iPGLU076l33cGBLa5z3O2XByQyrfB9bbzk+IDR5O/+kMftgaes6bq0ANObzTTx A1n5DocFgng0pvKe1OnTK96dhAa5WN+Gso5Hn9AWbjJrYeBewHrzhKTnvocHt3A5DGCNvvjNSGK7 se3dmfvPz2ajoCTZoW9Ez/s6QclHJGVKkMp6rWPClKGRmhetSP10IQ5vrOVmN6pajuokS69UeGn/ kcEVbPNANexHCXpaeXliM+iCd8xzRlzbeQQKFpcDXf/+Nr423kMDDxWwjdfxF6qAolj5wys/z3zG KGjpjTqhx2V+6i+TIXS5STbh/sAA1v1dA2avjFcZIpBmtlcVNcBM55ie7WDr5e//oW23k2V8zokp KpFOCkfhHD54iM34eKUbk/BryM+zQZS2+3CYLlfsQACPEZUBPhXQIxsTq6OqQKwPO6ij0zsInV2e nK0PLVrWwL5mzTZ1GjE0n2jAUxqp6l/hZ0N3iqHzcPO3Zy+mKOC4ypOkJtr4dnf5S6Or+Tng0us3 4IRmgnuf9Otugb1ug/+XFna4MFQHEbuV4nm7EN0N30oBXfTZSzEuBDPcuFT4vsDWGt1ED7j5FcO0 x/TzSiqHN8eNWXyg4qmmJ+yqD5bJ/zSW/n/vhGh4iOUDcWknvITYXqGwIYuWZGUPAsF8f9oO9z2j C/wkNpQDhTiIpNVl6nbppxaxs8v1mWRxABXDP6ZAu76SOXBnxoRJ/8sobJH8Iq+q6iOWvwxpqhV5 SmeTZ+/RAr3VNJr2YrjJ3QzDDpPvHK+mxkJafIS8dCe60UjOo+aC+0ufidk9pORqCYf0lj3n9M9B +RcggGFtRNAoyJ4ExuXCxzRcmC8+pqvmcK7/tLJjjX2wxa4epo852Wt05B2h6wvqpJhV3L1gPwT7 sG2IdbbPGuek5FLOuJp5XfSWh32ktsth7V/nEsNhDE6RuzajJs7HcLPZ3CsUVVzAldYm5mQan14J WEWlDYzWziJiKc+LoFpEjqD7Ok0E82lf2JrnLFPTlO6zg9xK0fqu/uMrRBGHSipDfNfmp2GjMVTk zt4B7WLeNH7fgYmSoC+FfyBcY6Pv+kLZDut7h6TBThWhmPLPqnu95n2p8wgSxLfa7AEq5HBy5Hbt /PrIL0lQUj7LHeUUGRfKXmscLkpEbbiVHQrzuRQuFvLU1Dy7TAYmWjeJUj0JzIYBIJtJta1gmkHe z6JSTtJgYIcmMZmyoPhHvO9hrX5q9I/Cx+tKAPAHtzLvUoLJ97WyqolziN5qxasJFnZ1iiHvJ5fd 0PpfC7yqVnbOea5Oi3Z0bni4AqnK4snLA6IXBER5AZvvhscEj/CO/ue8GnzWuNcAktQr3qWrL2Iu XesaFjrWsQAmP74q/rvLSt3lKYyyrEBksgBZlOcO1eijpZRXNdq8dsTGGSKQGw2SBkTCvleJEIvG NiIBkgymdKmNoDl4fthV44N7574X8/YmzrfPc2mWX1ekpX1mwVX220xOHJ3Cw1+oNKnr156Il3yj FP5JuCcFfUpghErM8p9XclUltMPegBKNzABMIlC0tsgc+u9JShjtCVHDJ4cpgjQd0tcZT/8FxNZJ sSVWohprfnFCJUAuKYOKGOelnjwi8Z2GAhsoDMvY+PrQZGhvpmNIL+Ng/in6h2LhR9TIh64QfqRb nCuj4VY8HLn37H0QcDKoKyAc7tZnJfryyaQ86Ix1CP2lFbaIdniALbjBjC03dpCaksplxjbs9oDG d4Lmty5ktZYRff0o37QLtWFZ2sWiUioTm86nOXcLdfGUgNFyM7yCabPRgYD08VTHnqPFDA4pRdlD 05egmphYE/+g21gEvFDvHSpGoWu3LDG9W3EGh7dkRNVBQiZZVaUk9r1A+Rq+VNn7W92i0MkU5PSa VYs+Hvs1GA/cJxgY1q4WIu2H7Mv/Hbz2Vwded8Oen3mAOQz0QPiNKPM8J1+dgxyvoZ9bdk1Hyw2a EXkg3AGjamjHst+IEu6VXRgIHN4I9HmMOo686K8RiUPhWg0k4NQPLAnhJQ62wqhGsU5YE3RSRcVP anK4P/jXZ+3Ov+fim9RE8jwSsWbMro5p+1ZIn6bQZvJ8YBn3/3A1gwfVQp4vXCEJIWeJdbBTVnJI swT7kBqmO2ek+PfKgNRqTT5++6N9DZS8Qit+rikwA69DEVHPIBv7ZeafffDbOgfJ7UWyjsVKu1vC zkOvmFywJjhgJuHujCNOLNHPLiyPrj6Mfhp6U4C0bqEWGdI89yjoKDB4lrE5FqG7eGXLyAZEH8ZY 2HpTcYjvdu6S38s8gEDJfiJ2eWUd3XNLDwUdbEEqF/ejUebU+b02YM6gIq1chbn9W1Nra1+ppT9f DxAx0FVHgrp049u7MfsdVot/QvoPDtX2fufC0bWsBHBiQ0P3marfKCfrsMhyBfwruPqLAAUnae71 p75JsB4uTq8mTizjGJxLEYnG7ljekdAfIwWdV4mc26aKwhKFkfibWzy7PFk627r6Xe6vQ2J7zbbQ RkLtMax9QAAf+HODNiOS27nw4A+ewelNGsBY97psaFxlZZneHdNZdyojc+0H/H1FApayu2G4HzEt x6ZSwovGfXqEARKTFmCv68tCQz9O3VnsHikxxBOqxvJ2Io9J6FVewRImkV6LEMTLJIm09ZmRVTBW 03rXSHuq8qDp9m9LlG7cBKeb3/YmIkg5xaTbh3qUG74G+zGsPj3FBIbb1J3SQhgQ4gHMruOsMrFl 7a7BdBHoA4jEwh/ZQ75GM9oPB7EkLUzFOlKwqLK02LQgbS8mJa6M5TwX/8j8qhwZacJPmq5uRFu9 uhazBkQKvMfWJ6Fjm/F64Yu831Rl5HiMUOqlbDVabHOBnJs4ttQF+i0T74TW3ESg95BZOwyL2trp fqN3iS1anCw5umOjqgRaAMSm02PX1yIIL0y/C9pBs8FbR3DbZGgsW1Z8K5p3qqaJrz4tBiHAps2t y0ydle0ecl1VXrCZJPTEXV/xpAisvoKaqjZ18juBBQOP33VetyjZexttms+d7YGiJDwaB077b4Sw Yndh42NUt6nuIG1Cq2fMYM3yXlY6aE0J/mp/EFN1BAytEC+4+YNjqmHUrCa8FxqPXlhaXtRJ8WRD sX2EUfRDVbP1LvEdO3PCAM5N07qNSGzarXGFgNQPjtV9f+BGfxTwCFfrFLgGyL+j764y1onYHJoN y4fssscGPCs06Tu6BHHf7ZipG+Mk27GowNc3E8g+r9wHiQv3/QD/BoZ84xsPUL85M4GD31x7W14O q70DP43OuGGUaZx7Zc6/MPd0DKOFQfZrazBmoa8QjemXhFjwKZiSfRPfA5I9qdSG3TCjjOKVTwuO sLiwLtwPljWVbPuNx2o7LZBjF0Mm+q8yFBGS6drZPORTWrOj/Y9Vp1e54rRY3QlVhqEMLPW5HSGP 6yasrH6AnIip0XhxVZ/AaEG0csuIBs3Q2lsOTzbd+SFplHmSLruaUrziFGH+HQZh4y+odPu6xBuc bNvRnz4v4p8StcVDdNIa6eraWD1/G3Fs/P0XSnK/jN/Pa726XLAD9kYmPAeloRTS6bf0UzQBDNz/ ngLJPw2mg7nrjbelcenxKvYh5pF7nD4Tex7Y/drGC/J6RjpFhHat7/R+B72X1Rj1caTcvOYsyqi5 TbHaMlDm7BE4lGN1isfFAArYYXhmTZH7Lq2pXqz7e0nPBy2fpDRC8rzfPT/4ar6Tjw3fv+h8+UJX L6ClmMN/e1tDIp6EovgHhz+mlX4jGwpCaaUgY0uREV2om5lzyGw3fs+z0rKbSjdsBdpCpn4qXwKW QWIkQ4bRfSAmkQJhcjLBtpFjDhyX43iU+iL8i8bQ2RAsW8GFQywwHMJrJPL2Fq86VVWVbQCIZN0J a3wiBlKfZXmY7REdQ7dP1HNy2R460tPlGX45ONdDRv7JEGtVZOJi/mgOUj4BYkwW+aSO2/d/Ef4y gLWcd/p2eJAe7/o+IHT/k8AlLP2XUwqJp6mbhkShMTFhgESegeBNYrusoaFshF7YiFes7OdwZIPt RpcN20iUmyDAmdcZYrMxZ3wK8VUkzvldhwefefo+NBPdXeTPlqmkCrFB3bSXJcg63KbgLpHASwzU PgZ9K0Lvjtcrgdt0c4ghcKPcM6Uzgh++Ern7HQQnQrYxTGrI/RID4/DDlUCf2xeUutt/Wcr+Ofdl 5xEfEqvKgHqARYqISiForGU1iZuZlvXTMO7qAUkgwDooR5kmmJ6cGutYWE5+eDyjdt1Kne+O+u5L NRZlrG3j3yzZl41v6KCkKGy/VsxjH9ksjrVLKDNcH957fVr4WGSnGBr9zXnhWHLxMDSgOEqKSRv5 ORLXo//QNlAJEO2ehFWbw2nANtq7G0wwRlpx83QuM6khPqeODbR37LwQf8NEfkw5rWAlBxHOpb9F FS/RkmT+opEymT1TRY4suDwPBlR173Wrtr0lh7VivyZb1a0ioX+weVHekwmq0GrbDPMKZ5Kn1Ajf dIPv15Bi7gNQ/T9XZ1d8JbydQnd6G6E5O2PDaP1MvITT3OCAMYKGLZnvsmZIkC3Jj434N/R5mCTN 8QfzdYLgn4x1LO2jQ8BU8IHlq77ymhidbMTteOn2tEMW058irL6SshbvlrpJBPlRfaaRen0GNJcO iW9C0w1pWO5cgIa6EbnqKojhga+fGTDNiwjM8SUDO46Tq1uu4aY2uqPfx3oJd7nNW7zTh4nLL/vK yJRAFUnP7c3Js+FXq3X7ROQlvQZ8MFWv5j6pc242VUF1JY1sZbtI1l1vwL2P2VH4vyZxrSU9wVhd mzak4Wh3GPaWMlM8qTznuu+bgpDXGWbHSb7tesNS2NvHB4Pd0WuNBAbFsF7M4IXVx4mixoJ0yddY Kf7hDB1vimJZ5Vty5UNXQOeKlr9xw3G45FNMcWkhjAuU1T9Ivx+qZ5bRhJPb08hlsUtJFjFiGnUc /PmtKagjW9K71aA0UcGhMwW9JnrqU3KNQS1rtQY5ojskcY9ofuuEueW7WoAV3OxF3GfOdbLLLSWf mJJJd0YILDarnzC1prn3cqE51SXn785xWTN9dN4JQuYpnQwO/jC2DGXfscmmb95yIUJda/gwAhFe 25wZkVPHJeA4NggH0eOeAvvcxKDg6kAFdEKlkVfy+KJvL2jXe8w7D2aaVMISc3PH6EAdwleLQ5qa pfK+gVg2eLUBZMpcqGCJ5w0fz+KTFHkfPhY+CDzaUGrDStc0W/R0uTRc5bJ8uoBNQ9oaWle2/aeu Y2G6gAv+TBth0+jNk3ht4E2qgjnHb5JLxMMKUCmITobVGDrRh5FLqpmAYIINpF2dkJnJ0W5/q1S4 UE1+WBDUT7VWxpxROIDPP/WKNC1PdEArjLoY3hJrYL6gavxMl9akyy3b77p0ff5LDD0L31yBzj5B gtLkZjp8A8iVEVjSmZiUg3piL6+C3TPj93kqr2zRCkvWbvjB760EY3lm+fYz3r/pZ4JpeupgbAvM fqcbxEFMhetVSYoOdapuB8LVljJwrE4Y4Ie5WzfGDOSdZm8PHFUXEu03WeZej2YfTDxZVHOoRcM4 H5gj3XOMci5fDopu7ljVWNWGfYsUwp3V5MRRyG1r1Ajwlbzt0vtgE2tK2n4Ae3O1rBY7R2YeDS21 T0OcK+oSr7dLAEyLLPz4gGt+M+uchD1pXGYjwfUahZtO39pJg9W4x7vfAfetCVtmn/e9ZKQAxxML 8e6j+hvJ3N/TibnGMzQ747gAzhR6y1CWlhZX3BahTiQ8WPxuw7ax4+pzVt7773MSXPHvCpZJXAl7 2PBt9sJ93AKdDkGLSMDwKniovN7DxFBnHJDrUrQUPmagvCr4Vxl0z0q5fOyTh0hFJ7UgfFYzpHHz NGzOU5FiOq+zlKVm/bv8XHFdrUiU0haEVCneM5csvpIcElk42t5dfDYhn3BL1QCAgQQoV8R+mfQ9 Anoiq9erKH2JxJpvtU3qcjl+Pd2kUxlJXY/iJ8C7gFcnmPdfWx6bFxyc/odxXbKqao0mjokDRGQr om86WQhN5+NwczBEi5c7pxry2mdXZyZmjY3DNXfh5F26Ub7Jvz0uJ4gq/xU+bfAEj3cUUS3tJr2o 6uEGG5tzQ2E9vvjnm4JfLX7f1mQINAfPnlGIMzTZzzkyKargDbrcCQqa3jfJCdfyZr0RlQvxG+0X S8N0F6su/vuorcC130tFg5GFpjlyV6RDM3Daw5W1iprx8NMOcSa0CmqdfJTm6vGTvG7ed2uJqTS2 2Em0YcAZsySAKMKDUrFpf+VeuiInc+7MvFRM7FjO40aA2sLjZS1c31lg3Sa8GW+90VqCuxusx2RX dk0XJGs4NJUt0dXSOObHrHi/X26kXnf+xV97kBnQlQQsng0c5PeDuKQ7bdquawqksaLp4U3yqE4A 0UANH0efHe9wsp1tF400tmZ8lcWFkxsYuhz/REHB+ZxKzMaAjX9aGGse2tiQ58k4wtHif6i5bAWL Zf4HdUEBAChkxT9RJgjxMMwVQhOJKUQpEl5LWYkFUsmajzGjJTC6ZvjU7VuiSNS/0k+p4C1JziCG WtF30plAryi8nGp2z7bRurNgzV/6bly9euNMgLGPlxOQJbB/LmWoDHsACTx9JTLl79l6bgWmPhuT VWbQItk5HUgGnYUafUWCUc+2Y2YqFTcfIHiF+8sHIXE0adKSv6eaUGn0JUQwuDoadRhg37nKCgbM cKtDAL5jiRAesdUxQFLMKVSsomdHhIRiTfF+lL+yXeNoETiczMwniTjDrO/FfmfuCQ75DMhEz4Ua IMBZY5YiGtuFQRaC6UCUjVDIYHzBEPM7+zQ1DXRLMrd36at9j8TLBLbH6NkI4Rgbtptmj3BwkI6M OnWO5xi4HXbowmiZidJhxH9MiqSR+nyyQjcOfba0UBqL6DOXcJk8Ty18mXtIC9iCIBHbxZMCIRhm 2LgPrfGoo9VcOpZi3FPa86zrK9QRmRxduAz/yeQ2LwOeLnmaSYO/rudKNpBhaQTjyf2g/ma2hswu EdncLgOag5f3h+oxmAEJq4HztfPR+0japVKq+xPn7GkQ5VuRraR/Vt7Nn89ZSdcfz5KRS3rczCbI H/h3FskOYuMe6xsI20w38YFYqRgsU2OJxCTzoPTu3FS88IZBAVEW1EcaHUbfDA5U3BL/05dXESB2 tLdouzH8JUgGwiorxmTuVNk5TvowHYltM54N+cemCfgtsFl1MJqfdtyYZi6jpO2OBaxbvgqFMd2l AAJfFamCBkmvyYw9Tiz0DOuVvIp6SpwSQPxjQl6b0YZGRN4OZWxqNtFh+6V7Bdkjx70JkQXVIGDv qdrOTXrS7J4SOAN4arWDTDRfqhocnPk2Gblyy9OY8UM8s7JS4N9yOiAEa+Pw5oDF++CZm8Wu4y5y ZirjmPqZX51xsZTkez3UPHmR9cDu8A7Q48GypYPDLQ3Ri19+aOP31mqaZ7NfbqvGlGtvmD9dDWP9 tTOPe6Q6AM2SugLeFQlRP0F7OSy2+9JJIH8ZLidQGBXrVSrc10v8kXn/ojHRRbXTgzJSIsbIEePn Dxp+pEYwu3ZxKPCkhIpi2rhGlQO+4wg98je1NqgYCTajZNGdDccVVQDoa7KX0byMjaJvJpFLmctX /2pzNnwL/Yffd8WE+wNfgMWh46L/OYlmdSSt7Ol+kTYsCgakFLSn0r4s68M/3zmyCEzwJ+eFaLf7 wXUB/vcQDBjmGLR2XHZl3pQ0a9Pp4eaFB2f03IInB8k9yem2rj+THO6HC2gqF3CvLupyS97+FW1E wk35INaZ+k3WJwSbevhmgNcJUr8K1Odq5IAAj5CmAgTg2R2aTMBS5DzIrlPoSie1dtvNFEJQnxOL sL8nPTvzSfFcZYQ7dTxBmEnXpTbuI0PBs71cVhPBOCOteo5dt4qOK+1ifKrtQSrepAaTCW6tA2BP kbcveIiWaZ2960i2Nl0dZmTrksufHo8nZW7N6OwPDkBkXnOo2FsH5Ha36ksDz3j8jYGz0drGZawR m66iTLH+vetkXo4f6Nz9udhHbSXW+HUR9V3RVLtzK7Gl/c1p196y8XHqnOEKAZhvt4v3yQiTWxrh rT8mujlx9I5BQ6n5c961XlrKFrDgQ/wIj/jkt3H9PzVyByn8MyPX5rkMavKS7/hZOi8UfwMf/vU0 wKt16Ke4F+teXnzdpCvLYzL45EUodYhFa2Y0gVkEcpyU+UnCZORLskTuktKDMvG2IN3qBebOGSPY 226Jmit3goEmYetTBAIoNHqHWeEAaa6Nqf8xoRUgAN6OxAuQoXrxVNwAQLpTm8oOqHXKTSN0G78F C0PrIvftqb3eh1a56uyC1jinEmYkztgJXTdNFcjfKf7twF4sIipmcXJHuU9wPJFXcSGWYlkRL8WX PwyrEzzle99j9Y7bKCThv569NOx/DRXmns8ZRgNwZpjIFTJMx+2eBlwqddnZxJZIDxrmd2EZaIir taGpiopXh6fNEXNWGoEciedPiOHpLbH7aygGhsMPRYNs294SVaRRu1QFpcMUqAN1dW4VNizijAyH Q1DsA90Ee7A1Spt7BcBuK1+ZnP2u6O37QciTQV6IvBeDRgylw5dpjRtEttXnh01VNRxiKvtRjwuK wch7Kamq7fHQNoMGXFQAlFRGR/KlFQVJ3nzzm23MeQV3fY8L5Cl8Hc0vZQ/xzJGf5nK+NhjKj2HA gtFCPf8PCLzFsEpiS7Gb52xzlJY0bvRDP/nCZn9PMIIvo4nl28t3oGPuG4fVp9zUxeEAG2e4qB1S 2BuDRLU4G/JtccQS8q6UcIMPLx6g8BzyswVkghlwBgJa2pb07rHoiLWhwtN61z/fb+TgvPsMpxdu RTfUCEnjX61XEoCp/YRI/kIpUBf3LZmPPXBBzV8QVBfAmwwCmbwQEBeeuPHJgWnQypQXZp1h6jvy 3BJjhtl1m/doq0IWVD87UXFAG4ePHkShP5N4tYAbTtavUFxAFM8LjzdqsTUuuUXTSW4vniNdZuvy d1saSH0nAyofeyVShGCTMAfhnd1x+D6LH6LFuv3Dm5urHGEtuOXh7j6gsWMxMHGTxwYxsDt7MjhA Uo7+SKFKmok9W0MWKkJ+WSp/JxE26uyYTJ5nrBAmQW+Uuy0ZWkF6gnrm7DlZYVQnZLZeZYXuO33U CNsrsvJw1l378HC95wZWpbwfaGxEzKDotMctYkAyFdNIshq/TNKlfI+5hOCp/g/ma4vIhQEVI9Nu UM7hKd5oYeX249ABd2VKoRv8Z0Rehx6i4PEzPBlHdSjZKdt5zmzbsvAivoULyvB4upkOmmYK/rUj VkpKpm6O1jPrxfUrpVdTKpnhKTz+jACxE0kWnLelV+VmgRGY2SYH2Fq8vJX51YpD63+UzkPIqMzc VXVsqA56UiXYQxexLt5grHSRjM2Ar1g7VEwUhl9AWN17Hne6yq7m9xNTN/4T7wMfpGf/heVMyeDH /IV2Oypx34/zAvPtY/LGMab9aKNvHwxQKHScti2UeinYzbswgbgI7npHhF1Hjl2Wp0FdQAAmfLPz aijoHfZeuFGGCnCCaFKhBfJmigaDeZBY7bSWhFJ7IV5FL+7xCJk0OXUrPegmAN1SDc2bkTRUaUm0 4UxukpQ6HhEAS2/YMyTQ4KimUcbV015VVQt5geCFKZo7WM6ayuma8tbyqdTJbA3pkxCTYD2eUTS0 yZYLKPQ19VTig60+JhBL5JRjX8GLKOuB5etEiGEVCUqdGgEfUJdn094u7s9iuMDWkWjg6UZCJLXc eTMGnoPwbIsnkbdiBayae0hFB2jV70QgYQ5gleZMhHnBgs5lcs9qYqP/WF+MXPbTt/qPeBSqMaoQ JnhBXjL3ldNUh0ijs0omgoZJ02UtywnqyDRbKW9isAAGR73xhKV4rTeEe3WLf9ECcZuIK1zVDSrs FVmvaRp4jgUl8UZEQoYDOIxY8OmmbXHRSkNPFTYIaa+c9I+diFgvWIqFQw1eAszWLLZsoVA1uAbV olxHBMmFhkisDCtHDFITMoiZ1eqY/wVgfZpIWzaampPm5C52rzdzv295ZdEaBfG0RsnvvjBzhHt9 D+dMOTjQdtW1zyttnjB8Q0oqQ9UMbIvtweEBFBx8Avn050A7/YuzSmZ7NyfnGnWpTnuRf9/Q+Unt 5tG8mM/F73P0uKyac5T0RB55riW2sj4def1zycGONSWxYWrl93t2u8zQfZAn1kjukvLhCnY/P0RP 61xT6D5gvUOEY3gjzrxZJ4F6YyJs1idToBGqi4XjV68YaYB118bhYFrO5wmwPyxDFkJ+Ul2gcO0z z09Sv9UJBjNTejBbRPmzjWjApZWtC9zGQLmGJh7rKwd/7RABwH24/orVx8yusyNAVoP/MdkNVzKm 71DHH3Q9MNvWn3821ksdRklJfcI0u29d1pYWKgJjgwc6rX/gxLGPqOjDZhksByXS8WitFB0rNlS1 ohHcejWxAWnQOs1Be33glQJ5T67BttWgHxgZeQME3yor5P7jFEyfMpak4wNbTpc15rZrHifJb1HM l/8Ud0YSB+a+zvv45rjBoJ+xPBr2U31VIc6I4uhG7wy1Xfg88LWcmCXLxHMmyxRLpXjwo9oZ2BYR +a6CYpw4D1PivV7Dfjd5tdoUNJ3Rf6R3J99jtUaBPMUE0itFUnL9WjOgWQxtMLo620xco0tIeNGr hkoxMVbiHt+DDFRuVpqjOK19YjLMb1yu8yr5K3mHClWPNkWtO7QQ3KW9N4tzNqPPZw4oh/6ZYpif k5ckokAZFVRK9JpA0BSZq4n0cfIaMcNjeXbOCtbcQXorFdmN80x6ufCnj8x9OVAbCtQthupqQdBu ypI+2H8ivymK8mmpR1hqbmJyYOYY6rVIB8BtF2zGHhSMl/cA2feUYIm8pU+0ro1gROv12VktND40 V4HX8P8xzjYFu60ZQNsjEWOrPELrr8UDJ7oUeyO0rtGM6z6lQsETQz7afBGJkJYKk36rob2NYC6r yfVmsJvpEPgmy5kJ/P8PirbYqINQ27t5dmI23nIVS6TLXPTI1765GlZxzsYyyU1X0Vqui9TZKr1H 2fgk/3FWIc6puGSEr8nFOu/m04ArzB5GHvKD1ifC0VsckZVAoJnKZ1+mwMIgKn75m/OUTExRHFnp 7kBYl7hZ20hfPdGHvTSFkDGJSFPilGxpLvI99YK6tAjlXFq/dxWynbpdEpAwbMjSmMBJKs3YQ1JJ MOdHFbNNupa0nGKfrCwSWiEyo7xDrTF1ldbI/aDR6wFlMWiFJhsNoGQf+1GX4c3E011VgwiyaULy D+2rWy6FIT0PaysnAR466FcPk5Y4jT3FD5rrNXDjOwetJtjGuegCBjBz89ZuRPNNQYOE99c7tjQa NWnYO3uQihhjDPACKRcinh/2GBoZFzSILBfI4NNLpZcwDaLhVyvvky4CTow6Kk9y+zFqkemWn+jI tZ3AlcVQdhLULzD9X+14qNU83bRwTlgrAYhSzjkVfTjwX9vMmic7h3PU1HDaL8FuVHwXSM/Wjzxp ZuwgcurpTdJcEev99epiMpA0l5umwE0bKq2QXgMJySkJrJrUH8GeTdKPNgJjI+4dA71j7aat6Fsk JNcmNt3ZSTGKLS3ZVwX/+g1jv5OMREu/YQ6VH8rca73dcrMf/BfCfMfYWLlgFmscgxspJavwgSqk dDrX+FOiKftD6X7jmm0rdShThQBu8VpjkNc2mJfJd1UcClf0NmYO0JvzPUMCrrVfz+uMCImSv6Sa F7yaXN9KZXHkfMiHs/c/OSOfRTV8KEjGCS7gm0lt6zRgWd4vrVDOlv0j463wdjfUdRJSAszQ11GL dthAhk1yw885GuA5mpnA66UZTvvop6g0x6PfQ1WfME9jxDp3u3SLHI7QGUPY6YFMWqH4VImnR3Fa sM8cs83x2GlF8P0VRyHC/5s07sgeQog+WOebR2bl9HF+LZ41moOonB7yDDcCpxTyiwQ4FnPMOMIb dvTs3e5N42z7PJz8TySgD0k8N0XU5KvOJryu3o7MMWqhYAPA0cpwolj3IeBAWJGBDkrv/iGCJhg/ Alkcz3kIo5Z6xGRLVF6OTuptg9gasI/KVbY0xaN7MZa4NDvIn2Jpj9Id9FZH7yaN+oLw+iiJizlc DZa00vMJDaLA3Ie4vpw7xijratUkl4+lAy4J+68MoT7xqMmwlIv/43YCHz5PQpqtA2mUe1o1Znl1 6jDOifWErNyFepBwvwCIvmDEfc2NPkX8kHh0fzWD1NJptU6ITia37rPzU9zvwJXFbGP7DLPnyV5h IZKXIECsqbVPunr2gH5PxyTQTwH2ezBderEiTl7lZARgcWj5l6GMIpdI3EDLlE1V+Cw9uAbgdkIU 4dvJEjdhs13kapR4CL/7Vihhe+2B8wTCAGWZc0Q4QXCmT6Ht6ftJ0KRBIt8x4T/ecnYXSUKVf4gE ze7GOPv3kZFqC1DM83KTNhW7oNz5Tbi1Ywh2eaQ8FYDy2Ldcj67iTTpKkFN/C/8836TD3oaa3s0u 3t2E02C36kjQ4y4iamBl8hEmL/OgYj2SNhi+haXQcb6pdnCL3vjAnwNPvV5liedkB0c/rU0s0CY6 XSXUAnLaiGlGPs5OYaKZT8WfGU7wI5zoxCAIfIAoFo+Sw0AZPKjl7kA7MYBg9HbrUu1+4dZRT+RG ASB608dDPOh69ddUnHRwW1BhNnhJA88bEjGC/YabLSdnxvojH/RLCDNW45fJ8+o7+p4jpvYeCNAG ZiYiN5ByJL4Za2aP0Z5jUmALRAgGQ9uc3AgKLmnj23h/SdSnn4T2/Rd5SVJsfXt5rbbMisjZ7P4S zXSO2yROqkuAjWiRYxfckMD0dtOzh86BjISHl7haYpfmVv3yDKuofC1O7DKVA2KuuEV0VbgbMTGk oqeowBf07+o0K31ldsMP46Or94Y7tR81IYGYp9nPXnv8DJWN9SuZqhfWOUQy7DL0RP36DZG6wV28 e+lPFSHgyYezHMAfyDU5PlVufCymErdy3ey03iJWzNbjB7BtK+yZdqCKlpLdElot60s+/w/X+79X fCFqwXPsNsZY4SgnAmgwTdpA++RglLzLivd+xUAILJiBUbzPSerBANkbxm1CZoJdfYNyafNT1RJ2 8pDtFXVSYd2FwniDcetWtfyv2qRLecsbVU5wBkabEO4m0NG1btCMFXYJAIPw8TwnzhtPbPWTw+A3 wtd7F9ULp1orxBaVx8rMVeqI+YFzJFdxykeXNXBWI24SKJRtiBw5qDOJG0MDMShIopChcQIebmIm aXTPxSi3Yv/588JGME8MlsvrfvW6wg78bKJDl6914EvYqaVmx0LkggSseIieFZLgDYwtYyW/sJWp cchME54Ve3DZWRNh777tqvCDHG8jTFTjaPJFJiFo6DxmwbWblzt3J7ZFW5PB5w/fqgDn3TNW2DqM JBF+0EnejJlyVNEZ6Mqw/1Ud7mfVkoAwgKpbiWrRBDkGxgMW4aFi3L5GY9VVhEKfKWwDZnWGcgXR ELjVDdfaqAPCi46GvmKxJYEy6mZOAigW3jUGmyIGoNJuh0tVCGnrcYZhrRw30h9Bo8eJBGC+UyMX oBglmUiz6gveuBWbls6Bj94+HINmiW3ynuhZHkoG2iL9TXpC3GDwAR6YMjhBTAXUsiukIejfemHN TFSYY9QLz+mxm8psLXoEntvc5RF/ey+w4g8obhIBEMjdzC1BUrVpPAkp2uE7oABcXlTqKZI5c72s FqjmpJfgH8Hr6d1+jkkEt4bA6aeyRFg6AJB6/ChoLw8QBcuMOtdWxZ6VmIBnQTCLxduGIpyhYEy3 tDg9uK1Dqm5R4hryaN8rhZvJaX0ARiwREFvI7Jv5s+J0AzUR5ErM+OcureUPgByDR79h+i5iPigZ WvUgOnkpFmT66EEAfWkhD/TWDfRF9W1YhZuAVq+TgBxP56cOvELUP/y9uAUcSef+VaONns0zjcoW nyKdSSXtU69rcKr7WmAdtcxb55wFjgy6gOHWO2dHuI/qFcnTgUAxt7UprLyBLB9zCgIBBsLg3+6p rU5YU55K5V+09iAlylzHuNaRTQmg5vIzwD4gju3GzXqPxwVvPxizbXIoPCc62TactvchpgVyCLRU XoRcoUqlnyVpFKfmhLsRE4fz8Lu9aCBVkBTQzgShUMDG88IxCSSexsM9BXPKUFH+gqLN+i/0Sh5u k1UryG9fuRSZQh/pTHtGt0BVRFvzVsUDTA1Wwmys5Vgx9pPHQ4IPXzhxpAk4Xw+KhXVUeT39x8g8 K+30WANvjvg7J6hccP0FAdgglihccNS99ymg4CJjlRnSmZkNMSFwVn5ApPMI5xVOA1C8VOQ91GEk Iqpj16QmgTrHjOPHCw9RsaZ92wCH+ohCQVSIlz8PY/OTWny2KcCxQnuhtA+GKCCLPmQZmXVQ1x8Q Fc52W+oorEqztDZM/BpJFhB11PyQ7LMOCU7P5RAJ//4pFz73nmI11RLimnPbt7q6+Ejrug3UfBif wXvUvlBLsJxom8VrKLN4bVd9sOPKA0v/5A47gzlwJyE03Z7AYMBNbyffnKMzy6Ylfy2ESvoui7pb woVGajBnf8ZkGpqTBj3yFIiFHYBo+8VYPjUnepdld+cnNO5/iBIiXh+yvFoAIZ2gjEEolrRvzXyB E9ky4W1EfDGt09wq9VKV6rgTZa5EYsT/lzGyzSrrz/T36mOiVSu6Lp6GYuqZvgOvrT0gjD/0MNRg p/kQD3sRK92TTzToNSRfRdj195d5k6qsJjiNppmjUc/hSaq5r6DOVk80F2NrcnJxOCRzbezd2BhA 7Tc0Hr4psgFVP2xh2up3/PPSg9uf2mBEqy1hIoovUah39qcNzexYypRXkmW/8eI19dAEsaMK06A5 2qH2klzncVjCyV1bC/GIjDs3u708GRNV+WyBV/A3nPPDQskzZFSuQUZKB0OJ4iCoKj/dcw994g3n Quht0wQgE6NTIMS+8V9JPnqtrKwMXtKKjq4wc3m1BNJr9u3151ubZAtcmvumQTQn1LFyYy36mCjm sYT0Q+4GIf+YRxJOvOlKAWwPVJ929o0/ay3DDrNr5icFS1hKsx92Y0ADbKj7xeGchKuofXZKlddk uBDHU5Pt+AdbKiVynMowg0YsSPPqyxWjItagGDU9wqvWnUPFpfoLO1eGYE3uIpItqJ3Yw8SwvLnO S6GGkvyvHujUbkwwFVKt3ydIdEx4LX7qH5qyZ9SAhi69ZrQSFyIMgD9R8ASnKgTa0Yx3XropWQid Wa4OMSBcs3Waj0mXTFNTaYHjfRzI/s7soTf+8lEdQaKCA/KOnD1kEbmEVfEf1kPJFFhjoEW3MMMQ nlGUrLZcmPjDJQE44pr+hsVLcqreMGe7m4y0ci2yK32K/i5nWH0rHDsiB5GNXdLiblgZMW32bAVX J/W18ZOvEeTmUSDiaDmnSlpuHworxo1DtElTRsGZ+U5371NZxNqaEhzgePk6IuM+C4r8MYdVKAaM sfiv2pMtTtZr5531hPXP6i3O9ruz04yPXaKYGeJtI+s5r6WjeNDzgkzeJ2qKEy7IzktivIc92yvB E3Rqcd3oXVBarKpXJl2rZZGQPGIO1fD5K+0iQ/3x77sbqlP8jpe/lG6K+xxWONNF9HCizVHqjnuJ VIlXkUz/h8hdDvFcxm5ck+QuaNx7S9rjAB4cWZ14n3T4zbr56J2E5jA1Kp/il7B/St4hIbjV0IAH sT/eYG3MZXNyNWyDG3P/rM4IrQfEhJptyJSHNdskXQpmKMMXc4oxPJszdK1KFtWpANqYutVTJx6P qvO6ChL5xkdhf5mWBeokqrmHlesf6u5atd1aBEQtQQUYtcmCXYtnS8hrHt6FUQnISKifRPYSMMS+ rRTpHqS11Ch4Cdqj+S/BS40wfRaZb5go5lBrSBAavEH6j7ajGR4FZ4InM8YI+NydFHkOgMt1IumT tU6yI1iQr+RF9ZKxIwXaGd3RIGWFyDmXzlE5EFU62waZF988Wt9DL/dtC2tkHYIKQjDfxxR8lvQz iJtlVDI9NfOK9aUkVsUxRhtmqUjminkON5eNAX/7UQ07PZWjPtHtdxjqLi8w2AFffAiIe4cVCzwz xz6AoGdsNHOYYvPAr7u3m+cmXRknggwiore5Iaxywt/yQK2ALuArWY14Ho98h/Dx+wt9DmnBfedH 4wy0CcDe/VZSvhzIUHyFYaTLHJSiED2KNkAa08pxahjL5mTfSfMPvys7dvXHs3NOUXuvPY7OwPqo wDbbM7BdymoopvyOi6/ExwH+eluuD/59yr7NGfSLJe6OUW47IyqAM0rfIhe/LGHDF/pl/+PRN9Va 7unDx9HyAgZkW//FWZUbJP94owTpzMfbIdcnHKzzf+4hg9nMkHJg/f0yf9zNH8kVlZc5FC3K1Z9F KHbRbiiHAy5IkBAez0HwdziGPTXPupW7Nh0MKLWgCeofaQCGcIs8DROpjTe52uqasAvvfTvZ7X/Q TxTb2PesStxQ0sEYVDvw+XWnJ9H5sawNzIZlIcYlkSgi2M09hXekJAlV2Hyc6wspS3XPquhw5gFk RoW+oyywgzuNou4J5I1VXgqY46sLujhzjdBeGGtxRUXk7K7rLGofqtmgiThgRWg+lSOqvMlQu7UE 2/zBJyqWwyo4IB30/PyYN3RfXxcfmlvLjxdffMciD4/KF7+E3y9cwFDOKmxiWLNANjl51Q/XMiR8 oChWCXVp2Va0s0Kwj9jY3ftpTIxuILzTU48iGXb1UVMYCnup6q/iroNNfUJN5NG8X2e7Ppu3jZia ArKk1qqlw6oB3att5f+vdFUW38DuMf3whg0oIxjdi/KDnQyxFmB1PgvEQwqBWohLRNAK9s2bV9HA swWL33ed9vU6UHJv+ltUzIV3XqATfnAa5e9XFcCSbAxgLL0i0GJzTuRDXTPx3wJNU+4khmn16NNJ BOOBoRectOYrGOcThufHWDkIcuaitqNudABsrDQDcvnXxNZpLtRa0eVghEotTd9mJWMZMsuPJofY y79KFnAAdg9SScBnsu3wsP9PkyeXPw0yqP8rxp4ivTvpANu42TkHbHUweFPotPJ5mTDC8BwunpLH cvYbwVopxkeb+m57/Ms3/cGEaSClBLU5xqxawfyBdyYF4TKHr4bM61KNmOSDEzRUhDA+MHn7+20G iLvhzVtZKg+LbOPnxPe0wSjXhmCSrb+yBH+knw6WYrVA/K1b3PY7E6N2WwOj3rc1QluLnQqtKQKT CwVQVcExVZ0Ciw1FMZyd/wOvJOVBx0jJuIkiG+fu4lZarAgNq33I0Qe402I4+2Lwa2nDMQREb4FQ CcXiGA5yGhOn9by+ig9OX6PF3pFeIswAOE+3TVBksMwti79ry2hCKHIueNbl6Oi1rwb0WWTPKC4B yTgn+nvXoQxMlty0INZe1tOmx1aGXde044l97ASbXwR7eKX48W71qfiY+OHNcVTLF+8buBKoKfJX zC1GXMLtAh/T1ZrcSkwrfmuhI3ni1AcqQvpzF9QDnrcaPg91zGT5nX6lBLgCBreLQ1aNngZwEXxT bl3qKDOmFhI4acE09gS4teJ/BFE3KOyHF9MQppg70P0HzSFG8taJFVnuTpya3ubj7xmYALpj/r70 MnIRR1UTwGCSwyITdX5zUFl1iAVT/hq47TJDBbiYmcXAThiIj4VslyiuzJL4Bx+xRXziMAi0P9rJ rza85CNFydXT7DUwj6Q+o1K1tpJWnmjYLxsP2s7jjyNNLDF5SSYccH7eNvRgnTD/nz0IaJ0GPiJI AIZk8yY4iLw8Af/lgpWeYun8TPwAHTSl6Jo79BzQ4hd5Iy0Cic9j7SmOsiDhNwHrAH7zqpXZyGs5 Ac6nGJwMGkblN4o2DAaz0WEanY/+aIa5D6Oq42nnRvc0r8HXlxF6lwji/68SoO0vE0DW4cGCM0GU B8B2OY6FlH9IUcnAZ2xhCI0dgM6fh6OZgUKcx/13SQ2pTeFbgf8hRBLtvKxrZU1jiFSxnMhIHr7n qdfRzi2RSkvdoiKcWdrcdLFqV6ej0hLzhtiad4Z0hTAXNQE8VaH8onDnx64iYJyfZgHRcuTx1+0q kcdsKnYv73AXKfJhCgEn+m3FcHHCCM+STlSU2GTzr7GNKTGLcrvzHUKPYvP5g3oOjj/CJAwRDyPo 8x6ud4nyNDmQAxhPLxxEEgIrNsoNyjxqD2VyEpJjkpM4wKfuOiKMgukEOdS7vLh8ao+FjQwy7p4r 3C7usZwVBpN1pJ1gMJ8DWfuDs6li1TbCKIkz2YxCLJOmheRxIIOBeNZbsp6cnnQ3T8dWEMmsjDBW 1oNNY1tPapEFkpPcdIn0nyK0JjBdnG1W088oTEubKmbgP7Mr6ciwDA5TkcsMzeGdOfkbFV5TARUz 096CYTAa2jZWHZgXPT6coRo48WmSW59nPHS/Vp0rQ/AhcpcdvW+sZOc07MaDCRa0XjJVC+txfOe2 d1qRM3TxbwMx6neXbk83a5rj168BzuI8x6FiCO+tpU6PmKadYfYF+eZOs6TereN167S+14ftxA38 I93AZuOAkCrF4w/dhP09ucwPptTbre1dAOM7znclFeVnIQ+ES739PSiegLyJUid5YNFToZDaideu ZDdUN45E+dNNXSnPY9z/hol0y7qTLFgWmFe0yLiAUKNi5Pzffa1Sc78xNRzUbHA8pKA9NP44dqDV li3IASM9wl7vVX7LFlz+h84hElhXhzE8cyEGQOc2uA8G7KZFPb6N4gqoD5PYgOvzImF/we8qwNSM 0t/VQ/0xsjpoOpNAzx5gXswSd8xJ+nd9zefI3XJCNYqO8g8KOzrvVNIG5hwm78ch/Y46L1wOJIsn OhBDfo9z/oSfjUXjXq+hYMd4OUghnJbXtlImt/qWX8i/NrKDhTNsOy1KgAZ/+KoMTqXgLL1pp773 cp5oUkaGypODpyD0AoyYmkdjT4uz7EnjbF+wxNQ1RBybegrEIcq8bADPE9L3QWMLFCO3yBrV3L1n 03PKhHyx9DmQn4zvlNWDVWxgAp/rCVYmoHBPb4wng79l3GblgPBlWN+gNTilG+yuL2Opmvl9VR4H cir5pVSYQyMjMFOKdjfPB2pdXee5VH6V/5nuK59bq2Me6HRSEXZ5GpKkNcBrD81q3V/ZqElCf5Qe CTUHv4OSOOiparL5ZJU/mn5VcwofHNT9+UhstOAwxRiYw8lTwsSn6Cei9+Vtqq76MpMUo4ZHyw2l Z555JBXGr3CQ0Ac367GOio7MqmEPGcEmUdHO1ntCYy/jktYhIpgB2ff95N8+JJIpoCb80tP1oC6o +Zr7TEkR8ofbimhMNf7VKrWZ3IK0nVfU/QVEstBuGicuA17EXJlv6qTHbJvSfVc/Koq2boZAjgA3 eiCdPMWf1uSeCbQp56nMnN9sL2bd5L7y+gyaKq7SZSwdkb+HHqDO1QKt0mh51ohrhvnRPY+yLYLa tX3TCMIJkqz2S0VuiEnMCMBypkh6NGx+8xZnadRTnQXd+VWYO0vLGagr3dNgKk7NUVYEq0zZJ8id xOCyy1pqh3Dkz4lRK/jrklGHWAwbvtyvIT7LYaTWwM170erkcylAj5DnY4KgVox07OHUIGQS4lqU DrXawaa6eTgvhc/Ou86s9hHx6ptT8PzdLw11k0ARFtCAfUU6eRplGxWxIgQF/9+D7aujs/T+Tezh c5EFnM4zCfx2QiIuq/rfkwEb4I1gQJH38yL1iafvEwCTqa8DLkGIV628Txu9m4P71dubkrjtZdcm ikNO3X18h+N8bYmS45WipoTejfMxmb3dYnlV56EyaPGR0tWPuGhkZKEFqVQ+6iy/NxTU9E110zbA +LymZi1CuZpXcDcccTvXmXpTV9uM/eARW2anI1XoGzetq5h1qTjLTAljJSr7y0PPHduTGMYvYuAL DaIWVOntbS+hDAVr+eSbhv1U6j/w5ZHvod85s1rEn5y1iRxg3HIxvmFH/5NGDvXAqKD5fpNAGd8U tRNMI1JgH/ygEnKHRQQltQj+QQ7u+HcIUlm10oVK9etKiZpQgw5opYrgbEoyCAWMy8Szw5Uky8YM /aHHTSar5wrZQoOwt5iBlu+NZBf26q+mJvVBH+NoYOBEZj/3kvWeZym/NpV4dQWra+6+x+PCKiVV ecoh2+sb9kFlI99G/GlAHIJhlgI4Sz1KVPhXgNHxNi6SeJNt87D/m8A5UYsgLvpyGn5j22omFcKq ZfJO5PP5ieheO7i5xapnkhUqG+8SS9LtZmovBewk9IVz7Vum8T37lEDHWMDop82fe4H6OiUvwXYh vLDxDJhW+h14zy3I1DKchw1jh/47xpezYqsy9+22AI9qMw+vhd69IomtDiCTmbVR2M/lv2BIwKIc RQrBjFYH/hK8eJw8bRxruUdKLPADWFWQBqnFNyXm4OgVQfO4GMh0av/jFGPyDwGFOP0xrW0OOXK9 y/mUw5aB28L/o3b2NBJaxLe1Ow3iC1UktrbZKSsOIQSsoeoTPrAsOHyGgk+E4dXM8G4Y85G8OAxj cCbc7b2DvRkltbwlOK/YnMwOu8ME4WR/kFX+B0XdJfSCO+qHEzfxGu+n80uYCINMtwV85pziD9V2 kwWYQXVy/IR1J7vIDsG0R0b/IYoQnQ+4t+329y7UiAdsiHw210nNyxJkG184YFhOX6z+uKBdLtf8 5ek2eOL3aX3oAROxdrCqAIoY7meB8lvBKuLaQWMkQLGFJxqFjVxUo8SL2LSpvHAgNhzp9Su/+ZVL 0SY5AZJIt/4sbsMXkYw6+dhPm+Q00px/G1e/zUdXV2HMq75JpDf6uxHhzFfAREOtPhJvHaU1/swG k7H3KFPBha6WX7+JnQ9DMj5EdRFRZV5A6592pKSt5Dl0otwJ9xkhauKBDhXju99gRQJbes0pzbAj /xXGfhtNm6UVxpU5CJGNAVehH1tZV1kLFwnbGJyUREylm2tltMW5naEOxMrBmpolI+mTY3wQsggg UIs7BmLa0QpJ6hGcDwCqxFSI5GREy97/XWzPtBkUI6ADtFKCXiHnJUcvWsZutv6wIXLWAFuLxE00 JeCU8ksO9rzBC5po3S6rF1KLHDnLWJamXvBshrVjo2ug1Bevcs02XmOSBzR5SxsukozYhEFGC1Xo SlExKw3HEvBOkz12i8Bcq1soh9y0z1xK771zl0VVdwT4Mae2OcsFl6tbzqMBJyPB0XqKvNXoPNwF 55hlQtrhvtI5put2UaVRKqyXXru/101BFsBUSmbSKmBlLcvBVGfru1/fbqhnaKzmdMPbIJrIuLVu 2DIo2WhF/rnOOzcpGIs2gTgZla1QKNFR6Bmq2xQscPSv5Sqog6sPgwB8FryhcJ4Wn4sN1+CmkIlZ VzbBtRzIrWK2YQYF4p86N2qsuyvZ743hYtSYG2PG4bvh+f3SGsTDHGWb2lUF+XDApYc7b6h9Bbr5 //YZjTsFGPOxw6XyaNGS5BJQCaMZe26DV6sOWmw8C46HN90McgLqpqpiC1SdT0m4Vi+4MSaTXwuy iTIeEV5dGOnqxAzOMczNhX6vIU4er07raNMKGCwACEa6EyUmxQbmw/nWcZKSrZT1HcawoRNCq6o2 76NqjUnqyW3BFqyFtQ7mXdj/W0xd7qOwfgQYvqOwiR9jDt+Q5ovMjL/D11s4qk8cIfPpz8HAq2g7 Y0neUHtxseL4rr6CR0n04ALK/NVD/IK9qha89vrjcjiBTcuohJBMhXBDgoGyGZnNBVxail2wl+o5 Hi0wZ834tN7KJVIm8oxn1jbcXOpRQUq54p3sd6UTYGwhIjk+NJKlEc+QkEqn5v316uKzTDw2Xs4t 9mlAIG4JIoUOkqLfSfrVNvkl1y+S4Rp+7uNcxjSiyj2Hb/SZCsPQPp4+io42sF7J4rYyLzgDH0TW h6ZvKFuKjjS0kSeQNg7WcszodXgHTXS6LVLvAL8mKarK0EOzqGdDAYxwb0K+OzUMSle88fS28Vpt 560Jga3UzQ2BXtir0tQlEk4tDKfIiL2eOxQboj8Ozj2Le9SjywRnD2Ig9q5YjyMeGU5QkfTL7Ra7 1tY0GVeHTqQm41ORMLdQOIed+MrSD60P45oq2CuVafqyvAYV/zroRmVB+I9X08vDlYCSb0+ipZNU 79hnwJDaKpCs+BG/hEcPAqhN+XYt1XzDwgyqhQwmu3v1i8VuuDGsofyXiyE/cPyGnOYepClY6iCl oCXMCp250WamsV6qB/gZP6OUSPaXlYLQ+tyjJCL4TvbqDx97Zqqppc1v3NWo21XLt7FZ93e/1K9U ZM3sN6ay9KxIW74Tsp9MC91hem7yAtQ0bMCFg4z9cb5JQKEO4ypv/S1m1WQUUabnd2zFnEM/8Zot zEBeAZBq/wLjycAHoTah/niFva/Cyz+qRkT4mJQROdrmwtmjX0V6p/n4KcAjXINfpdsl1Ca4/eCB 9UpO/4FqvYW8RXEo8FWeUO0bolkcVTAi8Q22GZzQjRFnRlBad4z6O+ukI9CHvVCuklMS/DRdEHrV XEcTYqCq+V4GX26wnNdj8htAsdL1+I+lYYRoc8wbatPiurWxUoI91UeC37Vhzx49Ir2zSSkRu3WZ 3uaI3CzLVTfPUlUFOu8xycWODzetRMwpIc1VyqwW9flYxY4H6x073HbFK9+4K6dfpngp2gK4Q0C1 KjQnhI5HbRf66RBNYUfbsrXIzSnjBdPhKq6s5R2Wa7FxUWMYvkj0xiBNXBlfOz+WywbkaXeBUSnl FY75dyFYY/k3+y6i8xGL2MadBPWElxEB4uZGF3M+wZ4g31ZLYA5wHI2cVF26BN07MQdinOB7/bXR O650SiLmFvVgu1w7e2piqh3xyoumLlHGrcAC2GF7LW2DhlHCqKzUDga2YoOVFU4APYNrMUHy+4dd Va2hxMsAJbXqiYX3y3SY7meXGPcsAPLfXVRMUmH+XYTkPBkOqPmRtzpGNSW/LCfo3dd+fW5n35Fg g+kw1vtdVTt8rO/AIVfBTJymzf0Eif100NoMuT1WqC0EYZ10mO/GW1CanwOzrO/TOlCEh5gVzQNb aVvBZzy2TCWafrrrrPkX3sTRUp11MKvQT35iD6JMuwwbYsVKP2xe2H3viq+Unr6wlJtViCUyFjSJ oV0XllAj8kez3/nH+XnbdXHBU4yTVNaEmojBrcFBl7t+ptfj/iabhPW7KD8p3ZDH4+JIBgUDi9IN p5UP98+apRl0DlxsL0Nb9SuMJtBB2LCiq6P1iwu3QSa7AKy+O5SNYhSujo1N8Aes4zefNxJ4PIFe JANpMKjCFwnGsYWhf7nWy0Do8errjhXoEbfzC3+GGRwV2dr/2HCT0aTKH/VPKR5Pf3xm8cpuLEgL 7wLY1acuqwMzyndPcpW5hqRrrKvw9MnCuJ9ri0cSp/OfNM4yP26squ7uPV5FjzaoTNQ/v1YfhzSb Yad6T9Sgxl7/z14L1uwB7G7mGGns5J0cQ4+oz0iLgze0f9EXhAuEjgxgjaonALh/eEC4hbvy/N2K bOhiytfoHRLktTlhAUIn7iJ+ogY1Qyf/115uoMP1V2T9vvBqaLiPJl4+pWVxoGl6KTStWqiqsBgL b9H1Iiug+OxhCX8iMykgRAcyaCWOxT5kOjKvGfMHxqdbBfGshJiW1MUOFQAM7Bn/MOJVjng05vc7 SOymE3bjNCVqAOGolLUo5RY7uiGi/Q8JUS2ugdZg504C6Qague/GgRD8NHnmk1rQmcawl0tir59z CeR+ocFCkS0a+oMNtY29U/W83gdcXea02HGM1e7sMKwqlQm5ukxK9KxhXQK0KQOY4pBucsrt5q/H mwJZRXcP4hhV/Bz6HY+l0j3M3xyfUIFjdlGbYtuEINkVNevlJpS30X0WkRyeGWZisLszPhL8n/Sz cl2I/irGjXKVWlFOj61U+TpiM+6ohAU8K6z+7gWh/bvIAYp1fV+ZuJ3cAC1ID6iU0IHrUnHfI/g5 RLJZG2POHtdq2L15fG/NAQHSRO+36zfBWf2rIQmDvn3Zz82wMd3unoyapY/MnY+ktfUPI9kPpvDE +p2HGNnbiayjnSe6CszMkXHUOdg6qrjv9R8SfUe8qoWfEZBEzhm59v8hqPp52jfSXCvfN8o6lSSE tb8DoJFRvjWuEvp1BAUPrWTSXa5PMBm7yQTSE4xtadxKL3vyhpr3N0F6kNkOho5cJzpeFjjljL8z EQI/VgwPb3ySDlUFhY6qqesCwNSTJxVuKHAOyAZR1tdhONtA/u4Au6OosP/2uzhAw9/85lgeR+Kz 1Bjz5mUZ9dLvvhbmOqTkbiGtc8Opau6qeK+0pbq8pxPlOmEw4xRftuunH+ogWHJ8d7Q9qK5OOjQ/ K3FBs1gvtyjCSOERDuPQxutjxe3nyvj2mCcs4vRyBlolXe2f9eIFeM7b2BXl7KsquGqcuhEopgcF RQ41hpLdV5QSGKalmTBIFAfmq3VTbXYQpgmLZ6Fivm9xcdTHGfYywoEZIVN/aWCZVXWjtEodBwTC 3XSkVpOY/1SFccVhi0eTg/ShIVgqML+gcTTvDuxLrYJryd5xRxDLi5rRmwDldaNpi6lrVO9Rn/IH 72ctATaIcOyxR2Q0dEfa6pBP7GxUdnHXZBdACNqsMgawLC85yJenvrGOtzkBAi01ztcvAgmybr2U 46idfRMqFsA2ctzPWZUkDAQM1XaPqOUJ+SELvqP4gR6A6bmgi+hSHfMRGn70Cbsbr6a7eqJQqj/f GtfJKN2BQwtjSA2hwgIA0b7NdsEGnH6Ia5++EOne5Mbw483I3/0D1QO3W8TEknNMTB5EoiotKTdz fSqT5xppxFEmlPn9mjOSksCxY3fT+ybLiDjXrBoPmEzyGpvcyubCwxFHjvKOKq+QMkDFp3MEraUg Lw2lrGxTFF4cBJUARC55O3PwgOr8Psu0krGNb3oTVeS4pZrbki81N4jKrdedp1SoL0LPT4V1PgHz EtOovwIh4Ke75QhXebQ/42EITlJUd3G5ypwyZnPP/+8YG5gX1oysWv1pCK/Vwf/lv/TJyeNqdx6D 5tSdgY6lz9SQcD2Jy7w2ld3WX9MxCT2urR8NHG+/p47QDBVz6qdEswDPboN25sK1oflz54NxmjIp xPPqZJ74VdZTOXpFb40S9OFS4VKMVF8SFnz0UXaGu4lUwASjxHHFBegDKEN8Nq55zEKDixzTzu7p wWlOACXRgMNDVrrF+kpcbRBTxYDmRAZg4XYlHx/48T98ZdrLTZTFV1fSP6lWsLiKMF3UNnG6HVdA Iodxf9+uW5j2Ied5kWAQ2lIqnYAjJflXLYkWvrYIdXhN7hk3kEx4jLrYSt3sU+5Qs5gMu+glsLH3 778N+xFBF9f9BJRRmXEb8nuChVooVXuV64WUBeM2UTEa3l0603a8E7VCwTTDlNB2RmhXpo0PrDBD 0Yv28DdAj4mY+T2jGjNwc2jy/TRc6k2ODQ6VnV1SC3gWgHT8XT6QQ7JfHVjjGMB56b/S+QBRpBTm xtrsUk15k2Gla0C4byZ6K50m8rmKsKG6AQ8+9WT2Lcym8KIdRIM4RBpdLqXLaazdLOc3TElE6uLh +xsXGiZtCgBXnRIKrkDw+M2La20Pa6T0WofjGcv0PcCFbVlK2E0poNrcOEvl+RKns96B/MFwYtJE ylaE+DuZ4pwMMhGXVsFxwYwpL1xyWmNS4CSIB4X83npk9trxoXbkMPRFX2P/vqo8BFP0NXsIOpMz 9RlYJvseY8P1+TQ4ekYpu3hEjbUHkYvBOXV+55XetzZUuaZ1OYd1X7gQjDkg+TLSXX3DpHBgjVU/ t9B2pd6XR5msRFDyqI6gPoFZeyV7aFU9hlg0JNWkmgVlXjagt2JWjvnIi2jrF42al+tyo945m8qX 0+PenLxeK02XRk6XGPLr88S0FVtUGlByGSAQUs5b4eVrApMI79PUvU0KaAwN/Kw/zJfj14Yi6gzt rjqffiSTroX2SQXvIkwhWDmwxXkDT22zZsokLgTgC3huDvAeEAbx2Ev6PDkAiclvK1mbSFw3BK+k AI0GBLGQa/qVIikipRsQJHZzHzbPdquQhg1sRRIXfkX8n6SOEiyJzjoyaeF5Ajh0323eqty/JsBy 8unlMMVslxeqi8TlKvoOmvXbh7WIfk2Y5Uu8VFBnmHphGT2pHYelHCpSMV4kDeIJiffNEyHxzFeI 6GwI045ozYtxO/fYmterqt+3AzV/sPE41m935of/6Zr7csZHsvb8TBqrLv7dCQ1FnD0DeLVLKoZo wr15oFgJsFzDe3lQ/WReBmzXroM3QjE6q6G/ckr/0/Ka2Uo1Fg9hs4PLPvBFgxPyA+oISDBjXX5a u+5PG0+X9impRIEUMo/BIz/OAJk4st7zEqOxd3BK67NsfMj2uOuIbVR1QffeTpBanH1mQD35ARGy kzM6f5lN2VnrSmSirtCZrSX6FL7iFsdzOYh0LVV7IxSIqY/0aMgYofBTuAPXqFk9HarWesWX2jt0 5xSCjXkiJ0nbc5o8JEoFYI5gC1eaDm3dbkAeYHHtPbZxV5St40t/AoYx4OdxS2vRh5FM6WmXI5l8 lofpR0yrrKmmrcFFI6gxYRDUZTRe5TgESlrFaHVTiNw4KQi5TUDjBfSa6psMm13f/ojHf2tkNM6G xKFI51yRRU+DTz8oOvOYX1AXoVrIdrejzkLIwjFB/qpfgBIY9SD5JhhF/cRlU2iNoN9d7Ba4Yd5o y9KkZgy5ZQgv9d3Ojq/Tjf08g4f766OqjsGU1cExDpsZuXhqoqOH3vMdvMXexHRlNIjpf8bCX8Ni Ucpyp44zDH4SUgoKootXseid/SsJ1/pWZXECsgc3x43AGWwwKe3WIsoUm7MQmH6QYAw6oxyu73MK V2BivAqPEXhkummhM5WusswOAMR5GOwdt9ruNGH9CSqUO/8lnh3KXXpwGzVMY1sRlSdR6hhpGepY OLXnc9dKq3mPh0eVoicaMRqENShApuRL1sZXLpE0l/pFRWOaLYM3c56cINOx8DTsG+evcxbZBDVm WGPPKABP+Oal8judphDxRkfolWSX7J0A73XXhj8+bMd0C7K8LCcU1Sxi2B2YsI/u7v5vN9bPGLS2 ZJrJR//lnN1OV10+GdHrdf2NdQ52mRB/9W82l7OmJ2JfHZjsOq2ObPkgfE30641Xms/HlDERC3Mw YNlvUKNAM3ZgtYVCVAWg4JcPhpsm2AdsnKIH6+PioR8N3L9h4mZFp8cqfTw3b0YRJzxwBlObNYYQ PXGUCWyn22rDa7H8h3JE0UxufksZDVaWLg1uuPrVmjJQMxlMPa6JAnle37j6ZoVr7zb9q0wVaRYv L71reoUKqgv9yiB3EdrEyuDDQyVx5hRBTsaBc1JviPL1zYo1+CPQJOwdkgz3hxwwjHh3w1YmEJ/4 OK2cvDRtqsY/LpRGTYKxJeo5eTvW9U7NVEARqZ1S/mjupX27maUAUFnpZMlb+KYfbuWnZLC5B/Ra UvIruUZkzQlLg3zkm5TwiDF0LW9iU8687CVJgn2Bt2xjqPUNRaw1IfU80XrkDcZ4CzCJFDpaO+nH Y6xS/IbfPLXmd/W2svHOImjU2GkJcyhr4naqmpbe3nZpYbW5mKtyzEjirgQ/E4Jh89oY0qLvAO/Y zr7UnJO80Jvw6QUXE2VdB/C+23aZ9YfONkmxx9fVjszAnIp0XCssPj60vl5LNVoH/E0TO2iRyPb1 TdoZ+VDnXhDanbSxEXlIa2wu4KBax3SdzXJ1y4q2k21+Uv7nfvGjYr6aqugkcrKy+2hdu+UsrxzN KlfElWDWqnujxELFR4QaHe+ofS/MwDksOqPKrTey6KS0A4Y+NHFfvlXabVcKTazglweXBV0MPVoD EE+J7VJEJKXDzEO06KwhOene4cw1HUQvGWZEm83eEigt8K7zgXMA914vOy3/AIfUvfitdkB7vPjo i4jY9KQnpltUeOfwndfkvL5DR+oaX45RQwrn06nMlpeEKpCyutszq6EetiUatYUTcc0NdE82PQLt x96rIACGV78X7b9OigW+Ch5alVjW2QZET0SFN1IoNLDS1PR16FfEL/Hs7mwx6uMdSf/TAXCGJDXv jn0w560mt+monY/xhUm67+2Kfoy+f3UxerqU7Z+IDS45qq1P0MgaENXcKsyVWFWw6nvsp9COcRQr lmWJNEimvT0j/zN7LkJ4S2/UcSoXT9oHP/SPPaCSp8K5a0X5ITtUYDHIPiewaGGwxQjSwvP2tzQI 4yC/yNkja25hLPjMwNlszya4U/v4hDhVpVn9tL7jNFDaDBCfzvK8T/5uz9rTB9unCpqGxzgH9STP pDZhh4UrjH0m91fYQ5b03jptfhoGxA9M7HW64Z4hkd2oCcyNZpULZ/4bGKt1740VjeUUDXzCzMkJ RDqy2fhx4a7BdXp4aiPx4fj7K8FHNn+Vp7eQGj1/jbbfQFDK3H+nG1T0Stg2IpdfHCwYgWcINK5K jp8my14i9dsue19rcf/UOt/NVrRHCgRt2LnpS9s/+KsqY5/9v6V4Y9LE/L31/IUrVvwu6Ay4eatr 5ouCRbH/3IQyg15Iz8JCb+QUP/iFdIJctOruSqrQ6KzNQdSIO97zZJczfS5mgdQKffCeULHM6EdD wTMILJ088xtZaHDVdP2wVmNyr+b5XhAw5T6YRzQTOhmef0U5kEzrmzPjF6j4w8EIEDVC4/QKCVE8 b0XKjpIfzcDCgfec2G9ei48FTaCfK1yOeMnB1FLcscX/p6BNd1ORytHOereNELATk4w0O5eugF37 gfl/IzpEe1rja38vNSOoMN641olOiMTmePVOqnemi05VT7Sj0B6CrfXjkWSpjT+EiaDDcjXnNH/h g6MihRIUcm7X6ZfDIa0ZYbo3A42a1qIlMzG3Wd3qdIxsCouZmMn1gE3f96VZ3Zl6p8u/C8gxn/En Hx4O5zUSBcIeciJ4+4IxDy6sqfYODQA0O3MnknMAdW0u/WqVHA+8DRFmbp1T5TDQ4RaYMTEbfNer 5noKsnObbqngKMHZIuBUq4BHqPF1GJZoN/exUZI68vYEO7er7hqGzuWh3hHfUhnjQa0CgpbFrlqZ qDa33RbHDHy89926xhKVeFSLajfnk1xqagt311SVMoQyGTfiVVPp06DemVJZtFPRLfd+AE8VNvwS b4GWtly0qsUgX7Bf0D4JLVhtTdMT3FPHcYh3oMOMSvF8QKn4K1P5dNZTac4PfmfJHXSyORLymGmB tN+5sjaZcdt4G/I6Phu4JC010QgsztJjM7zy8lF0FikmnlPySEBT3K14yu6G8GJm5vchRkCNJ9PM DV7nqKrmeW3ypa8eUT5Gi0ZlYWjtVQx9N2VhJ2A1qCBYiRG9TnF8/IEb5arGSdV/yqeApaOTY+Yz fpOmxol2teKHmp+bstN8N6tmKCUCBSnnRwyUGtrzXUKI/rLjtNu4A70i2L+f4nXO30K3gea9Bm9x 3SZXVd7UguWY/Mtj/RF00WKbR4TgpC9YepbG/EMowzsLjY52uVL5MQjUIotCIjBNxCvrg2drHFFD 2YAQ6K0lIZvIirmh72gSegGC5mKF0ItwDR9Ie55ARX7upelCoUhANCoI2+snF6+gMDAMij0B1na3 VkMq3OyMuhjyMYvunaAxoapSaKQGXV+ejSTF4l8s9TuzFuXEfyARMwUYpSZgvXVFCi8daNJx/NoN fyYsGx56zkK03I4nRXj/0df9M8d/bIhMOS3FBZNH1hJOxduP8VDTvtsp+I5X496hub4cZJNw8dUY DddRnLe5vI9kW8ghFaSPJ/wrmBuc/ZxeUwgctZWyq5PodUTXbuHgkvxCKr3Ep4h6XfH4jV+I6Msm qChnRmL+tDvLWNJU/NA4MgKu6mTmYyjIly08lPaG8ezekeKiNQHpCiQOAmyWR4vvoXXrNkvpzhmg Gy6tV0wG919VZE/33w3+KZatr8Bz9J6WS0IXqYbdl1Gv3Y3rExehATbhV9zbqW6OAetL/1aC62+n DZw0H0I5hpg2IDGBPeYQTyMTCss9zK8fZRxNDhw4L8ZKEn+o8INuFlIMxFc0Burk/z9HEhvjtKZd 7GsS2wHKt1hMZvMn1vpAZdrXqgdZcpYrWZWk4wGqKCn733NWljkYXGqHnZ29JfH+tA7CkIbKYAVk 1E+07vL5ngrF+GpZMrvAytrp4OSuTGY8yrHfo2WlUIbS3SlN4/JnH97+Hsd4l1owwSiMW1OEZs5T vVTsE0xzk0MXqVavpOUsxD1KbDJr0dhUPOe6Xz6x8AVSyWzUDXNPhIVHR5NnA3Wyeu/C+eM4jQNo +u1AAgXg8WoAkzLRWOj8qf7tTEpRHhfu7mu4ChILLtJvVVSeQivoY/CS4EYCYe5Rnl/5opDrOFWa YSz38TF8MG22imK2NCqjQrqFP2Dyl4jKYPlTDIh1q+BWZHlKcaDQ2IA1CKpHvqsciDIpEb+ZygnK mKU+oFujQTKFaUIjDlZqoUwoFruDCyD4HgEAjJMel56RtgcIWzYRpPbb+DuNZ2BanHe6W7GubMz4 aOE/+fiDB0yinAayjjBQcloSOmy7VhKCIn+7fKEaZ3O/lLNXkf5FzW+uCEeQbzoYDPGSigRrGLMO +wioCwIJEAhkAjilTq7YogKbCtJ58cJuTZv7d+RYy4uVI7NKQo3vfSgMAWF5bWrp45tkIxvoNwHA XQ3eUPZO5Zp3fopGb0doM4a9fHH+DtDdc3H7Q289jxK5ZgdlxsmxCCV/tPZv6lArhk+7mePgvh7F Syr1OulloOXAHUYeMuqbCM9Cu/xUvNmuckCIPaXkm6K5L9g1jvwkJ7/Kwn0Zf4dH5T86qv0EK+8X l5uZjmWAMZzqoFX8sYW+TtjXG/TNmNprvGGaqsR8M+XyIvXyqRLi8fUOr12o0nfQtv9wbYNiua8b aViQkVTRUsfxyqPbQEjW/l1B0qZKJ1NawtYsG5N/nEZOdJGjupzMYA64U6DVwnYGH94qCMhEQXen DZMpTiXcCykd3dfPnDeQ+C2senZNvUsKiYCW/ueyLLp/M5w8p5qMh7bg7dn+9SybF9rPs1WG9nHg Gdn1B0zdmOH+AeMBcC1w7A2jBWjy4QiJyErlG6Oeq0xomijfpXb1CcogMhTfeG1VUYyx1tM/tNBL 7qlgZUxyL/IVj1478z7ZQ3w7GwI191kzUahG5H7fcsVxbtCr18XrsZHmtlfFXpyUE24Ys88qqcGw Gngkx8Sm1vV7wZhKJJNck8wG7SznIRb178MJrHOD9HCj6c3VVgq4vM0798gORx7Tt3y66rIey9L0 BNTxtelBmHdQoL7enMf9xL19P8fNMSrJUYKZo1qKsmJlbeL5DJTMBWHnfFj2KHfdql6qj41HxEqe wLDaOmxkajcEMBUhOwZjsAXm9DKw5G5qqq338Kh/MJp5NBrrMIoLEJJaSNJ403GLNWAMh+K6ZZKx II6jtI8eE9SLZ3P9l/gHOxkk7pHdjzYpikk25wKbMAUePrus6kfnrYI8l8y81GxPbNfTSMSVJEod 7JxMUrkOyDgslYuwJTb1CZRGk8Z7XFHH8UUjI3AXbr5YnRD0NbMdotkFW95Cfrtj3cgF2K0xDaQU L+C8zcPBGk7qBi0PFuVxUU66KOMGbQyIm01aomobVaSG9EXIH3yuV90Bw4mFznRag7pP0xFkpj8X CB3lbCbVrMo8Xh4nqMi3I5PXujQl6eddyHy86QeXzOB9iPlVXLb0cbmVA2QwZgEeocQxmckWHM+H T0xqn4iEg0nZP8PaEvR+fuckgDSUu33PzVn1dImlf1FJJ84S2gkeQN30RKNBXFqK0GNwlo8iyHVx kboKHIHCX4U9KsLQrA2dZPx0kQFhrMDdLn27SYW41KIBZg/wQ3kIdpexcL1omO6K7vSn/zjaMw1/ i8PcRnANjMqmh7PNl7GKiLeuMswompPkzoBjd1j1/YY2Df61tNx3LTwNnPLpqyyk3d6OZl8O3yM1 OJxpLv6sRVjFoX4sABhl2vht9dSvwCM45rAGM+XgfGslwDnSmbxCNfVCfRhvAPrtIAHVCVbOq272 ie2jfu2IC2cBeTRHjz9HZg2Dc2TP41EXCmQ5l5U3Kmjny2frUTnNnJ7uHxON0zOXh5EE0urLES56 hL2yfyjOcJRAA8K5CzVAVot/ZmNP85O+SAxI4WwLJuy4YYdDT+8Lmf+LYbZCLggeR1VXJaIxbfqN XVMbrPVkxBxt+H+/j+cAbPpWj/FyzQrnVfZArywvNApbPPynifazyG9b+IQ7u1RXsDkWhRJ17cZg bJJX6sTjk/JA1S9btwTTCLHzInk8folCjXqCMmm36yebRrd9nXyBlJ9XrmHN9k8E6hlpx87uLsfQ kk4tVgzpHjfo3MYOk067nQE/kxx1GLjWAVUcBZR2Ah3QLsWKJBwzTEfdVSObFvveUs2a/A6NXVvh Tx4W+dETkbeoCIQjOrQHF/AlQi3tVnHM5vRepWl1LIXbEg+MHwEbLBJqf1yTjCKV3MXBlndz5h/d BPKngbyHCMz4aaLvpqjO12U3hcr+PDu7GkXcdpA5Z4bPNnA7wIPzt+Vj9JukjeDvMN5c4Tk+ww8t vkDSnhrWX/031229tqxHC3cwzEe+0+I0erDhFPt6pO+OgDwKsf51LBllQLVaLCcNFnwBOZf4/aqd Bn1JL6+aWdz1dbr+2s/7M/R/iS262qm+gHeQfWk1iyRkgxuDkefhl0Y64yZj8GlU3BGAXKnLB7FZ q805uxnEnS7ecsySU2ZE2N+hxYWwGdxxqicr+Psd9XvTzaC2Ehg1I1VWuOziNWJhup2NoZZ6VXPt dKKzCXPgsdfLNgiZJy1yoR5z9Nllmk1xvQbHGzLPA5MYXzh5JG7tHGSHRlQ/5vS4p8Fr6DH97yyL GyMofQgsZKrbfKfkVBFfQi3eIMeUAQH6p+GBbdMEffLN6fG9YE7znTc/ATWtGaOfFBDqEX4ZUdAh oal+OKbQ7ds+Yv0cSBTAZdC9Mm1Jjmmx4xYFkcr4DkADUW//vHUOD1/JOZHhxzq7vgI0/92LqVvS H3j7C1pV8h748mRp1sSHtgzfa5fqVNsQP/VIUxFsk19bHRmmHIgu1XelFuLuFg1lisOKXeNf3Ne7 4wegZITvqrZHJhj6mgjWZUlBkUMKEHjr/eWXrnpbjgi86mx5nHifEwu+F1kTYuUayxqWzJ2DH6up 9YUKxzB80FdBPh28qzzbXasLyR3X3CEEDehx/62+2Cpny4iBguHzEJI4KCgqk52Fb+gZ8PQcZPLe waRejWucwExgzDc8N/4Rhkj2qqbWjKoTXkbWJsyh4moabCssX52GcdbTzYiZY6so4lRWRj3Yl/iQ tQxspuqJBgJ929nD4QY+nshjBLk1oCqWCOY6i39lVX6p+pi6coQBOreBqzQD4JNlqs1S+x51vIgl BwDp3785T95RvhBHW0tXCpJAFSH9HKWhp6PnHKCSUXIVqKopkX5IAgG9GAnjEGqX4g2uL0NcHJ9a Ujo7+6/fLD05UAYX1XWhhTx1ABHdWLID8sycd5o4NrpojaOEMcY7oduGSNgY0o6M6tMcL9U7XOfw /6cH3IYiZMNk1PmmgfYARcoDhmjBJDlXvtBVSa8JUDsFRonpZCF5yr5QzK1GyGCnd8f2t7cvUVOI UcKFuu9JYi0MIlkEzOw/8jZK9YE6Dw68h5c6+z4X/D9DZ1uoFOVUjHbKhHf8QEGdSNMEsKh1QGMu 0io2QeSeIn8dU3rW6r9sSCgcnz24xEnKgckaXAKoYjyLoer3jx4m9wVYLg9DgcB4oLxSz1YrHSE4 C4083ZuvT72jkqXu99RmJqc4KmX0Q0qAiKVPvYalU64HMAZ2NDGOwKTpx+WWdH3p8/Ys24EU/ZC2 h8T82wah1hj1pcDEeLwd9G5W7gNOl8p2fuu5eRXeb8d/SzZ5OWRXP/bw/tDwIiWBOW4myZeTFgA4 15wAMLgtfq9lGIh9zTtTIN0Mmx57phIZnhbzg553jBNVXgIkv8IrcFUB574aqFQK0axOzVfYAks6 4WHbVgzi2d4t2vqkgpLnlggV057Q1YLbcXPkyw+clhUNuG8GZY3jidIk94tQkLxaBTLNRw5Y5QSV penNgY9RhzEAZSi0qbhJCH7DK/0WQRsioS7dWLdGQS6YZSov4jnVfXYezzY6B6IUTxb4kID3OGFw uiHyvzSX56A4wLJMXfV8H9exax3O48f7l4eQ3gaOr6l+0SQAu/691zLHvO4WKENK58jTjdabIgWM 7VI0DbuXQJeNPwvSq7ncT0Fzde7ZDFanEdigsmhQReuCSfbCTjN3mgX2QVjOakWJZBMJbVrzVDW+ s/8JkQ+O+Ht0v1+COATWGLcXq7JxBfxkxY54eNIZFZdN1AsLzsX6HU2Vt5pPhHAh39DixAxmjL+F 9N7phsF1dFibloXTHUjc9cgR2zrMK62/xc5hKs0LxsA8wLAsPY0xAg8JgSMRcI+LugNQE4cc9ssx uM5NWO7aGyTX2QoG4YPYsDn/ILM4V+m4c0LoDiyffn2lqX6oezuW0vnMsWKskv3mn9xShWl8G45E eHGjfA8HVIk3/EUOKr5UQCssa5HrC1PRSIDnbZeBpLxxpAObsl2TvIpPEqHGafDr4Vez/vGOPqyH x8CgALR3WhnJj88F+AdDHEp+T1Ot43CND43xl6jRcYWccxddUEpXuwmSwYot5nJ0cc46qqrFkJqM PZst7iksPk2XO1xustMjVLWZ28Bov1wLEqYhGUMi85QpQEAfKNockFi+4hwNf6KirFQJYfzwJCiW o2KpmTlZAV/7edLLTX2q3hQdp0rQk8gTiZXwer8NUk/QE4cc57neyrSCYUXB/LpOmZ9UH80YCwAW SQAnHm4KWFkp/eGtzzKY2UGPR2Q8Sn0yZ6u+5+oTG1Acmo/ZjJkRMEqfQOzUc+Xcl5N2xP0HbRcW aPPXirwaa1v5e4sSk2OmMnAGwnkjdf4RJgSxFpQOuWzKnOJCyVaLpFESK5ArHtwM6bueekZ7Lrah wFQeYy6OtCgUcE5LtqncT6EMxhjGq+zPPNDnCvE2nPRIZq3KSBvWdKzFL2kKBFWfPjmSlIrcRww3 K9O3wLH53oov9hRclLZjiGLB8AYQRntTab2tpQkP1yzLhzb3WcXXKbhdZ0lJ61uqQ4vnsIdo1ZH3 99Ynonr/EvcYWtoUwFNtF+4cw8q7TEvAwntE/5nOcYsVKXHmI29Z/xwYEXsv+6gLIVDnVe4SfkYH tXCU+dfR2lYxvQogPP27ARYhTBLYDwtsIG4iNbxBPr+rRWo3JpYPGV6Z5z4I6dvXJT0Pzz2L9Z8E xrxkSTQ0otMHYE7LqYKKjGRIusB2ScMYhl/Ipo9THhYE+NIOaLAA4g1ewdhpFsRJmZAHqvJkMLr1 Ji8yqtJuf9ETv4N31KygW6O4jK52OwSt+ttf/uO7nNRDKeM6eUefJgjPsKB/t4W7GJnjr6by/Hoc OzWerzfBdwY0P/UnS/oMSWr2eeEaEJGBx2/ljhA6RFVa1hCNmZfVC+iD81Y4BmhpG0yDtDqkxys/ IvRnIvVWMwB4smgGYwImtdqVrreOjgpFsbxBzOwvdJAw0r/bNxfg8++blQdx8koluAa+/tJPaOqJ 9yzaFZKz0ad5ru5k5uhsKwIrwouztkcLuNBK21LSQhyacAvb5YJZix4Ope1o8CLXVpob619mCBG/ eZB4kuPpJ5XZQcTYJ9fLLd2IZRO1qu9bpV3FpflGgZPKZmFRk6BalKgYvRAXrak56xXpUVu6mMz3 aQ6ymunSFGsr48jCfiWAy0Oo5fjKHv330Fqfzw0xSJBbZ0QPtu2TEPUfJk43JTd57ahq7zqhdU+g B/0IzZu65p9s2/pBo9Ux6DojZxyXLVzAuKHdYNUs6BosHv/oohRY0ipyor/ekWP53bXctzqtRUDo hnMaLxpXJHU+nRYhZC8+6rZI2UF+KGxLXEaQhYj27bCdf7Rgn1trgUJ24KZvdAbuRQCS1btbQim6 7IP5LX2g8LXYLEbFeR3XJb0SaUyvtC63Lwv+vCvB5HjT9NpKGLpSt6v6CUI/xNzYmUZIiuPugpWL 11mYBR/LkYDK0kqAdnEyUmu9ZjI9O8rcGdJGKU/IbUqYfvX21Lvywkk83ETRn5QLC/qP2tdHN3Iz dS7Sh/vZepSQb0m9np94oNHK3HEv8iKpcyz26jghTw95UNxJQncUGijkb+yoqSUj0swzV0LJd50+ eDOMJpP0FgAw6UDP1dP089IMEZuQe456Gs8tbhbwdUO7BpZXJc6yQZ8GBLKFDI4TN5QVCgnq6C8v 98cmxCwA0cEct9WZQEH7d8t56t7VXsIin0jR9bsIWYzuoZMtkaUXZevdaAWWQMkIlrlJI6Ri8U/m 0b94kiLOMw4tl6viGy1jJ0OAgZmIRbh3AUN6jRpKBvoNLZIW4hRbCZLlttvbtssUkgmgao/Mr7Q6 i/Kv50pfbEBDiB1Kx0E5z07OeJNxOgbFss4mBLEKg+kPUpymziRxHXQp9iRkvBRzV4mXtFtK8Vda OX2ngpNbSYDhC8KXrLZxldFgimr1LGH9sjcwEwlzWvahoJuXHU1lUq9nKv+RTdtHYRbjRHb27Di3 NbvhGZjQIIRWfaXOyzxn18uQ0LEcfn2Kg9RObHmAcqVWnPOQ/P9Hb1wQz+SzCxMJVEIb9dvbKODn BLg/oqEQYee/u0LYJ/Ndw4FWJX3BynqQCctVb4RFghHzDkhUiyToapRtuyCsx1EtODS8xFKpKJzN /EWvY9noVBwmgA8Zpcln5n/aInh+qJ9So2d4vWWt9D6kN9AboWS/ILEyG9xGzrNeELwEk8j3aztd IwnWETCtZ75t6jDcu+hyIZ7IlZ4pRlc6zgQ7xMClFKoYCmhsZxTo+eJ23YWcT2ichnnoMwl9oRYT ZG7j6rVTSYwFaVPS7x7qU4gc11Dv3CJXhslwI9t4OMQRkFoJ26LEoacYA5OF9TsAe4Ny+sm19H6N /TmbKZzuxDeThoCSbSxOyxKhFROYHFseteGnH1G3pPTHU8KGWHqCtttIxHpi4pbLJ2enpRqXXhsn m2fJEpqVZoSwxivXuqvGWiAPxv5Thlcr3PHfzHXmVEAS3sj3hNkaBcfUgiZMr74CQujhseTqRaBT 8YO7nP9rB9RbqoMITcW9l6fLDlbpR+UsKk9Klrw0IxOSMJjiwVkMR8172CuPj396j6Jkhv/wsYu7 uKwGed+uKVHjeisDopm9+sCsK1aPFo+u/CI7yPGAV4Vo5ASzQ+P5e58f05LU0EPTF2c0MAaWAEe0 oXAh0AzcC1x6PxBrFOf9ymVAFBjRcUK8HL9LoQJmT4hPsL/D5C02t2+CK7vTi8VtGwoaQ42AsEV3 ug4UvRBrhUNRdv8fE9c07HydmUCrU51jFskfVIzWsovCvSiZJnKZmAMUwPupSrKxCh3H7zg2zMu2 MUge8u5UWs65db0PURju2ejhYwKscyhjCMM7yZJMPgrSnIWhXRmSJW4hsPof4oww73OI/+/V9sqH ERxIiKN5MWMaYR7pJ+Oy4jo51B/yQdz7a0eyb/8kshVdtzQ76hCbyZ5Hz7cIOQUX/ZBlpsu1Gaxy DtwrqXcmDKDCm2oVgCjzWBzpVKJGSi+Pb3ZIYfu4ULmBQYR3fwJTVs+Kvtxy+bxu0fveapTLgUOV NWL/9mEYRKg4TAVmSEMeDu37zYVmBz9jo+6tNeLGuomoLwyQ5djs5EVgLScFo6kq7fSW4c5zpKxb HfsXrHEffdx88s2HgtKU33ETjTgWoZ6JCjebzsk40BsoPLDAX90jx5QqHVsSBWP0BrvZKfj7EJrs DE13xUaHDNoo+98wEaNfylIX5zQyja4c7Rga1O/hkTIraeEPGbOjotfCuWAhC3hjzdqLMNYHz/Vr SIfihemJ6wTWxVKYs903wlhy2DkOymB6ic6j4mCyLoNvt0niMEFHs+qg6v9UStPINpE8IKH/GAJu hYMNcGIET8OxN7uWj9yoCKI3JVdeZwdiSWiiZz7BkhLM5nMSLuTATO9DSKTNLTAU0/JdPY+lgeeF atOqFIi48XEEdU5R+LMiY+4rjTKV/F6SRV7TdMTOkc1GhE6laW1SmEdZhN/eRnO5A63SOKgH8bpj jnT2VhEXE+pJd+MRO3eYfHT/+LG8Ge9om9t6OoKTvDnY1XiJOF2Bydf001pKPQG/Yn5QZr+bsZf6 qXbzvIGMFnN+e0/BWwroVgEq076hqqiN5eroFAnaZfJaSW1KZhrfUY/8++E5FXOLKDEbmrSceJAC E6hcXWNmu+EH83u5t+3w78iod/haNSeFj236o6C4H4bZX/wZaTXzTHXNn6HZaBXMFGbClRk5OYQy tfvORDBdoDEeXYsJRlRK0uDGAj7W8SSQYrvYblvyk4V/7tQkf4JvaeKgy66ED23V+VBaeu7r984M SyuWOBSaPyVug19MaXL2IWwvFLI2cZHQxRwat8ttdmdRm+TI9b8R/hUFR3VhUFsnARETJGjFT9R5 kM4+I/GO/GooV0tdIgscLpPffFThXHlv4ivhyzkVtV5v//J2J4gNqsJ3JV0/W5lY4sYl9eIBzojK a9rZrmPBttrNGFzFF68I7TLEqGjWsNqYOaxkq1uVEOgzJLv2d1bcaHGIwQS8EqOTQDPQTIWqLHJB X7hsK/od8AMlB1kIye3zrdY1UTmB1Z09ZH/zghznxa8Aa509fzH1YDBNI34HUmx4u2lnbyNhxrSJ By668lGX8M6XUtlRQaXrOB3FSAAfCtKaYU0WAS1qPDQ9dl0chiNwsFDeYLldoCBlB/2XacD6oAg5 R5d8AgcaJ1JO/72h6pOAoGnZ0FyAEeTT2DBC7PIDXpCPQzcKjbt329bNxSab9FuCmBuA0zreZYPi TMuAwjHRpNl5wenttj1wVJCqWSrJ2+ztu4qlq6VOvYwi4KeqHpPxM3kQ1UkcTuN6McT5ocwNYwSJ dkEvzPFAGM0lp9j1j0axhUDDCHZzN1cBT9CE8lQz5zcoNsNOM5bhokjO9SGDiWHrCZ78qqwGMHIK wLXL72F7mW3iDiOqeqgCalnHCWuYViGuMnWZBd09VCjnir5/Rgk4I1h8zmxWg1tCzpykee0L5AkH nnh4LLubUnxAfpsSx9K2Xrxg5MSNmPRsekpeF+t1Tm1/M5Pu9RTu9OzkK9DGgmGUoOfNSf/z1N0R T/6VjbUXmooxQFv+GKQoee8GpHC75tliHuj017MAFM0y5dmJFZLVATwzkRBtsHzn6A1+pzgK2bBP FjF5MeHkv7385zF7LtZ3wQi7oMcL2zkRnEbH/Yp0sNUf1k44f3/MzpmH7xKjBuhqysspxfG2f/Er j84osFdw+PapltRadvU8/n3Zu0YYT2aj9Kr8Qc8odFjOJoG/s82v6wO64YeB4AmeWjMi6ZHMr5x8 28kGWyXghLMBlRoEBFXZGDGbaZT9MoxP9PMXNoIZPs+loTHWzqyxepjzGyP0nnSsbyjc+VWwUm+C Iox0e+gxybukao2sPXOwI1HiQ7IJacbd/sm6ZiXiHNid9yfZpZamMeEQY/Qo9nMACyygsn5HBby/ ONKIISQg5nVam74jojAv7yybgQhHPtVDn3E5nevQRoaIuk7UWZ1rp03cxpsYTy6SQ0S6ewznyOf/ 2EjkQbbyvCJNKqXnbuHt5p6hnbKTFUInqS6lLd5O9v1M1QV4h4XPF9mmJkbCxnwVO3P8aACxMSca fw/CJUHmXEGXPXExXawm+nBxioNVZlw5PpxCC9mCpaD7hSmMMI+G5ixqIxEym61eMDP7xbLqMj2n 0reu0GWKlFLFHcfF1yKJBm8WZU899VGjSxrFNRbhv9FWQCqRB3bs4d7wJI9lzrwk5AJJroc/nsNj TvMyewJfu9Pyj68OPLbJ9MXFRlCrpgyTK7gP5HV8SWpejDPrLCpB4WVeQ3am1rtGGjy8urmk6yZ4 11zdr3/umz5E89p4omgZ6sBouLf8bUg+I6EZT1UnCvqnzH90PJB2AYRz/aWWpIbDeqfr2aVYdiL/ AZ0ZjqAUJDmKr3R6O+bhT5GurfO6luDxjAsTiY8ms6Qs8R5+W8SwnuBcXevGKbLEyjce4lBVvamR W9VOdk4eOwMaZzT8LNmwhRIIdTtsOPqIoQjAJpz8n+9Jhw5mJt1MmddCwGRXU6ODaLyw5bzVk7ti MMb00TdTtNvDMdsbUoa/CO62AO8Fr1ev+GMpWga3gPOaP2mv7mVGydPcDodiTLkVwnfppwPRYqfQ GiGQhMiaNFdNsIMikBS08H/GzxWhJiPsjdcNlE/TWV5ex1hctxrMWfC7iBsRx5O8cTT8gftIfvvd VWn0tb+/oHid/5rhjPl7dYNg2tShe6n55+SB5XMR4yNUYrEM6VUG5ZSxURxvs1qwfNa2i0kHMCuo cGa+xffrccQUKJ98nzXCy7PsCXS7OHliuSfRcWo1esJjUGyDEPZkmrPh8Sv390d14OysA6uk2QO5 rcM4TvfgXITDBQ+1if41RdbzbBN/BlrTMbFAZSdv9yshmWpCIfuSgW71cR9kN+EuOyvC3KTUvE/f GQ5cb7EK8dl3d1DAk/Qj6naIPzb9JLlCPYYHMWG/IeZ+iAHHEkShnRrSZnxgwjfNvFgpikgd1Xx9 s9qKv42UzSPjhi7AkRe3XhKz2nLSNOJDZDVrHBd16dPLJDAAjR2mwiVKoqHOg6nxLBElXAUN4hBm 8faqMUpWNJCucGPMcPCS7RPui9PXjuMSG7vZ0Se8KnQ6TFxSKCP6RSld2rHc9oP4ILW5PaIIrx0Z l8OXvquUrj5Rztllkt3cq2NzLr7PaxhEUPSES2P6WZJgd472TGyvisIEJc5SImLgyVUoZNOwVmYw 45qVDmdc8Nj9zXbMnRymxjRjM/0I85xXF017pg5lfj5hB5Ws3BoCukpfgm0EDrZzBFK2jzp1HB8q IMgFlkOGqF54ARlQOZ+dVUwS9gkWDMFRP3PVL0cuk/aSfsON2fewMNb4OVdFoLFpjjxbksgBHRr5 qd70n5YuFSw7kC7rTrutL3xwwQcKPuqAVltK7jbmRsSt6HBr7ayFKdnWiDoKi+C2krEPGr0znn4E kVC5ImSeFw8b/yV09V52W+PuxGr871folIts9v424t5zRXZPM/7/LTcuBq6WvFadVAzvzWjfc73w T8wbl64g9QKd9uDx98hDBknJWiJQZacw3U21trYLh//F6LW74IShcADbk2duLB4eDIDf2Umacu+G mNH+dqE4GzJ4X/kIo+d1m9MZu8/ZO2TKh+jcSCQj7Bd3wZpekpMstESGqkiaART6NkBuINnxNokR f0AzumtgSY/G1gtidZSfm6wEuvCIrzkm+1KDQd6/f1/tcEeXGog3RWA8oktiVXjjDIBHr1BgTaEC WX5Skm5Q5G/hAwDQj4gMaV+lpj1infleQFX7jAyfZ9DQ9YIE40E6ORLUmLIlzMRccqfzTu1nLegt 6YSvrUiWo7S7FTX8dhNotZinxJWZ0HAL8jwLfWU0tcZaD4WLLifKdBV65+evNPyMDbhkqiRTVA91 n8rBxpkLU8jk1op8NKVi1G671GJo2ThbbV0IuR76Ql6BY3c6tjaVhdkxynij2t5q4WUjAChIrH8W Qz/wH9eRthib4TKbKXARDS7x1OvS1YcrC4RS2JOCSlOhINHYDXRqX4mGAxRyhcLoVF8v9qQycEVO yQTZFNyxmKzUucN0aOb45iN99iQo4BX16OZCg5WIGXINJQOmPACm9l52EqANjS/76L2UM9w2Vz57 oKBnmPT9LsoP+IduvpduJ4Z2f1ireZ13C+dR1aA/v2ZFE6j0/3PTz7rQtvoS0eW90HiyDj+cZM1C 22wa/nd2vVhu9B0lM3+XEfZNy+tA7oaCV9HiEuB263mNeYdD5jmX7n5Bax+mfwrIsJO47z8Wsum3 AH+Ia80b8lB01YZyao/1POPgWHPVeCFwLKiUTn8EbWVzc7FrBwh74Azac2rUwW7ViGjnvy//zYMB ysgJOvdL41joiAmw5VyMmoLop1tRDGHQpsiuXgvb6YaQPYkIG0PQyVF9jxAkjaEpZd1zUkD5EV6U j+A1kXnnp1CgNkwiG/PAfR5GhcG5Xd0xQXwJlq9zhtHXa0xbaRYHDw6i/po+X6AmiDKJby3FSM4U iwtsWhZGws+uotLbWzu+Empp+JStNXuVD5NH29bn74IG6rBfV0sfQ+DO/5GBESsgl0lCrMPlyju2 O69oXpkvBafz+7RAJRkQzp3NF6zb1OplORsCsiAs/JaO9yAKwhy5eZVvj61Ll6rByBc9gXIg8H/p 3HGsLHFawAvbjVDWOJW7kXenmUeGrLQGfAqyZhYwNdiGq3sCwxFzzY7aDYqgP6oqNKHrySjaxb9/ ew+Ptfeop2QbVYrFu6OglGHNLZExEoCXbJ6Ei5OClp8cdhylihlbhf3lZSpl0jOMcXGVztl+3LNu zUIiml3dgaY77hd1nfzWTQCIb3ESNSDrCBgKsQ1tBYoBKaGkoG2ZlfWwoumfZpIA4vRB1S8/XFx/ 5zXi2I3wKdXaufK0JYjsARkAgtASsGuk1Mby+HdD1IEWNq+gKNu2gGdUXeULQ2woZlfMTfcWkSg8 GnflD6ITLBN6/vGdvJUkLacxTp6C/5k5/gT5gDZKZSi4yhGtzDH7lstL1clr9kDTcSKDpUXZMNX8 XsKz+pXWiCBLmqhsFGo0aKYVaAep2BeE4Mkl0wnoKahKY5JwcGoGUkE3tA6KJ+uZnXLFfz5MHkZc 6PCvE66/sIaOYQ0Wwo7qT5nItMzty9ya9HM0K/T5gadZXnkzwtL13+xHGz+Z2xD+Hi+3gaxgttaP J96aAFFQCxvYV+XS896Dq6661Gy3P67x1kLjjUBRsW8ky7FHfrx389SdsA28GCvd5w7FU9vvUP1t p5FvvuFi0i82MX8sOJGUr2xijnDqmcjYQ1xsIu2IyC8DMYetgrCRZZo8HiBdc5OS8ZZSYoNtzvtb M3ruUKA4hzcDXGaXhupA2J3sFiPhatz8Ze8+yS2vL+97q+M8tsMuZ2qInVLusmOQnkMUPsYDsjSm x0qGETGAcMrqFWiuDgSAZ/ShgcBSxG6vHYc9RVwuyQ8y/Zgjb0+LhYejj+CHvDtYku34ctFWTa7L PeW/l/LWQPAuJlXlmPDkHtg3qvfRGKPH4K9mI+F4cU1GvlsKYNwJb0eybjLUqMtjbvi4/2q9GyIq t6GMC6cH9owkIYsqyFVGFTBkTHq683jW/EjatHTHyYjCLHIH6gOuAYTRmueOYyQ+QpiZlXjtgsMx DcCWkTGHvs1H+nD/OExwAKwcRnR8qNU0A//9Yqzl+l/9NCsvq3tDiw7vGf12iQE9kPkP6ze5Lg2C XPyHbyTaRQGYKwJaz8dn+SGrbDccciHJzKRZDMEoAuYpWH64JosdXjGuClYJ612yOv73XVpafOpf NxC9SIZweIEpISIg+PK++NnLT/i76VQp5XZFGbdTOmsi3AHuhCa15ppspLLh6kNqRBQKoQou1EAX YgKOsNRrk7CdB4D1OVkQ35/eD7LLyvGDJIsWBdPmNJqbWc9cb/zBBJgNyNzrnCBjavdUlyGB1nhw ifSbBHFy55cTyEFAqFAO9NP9SPAT2cZrKInwpAr91UjM0y1PXOtNXlaPig1wmCRm/hFYzMus3AXU y2kYufcDsYzaNe6ua88oreU0FVanfntJerUXURhyY5t41sICJYYXR4lSNyTIXFekEE19j37kAJtw WLWof+LFf5ZApQuLoZQzVOtc/9/HA0asYKTv/H/T74ie8NR4DZbqQpK+MRIZ8uN/0nws0LhzTo/c TojJ1JpnjX226bh5nKrmZ/scWqPd7R0x4XCSgdVTKLg8z48wq55ffm15191bj8kMWTJ5T/QuE9qO 0Qv8snoFkhqrUvGMxH8V5tsTh6L6OJqbpY23FyNB59zhsu40Eu3yLjDqKBWAQ/C+0PTLZJt2UAAM VHTMYS3dyqli4oHSO6DA6UnDf2GoFcwwKGr1lWtgdgVtRjSH45WJZ08r3O9wKJurIjshrNgzIoJZ 3eYeo1pCX7gdOnjmvdUdBZV+H+Yu9aQpDTnQ9xtovz1Mc4R83Ed4sEXrbgDJq54vlPBRsmpogDJq 8y3lk6+j7gPYbjKFIWF+qayhIxqX6xcXn8qFZ+wKrFtEra4E7k6yBvjBJESttROH1QKu2z3JR9st 3GM9pSnJtZwrH9vixBgrGA9AcQrR4bzEOJDGjmh+4UwHD7i/DNLXEzbs69d3lJjXmXutpdHajPqb bKSZRbXVptAudHp0MbvMfItduu4rqAmDn3N1csIpJHNf/g3rSEEh9QiX2HzzloKxHsXuR5hLEvuw fhRjTxcfRAKoGAFhXxSubn6YJyrCmme8uYBa9YGNfFXpAJnYa2AC0b9prrJQKiyadgWPJ2RKP3c2 ipYlqlWCzI+fBXL4R+aLzCKT4hZv6wMOuCgd90ns2PyQQ9Dd08RK+VCPFGqdhadCSVRBkcMDO2Mx fEL6ewe6AGbacCC2THKqSi6Hb/91tYcN/fQ8GMDjuHoKc6qW9UbEXaXEph8rxAdFMui4JsDiTEDp UvMwSWgBx7jp+4C9XqOPlQN3GSHepfaXC2uBt49LV20vMxhWFnMVP0rgf2Sq59/FVubjIvk5IN49 9sx2EjAfqwlUFK7DssJkD/eTTpZ+8gwF6mWMXUIsPuUtp49qXjMOlLOeeu7u9t9Z/M4LKi1DRU4e baHQnFy/cK35Xr8hGY90r8p0IGJFpVyc1ZbUS034bC2EZZye8iJ+O/yi9qtjNqw2aJ8ZEsVVFi1v 4Ns5yE9bZKwJdaJP/e46We4nMBmxdJIGu/C9CkO9sffrD1z3c1KoS1kEPV/1wv5SQ5qS8OObTGXb FznP+/TGjOkTYZNGZBB5VMwXF3hraN686FO0toiYRf1gDMSc1E8bv3ztHJbK9By8ZoYs3BAqQtOG tTJ/J8Mp+rxDYKt9TLhmhhOqZdDDzhIa0L6WRwgYFzd+DGTZfxwG3QYYCgIDqRb3aZrws+Q7rb1a KdoraTkSPkYwUeWi+CfOHneO+mj1NeKVtEce4C6y9XEEAMCYW63v2n+R/I8IUq4keG+6upwgOgk6 HAwVRA0+UkSUbTGEG4/TxU/k+BKyK1A2WezeQ3WHv5a+5rJF7SyGWa+TVRZ4NjrP2ZKKbxuaSfwP r7Qky+hHofAjVmSUqBFRweyfLR1OYefPJLuy2Pj8UUgH+wHjv6uFMFDH0t7GbyhKaTv9XQ6lLuRK N3vyBDfrSB+jBZIxkkYlKrnU2vA5hDRDkrFO2LDZnkJiRgfBAdRSPcRD/KqAqONedm5i7yHO1XfJ p/QF4P3untOjKwQNKXPR7yoBQxWqg6qUZL+Q/jJ7BeEGN6bh8oCK1YFeHjX6b9vejTG6Fk8gSI16 n+rT1E+GKxbDIY8a+tN+9KD7BakNl5JzBz1YZYPGx/qH1RwfPbuzF+4jmLWzA3LjuSx+ox8y4DoH 8HcLnwIIf3q5Yn6S6BR58sUC6c8/2dmZc5hDqwnOHGYkO18z+ZcfKtak3bfsacrJcHEHU0No+88j W2eyS2Iz1hv83Lae8D5l2T1JnICZcpFqu6pXxJFCNuOZhT5MBo06ijrHeMrxY+8595PvmexLjQRL 5j4RRZqUON/kMhrL94JOk4pcu5fOvgaaDalx30iwj5XL6TBe6TfFMSl0OYVs0tQvCWCfL0ULEagg QVlZzEdqmgv/2BTuUAKm023HnkxBMMjYQOqVyYH3IINe29wdtx9LaMuKKsMuKwVDIR9vWQd9Ccwt OIAyR0chLM8EqGCvecKj5yhZGWY2rcaEpXm3P+TZ/89YwaNkZjI3R5z0rXp9xPdmx/lMAqWGxiqK n1eT4ckPUV88/jn3jCHaZdCWeq0rgkT0TZpcbTf56MSVLi+YeA/iJ7ZohxzOOP77U1lXxIosUObe NnKSiVH2DaGH0uOdsYisSfCyVX1ZM7UEKLno0cu+Wdc82LObEuXU216jRWrsKVOb78YwWhdLDPTk D4aa708xU3OdvDRAQRheVPPBlX8g3sExTnJEsOI6DMgNqZ2bAa2cYsKQRwme9kFaKIQAR20GPDBg 1uHH5tm0inVLdelDysbDwteJgAiNIevNrjjAP4vimDOyQuAQ7kgV2pPpyVn8jj87nHE7PvGqbFkA WVoywOtd/7YaF/LNQ5JwXzUz0qZ9N2ACPWNnafBNdJHJtCI85xo6pTunQGMojutx5PEKN0+SfjWf +YrWmlu4hwuyetWvsk+oSHLa1zP8IccHnX1QlxT/hLtrD35kQ2T+nk+176X8RjeUJP6UkfZCKrIn ZjUu4PxZgamGGsIhVvHH4r1ePdhYWHdOUmGi8TqI3YtwXGGOzQv152mblOyNdFS4aDwAZcunODfv YGo+KYdsNq0HxAaBCny4RSjGReUj6bHy2YSlXvTmxrY1qJEovDU7QoSNbOnG3z/kNQqeaigVxMct gz4nkskpf+R4j6wDtQaistKWsOQJmmCLKGQ3KqEEFSE5t7ftFmOe3HLJh4ePAoOnrSy0hWI4dc5J 7gx1sIAMDdEEm+4wmHLJBLDxQeZmrA6pPLaefXQbkg/OC7ZDaXxJnCy+kk+ydY7bOigKx41VJXiT AQoQlwIEiDZJAQg1IjWNPH2lO+tG01ruwlS86IZuo0njiEhorHaz4xvJnCOdbuhzksyBUgHU9AXq QzjIkwrmdI4fz18QIKSZeI2+wwBoGPOirztLzIvr19pLiYtZH1iVImICIRzEuQdbhKH2/5Cvekpn UmTwcOux7KM9ondP6/XuwGrR1XqBwOxdIiqr6Xk/f8WTQYZotj/1BHB1Rg5cVfUDhx3qp/+9M4aH FlWmr6TQnfZTLN9EAisTbj2Ts19XJ0ENOTKO9ueQLMOFtE/ZyTcm/Rpo4NW9+JTGxXpeMWqh6OGE m5tEueTIDvzRzL5KYnqdus2nbzFtKvduTvA8Va5MGn+nIrqfdDuS9O2U+JPuME7MaHRHHqRK1gBq tn69MrOfHfSXcP57Ksz+75QTZ8x3xVefUiO2EmDN8RX4J5vUjEo1nLIIB8Mpccz+F/ztvvsjDr/u 3CcoRYaidJEI6widVMmQ+5w9CcYoOUzcyj+jsopCLePUHHzL1JahPFq6bUsHwF7ARtGFSflyfqu4 bnVTD4LkMbVHhMJxjHjXuxI0ZH+x6Rq/OZSSI9pTg5WxHxc71lWAs7Hjq8RsY6pPGYMjM3XMuiza J4BHdIsNz95BoUFKAfrJcUCgE99FlWTqjLiogWu4Z7J9fLuJpgw9UUsmM0vpy9MATeTRStlrMQp8 HPMQo+iGwm4oUJGl+zD5LANtmP0wCssyLY/StW8PwkN190sSRoMj/UTSl0uVM18MPp3gfvbn1/Xb uqlJwm7Ge5yaTLNUAJNiy+cYCumqJBsWqC3eTSxDyr/YBe54s5KUdwEtiEmDVYG+SzV975ekdmMq SLET97NydNBFeS8mZ3CiIn1q7WI2BUzlTwPOeGj2oB9yPvekRVKzYi2wAgFokUYPOGUPVVoPdw9r Yj+7+mlW6Fpybg2CcePU2L8ODOuiXnun1Il9zeBTOek2ZmEx6C5sWM5CUmUf5j2KzRWP7ldwkdon 6Ji4XU4JaL2aH84Se+5Wp6uLWMmnyv5PjsZDAxfeeKXIqfQOKohsPemGcYUHKOEBSyg1SuB7WPEk PXBbxx0OEc9VtrRyIZ8PTo7efLqCjHMK660jeltMAVv/kWA+y+OfedgefYT19TWFeGkHT9DySXUH xu9aKLp7KIWqLqeNrSjSTN4FLXsoMBwppNzcCISyfMXJvFYVh3dECsbck0jEleehtXuJ+RCzjLG4 aKp6IKXtAMxMIUNHaA8KoWsY34TV7PVHw/l/E0FvUs4TyIEMW/9K95n8bVbxvQ9ZXQBHzHP4gwqA nY29uXa1jpSbNgN/gS0Pc+KNThygh/1xX2HGIhg2B4Oh8qBhirRpuSj8vMzhQ1ifwr9IV3OcYkfE GqVgxJAqDNmRlVvf1SvCZYzex6EPwVVsMawGh646O/NyShT/b/89ZL+W8tH7P+C7C1OKESL65a+J JBbLdcmVebqjtGrgiUXA97ibTq/aVDx5U13YGxhhiAAFuAPEqf6JxrM66Tx0LXugHXd9eG2E8k11 FwpDzPdx8UVhz2D70BIZg1H3oAqiXbrj6qCZqZYxMhFhBaG/+zclFIJFjHXZAF5SAAUiDoqYTrQN mj6jAKLC+fgV84NslflEiouPdUf1v14EJEXqQLRe9qT9sUmGkQfTFocLPjXGSBOwy+SfgO6Tyrdr ZvAuWMjW0dBa9Hm9QOwYdLLVtSyuiCf1J8kOQcp7cfVxxMD5ObuL4gFIcDZZ8CBHY1ueDztOitiu yZY42nJ8JGuq/L4fL9+dxwrelr5eoVTsHeFO4oTOx4tnMycf9vUY4sDg8grXuhd1rTBwLaIVMcci FWVGZepmTpJQM1Gh6qRWQZ693Be7pEnbBZa3h63ta+PV/Uoa7VFpeQh/aSOLNc6TOhDrmwuTJoCE S5CdBTMyZBTLJSgwhjCihSQexOe4152v98uXucl4rDWLeuZXvS/NyYwiTQXiMqHlVMmopdWEfoEI vrPAiI/SzXxN7tbul1TAPJKmlUytlcE5oKEsdi6EPU904tQj/fGaAs1DN4tXAZwmhVeJ6sZMHOMJ KZ+wsbLink/jjcgKEgrdscwteoWFYFcjFI60PJYxK1A5deXq+d1dODvxKxfSPh3yRW5npla0/mZ8 1X08D49/RXPzhRQh4FEdAFDVnYxc4cMdI3xcVbLiSOuIXZwxkWGZ8B3T+mz3JPPX+KGONmE7+Udj V/FGpLaUobjoHh9t+utELgpk4MnbTbqZfetD08GI2VfArmBtF0xivWOyuoroyJbOpviemCZC2XaA 1s7vSI62LS6Xr1po270fv2wSx84zJEn+RUhRJhlpqWrvh3qQFGUka4GkI9LIoVbti0K5veQqYU0I MS1AX+CqJ4l2nu+h+RRyANnNFz2IcKkfpP6xuI0DFo79DAXTvvcafkV4yqmp+5hnf16lFs5SGwC5 Ziadav9tHA5uwMpaUKr1ShtKFrjFdwCf6HIsqx+5EcEPVDnB1HYJiMBV37nHh1htSEWvwpm8OS1Q W6kbNlRGpkvqYzmu9RmGS9vf+VxE5rI00154e6KUWnsDvxFvOikL1s17aX5GRe0NGsOE/Sr+7F35 jUPMAzIZB5dleyhSMzXUfUiV9FpTWIzU8HpxOcX5fneP0ssQasevrAYFGhzGLBFw4lDtjuRq+gXM XYzyb0ClL+U4e643lvoCeKf8nFvQA2MWinFE33xZyWtgLU+I8SKT8SPg7H7OB3JNON/8SwubX41J 5ZMlzXvaSfJ1mWiSoFumxKPKyLjJNb8fpsf3M9Nj4pRIejhriOj4KdS9neJJ+p/uiHtFDCPJ2opp mUBwfPqH5pvOzf7i+viHuQBfQHLcaJVIVODJBt8djcs9t6U+c1pe1MWF87DZTDkKn74M3i9xE45C 5Ne3290tH+fNAJiMUSgdsX/DqAoy9pwyvIR+8NXAmwcDGN22Qrjfe/ivqVoBNpGQRHgCjQueNixm Fk2w+dGj8KeJdW6HThbIFO4CwPZcSOXPc7tV7wsLcTMhl2TUSOHBdwlART6Q+GlkOg6gBLt7para G2hVQe4dgf9b0svnELrf7Z/p8KNkemm/kI18a8eMYjKDn3ujHm1/dMHV4jBnAwjHndBDsmcbbnTK 3CxtyEfmeCoBNDqZsIhK8wSManwAvIKqMIftDxGj6k6qhOX4SSTMtARVtBbWib6t1AOZNOdOz5HE i4ZkHuAATM5ZqRzVvgLCz89w1QBSrYniTZ7jR7bHc8P2BpFBCvrvc2QFSLqHH6X940HCqFw3E1Jo 7Kvpt5rZCY6XebIduWJRhTF0VH9I9o/uQneoY1tqlEkqK/fNAs8+6SOqHssDzQDI7E12gwNFRkQt EIJ5etstprPHP2AcPXnT/8eG5cqQEFtQCAjsf+i3aQi7GKTXqqTqDpsvrRjzcSrcth6DW8gVAgSW 62haoRohx3TjZijabsfZjg8I74BuSNC8G97pGnfCzcV2drtpQnsYYmhaiIe7r7oUMLTRncqYC75T RL9PNmPqN9bOGxq03DcROeTX48YZ+Zj1d2ZiC8aDJHKOTcC5E1sj17DQzJTRsryuIhTQtLkif1e7 bXbioHj8qZ5Uc+5FoRxQdOS+tsFFJcPb9g/wEEy74/K/w9PSfJomayIy7t5Yio/mJESuPHDiyuVU 4K7ILYbZBRarFp8WidLphuGoeUPQzfpgfArIZygLEZpsVdTOTkHsTKs47ukg3axTkh88exbKlO1B fvcyMr3v04qpyZvwGQWwX4hHsTD/5Mx9W8Uz1fndI1qY1X8GXmXd9ZKi1PGHwlcLeOEuIWa9ux6A LREqKnfT3xT6+u5V7fV2OtBtIW6KJPCWeARLXrqJBoOHlZiO3aW5J5yBlKgTXTWZjrn2+KgftLnn dN3Wt/I+kQpBVKLOOYs9u1+6LLUmHWmonAP/kox5eNTsryB4PXHH6pySg+8GnXOwujd3q/3Oefh0 Z6qJ26Ie4Ab5KxrKrOQ3FCM5TkBEfxag7IyzUmfh5BWgy5cvt9vl14R3qJjWB0toS4f6X0a1XXMU a4Kj+8cyBKw4R0c/Z6ATYVj+wF8rQljh6jrzZ4boAL63EFxqYfbM1nqIH4966hZxLcoj5elhq+li Ogxa0NZ4jpRvk19fZzPFPucaXM9ZHBd5fPLaPvAb70HA6nVZHceRGETdd99n40dzA42zC0yQlexD 8ASw56qN6iriZbTDypO5GQUYfVpvFaTcLR0bqao3Yr3RGfx8PETeUQC/rqOkbNSoG+l/a2lxkAC5 ksTS0zmLkIl/iIarMG81GalTueF1Te0JRKyy9l9D8HFFGwIYgFGWZIAMy+SKebhMfx9rg3R50YOk sJFCY1MZ9mN+KCKedQPTZ2KFlewS686UckH/kIEKkXOdqV/r9XHbejSovr6QXaR5txEcemKYIjpf saGGZeC4x44qrLwbg3B1h6BojIXabG56fB9V0BHIGplX0cIWydDrpfJbiPI5nsIIcN+u5qPQXchb B+cYkMnOpH8m6c5LJMHumo52eMJpZVGTtE7AM4OWNtaznGtf84hg0Y1JWP3mt3OFs+OUXv98mX/A CiU89o6uhstawOMLSNlUtNJIj8Fyo+TG7NkEKNz8bqbOWpdSjA3Xj9p73tiwoRSSaLTgbVfRgJY5 IrZPgUN/EdmCxlRLUhLGy0ffeKTgCKQs/WPMoqU5MZYREGimi6C6X6cJp1Dy3r9WHfB7Jms5SvQO zRObV1cmW4hefh4oD4Id8IWf0wbaaMovcy7pFM0JTT7i+ZDOuJ1zTIasjz8fApOPSF/o81UQINEP FT0vpo12eT+0Yu9v+rlKdj9wP0WqNrAz2qndS39bR9XVfysmjUdoTzWXTgDpqEAtW9PzYprIY3/8 /fKE/uAnSwlciCCV4E8THGHbJmf7UfEnn4TiujRasPbelEpDlYhZqAs/erXqxfLNJVyBGZcjGvBc Rqw5lp+PxwMWNmQFSxylLPVS2Ok9afHN7/lscGFZ2YUwwtOJRJ6da9HV6gXD2aNKPtP5lbtc2ObV yPxpCi5NJmjlP/HZzoD/86irK6qRLmOulVaB6U1K69n0meKcMdHYSi8I6CgzU1j3VU4IjePhkgAa 6Ls+C3ZfB4sE4DLW1f6qevvhEEmNMdMvZc9am6IS3bI+9J7KOEDLVvxBdxrOG62xnLo1R19qAipo XU3nAAQC6gOI5PcNNFGrFCLms3twEG60tqIlB3Qwd+qVZ2FPC1QtRAF5gn2Az+mmA3Nl00H1ph5o OYYTMCs9tx03nB4nF3TKzaxmSrz4Tm5sQBiR5YhwOvyc676kC7FMuo762AqFt2pe/PxvOaApqd9w OMlXO0SkIdYHhdLeDJoqDRJ/2XYsbrzFakaS29i9eA6aJ5qYtl4BF/I8jABT5egBkD4ymk/nHUHC NJ+q/x9YLeNEgDCOSajGi7k8sm6zDx8N0pPn2XL0JQbC/sWRpiBTSNExiy7otzdBGlxjPfQyqmdW APFWI6HaWvtuTbDeaknanCD0k2pdc6QwW/NOEg1H/Ek1NB7Ci1r04RnBoTS88ovx3Fuimp77F6Sl ZlzQfeuGQ+j/gbiYh+G/RBu5tnMGch34HU364Ic7D6jzmFBBs0WSTC4NuQ7NZfH/gmdO3Az7KgzY bDdGCRSSh36dzF4uhndZ2mh6PtH9tY1ONsLILI6skJJXuKcdQ1sLN6+OhMbrNPXBvppwfHEkRQSp BYH/+7hjH1c4HmjIG27Z6dGqsW+m9YKbI2ADQCm42I4qeC+ii9MS7d/Lof0ljQXVpPB4fBcY+558 Nl1CWK/23D7AUmDsi+CnJwdJkgpgpYlDTNcOr90lEj2L8vCYJF5KLMY6uLsfnTBjjCySBA8A618l s7C60BHf6A16m1nxUyXx4k6Rlur9Xb+U88x6WSypJJW7qw13AauFVJcQScCSQF4aRJCQYYfqdfmZ FUmLffDmkV3vklvVASdgKW33tIV1kERLiPWPISKcHam6uM1CXk5PnZ1OQ7nrS/m/so/di51aWrCD IMr8EQ773UzF++R1Fx4THjknG9OoUbb3Qub2xuyvvFl1Z1bVH4zggm27MmiMu01o5qeyny4mf0x2 GqNK45T6XnoRRx37qHVwZStNpJdH/f2c7Y7BOOTcyMc/S07nJG4lUVhcFAgdlnUVaWKMHgCXT6l1 KZgRpW9pIaGZJFCWGMVM5HM7PSVEvz2otOqHgR5PYnYxPkmWAjZK7uSVIIU5GafFWHMCHWfgxVT1 DNNL0Tq9LLh68QAciJdN0R1he8Iij3ajEh1uWj9OLvZSHFnIiszsNyQUoY4uVQQxyB3HtyHjo0AZ OtdBnneyskvkTlTts6yvIHaASdySDaidYAcdh+cmxZ8B0UbqzJ8f7KuOnLUeDd1UJAFr/GVFsEwB mgXEYKDoa9IzCOZBu7T3HHJ6GbcH/vPFSwMg+tqR1GibgdH4DNIOW+c/1EwCvR2YNkRlGtaDfEER hAF/7rL+/K50Wj09JK0EjagDQNztk6LFYugc2rZYeFGIRLDaG9Gk5peVZaq8oCVTEvX++YjWkNIz NAcJcr7YKj0e4U0wvP/W5v282gUasDZOs3aKq6v4+2Kjyf6kGNWWZY2pXoVPTQ+N5OFxAxf3LdBS 4GePFcvhlvYms7jsKPAqOf4dcQWEPBWZbAISRhDwEQRAxVWvkXjykW/tNVeP0v6c1DUES2dlKZpl QKmwCylnjE5QVqoRWjGi7wI1GemiUzlL3H1pKJwWZhbE2hLi/RPuTwccR4Kz/G1DePEjaJGsjgfX PCVoyGTHdHXvRk8cGGb7y91ZGBZGiZ1dWLds4hPlqbkELMVYXnux35bnzIZF6claLrAxAvuN2nPN jZCLxWpEW6GvywVDBVXa/1cVGfcgp0IuYrAxsIc1FT7cVquHL6qbgRfZG6w6I9Gus0rZXo8hLLOI E9myJcBtoaPgXGFSJ5ORGkopFXy7eB6Kr3fNU3TcqM8LtrQ/44M/HxqD/ZfRSuIPN8Gm2IfrkwRb YCZHkS8b4DFWmjHAyfIo0DzxwvWCKuO5uS3KK7KaRn9PkBeFmAk6Ox6dPrXLpatj5rYZteUnW3ib KDUrAXiIAyPtsQFCK1ElDqHBk+ER2oUZrLYcyiGBIgbuR/Ggfoq3PRElTFB7V3ECdS+Z7l7T9xBT ief5aHLqNmYweBWldF5wCjKiPpBFHIxBdDp7BFG9MeqWzS61x41STiqwpFMPe0zYWrOjroeLq1kV hzZZUf22u48fxC6Z8cvQ5zgXr/xA+mkhWoTyQXLbxcAoun41iG7teFzIVfdjQmmtD6TN1WUDSqG5 RHR3+Vtl/YlQrbszAFGsuiXVTS+qmDaq6VJlMC8/b+ihoznNY/QWz+5KG7LwQ8MxJGzoOBnH6ad8 Qx3B4LkBmoL6VvC3m1MMsyC/oZkLCXQTcC9pXiXKN4r1c3vzdFOtxBpzcjm/DNQs5YIV4nuH8Pla /wtAV7iva3WqybuJKWWM8LTXo1WLnCaYstrReNZagS+ze/Z6hQRWSad5oqVyQoqoJaZ4y/CbPUPP ypZYfko7dA8/I/fg3kKThKq3IBJwr+s4rV/E+fB8AQCp5Jz2OnXCEsphZBEW7sHVb10XXkONPkah Ff9B1p1CB5v95sM6jEx3z7ahHFSc1jRDvGGmIkI+90SBBRQ+5FSvBwfzUZLSu0fcZehyrikbQwUO cdgKArKFwB9L9v/G/qY+5hwjUWuBvqkz+TqApQg7uh1b4swrO/UFoyeS9td2fP/j9BDHYbYErwV8 PO6a5r27mXVW9WzJC4ZqwQRVL+YfMYbbbBCTjT28l7gIAZB9uSm2opqwsXLvBqN846PY1zMRwaf/ WN5J6mObzRHI/rEahUSxJKRtH+LRHsyYXdB4LhEbQrcCSPOBb6fwZOomyt453zyOgXStERqWXTwG lx534i/9/+7cI/bBNuy1kgBSRZoY7og+Sz9a4KoCnCxIisb0isdbPj2YXUAXX/m3gEL/06C1KHn8 pT9MbJKseTGPkzzyQooMej8S69yHhK6crk9JdfqXCQvQc/tyvVcEbE1u1QkqmQMLSn1aHc0prAkg ANa/Fp9kd6Ssqx+bpipiT4z6X/agtUMMj3j260Tatv5cV7J0qsu9RMjwQhePZhPrUoB+ewSkrpkm q2v4Z5hmqBU2p+zKfdVcQ1PLXb5DF4PdtoNsWw1LZr4cfpNINH48vx6HPaQMetd1mA1hMMDDHMed c0rRN9EU6Peni6gkcfLkENxtoqWQlm585Ne0PQfpKvckLRAx5H8XLqrsS3jFhwqITrChLWCgU/WA bKKO17i/kMdFfuAKNT9yQSw8UCH3xR3G+nEhE/kJhqEpuqf04aux2GEVz/ZKgprWOEJaeGze32FT OmXazlr6e3bofbncifa/HcocmhsBknVSFgD2GbOiY/oqYrAcF4WxDGdhZIrIjIVKbRxAXKKwNVMQ 90jjPjW/6agMUKrZO/ff0wDHk27vxa/VL4P8fEggqZrbsqZDD2+BiVDW/dkTZO5F/7bD3KYFRZm2 u2yy9le97IXsBmCwttckt1iuScTEPZzgjXF4qCsbmwcgknsabAXvfiSiOss2v7t7enEcq4ybYfd6 O0mNHf/5Q68bl3rurJGXKiGpFIDi2h9gH77bP0tfCDb1nJFaojFYGztYcLbwxRUCh8StanLQ7wwS 0HbNx407WJdGLmNZq3PbmuYWQi5aSq/l5857kv291uLHsVcgqz7lD/YlgcOkePajc75xbpTTtQLE StKe5KbVONIL8bLfpn67ML6T2is0omJoe+puPGsopqKhzqjnoaS3KUL/daj5bBS0i7T1LW79ALCl VlC9Hwdoj/i/CW2yXpTSk5U1C9p6dLYJWw+N1Sl1DMVH8WdRtuAe8Z7ZtxIeyB8xqsq2NRUi2gRC 1FVTIA7Bw3MbKoHbVRXyK109TWV2RLtl8m1ftkBNnBh3BjHx03uzRN/saR3P9n04DDIGebmjqqTk xK7bdtbhcire1c8aQlMdv+3x134+BO+L0hN0the1cNC4RUGLZyqfTPyiujUDha54XpQPfD8Z7AMp h2sa+qaSXR9ts9L42ldsxNgXX2xSvYPHZ7TpiaFZBxuSnVI4uIfe0KZb/gnRzPQC7JFYxzFkPpOU f9KlTre3yTRLp1idpEVCCJ1kl9t9LvFjxassQDCUSnqd20wGeK2531cFZAtpdaR8EXm3gLnpkign 2abK4y2Gwa5c/exE1YLqf+5iJSpD5wJKcCZ6nWDaW7BXq4KF+lvxipZssyBoLZbpOEj2p+2lA3Pr YxWgMP5S68RPKooDLqkeVRAnl+GUzV7pYBhxby6gv62cXAkV3wVHJJ+EnaIuBdGpbmw6Kg7q4Z2f GzkaCS7S8WBQsvv6JvpBmoLZAkdF6wfb67mt2mp5lVyYJMCP9/3e0gb4UAHz0ZBAI4HRxEL35d6P K19q+vfPxFcmpA+AuLzu4leXKWzIS7FvasKPiH/aHnKuuibT/U3jDX4s0pn74sAE1vHtFPA97hsV nc4UUzob8hxQeD6bJ5j50VAkMxixHqzzP4tAct63EPHlNkDSySWqLJ0pVdzm6v4JRRzIRiEkCdaL VTH80sVnWYTsMWkLZdigM4A/p5C/ljnKaSfm1kxK55njUv9UVfEiCfpNStk48VMmz9eZJZcFeFsO tyONMdx11u2oy7rYB6Gwwy4FsG9XUn9xd8aJG07FKA3duo3xMjZZ/OIeIszaZCZuW8iZpG6Cd39D FZrZHlpjrh2VTqCeyDEAwOuHBpVYooNFyiZ7HaXukIoTrP8/sH2UgUAKBYsHfjdswSDjkPOQ4kjE xDXZgEGZTZD9yObqxWfN01fwLTlsBfpC7CmsK0hbROHMzasPEuSv6wQ5wNngZjBF/DComA+w1VwB XQCE4+VEE9Fo8fflDeN2d/ymleL0cITNqnOZuw3ie48KkDbIQpDSRUUCpTNZgbjqDvLTygtVA5qf cBcBigLhDOVnb+NSVQHo6e38+z2JTGoEOvj+tAZfWnCxk9liHr+1WvHp7NujMeayLU/jpv2+Uw+s 74wXiXjCXzxOypG5pgCbIKIlup+M0vkcQG/2i7yuyapdm8dFUgzyQ+T90ofIWA98TVAOjIm6xHPH QTVZE+WYNNBQUZsFFOiBdswUe/V+W0C5/vAY+ZiiqBgQI1887stCA3SaJGfdk3rgdxCNBQ2lXEYy V7saAU7yArnqQkMVljnzripxOgppp8+57MmTEkuN2Qi+L2b9QJ4uF3yKlPlaDc+9JDQR7QgdDEuG VKTRJawXS3YZ0K7HO3T7FCg39UDqcdSSH2ajWKaaQlQc5JrcpNS4EPcQcjAPtv5xkoTFHdc+1c+H Efzt14A5GojLg12I1Apc8e0qvTBrQsLNUN7EMYOQ/kHqq/BOwT1gVVMEw9vPVPENLdmCP2w39bYh zfCSzncDXydD/OhHTC/v0d9APd75jb+Q3mtNPzo1alA/Ml7TdmwUZHFISfLNAl7CDNVoCWmwRjxm N3onp5UhGR/Ffo0F4X1wqXxAKi7xmAWzPxJXk+WXXkY54tpSuGRjyG2QsWBW0Yu35WrHA5Ms0Lvh I23bPd222gqLNBfzNZIeGUxg5bQ5ezn1VADb9D/aevBxBFvfFu0HJ7+OuJr5cd3qwiyXO+Nssob1 AL/2hFfj3fQm4gBC+/XUW4EsEModH+SUONfmBi7Eji7hiAw9WwakCfo3bb5Yxfni9qLcr2hGU2fV lU+jApYqHZQu8LUweY4zn2rquJJLGMdQ/ew2sSbT3+nvOuS0+/RKudAZ0zBZe6s3cM09EM5nyAOM w+6LWwZN+aiCR6fgxDr4LOIvqa5v/lxraNbDm0qbohNvIBIM8r4d+6oBxY9TeyUdJ7H3fpt3H/IK zMk7WZrY9WDTTg0shrVezDdIqY5+WhWCkrhQqdjtq6nkjjNn38oQp5x6VCWWpLjNn3g7QNEYbz8y pZoYZpkco8W1/Jxafztw4Hk7t1G17Iu3Fkt80P9VAKBHTBL1fjMdRZWKT7Md3spPKixTEzoTS+6G nYhvwo6ghQDMOBn9H4IY1/M+YeZr9Mcb/foRfmHiWXyPJUNW+iPXmFegwjOL3ClbuVxiurbtL2Ib soUzxZmspcKXw9Rk/HPRlQuqYGj6/0twS9wbYuMuEKlB9IhsX4sOavbH6ucbjOE0waathHDnX3tK S8yExFsSmCZYsZgecMJ6GLtSOAlwqQ0/f0dUz8yMeZL5LUvAxC3vCaKotlV1pkt9vkybUbib+lzv dOTf1hY/5rIChvq2wxwee46khi5xZ4qzWEKtehfzCOaB/sUbb02jP0nuCV4NeE045sBqKq8dgv1o QJrmnGZ4mIrobWTQfMJjSmNvIsqfy7kieDQ2NVTSOkID4e5VsVJiPj/5LO5pu1zayTZQlS0kK9Tp +QycN4K3vxROmZOQ0VevhsSNUKz9hE6i5YhMKr1cRH0SX1i87Imu4fpUbcOVwt8gw3VOU9Z7xpYy bMdb5Embv9xq158s15+Zy14oiX5e8f5WVXFvmxQmneCyI5q150WjW7X26EClgssGRyagFcB9ZLgN Q/YhSYD6MfI7s/iJZ+nEXJ919oRHWJ6WObGkHalDLTpzk6xzGHJAibjPfr7m+rpqnWoKFiEBv3oh ZUedKB6YQvVsDzLJexR+82OB2B0NkHd42GutcheGvSEvjE9aQofzwpsUD7jsVn2SDmiuGGIK7boz sxgSbOoBzDmfytELDOm6w9P4zkZA1NN3eiy7gvSzJO6nALX4G61Fh86FpfWQSfBu+Zdcp4GX7xv5 YO0h/4exgxsZSBqyBuuBj1hvBYAbAbanjyMx3uDtBLEEpwVTr5BbZFvHU053550fp05CPP9QG1JL fIHVGVwYYDr8b0xy/8uGGWDQ9bACtV5eUiDAnVDxLuYBeH4clBoOXFj+KYQ6+r1a4psWidPM22ZC 9fqJA+7MW9ldz5bd7kDoCysiDPDgk6+PQd17XogdajoG4N7vBHi0w+Xl1hnTuyoQ30d0x8CcEKMC yRXby8nGUGqxAo382ejmeeDrp+1mBryWxk7knXyrYHCWWqr9HIHulLIX7jLBT6+2sGDLW11oIo2F JShOkS8owAUP+6E5d1wUiuX6WJQlXpF1YUfxcqxHubxYox8gha2PA00Q1IcvgYzGwoM9RJfgiS2/ PV+HNo8//IGNMqNUa1F4TVCjffh3L8L8hzM0fecWQKR8hSH8sJZJKD6bvDHlzPP+vg2mX58FYN5d 5BU6x5t4MimWfCm8ThKIFfiXDyRYrLGVLc6X+mwYo1SQFRkeX/MPztiFzj/RlMXw15ArPkBir+yZ DNoLnae00G07xLjCs8aa4uJ29O25mBFXRu09lSmrEaNLBpnL5v60xaJ+sPGDQ+ig34Sro1UQm3w/ Pks+NJH+1diI3DLG24KVz9EqE9k/S6nz6WIyZNKYI3Klh20HBy3hRUnSqtDTv1zV3v9Vo9Ku+DgF f0epEhgp34+t4kdeyftg9jvMU+dYYBaHTo0SdNZLplXC9ZRkUzRrHHx5mIuqSIGM6+5jgE+a5Bdm mo2ZXfYJ2De/MEZwH2l1ujeS87LjiLAzgTynihfdGaNf264NLYgfofqFLkGaVicHhbyqcZ5dP4rO CK28CxBGF7I0GOCWICW+ANnaWLjPIQ/rLyQ7pcjtBM/UpYTCJyjwnx8dBJKo1Ayx03puRG4WPuZw nn5WT9UyCO3YsasU8HN1MmYBv6YsubrADfJx82GQQ/ybpEmV8/6zNGDXF1Zd4eKQi30PjEi3ScHS W4dAQ6g1xLecq7oQfqML5vsZ9WFTPCnqIA6lufMvDaENlMIfSF7l1Z/+B+ZZP0YXIRk+ZM3Rptyg 7SPza+OKhEoXKDPdEDB1INdrbLyD7TydE2ucHY7IFAFHCfuWAor2lUcqBU3lyG6hRsvf7sC0K8Vq pekCbgETxqRGq36r4tSUH6wayxaWxmLY/nAJX5cs9uzMn+shkGdZKPBgIMxJBALsCYWbcKajF+4l d/UwZdt7z8KhgTxsWRz49+YI5N0LYpmTakSg64Hke9I5K1o/JtmwoTIPTWViDLrzkC7ZR32Egzl2 diE2ViWn+LqvUx9cfzoO98+T9jszOGafJrrr2eN8j4PqggwWc+vDvF9rnlDLePpmLcPkWMwoNvxJ bnUMN1AYabC7j/K76L4S9RDI+Mecw6d9KtQ84vCFVIwEiKqer+QNcvzZwEuit5Kig4i6ESm0reEc Ns80TEOilcZ50zFnrkvJMylbDmJD1hQuQlJE5TWbirKodwmo1sfIZUZaks/D1GTKeur6hx4wKbOu pchmejAn5HtTCfT2lst07uEBR0JkqQD97Mpf9R2RROWUucrRxLJ8r1GslSWrwk/YsvHnE0g/oILe Su8Wj+xPhoY2VFa8khg2lCD26dYO8cA5azpTxjb+xVKI68YL9xPdnokxLuI5Mey++kEoYLuEvZs3 wCvHxztnei2VIe54wKN4V+L3Ir6GTOdC5gcK+xirn6kWzyT3ge0DYR+Aod7EwkbNshJTKNC/cJCN ksncz3tOL6CIgWiMWqATUUv8hrq/S/y30F+GX5cCMlm0P9wVOa6LvEfQGYZgCQh17U4OcDXq9IyM drIerUdAR6ZP/aTQ/W+9SILgROsEgtQBICINN/HVZeQUyaxpVRTTOPeKxOggCENwCq4OUFBteCvT IWES3KYy6HLng2F8fDsAD1EtxE+Ua27w5trylLK6pymHIghp2CpHeA3ZMaQs3hfUCeLs6Jk8Kuxf T9bCwSsWVrxokIMKFWejswVDGaXX/BqrdD54MGc1eF6wcdDaTKrR5o1igJjgvUQ9l7Jp6qsg7wRr FqFYTyfpv/2ZEq8mc6iMmSoMX/aZla3LrqYprZIv+ChOPmYGhGM/ti9vxTQMAloeGvfuFNE8M5Pr bzu+/nUOitUHab+49bGFmXSJLkqyTlcYRdnMX4ZC2aS1YRABs11e14xIHy/e8xL1GfZ4TMBcYzzC ngo3QZUc/nNNKsGPri1jfH1ET7WymGoQjw5DDPeq0xZ0xeqcwlnxLTcaavSuVYJuBI13DL1QPdSq FtOfYTvbzeXcP9x2Upm8bhK/20rixjXgnuLKjGPST2B/cOhYXilM3ygbzc+vfwnynwA9BR9JVtEw Fbva7NX2qoOngczC18RBZNxVNiyNw9bSjq3qLwAa6CNTVD4+2Le6WGdUtUs56aFgU1G1Fbli+bx3 6Ta5PjvZEg58NCpfVzTB8Yh+VOGctx5DltzQXAYpbwBxAhp2JzezWkf9+FhQxU2uCZUdFcN8B6ta 9B2Bvu8LwvrqdjGEIadX9D7FDFQ/V9GSd9aLzlXzjQ9i8MQOXW+ioSzkJ8RW06MgzPJrVMm5YNSY ftIB0PC3OL4YWNsQ4phEiQqM6okQYg/1vyGpb8mj9xVWbTALkmNBuPdsH0Nqmghu/rCPYA4RXGRv UB1YkCMhQEUs55sVpizqNqWkb45pPkrogIze50hrGWeCYOLYO482p00V19NIbbQFy/Jco8Q2Edlv l4GVL93DPqma3vc9QcwdeqJxQ0kmblwat4JhCRyyl+q3TzbM+oVkFcUMp9opCoezALvUi4pjbF6W ZvMvpzqGSKpODJvneTHdoRXTwWu3bn0ZKyXTY9oh4Sp7JsmvgBX1GZZAijTgFon3Vs4RqAlt7HzE 9tdqQjjkTuHEWkJhoK1k0hfnQWHTRTerzZp+wp4OVZ2XSGWKdTUhjlLAp8ddJ9XbECarUgxrQMLz 9K8GsGk8SqRa82IHXlJEtzCdKiE/5dpUnd0S8U4nEj9oyBK3gMGlT4K+VhWgpd/y5o9vSXQAs2Pb TA3k2T1kzoefyqzdNii/0tljsCN7Fgzn572BbzqiD5ETF5HDyuSztsGEOy3kXfTfcbpg/FVU0fW6 7UT41Rsb6tEyb4exnWtXG+yX1Y/m9ZmC0ei9SgfV91xixTixoKhtj8NLLgX43kzyk698BESSdXHg 8dff7wea3+fLG1ncXyqFZhZYvtbw3++ecQXbfbOcf9K3TUYv5uElOZgEZTgKZdFNae7niFmykbp1 uCKNQWM8mdz7aCuvCPwZSLPdJ3aQlbncMcgJw85o7GofFzLPgYCQnggGHTe0tw4nAq0+q8+gW8dj t5Ib4tnf24R/pfSDqnM/sRrz7VtqUR2tB4H+gAJp8d+SgwAum0Fg4aa1Q4TfcjFrlHlaR46ZvKln Tuxn/78/D8Kl28JzrYbJPuh77K5RLsrcWDOFRmGtb+1rLE4XLGI1mmDlEHpv1MNH9EEjhURfj5QX TOJh89ldR4jpNjE4thL7T61iHFepsVxLrtPKW8CZVtXDzT0JIK0bXbHexPrPhQmIequdLaNNXZsl FSjKkc/7bWqy37jhP0bUSmX0F2p6NUYW1D2KteQtFk2FyU9fvZv5gcAUj6WLJaGk8iCLFjr/qyNP klZnlqDMCKQ+v6l5VZllXyw4ufX/+cJyuR9M0aWPgnxTw9KtHZBvfjUcLHT4RttnvT5DIToa39Zv 7gA+zXktgs//9tC5BT2kuMz96B5Eh9jhKe1vkLCKyVPRY1L3uimKgwzjXn6n1aH/Tp+k9mRLXGiK zn0rrQhU+/8lHCEaisNthvM2F2fjmbYxbVuBA32L/7+hJ5G10vjo6w77BiyAL6dKVifQj0AYFCst xl8kCAI9bwG4AobnAFHfj1GZAwH0fybQ4SlYvC5jaCKFo2ajvtULRnMoZ2lHoovw9Kv8CMhPlynD P9h2LTox3oYxic0c095Y0hpMZm5T4bE9ubYWrVYJ4FJxwGLhXvFTfuFJxQF6jT5tEuf/oMU/Rio0 yXsrv2BfuDrm8268OdH565KDgZWWDxUjhPWcL4o28OPsTNuTXmGsInx5Xp2t+n28YGQ+SE6i/XeO ZMZu7bAhQgLr6Gyj4yPwV0/92L+7xSA3ldA/wH8P3F7cOtcKN5bNoF/0iBYMfPfrziABGvBeM5Ii HnDDNA20JL9xNuALB3LWlnnvspeYpuWYQUdO9Bv36Y1L1OAYzekwBjfqxiVEKvUlUfUy6KOxHzNL 8/LxhBgHd3lMyoOAUWmhTd+h3dOQYTqbZG//8TJALHWEQ+OCOQxBnFHkgVPq9FyYsjMrrh7ym9hl 25gy/6iRCbb2hvHdCRWisiCT+avBftFryJaLvhUkXbvnRtRFtxiulXR2fu4DAddKqx2gYoLczylt aqo/Z9/8sK8lvCCuC7F5P6pCSlkZtO5uI+1pKnc/aPHSals/WfnTHN6ReYyfVJYwnjRBey4uQu/Q JLvILLJhdcK7p/JP3/oPkAlrH1ltSA7pvumABfFx9riT2SNZBH2foCaXYxl6w9XQDw5Cdr4ehmFe m0FePHWmfiM2aGRvwcpOUy2E9x46iHXEBlTWSQ2LjOrDYeYsUvsTgQiwchmfn/7MyaMqUepz3Nha 45NKJwF1n6ryefQRxw8ZZZQ2A0BZAWz/7FHZhWaRrpC23wn0wxygwkjUmgov3+w1kpiWIlcUf4Ql kdPauHxFEgTuPSYvY6ew6B9AMpk7F+or0ZS9clmzpqDxqAvWPa/LOq3j4OTPvwD4bYlP828Ifx1V 71LdKUuRMhp+0GNN+TAO7RCbhWjuK1FSxoE2bygeV74uugPMBbRjZ0HnFEaVd6fvp+idogs4OUmE 901egdTLS32dizUpZ8EZ3CNOBNuJIGdQDU+4sq7v0GmGAJh/HnW4CtiaUo1ysS1jl/914g21loVL a7mJeEgL35PmB7zUHFMdQ/xgt2pXRdDyIVT8xTMDvacpVTC7vFOzALmq05jP6CQqatUTD4OO91If Xjc0O9PrxmMQSEpWZrUIc3c8Eb/x9O7pX2chFiz4t7hQ6VeZ/HmaZIsLsL9LwFblf4jD0zg44NFf rZjZUOJJDcgBStr7QeedSFZY3wV2lsO05ANzmopw6TTwQ79hnsnbfqpk0KKVQ5DH/+y2KqMixOG3 ZCnveCTn+uP10i78uxj+lChThihV4OJbGyl/ibVMm8uCqm388MQT3I5alM5TIl7vnOZGe+svdJX2 jf0ZgrP3tKMmPnoLb9AjBoa2xkwt9oh/zQ4E0GvStFGrCh+ppZCCkkyu++LEWza07y16u6+573rV 5Oo93lYBXF0VkZexTZBxvytK9r/6Eeq8r0c7rNh5wLk215HuqC+77FQm57lJ2KOemDVZfIno7g0K 0GyV53UGqkPhJ8mxnIR1CelknGJdbwQM32gMCH4m+RK94NpVy0c1GmxDUt57QBAe+ayoK5mN3Nhw 8H/M0/C6BVfSOAeY/ZHEo+nFrHyOkQRqXazhBAc7NRDWEohrnSxqpiNfqIBGsuGyQV6n30cQT7hb bDXHiad9A9vHe9Pt/ZHatDQmO2tJ5JEcmT8F6+ujQXH97wDg+0kjjuUYacE2fE1JRjdboPe4cSwu dwOQhLnzHxOYqGtH3j7Mm63/7j8d9GTi7dCJfuPolququsgNUWphE35fr7V85RaO1II7gjgbqN2C maV8xJOVXfdNjo7c4rQRDPG5qoDfu+QMdf/HMxdueirbjao/32c7R1q7CmixwkbOLwINLfUQwkWt SViRQDFnPIMiLluqyBrQvPq3Wp+OXnWaPcUcSdPxJmayMXLJbk7g3i4rBrxELwitRCIm9CAQ/Q/n 5zJO3X96wkfm1uLgt1hAgjVgTYJLUmh2B6qR5cu4iYmZW0Hv7w3Fco7Boxk2NJB+NSemZxLAfWmc ScJN8fAKZbNxf17Sv/rNe3NLLy9B1vBCFDwYvdnQ01jgbC4FIrKJj4U4HRGehI9cHhXIxgAo86Wn /0sAhHXr2cy7wt7PpfsNQf+Vk+h4xY5GhJ/7yQ5TpF48DjSY72YdIrK0RYPvH/SItTldKrog/7jt Mri5oVvWc10CyQZBOYKkBz3LY4CEfyrbzKyYeLT94obsA6HDjpu9ckcPfsTa0rAadpi/FO6bU6Zq /i6w3Uuvqh2MitwyonIDxaySgqDS+Dx22EnlnuaQAw8g7TZDqE00GYqTiBdPytdi6RaFCmdr4HoX TFOBWey1HJ0avX1llp411U92cLJn1rqjvhfWoD+Jp4OHqbA/ifD8EPamvk1Z5KuyklznhVkuMrES tGWSIDxo/F9eiUOZb+xzSkvVQ+PR46+D77f17kkCmgNEREZ6fom17sR0XSS8w/9MVZQ7YEgp8ieP hIanlesl/HX6WJX2dI8Ji3MCGTRRDA0ZWtv07MPJU4unWXQsAfMVuMq4eNCoEcjF1g7c6N4PqsGv epxv3jThnLGjBkmPJefJWBNxHDLZgAeZ64ySD7UEqyM8zo3mMzS3UK3ITm8l/ZqAD+/5GsoeJD3g /hVHmmdVGQ07mf7zSEWrTe4F5CXaTWdwdif0DgNGimsOM4owF5MV/JImpdSToSOUIheXSbtQVKHR 08T7FA3opHy0FXN53alXo40F+lF7foOZ+lyDrVHkZi8/ZKpmi5SL9deDFUNTxYslzF5g6St0mJ/4 HDe16t1mpSF++NyQj7oOyBvRBRy5JspcZd4apDCsLOQxuEcXIiGMJS3tt3WxEIb0RGShUShzOhZi d2nAQe24hQqhXfcjlNuSipq+8DMiD7MHMYkqRb/Q8KesmMn76hfgPvF/VSqe3RCh78R4NGyBGtt0 1SIBjU5g8teONxiksk1eEU1U1qzuezco52l2ZZ+sGr4KlZcCWCCqwyRNocNeRRu2VA+jXpZRlYv1 YkivLNm4ALAH5atGK4/iB+9vzuG7Fa9JD8M0TW7g/5MabmEnqxVFCe/nAMqj7REM0lW4z46GtkAM BS7bmGPuBHtGSlY97n3NeOo147WdWrk/YUpNKMHCH3g8tHntsBt8eZRlv2YFKQmGYh3RdBkti2qJ ZOO/5C3TStALh5gbhiGaRie5uZoDfyjJKBaWgpA3ty0uBS8Y4RKCD/37hYRNAeI5bqvkr9OUV6Dr JtuCQEu5762YPcDWCsKs6IOVQtfXQ9Ifvqj+POgbh/mzzC0JX8+SlHLozhwYTZHhmx96c/uslfsR mYveccn2l0Mrnd3PwGrlIuTttnBi0EImFsvxtFqd6rg7DxzovfyiICspJno7z9YEZ1OXK8D1RkYJ Xq4x6GO3YW2IULvAYsSRyQGlVBtEAXKeXRVNh1AqDjNu1ID+eVQaqV0Jq75Yld5O5AEYv5THmTu5 bgyyAOmLK41Dr9vKlc7bhKMqGXXl3Rski83KL1FcvRN9KCTlmRcRYL3+vKYw5QllxITSMe6/s5lv 6AsOlW4d3KzxQgUN96G61qgbzAlBSPzFrjLQX4m3gsNHaRLKLFf2l2xt3AkDyIUi1mug25amoSsm D8zLOBdhBLUCKklzzcm2iCzzVpfkPhcBhcJ8nYi6Lw+9x1kNQ6MDFtiva+RMHP7Lrq6bkRcD58N9 zxSEAmK/dOth1sP5Vf+Ou98StYaI9dqAqVUBxRdOZ5BL7YCK5KmRMtbeSStfVn1yrRmUH15dbUnU e0I+MKKwdugqnhEkh5HnlQ255fLji91vhigdigZsGMbLHlOocPdbgHAfH34hUrLnSbA7IhLA33Et LZBqihQ+Nfm38ZxgWvPAzbWV0iy2+qxJ6NRFcM0YrwgGKSfibTGYjfrUo9PSK2sJaVUmkjbu1pbt 0S+MGkSsmzFCTPYczEn+DrCqbtY5b+1VGxsAwODj8bogSkDdvlgB+dBS8EdvmGepSBbu8li58/4Q TPZ5NlGyMcGYsz0wKcZcFKvvAot6Rcw85pqckDGG0EfMlSB2ygLdcwlBNmwFYHsP/2vlYfFGHXxN H+D9rSx1vYQqhrly9zekpkyx2tuvMSqmwcbDdH9kyXP8ypasjn/eYcwj7koociaC5rfa13lsevcK n5LL+wpBPcZltSSFlimeSt0Iu3jIc/hBMsIX7ZdeOfRkVtZmtageYOl1iEW+fDVLDp1HPPC+DFrI p29yk76T1yD3aDrWqFGdqtPobs1XHeWjR6N7L1rdhRttVvR0SvNedYawLmIhvV23LlnAXb8bx8+4 hOwJFD1HfjhpIp7QnevRp8GGSFpPd8AbrhjJiOor7XYVGMeaClOPAx2WqbN6tJ61Ob1UJaZ+73L6 V+5jfuy6zedEjb0UVdA6zvjRyTyvYh/GXlJjIxy1r+uwWe1Pmd8uOqDZLlS8Tjgs0W0i7Odu3qtr kcmx0zH7xf9s0iIUUG357kPKZ7ZZ/ekDmpZJVVvv4O5V/wuLReGiFs1zclHg47P6sV/aRdYcJn/n +wh/K7kChM5us4YkcSnSqUgM6e0a2AepbyaiZRpoNrn4MZYcf65IB/bbqtxQIk5CPi86R6kybZak hd4CX6v2+eopeeKZFxh/IlV+aUHruXYnyXzXSXc6QbzTa2/khM+hdTYObSF2KvaehN1USPfbR2X0 eorCzu42C34iUpJAXm5bLZ2mmuJONEfgDdpN8l5s/Rd1NKUrsuMOtJ7NSY/1kQY3kRKPYwJK+pUr q0qbunvP2T4UT2zUufy5JODQepkoyNeIy7UMH0fUsECWindIP5Hpq/t+GjWcZSxLfJekw2TBYH+D RVi6NtUWL4+wqYzKiNB9gVPDHciQnlgjgCbEhtSkCu82EqHByz5LttpEIPtkcfoclp6UlYBYYPxQ MGvmEG83ityhEoobhYxjrzi/Gpn9IVAe1A1u+L8r7E/HErvENHtYTmWX4f3rbAEWeLhjthN29VZC C9Dtef3oqGfcq0rco41OcrArkb2y6miZcXopxkgOuZa8yOC3bjjhg1DiDlndMVa7B8qAS8Jn/SHR XBwLZGgdn2f68I41UUrdr31VPAlrrpec0MvDmIOMlYRMgoL6R6i1AxAQn2aREVZrcH7yO9k26EVm 59Loe9tj2kRL9fxyAUzt3QJ5TE/W+OTXzVTX09K9VaSrAr3rca4XhYGiu82ZQIC4tydcuiQF3DoQ uQWXk1hi9yhnR13FM3BAwzXw3RkwxGgq3VOYET0F5xvLDvzotfxJGQDgPyuOJxx0pYfyetoVQEf6 CaKmbWM2cCL6hONjOmfjz+HRMmKx+BAcWnX6zoKO41nRTzTuuuaZIiF4XvR0vANsNvWx/i4Z8VtM vX4wO7Fevp0NCuj/gp6EobpY0MIDlrWeI11Cu38xjETdrhojD8RoJeusnCqukXdu4aOnFg6nIAZ9 BOH/7hXjHB9N6jvQtJq91+lkxLu4bkH2kyaJnqHr7pXpci22HUNwKW/vW1RWEWyztXkfMxQ2Rv+F Hw/iuOWG1zUTIsk9vO6g6JSGEVMHfA7Osn20woQInJfXsbeCWzxeaGstVN8A9SFLu3cBeTqPblt+ GrB5ROoWfshwb5xydoBRmZVZRwuJdPS5nTC7LgmKMIbvzNvpWBapSkvGfuCGdF9WK9Vtq7GnbvGc WS8MCPDG2ym6J3q5UJwE/iY67Ix9nl1SfN6610ed6tYki9KWHdcmTSZ04L0y3BLD0CM0o9/EHn3t nj0oL0JdnSe+aKma6AiAfImH2MpRJJ5y1NTURsKRp6JnTkpz2FgU8H1gcibyuBt6J2i1STU4diFH xFqaM1isgHtEK5qy35q5i2Or6ACsOsnCxNw/8NRa+d/UOW5JrZWnfl5ow3FUIirXZBZB3sXusRJ2 CE7bnusRqQ42u/SUYo5D0hZF6rufy9BiTaWG4zK/lq1iBk4Rem3jSIrlNfZyLYi90w14CVaox6QZ 6CGtzQT9wVH7UWWzQBqyDK2KQB8v2KbhqaqvstDPNtxokONV380sezNWLzvWjp7kXMEhFM7y8EOd 1sUOWFdhDeVw4AOBFbW4k73XzPan7k4Io+uMt/b5ADy3pflXZyjvCEDlxE9v3+rXT98EzkZNkpQO HOsQ5xZYh8U0cG/4WQogVhCOhWl/z4l7zNHHTCm7FUhjY18oDARx62N96Z1CC1wMIPyhTPHQrck3 /YDqXOs3PWmdy6WmQPuR01DCnsnk1VK4x7l7zxkFYBkJ7+/RN+7ku5LMtztr/CpnrZBzAcA+n1EA ifaixL5HuNSwiH70EI/85P8eAOjiCVoICll1unCkPnugX5rhnRtmSUo2D/1/91xaQbZNDHD+JG9/ +AJj9x1ycMh8L7uzAh9PY0URP2jeTTp/eNHsfuQ1DMRh48FQFB3ejyie1GH5tc7LIshji4UUhpBn akLODFTpcU684fMj17pUDuu+ukpCE7SJuz/HYog2cn5GgcD5rwnkgjRqBIN7htCDymhgXpoezWEm 7f31VN7pq/kWvVyOo25fbLQcBBRiOdj627NUdrjwqhIYLqL/1PORiLx3b/4AhQJLAiSQ/nxD85Ex GOcxcW0GIhbOh9+b+AmfkcfeZ6yP6hw+FsrozQzCnWgxJ9ykxouczhk/8LHjX31iQmkUXmYpy02/ ujtKVcvCP2FPCmEPBDr5hj7M/2H2sMgRTff5BYqOlO14WID9jchRg9P0WKhhIrEyqKZWTjmXqerU QubE/QDuj1346SWj6tznLvVLq824X1Ssuvdkw5mUhNHt7Pdp86FDNlPFQziUXBD48pQOYY/yJ/Jg ktWkdyb3pWCD07JYesu6mnvOoEvR39p71fN1lImrDCrSzvopNZlxh4CqIi3FWYQ74nu1M7mOGL7A 6YnbClZHptw9/xj0jOZ+9Hwf3bUJ5ELGtkDJIZk4gT0EBBZSu6b5yxAqDM6rY//HJiPNjToKPTOQ KjbUj9WFQNuKsyvdR7WUTlONqws+VHYTxFbwxtYx2AdgecjHIHQmCZhtdb6ByJoe+ON/yTrJdbWi rJs+HmfdelNoeedFyQ/cMcDHJEaT7cn5uQxTDPPwUPHTWCjbqktINl8syTiHB+R7YC7eAF++Kb8B iefNyY4AkOAsmzN/ep/zyhcm2kyK8IDgcijobKStSJI5F9g6Ez+WQVUygCw9hBrvoEE4BjeWiuvf kPGON2ApkS7Pxwuc+MHT0aFn5tm4hfavM+fJZgI0QT92C+6VzsMXxeei9TDsZi0+NoqtA2igmzrZ 7WAfJkxTy7+fqLzgUIIIXCcceXNdKBNvq68jLm7I7FiQAftUqORlhUvW2SWwEjC4ZMuebzh4Pbdo k0ekwV3n4VG4m6HY3wPpXLvK4tEiGqLXcBdpk8c8ely9E6ddpcPtEXmOPUtjA9cDxLrhYld5poYx ZeuijkYJcXt35IpRwds+mJAjPy2fdMfFXQu/SsC1LksbL7INvGBetszs7ncaSm68Ysu7orxhmnr0 H/WC+L8HYsD7EHcJjAgZQmDkKVYDv7AGceSd7WfYIzrTXUaumGtWK/vML5/1xayhSMvdagb1jn+6 U0acJU5bClZEpDU/X1tiMoi85GK1jneJZr4CYD2qyZ7wI5nPvtR1GjvCx292fZEqN3XNw3QX1XV5 lbo3VHJ6WNP6O8Tc//3gv8Fyt/Ha+ckv3Ofm9rnVg8v7GMBmNu18bYT/FXNq/w1x++BTtYdeeXaq NFaVlYNuxAoDA8wqlyFbLJGz7ovJ397aIh6wX99OOrHB0DZoZrMo0IZlb0oMH2iziq3/uuNA7x6z hKY/Ayss7QgA082MyHykAEPwrcW2J51ZNk1y+VXGfSVAhg28vAzRNidAblF+vo5TzZteYiBdL1Yc Orp3k+K4vGQYd1V2C5VEtpFp/0achth2sclsOQ7Eck1PEJrK82OcmUIyUGZrbXGQadwrfQ5JY5/7 EYI4Wu/8HjW5dh0sqTVhSlNO4ByBBCuP8eHI5EJGvrJ89rNBYkMP0igiA/EGziIL7Zl0Cj6qBh0k AJwKEd4waRW7Zu/V4oKk/iANx6gluW988yN+Mo9+1bNHOsEUMpmvuSq6CwGLrul8n7mCMDIFWJM/ qVnpkg0YfKpy6YQJxtmAPiQlfM8D1ZpifVjitUr7MkNC1R3V1NxJQ9QDgnnfeDAVxk4CSvv6YMpt 7Jqj64WxVc/rzmGOg2xX8NKjVkkDFiIdU+fvj+Od0pTEHN5k3wNpSlUq3pbnK44YFCxMeKsTZiXc Nhp62PXUNT9qX7/wnZ7kE9c5QqGgpT6YEF1hRbj5GkAWxiGAfVc3Hqa3hIb4W4uWMtC++vA1k8gL iqYdnNqWiKdjMe1Q8fX8krTcZrru6TbyZvgKqnOUslXev4hTjAaStDYNajdjUQFuzdkvSb4Ig7sB +19s8bK/4F41HIGqhFXzjVDrul0YFOF3ApsLPJGwOr9b6t/z/JwwjX7F6lkkqp1XrCcmxEl6/Xik ztrmzyl9Ntbb6ai266kfpDZQ8w0dBetlZdAr139rU+cQyKAvQMrdbxK1SneboKinvq1rBiGCgck2 VooRJhT40M13E/W6DTeO6PIyKCntM7NmSNAFCWPEvIZMXHn8AYGZvqWTpOnSlJfOt/jz2YpDsB5l NMmLVPiVj7wU4gJjmxDs3ts8c+eE6U1MiXLjIUeGadjc+imldlzCg4Q4doQyTyxQE27XE9Hfthr3 okALlLF60ThhG4AXqqwvyW+AK4lwNb32hN7AWRs70wvy/jN7IiL0illdlIXg9NNE3KZx2lQL0sN7 XHWdbc9uReWSu/sjXDAwmcRcRSM4HE7SPex+PnCHTDIWm3pl151gKc2GOwekj9SwgUbpdho8hefB fBH1ekE/21pKpKr17D/3VDgD4ZFJN+y2inn15CP050tOq8QZxlO7LerT4DCG0sInaYGD7yWOZZka 1MF5HE/CLBoQUkUVq7ggH0P3HKfbdlgIx6wxzGCJzefnCMRXJIgE8wBZphneQW1tDJ2hqHaDyn+I +msYf20MAmbKR+W0lXaeSjoCx7W8iJGvPmDreP4qByKgM/MmNEzyCtyVq48G5u45Nx3+m/OzYoOo P5fQiwOeKawfGs6iTptDeqBB5VankeODxi+oiy41l4LQY1dQNBaDOiNzUKU1h2irg0ybeudS75S4 yZQUu1525Q14tlTiWIgGCkrgsPH+sTn2jP17KwyaxEvwhtoIrOGEy0HLaRH0HKKc+ydew32Zr31g SFeuSYD8npoUcniuRlinumeH2OkhKur9wyJl6FdDc9BeZXijgFnkKeh1tmwsk0ocPfKMogqXqj5X LyAelVEumEduz/FLrkRFfuAS1ACIUaPHGDnX8yemOIO6huKH6gseb4rdqoAyBIiVXv0//Iunb7nw yzdinjb0JS2eqehadxD/i+vKTkM7JXLRgCmkyjn+FD4ANamAoEzoDPB88GeHG0J+4WTKYgFjJobP qy8+Q4njQwGsR5FGXwLINXPYEnTB3TgrdK2m6tDZT6w+bEb1dLXhBbZIuUS/7YZKi88MCGGZczrc VyReDRg1uHb0n1gpn2L9ZpZztwMXmCH62vfoAsXoIetzTxCZdniejVHvhgYo88F8pgQKcRXuEAEk /8Fx2ExVli5Od4WKT3fpO3d0wy10UF+FO65DjU0fE9Bs8nRr+0cWQqugk3fEbizIWrDm4Kr2C3Jc Z8Q+rQ3enU2TTfgjLuMGNZk38/QcaUOVqyXIIy2JHIDKRfcl0Ywyjzk6/12Z0R669Q7oPGmbjksH Eb/0KwKXk7moF3Wh7/24XPYgSHebd4nJcaMYtDET58G41k6N2RagWL9VbQtLjtaBpf3MyCEcBGIY cyb9pLY2oOGXFIic2pA/xazRLyOMU10Cgj0bWZLj7ISBHmpWzKWqjajAarsLvak9vLbq3zkLoBJy NXNIOjlSY0zCBsfDQmly/JgRaWc21nHC83vJUYGMUwwyi8heGRLmPN745h4IF7kAKOG3pp8XVAp6 zQS8zM4pEcs/9cMs1a6rVI9ccJvBE4h+3ky30mI4mphTKziOxBq/ZBF6A3W1rnVLseL6D53KtUbG 4OrYMtTQ5ZErfxSA9aMPX5JIwZhTgWUZFfyx6R4jnhZ7tDtG/tzYiabB4tUNt7d86wMVC15JmL6k tqCQIMJ5HgkScWodk5FrbMrYLdoH59VFcPZZGTvnv4jFKWqKQosf4JNID2LvcMnTP1F1B2SfXiJH xKTNc97HGnSaLwUAJA0UoEEGXz6skc5bvglTch8oq4ss1XZ9wN+rqhiOrknqGh5VFt1PfmisW0pr stnBqY7a5s9po1eByBWgZkHUH9me1zCOCJR1FdkUk9Rnbk6/Z5rzlZwumllGTjZG3i6m3RPS03Wf rOwvaV1WIEEUwPwJlY84gzFk6fPVBTC0+aZOReLrW52qIvnRlKmk2ipd9NRkB0mqEGWFrglKEKIR jzMCfX/PcA0B6PflGorsNu19e8xSHzfl5SB09s4PzqRd4pU2wkWI9nwuvNw6NLUDeF2Bahpa4UgD 6bDNQ7qGRZ5IqfHYZPzPsNKr3UMkclziwts7Tqp40JC5cFNt9OFla242Omf6thoXYuYlW5q3wOIP hVg1cHOnvccALwSKQcxocT2vIaGkbMj+Q50Un7089vdhjpmjQd7Q3QKgAFPD1rcjjI7rx0sP7maT RphdFYPRmZSQTMxkrNl26u65I0oDPUvXDtWHG+r0kZU3igtKi7Mya+OpfkpgMh0GTdLQ9qIlVxdE gOLR3T6q2+PZpRg4gOZjAh3vwhOx+amcDBeHo20lPeSj/6hhkM0+FEtO+k98W+AjKHiyurDCdwQD t9b4f4oXI9qMaH7/Yc8Gsp2DByDVheNvXeVcAT08hUuipMDJ5mU7Xd6KcgszUX+UQ5xo0dsmQKoR gEf4bg1I9zLyj+V1pbtk6nXkv1Zoq9mxa65yIpzySCHVBpp2k1mtONXvRuGTzTGFJYTEclk0k+Fo JPq6KvzvCeB45UGznqmgwPrq2FOtFDsyrZGo++bav+8lHVjrjuG6q6FJjCHb1eGf7OYv7jDvKfQj tvKFq5p1JW3J69DWQcOrop89wrcrp+2e+TcE5wCc9egHYxzeabkcENRSmjG0DPfjoKnY4X0bTNIQ EiHz0pVJKLtUilTO7yGd9fDtk2hCAeHdPZwkrDaLnNMJAk3fecVJahBWb1g88Z8iNJXKkA6kY6Xn FC25r5Ni+wH0v+J6AIHIuwdSQ5RZ/42hYbqAKnmT4FUobsrp/0u+pNUR7DW24rR8LHI/1lZW39cz x8eI++BMPXC4IOKomOcAzYyCpnSggGUZJoB1+nofaDgakkpXIhsYNw54f3h+SpNVC/2xWIjnzSI7 xxV0zBXK1zpQd1G/obfBNsq2l7FXUidHBtxcdptw/wPDHBsRP3lQ4X9KskIzEtFm0zgcAqE0atI4 3/bPIzQOtskUAr5Qk+Y7Ms6duANQtY96mzyEKmQ9zGPXkGUxrnGeDxPxOnlYCZn7cw2G1BL/o0zd sGZTtSN+DE0gUDvBE3aRYu1Nh3cgpPEnJkR4z9fpl5Ci1JnpKKINGD3newZTZo+kAblUvXW81RwQ nY1PmabE705Si8tRkaamMbvgaPfJmXdZitA2ROEY/UtvLk7w2uD2FrmbFoZtIq3fgVyLdK06kY+U F8q7tn19zlU6+Jxq9nKf3vfl6jktmIYD8OAIa4ttfcOakOQHm5UOw3pHnQuOSWTEOpo16PhG6INq WGnw5OHkzoWui8M5tFxI6FgOAhS6NBG6RI5hw8B8Wah5H4KxYbXgl9kHM37RedSxpqcGN9+Xlpqg N0sxzzHXxI+yf8u3O3oxoy5J4gqAjEQH7Ovfbuf0Na3Aptv/BsyEh3G+xYYyCXoVGaRjRiqouw2R +Wfdn/j24wcOnvinBMvTd1pj7aWMraaY+7xWmZdnq7+FaoRzAHTNUetPYcbrZsORQuegcISCalnr S2fPGgfZCawCp/VIMbqTHqCKtoxvWMdwE1e6NzTf+tOC49JBA6QOzxhaCOPexGToVvuAleZxktyw zcECdMU5toY8qt+7LAWzZ9++50kfoIGHkm7PwrXJnsajmAlilZiEezcDHJJ8kLCXsZQyoRmoa7/U 2urH3N+swUWDnv4l6Cpxh1BNMcNBJpgfk1aS9Q6Psgf2RK2t893aMjob1PRu2s51P6loW7bk97GL b5e64wyFIf2VfMgbeD3oAJA8XX4Pqum72d9In+fO00yTlBFEwRVRXLpGBGc/CcQntlgEptya2zHS gB8mAHP6lWvgqi/ucqqqaQpvU4Nz5+swRD4Begb/uxhDoLV8kQJdwc9b9fHt90NV/wXGpHgnDCNF +QB+1FbWOxojd301FjtAVRFSahN8uTATqJA778k1oxWOHLVy7kTfuN1/PJv0IhoxlMO96Smjlai9 0jFgqip6dwxdM//bscu7JeEQsc1wbwD4sekP7Qq0lGBO6pVkBnZRwnsqK9CTo1PC9tz9UlPq7jiT TYWp9fSkYkcB3W2wSWjPqv8W0TfAXqwsSBZjV/BDZ0IVA76h/GKBVELTBb4J4FLbdXcFAubr8win iApzskYO1cPC/CCI4s2NcfsnEoqSZW0m1Gzt3++1odt1AuobPVbsET14siRAaMdkV+6lNo1FC9cW D0EbfrMYwg3LSS9N/CK5reFB99kqRblBRthTPyVbd5Hbnkk9xse50458x+pRUPnF8fRfg+uxdDKW q/7CtcjnL7WMshdOulqTJUHBDn+CIulbqMX8KK0jjIKUo6x2BMEKk+w9dWkfyzzrcEE2aAqww4od DELK/6SgD6W2bfD2aIQ9yZl9rGBkQNPS2bkxf39FHfDoOITNy3kE+oMpBNzD5VRvT0XH7f41l0wu 8MfI3Z1KPyZ2H/ZU/8i38rwh82M1u7Q5rszba+JONCk2kRBgIanT730ilRHBN/5v8RJkMRVgx3zm 53eYUixRE1QeesVN5VZ0/eDRkhfNn3zSbqyrZ+sLHo6ivkiRk2jq0Uiq03rToNP2Jy8/B9B61/NB 7s0kLMVFUuCQW2QERmzew1Cl4fryCYpDP5m/UhjN0mCnT2Dma0qBESd15AumdjxcyrRXxDpId749 SQmQV84OOJkQ2Vikbslm9/hgED3xdOV5htO0op9A/wHSFAjtejH5rRh1qxXIfs+R3pimVE7zWxhy oUR2LL/sYE5ogEnkdBkHuLIpvgo8RTcDAoiaRqx2FKqKlUp3RIwsrWH5HD9yBVY26kKznGJQgkTJ EnSIUUbJVX7/O5zdITCETo8YhhWVabMRt38RnYB64kf/8AUHssgf80IJtcWmXXk4s87N/AhwaEuG TlWDDyse6u37K9mxhPuqQe5d4/tNEwbpq8SQV2tpV7ghrXA2hJXObYiv6qvnZd9QXt+Lpi1rbwQW +JVPHq4ZGM6oajZbSAGURyITDmvnNSnRkzyOugYuIzmYUUBY3XRhvFnhRoMK0xN3PvoVLkz5+eIK G7t+eq1uMOy31oIiIR6V2PjPNJYz16zA1OUv3Ro/MyRRsoG/loU6zxc6/oXbPQ9IqXr6S2GiG6cK by7EFvi5vp2GH+KpNOZ62r+VpFr4DF40sZGgGchevsgXWYJtH45JLIiJyu+wOFT9VDvoMpsl4f0I kjMpGHNf0YIwY63uinM77mpsVDJNlcIf4Qt03lLmHSEIwtn7CO5FPQSiOxJOK1q7UyZN9K8PDe4H nfNGsHiCuXxFhbZv/bivH4fuWyvVP00B9ug6BF+RgQT3Dt53sOwyKsj8dTbfIo7th9iv/oHPn0D4 7jwAIzU1DS4mvUdPSD0WVg21HSyelkHtsVeJQVRwndy9t4UbzuIw/eRpNtcPNprkFPmQ6U/g7i9a OgMRMIPP8Uq4mvThifpznuLo3CYxbbTHhT6Yilt1FmkvYSWStGhne359qRrfOIdPfVl/gujE87M4 ZmW0ArSjsl1Ectcv21Yj3V4qjH8AXmOhV/Xo9ItA6pCJbvBZQnnk7nFp7yQHgMIU+9M3maPBYFpV +HtWoPwvCma1SKZgfoH6Eny+Lt0hMAwNJIEqeL6BCx8clLKR+KvlMPg8LGALB6Qpf2IFapUZm0uE ZWjXh1uOQmCX2JADrJcc3Oj2i70djCE+y5jFncM49vW7NZPaFrMU3xmc/6qHbVeSJBvRAmv9t+A8 9bDPtSFU12Pp9PXHchiHzPnObAlpaRIAw7FzfHdHzxZZWpxnP5JracPahP6edGZOOpXf8ZdA+TYu n//1HqfdCDUKTtr6MbLG8VSB1gh51rPu1S2Zx2rNZH5yqrFG1W60UVVROq0q/IzAD2IMGgk7CNhK jcgQtCwTGlwkVk/3xc/WDkv06Re9LrxHurNaNmucHDVtvCD1aE5M9sSlJHu5dFhd1HTYMXQr5dpD NtDydtAeWWqTVqIlvAFIEgmQptpxXG9VO3DM4bQGrQ5rG0sz4OCYNY4YH0JYGBpdU2WvFG1pnBYS NMEwgY/hPMFU4vMrGKKkM9/hRY/02bdJsJRLZwEDH0Mo6r/Lz1lrNHVfsc5bh6o7G+j/Xj+EXKco mZAd16/36NIMubEQgdLyzqp2ApS1I9MYR2WQ6vgMBvH+9VLjD0uVBVm7Tcz45EE3T78pwr3xXAk1 RCuH8ww3/NlO/UI7wUtnCo5CdoqrSFoG4+RnDjdWu7CkUOmilKqw7cNGUO3U59amE76kL+bNrkiA xthdf2uz3j+YaZj2MM49H+RDyp9sCLmbsNP58RjSlxIxukwze6n0v34sS47T7IdJkmIZLQPf6HKT lKC0ID90lWw50FpnZzsGBJL6IoyFz4qhS0rOvdjW0h9118BI1stlZFNGKA9q7cQUOfMfakqvQOYz 8OO+IBre+h6JvVS6wXLezEWXXISqnFBE1SyqH8CxC5wj3TCzVCg4ZR9c0KXa2JeAOnKyhuVq1szO Q0ZnuOOM5UAs1SliGLVuvcOFvT1je+LuvaAzhUIEidd5Ptj06D6ttyNJJOCQOE/UHFDN1IoTbRP4 vdfx5G6N58R7iF+000yqRBvpKKyY2JO5G/74jJzp/YEogaXB2TXJb93CsVdFa6bDubdsjbNabu0H 6v2FfqabdRYjQGy3g6bWZruCFOhMe+QFcrp58w86Fs/qLHPmWQG97qrOuwVTlUrLmcgr2TFHa9gL sUVAi3TuTJ4M4tyAlUgYFS9cbZ+4zFg6iwhxwAEIAdmnJCD2xt80XEaXb8rEdkL8jzFnXi561u3F 4CD3HAiYDKar66QXuOwkC/a2Ffr+eHg2Zz5D0O6PCz1AGIcTbeuVwh+9iZK4IvnyLbF+0Dj/4iHt zUR+YsTSBDLjUD5hHrZ/pFs8wSTDN6GZ9GoiRPhwlOa1AASZngIGKscW4ttX0R0zHCGhhJjmdnMS N0zsAOYEG0UL/DsskS3lZDNAsDFeX8rV95Y0UsZ5/B/K330IT/1cFvimGKAeYd+9gzzBvE1YEgw9 gCpvRnR9Cx+AqhFkRXnu7e9EN8q8tNtkQmeT2yhK1DK46NpI894viVquVRpvh602PxJG0J7tUpPB ZYMpfa0mZYy9yq74VakJAmopn3fmq5KFKrxcPeZFcu6vhvnllde2gSMG5yrANFLDvTigYUiti9If msJHumSXrY09QHINYxHgOABxLR3Dqe45pl2rZEtbOiGAnhF5oZK0tgI+wgyP/rZbcsUXsV8rMIIi F+RuiAb/v+x6hBMYEDyrZjTIDH5rL1/3M70vMYCYrezahUDqMslcbcfFf8oQRk1BJ8pHbRh/Cb6Z fBEFby1ge1SJHCDmmcPHsyeTXvV7i/xme/bS/HoYP1udHDUdXQV/xDWX859/uJ4h1C9dxwxu2Imn aJrcQ7TdQmGwEe7UTOCP2mhHZV2NgxS2CMp5mxIDXmRUXzA1dFpHVTmlMvilqu3v1ZmNMT/x4Ada 5LEh+2UqNfI2f8EyXO/pjJSEHXc10sApcTTZGTd5D4kbp1kom7dHxB+L7+kW+V6CenO4K9NxMDV1 Wob4WLoUV3bbsTDASHxB1MRjCM7Y7Vx5l1AeT+84YjVa69PwslswVf1k/4vQTQf7hWlDj0WnwJUT +0pK4sTFZHMvetxoEeZSuF4xTetliUE2pZsjdygF4wmuyHZ58mOTWQQul9r9OhMMZh4iAEq4epxY DQurc5fgNv4CBsC9rG/qsjHVsxNwozPEqUZbd3TBdD8JUu55yF3XFLi2zf71t1EhRxr9AHOOVka2 l+WkZWoZCtFAMYXgPyzFgDg+strDw3/sps4gmWqvP1Bx51ZLXbQPI4Bw/qAPihcrZOK3ZAFIJN0b JRG+5WKRGMtFn8fuTIhYq2KLycGeytih8Djqw9rYTPU4SgebeOnPWaqbIcfGxoZ85BLDt1l0bLPI cCLL1Jspg/Xc5RagIdEsiQrQfCaBAeA1cE19BlaGLQJ6t2SylxGuFl5Dj1ZDcBRMHQvHF55hECCw Aw8kIxO+Ea7MZ36ggHR5wXE2ScqKKk8VAl32V60pXVOYV6Wm3Gs0S99Lp3lWP7B1qbIZB/zrTIfc BFDX32LR5EdybJuSqEW1BbsxTIpYmCQRbWfygo+qJwjq5/U3GxkTEsoke9aNAtrp3dLUQ/+BpayZ bWvzNvYvCSJFV/hZTpZNK5xkULSjmWarmbQnh2Ya3YKo9CGlriN340iW8ozgwW3OC1mhwn4NeqTT coCPNZrfx7j67CIu5t5j/lr26KuN96eOYiJU9Wwc1MERTqJ9ZHSctmt/kprme7ffYihadiEsnhcu IOyXVwTwg+pXxtaLxOIp17MsDGrMV1K5yDvNcOYaK10hyOZuElld11/VQcpbeXM1BkPaKBXPGrpd Y/Oi6CAK7UQjEfoycAgFo1bHYPDFQi8SiNddWIhi+FZRxAzec0DYMCTen1pjy1xtbwzt8wnZcfX9 tBqK/SqTdhx/KRP+yAjnIuDRXrbd+n7/LjCa3IwxioPo2DSHf/IEfbJjHfT/BCStu4ND30iWZEwu RjrKR60+r7dFRbJOHv92ylEy317QcX52SENFkcJ0hhQ9U6A15JDTgCYSrwA46ScXSejx3gAxfmnh jXyKKtbEhCa+NrloAzaS5O6WRSNrwgFJ+BMaQncLHiA34ix+zzWfeyve2XXbtiYllwMNaRw9+oCn U0Nsn+6NvNSW68RwLxRuV07rQu10GAf634cGKIOikTNn/MgUgHVqY8XOXfE0G8Z3kLCqa8Nt+R11 OdObK+mt2UuBGjaffBqj8cXBCRMWNmfZEDseTd9uFeoSqzQbtMcaGhsqijQ+deYPjSfSCY1xgfJz nI+cyFqNf2m/DSD1ffQDCDQyrPy1WUsJXk/6v5JaUHmWrQpGc2xFSRHAi13NB0CcAZCN8pUHnJgr ew1G02Fd3vl5w5kRopsrNmYOJAnpT4HpipVAH3yK/DLEbRNfxK/7RSAplgqWF6/j8txgX35ZCr3X yPBONapNykD/7BmpP5/yfDs4Haq9HT7/AGUxZwYhTU9SlceiNhSJDlK3xGY+6z3x6+Nmqqa4sSF9 XZK4dadQxifI4YyMBE0d8V94CpcfqYlGsAp+ekildXn3ZtrpERKuyimqV38zr01a/DSky6/g1HJ0 iKuIgd4ydXo/sZ0XiWHzgUikS7cqv17KNHSxQMnSdoX+6O3Q8nA7ybBzmfCI619tLVDUTLpQzxlZ l8h4ISMoSYgqMPh78p/88MIuY4NvSpgWwDGlvLf+dEu/25JIHzaNB8pwPARWvoGPawxaawdYcu3O jalXnQfsNLt9R3Kq+I//OVwGdVFAnPKotqwkNkvN3XiFz8ckKxfhZ14/VTshpetg5q8M8H46CqZZ o3k+3t8JX3iUVsJNJqbosinocH1+SISUgbej0WIcZYejEnXIs6+CfUYlQ2mzlJFq5zs5fvqBkWdG wzTEi7LzNv/K6UBiu7yxBk69h0m5FoO3L1ZrBkxnz/3liyQSk6jJTmkHTa9063gOFP/IlF5Sk1wK Hwe3EehzHE4AlLAkpi3IAxzkwKdeb/S7+QGmKQVVvurwTGlg98/0U5B8wAzsTNiU39AExZHQSYQL azDy2WwbIBul9KAxSyGwG3+pcXZxfwPOfxSGigBUE1CNbDm14MBd8HS9+/helaw3Hph4HhoLeyU5 vqCCbJP0foDHtxOgCCcRYojyOraeMnOwdzcXkXYAJWC2mLMGW58eKWzmaq6AYuiJx9dDKI0eiwDC YKUvCUTrpSzJagBACy9BZ2yoARzRME6Pts0Blc7/UFwT42PORhq3H4l9WEUdVV1Z8IT1FVRMizeW Lb6LhhpHHLbym1hg/pn0pF0wXnNckog8Q6QrBVMaD36Zk0QufpzVJA/jCGqnyTPVHfA0bD7xf6O6 kjncH+IIp+hwgpLJUbgIz+MjNagH1GTbVw4umAbgjMPpXQ4Ue1biW5wEIOAw3EeJ8WBmF/Gp7y8k 17zvVUJomhbeN7STfUWCINafalKVWTStIss6hIfJUyVDwWpl29Va/bH327ZBK6rX7Oo8O8e+sAdn 7koWPYOtWSqEOk7k+3anJsx2OB5ScPQ4JEmqpxeMBK6QK8eHF5zrUNKw99n+es6i6e7YcRVKVuii 0VyB4AHlI4bqbAnxC80i+t7X8krNC7GmmfKuTtRTI40nlYkcTrJzEzJC+fG2o0kHgor+XdHKF60E m3BDiCswKNdd/LxrhtV0j2Rlg0iY4Q463akRdCrSTFr4vu09oJ1/h2T+h83sOZmRqvPha0ye/Byj XwLatfLPszaeUpFilRUkw8q7ODjb6hixE1WGfM/AWLizzwvxe4OaqV5uLxcokM+geqYZ1FhvANXk coMw+DNvlELHUcuJJgviEiIq59O7rtjD+xxfPsa7PaxK+9wCkkhfVXiu0FLoF0+tU+Ysi2Wt7FFP 1Oomua+Ce1Of8q7muYmYEiQrhvmlukD5gPpBbEdPf5PmXmR0T89Ffex0ci88cFbBJdr3AQ8RKTTn ydSxzfP/w8+ETrVw74z0tAhU9PUzA0J4lRjjEy0n7RzwEA60cSbcTEKLt9Vjmj8XP2b1xrBDZ1XI 87NCfmzEp6H/GmJ5N6+m/Wn515TSgN3uh9q3+hE+w1pv960v3SWg+1uTwXffY7lQKPdybLmo4cCj Gk5kGK/EAMMB21Iye1Dr+Y/ncK0Rkixrl5kjpPZjp6npPBts7eMVIGPa75vLmde7U4V+VE8oNy3f MoGbdAL1WYZwbIiYAL33OLvktTgfViXt583emy54HMqxdxDahjqKZaBJMVi6FevR6Og2cnGvcz0K 4lWiuO7Wv3bnQwePK04dmcfDJvMSWeZjtQmquvDF6aLSGUxbAO3VRoggmlC4oeOUyTYaDb1sy4NU fFsv2LRGZsCZTzL2kfvdHqCC0KhbfsqEp4zLOsfuyvC5WMoC/nXyzV9ZO0zUhjwR3LX5YTpGnnIS J8+HNEkb7SIxTd0dglOBTWwdvHV+41ZVi0jWgwk03W4oeAACvnBJ6F75CmjoWYsyBXacPXpFt3oq uknx3dMZp76tcHwr4Wu5aasW2scaVungWh3K37SDnQeeFHgQ7qZgm9cnxs5lOc1u9A3QZqsVfsA9 QR9WpT6fesoBOz+ubmqy435s7Gmu4St7WKk2Xcnm2m7hc6u6P7JMBT2HBHDIDWiBvuHS5sRoX9C7 wVs/jimyxxy8oG9G7iioPi8HanUD6gH8fzBzBzwXYC04IKptbB0YkBv6k5t5qhgF3J/BqLlCu995 0ihIuqJ46zk8Z1tbBBsOOKlidyC3wCkS7Zed9DLg3VmLmfBoPMTCLxEK+QcP3WAPdn22rvsesXLU hV+CShAAygZLlpT4W/0qbsa9OKdpNQb2+VBySBL+W393Rw5h5eFYFD9kmaMjQg3nV+Y4HSpGSnEB MBS6jehTrR76sChPOokQ8+6IH7rtZBUAKIcClfgiZoAe6+ZHM9AQ3zSaPP11h405ayvvVKFq8pZi Z2jvjQIze3dp9JoP5JJojPm3kHjQMXpkE2E9jPw8I4YtS9Wk7WjFIOr/vdUc2V+7srhKBkBbLYuJ OwP/GJd+T17TxJSB1F1Z9Ci3DhqR/aH9jYVdMKjMozN3ra3TPS7jWHjD8C25BWi9/rD0xjH4WLCi gGWbx+VIvOdCkkrQUXgXTvfXEjHCaOwFHYNZMDWfUmdKjMIUL3KhaH8dN7wrqBSsVFhXdtal8fpL Syr71nyDVGqDkJPUnwHczEtn3l0WmuEv35mqaRY99M9uwQ3VpWzzoKoBz8QtMzrcqN1rw4pUXHhL t2uNX0u4VPEpgFJiUP7HuUxXXHmxkkKcTnqAQ77djW76txQ/gIWUmN4Ckuz8B8VAjVztQgkr7rJA PUYfNVzBI50RLQFnuucjw2lVY2f3TpQw+R/UjLD+XqpopWr4vJkg91rfbLxvl/7zLIn9Fln1QjDN kBy0wQ8nDvmDXGL+9I+d7wuWrFy7GqOIlxk27CJHiE5Y6nwdM6OcAtkT1v0yCcsvop9ltlziVlW0 3n0nJ8Icf7QX85LVT4leFW1qcm2YsnNUGy14xBvjG5i/0QFDjrvuFqCFYsu75UDFcHH2CNlGdMtD dGfFxJ0SLqswZFCCEbhRJmgYNReUAb7QK/SPpfx5WCAZVVHNsVNh+KcO0K74IDKg3pR7xm5rAVXf 1joaAkkSOyven3YzxI+yxF5pY/AjpJYL3PEYoqcv3XCJCseXdxcaCSYKP4A5ZHkemYg0zwtLPuNL n44VrrWvCXdxF5wot8uuyFZzMEnwKy5ex9rPtfXT61vKNFENJcXhDHQ2ZRpxggRJC0KH3IjtAO/3 dfU+E+If6uu3LUHPN3f9sq+kiELQveLIv6BUpLcfIYewgG8jZDGcKZ+LRVjgPeHACJ2p4FJ2FON4 0Skm+J4tdJ4xQYz9wdGLM7S1hMklx3EgYTlfcYJkOzO2fB2g5dqmp3WfRCTsd9EkovxZweBEhEDK NwQcaWI2AG1BOZJggJ3klKBSfvLJw7dMHhzH8+jiOi9pfmQki90gaadJsYkybbKk7CM0PbWSLMCK YiaJLbfG30jhYOUzZbLCCyes+O47RGtF/kqPSeTP2bbgLVHcXwmSbm8QNjj2d7XHsOG4H03wra9w zAY/QBHMTvfNUvUGnFE7JULtn3OEQPo9PJGyGlijokIEaHCjMVkH+9oS8G3kH2ORAHvYIWlS0gtG ZwPxSU3R7DRns9xR6XrmAjZd/6ecfIl6Y/L4cLnPfaHEjrFzsgYhAY0YwWjT0osVpqb9vjKxVGlT 4Mo4hnrkdEsmzdHfZXGWhUXsmgoJ9v3v8WnkOcNHSELDxZKDojGAnFTjAhbZCnNZF3EnXm/kF4nA FjGO0AThreQSiM0RQtGQOa08mD0csADgEI0/EFRgthzfoB62/hL8BDd/Ig1gs1ynr2/Mw25+tUg/ RoVoHCgvPYtB0pOdK6xokCtnlRiOwoDMMHQK5VvyKj0nSnEd4C1EiT09HuuKU9/bSyC86S1lxLgG kOXh9kCVnusx2uElj/NwwXhdWO/UAVkwyAXeNIBu3+5HkVjJCyjqxe9zZ4YELVVywKfb11KR5Cop KKNkruhN09TYGmGdMHfTtFF8BFRYfxtWBP1XBuLj2nsAqF76e2X43HdegPpxRdc9RcG0jprZSOBS h7G0k16Purce01Btk6rmg7Gi4x+zhjGGh1MV0GOLkUvAF2U/0m3cQPxIGkkSN3bEGgyUBB1x+IWF jO7QdqwRIU3H1JpE00cxGYEpWKMzqjxemVZQaF4wOq6pLXradHYCIhFYRJfhqfCx6m2+05QTTjqk dqpITf7KnfO5sRkNqqWkdNHqNcza74M1RKyTIJbo8PQs284rzKlQA9o1QpHpY7rADV5qUo93crox yB+Ljl/eebmos+YycgbwsHAQmQMYwzDRIG1JPbwzgNhqjjY6yfISL5btR9h8osgMFtDizL1I4xxQ Zt8vBsz2fpNp8+OtQabG8r++L8swYYRZJOnwxFRmYCT+Z6fa4dPQFdFndYUfZOOd57hApfl9cSHk 5Rl43Hy2/thYwgoGNNf619toR5FdH77JymTDZh4M98xR+Wch4AojSkVDZpY+BfydEhxaRcKoH1VB Vb7jgKNM9+ISB5i+VIvrgn8jxj4LplpNH9iRbZrEe41ivfvAOvt2Jek5qjFQaCfQL0tShzAkGy4X tgFZ+/atNlK2tfZRlmkc52dlXJ0SlhYfzc9dDDdZ37awF5A7719fhoicMvFj2CKFc6xgx66viOiR LTBrVFvi2+NZAAUDjtX/n5OkfEj6ct0HxE7/Y9vBnbDW0/8PAiAyPcRKk8fI+lMn37Juh1u9X5Q5 jBP79iMBxJNIH/fZTlIMwZYtXIihCHrOTAtc4bOf+KiotqzOBSOIzEjoMA4kD6Jh/8S11/YIF+7X 9ULS4dVB+xo07h9K1VIiG0EnNQfK7c430Y9oICjJqaBnv1cAUgppISuj8c8k4xBzzo90VaprJVa9 vM1/EMZxp79UpSGzhMtXVCWWgTjs6MFJ9N+gx7mikBU0XkRmbffhYXAotGwYDf+mJJEq6oXZkM3Y 33D8PG90OdTYy/tYb9nPkpQTerKqwEIon3VJDR9zWZT4UiC0YxhoG50oLIsRWqhBDdzX0tz/EF/h 12BEhP5yiT9hDgixxFxFmjbNvLfjkrfn87svVVeoG44YkgVhZVGj+kNkGIv2CUw14OZtwTey0+Ln v80GUow5Em/TIF8A8UMIF37RKh/5EfElWYTmYYVeAw21TtAuhNbqvFl7wZzbGhWmUI4kgpqVUzie bvBBzuBlOM++qn1tNk9V5MIY9w5JgIaSQmrtkfwsgo6WbLzaEM5O/ia3d+cchuWB40VQPRg3st1S tAPPTaQ1YwB4po//wO/X3u6xJ7lPAGypPB6naLYY/96WpxG85B6pgWNREbkQuKCuu/6ZsrFs+KrJ Vc95d3F4/4UVoM53Um+Grn47j0G7RHbymogUGg+lxGzjEDXtHk/94vgzYqmC2nQeUR2VY2I/ibR9 UiuUAAZpTa0m6Bhy0Y0vjz+HKHgAXUODXOrA1/rlH6g2kT9qvVUNDdTciHla3PzTD+g/VcNqH0Um nlKrv6+ywM3aG8fIZnsWWiOh90UeYtGpe1CKnbrppUEh+TEUWA047h6/YONllMnoAo4vC2VGLyGf xBdNAkmVx1TRIrUbJsm4WTbtiTYyiV9qQg2b4BqCM9JG1U2C8OG+/SgXIhanIvr/yoNEt8dU+oBC PpBom4tu+hoaLvSCTtXD6ok7Z65p/aFK21Jyi00ZX0NhpS0dCcn+Kcu2XelaVgZBrqlozvEFktkk VyeG10qHg+5mpg55gtKAg1ia7fDV3CJOzrom6SbXawG1FyFJtJ6xZlihFMO0vK5TV7+UXi3OAEib MuzSRk2uQKYtphqzLVmyaVQIXgY2d5Depr68tGgukXBTeFUNxeJMVIjax3n4UFMR23NddGFOXHza ZJvwgwhHIUbA/YLSMvEXN7owWX7+4cvaQnzox+eyYC3RgUzQnhs3Aop7ulkRdOkfJW792YjBxnym 7kBttmnZxjt8PPFadS3Hd5OPXEQuFIFyFXE4X+EDYA/a6Mfaf1SeixXuAYqcFsrRMFSf5VC3UCnd 0pDhS7NxGyAtL65z2bVjmmUrpvTTZluTp5hJ6dwdwFrULZ3XqMq9ZINaqgXrfRuSLsAH3rDZ1SdI YE8jJD+wtdOk1XCY8EAIq7bTZ3LtBWjzpHU2LdmOZl1WCW3etvMY4YLtvLpLMqa0Cr/+Vkzf2T8f kw7tIu9bD/gXKHdwmyhl+6vT+og+pJOJQKIIBuNfYcHzEDqZ0vtLtlIKrcSuiJjm2+OUj2ZO/NLR 3BJxiCo3g8N7Pfcb+HmLP31raCiCAJBNJHOWOSK4Z+Fh3auSaOZ/NzAC9oJD8xjO0iWse0krDwcx 619M8BH80+V932j2IsGVcByzi300cSr05zDi7gDKxXzLbmNJEu46obe6ZlxYs6sya0LIKgAzgGAY Ebn7TVYUE7F2NFRlULk2h58MJP4Mg52QCrwtmzSbT0wChcsdiKZeTHo+5V2D8jcOGVzXRztPrLCR SE03IUBctCN0CCeb55fpZzVBXoi6LVC+kh4DD4FGd6PMmJ/VBvccwLL6FrSq66xiO+/Qtsf5wpE9 LRTKeRIxWDVupBj8coXjmjbr2AhSCLdhRbbPBMQ793RlDsfDmWzz3bpFlnI4LXBXat57NdOlrFdo YR4LGDsMmmvK6KT28npSJVja8jqvIGEKxYe6KnK5bubH2vOyC44VMWWV1YdCqG40DDbltqHr9o6d 0Q52xDsswLmEu4dany9M97SBHFJAfjzDt/bI/inrRPS0vJIXJVvUGAhXnVYYFSZlPWUsjgWrq0Vp MuG/9dwe7zGxBFZdRR2Ebk6A7L0yoMlrXLXsGUf9ZcNc7KBjd4OrGa8Sz4U5P3QOCEN9Bs4I7fmA 0W91F49pH7xZv9aw3CtJ0X2IpsvA7gVDrO3P0VQdOFbsNJkifC9MBfkGssCyzYt4GOZU3Zoev130 Uzz+LQ6bN65MwrC5OdesVjF6rN6yOMGdtYxy4++o5a4C2rqhA3zVlAhaIFS+uJMA/pmoWyztKjLN dPGopaAj99Z0/fvlou2Ua7TZAvvTqAiKArVjSeJoBXLnWV5ocXFmy0Xa7PVesQ7wGhfFEm7UfYl5 vgyhlNodmd5jWstmgCoMc4aikl7tAgWbyf/wIen8WtKds092uU0feGh19XACt/vPDOYIz5jVNRx8 l+visr0FNDiBQe8AxCUGOgDqLtOvrHzww7lxcbd1rRnRrML94sdglg9VOgQM1ujV+ReXM/GW0X+v 5+jmaBZj17AckCrUlA6uS8tE7eEwrO8Dau3XDWGQnWnIx6PkKi3QKjQpW7/39eAftD8tn32NOkH+ 52Cv+zQ4YxbMLvuFYwdUOULXp4r3Y/O8CilNBCW0NXP3k4Il40Ul9MYFp4FITOZTaUJEMTz/nL4p b0iFpnHi8cLNqSzZFdDw6HLl5eM5RUfb2fuICxGM5IIEqXp19xnXTXtN7pO99B0GLlCx3QK4v4OS IQQlE2SMTvMt4/LFJvb98AMrH67gC9zXi8Gg8Z7lafL0RFyv+xyoTKvRn4vGtLBQ4ZxYgCYZw1cX a0UCI0e1BGJ9h9nN96XPE/fI6i2OPUA5rzhOMXMd/8h8FnzD8QSOYLkHZXGF7BfluuEOCVYJNofT ppqV4d1RKJ/e0OvEnNLtN2fcDJVwH+sNDrlLYhZKvo7dHgX1Lz7x+FoRX7nTIl3LHDrE1DddUIN3 A5xIaFmumr6xlx1uKEWr+EqofevTGj9eNfkglKkK4LNOnEDvoLoECEph8hqpfr3ltg7F1h9ItRQI DufRAtjRrEEPXMT4NhTmlFUJJ4eDZMzno4cGU+JkevXItoNDbdkY2GmEuynHC6NhT9ksJYX5I3P/ dVBcSyGatXhu2Uiye6NRmua81nzHBZ0NmJJb0Txmdww1WGnqFx2H1aN7sh0sKLgvUtgfumJQrDpK 1I3JA/diziRgQjyplDP/MGQx9opEkPM5ZCnxkcE9y7ibhoyoErvI5I4aYojfSzM7KkaECJ9RC5FV 97FsbOBEyrAtdYid5ROn3xEMvF3e3o3ta/l6KBn02EHsJtGezHRHcX4cw96eqbvF5VTkaou828rJ iwLP2NC9AvdZQgSFK7X+NmK9aLOh0By29V9IcLRVOme2S+RcPt2vzXKZOV0AD5CEU41Wpzx+OHV/ lu4PRLHbuGPrJCzo4Sy0RKw6G6HDvSKEhQJVkC50rwH5h0E4JHSvDHQxVT5V1Q05GOzpA+OLGAOY udBKh8L4JVkfF5HoOSJaUKwMaPVTO3I34VplSSl3zOJTNRex1BEtLJfKPeQxtyrV/DuzsJLeyaDr QPxD63XFzJyWlIiovYGbQC2Qf/T9H5nqM7048dXXIVa1duTwiSjbag1xAfAyfiXlDDnPaERwXq8u dMEhUXjwCndLjrk7kLF5T0oUFtrcDXisEM5te9BR1RXYc0PGpeBeWKpacriFjcd17FQEu6HBoSR5 eQQYbjTcvhs605K3TWQPd8gzzXhBxlNBxAucaSoJ6A1bmZFeHx17SYQuhhjV3gy+3yxjTeUIF/dn dEXzLuPAY77HRR/15t5z6IUa8wGpNf5qo7lj3YaApZlXPHvidXy+J30zhshP2BgdwEboYtt0XkWo iPkSZ0kT+Dig3ldxYVg7jmJoC4Dov/+iusXsIRcRGwoz1koI+O8+Skutf66Lx8Q0Q77ISExraMXy ToI+f6nHQ9aMjc9Dp/O+7d2rmcXR+eLcbxmsasnt24WYOnKNpqEUYLJ9y+JDDz12ax0dXTPf9xiD yg8Fv6DBu0UvE6yWwoiB07iEYYQgawOpLP4Sg8/p7TRXl5h2cg0NRncdvy+EZmrCEnEHMt3c2AMT LSm68I2kn1nPasuI6QY3RdmS0VNCQ0yRw++3n2/CzjmJl+VpmBbDPzygXpfPwDs+YNV9JMIJPHcA x8MSNq4X4VHANPHaLHHQwjVX08h5Ccti2JeLOpaXMbSLbn9gjlojCf1Zt80GJYDk5Gm7XT1Fu2m7 VYXliYhbgjFrlJcqkKCkEr0dH++w7LLPhr4+yn4fNVov163SUTe4HsQtIBpfDmnyurSHxeyIxN7l oAFUsJ8cKHpST3xqtLmklI+ymfbNMl7eKqUNOidmg6qj2qyoAXW32NnRElbj9xqQ8xTrNVvVHlm5 XbqMfF/c6FD+J37KuApDk3ygU4MN2ro/dFpK1oSokNs3yilyp9tm77eYMKW7m581GMHVUnuxHib4 9HzO06MGPdxSTXqz0e1y4GLBjkVGRlt5XLRwhi91innvAw02MuWwcpqXZRdcGeeC5OKFv41r8r1Y R47pPFUG6OHJtw+PwnDtq4WLyNe9g3gSjiSgigcqs/dwBWrVl/ObOzN2GCupKvcQRPCAr8UTcwtO r7b4UTM4MoYbW2eDd4C93xa1qdE2dy5BFFtO88sScqfxOi9FvFaGFoS8hvQHrtfXhKGuJ1nNnb0o wW/LGRp7307EtHj5CXDLvodmkpA8T30nXQms+RnvAOAB2QN+hZCyih3lLN73t6JtDRsKUbqyd8eZ 3qIdbH9Q5+WyyXpqtOWPjGqHdwkrk8lnN5MTQMniMAHDYD/3L/RPvLZUWOBuC8CIkY95x+MYBE2O 2xmDxYw3c8yGxn1KpEcPZaQAXSx2MPx1MoxZ7/UcJvfOa6fO8qqdchIJRhvRdf6PZb6Tp2JCiFIO Pc/8141m8wCj94asz72kHLRCe7+fR03flXzYrDpiMHJ9pKYexMERQGzj7CxfuJ53t6u05+e1uspG mJ4boQsJqoXYRW/CHtg7WF718uzkxYE0KNfi99weSO6bDKjIOu7KxESuMomKfzpjU/Wyy0pfjj5a jjk5EUex9Okrf+KALV75NSMzDLGaPRrjhlomTYXPm0Hy9H7T+wAOYjTJsVUqCxgCo76K8frGo20x gKyZRlbRCJ5tq1/QmzJkgo0URadz+BQ2o63qkvNq478gKJpOQd9OSEXSdt+LfLO2jnqGG4mlRjNX y7POJRSV5txU0t7EP3h+qZzPftDkz6XHbwXvraaU8atkKY22LKiCLK3t2hdBeDpi4kYOVqC+159P mrz9Jpg3Gg7BwoDyzhmAVgVYWA5ba3njlcFeFDgatvt6aKJhuvpgtcUcirblJvG+2cKoaurK5INR fPKBSTDVupbedgaMqJC/xppG88mCPGG2bGf/zgQnDKdLxLlQMnPw9XwHyXgXzJpdax+TNpQnNZYR ibJCwmuMGQXDvjjxW4Z86pCc2O4X6JimxI7twFSIjExdVFBIMDjELS8QjT9s0FNGIUGpKQO/WF1N vuGcZlio7rOT+1MD8b6qYuNno31aVbaOVzX2lgFZaY6Sm158o5MKAaaJ5qiA3N8G5ED1fFwQZUjq UfwTzp9QZl1kc59cdMlmsGr4DI6JzCRd8Nk+YA901bKbIUS5AOnsg5sEjCcuXRl7tlFpePsdK2cz acazXJT7EQgoOVFNInSfnTMnPZAdnxmtPlgoWOhb5Yhx4wSVhmesny9lq4YsI6hR4HPm9yo/VoSt DgWvvJh64UNJn4z+FpmoLetU/G6FjjSAuKrO8ypKp6SFQS5sfMBfKlFuN59UKhazjIMoBxFwLYZI OFgyTVRU0Uq83D6ai2zN/kiL5xhVkXMiDKZd749yw9cSBV7xp2gsreIxrFNyTzWeUGx9B3ZuBerW 5OkgG0CqN3AHtOL2jO88g1rszoR9N6mA+Xh15lzUSYg+IsxhJHCOGgqHrnb0BezmO9c/S6KJOrsy 7nyG5RbYfhNxzs9ldRE6IgJA05IYxFOrKnnoqBuUrNcARW6LIVO+BR2FVkFpNTqH1PrC221YoscI sUuv1HuaWFgP6jEu3SAwYweFKQlcWGKsMiJWFAS2abe9J/4IDh4QFObo8lVnudJEDQWVGkUwBgBf gw05n8uHPhcB/sdZwm15+i1gsInyaPfXqYkoEy5db/GlLP4dEOFKu9YgfFtgvfOeYZ4cOihLcp/L ZxDFKxjbCbcWoX//JEEFIY2IuqPSvuusad7ZXNudhNm1iFE7SAL8Jdrlh/8mcbfNU6U9Kd5M132F gJq62850uDwzi657ano6rSXiy95+IftVDK4Nm6TEjxLtfYbE0Jv/Rt3a0l8OU1snBCWzUF3iBbPP MhxuQlg3PfZi/SrHRieDl5/XCjjQ3d6GU53H8DT3WlhOt4mxkwRJktMQKlLhuLaNYXUMDnBUmnrw QQy/57Z4GgBMBNFWXG85u+0SLWFbuFQJo7YcypIoiILi29H32hJuJuxPY3Se79x1eZ9c3C8RBPmA 8/2JZBv/8mXdYGFRT/cMUbd/ldEaat0dLkdVga64/ycu/pll0NjbNzRH7IEEa6gPmRLcaMhyYuah FB8rkKMg/CtXZ9ly7xS6SXbndRF12DmRrM0P3pmmQ3r0aPgkGVoZ2fD3jmAD9bMZYDIkm94YsW5Z WE16y6oIDbrA0HuLuza/+wzn52CX3zmXABohpeN8yOhtRum2us2osKeo1u12QwfBNw+zhPaD0Ntb U/mY/znEDKcjZpaaCqhPdg2/bEY4osVh3OxH3OkQhTrpuVHA+WNyipmh870KRXKHtcB9t8zMQ0xB bra5ufey4j/EGh/MFhJKrs/O09YP3m0+XGEU9fJOd8URqO4VXQB6JP/IbIy80rSE+3oiAYo64Nws 2MgFD4ei0ehR1OXRl3kQRMyCvhd5V9AnG8PBERoGIhtVh732jrsKM2ToYx9Vsl1s6g3isPkuKQKE +fegKab61D8Nu+/GVsvOiIqs40pDkUG3+Tx7FUaQNG4qkYtUUjuoZ/XPlkyuLnCpMY6DXhFEGTKN hJurV6Hde/YNCfAO2d4MMoX0DSAwwAEHyV60fMNBbutvzrdQWf5l0PxRsQi9scY7Rya7RlyN0AF5 278jV6tnP5Mo5efEUSkS34rruBhBVuWf85JSeGybskr2yY+NziDWeOC0QlpEmbaYti/FyU2BVIXk UYmLOvCdrkw/MIwl6zOYaMnilW+T49AaUXzMjXky9OaetV6uKxpWc0UlfN43tAWBJhJMDXiu7i4V xVAeH2fL/KC9YrTfbuoGMYTLrVUjTnRduEbiTJGaU7LIFPmUNjUy0Fj9k/6NRhJfk4snAH6/Adxe n/KaWVu9sSdh89c+zEkiefwUXmu8siD59za+o5Yqp0qeLj3Xo2drtXZdAnJu2iHxTJ+eiyPkvIK5 ZsXVg9uQjnZep+7zZMXZ+ghJIn5CGhaepAb5AXKeWPNQf6x98h8CEfDHr7rQ72h2lk0rheabaHLr 5q6E5pDUKmZzWCvLQ/pMnJ3TpbHccAgfV+RJQQpiaHwYFc8q69iN4Ky5vaaISd8e7/lPjJgg/mzF vxLa2NKW9WgSUBm0df2J07c7Q7a6VVsCIbH9ElpXNPl9C37nwz36aIQUgbnltRMCmUo1OR4/BTOJ rrb02UWPW4qjNBCSxU5L+tkFKUc9ptZ5A6Txp5mcVgppG0oM4llrqyGgIdDEkmXb0gLny3HNkUQ3 qLhf60Z8OZVTOmj5IzwThiu6fK5f/6D46o6XQklEQ6qZEaOmsMs9DAtrHRlxYpoOkz62NO/RSduu UgLjd9bNaKN1B4fVGn7VnQyKXWsJ3px6uq4qjJTgYxZ8d1t3cO5ZZvaCRSDS0ImU7bnusxXjaLff xBh50phs0i1aB+n625k77IFA0OXHeN4YDjcVExpak5x8RBap3YzxSKSurbnlST4ud2z6LF4RKXOi zMAWoPDwcYrHLnKze20Q3vrhHm5r+UVnhqpIS1TgmdxmZrvAjDB7h3S9d6p8ikOYHAxhQoJpBLfe +g1QOQKIRv7Y+e89AMFstpAy9QZ43HN8WiM95sW8ivMkq5sPk235mKknaAkqRiONi8Vv+zbrRYpa cLIsM0tIlLAo+aSKMckzbZm586thg5iIHruEUElUrk5+J5dOR8DNqzvulHY8pZwZQsdWMEhptY7j QuPkCJcAysvWDsnHXDkVry4EXkLEDbD/B3wpxePWyB9Vv1X1vKMALzfmrtdUg6ie/VSbly5VZCC9 H4/Lb7HATZb+sfu2yEVkuIHLj0CH+K/10wr2W0rtH0hh9wQRGi9DLBLXvqRs3HZV0LZYXcvr/V8t fVUhdvBno6S6vLq963NMxNkqe65bpIrtFghH9jmnuLpZgjhOKMzMTkmM3giEtLQzcO+Jv1fcXWJw 3uRFsaQgioTIchli7R2bgkchtSjqDgBCVCmSVW+xMH+b0b33+efOClh563fbs3apdgdfqTQB1ZvM aAdFDp9os4yh7clMrgLfzKjl8I1kssonB9DXF52tCOLi6nVD0r+8tNwOfQJu8fuS0xVXTam1zYtw dzBKh6l082o6p2PHCcsXKFxIA66n14nFV54T036ken0aCXE8Ue781xsFifm8mMF23Df3RtbzTUs8 fbx36cS7CRw4FOteuN7VuSgyjsDBUAphqRXx33xQCoNBu4Re9Jvwfw6qrkCRn/MHuQZkCltB+d/o 0+AGbVdKE3uYgFYhA6ABzxeyrhaYuUcKcA6L/Hf6Em6pEN5/hqObiW39zWUG2z05iAEf+9tHkKca wTe9+6Fj1tlIZcFLqoV7yolzAJiiNzpok5y9JcPWHfrIjn0EgLAiM4USoZwGv3LiOpAUu3PBFosG nFFFnfvFA8EM4qtKJglWvzNRBliy16kS1gFBvGmbYSFAZ81VW5ua8UTamQwfKqN9urPqna3pQQyi t/BGH4mq0IOE8uMarbKxUHIqRiidVxDTHWCBjxHbleUGvUzEbXARphyAd8mzDenUpHYSZXveQz9B 2BLO8t0Ab4pV1kCjNaoTakcU90/bU2hoXZvQ+H5xLsQ5JL+zWOu01xibdgpQSXkWAp3IhX7D4xO9 8QQ2wOvbJcG/bfi9fCzNCggkMPvwBXWrP85ENMDu3LbO/Lvow5bGgPzLUjFpcbft/ZDIOmotCvJr dkGQCMGOSLI1sXptves9Z6h4KYiLLJuy+GkIPhWSXVKji8HQcWoktChyNBXGY2npHW/T6uPFGqlz FBZbn2TVKdufUPuhJ80LJzyogjPloUhM8ZNR/02IyGI9erZflbvEj/1su+Zo2m0bKeMdKbBHZoLW b472IR0S2NKxTMHKEKjrN3Eiqd1acybylQxEigoB01khd/yuDhQdfC/NnLn80T7iEofL+htYfMhh w3aGwVMN8c30SwftaD5dqcqSwVZD14zz6T/yAm30iJWxTNU10px72nBzQUpLCUut5yvJMJOawdxF aq8MHLUNbDuWdYQnqAuncMtd337SXVrnCHTd2pYEb/FgklwdqHRPRHEmtin+Vy7eGTGjsBKvffGL LRz6lhnsD3hOod82vsqyU1AgRU67gOIWniY7VQc2G83lEiB1vQn+MEbeDXeUcMpweYobJUtFwWDf 0HieByk5d15HGHW/S2T/pvr7a6ZBB1Duw89eJ2fggKKuXL9tG2zHKn+6lNIPVleTwAWwED/3X8WO AR+FLvVQXP6E1o+vFfDcA3EjQml8yWjLyo933bfbRQSgjN7s0lbxYKQJXsHnPK17mkA7wBkifpfm PeTeYswh+4rvmZsTe60t376j65fG4pmZhH68jbrBgbDa3TFgXV/eQ1qgKQLlL7Zhhgj3wrM/TCRa XSf9+3NpgasGiWyz3ZAeRwupg8spMmXvao2B2wbAHcjX6nfJeAt/M4rB2iizJ8f8F5jr7Vm8/Aul P0arHfewSPpY/g6DR0Gr9fJWVf1rvao5YuPqLlLy1UaAvWoEomog10Oe0p0axOTy9g7K72i/Oi6j XwcRAHDuClbpuYQCY+9gwNNwXmvUCEDRHyN0rQgNcn85v/OWWqepq+ertr5Lnt7Mm+zDtqkwMSNa 3iFNlbFGCAOxFe1RM6i7Ay/ClbdrmHVImE7tMR+4XxfYOe91XEb0we/oOAxIdKHh/oCFB87K5vlv dTkvi3/Si6HSV+eCZuSnrzbCWF4gntoHe3W/RTo3giOTSAbnsp78dhdXsjNOTDqiwcDbPIFncZjH qD8kSqPkR/TSi4lkAlRweYTKK8aFtGcQo8mqaBRHdf8qiRN4oM97zoKMLHnk7so2T72bZWC9sM3c /iekM4Ff0PB4XUXVc1NJ3NISx/AcOIzP7NVx6Najn8IcR9c+Y2aLKeXBgWWU0ai21yYhPDwi8W83 n8qwEq2yalNluVrLSkk0JaQzfMUGBH98L3vF2nQoCBJMxPruoEnEWzgDPHM3NH20BAMUrfCP9Uai H2XdS/pFv+J2fG915YVwc0TCfHNGSVGPdh9IRO4NWnBAB+Tc9jzS1DG7R5nLwTgpi+NUsFVP843b gXOwphVCiOuc+ibynVJDRQcMYXWdF74XBz3RSv/dc4jUEHhlG5FwktOLL8JMS6zkqUf+njT/rXGZ YrOzvYAZoBRRA2hUw+7XV7gTU8iaBhRxGjyiHycNrdafkRVyhHD3wbnSDmcRiZdHNyvRwN/qQ+u6 NiLoeegFPMvdmDh9//1Qi5SVoczbsBxoYfJWvPZ5k5nx4LZSFZMItzz68gFqjYbZ6aoqgoHfIkqv bQ6tNQWPFJTkytA2hYp4hP3eKVY3Mv1mVC5M0H5vYQYTsw4BuowJxjk/4lVRVaCPzG0izVqRnl8Q qn2sHKy0oA1obDNvR9tZbgXnhMQ7SS6G58Pc6WWin8fTdVVO4wdbXn8wUEcKswaJyAsYxccAKxDJ uNjuw2E8R2iul+vb4FVEyPgBu8LIxGPE/xvlTAYQPLeHW9DJDw29wU5hrkZYSt9GPi0JN8sMvXaC iJ1vfcmDkh1N0sLrTEBEWqH4pbwwP5EyB/LnTRFXbaxjpYmiEH5vFvTdtWFgmaXMJmvkiN3tDeGJ z81VbI0SNmooJpDGq9v8fktWk4hufYOZfdHegHE/BR/2JIJFeYDgA7I9nC1QCCljaC0LuhR05NRU CtrOt9ddXT8y2XQD0V9uuZewHWHtv6GITF55xlalg9PjWa93U9n8lBshP37ep5GYURtCQKI7EIuA VIQzCDFw+bEo6ufQqr7swkrFI/WNvNnORylEf/u1SaAaD7V46dNxLh1i3ojX5W8JWyGM/0N3sg4C +e3ocIcSdU0/5H23fgO+HaGOKlGWLcq8RLiImhx6+Ih4qaawZt9hh2E5cgjCZ0R8jOKqx34X9N6v aIyQzt9HWOGIBP54m2mvEkUPa6Nke1YoUJES81o3GmfLarsjEPVk3tgctcqa7CIWL2B/ti0KRpU2 8tI/MRNn75gRglWx3jCSrfkGGDnhHLlGZg4Aq6ksEIIiWt3uQHmJ/ZVVd4HrHbtd2m1KRrjLo3mz rY4BOvBGwW/NLXM3dDl3s5INSpwa6zwKdgHs/x3RsB4SPOoI454DvK6IhsW/P44IQivj+RUxV27M szw/hmqWtgMjbCKCZ6vLd7CpRvhzsAacZLnytKnq4xElvrhvfyl3QlrOFG6ufHgnpq0cvaUNIbD6 7SikjBJTqvkpUkf9j3Ke3d5kM5fHlKGB5urqthbbjHlfYMCazd52c23sFwLjETbv8v0CApKMM0Q9 KTTUkYPmKvLtXmAAdFKensE4XiB2sShkSuLAqg3jMu8ROvVJZyfJKBgU3yoI5yfmmyiyV17g/Bpw /IoU5L6TAyoIaDZJ3rmPikNHdjrD8CUq5QwcCIfEkRk5LwSjC9fL1zqxAnqOJ1bG/5mBRl2iSRh6 b5T9BuzoEHOEmT95B0JLsPcVtlMpTlPRoHnjyBvD3tJBvy9mGyUrJx8QKr2q0pDNonh1J+Ey+GQi Hx1pknEf5/O1/0+Bwr2HuAWTnDz7Pl3GshCvpM4EoQTSO/NY/3IHCrYTKLQCodrFA1Hbab7FWeZ5 YmutjEUxV5+oyAEY/FFnHpQvL23wvPzYq0UO0ezMddKQW9MCMCY9oVLFSJLzESrinejF90zg/EnR 7NfAtSEioBVmjlGBl1iCTnVVLGx5JljWiZAdNvz2x26fnR5jUzcT5wM++/VKzwoZLmGCsLiWVfI7 9C8Pf5AMvmVHGV46ZVqgZIEfjMoajlqwHyLFMKWgJSuvEhxjyNyu6R8dR1DDqVniAcuv9GdODP7k t2Z+eqzumIV/dOTCA3D/0l4G09wAkMJwEtNBIdheu0FIPSbjKe6cnw7ITWbra0fkD30H5ck2UTog 7OVf621lrTYpqRpRpXoE8mbA+cFEeLL8xN+cVVxIflCm3dLQkaKXoVYHS1KKF3PYvAxd8mQ8tCZy Iy7CpiqF6DT4Mp4IFJMPnmUUblGeYhxC3Bg5U9SiJaBIQNS3DI4p+teAx2HwnE5pstwd61HhhgTt SqVRHlbDmLRDW6y+C2u6awVOxJRLI02UgME9Gd8ytmd70uy3huL1x7nR1hRFDON3bRmloX6KT9g7 TDZ+dnUGcIL/tVe0WyNuat2pGhuJ2ChmWI6Qz5yJtRAtzRqdB+ia8U+rvW36Jz6x2Q41RW1ZfUf9 pIhVh8MSbjpBYmVhmMlT1D+B7dcufu3PRT5wPXvPR90l0lTviMhWElfwTsxNYn0wfOJuLP1fnoXf SvmE0cbEcjYTM2KOgmNs/upK1F9ktlKDuRs5ZDQvN57WHNsuYaIVJzfG3yvL32i+gaT+jO+iv097 sdcaFLr7Lc02c04gR7ZwluhJJh2zqPU613kz+y0H+/om452rM7ps5FQVaNAU6jQGLq5PdwvSvpnK o+/DLPGd1GOnjsC8YiLH+4qQ4nCf88sTT3dW2HWVwYHsEFuvLp437cSrn2KiB/K3OsWJ32jZUUF9 E8kB44loC/q09Ub/If7X1fRcbExRa/xBQfmOuprIIGuK/z6wqQOCiBC1xjs9fs34gk8xNA8d7Uwu IAIF8sg3nRD/gFibVw+/8IJxpxQ1Wmm1BQyohuxLS5cGiDY5Ap9z4Az2r9+vnQ8vpeBC5pA+1n27 OFSe4aZ4XW2+bUeXn2hdS7El+dbOXRrvm8bflkXPjb9a7It3NB+MBabzjNAkN9U7k14mTgY3YwtF yUtZ3dv0ddhnTpEaQdG0bwpwmR2v5VUgpGkVzY0voLw1RiQR7x73d21Ni1Y9vVZNFYMVeVN7tuCn Xfpo0+K6JBS34YjzNOE+YeVI5mCK+qVYdSs3h7BEDeNtogXPxb29CzAiabGMtoAlDX2ah27+Hro2 416F9gkLPFaMMcJOGTHe2jZvimlwPCJgKFU2AmbAJOcKKVKCtbyiXYcp5StcbyqU1vuegO+klkec MGjYMbILaFfRSC1+V3s4CF4tlUTxSD9pKre0tAW6bEogEl4s+R48sldyjSYhhMY51O/Z9lQx0r9+ 4MvK4FDePtMaHdL0FJGi5sJzNRYYgfD9sf4sBF7c18bVZwfphLaOjF1ATYr7LVUTfiNwVz9Q8PFW 3C96tnDtY1faRZGQZiRQdNpxhN/KbGrqQjyyAYQWBpy21q1UpOe3Zj5RGOCQQh6RZnIRDyT5yok0 zqmayQoVLByzgJc5LBtVCc7A8QCtPjlbZJdMbRIIHpYuJm+ChHoi9O47bzXRODEV29NwDGYA85O8 7Vbe9rZSnP/VSwS8wvXmjTDXajenIwjP3e+YS6xA9lVidllDspyQaJqKG23eWKvGzfTUgq/c46cD f+qozfk/a/7lBVEF0yeOOrUMawoWZ9rOTpz/89lihdfBVEn46TV/aXdSGNstRR1MxmDQ/WCitr5I 8EkW04REL3ke4bD4thZX1Zxh43czd7W5O5LZ6vjTSLShU8oMMelobt0fyNicUsEgp0zo7afRl6mB 1GbEDf5F2c9eVndpiFNfKn4aR0toV/lHSiMLG+KYzUt8nMsPKdwKx5R2ygYua9IxjKeBMr5jNEOB Y2NMI6Y0zqsCGYqbhnlADH3pegaFhiQ/NuWHCRyULZFI8VONS4dduf4clU14wiz3JgV5LNNKIMlI STTy2ARaIBpAwpDdJScdbr1d6U3zSfAq5jkkvC2LkEGTb8HrzfzH1YV/omO0olfSEVXe9Qgx6hMT qZnQB7M/QKnlutkkuG5Mp+BHGNOZkJOm3wjDj07kkv6QNE2kbMC0mieJIv+qW4+q00oivXEP8Ks9 KUPdXhebW2UmiD+bDHD2JpqvjAeImgbEaqhekxWNyBnq2khqA17Ejb1/O9+E+Sqnt/c2s+HrHvqb nO5YPB1krg9cdatd7xyOSIk4YBA5nLtI/35KgXh2Hr/436mw3hl9CLGlURZreC7Y7BqLH3VekxZ1 1NonjrXwkj7cFfdK3UI/JFv9ZXrNc0AfdbJQytcr4Hh0eEMaQkCKtOsIr/Kcx83lB/HhX6kAldwi IrkHiPiHvAXJa0ZpT31pnhfQatE5Wew76TjErFV4flVBG9zPAX53BlAxAQ3rxkNWAZAV16t+xYXn ivJ1tGYbmgbv00VSYYvmsxEYaKcohcL0WXmPzCJYHJW5N3aZDcuftoMzmSc0lm+fD6coPxp9oUQu I1A+W9n6lOi2kGrmAeOKXuTMFyGRvxc+O3FN0PxwGg0NzF5UYLEqI6mGw3X5bBNQdg1u843WhJu/ bm2qlv7yC6gGRI5ffRfqmFxFMqz6PjpIlVeAYRjZR83ORB/0fI2ZqDGu+GOY5EfU08X3udvzJVi+ ZA23dnqehbIfzxlAR2AlI10JlDrcuacLgWeouubFmbB0wWcOJIr9n4JyggCfAGdz3/asFP3IDm1H 8kocPvoSQ4lA2e7H9K6RkFGlKShA3RnF00+qT3/zZWH/fN5Z2aiMuexHZOzedeyxaLQrsxW6GmJU yjSl1okVnWdyC1JoSCvHZKPqZ8+j17dhzcfn6YNTFOFQhSdUxDeoC0dVcGwpI/i90+f35/4CLyuF wgbj5MkfvUb88kUt6Ur6tEGr0GiIX9iIUUpyCcipiu1DEDbru5ae5brWr4fIoMEbN8FW5K9LmCLC N4l74aHGlzRt1qG94XUkLmVv6j94t1i96I1/TaETvZTxBJmnTbhx7LFoaWL+IiRvGZq9TSnWExf9 qhDUOMrdfW/X/pd6ahMils4JznDcXW/+djwgUPKGILOuvjmczMWnXyvlHYFBqQ17iTaer+1pVF7s gfVzlbNlEXSsKtVaKmWlGDQ+yBIDVl6Ku2tClSbPQAI6aYqQ9lmMpwnxMpZ39CptFkjJ9VtgVJEP eE7DNu2dhddpLSH6ygTzl5QABgmSK4DBo5ruf172YY7Hqlhj12dtvpjHc/SQGaHdQhjLkzphA8mT Ezt3wheND8AnMYpjjnWby5OitX6qUVScRMEJz+O6N/NJwitSPO37szi8jWc3S8Rcb1xkt9IOqb9i FX99G8B1iQdC0JPVw/UG3i0j2Fx/tc3QF2jrSE58oZWE5wjx37ajcxqA6q/MOBaby54gAoQeheHt ga48GtF339Sn2Ja3aGMdEVJo9Q4IdITMWRu5axxfOLdzJlVRTHrCEBqocFqWYP1tOdvCbkCSFMOK l5ReN24Yh9N7/AJ8HR0wxpDe02a2yogGEhH65bxa+adCsnQqNZ4l1uyytrUMj1YtvxPRGRO2V+3Y ij4TFGHpyGb8tfdCDr2KxLhE/Gwy8WKBk+Xvuno8tltv8GBKiS+2OdEpkdivkN6vE2Kqhg0AKypO HEZOm51QHdkNBFap92b/aAKjLVYO6LjGM4ZmSx8ZLcFIbgv8EuimVx37vx5k+cpr8RZMQkaayLZd Iyz3JrWJEibPIQuJlUzg8GMFirG69/bYCnu6qgpCNJrt6/u8u9vZEayDUn7xRTDGR4/dKqtTuUE0 R6cFbpjQn6edODTxnt19LBfo4+8o7rsFiHEPOXy/42IoxNP+14gG/z+6Ekui8TK4NYI4loRub/ya a2iwggQ1Z/1HzYLnn581ihM0GdAB75lXHTMI198iIo7JFBngyqm4IOkTawPpGl67gOx5dwl+SGKV TOmKHBUaiQcmFTssN/SqvdueJEwbedX9MghwXU8WAb10a1AtouOXk7mKKfGGclWLJ2k6SlEUKyqK IsmiEPg1GA43tAW1G7RtGRQ5vEW5k0OAga8fY/xqRcXRYALpL8gDQDyRdMhvhOsbElmMYRG98tgS x4wW9MNCcO6nMglpINeacWaGP+nRyXeu0JeFuOCYej8kHZk5TCxC16oO6gcbKUHRWsly6P9MpBPX DZLdTHZ+rFsA7kLZbqc4o+I9Gj4CiBiNrq8OnT+a0zRKhdEy9mOPsLhZjWk5LBFa4xlpL5zuQskK rP7CtppwoF6B+iqF2L/AVBeHlW2UstRjkBqKaOgHBxKxZWM6GyA/Da7Num58ClyTAgCd+spZBXJh JfXPeXwlFqT7Z+EkK1kTQb7lwJxdl8oor2Z8YVJVgVCKM+FC5o7Apeg9CeBccCCpguu1IhdEQ09t USlFPChsHkIAAYVShZbI8+k14V/SDphqcPcv/uyKzULdly//qO/zdf9vmxQPTSbtUr5bX2jir65K DBDn0L5WcR0zxq+vaz5O4npbZOE/fsaXWD9CUCBvfj4LQJIgoLnocD9fnCq9WGoOCbZstQ2eXMjG oRM/XVi6GEXQSzYe/5Mn5khwHHUP5JFYGAe/jj9ZiPVNVL9e5yi5hvgaGQPV5CMevU0yt8Ugnu1F 3/MDk6xgnZ0rXarbdamqX/v1A77bfriPpfqjmTYJmzLGt/izw97ovYXyBECYvr0xAmDTCQk/loOM VyAVINK3Cm9eBsrE8AyIokyuPATNpPQ07wCOUDCWKLQ1qefOZ0ja7DulKDsCrY4SWBhygdNjsSQc M8lZAJc0AM7BrIjhUBbJB8V5fmQMBol+HOS7lL4DlBkXTJgSEm065aj/SOe1YSjCDJrSwdn46BIO U3foz+H9VB6Sz+ht9JB5/iziBnNF4NXTZtc92LbPeIbEvwI3xgio34XR+JFbSadEchhOMSUl0R0x UQhgkcTa3eF7K9d4ceupa8P5gxggzTJWS4iQ3oi5knuoLkAVVwP205D22pcWSUoYprLkyh3nzSLd ckzpofH1/tWOxXZfDMxo6xYBfCIbRmOBAEWjtBswrUxdVlqPV1pCaDTCKRv6az2Ia3XD8/w655CF hISeuj/ABE8vIEBXh7YHQXYJ3UqCckO0tCWONofk0NvziKBoKOnTyuTFjpLTXB4+jViJvWFNgKGd 2OU2md2J0r2U1A0q+nfWTG/wRtGzcaPMc4oIw9XwOH34bVtcA+LWIbwYcbJHIiGb3vhHS8qSfVdB KOWWF1m4QUFC5q43EYpxH83Xhp+XRLicYvM90Fk/h5k+VWMdMHJEVLAoKPkdtPn9UakIiVfhkvuU YTmUth9TBz9txTJ2k0OoX9+Oe4+AD/P4TY+e9V1Dcnx59cSjKXC3NXpEmpHZdM0W1Ufd2FBwmrXU 5WhVenoVrSzRA4ue4GADPAZ0n5aj6s+j2MvlYYuf6bhrNsaxuDeBDMpB+ADMRp1eLCdOYBKyYCz2 +rnlp7rEC0fMbleqGJq27/E8omMtUQ1ZFQPwgVQ+4rHOCL+hf82Eppl8G1ua2AInwz50AOAmVnlg mkM3BtNxbpjpYxnnDWh4+AlTU/cpE7imGj6O7GBd1Ef6ccnACCsVTt6y1yIZC4CHo/+KncTKcfTz /SFhk2GMMNFKrmT2AMZvWYChP10EgGVAH8VnY9WsQdxtaEzUNl5HnApjGgl4xJLhvJuh1MA4mJsN ttbMZMpoRRl6RZMsLiJge2nFmbrQGJ7mAaZ079f4GczctdJD06fczdHwZT2pA/Vqhjsii3qqo8vJ 688NOSFeB18jLqb6iB75bAaPkFikzwKwymI83EyXEAaDNr0NflY5aKOCzcEHXDfh5NcM1jNwpg2J u9Ga8TQ2o5NzdMTntxPIQ1YWVtfW6Hh3m96b/GLerqUkMnHQ7rPAjaJUcb4h65+Xn+mta2/UjAbL cXYQfwZxlSxJzcwnhoUisM8/gRV81RY08Laf4aTXoQBsqnHLljcF69RXMt5dOhoGEeJPucI4xFwH r9Sibo3b5ZL/H468cuMpD7QF4/iT4Ltw96AoqLkw7ous+mWF8wboJW1/74eAitGYYbDYX3pLDqRR i09iH31Rf9JpLjzOsA7hs/gCMvPHQF/pHM2jKom3VuJ8Vv+1fg7NVVdmu+X5a+mjejuNcd9rvPLx T9nGdbsSQF4zODtkcUkh4xpslX1h+2F5lBhLQt30nD04if9NNM5Ht6Wca/AyPCVrsNYJB/TPs8v4 6v3h2pxlx2hXVcZizL5g2XzwlVBhgWLwfhsODIiHWhyM8m92WmLaEKR+7Ohi5POXNoKTCiG0yeU3 aQza5HEdYtcY+uylLMHoUQ05Ba5MYlsHKl0IQhm2RmCckqDCPILNce7g3hYk855IUlccUNMupNAO PFH/cq7WU8YqjImE51dVjPMtRce2LVbJNJ6Dq1QXI3ty/k0Bw/y6+YkI4wmZ0iPTnW30yzuS09WZ E9/GsbBUIK9tBrFZe8CKoH8qOZ1L3vYTu5tyQVBV7ZyJWIA/RJuWetV3X8KkxV6KicKvdiSoGAfr NUDwVIRN7WOYW3DfpIqZDqZB9ItffQ58iOrV0uS5ChXQxZSSulm54olpYo8KAi6IIUM6qybw1ZO4 TqQg0ysO/INNdhyk1FbORGDP9sslmT3QWRtB70ep+i+EDCLEVigm03hBLFgR8qSD5FWuAENDlJZA sm8trU4swNImn91/eLEzqyO9csc8RdNa222rMM4MPzHI4IWnmcFDU1cdI9VQnvsGjn6bmmhd/Awr O+XwEs/xPbdjkbW/gZHRk1x51RxjO4OdNKp8EvLW7JxU9p4z+eoNOOa0IxDA8Qain542GUyT9jkC NvBVNCPuaP9LiegnqA7IttV0emYXkvE2CQ365jWG0FZ4k0L8M2MznnMwDZAzC7K+xy5v3YF+NFvR 9XaZHLaRs2nUO0ZJlLErFbI/WVYY1IUC/aJxH6vy2x2wj0z6bUWZqVG9C9hH4fwbXU5U/KXmARB4 D3+C56oYlr/K+tD9a1Xqz5DEfS+PHufJj7sKhNx3EAM8LHNUqshZyUsnfgfD53HAim0CEXzq9EZn 5QxFa3mSiS9EH93bYWaVzqHzwZnloWN2MGpkdwx4XYaDlc8pPW8BK6C0+Y5C+x9URXClr5fWSZM8 9S2g7pV3BEmZx8/DTO7luHHduCod2FG40MUa8er1ynFx0HkMjAySOtdHrZEjrdPPrEU6wFn5RAsg A5ZrIYhpVSXSy2tjOs73I6YsjihwHA95MR4aLg9uYJjo3DKg7MfH+ezvdBIefUoxkE0cVHl89iCv pmNiJE8cXs4fFtUFqmVEXp1tY8Gac/gea1rBjsM9A9ycDFuPNuJ+1akHjw9YQds/6WfgfzWuyVRe LLyTLjZbE3K/XaiLZfawq+137wc+SbsLQ9XuCUNKN702f6OiTUW8oAL4JfY9LeaysVkqhm79bYKX FbDI/Hkzuovn6r35Y0Zm9NchRNJkkjxVEvUnWsZUFuuvW1D9SGoqlQJABBqZHnJ0O5l1y3eLjuDP +AngEgNXIrFkYC7TC45EXgWDc66kMC/c/bAy/m/4xYHE4eLCSU/bRWZ8vr/9O3Gn9V8GUq18pXiw QMQ6vyIdAVLNpFN24X6DcgvwtPsyuD0lDH6YEiJAba3/2NUel9fffBCQt2Ec0mS7m9KrGmv8/yYN vFUXxE8j04LHhS0EAOfEY8vdjZ2beZd+ZOCmCBayHuJfcPX/cw0tVzBRaGoLCD8u9QKei/eKIk6r Tr1ubdqKzqNtM6re6tvjkUtGct0XNMvuHDWsPOMOX7i99N8PFasPKnMBDL1ZNgOuVGGy60ANTy+x ROZ9HGwbSnfQgYfeeKjZOg1xp90kqHQsNe7U7UqK56oeT/zmm1yBsIyATscj56zn5H7NqUp4GnET CAAmFTilREYyLkO3LjT0r+lUfTSx/BvOkqiMKfpA1NljQwPMcn+sIGqwIv3Xb7ArTAon8na3YtCY WE5GkvxomG9cu7Lb9FhBLzBaZNm7OzC+TNQP60qt3gMUxx5kW/krh0a5r2CwiJYqz0xDx7H9Cg2q PKjXSDLBt4a4QcUTvoBwduv/h1eIqiGisMfNbi+hg/U/6Cpe+2S7h6kzf7EGvaepQ3SilCxLVVo5 dPhnrbJTZL+VybeuY8Ntcmy+mA+2FZUjzhUYJGtBNm4GCcktyOhXdYfWpN60A7FuTnITPz8q2NOU ElWyzgGIf/yO20sk7P+iAJ+GX1Lckipshch0M3xrci9KlcD9uzn8k5vIF5DyLZJJsubIHa8BHtdE XTe3V1zn9VXasbCRNguDF26GQiixWO/sdW10SvWtQL3S7hNPgT87j5ZpLAuCF/M1lGEAQjXLxcj0 ZaU+Yf2u10ZGPdcMC6GNs7Fp9/3ADS0Uhpwji7oNQL5LQhCVfZxryo3Vxl8GtKpg1HHCNPJQcuLw 1pQYG3T/ZKjiA86bBAQBURGvkMnvxrbkZfB5rudcg18+VutIuYhPIWb3W5UGKfEJpSETwE+GmjdE tyjPEkom3Pu+I2iwOY6UNXkNY7oLFPZLTz7/saSBWmkpcEccAeIjlZM1amDSk3gEMmr5I1VNfLaB VI63ZPLWFF/TT0/e3KHiexIPgRkkDqPTwbgMeq64feWwVBWqos8Cz4bEByFbWYQsDRaf5I5B0+40 i+MEkQUihlcRf/OczGl1AHIpOtho62w5d+NCWJdzz1AmhgGjpJ+/vpL6lWrLst9ICmdAJ6FJhCT5 84UgQL9JQL96XJhcDlZPFdyzB2EXJK2hDNURBZoD3O/ZPaRBCEU2D0bCcg6dIT1US/uIVsgylBl4 8/cofKMvyoqXt/TGS4c5nHMAKIDTMvmi0Rwiu7l001voWJYxl4VcRG68NgyMZN/MEDdO7I1Owgjf QRsi+X3vpM2Atngu9aBFFPeyk4dNs+NjNu2L88HLdB4ZtwLWFnQp2ollnm14yujGZ9kkTBrA3gO4 29hyRSiyk69z8VZ1OB6LzkebHzHm/CzvxCPtlEdDgX6y0FncCdcI0yaFbvTxjlXA9KcADmpafTc9 18/Z6HSyanW9ncZU0+OeW/3e6HCbFLKnCwvZX8KQP93VOFXjGzK6LOTvL+EAUbMm++qOQaQkGo3+ nfRYX+4yiMP+Wnxsym3Ku+AVwZadZ/Za6K1RKVdNHSkMxgGMrH4i78y1XiCnsBhcGceVp46Js7Pf 5DyxN3yO2Tg09LX9Ykncp+Qe3LIu9Bbt4GAs7+AXzyvdCfepVO4VYpRbczG37nrPS66QyXWsyJSb +uH8z38reLBUmwxU2vVcs5ictLGahL+ydvjpJSkzvmdRYw+KIlwmSD/6OsHU5DbJcoiJDQmYkAMv lgk9tb1/15GYOVWoDMsTSEFIoO/gS8j1xp2YcKa2OFUgXy+l9AqvuGlfEWHcU/F7dj8lJ9u4yAQU KWyj8ODlVpoCGHjl1iACjaxaaMifWqlN4VMLJo21ybE1q4hGRtfMVfXoiilHvul34nX9ZXkgwwlE O56GVdCsk0j0x++PPH2IA7HbhJ1ZU5ODDY2NItiwQeM07nrLp7IpyBcIhfwNZ94lss+KKhzL0Wz5 arsXKDN22oIzsxSjOgE6N5IhPdUhQeQKcNV53V97edzmwkJbnPruTAhEyYk/Z5jSl6yDar4vgy3o bA7ZedKAucIjx0ClP8+WHcJ7mYqc9PKZSU1yId8MhV6pylsl0DMTmAfuXQBWlSYtusOKPeuw1FLF mR78fKh1mT4lwNDBl4RlELaO07n1pF78vnmcOqd0eYS/EVOxNtEr2WEIOqs2QEfGNuZ1sEO3ByNG 2bVSDcfaMzZxmzbkm2LKmf7D2iNHyeIjPtHJ57oNeFRZhCE2DtfVf4RBZ1fQsH20s+LmgUS7LD7+ Jv/MpZ5YvnNRqRGly6atoGHPIVGJJ9lyuo4YzFBbGiBCfhKrlSzJnqK0nhPqIZSv7w8SsBNCY6aY 1kN/pHfssUcREDe1o66d5eCG1Tpe39aKBHC9cm6yWEBRtVSSGFqHYu+Wchlg3x+VNdgvKhCKU+d+ CS/oCW3cV0IHMlmU+qHGawRKKWkxUqc7KSBpQvyIChnY4Cg5/JHLnCWSMUv4BaWxGRkaJmbjLP+H 2Hq2oJvcAs+9hBVyQB0bTcsZQRPfhF1IEZKvCpnmT0Jt0LmVQ3TStLK3x71uURHHqBt0/vu1xIi+ ttdAj9bsx5KxWBXMJYMpafKnBXskZs6jH0lYJdJaQbB+LCtV0/zKFYeuvlj1WKfvx1b9Ot7lFwkj 1EgsM417PGA3jLTG2DwRwcm6CnCcuocdsTLwwO5Uyl3i1XxwURxRWx/SzhIctSc/7681aRkR9HQU 1OEs1AsLBR3VTXd1Xfz9z6Os0Sn6HnRtlUjS8+EMZEnsAr2Tk6I1anbFDYsT8h4LllG/0b4XM+pO jVHcbRMFpThRhprP8NQSpETNWC5UC/kGHWTXH3mZ1lTZc0aQ6AlVT9RVdImP8f20Oeh8xZTJ5ADX eZSGq938o0eodhgZTYwvMDXqFFe3ccHjldw75wasOX3FweD0oTSp641bnqnppxn8Tjues8tPH7l/ b2wUOvChK773gZ2Q1D73XSZCTNPIrZCWGtIUxa9PnidkXTk7PYgnNSWja8SSOkub0qlkDUuiKt3k WFDAHHKAoMvd/lrAP8LRuJ8nXccF15ZN/K16OJ30O2BWdtgkLMJi/KvNQ8389g3d3fkc2MT1X6nK 9uD/BAKoNAxK+4Sx2XM7I5jpd+tpn4mw0bPWcQN4EWBlPY4LmJ2zj4Skm42GYf9KP5Oc2I6W9Cp6 Jc7ih3oeZR1zokpC7qJweltdDjbCJhWIP2eskAIgzgV+mEipKVLMTvZrdtg9+/LaARcNiqHC1gMC P7R3m6tOGdkpB2UdfrobtlSauwItb631CLpoBznegSQgHQ4APNbLC7wpYNHIma/YfoFAQZmKvTHN iMk+tY0YG5TpoT5NVhoh1My6zmUDKOKGRxZqRXtPtyvC1kXYhwjBYUITo5UFvA6Jsd2NARCYfnq2 DQYwRUQmQxqvvo4pyUlM0M40aAXexqFsq6WSzEwL4rY/Y8NrCEV2hustA+donwL11tSCz4jj2JWw ZgYST+roDtuEVpGkPevFah1gy67aBgjir8MEtrY0AP2Fd0df/cZluYOl68oa4ppLCB5NMqkeBn6n 1VDeUiZxjjb2Fspy6ylKalr5cMu4npREVfNpUmaWf9VKw1eeJsAiFijgW/mVSTd6nvJGxSX70Y9y 2YecGI2zyuVm714771N5/5Mf/v2SY15HIhTToJWMyEH4JfU89skpvEZvH7jLqMFikfI/r+kOW814 dvlY1yyeIg0ECeB4TVaNN3XjJZfKtCLmoHbOUb/PIPYUbVzgLNzg7edYaLyovxx1TdtiP63KdZrY yvdCNJ2zWgcwcC2jFFw7Byt7qQFeuI7Mfofci3lUosW9LZ2A+v06rIsvVfJX3ODYJV0rGFSh+Hkx 4WcJ3Sp5JoivzdDbGVB0Q+bJZkgavoGTi6zFjjJyHLd3Q/oh6mpQOld3QXr1//iQktgPaDx2EPRi YjOpJ7KdAVFyDx0vDY1UURcLhwHPki5sfC/aK0+HOzey2k5rxhG30jq4kBqPXy6bSPIqGpbFBYSK L4f+oxhDI00F7jr07zqWx+S9WZMH6CCPTIRnZzdK+s+tl5GypUHtkQUxyG8VCddWsTXiCmBIBEJV vxwNsTxf/CAs/KXOq6OF83j7ANT2+mhzOfxRVPnMoyJNwFhXXb/pVVhjQDklrxi9lUzZJb+cRQeh QTltPN+e/JLLviE2xTWB+lcZw3UupWAoNzbAa99Jve8MauIC9uBddqCxRnHMOjMIgusQF3LGWAFm ztQd6emCrCdFFsYEwZ4J95JY1Y5z9qxYEM/6BPGIbQZj8I7In5uEe0BW4gEYrA2i9I1ZRdiqjkSx +B//rLhwghBKi5Jn+ZMM7/7nwds97yqgXS0G+0ObcvnnYFB5j0TTbxMoz4DOaRGt0av56OAIrr7J LV+YzDflScdaJplCKIkWoJ01ZHZNcmP1ZSzZyZCijXZzzTf5IFLw0nCHN0o9Bvyb69/bLvRsqKBX Jd3vmyAAkK2R2wJzvTdC39SDnw2dh10yscH5uZ4HYMduwa70LARD8uYA2LSP3xBBGYhwImdaSbAo aMhlLznqSRJDE3O82WLf2dhSQj/oOKPqsB0EL367mb1AtdvvcL7MZ9BQ3AWrTn9JlDohOx5qPHM4 IUFHeR6sz/VGrWLZxk2JMQdv6mZoHSouknAzc1qLKvB2G3ClretTUZQNkllLF+/sqqUpsLSoKpFm 4UgCEoL4KtUxvIvNq4HFUf5YjNg04j3DMU4v2VaL5II4seWGnwtz2yWsQ3e8+UCrw8Qf1s5gNkgv 9DVoFB5/VHCI+TLb1GPoMLu8TjuFmNa0fREJ3AsSMpN8I4IT9daJQpiqBn3VFIJCCcgBjru7A4j5 nHZwLQkbqeVusSqHbLSg6SBEJwMjY52OnIfHlncg8ibHWVWKpl9DprVaYNRtQMCUt5mhO/wCOdnv a+eQSexa4S7oZxqI0Y3uaST2Conk0431I/9CLwLs3MyW2ut23GsDdLXKmAf+9WryZLRIadoB/8yZ nGXeK7TuTcF4U6q21npznDoqJpq3ZFTKaeFCknrM5J+rDhOVHtrk/e9FeYV3lsH063mNaIlQCFnY GG7TJvApK+/hvAZG+xpUOs+tO8yPnDpAB/o0akH1Sucrrml09x+BwW1+PaAnWbc9mT9ZiPigADc5 XChNcbrKHNJ1aoJwtpG5nLw5gKTlmiaD+I9UxlyeZ1IZEZdnZjxFHJXzpYGajbxuo1u19a7WW5cw 3FJZgCMoFDuAsHmLzL6N4ypfHP/5cEpN4723gbOEaORQqvAOv+vmqs3rU80OSBG4eHNRXkdTBGRm 5XkhWwBKkAPlcBbq/3UyLWdpajCVnEHX83SeZlHKS7iW1jGCsNEaWnlT2i8wIK6I/RB2hyrIFM9P bLlrLi+GKmftGE4JqcYoh5HWj5D1R7bf7caS28APaDrj6BL238nUSynO0hI3ljeSiiXD4DeNWkyx dvHuE6zjEB4IGeqBsIWoejs8kbbcHFxDuI0Kaa81qJKaZW1iRjvdIjECO2/vVMqgLbIiqRSbPAxm j0KvMAQ7PoPWimqA7MXRn6ONhDz5SNcgR2Xk936Mf5fzaAH+51MrPQJEzjMqYKuQI1K80z00QBTN STDE+WrtrO5XiR11G04yKHQ5kiCCc3w+G7hK+N47BcOi5ZMWjKrOJejpoSGDWaVj2cnz4EOdXQVs MSc2lPiE7CXttEXzqBbDGVpcjTJFmnp/ZQdYa1wsuopKRdCLVxDCBoXoELg2PRKFbutNgQw7J7Bu FqjX4ABfrTQvLyoRvJuM8ub2Ra6Dw8i3fMGi4Qu6JbhTmf+CRSVjwQnLsHeayLcdN1QVZvBmZAAm LiOaU7mDKiswTDLBWRbLgptddNTYwawCXSKCKhJYrwx+JdsHfsvI7syG2MK0bCNpdnuoj2gIU1Nj 55zn9MLr2wFqTZWAHgpLHaNH6oNLyLFE5XsS5mSLdzguu/SUoIu80K5spwI7nz9eKx9wt0GpVvtS wpD0acHv0V1Cmyzey15+jU8g6yOtVcxQYGr33YzPxP5cOs2KFFci0euoGJIc7rOR58KZDAu2VgZE I76csPC7zjZ9FNTpc/2qow7A5LN1W/ChpFbcCpYGRwmh1FTnbBPPlET2Bxrbxdf64R2DjUD7nTvf gmoWnK+ZtmzM2kxEu3yx2K8YpudRh5jHkLWmNIBGOS6sxQHvIIG7fXeQrglAquibCfs4T/bCLri5 +tzBMTxQynornC30XAkpTDikql5FqnSlIIqlNWdo0FuKhp65O9JIMd9KZRSCpQCtwSxkBfH5LVsZ sELPFu9n2qMrWjTLFOmmkpNeFRq32A/22IyEa0dBAZngfnj0kzcFAYiCS47txijdVFCd26XIOPur oLVdoAd5XvUvQkNxKZRCiuHFUzTjTb8ziVjfpKYTEmWiqd7UN8FQCy/NnEX2/e6Pav5T9vyY8PcT nDa6spCybZiF/zxxY/f4yv5qWeoSpaZYFS/TQ7GuyNm+MjdWqQMpE2WoM8UoYmoUDxM5EA/hYFxM epc3iUrl6iXu0SbtGgBImMxxU64FXfgLOdRK3jGfPwENuLmzy3z8RNojIrrBZF9gkzGqBrLtKwdi fJp6x9i/nRQ8Fpio/fZRpyhKdCARe7bEORJnQ0vXSQVCGhrkryAndQQd4SiY68tgLimjPzQ5eFCh UWfoUzRUFzjEhRbSz4QqogxNGUpS6g3DKU/NP3gkRK8JQZQDVe1VIRRWzgZz/LOqoNOpqtwfZw0f HB3WGi/sO0TSYFtPuTJ+M4rMkvP00tMZejmYDlnrZPQn4wlbPY6L1PVWYRxU5O1+MPSYTy8CTzsY PVYRTa2gmY+ytT5H+kCpvReU2o4Js1U3OSTZC/2LWdcGYijGP5+fCiaKex1osRfjeBEQL5k4Z52I ZxUT7sA0V//6E5xU45wpuVTxU1iDr41rt0EVKUeIRCOxBKPzXRDk5AoLPcIOvl/WSfTU0xjm//Zy BjkIC6z/VIqAnIczt2VO0EdP7lVGS1/mTfVXjaXUY5u3fdW52KfPjl8NnVE2ee22831vtBJp1bNP 94G7iB8Cp5EzVQFsaN4hFbSvSUhOxBinSh10Cl1FAG++9mV+Cf/joWp7x+m2MbZ4dQS/U4sxA+Kj 54uR+G3uYFc7JXY+g351G8j/Le1jy8jPMYyzOG4h0H49KoghOsrvIiuf17WBncof/24q9VJmSusM 2UzaHSwVDPCjwQHbQBmn8P27xL1X1bTlLx+55MqbCtKYM2UrXUkebw1HExgyieAzvPDGOl11Rpa+ d7gWr+5i0eHft+wxywMWYyWD1Xmvak6Ba2W1fpgdAPm8LOi84oVIsv4/huDvg23N0qKoUV/NGziP ra3JcOQIItJIbn3hFyDgkG/mYHu2Iltelv5f2Gv6mgoSC1QxXHI0ZTUWjQ4S4b99J4grR6FzK9st 36rOEnqAOLaG7nbsRAFoOOUNEp3diE7VYWt1UYpkPOZhJ9lAMOluoCDdfmc6LMQ34h58/OyZcZYb MEfIz3jYZ2riW12ajF7ildy0WPUl4YiqzpHEDvEyg+rWGNP6ZfN0y1urvu4qjg6qG6gWSsr/dwmD ++b3jcfUr6Gey7BwcfQREJL6v7aZGlB+pwszEM2yc5dyAz61bpN+Gyx7FFy7N3ycIlDr3Ov3qXAa Vb/jwx6RRcjP2ahi1JqXZbrMn3syV0SidNPAXICzRkpgUcH0/u1Rbmkg9W0b6LAcAlCXEg/TV+d9 KNNp/dV0t0YwZv1CJnyemQ2A2DdXffxi5bRGIoWpXQDvkNaR5Y9NoLkc01BFKN7bwR8xPA/vYiCi OdaE1PtOEqFyI9hwMWcZzd5Uo+FgbxOYEaKrLaIWsX0/3C+eIOox2r/YN+k1k5vwy3bOvx3bGZi3 NC3KYvRt5DaUVHr/F7jsTEPn6heSUdO1VoNPOERSDRt9RvgNb9n05kWNPkSaqPZvXsdHuRo/y/3l 7aDcRzUgOmL+Ne3EvObJTVlnOtX4IgD5Rzrjli5EXhbopDp38BWC6XPJqjGRJQe0tMGJ3YNDMRU6 3DbXYqKuvNp3sj07Ax+sySijzmhCIgob928BXTg2RkZlenvmnwwgniLLpqn/Q9FJ8P7PLfPWiRh9 QieAmdej0vLoq4wIpBhUOmI+zgnREFzPRyk5FPeViiMmGlKXBfeNrnAvxqtKUTJFP2x8hDDvXHSX t0sZpwpez4kVEw9w+VIEKE3DjRPnFCCxJDi0DaZIcnwrTCci9OvZEQ9/nr6SBCRydLIjh/tCc0FS gO2W98vGIyHJdGrN0aGoVaD01eU+nXaMuEibl8UhWN3sP2p88cu/5CTUn4IuUTO1lzV/GGxqRMlq UuW/DoMuXT4b95TRx2heGHKM4ONu50PWP+dv9Qc3ZoWJEQcCeLdDm9Ei8MeGaRMWyOJ+R92gJD3n L3qi6/QKDMgEAem3QiEFyX0eFrKTBNSSwNPhsar2XLjx+6OL1ihyWf0GWAWRRJt5E0Mkdj8Udykf lfKnbIHdCZYldNmxaIQQQ2uNkyTXcKAC5AVqkWvEyVLwGjF0TT7uxAdiaDm/5cFnz4mzSi1gMmoi nHXVKF7fP5LR3ChFMrJ1hGzNE8YpPX6zNfCZcrXDEZxzrDQcamHcFpp3oWVPzUUkxzkPJYoxsz2/ c5eyp79/jtJkOzTMM9pEwKFi1sit+z73RdF254NXXdAl4wA7y0JiBEUlBbimrpaaOESWxvGk4iNM j9ERYLZMkaQZhu20/LwduSSNvuxil8l88SeLZ9MR+8KQj3O/GKVBg7MsXCRYKT6QKcOsr18UscLu wMHRKVH9XyB+IyFoE5DTHxhIqO4rCB/b9/DaFyU+iIU+9936qDxAIt62YF8wvzad74bh+HOXTBAN n8o0KeFoqMYGIoyYlFiM2753Rb5kDFRs/67zVzW2zawLV73p7iqKUWlKXj0uOKfFMzBgcOdwZ431 3Tk0TmNS5kfohUqulqBUltdpMONjzltwjRes5dq1WmFYahobn096urroA3XXmQKb0B9lhGExWD5b bt9kpXZapzvc50XG/PJWfF13xytj/8VjiVOfupYn7gf1YNpxCGdBXUA6xPjuYZW1VubWYN+YZDNR bUUSOYmydj1bQLDjkXkktIt1Ld3b3WWsC+GdNddmWOnKeNow9bMFuDTOxv4tMwFY240e2IJm6P9P Ez8bQpH0up8Ebz5NOg4mPhxUVhud/u1mkdn4C4oke9QA9yIE5gzKlMLm/7hPK12e7xcKElsQJzDF IxBhEIeWcAI0pRr02h3dkH1Nz25H+wPmTzWjQzmfYzp/UwC/gXhKXctgM/0ShAIoRaWTIaD54WxQ p4Kj3vtpDA83y2CRf0O6TZScK7BzFJqZqHuCVrRxHZsZlcqczHvbeHtkLZq6vY0bopwy0xuiyYPM +jgjBs4H4hsKbQKfxUNz69qYtCXsty1e11ZT21A4y/Vy8hFYqXyJCLIgQAq4MNjr0bq7qHNxtRS1 c80ZS79l0zqxoF4h8bK0qBGe6ACvVDrrZYRkyE4C02JSiYVzy5xt+R4IP7+QukhsVYQorFpH1DsF sTbbluoXi5Tk7pRSpCMikoF4JrHjYaZzB/qJG4s+yvrX/3l1FjqN8N4/aet+AbMGvOlaXe0hb5T7 jrvc2MD7zQtWIesBgWrapgygLDmnOW/FkNltveqGvYjRDDH41Cal6n2f3rpaZQdQYwFdrDqO1Ttp MSX3u6SUsr+NKrwEoyyEiF/tdM2igklrHZwStEOYVJKdSeqy3P7DDofWuTuUN7hVEBAmKqBxN+ad vm9CbXmiDE6b6JEwlU9j9qh7ZGSUSSlu0+Xd84ogBSoptYBFNPDah6CxZC1v/9504sFtBb2RepxI CtGpNRXBHaBsnncrNWQ1S/yxnKabYRn83aJLMpvr+azQh9rDGVHJbpnWeWZ6Jy3D/KnAc7h7Qp/K QEPa3QYcBCeIKXPO+VLgvWJ8sIWlgCJkgvpuzm7n/EwUwpT3+tci/d+OlEc0r4U3blTCLdjgltqV 7j7xEn1GxFugzvaeDwUJJEb7NGJNPqKW78s69AO5oXGiT8r8+OshrP0ikTLlvb7L462seOo0JD4H 5/37zxeCPLp7roSdpXry/bnuSC09rEe59CUesNa7cn3TQ5M+nxrOCPZdZYPDMNGlk3dAlDx9L8EO vpsPOm+m+pdwCAZ5k8DhBZYQJkswC7KkGariTxTG9YwE6hTXSWq0GRcjRf7Uqf3USuRStk3SPF8E BUp6HFT6fFSPwOLAZJLe+PWuaaodRSdlfddE18DEMxEgzTrPHrCAThNMP3uq4vVi4wJ+hDyuqONO uPULvGukp13eeBE39tvde/3H6Rm1sleEdJlcyIqOe4UD7rLFxGCpH05nMrs6fKnxhFyLJ+cCHtYp ygllZnrV2bDm4JuLMHopT1CU3SoOjNmHmhf0+WL+lH+uDKU4uRHDNTmcYMXPLYXDPnBkpDfGzuGV Mky1KrR+nXGwKvQ/9eErbqQCvoRHXUJVs/SDEY3oRCWB0RSUDR50c3Lmpw47heUlG3U28783MoZk e8h27dWglHC65G4QODZn02XLI5Ag8ukkJBK3HZ+jcvawyD8Ne7yxIE7AHpomYTC7L8eWIMNtY5zv enjWbvL0/mq2RMl0ekIp7kqThY5Ioi45wQLARW8/WMd49AsJdNtUXZKeqjRJL+IbGqr+xKVC7uPC pItMr6bi6O/VT6nojFWa+H1Fa65yK/4Y3YQ5f6rBB4Yw6L6D3hL1fKLt7YVU27IZ19bA8A8LzO+c tJllJKPD/RudwhLMcDcEtL/Gdn9sTpi9A9TSa6J8dsZpIO5yFG+llAx6plK5Lb8zXl3e7M0S2Nkk /FrBS/IOlEZBsBq9Fztswk8dMiPcb1UhNFGyZ8pXJd4T9TMzvw0X3J32R28PwlwqXoBIr81HWDLW Mtz4c01AdXVlDPXvKnZGXedhFhEWeTMZDoTFrn4QsIhYNNFeeQXEmMVm0SwDw2UeeA0Ft/ooHH9D bkvPLwe+41a+HyOUxsK+BKIm9TBDlyjffQ9d2OOKjZKbC+nqMbWKqxghqM/7y8ZkyVLz80iEuitE kcex5aRXM0jO3Jg74PkKQaf8QeLHgx6EkRX1BOVCqziJbM6ZrdsCxNhTtIBl/FaCchvEuBnkVnww A4UgeslhkXd+bPJr65+0qfrUjBNOdOSzbOuS4NlwVdgK5h4waCrO2mzIzCF/SAmwZ8+eIXf2zDsQ W5FNeycV6jfH3ryG43fHgzBd9nkB+eg8Bub4S41TdrLV5gjJUpbUBdNnxDIDu2dP6iJUi2qRfmzG c+M3J4utvfkezaQx0Och1fzIBWzQ5DhxivcU3NShFJIHvVhYQpBfyDkOP1ZVZ3PH2qwc2ua1xnBt V4mWEdx9ZvX2tC6Srdt+yC60sKBPhv81x68bgYYk6pMZH4sbPxt3xYApdx4RArHNs2Z/hHywyWhS a6RUVbL6ekI83avKPfPiej0CxRv154ZFvsVD6aNIh8e/aEmYhxJVQc6AAdrKHkvXKN/TTXrbOoYn lMEf4lxTm1EiYMoBEZ8W1+L9/TM2jczUA0hEIA0sPA5cQnoia2S7LdlhF7bo87deOVNa/w8mNgyh H58z3Xe58yU6YNg5ucuM22z9UhWyYjVBUHqlj2scr8e78x9pBcNp2mx0xrJt3a10825JWhTZYVrH YxEQJ6RlwDMYvj4a9IhkMZZMCBJAbUEnu9aWkHxEgD5V1PhnFFdE4mMABkhaRcuk2bhzUQQ1MTLN kCWkp5HB1b7EXQRDn4/hn5dAAnj46hpQBF92C6NatX150drgBnCi9wKlumq3UTRtszIDfoy1IFN1 ge7gSAv2MpS6i1yV8DyOy9UrnooND+BPjATA94kaOYwnBIYCYMt51rlq0nQdq3uUaGJuj7eeFUc9 Df1bkS/ZjoKrfh7p9T9RJtwyeGcP3fa2q7jsnHA8fF3w8s2uQJSa2aRXvUOaAU167bkXGEUq79Rl 1lSXu7YhdtiycHLPjnRb1sqJOw1pZScnyQizveLKayUfA+jzAVWpkhNaogf/+sbAYIXz4j+DDknE cF2Ge2r02UslvrDpekYfLqb8T2ot26TXyPDvAGXS/IWumSqIcUf+ytbX8ivmJJ36S2Gb3dO8r5UH faa17vEWslnLKZGP+zUf5/yIS9bQz123it0On5I/rvubil1lst8cNkYBg4zb06QRyNXFP0Epp8ai 8h/BEynY7zB/fQMcnf+VZbF8GmBy47NpFCey0Cr5oTq0UlfqFORuCsE5nH4YYuMm9C+ILjLW5MKo 7k/PXKlwZt+J+LtuqhmwKJ/+7FuoTlMRSd3jeDnrLc8ou05qV+QxKhebTqiKdob0DcU3wjb+tzqh qC9KSRnewzN6hfVvHFQ3o6J1JaVMFUUaeVqB65RKQO1qgXtnDr0pafd6eENpDbQKKMoIc8yXLiMa 4YfjHq7N0Dt00IwnCG60yzQG1/T7L0meAIcds+KUSz067lzBa0U8FH+mqiDQH07coA9AaO2DijfS fRLti/ApAWf26iDHwLEXSb3YHHvezzhwk+Hboo/lEZM+LoM5bcf9EwWsbjaxJSCBJ4KC5verJN+z XLqgvqoxG1n6kc+E633eB0Q/0nOuqM4fHLU7Ao8tgxbH6KyANeMJ/2WrzrZPq6BMUs5TY+w3Q928 82bvFVJ1Heuw4c79iszICpBUykny0wxkM9Ry6vZ7doaxcDesFL0Sorn/q9zH6s8Q2RGBSh33d0lA sjzKiq6EBkNIDdn6AqbDherrAIjPCd1QvpidjywuKTtyCvljo3qUyWkYuZjXm49YgiKE+JcnnhKo awvNDGWzOcuiuizej9j9FKNRveb+PHPtN0L9vMBddwgPO9kbKH/JZ5howu2uFmFbTy5gfOQndqOX PAVErt08+U68Gf+DitQXBvrYedIYPA38MW20M8rIbwGqqXG0Ugevz9nTafnZPID8cVvAx1NKxJJh yPBgfcJ6N3RmYOjbaQlEmEqddAGsQQGL1HLXLndIyVGz9VypaSWmhmEYnWuwliqO1v3Svl1uD8LY 5d+cnxfaflBwicGxuWDNcEQIluzmKYcKDSa1GNxiNk/WK1WSjoCuDvHR2Zd5pAUQ7oWleBV1TXwd rn2oyzCn5i4slXGRS238BmnZj5pAgeIb6/sWzqDaJknNpw8QbBHibToB/OsDjDWPqJvEVN2tk/sh /CNcyz/YuKu7sgCudw3ZKwtveD5lf0P+VsQUjOCTxB0ZHEjFmGJLgz+HaAFSC0GNtNn685jiiL6e q+Xg7KIzpa05kLE6fp0fyUXIB86m1E7zblt5aMYAabRB9RoBktGf3mz1z0siKVI3b8Aob/vrXAAj 37NDHKUeT1jbB3DcowQKVbczP3QYNMItknCinlJx850ALrzI0J0lwsULYUi/EfUVYr7MlToEieov gcob0YlGyt0Df+C5vWv/Xa/Y84evrz7qVYFiz9/zDjdcPllA0zVkIeE5QjEeHUtFWU1sq0Qw4Tgp BCrrudCCgfrUOVbN7S5E7v1XPn1k3hnlAU3qgI5b1foPgHRCuIZiboYpb+hduuoLQqtIpR3kS82d Nrtu4V1OQXd7Kkgt0SwCSZyihD0/l8utbwcVFVMbJLdMboePVRcoZ2bJd6bmPVtDa1fJ8aRXLaQE ZuZEt1hQt9FRKiIfsoH/w314SCc5eG6MW3TzbhIasuPiTGtSZTzLNYsnPeOepgfvMi5NmvfKogwc fzJ8D6YDxO2mzU34Z/tCnYfa6EVl/eCTX8neNQluQpJmyrFOcciB38YE707+OEIpg6TUaQFBg+nI uFaNiDK4FBj5STghElbeT/PTglcf9JGggQRplw6q5kd1MoBFWUhp+ajfq2behYCv3vii+6Maxdjx l8OrAAef8lD42bDeQ9ks12dLHz3EbtjAoIihoT5JnCZKG3MwYgh+1KZ2EVcfS2KUfNxCKqEysBgr QPpZmcoy1A81PDiYaApHMb6kNY7qBLcfQ8D4hz9qQu71CkvE4pFp2XifwF9MWeQX1czdV7YLwyux OrPAKeqynM4icNTIplF0b0JcIkaQ5iKmT1O8BF39BFn5vdskSyv+34f8Gxe5/R4NNKRTt1+XDA3G R9I1wiDRcUkeAgd1A+vSwICvuiBDbec5EdIYUzCAqTWrsKg1hMwTyxEr1DpP3dz2fOYEE1tMMZHI Ctkr2ptIA3WAUU2SeBnxcNtkBJC1U7TzF5lm6WetNlllI/9v7d0mLnHmJ+eeQoB6QmDk2eq3WzEj Gm7oqcmuP7lAkRf+zcMMexqVSrWzsVyH7A2ORlR0JlZkKTBASTMiSLoIqgDZt/Gij+0cmbrMdDET M4Y540HiI1tTVrRdKL1/Ub3S/9wGFL6uedPnwRBr9LQHAw1RbterF0QckkJA9Zgv2dDCiX5yDOXe f82SV+IB0fMYg8wokE5MVUrzrJoSaZKooJV65JLbRacgYYgHsjZJNtOx2i7zlXJoENMWzSRGegye l7QO9ls4OCxdXZVmA/QQQdxbGVAAIz7+HnC3ClswyvNbIWt/WvomFvEJKsj71xIG1w0QFxTBkGIm FYUEVYKXpxQe7fMDD7WEYDByifseih36yIzAgCinJCjAHWN3XMvFDBUcbwLf+VS5jK+vFMnlFCDL TuX7A626uswl+Fl9phN9YbO2zAWkZt4ctKGh/4ecvGA5N6d4zX1VsEJeAVYhmo2vEn1VxUWO5UCp 0/3REX6/OPo0JXfiDzXICnlGXIr0LWL7AlcUivFrfpbdVb23PlSlRc84OS+s9tXC+dKle46yxypC +QJZUwbJCzppc50NfXnJ0SRMXPbL/e9JoQvv4PYcChLZVbs/apB//jzWR6gc7xQOXaNh+4MjrQC2 laOBlKMZfgVrDU2m7/1GJbtGFkYNJb1sNXITNrItG6wqN00EYHgvdWJLMJjwnZNxUlA2nShwu0XS s2G+TuUXyzhzxtCpUdRM0Xgmy1CVjuRqyIZDWM1bLKWVzs7Mi1CyhvAb1RtU0teQ5Qy98KtdFm94 Zr6zAejdJ27w6qM9cgf/Ywo7Blb3dN7d1Q2afLvtJds9PMS+J58016StrDNIqlTEFAAd0k4LHXkJ gOWn0BzoWgWBqnCdfiiFfyYiO1nmQcuU6Y9KGOTP4P0UiuwyP6njMjynDXNqvZOfQv/I867lBrg7 1r+nLzXGVTZygwMo6xzaCmmepwjdxh3tTL11Nh+gOUOaY6TVgqsxXVGi2CkwD3Z9yETLGsFVCE6e 0rldoEghGotbTCknoB4Rdq/E/cqo0/TCwFG5AHZax04m2/8kpTYjTm7/6AAuhu4Zhj5bnvKihkAp 311zCAp6yhR2B8YYDVaogs5z2gTDgZbmi6C5ZHR1CqvbqDUukeH3tJqlppZF/RxuzGFbgcxU0KFW vJIxvwRIC6GeB7UTvBwpDOHDW24ENFMKsif9hjxyAHmtQPzrAsICBt5+TtNK1J9PUFpMDiZuWHkv i7Pvs1MBT/Oviw2DV6RUWq2rFQOZqWqbQGLscWvJ6ZckEOWq8M03t6N3epOVnMoxhkcxOblEsTSz 3gqdg2fOrlO/w9vx4cRG7f7tsBLkIW0dZ25/8i462r0U/xpAXsYTi8tAtkfkWT/l7QFla0H3J6Jo bD3an21L8cv+Yf9GQDP15ucQSLTPFjima87jCwwJhlQxRWPU6qIKkz1aWXf03GBoLoZLRhtGZd65 WRzpIaXk+RE70UOrJqjASYXMKSKWuiBCPLXKAbQDm4/nanBo7iQQVawAPmTKW0FHqy0roaygnR5I TYWYum50hBMm3yOFLI32KmTPEN9AdlyX6uJHLvsqSeLieUmvW8vV4nZ1h7+x8+I7693eHY2PrAV7 Ps0qk7+vHZeDcd8Y5zSMzNGAKcIduWdVrnLimS2gEXXliS08Ld8jL0TDDVrag8Iu9GT/27wm5vmn NYiW8vEPrjomXCEGDOvHFP7ZnrbHMsMoRcxs5QGNiLktLIvVz+Xm7vdjKHNRcwFfQZcvjEA981VO OGewsvHw9rmEfaCZgJgl1huP09CmRLL11NvdOkEUZcbRu6+9dr0us5MvZws8ageh06GE1S+YPOZq vviIJwfd+c8O6zmJEkmazg8oe6E65PTNUi/SjV+YT59j1KkgYM1TAhx6iEz5WA9eveqMTvWPTtYz Kpo5B01mEaqeDoy7e28UNnjPMBOBz5A9gYNLlaF4f/tJ+0/lC9gjY3TGJ45fT0GTQmGbG7eC4T1T Nr2Vqcbz+XL3QkP1bYID0V18Ekz0K91MwfFNu2CeOWX5Gyoai3sD4bSF1aUB6of7vWElmA3wfHun Zk/Cq6VrpUz5XDxL7eyFbMg+OVk+kotzNzMPpzc20+RVphDmVgfC1bCGm6tc6LzgaPZqp4N5nIhb HNIsmC99G5H5l+v8N7fCdPs3BKd3fWni0PFs7/VeT3wjI663jnI0ix1f7L0TKIrK+/xLiZKKBTy7 kdyKdj1UFjlbU+RevvUFtfZlUJFCCoEbYEIa0jt6cg97Z0tiRLHp/71gERINuQdKX4FuHWdGmDbP Zn59DXEGQTodhfKx4wpfk4rdulu4dG7RB5Qfs3W8e6ipSqU/N5pFfyKtcQioeriDEyc+d1aFwagm Io99QQJWC9wFUWH1rWNzrDhxxy38wG4sfYskQxMkpJHSRYDqv3Uq0T//rrvj7Crynz0d52TL+HFQ ARvUg0QZasWtnHxw7i1/IPN2CjTIFxhjb8xjsXDrqvgCtdExp50OmY/Nuo2ejRT+l4Abtc+kV5El H9Z/ylDyzvBEDonivDNpu4NqbHZNIc5dxYy8Vd1BWaQfjbLb0x+TWFpRiXP2c6hMReO4KraeXvd4 /snD7gobzLKxE8BRioHusVofhXSxrwFhoOXP4GfIP4XzWQ0FSKoIv6QXAZRapX9Sht41yfRL6HPG z81bskVmCOlP53M13x0CJoKS0JCw7Ov7WIR/SCdvZpcQNCyLJDy1ok//TcnPaUz4dG4e2HNzSYAB ZRjZE2hqNZXMnsmdIlSwCrdhAvfhsbdgEj/302nokQ6ZxrMzqJ3Hlt3HQzvT7Ih+Aj1+mAQGzTnC 9Oqi7CpuBvSRAKzIMmwABPuLh+CJTgg6BoAfPNJSWfD0mFf9goZOvGCIYAv2ae+DJ9ospUrWix+H 4DyOrZCL+DazM0w5wOMn4ZMaTGUAYmPeVbC0jxdhnTQfFupifGiy4nH+29XxVlVeXzH/nc/6TKMK hF5NSSraoBPk6h9IgdY8ce5xLQzJbkBo4LrBZvQ36jBl4DFo/8ucXegODGxvBrsAh6n04QE8jt7R 5+H3vfz8w7N8/i8w7ux6Qo5IRyfiAQbvHzcp//L1fIIUlkFXYRS6SCaU9F9eI3ET+KNjPtZ/gjxu ZCwVY5ugphNRN5FcD+JP/kOhekEby1sndI+7wiJx4l9tnq/cU27+SboVI6SttMHTaXQbipdpibME yhOnvEFGNCsuYGrUJTABhAJIf4Gw5SFR+4RXCm++jH4dhKhhu6DVYHMjpksYWCo/YoSvXa7qEFxt QR8GjyapwkkrLi39kZvvV54qCWdq7LJVOPME4IgSsLFSprJfrFhyFAow8bg0AiazzTN7aAAaEkJl QtFtQIQHI1D19QM+m6Ji0oDnFz2/f1DT6oo1Wlx1VYCYU5LfTH0KZ35KbObeITUWZXZeHG/lSr17 arb4RISfvxd6RA8u497cg5EEk3eT3iSr32ZvWpihVAlC/iums/2eaULduM21eyXg0gh6WCHbBbqA MJHsxIZb9b6v7FTpB/1+kULue9r1l2nS5DyDI37F9kE84ngcXDSgQ4lLS/ARF0O0dNG73oZD8RTg 01rMBGWh7gGkAJBkqfDIvvuRVJHkQqpqVUECEhXErFIOKfrJF2pgcfISlUduEEYq/iXLugyVYcNd NQpqV5iIp1OZD2wFrYg3NWqqh/rdsyoXpFTR5U8Cg4+6/DXpfz3zwOJqEXfykncj/wIRaHFmB2ag 8I/qoxynNb7USVPkLTOzTKyOkiG30cRk1NeBXkTvwd7m07YHZEdXqJ7r6GjSaB4Is7ZPJ08YQ5zS D3nMjB6CAi/++NHevFqNEeiKaxmoMjJ87kF2oS2n8WLHTRGPxdwHIbH0yinFjzQC/No2BDQAepXs mrdwr1lQ+9NG65fhR4AkD6dRoO8HeOJX42mV+GsR4jzUTsfp91soig4p5aU4/wjwJqyjmfmqzEMK KkoEUoY1NKPuTEsYbniA9TOr5EfiEidlGz0m5b9rhGhPXBmdw3VMnUls8n9ZcE2G8s4TJjOiGrVv durGqpInazcm2ju1veNNuOJVB8wEyfqSBAVI7XcqNz/zoZ+ZteWvE+lAQg6ISUzn1sYRTyrw5M2I c6pWeI8BRGjxbZpuFmbBIJvZ2Z9WMzk9Dvdrj0HbbIrwwstyLZoGM0yhWfr7LWiqDZ/MAVYSPJwZ 9BABMBEyWSGk6JZ1hIlB/W/qBM98urLFPZ/hv9+AOHVUzem8LX2JgDIsa4siGqcxSkrvmn5VFt6f eGO8mrsay8vh5Zs52Sw3AZHqKiWKX9w8k3V8gy8IzWaIPGArorAksBLy2zjzCZdh6fd1Btt2EzY5 VS3J4xQrsC9jd1b1fUL8edDe8VwZh8VXXeSTik8fEoRFN4bIUDs657pd63La/bevXhY0LMMIXRai f/Imd21/Br7ah1N9V+qj3QkO7x9eD+HkOUmR8NXSEdZMKVsJx9vsrBR2/JMwcBM59wVX0JSVxiKy cBOtlb+o7W5sN3qHhHgg0tVOAlmcpFC2qd0mblz5qO9PxIF2HRhmjSkzDcJl1dkXoYisi1AVkkI/ b2SIvrFVqiX4HPLdxXhO3EyeEi/HtkDWghh/i4XBASFCBqy6vFjNB6OO367zhruxz/N+qgx+0EWz kR97AeMdi5/kmva0diCAZd4je0PD2sAaMlXL5A2adJgiWKY2ahuV3vISZbX+vb5bDO8Ieczky826 rqRI5X7TtRCISIplnzHgLYZ4S+09UbzFTCMhjuKtuEgCO08nrvdxfV14SViaYHWdQc+8b5RPA3Vw vxnUV1roMEzdXW1+q3ZYkHmy9rTI/1zr0ggZkQwks3tWyVqFjnvw2rt4IngfPAL32tIY3O9HSFgh UnTBTEirgD+o8/KFQ9QdeYrRmUwQ80b5wltRJHJJhr0mNvnWcvcwzMViNLRBrs3AMpsCYWKbUwtk 9zjzSCt14hftNg/l70PGS3LBG2nT3KQTGx/jyM0D5PSb0aOHon+FbnKLJc+wMQgOmy8wOBwN025w CDr2ey0fgAyiZezeX2HxOiE3rrYGM7svD5ldjrOPZmrAVOtPyHG2RpIdfXse6ESNhLz/RPvCcmjA jpVJsE6fWLEJ61D9hudSF0Np8HjKCHacBBOh0zv9bkY0LOBRHDbslzeF0y/BnDzAClkDEolLjZEB ISp68yY2P9fFXLDtIoheESciZtVLpkT7jZ+QTSrBduFuPoFYAcUGtZztfaejS0pyc6jI6Zzg7bVu Nd2m63nUrpHNfOfZJZypTyvv8FMhCtISdoEagjUInR+aVKU7JrzwUCqPyByHvLCv6RVi+u4YLi68 WrI8XOfMgDHDZDlh4fLzJG9/KQ8gx2YwI0nDHt1KJZPQg4T7/RYPScBEHEQKyyS/0KdpYl/m56ap t3MqeGhUDoetzlb+r5nKjHzH/EJwXwpVYygstuRTJKFtGa6U7Os8x7xGoZ6pMVaeQVLGcW9I7FMU krRgu3Wi9NVGDfBT1puFf8cUvRSIOLeJISn0f+AVCtnJvnxol9Pbj1h/+kYPTTIeM2V7Io9/GPGc AuxLpudiOaBwDlpCBn0hioLv5Li15eIERux3p52sEm/9Y3K1OJq3I0FVZQBPh93HcYn4Ka7ZtJ94 W99COcUc/VWWn0viVE2cK+pp4bZD9G/k6t1/rM9de6/MzntyteICHEhQuBNfs4gmmjup8epx3L0j g4qBygWjMwYdH+P+jVsMBD/71KsZ+1VK8ct9KtVkxAcdTi2Bkb20BH3znnG3sI51Rd1Zh+y7hUll CqfqWkrn4r8AiEgIDDCLoVwCrc+6CNsqb3fi1YnXE5b3p0htkvtidonLs+ZolC35Jq4FDCbiIj6u zCvon0MUMNsstYI6mRP1dRmOFcH9Jhb0zP5xMgyUfVJLr2lPBKvpx+1UAwFC4Rq7tI86fRBBjbEN 9MhOSh6ovExIojA/5YLeWS5jGs7yNxOiBIzWVQaoJDunFQKtVg44DvgP9RMHXpT/XyLZIB7Sbevq fNrozqCMBMN7NpeP2ZEvEBfabXFrAUZaqK7p1fCqHy64gyOpiOSSAoJrKyhiY2t+fNqNuqknmNE2 s/2x3Jd/RlIbtdgumHhxmI1eZLECRkJe3wiWXsos9E+sGJJU7UV36UQl3wvKoCLaYQNTo6+Pxh/Q ukh0A+TnbB30OSpOkvmHtfl8OSZ52FU5pZokZoKs6f5i2j3Ne9ENj3F2HPgpdRXHmNfOe8RwLefA Xv4s4zh/KCLoPARoHI5hpI9ZxWW2aey6BX3Oh9N//WQ7DyRvcQ8fA8oMQj6Tq3mAVD//RJDkYCLK X0hWFNvuDgcnyaf5yHwRKVix4iV9HGcQ+oS7Fu8/3yQmrMWw4Heyhz3KoN1qwq1Lyx2rIRls8vXS /DrBbsuUZ4fUK4+4lurfJo4AaXCtGxH0MCnClKT9FXYAJzzpZbisQKk9B13dLMh5AMPN0reQtbbU /3ynFRP8SErqa5bE5awSa4QV6p8umDuq0sB7mOd9DlRE0bC17iCUYxx19EHmJQNW/flS1sIGEfxX 9rHqv8v+ssqQtItoY+9m/CE9Qugk7Dcw56NORliFig18+uki7W8HPjRcsjmi2p7REK6abh+TYc2U X5TMoYtjlDY//VqMlP3XfGrZ4JvSJuReHzYCP4mDvSdTxrrIq/RdJ8cibmLJ7IXwLFkjC1hWxBYD 9zZKFqlTbt7RmxTh7sKoj/B00IzvQJE1tNgh60Gd0NABnLF6SB4yStKFfCDySUyRBwAr5qYKb9/+ zfBBh1mA4n2pnOg6cV5lYMvuo8vpK2B5fVARMaFU3H1MWMRDLeEMIT7zWYJogSJ0qDQw4PNw5KLq YziW7m99yZxcM1wtE3mrOfrnRov3/7A7laCVEZnB9+D4ldQBpCInq/Fir8fIlq2P3xEBHDHbo8Zd SLMoaH9ivoEffuqbKLSCFDr9zOZYjFZMKE8/pujghQu/4DOXwdprSCtJzmrrpMSOFOoJiZxLGCj6 v4hfQXWIioPALW+8loJff8+8yhjBz0nbeaOY9eYTbeoJyEiM/ez20jf4bZ5UFU76SNkVu/GLfqix 1RyGLYzhygGzdSUrqwVuPsnozGEmphYuoFo0TJQ6CyEO1QX8VnBGDw8n5/+2DJgr9dsEXhNeWKxY bIe3W07MyqRsPp6EitmgGa71ccEQB1G+DgpaN8XTEmbVNRaEIs8a2gVIL5Izd5lXsqucq4J22JsT jj+ZfuEuIBNCN0FKIpzP/vdjDwo/4icKieAPz6OlInegaf9XKN7INXNzifQCOCpROznZDkspGMAZ 5TDLylsC1cbg38htaEyJHF28XTUtNUTZ8pa00KhnIrIf82pnBh/8ha96J7OEj44GcxGddz0ZxKQo EnT1iVTxX6Ii0hWGLLrYWZT81niou6VsC9K0d8Zq3jKefb7XZEJtYq2KI+khq1ZZ90BRQnMchiB2 32hfVB0tG3XNugY1v+noCxkQHe8/ARj06Y9W6TC9g8fZDhUM/y2JbO5jNG+D4yBztHCFZSAcx4cA EEWMXX9SyXLFS21QaSKvUuYGwOl4SVJ0uS1SiJDCrQ7hSfoTAFt+UA7WRc8WYOLGcKiJyrFxlJ1W u13siEFoDJ7sS/byw1pQALbalMsIxeUTUWBGoBOKEZ2D10Ov1vvra/p6XTKgEaG7ah9hmolRMnIa 6Jz772uC8qfT6NQMKykr+mwibD/vxsCdMfA0cD6jHm2wQOfA3qCjxfbGol/t2uh3GyuseJ/f81hR uXU9+DejX+xhNVJKCIuKZ1H/Tnwa+KUK0i+hW5xQUVjZnOzqXrksbfQYX2pLIKwGds0Gi0uKCeiO KVVqL2jO0+EIzsm3WVVQ3IZVA6ETQGxJkBHbBokJc1qSskO1mCvmb+gQRYdtRVuXD4N7gCRdHktQ DFCQm5FstzYpSkNHJGPyR3hjhPas/7imE/s9rf3YMmFkN8LKJ9osIff7JF5vsxJWEJHGNGmLqiw1 24MirADq3LkiTK1lwoGjqmwRxEU6kIBo5mHp9CFuoPrPsEhV55pz5+lhZ7HBkG4Qgr19fInum0kG CCWFkzBjoq9+SA97Why+hg7eR1UlTS0rmy5VFokt26zeuelWUxzoDpPmBnG/0JNg64jXrgTqbWV6 KCIOGo5sf41kLkOLgrLajPSyejAJKHHdX35Nz0lbNPYNaC3s+DltGJ9rx7oqlcXjoiM8vKDHlA4S y9U7iJnvJzztw7MHiaZzkRnaaGFXfmRgsZ5L3pSiubiYq5MsO4PJJpcQyx1ivNoWVKbZ5K3rDahF yW3Pmg4giOx2pgqot+sk3F2o/7PRJY2L4PvLClsLrYFy8+NTjTc+KOdUrOPDD0H5dPq/H43DfxVJ IkcMNu/Wtxd1tGVh3zsCrv7FGxpsVxlVELNPnYIc1+y3UQ8oGvC4nCvWlNcCWKyK0bT0FU/TGuoj nognIRjqa9kPuNF3h+92tTrSnUdTesjJSEPO9v9VZ9wzBsF+uNcPtA1C3indFyv5KIwFHBqznW02 8iAImlkq+EONv0zYg7kGhpiMI0fJy7Fscq7BkFQcSjCSQBs0z4S0Vf2L64De1H7hjNSKl4vBmfTl W6r2CAigs7Es6+IqEaFQZcug8HliduGl4Cv/4vTQKb1lmqMUmgPnqakBvJMOuQXbqFdeCAAkz/E5 M629pbNl3pGH2hFY8zEXHSHG9ZmS3/t7BIaT0AzBi2VjNTJtSQUCmOqNhihoeKFFCLgry2Zd4VCL 933V23kVowvrJYOXMTD05xA/tmEl6gZgs8Vxt4YIipkjDlwMv5vUu/lUc7d0dDIMWDnwLREDqPZK FtiKFv6qJGc2Zb9uBbTRV3gqNWe7TGjzAqvdMP6j9iNnglGu9JsBN+UfhC/DBGyFNENSUadmwwrT JvfF+bT0GdmydUcW8yM/fVMRIQybcDaGkySPdyRPGzcoQ3TWPEEZ3jBeHvVJX+PdVxfB/lQYaP68 oJEWOF0jU+pJlENnxwGf9mXRZxwtazwHKLItsQW1t+2HaYlXXNnWgiNI1TLKzrjAIKGDcB/lA6T+ C+NnXAeqebPjj+F8MTXMZsvTijzmnYLDQaHr6vVL0unlEKxE33N1dKp1vnREdG6po8eLILaUHMnm SnmE2xcfZiK9nRkUKYY4vMkA7JCvmRkL72yKK+ZtTi+WjoZwDzOoy8WbC40+OKu665TgVz/mMz+Q M5ZTWfntthiS/LY8erJpq1iTi8PlApSDfwdE13RaNuN1fkqG8SunBSLHU31H++qoEXS3BRxDmSH4 keXiUD+520Fs/M2u/sgFauEyvQoK/Ld1mLwnXjApdu962jMV1ePtzbyJQLrcz++nG+YmD1o1zoqc HPCB/suYgCExGc0R4+JQf8iD10ewQoJMlMzcjQ2upewiJTvBiEDS2Z4V462iNJ4W/NCNotazHTUY 18RTeSAcy/J0iCEDM9jqsECVfOruligL+NLS8FdF/zMr/gxiGI8AlmkDYZUL5Qbmv+GrU6GPcESg 4PaLX6I6FU7pbFxRf3NV9hNtdPHE0Ypq8TM6SpuQk70Zj2EHGRXTiV0ztoHGpz0PV1cUz2dj+A7u VlZUcMUieA6ypE4a+Z8cn9/VN6o0mXV/Hm7n4sIbvaxAvhnbgd99zZaaTKkCEJxXTxmAh0esDPWq +/ZSn/NlSXEjutP5fYEJKold+bJDShwXcUZUUiqFzDTiIpFV4H4UmL49GbHwW9/BLsz2VwY94k6M 4AVzp1CNzomLVwVKWe/+eETMWzvM0aHWHhuf02FdPNwFQveem1fg4qKVZH1gbvpVZCHUSSWH/MwE A1SbyVwRHZQ1WPvVmrRklT39lGtVn4rX/pTvfPnhq6JIvfwkiY3ucC7BiCKfLFzTKMwQTluf4esZ 4FyUxK19ktUM6BTeGtYs6bFCMzlyILqnRxXjMzJhdHUTShNmeps4DFn8b8a1nzAvCF9ZNmQwLkWQ Hb11GD/MnTc7lDlWHCEd3g7ymJSiT1MBZl28a95VQ+aRk0SNxrEEPSvFz698uyoGsih4KlInscVj eE3EdMFnJ8VaCf5FNKxzX1qkAYnDdyED0l6JZnuhAq5JpQWj6JF+Zma4BD2sBxlt8YjXgdgTFRX4 5ysfCeOcNeSfcrfkUeQl047TnLNNQ2nLYQ/VQ+WNMvYoGUuocdzA+ZLKpKCXj289I6OUg1/7AMCw 32WzPvok90VLj0ON0lTM95NupvFvYtbGXuSMsJvXZcdbg8B5v2gGSVqV11KewU42K87vvO1PPG8g 1vk4rogRne4FQ8uegp6TNHiZaL8SWsy14Lspi9s0qL55gIDJ4q0ZfFwaUO7i/+rYGqLV6U6D4sbK QuwiuEJfyOn2GhxN1InxpD4rsf5aMcH7nVn2yFne+XEDbasiHr1ajlLNGXsToIJ5A+ezMPI2eo/s 0iRb1cDkG9wUymutPahsYEqYe2X1ltLMqAIhpwpPntJI0dIq9wIR6kjsDKh2xqv7a6TxoXeMXvY7 gApJ8pHy8rNFZxNLr2QqKhZ6qzNdvyfD0m4qeBunWVufXBwLOSbuCqjowLprxDTxzNXJ3GjGJb4M S8eurDa8pUIdBnAYXoJI7dJWHKtwnRXown52Uot+JY1GglNU5A+Eb4Qqg9SdMEorsrJxS3EFBAzU E2z4z1QabCk5QcieBN1iLwkDFUYCEwVqCB7k2bTSUumduYYSRsopQXF8hYxOx+Qispim8hD1L0Tl p0gHD2SvNYRzNGJUEBvdTNVj3hxJ66o0OcSFbQxtOJ3qkg+3sdz+PZy5LY7SpZ1sQkNgFhcuGuO6 UL4dbR1KABjGoprJLFl89QkgYIRhbl+AQOYEZB+MNX5TUCyM8RRu7m6Z1hmRqy3I8d+0TXIsS4u4 3CqZjGTQ51xMUw9SaU+1jhKTFa2MjjIplAu1iL/ZCy/bc5rXT/fBVLHPSNqUe9wSmkfs+HOjLkhl 1qZdrkrwJ32as281R2Nj40gMT3RE7HyXwpbQ3ZxduppZwlskeKBZ+WAhnQrRm4NCdrSqmonqUcJb l+yDTN0G8eFPUx+clzQH2zR2it+J65SLirxAaadOhPDeHG6nZRN5JeFnWPsBMqASr75+gAd88xON hzDMXK7/giGOYitGCjnYL0sRl4mGDfEM+ZkFFDfl/UdoXFBGA5Kw+2vAiPJQeaAcRfMPhGNhM38L ZMTvaw5/qv9UBTBjgCxyO+wEw6/hTiVTMPIc6dUK/nGQsD5nuHHNgfsPKamDx7d7x/pmzGB/49S9 j5NACKohGnjNWg4xCtQ+0SxiUQzTq1Z3njkCGjqpB3sx3+CUN5DTRlupx3670TBSGgBphPGBq7HQ DrurUIGsebgI5JDrK+0zo9AZf4s78dpGZnkRwI5HxwD/rqzVXbghykuRCU3gzqdvxeeiEexmDMw0 XECW0InDd8uG8sUNxzZrCW7vxgq7gJUAvNRwl7m50B1QAwl7X0SA6vfs1hDD3cOnsGHU8XhDSoHS ALf92338qyYouYFZH/NkJJa44Q1uiTk0TFz4AJ0ILDjMl6mloJNT4CxXEFAyiV0/Jb+Cq5ub/00O l4gHCsXqiG9vP2pdMcvKt3XEsh1qoZU6isA6PUWniYKIyL0H62LObbTQLXVj84C15r4M4dn6iRJd /5qVWnC9SlVWK8Kdsv6TNYqh0G9LlKlTsDlCa4yNtckRoQ5aihv7B1okPc2JCGx6V44tw091QPx3 rwAnZu/ALdu+BUJJ3giBsHUUTfBXbhUp5WCJei2MBAxf53sPiDXUfpNcCioUm4IJNisjTn3RdM6p oznWRO4XcaIPLsRxwuN35LegvCtTZWUM8PV+K/QdZr/BN4FFwzMJHC44pe7VtbLpHFiER6ucr4lX sBmx8kz9vyqRu7hAbuvvKAxvqNjC61tZIGrh4EhwsSOP9djjxJWAlmhFhD5h37lUNezbx4m42u+D L/gO+0z1Omc7Tf2aU7QcCJm8vD7gQRNj7aApswhLbl3wq8UShq4wBqe8zjV7rkcXdPB/PgsFzvxH /0tUG6D27tRZaWUwYcV7lF5ZqJ7zhk/xEcppJCEDPa3WrC0P916ox41GJkOkCNfNVynlBSHiZmtr EBA2IWqtiBV9GBfSn+DWF9BY8a+PRAGHn/uquWnsTBzwinamXYjVvXtnm3RoX6wFFIc8GpQjsRQ+ fSJqF/TqFFJUnH0s1zNemfY0rOuB6Tp2tJy9T00B0IvH/16LqakillyADSHctRiGlanDyfuIGxc8 0Hb3LcfI9BW37kfrx2F+uPIkk3PCSL7NM0w360Q5aqPxHMgHC5Ij1LTW0cIDyoS0oZKgfgQe+vCu r/U/BsizDHvfMs5oTGInede81clKbcNuRS34tlAYGQq/FCNYT6PUTelcsdZlMcNKGMHcdjxGJ9N3 YMQOls1yEAhjluITC1HjmELlslyP2ZySMPs8o7mlLV65NowDetMICUX+wWe7QdODK0saMRNbNIKz 46q3LPD/VkyeERbE5M7KD9iRqoCM3B1t8/uyBKTm18vA67Mj46IyRkwquEe1hCUw5qpfH8XDlVD8 azx9m2pvyB4S6JJQM0wY0UvDn3cXCkyCTeq1jbZih281+dW/MFPE+DVuWjXnyLbm9X+A8bl7d+AG vVG5qa+OyRy23ZB2xVUs5cXLz4p23hq+FlNBLVSi0OddKyChmeGDlaZAI+NyXwJeiZfllOzquys+ XNxWHudUM3z2v4pEP3MNJtErRcFGpy73hzU6qWaMU1vdjRBTqG/iKU2zx5DhzUNyRrnoOHvLWLLO SgFQNsLYqUaKimM9Fsx9pS5EeZNCy2UqcTBoj6eRDbMU+tuD6PQE9ZKXI2xPXghkX+ufF1FN47F9 E4dHTfHIlcKxGL8XV4spEEsMHQ6oboIAZdaN7wD0lWEtN7WxgVDO6l9FJmvYgFUOtQVWWbf7HoaG myH4wuzRQzV81LZd21fDCWQ7xMoI2F53yyK/808rfnvN3Ae/HtLqQa1yaxgbhZOJG2X2nOfM5k45 fBnCZjlQzPuPbSHtg2u4HI0b2z1YZr4tEqxL73pXLfJq4xsyqHyjHmwT5hQIw0b9wOe2be0C4kwy mnvDnkbAfa6GnfHCDvvd188XlhkVLktXjLnFBZ2bF9EN2ufqop+5ymFyoTOfav7Wvwq+2SAiWNy3 2IO4MaYduvxBRVk/itMDCl2aPdqbXq3CZdCpxLwxP62/ARw6Yh8qMjQIruDC38siJnm5OgCF3PM+ jdtJRV3UwJcRhS/zPAxl5EnSOmIHZPifnS6UuvUJoumAeEXjg5LohZfMfBEafK7YMEJYdxlt6MwZ vAYK+TeWKcwiehVZxsU2H4wElRfvTapCJWlpCdqrkMTR4nTNdmh9oMTM2zW+s2DsDnm2OtQfsdwv lEgpohwpCaUe7Drp9ZzoWgrEWUyqFxgOE5uOkrvSmCdLWaCCOrOAOTKv1jkMQ9oQxfmZnMxkm4Rf w0YCsVI33z1NAsIENt4j98kWyy1/nZX3QDCj9Wp0HeteRKXWAx6Ue/4/haODIyKuAE20ThhchyTr cuBY7PlZrfrs+us6uHQHtzExzJVH8UTiN7k/JSEzEWDpo+kRMZqaJC6JYL7xozA1HTRgHaysQtZS PXJMKg6jGNuNuQn1pAjX1ikTAEbuo+FFuDFfQUHa4cmACdFajiYxs+CFEqxvVQ7JkUDYkdkK3QJj 0eY+2ven1y2VzGwa7jFRRtmOitYdxAXx6tJi2pPAthyU15J508Bv5o2dEZaTcwlioehy1nZD5Mdx Ute3taPvlfrezIulM8vDE9vXZeU/SocqP4kVuEVevifxB2dD0an6cJHlCJwiB79kOrFotzG+I6ro sY8xvMWf2ZqC/emUk0S4+nR4qiJEiukQFnOZaTtl/cBrOc9mvwQmhNeWYQ/fUL+y3j5xtXOw5+yG bIwAI1mo3aqPp6RQLTm2HCRTfMleVz5HceCD+oEHJNJYw0ec+0h+d/YrJA9EYGFJzn8BEdPgjicP Ar6f3RIWSAsX6SOQtRtlm2z2857VI3q3FqdvyEn9yLxLLrbTuvCr1XVOnL1gDLUUj92jCnq+zZPc oUIw3j0tnekQkk4XJJ4Yr4M5hIDUOwxA4GuepEWF9+7u8Z7hcJd2pK0n+2eojrPKu1Ai6gaHL9jD kMSSSqwPm2RnoMZ4UfAA343DqDB83MkUQc3aEeBJddgRbLx5eAGKSeu8q872DoMuMbrh5INPMHGp H62VOlNTj7SYW3ZrpwpU/xGV3UFaF8NIONyfK+/ggcQ0gPVwr8MHzOY1AnOFYRTySoQEcgO9/n6S huN+iMoWa2QKmiQDl7kSmsJV7Bh3Ypw/Y6UEKoiSY3iwZXY/eH/OWFXY6NAQinIFGI6/+UKbUw+v jm9X5LMo2VZVYqfrEzlJjIi0HC9Ofdf3At3ZAYKa8OaWM9njzZ82y3gFAteN/DEfqi32W5Fj+Gqv GZiG/SXI26LDHqd1nH7nn5NtzgiOe8E38wH8PwI0lzVayd+PHR0QsQ/ZQPzq7wV5vzn8586cvvrG SpVWEZUYQun5w+tkvvrmP2Ka4mpxyGOlNXS+DAnX++eOxV6m7Z5l1Yy6fIWs6NCIByfSXG3ONy6A BvsBHcnCK8Z5wVL2wtqye8MNsFnUBUc94bitrpQtUHSgnVlSqN3gsxtseWwJkY9NgZUTd0mn+OCf gzXAg+q5K9A4UABOiHdPHswguTOlqPhqokbWcloJW7QlyCpFznVngZnpAIPemcrKAX17yVRL+1m4 luaIcadozdg3DbZNpOQldR76uMQUKdURVog8DBhodMRiVCHZ3Zry5EbyFtWltO7r3BmVEeTgOOnf cwQ7HR0ZbmY2//sLlZtkhnDWIR9HhnxNu5EXPX0Ye459A0f9URgJynsSva26zQpq35aXaUHvIO8D 44EuKZUsFr9R6ZQFYzIl3akAQtoveSv7rPlkovCzWz7jAjFy8Mzy96E/hwl8UXS+TktfWtu088sh QeVUL+gm2UCQ2fgmKOt8xRFeo9OjqfjTL/LlyweV4OT1FoclclSrGy+vNibNavhLEboiiIMp/P1w 2T5Sxf3J14/6g9/paftkroSkfTeFdBFYZeLHTYrIkKoetyw9IXgkIeXN0l9NeccR5FZ06PZQ0/rG sykz7vSCQBDFfivj3uC9rajbAmz55/nWNXxeHjq8uxUdcPDJqjHDZK3VbF8sB2I9fkRuWikzG0iN cP/wcazGKDDkzvQGiS5D4XhGjFUJhZFXXqy8t0yopD7iKR038hnHg+xcTMpTc/OaB8GQjV3EbEij cVLDZ8h80j4A3wMQibSU3+kKBT57HXmXNXyx6RHQWAFIB3jaR3vDMetZNvwKwtbWhGZaxJxzOP3A 7OesOCBzw9yjY9983mOol/0HMH0iH42Wl35tcE2xCwPKxK/NORNHAweUjIP9j/9ssDsNRWGSzLv9 svBNA/aewpRSgNSpm4BkvkXF8YvGk/XQxhyC0C55t1WCYl4ca2XxZnz330z0z59VHkuLbOXgQgMV SiDQwSEP+9Iq2KU/sjivNL/JTyRLbuvkc8BhlmvdmotISCZM5/w64ArJgi6hHNqrlTrVK1mIbBPr e5XJ7cxdiQj7c69UuAENVfa2nRvgYCWXHbMlGa1cZ+z3vxbk24SozjVGMF3sHFSWspsMCRr0YYpL 5FS0x4/6yuTeooBiBcnZmjI8qCOvImYXfo/JTx8yj3jgfjWjXlVWwRxyU9RuWbNpstjRdU0mx5fh PByNBMDO+VDkCI/zMwVbTFSnQ5Z7nTua7y2vJFUTNlCRcECIBnzhGYv02SKL/JOd+ALVQtsDrQjz fRdJTdBNg6Hh03bdJgFCrjHeUc/Qrk2+OgE9OZ8PpiMs41zZdTo638gqdOLcQwtrrKj4CTptGesk SwaAhewh73R8dH1AThdArW6HUPEP+RsrjfrTtt9V9r5kM63H55V0FCtrBamr1lAp1b7u713tyOgm k2H0TC/aGeZPg0GFcx6+07ySPbbwLx7Lqb3K+gljRS6axkLjnk/1zgjxM1Ovv7uo6ffwZlnEEqzE E0qtJglX41a8CC2t112Rg7zKELrAYUzg+0njXfzq7pXo3XlP2ijHD+Brescy1eHdIpK1zzdvjKQo rwh5eU4y0xlJ9yVjaxjLzbF8I8fQIKuvSgSrQXKfosmj8B38gkFt7veJzu2WElJF6Pl6zuvfxm+X efnSoakMKi2xHrQo0xfz2JRTWucwMHtxiQQjwZCQuLqBwTe1JZfDWlS6JXdcz1g7iI30WdLdZR2a DdDe+f2pCYL4qST+cDTM5XL2noavcIV9qe9jkZqR6TP5ohN/i8XfEse4j/HHf/2CgO8rU/7HkzRU o77SJXTyGgCMXYe6f8RtJSzgH+IiDprVMHlh5dvQiXkjA8r21y9bspx2W7vJniwFTavrBPkJ7JPB 0ApaSdTJ3o0fjJ4GXFN7AuPFZowxZuOEyCyYIomyHGZBxKQn4KRLRrIQErERwLUWGAYevExioH2V bHvmzcjFavAeS7AdzrZMJW671rOutyc1Vsy2ef81aV5X2T+AtkO2Sfodzs5Gy6XFQTe7X5BtPcxh 9SSBd8TqiHJnoFRMZ5KlX3x1O18YWOmpfudJrkLlX87SBVSHyRKtvEY9CCwqKVtJCLHo/OEejsMe wUHCBAlhYWuh7GhPU7Jtdvqoz+s6VM/Wo3t4wCcJWDZLVoJcV5O3scP4iPRjQaZe8Afoj9gEkbWh eQMppKHaQ6YmUDxqXZ+2g17bXAz10QLUgq/7Cmjf/9adB5sFybHxClkSmtmhD1fsl96/EDjQQwcV QPoIRHfQ7o8Wrr0mdj5DPjwO40wojv/Jt/NF6ivg5vhLNLYFmfhRUkpK1TAkk4YpCxurZTzVpqt8 i9ytHHQE+B9sWtulCja3gac3EVjgnkgVq0HLx7hkNoqjT4x09/46EMZyCBcm20/1nztsEo9aWxDm gqjz8U3f7uVMoIYX4jXu+qnCUt8S9u4l9JBFnyiXOy5140tN6E1rl81ALC65CCsAYyGf24hpCH82 XBy4rFA/1kzjhNyQHfOrksVB4cAu1zcHJCfjPZJuyZMI1OmIaJO6vpD3DE7G9GuN6oVyzU2RLHs5 L9dzpcpkF8odKIOJqhNh4Z+87a0JBeYRQAmVzdqRB5UoHuI+mr6FVasrsUD1xOmU8VAvI2GouPNO fMvaee/aOIjl6KHaZDEzkngwbHbGcibCeDptFIv+4Ykqv6W/UUOWDcp3GzNndJ3gi/Pb5hjDioFx qSvtH4FEOmX74PKdK7pXFtmhI7HW5+Nfy3WTA4ThMZ8tcScleHg029c/VuzwlrpKPwamssQIre90 PiOxXw17pn/zgD+bDE5CB7Ak6ODXewYCHcPvDPE42Ja3aeCrZsrjLinr3Efzf4oro/P/vLM+JSuY 8O6I8zSCMmp7DzqzOE/xSEOpa8LlCxV2AZadSDGef0wOjJGbgsP4iE0+fhiI/cVS2iFqQjcWoPAA 5DSMIQBqsrLgjHLW3VYpecMvLCej8ue1DflViJ2DSq060JwfMnYo0SM1wcRVSML+NzlHppo4+vWL OWuD8f+45AyKyfjV64YJm3saYVQ+3T/DUk774IQDuZlFheM97cBXfF3XsbLe+SLGoRgN3SsGESzC Qc/X5mR1w9SMLUr1DSBiiHRhMzQUxmtUb+MEZewKcRSrCLn4m3gBNuaQncv6np5RqoMerqYP9xtb o0neBHjFncLaxSQKLx1vYEb6TvtlmZQAFx76S3N4+hGIkAWSbvK4GU+bMtiv7esiIjaEPqKdTvpf 2E/M/XLrRzEbulq42/sY1edzskqlpBUd66KXY1Z/kul73FYKuofZCxjPTAvIGqjiCmUkekBkwAEj NiW9OU0wEkYNgTGv4Y7oNtrjShvblBitBLm2eA3386uINVDdRWHj5fc6OkrAFMgfo53Gs5gsU76X 4l4TN1Xg2yyQEu163AZDTvQ5OJidg3IKJ/3HXRqPauyZSmmvFimO0GbJxT/bqHxT1aFnHaGyxnCm U9rQuVsIVsKsmI+wcFeJPiSFx89tAYDGhVdg5h163WE82VEyz4NTT1HXT4teamd2oY2uLw+JXEXG 7RpR0IDBr++gppX31c3W3yc4Q6V0BchPrskWGzf+srax5VvFAfhqkMAI9ozXzvsLbKxmzEibVQtc V0KQz9EvFndbEnloS9gjxzdzPjF7+U1ols0o10YZgq1xw6vdvOdMpqW7hGUAuHDfLvZlb+CM3jCY I0JCo2etKifwMcXgf9VxA3NMEfDLlRoSwsB+EbS/ZzSxycs1APpO/22awpK9m3SU4m5QWE5dfDRc CzYkpopHlKXXkEpMy9hvLqgo786rL6ituPh+hMTPrNaLv4x/DFXjl6jLdpPupkE1Aeilj9klLCSG BFOtDwh7l4F8clp2epbQhxml93BP41GlYY61PjtpEXzZg4Q1UCVZxf4NCy5qWct0jysMUko0UZXQ 2giRKC0MXa3Vvt0+qoLFJtk5xYLmTl8I4gVeRQSOKwcqj49ThimJMBhQeviW1ZxN400dOo9RGkYn TMNDEYRvP/QxAmTBKJm0C1tMkn8VbY2ySvZWSvhupuk+xcyk0zWYsTrPQoK1HXp9l1nD0G204QwN Mbd1evMlregYv3zcgC/surg/idsKpZB10niib7IHGfscLZx9rF0pGhuR74DS71fW8BZbYeXuHbgj hPXTfKSHCiveQHtUFPWSAY5BF5DdVjYHmdInn7pwmzdMV68UR2SgvRyMZOFHTT1l/6NXAu1RuhtL XKexphJk4QJizxm+UhS22IqtmRfIRWXaX3CYM25TsCIuNT0/lo3HcEyPMlTnePu4NPIT70wm8BI5 bs6obnmoOQKyQwmwayIMx19VbSf+sOeJEHf0ILeXrHBAf47ZxMqwgMKI0dZYzUMEwAma/6AhtOA6 LcYOaM9UaAQvyLygnM6GfhwsCDxETziXEKsrrw+yNA1jPQ0EPBWBwsR1eTJKp+LI+ej5+2uBTN8R gdkNT7LtszrorX+VcN/TXHxdy4SKTHmMHnU+Yx6XHSZ8QC/FY3FSpxj0egXVSYWrxjtPz1vtZsKB yAb/ljo9VfFf+IGK64glhoylv6CxkTayFTwXeawEImtIaG3biIRCI0r9q1/apX+qYfOWM1g9Sq4r 2ylbxyQ9L3VQd1kEZuE/oIOC/lCVfu4wwxHpHE8+0uqhm62u6cipd2Y76PdoNZw9uQsaMm2yrLDE iMoX+J8840NFP8UEPynTsCBBjdp+Vu2p8zTUskv0pzCfNRlh9bBtWwWDdav4NMJ/ypZiOP4UKNg1 pEbww4uaZst/hzp6A/WLnoCIYDywzSTiiuNc9KDbtq4W4cxC1eyouHfSxeyy9pk5f82YHRoGWoHD 1xguZVAEVjC4flnDRtUMLlJ1eLkX1oIB4ma8BxFYbgwzxjIflUZScftfXUa/Oui7dQ/pIk5Ltfnc KWZPTJFblAYBLir5I/rpQwo9mZQpyZKbMoUueyuifnc65j+FMCdDPrcoyTPlPnqRfDnpgiTQVsW5 dc/j6d3zJCH+17Eu+OxqWoQs3y63ie1vUwfqcEuPMkC7axGA+lzkifbUkReRTd2mFHXGVEE+nUaF nRm5GolEsU//zL0xzONKtJfFwbRi/Yd2OlsWjh6JJ+AB/nfI/lMVIuBBRZnNgzOFzpU5fTTLHLiB MgahI/CgtlI9OjjxwWFxJHC5IxTyn+y2TCpfR/as7Tb5hjrLrF7PEE3KuEzNR860iDEiXi28FJP0 ahHB5g+7m8KiU7A4c4VgBnTA7OZnO85J7kihZffl2D+eRAv8Xqd8dvDrNKG0uuxffB4NJjVsmKe2 N9sAwQn8koG+wU3cUy+PkQj8PPxGzfH+Ak22I2RGgXcv9Z4P3BgoCbILTwkq2/klQl8qUtaSmPQc xNODX8acxIhURphtrzz+/osNlXkGl7Z/BGMvb8hAIAEUAwE9tu/qAqRv/u0E0nE+eYT9zlT5mQgc 0LqyfwTNmQV3CNwp9nJHUQk28AWjGYXSGa6u32Qb77Dkmfu6YXSh5hRylI7qz13sZTPPtkxGhv8A hBqto0/M6EwbworwLxIulHFfNrl6ndjzRr2reYh6OQa5lC7ksXsdJCgLh08yCCn1eMwLK9rRkJf9 i72VNKE23R1sp/HSWGG4+yAVgWsSFKRA0oWFKMk30VBZu4FWegyDzahn0Z+CCn/TfOC66lVqwIa6 tCXp1UtGCM3ltolu9wzaIbCdv5VAjUXtX8Z/ZU0Hou0601f2dYWvFZOCncFzryGM8XI1LYSYPJ7A WC2Q1h+mW+DYkG4IfRY8Y+Oo7772knafO7cYr5tadTwYKxGf1V1KCcR/unF0YXs4dZ/S6YyulcGG dpP12FD3kXRb9P3fJskN8oCZP+Fg2KYAmhMNK54p1L1BtHUNPcsEhIFPR9z+AfWPaTpiaW5+G3Ms XXwZeU9Od/1O41MY2XNnDBvSKL78xexUR9mziEm6Pg3Xzb3yr+YI6MydNRVsrTDVLRQzZsA1FTLP 64Ywf6rMGKzB3ld0VN5XQlq2s95vJnKeRyCWYV6+RyvG/vk8CxkyTH2LgomwIXFv9Pp2inY31fWC 8tVC0E+jFXlegweBFBoVJ8BE56d6q3bNyr026F/1rYRxFr511T/sP+lOWYfg+BDhBZA3QElYilPi z7ER4ksmrhhPYZfYZDKx9bDdz6ES1LUr8zi72uj/opsTIqMm/QQX+WdGukyMEmXpZAlZ22QcKW+d PKWsagXSoLlJ5ugGTXPcCCv1mSrduW3yVJkTiwjz+WpJIRoo71pJViaiB9awqXan5scEl3ZanQpM CR35fWUBigmvSCtv5tNvT0LIWUO0SDNI8sF6wI48zAmITI3yNwCItxbJLm404YK+3kZ9Hz+mM+Cw 3qD+eds4LBxpOng+bYWBZ40VY+o5B369fcg1cBSic72zVUNqzrOfIvDlMbkLDSufiYR/IbeIc4UL bX2vNlyDLQqF5mlpZga7S5ALsqFo5qi2Orr+XR44NtuVztyXLuHMdqIiOY9SBuFN52tISFAKf5pc /oh1n4a0M1altcKp7YtCltQ1EzWoCdpPS2xLz6J+h6NQ7k/TwfKg9w0Tu1yVxzhvq8OEj7OdNIxq QEtoxWQTmNncAYUvTwHKUdgTFfGy7aKvtoPtX9wz6lO90UPuWlOGVkN6kJHNCiCL+daYpwk3eGjq 4MXO/CM2R6tSWc3al67uS9D+YJ2XINBT75ZNN2CR3SaACdIICngrclDeofnjuG2DPL0IDFldlxQm wKAJhsTRKjpsmRnwACDS4JwNDGwpqEMfJ8bq/+5cd981kSuKVDhoDNa1pz3vCl7lATqReltz9+kX mEnvZbJ3VyoJTZ2tUfXa4dSj80/oY5Mln4ttu6ogrvquZxoaTLfS2aWTO4vkMHJ7p+i/zQkywwmI E+Dl2aXFbCaHqzVevESK9iiYNP9aFXxeq8o7THzOJpaX8YITOXRPThKImbPBq8+1L0Art8oOBzrJ pt5b43+LoNhkR0IlHVYwEWvn5mFN2xWQAHhQS7hZG8oUyueQuVHJOt7FwyDMtH9+kwlw6KGo4YUH PG+LXtV0jjQlGz6RWQjCN0ZugSRDTTDYguzjI9T+8R5JYqAN7cxEbfIHHuEGJphQpeQDyAuy4FSW 6F8ylBt5P5PVY04M5vF0HjVj0nYVNpu+J739Gk5VfPt6HCVtR/w9MK/JEZ/wb6o+AcQZvUcn4ezu NjxS0gR3AWhWONel1kRptusHVVYhXenOAvRR1N0FRRnTuComf1yqCRw7iiMyZTup0S5ZXzWTqt8W py2kgKDLV0OU5ZPYSCXCzeQ7fusxRWggJzF/yTrmImxTz7QafqYB0Adqj0AWGoJ4usKzviyyUg8T rLvATlwooqarMGZ29VRcjhuF0im0j5MCCIj+3X/wFc8B3tZOea/dcAUnkWemEDD9WYajVoxprWLX qJUH9+zGS7tgEW9U+gcT8aPMAfgb04cV10beaboCv6pstt12PUI2rXCfjfBWaq19gxugf9qgKOQC dy3VKX3AEiadUJiB6vq9tee9M5WEGSDQ+2YHKC7zCXFH9BetT4dBtegXVXxs4UcCTPNBod+znaAp 7Aul3Ro5InSMgIy2E0s2xZB9bnK5Rt9c6nUQ4XqpXqV30ClTqmi7iNiL8jNZx1qkbXTqyERT2otI 4qI5E1jq5SONtinDc5OHr1ZgxFzRVL2aChOOyzIDqw4/w2ZqoC3cJ9APebmZJuroIvHQiNyNtYJ6 6TedE0ihRItYFavswAh1ZiyaCwsGYV8gtF9fLE0DHsQxrw35nIVdBlAFJ2wKMVPQ2JykuBpNiJX4 SyRAjP9S2Mpw7MHa6JNpU8PAY+jpf+Ci1dLUqh5xeMbqIgJFUexrT0Or0c9B200v0F563RU9NaRx GFBOK4ybVJeHuA6KNQ6zh3iz0zutkRqV0XFQmp7AhjVVGBqg/3h7F8zCXikrt9YQbsSbBqYL3Y1x jqbPRWtdSZTLz1qhgEsMgZV5P0mFgw3aX4wjDP8u1iP+YPadMZOHTNHpkwUtD6P7ar0e9wjMyO/k 2JynLCQSQ75G63SnOueQB+JboI7ZMrbZyFSuYVXrCN0BC6hxPZWVi3Q3uxJl1sgK8npOPveJltG6 oCxD217PxpsQm3IDQscTIxsQPZRVcx9rgFQx6VBFUuPr96SyWdJY6nKuaxDiOuC9k45T+arxaHie 5YvNpqNOQmXvnym0Dm/FuzCqjV3de1bBkMqKunLEM0QARaetCpVaw2RmdrdcPogtNMrzjaulfv69 0bOmVMF8atkMABmsm4Sd7u+kWyxNWGUjrNlH8PHX8JPNyCvCMZcSzqYCrSshi3qfdXyhdUYY9iWY K0WIK/gg6Pg/JV6OaUQkT+TPsHrS3zUoaSLFwdr2mFOj4YnPRvFRxQUYgYJYxGZ/CrA9+sTU/T21 vU+971o8U1soX3lbU/wki1bQfmmcF5I2GUsZR9oFUuE3whYWwje0hq/ko4HqbsjTRWczEplxdcr3 av/msnUHiUgxwUqkS5KL1ITJX0pQei+EKyM5AjoY+CbM+VTQYvJ+ZSRXG05Y46SkvhbajacUIQ7G OCSukhs+Eh+TVEWrSIOa8vxu0hfobZgjBr4x0ByaPFgzfIC1eM1mHMYzIqI1iBhnDPFlGiu89Abh VW2bk/8u7E6iB+nGosfPLhwgLZosmntllMPcwkqGHsnOVpRWtp/BuKB6FNw++Lk3toQ6cvgP+dRG Z3N4p0Hn7U6ntrjlkFiEK6wCJFvWTVr5f0uoxpbh91fQVEg2HCUH8NVbIml5jv1s+onnmKGEqUrn PMVtO5ApTcBlYSN+YhY22OKK/y77F3ENHHxKnErXPcqDYswPbWyuJY9AmqES18H+Sh+319L1+UJ5 lQrGvA73asepAiKopuOt2TYrGSPo6l+70BOhtE1NpDAL/UtspTdD/TEWUe94qgpLlAS6ug+RSknR v5BEyLaLXmzegi5okjdAfYxFuNS+Ddnro2P8gEK2ivUZocwXCSSpXAqZQ7SFDiFZLWfWN35QMBIA yqGP4Ktcjwk0xeV+0p2F3GvV9N8gA4yt4JFH2ZWd4zU2zlEhHYU4cBK/Xwdwci+3SumrdqhXBY/s Q7/e+R4DnNUBslPT4wyNniLKJIlwEzY6fnirFCk6wlpUD0pNkFYQPdMr1tE0l5qOi8tINKK0JDIb +hNF8EWHXZ8l8Ic9JUmgSPK6Az8H72V8giIg0Z+cfUZHXrp2ooia1Tvieou+EqmrQjKq2RSEy1Hs rbk3k94VUxSaIxhgRSXwNL58y61m2HUUtiV0sOPE+F3ira6ToZfOrDjyaFfNUVZZxva3KPfE96SL 06800pBqBCfpR0XmOU4xqo1FhD8UGCLkHh9DUq7JLFABMvbOoMS7qZibJNJJ09C4j5MLBuHspo9c 2GfNtfhFBXCd8RQ5DstJTfJ75itrbmxx70oK0rjCA7nVq9o4bSduHS9qv/5PKPXpqsIGa0KBcxhv j1/yUNr5Bg2VoIDCZv+0fkwLmBNJlOikhdUBKi3UzmJXuFD97VpsczLaDBSxbFmAOTvh5zgAiFRK CLd7J3Pg2AsmhbmUVMxnefFdsC1hMaEz44dNx3ojRxP+7Fg5mXid+HhQaHhIuGIRIN7c2LTbvmzB qzkCdH1eQSVAzqci7MM+4l8clOcA/7LPvdgIIAo0jo/eag02pk02Mil1avgbwV8idoZv3Vgg1eCq apkXbmm+2aLdgMGhl2EEL1jHyqN5Fv8JP3lxd++GVZixFUTX3jk/J8JGAObLG7saYhr0BuBJsO2w uYBHhFbjT+I6F+EZdEIOHhhOSpPG2EcauxZ4dC/bWjO1QqlCcioBntptevRkGNnhaMCuG7tGnJgq DvIE7hut+JAHlba24q4+i5JpsIGYVDrWcjoMp6p33cjFhUSbzl4mTs+KiCPRa0pKIXQtZ3uFJnG6 rRVLMoFJk32J2Ce3paK1JVjIJ8j15fJTDUSAJve9NW1WBhl9PaZsd95H8WmRcwaeN7WEMgQxhqOM QJkTQDad/zEO2bG73eZJIifwPwYLQTLSBTNJOCOxHOBOvd5zhQDjcOtljj1L8S7EroKtHiOWox1f 7Fc4Z897/7TvcihjoF/wUuLW9fuoedXzZN27ckTG4SfB/0jwLTK1TIjo/XQJD16waGMe5j1jkzB2 tS+eILvN96n+05iESAYhBAWENTSTShqvvbY0ZMPG1vpep++/zoftu+hnBduHIXujevDX8uvgEBQo CYGLr63GqOMzs8rhmq8ZM8qeVYy2MggyzlPwqysAElszGlSIDTxXLn10Hatge3swIU7R39xgZI/H t5jNvRbuuaQeaB36aZsdCAMXsevr+ihUSDyUntgpG2V/Ll9Qun1LQ5hZA0N8bPbWWf+pKwKUUanT ERQQEorz131T9D2u1MIluSOCRNY0MrtdhWMoKwzfbSh9m8dYHDOfcocf+JuH2SAzz2d3SShcHxGU M67tR0Rw6W3VLjlbRZ5L/Sazx+P88S9YgQFMF2pQ2jU2YeU6uyWe7mojLyJvfSwP4NlrnvccxA6/ 54TJaOch+g1nASpEtba0yEVstB0Y3Ug4m2UyBXwnjJegxFbA+AiIZMgYu90RCMl5+6qMQITINaHh E2VqCrxsVFAn6jDuRSQwSirhGdI/bvikZ0H3hrXOUG9B4jzwNJj53ycJJpzVczuTHE6wy/CLojqR n+UF55RMDPsAclR232D4TEtmGXjmUIUQNW78XS5UB/UoK5cQKikFtLRLKoCRll/MY2+X77Z+4qZs RUhRObDKCu12Oea9TBvyhi1xUbjRTNj+8iCAwPVCMUdTi3+bNca85XiXVQaHMkZNzv3mRYQ/U3me 578yExGOAteS5fyzhAZ3ewFAirbARo51U2UloUePua9R1gXguP0r12vH51XL59trX0XigKEuHQpb GV4TAku0JaQeUWrgPx9UaU2Y0rukyXVUDU841Nme+9oHBxKIPEEWyJrIxXiPEN13RLwSdaGXbIfZ TGEZgojxmAtcE4Ih9fiSLhKis3lmBI0+qb2BfuXJ3615a8d/mKI1wcqBQ0aI5bFgFq3rCTSQ1qlA 1YZB/Hh7Nnhrw39Lv+BrzA9VQbN9xoNlPyl1cQ0o6ZkoM5oFsBUB93iCj9SN133CLe1A5wmjvYyX AYwWXqUSCSfJTGmaeyhf/m69vCp5j/RSy47dVbAnnWLFMFC9h0xcDbfIIUW35Ln8pnDZyFXSZ8Kt wwsYFnH6aBRZff/qCHqdHPRKoYyDWQ1DV5KTKdSQ9CZaRgAyzm/l/NB5zD+oZWLCy9HPnogIzlC+ bAVx1hkQJDNUn2KCG9pQuB9pwZTEi6ddtD+TC6wHyWPTApAREeqBOjKZFYJu06f0h7RxigNDhEsb wi6LbV+wd3j/4jc2hubxC/qw7B1Se/ohnMDlCaKCNZiCOYFkelXmMpMCooOu8SO5BCGPFB6Kv8Ni 4rTyzcZPVF4MSBzfT7GnrbjbOERvsdCRzVsARSQkqN8EgW4mx55bQkNT7vFJa1akQ+wLO/HmZZ1o L7hM/FTI70XNGYbSRTSi+0aIc9INolxtwe/upqWvSbsBMICr6vkBh1Kc1VlcqN0T/QgnSzbBOEHm KkRcjgJLWVIDEZsuHAK5lIiQEH9E6Cm1/OMDnwm2Uk/FQNGD3Nnxs3pUw/sAZkAO0xAIidiCiOOj JEQPPE9mfsEP8m+gP9R71H9YUkeRrzUbMDK37IHtHODmKy/riWhel1UkUR0RGH+fNIetlv9fU8Wk P7N0So1oQ/HTmdp+p6WE0X0QfvUCVbK03pidfHsTaq1zcWL+eqTV0FosWcA9Sj+jXjzuRFPPzm+9 NTiRzJA6ZVrp0UOMcCjqFoo8LdzWgfYVNsAGVnwECJX2Tdo75xugyrvGeLUueMKH+5TiefIzBf0z nzJUHnCj/lGmQxs65lLvbygIjmGE8KuOlAD+QrMx8ZjXhXh5vpJ/pGc+UomO0CPjj61ItXzPKYpd SeXZJtlCkqctThV7LuWaMlfUJw21nPTOPrs+5sfsqQkOz99DVKqasL+4Sk14rf/+O+YVi453pvlj JfswvZ7lZSjwmdG5BvlJ2RKix/hSxRurVFjTWo4YNTJtBkRU+fonvYkg+Vg7YtOMyMcI7DEuHhet sLrgzCHwl35wfa3VMkQZnOyxXkCfOWZFbh/6gYkS+bB+4NNnKPUn8IPnAPtBpw0lcicj3zfciorc gqCNyJ1G4wSqyV+Q1cmYcKTi9op0wttX30I2CfECD6dSoLWUsP6UeRq7pGKl74GR5zZ+fI12z/fD VJ/V1bOWdQrOKP4+3LEp3pb8OHJsYfFSr1Gj/JHbDXZ52x0kRK536B2TKeIU0QRUgzrh9UV7hYZN gD3fYOj8eF+H0AkgXWj1anUkuXQvQIn0R891QeXwEEq9Xy+vLJvA2jUWx4en624Pw7OtXVJp3FT+ ry3v/7VVFFzQ4RGv4w1oK1HESyJPDAjFIECqzQKXY397ngzDr4WL+hxuzTl7F4kMQrUVWz8pYJBT eDeE38NRsygl0AbXIWX+UGX0SwDKSLtdCYvnsPh7Qplkut1SgWDP4CX6TX/DUu0e80to9Vfj22x7 6M0KEqQ9BGXYqxSfbhP8KJPoYQBJOpEthjpAM+U/8fWeJPYC7sPcNrrt0YMiMkUY4nKVoUA39bfh mObccM57rdqig1ruRkGjfDzJCU1sbVRaZJm0tSkXd8/yzHinX6cwPwrkN0N2xgUEXXk8kGhoc7xV 36AEIDi0wkXqDNUtu1iSBkoKXGRUEU5APe1EXEFyaydZocUwNLA+Z55YZHUFVyKwYx+QoycXJEGA Bjj6h8/WzCP/AfmRCgp3W/JGCAoByp9I6puDeOR8UlatqEEkoHsmwKtGx/TLBMKhw4OrH3ShBdHi ET6v7ymT8ouOCnvUBP8+XSiDXMJSwTB4Z3CC8UJspyu/cfvGPZId3y60J+VxwRw/SQu4c6kBRvM/ 1AIWHmjGVhomoYPsrDtNq16v69Hp+4XTdkU/BhSHsDmDMuG3h5WANsLIXRlZER0Jzh+OhrE4Sf2v MiqN1cvCfn/nKZVTyIx7rAwlSeS9JBwGs3bsoEXgYUqK5XvzgwlfgW21oBMebX0LbDZ9lew9yxVY /dcCTSJwYBOhU5GUGO+GKC8tlfUZafGPpauuInhpX4oG00LV3w266hgpy8OD2INFs8SG7H8XFYuD r0V+EmiAwgnxqvifDwUgM13+YXjUb7uP0M506oLBPpn8F1WNUeIMswZLPeqb09NpYL74l5ugyL+4 GCoNx37jFFqCQn25JuKhD/KXHctaevgC7L1WmoRYzOM94hEZE7ggNS2doqYukfVn/ZXbMWSpwRSW pC8KLwgeCX6kS2Zs6qRJjEhlGSzlFVauIckmvlOG+Inc9Dbbaj6iARUB0sGPRvg9Qc+zPb7pmTir 53ovmspz15ChRoSz0XSodX/HM/Rbq0+txSJMck9836XXFwFQvD6Zs1pTgylAZ8buvwyLbHvKHR5q B7XRj5igJxcnc/Ar2zR84Qu/08yVl65l3xiLzRzhKWYDvykgZLqZgNOt7dKn5eSPV39U8Hfjm8bi Y9viNM2RqxUx3ySueUNg4DGX9r+iZscyVawOc0jLpoEjfN2Yf4eGz8eCzm63qJrzGjTXdVwnejj3 3DqU5ca004Gjac7Ya5hDPkh/k+gekDMX3Az/9skk6AuS0Mt0/JJhVIQ3+RuvguUjcVZejX4i43Sk IQXpjyMbuJoVzPihM+rv2WhQtTFmedC8V7CAjdGdd2PIhsDhDt0xF07pIQF24vhSSL6OO/db3G4X LehnuJtM5O4i+Mt5KU2IBoQoMO7fUcNGoYjuRKQphzzvgvNC0MUgJsFaJkd93910IQS5+jjRU724 Bdp8srpDuWQMzFO/Ummkv55VAmVBn+KtMSBLed3MbDb6qHsUCYi4KZcdnCBtKf+/d+QknUZga1wG UIrHHoVYPlpPDhl6G7RckeTfBovTanIGXUun5WnxbpAsLAUVanTccL/BGNgBxAJEEbsB4Qwz0la/ QRLiZ8eWsdlmoSoGJ27g+LlyllaS+gYOKeNQe/RsKfqq9NLvVrPMoCz04hOKKXWrNa8ZA37kpsUd kW1eHDWKLXsoDO9qRX4dgor45KR20p6N/ySia2vwuyUZqLdJ3Vy6ApDWd1H0aXrGHGz8mePpHYpB nDXT1RJ7kVKT6icZrfXM4+KXxL2qiOJ+zoru6yIhOGAaQjkowbH7JhDCzi2Geb90o8HLdPlBsMWn plWhUeBQE4PFiTs2A1g27CgwtELssev+Mn+OppFRVwBCvkMXNXl2Szahy6KO7zPAZtgpt3Jl9UpV TLu6fzsBiLUgsBj65F/dE1HIulmQ7LuSJ81edZ4+jVcWUtZTNg9vESJ/vBQ0LSJmXE/JlOvL9sqJ 2G3/ZPKEzeEErIAx04tyO9qbl3XDs3g5I4m42zESsgO6w202Xk0nGba/Xs4X+G0xD2xF29KpPHMm Y31rFdiE7CgQMc+hb13bNCkg2uY3EiwCemhpm5oZ5x9+2z+iHpLUBeYlyTysQm8+eegXqVb4c80l aulApvaqmW5zH2kWABqdLVvrRqwfKudrxMFbl4NA+D0FBQIVZW95lLvroJokHBm2UarQLluUySza waCyMpi3lJVRXbqpTr5JY6x8QOgCUqdVvJt4tiQqo3JH1zCpX/x1SSfbIou85cw4jbItzfJBc5by UQBEFAX258pxQcF7s9yXfjfxz94azTtJhOHigCygszPDj7MUFTaZRA2CTCwnyYPk+mim1ml/oaVe IAG2FTgMF6zTRgULF5X2NEyIA8LtLTa5UktL3Vug5lLZUZx9A/4buky5viYWK2OR3u8uecBV/5Jx eC/4AwLr+mju+z9uUcwm1/Vi1fX6aBdU9rgGWolwBHQTJz5DD8OJcZ/sFjgA9IxgSPtc0GNWriOQ rLi853Yzd1kYYql3dmyUXH0EnJplSHohGPsI6HU36e/AcIaO4ZXLmqr5fk8pw4mi4OEa7mqG9Een FYeL8KVBCobRGIoyYiy5uVIrOn6KUVrYkIoR/3CMEhGJTYHnvPru9m5YDcN2O4LwCn/KOF5njW9g 6+KjScLKEWth/CIRA/DdwhEumFUWIJyNf8cjrHmPL7s8+lzn8GCCGGzPMWpIY/hhcG5U+vhyjZnv OLmmsr73cRgRolQq2zXqjSkLEk33hW3LK8RLT7E7fVvKt10FSRpfIOCP59mzvdEs9yw4l4vxPEAa zkSStpHj4T1Pu0IpweuDyVummsIONLQkZAO+gezWMBuXbfwKpUIrUoAXj7lbVcBh56fmOc3SnbpW 0A2ywZJboipVcIRDUGzkRjNtMwbOOo1vJpK6Mw0lvsiS3vo3l31q/eoZdLR6XadPhuxQgiIpmsBb v9R4xeXEhkVQDkYs8ni0vAGb93rxH7s77QCOs0fXMBGWpDFzia07nYbYGn0Pyo4MXFDj4ESsUBqY OxO1Uovwut4nwgnoZ2IjWzZL25dQAsrPaF6RkTCJowLNXNjwthTMoS3xhSyCCiZ5TOjWIfHsb1+w zUCz5J0+VotNr1DeGPg6g0l8zE7K7PXBYuiyyWhWNzP0P2Hhjfjn8ou9bbcWgBtCFsM74hvsckLO s79aupocOtBirTRV7bMm0vg1wDDf4YuVb5Vd9IN9P7kYIKaEucXvfaWi/S35SyAwyHAzAC5w9Ggs McHdTkjSglHQnRBxn2BlFrTWLQqYbUkBohHzQY6fsrISLmsQOVgJxHBfWAdY1fqZyOqx7vU1krfl bmhhPgOzcmsQ2oRTGGDseyMgs9fHCjtnPnUUu0OQ7g72YB/LzY7ckBScX1j71pRTeNXeKl+W52eE XzYw/wE+dz5izTEEVFYNgvO5fNRYEfpJoGXdPmWolh5+gwZw5ieZx85+Ug4nIeZoCwdSbld0flT0 zsIQRD7fqqcxeHZoLXKxOdkYa1ESubjY7vynaEbwZTbXydMHZqcDjCk+TWw9vjK75ViK+Waycxku ymQ1UI6YcgS7usFe4luisR7SVlwpZjAmJPNI+JKRlVPZid4UJh4yJo0WO3rWLxaKVK8XEHUPtLT5 0V+8gXQRCVa7Ev2IkcAoGiYIy+sCcpyTMjLvXzfQ5pHMQRQ8a900N79hwV1dkb7s3yypD/Cmz/DJ 4+EdCBe0/Y145HXMvlnsEQISuEjurDx+lQydqTYE1bDW6WPFIhPTDdwMiTF+a+RINvPq3NtAEfZr 7Ov3MTRmLnaBQZbw7vRGEFxGK1e16srLqs+fnEPhGj1AtbP9k2FPJNEnrGDDMdmZNn87LIQNF5nh OjGPEnThaJaVzBc/SC+2Z0WHAYE8AEuVkUlw1qy6y03uIC04m49r2/kQz8P4AdpmPxh2mfhl7WT3 XborkHJ+mC+C8InOtHfBCZw69Kv5j/B9zwZvnaLrqiFufuLdn1tBhYYifo+HS8RRZR3SnhwQE3Hg E9vJnkpaqb0gsyJlqltDO4mRybEbf5SVf2hB4mPJY8sqlsF25KQbm+8oneA7xqy004i8nubGCtdC CyZwXoFXS6fURGW293ZavDxdGkMfczK5D8+0lsvuNKXC4aZkj75FlwGWOEqTDvpoLJryEzZipt1L bJHA+e//fD3g4GKbMoVnNcUE7600RPPhMc6lCUEvZp/Fg2Fst4As2cgarlxo+ZxWw+9Nz6ybXtAV xs0jD3djDBEQqtXaAuo7xRZ6duza30/5pLI+vjBsD35ZZQxOzDLD9mBNchcSOBbQPHRXvBua203s wWaeX9p6nEjJreHUKw/LElFffp6YTBOy6PElASoIL/liIpp4y1LeO3dekk/fjp334+DTVQL1s9jF 5pNEoZgEzh1ZrL03cPBdFWmeURVRst77tsnoxXVA+ibAjdknUcJRrDCwBpOQopsakzx8olz2SGB/ 07rT+hhxaM2IiGz4bWB20nd4E3Hw1DLt3DlFhlGxquSH/69/jjOYbVc0mx60/pxZN5bHwtpJIQZD 9ZjV8k+rZOa3dCZE1Nk2yh60Xzd0Esz1S5o3bX7XEWqar2kq1bVE35A/vk2nRUaUEImmnaoQFXAC a+Ozuo00ToEanDlEDxb63HrMFb2Ezo1sDfAqVzEWr2zYqPRjWyD6Z+G+GnioXQYqR4BdBcFDngXW Fic1GYBlt2teLo/bZCoI531+sA4efnqrwVdIXOBXTW3ru0HqgkL8UK3uDIb4mnpeQwTD9UtDePhI XoGGRSlNwS+YaOpIVAcS6H68urvem/iUImmMuidHrobgcEsgllMPhyoCZ7hyHD45cfLRvV7kJmwq qu3PIkk4qehmnsjJ8j7/4mHnCueNPWHggYYotJVu2z7z0akIQR/zJ/RlInJSiH2kNiLuDgQSSOlP gXjn4UoRAj/zfsfoxAl/hUSTAvyQ7buux+9E1KWLr3YZFfDpaiGr2HUv9qt46FpkOe0VUmnInehA S5h3N2ya50W+N04TjWIJup8qU7h2OWLgRsfHbgN8D9GvW14BUQIFHPDcHFeIZYyPZtwS4DsNagoR z/VzFS8wXCmBO1I3EgP11rNF/dLeOkbs66CnKoUc8HVy5LI5UeYZuQfgmDUvYYCM4+T9jTfrOafv /mHjPGE1BT5VA6dYYzeuqNom6g4Mh4JKYaufR1yO64Wibgg8Ax+aLW9C+KSLrOwM+5YQnSG177Wh xfhMeiUHhGIHUKwvKz0NbF9qLQGILChM9It1OOEZxr8/sHiztjI3Vn0hTLYDXF0716YG8SjOp/ha J3hP74y2hIkcYML1kgfx9n5P8iiS/9XX1WH/cOjqs3Thzc0ZB/2fAtDdSMcSIDOQMr2mfUZ+HvdL 3BHvdk+25zgsGs7nVmc9+M7ntc33p0KZOEZt2t+olkAPl141ytqG1+iYPqlF9ARHfJoq6ftOywoI F1lpBn/GRkM9NB1gYsuVfJpqaqkWWLukZ+FNcmwlbAouwNcM49ceZZG1nKwgRmVkncNtzrW6aYnv mWgAkWDr7NJWaI96QTzTBQIVUtCFTvuSRhJgaqs5Y7pw64WqQ/CMMcOCdR/leENWCu8SfF75DZZh zNXZxZNmDyd/yqZaKKDhoUgsd0XDwLqUjqoX0pthx7JOWOQwMIU2TeIl2xs/gaBopSRwMv9JRJkx 5Pb1OlKUUygNJQO0s0ksiT0DKDv8CeSV4TUf2OZiCANog8d1ezoFaYaseUqdClOeZSIwUBZggkIc v7LVWlagO6pvmsd3qYvK1NJLdCkLFWs08ziLdNvea5OlaCpdcWpYVM8SOzhxvTnNsq5kcMDuiYul RSTSs9kuCrh5IvR99XJs7z8Sb7FaVKdGoQvOHjqXyWdz78uYYFY9v8epnsRqtc8bSsD0QFBcy73G xS5vhTn/hzcfVgLlcsMMhrdOsu+koQKlVtAW8cxBWe0IFQ5fRiIXS/p1hHpcl4ReDiZJfcJhB6z9 YA/hOyuTrEc9vYsY3i5s6yfhjLtn0P6FyBsaacR5251fT7VzszycoIRwkC/xX+5mqOFxq9+22FQu iR7s3UxyuSX52CzWgMejPGafZbqp9zn3oMbX8Hq+Q+KVsEHEutxYhYVSw0SlcZv9VEBmDohaFEkc 8FrrWkSWvQMQeeWGJc4a+qFTqjB9altnIPJMBdYTtCZmBQiK+lQMiV6jy4Il6i/bVR0Dopbu05j3 04wHGs2Pboa5lCtJ7399Wz+0Ymsln+9ItQX38P/466T5nDMrg153mnxxC13med5oFw9nBFTEnv7o Hkr9rtVDk4TPRrqC4s8tRNW3YT06aIiH+LrTMHU4JQNx1+t/o3f56QTK7QHCBVgRqr7lukCnWO5C LfRk9h869iNgk2RSvGpcvnjnMEaCqLJ+Dgk2HA5z9OjhQ85RciriZeuNvNR6qdzVF276v5HEPAVe cabvijc3TW1vdUs40VR1tYYI/alt9O/Jr+hLpHWJ/WWdKiM14Ttg4rGUo2gG8ezaFR6ZlUPO8NFe EcBDopvqseb7456LLYtszo1toVniccdt+vO7Ij30u+3h2SKWX31k2GuEypgdEBe6rhsJFY4ooksj RZY7/Ss2Md/gOVjcVW3Z7Iq6sYKT6Kzh5bSj3kapXmsn2neEh7SgD8l+jThDp1n0pExjy8/KVVlr duZZIvKUNRBltjrM4lbUOfshun/l7SULacjFE2E2D8uZZ+NyLseeSpvHao01fmspnDIeOv1v2Jim S1ud1cpzRY/jBAMni855+tl4l0JyMZ0lPgHE6ETLyOABQPfHqaADVijRKmWSFV+D5N098MKHuXKr R8ibK4S/ZMI0DkslwXL8eLURFGHB/4jICIsSNKjSCqf7kCv6nMPGBN5bVoudhhukKDDZQGEXB+sA Y6bpMvQAAALJ0uJSDNfH8ThLh489aiaECGrkI8LloCXusgXGaEMDk8uyM5TPwwOlN38QFbraXtCw cqd3Ysvq0LDhQC26pl52ECXAn7xsBBDVeb0D/h2e/6bzH9Re+b356emyarLFfvvXraUrnBXRQdXM Yt3/Nx3M4q6smjKN0FBnGSy05r+KeanOVpSH96Wxqyd802cKQPQezMe25a4gSLCKsJYHDU5t9joR TNv+JGn/vP9ttxhvwL0XjVuHRUQ3b8RY5noJ5z+/egAQ1urdqvcy/3qrfjzGPyJwotx6PaS0UENB FqESmo02/OzNdgUUIhua4+/24njlqfamdxjZNM8+zdP715DxaUwH73CIbfpmQ9jF9mOXQXPlmB8O FLYUyPhcTZOTwcJFEX9HKJrdXZlBYwPNOtoQ28p+0F3Qo5k1/K+KBdYUuuuPssyOK2v/nfXlb08+ un+eIwQNUdv+LZPcR80oqSdv1f9yu1BTLZeBgNZnBqme6i5cONKEtrDHEtq3Y014rce7UGB3LOWJ WCxNMbgBF/F4huPfma1BYVHPAgiqMSbBkq15NtnFKGehxIE96O70vvvRCU0fQ5Ip8QSAR2GsMf+O KUsfRF62Ms2HIJNbr5CBcO9N8XAXH+KKzMhXTpHB+fyqk5AmINYaNmRW4T0nB6C6P1HVawONPHzb V44BKNOGYyN5UaQ4UmW1cwJkCZhccDMoHmrxeda6j912jDao0C7kS2UWw54gUPYTjYsam/GxxhgL zhMe6V3892+9ctwdiVBmZIoLIV6v4So2+ZgNoZ/s17DBVdvoDP3TrgZ7JZu6KEse/Pg5nTPZ/yoE 4ZSGNAF6WbGyUFxnL0Sdb93wdmxOgKObClCcOfHU52bni0XY6YFWX7jP6LZd//8ZxyKcfB/bjnKD 4xu+/G/7XQf1qkxRU3Ar9JnMH6Co9bYAYRkRBmhCh8RkAHQ+Z/Y2GlWXqE4bwPSXrS0zaIW3bsd4 VeNFzsz9rm8E+ta5HYfMHgVytYIwVIfRu1y4I2UQmLaBjxPOqnFqEszml2VooUDTw0skKH1ZUBl5 dJ0wMyPV+4+3Nn8XADKFT2N5gjc3dWXIA/hAQB0xWuB5+o2YW3ZQuX/sIxDgV3CJTMJQS2CAa2Sv FYlO0oPc1A7wUcwP9phn1b0Q7LdYYG0LwcMeWHvtnLtC+iV+5OaErUoMWFxESTGeFrwK47wVz3Yd e1DPcqciTN8l5OHdUIWSCS/11be5qa9yoCSMnFlFeO4CreSRPYHmoWpBxyLPwFsn121clgSIR4Vl 0AJVSGzUe/CHOHQqPrAnzbg7wAPo9CToJqk9YEJiP7tuRqpOBgoBN/pyfMxLHFt+qYUTpyHlsHPn JxMfbwJX46scEhYlSkKJWesrSDfcjYkPSWmeJBqkfrgGgGUWXGGacx6GdmduT7W4nXW3c+Tdosx/ x9zJwI8/mA+Z/BhBskAAFz+0UbUIxlGcGPhBByiaPgKJpGhIkfCgvnFQxI1UmhelNCzlqlw+lBWp hkB+24zdsTk7+TYx9ZWFXfXSR+DjdkRCr60MW5VlFj9xsAYANzNLYQ2HF8pqY31KuPXcd11nuZd3 nZW7/55xulXdPJReLs/4uEO8I4SAr7mVCk2/Jx+5TdDwOT0Bbnv3XVwuDbvpPLVPdWs+11vslRpf O6YdUPLEKRSI8Ze4iZ1x1ZxCCF+0XtGq9v2GIl1ERlGMIu+s6VmNjlsq+0dMNYpjjBHXtzUcHJrk kWL0PipOf1Mitz5O/mD8VostsDRBhV6rTYTC6ITkXB9TajRJABkgqQWyIcvTJqilcj6Z25ZojBki GVn2l0dUOfO682Q3Ap+yYBpKZq6j4qyNlfsx5YLWsBFPFKs3BZss5/gcXOpagftJ05uIGS6QuU/G 5nkM322OjejZ22s3MgvhzD/EacffBKUPPhKR8cBMV+qdHAqe2KZaA610hYrNKrAVBicj8Xw6wA96 sZvtO3xbYauaycZBaxXWiJbg/Eu2NtzCIE7L0TlPM77RRDie4ZpgazU153JbkUdef1lst56ZopVm qetxDe85DclZSmeGJxlWfsH2XlQj65YMtRQV42QUZEcEVddtMgC1B8P+7wtCb0/X+sTA4aSzgQDc V85zCIrsq5CRTRAQfEdiW1K8VBoTZj7R4VypBT1LHoqlxFhMsDraarNcADRz158OG+EyQWqEBofV qepSQ8OP3AEBi9Yj7CtSnrsD/ilpEqqN+C8H7RIh6sYmf/WlvQXu3tWGfFFYw5vKhV6piJgVt2d1 P/aWXw38rkx0oQJaH/NA4RkNCErV8MR7fUlWPJrcE26ucu+9aXh5+2e1iC5GHROFF4NNuRh2BT1h 8xFXnSAH37xqqgv5Q9QIdcj2RwAAn7IsPLlLL4yXbf2QHVeTOcA6SUp52/GuIJq06BTxj+zbO748 fY/mFAb61QLD1xEhMJo1CvWXXUAYhVMmxzLOUwNJ1Ckg/+5I3ZF8PMlJUaQP9q7fEUKGsTYwDwD6 LHtZsfltoRrs0P0AOcxnoBNUWNj1xrwU/b8Z1ASIvIcNvSasBxlJ1EF3q59+5DfKFxV0PgRLxm9Q ZoLnIrVz5gmKw4qJTdD/rxc/+vLIe2XNyHLfGuOToC9JduugQlop6+NhPph9m75wF4TMaqM6P413 2UnXZ5EX3bZWUWHAN1fy7KHr+JYsPqnNu+ViQeB3m3fu3wjpAzvH8S8srJR7f3p6m7LADOjhKgRR 3w5ClyN/b9W0zLYS1QNmt40APFiMlD0PIRnUVU1/79ncaC8QZsD4L8EnhRbgivvorVWBeV+QYDVo LLvBmsxIljcbu3ILYWVPwF4JSXsXpaID+1FWa3l6K+dp+/RydxqNhmoyrGFpG/eaUK5ck1aegX5s bRkf9tDGGo7KVCLbfceYvK8xRjxR3j/icqyUwUZ19Y+JNplqiEUgnVUAwanEKNlEPOuawss9YLgR +ZDbHH2oesKrfYINmB0rVojeowOU58YlfhFDTDxeljp7faUnawCLgCUFCisItZbFVG1pn5aZsmWc y3uZ5lG4t1FUTYaxpFxhvLpa5H7gbShPfsSu/P2j2Drs3mbTOGQoV0f2arBFih/9k8jlJTk61k/0 9k5/EI3rbKxDqIqqEQMS3sPX3VIZ1+N938pzmDZ9EXY+454aAAAjLSJdBo7z+Z0T7KRUdJmLPOXC IHTFe7mkQjQdapQF5qf9me7vKdwUMNo5NQqfowHf3ruE71izqSmRgrXQrpzGEIjD4nyITkvg8/5c VIfv/X8Rj7cYjTow34HjFQyXmYIHWo4LolRcDwaIQuALMhdkDxJuBEYHqY8qGIOjtKySX+oxjZSx nsDL6CX9gBub8Nh5QmJx0TngnKF6CUIT+l7JsL4hXR98oDuVAxmh4KZmQ8n6BSLSBI0MhKuctJtS Jr5UHyFfN2H4CkmtAKkRTbiCiTbwjSXAncYgak2JJPK+yBvW0ZEtgvuoW0TjLTLamwEMae5Qs4I4 3N6kIHXp8GovT2udrZTmDeEWQewuQQubBZhkdOd7ds7tDUG+JpGkUBkAIGrJsZrTKem2Imnmr5d0 RRbGbefqI2FQMSupwV20S5OVnf5eXNU4voBQ0h4uFlyW9bymC+x1HqADiR23zqLPsZSwbUkyuqFE 1sFXV+QUZtFyni63PBczHb9vLfJa7XOLYrjj88x7e1nhEKI5Mqfkiar9EwGg+RnFOmT+UIXVylgw eF11hqSW+mMsHPwZfAVL5j7twZgvpZwIeDwYXNP8YpLJj4aTl6yXA2mvNPrV+wv7B2BZZqLsH2iL n3NBhN1+P6NOx1juFnVfjfPDLvjzAjmrG7+i/dDbZw980SMpqOFWLRI3o+q02YgNvVMU2GMKbgbo bO4uy5pJf8QLimHTgZ99FUybXdGv58hiJMAsmmtAHI8W8kfsgk/qtqLun/tzkbIxqyvWXLpuZAUf POGdzk5boBRHky7KEcjm4/q3mN7F7phCG8rJlS29AlyWMVtBx+cLslrw+mL1VCYd9sqsS59+Zp0h zUKXGEhrWio+VoDhXvtdWPg0pk4+aExnqv6BBEgYSlQ2/axzStl5nak/44UQA93blcbrO+Y10QxB Tlgr2ZryGF9o9N+holChRxeddn44e4tGsrdLvualy8qQpsd1c1ELKlQaD3cNDX79TYRL+nNh3cpq imVKhuKGlz5IaxU3qbdWVCSYXpUF0bY30iQY9UCMSZJqhYKYJTMR1YUqFo0wQJ6Br1s6ha333MaK tuwWT3W4K28IAd6ZUxxJWCC4LZswO/G8CPeNPp4MXdNAUGPz7D2K9ZjfTKMmcuyX+xCFKogSXd+4 jM9FkIZzW0w5HCY78dmkBGcjrPQX3gfyji6NF42K4M2H8No0n8oMIOa/J+kYawn4wgoDxO5DntmP bhfOcfEyt9ClE1keeRKOuhly14SqymHr2NbHI0TNNPEVskMq8Adtt6WMlatZsht47/w05L9g0u1e BeasCkgNVjHiHU2jTEFQzUhmJQQa3TpH53SJP4lV3SXB4LoLirOctC7ZXdtlh3jHvFs7+rSZR0kq J65PltzewdbPhg1sZvamRmVlrcweGzyNXljZeq9qb6cvG7h+mQqT7m74Jx/rDLF6fJubSc5qEESR 3tw3cC+CjqGhlcrVmUGlIChELyfVg3lgQptGTfPICQFrIw2QPqpeoP9XPxttD+ZSH7w8Nx07zi1Z +eJaG4vFl/fMnidlf6c5MAr4+JxZmLTp5bufIMyxUTqMgSdYKGX0zXiy9ZwPDhEZ1H6tFVGBI2Ld OskGWjeLaZQYsS8fNQizcmtn4PsnkNTBXSnOChDVAF2vXi54K2YbU9c2qafRXy+JbJ0z65HItZnp S9V/6uqnQKNrZpUrw+ZyhBQ3xH7rHFTaw60czVrocoitSq7xIXEXdK7Gjyde1In8koD3QcpseLM8 n9FBe0mOlZ03+trkzfF/lon/50Ysx2+bZMKsOKlt/CoG6JGbOWRy8VyI/zk2B2aApIJg+cjrdLej UInIhUGx3KXGCAzeTaIcDPxW0m1FfrJ/Mw/GHDdXwOa8BnvUmo5jxgwB+/OC6C2fwWb8gjKZeNbm ow9PTXN3mvS055FKkA54dRlDNBKtYnFmz0pOYrwO/pEPcKvSxlP+8uXuVasW+tRE9lunawlLUiWd E2oxyT2VZMi9C9WJQ4fv1CJ/6dJAqew14AZvF0mLHItmVUyNdnqCl8HuNVvmasqETHhxod8To86K UsQkXDRkteNiGLrP6pU5WaIglX7ZTjH7QNTWiBPL96YmU33inIiDTChWuKxKDD1Se5ZFEfMItQSr 10Ye7ULcl/cqQZ/W84ILaojx0enxBGA4AZNheA6QPMPKR0fFhZjKaDsik+GDJkvNwp/xcHnHoBoO 5aZCWnk/Qs4LSB7hOaBdJoegyxrJbVQYfUWLKdoXAMN1FNFWrB+6A4xYevW6amrVLaqsDxemfTFF b4WHeWYGStZoijyVFx3C8sYm+5PyybJHkxVXOdph8vL3FtV1b6gDtWo+A7DWqZWiCl+nxiJAEQmW jEk3ahnKjPEpB7w4vYkjS7deUCl9yc1mge5uB6H+4+JAXUmhkdPb5W84EqigrFFgwT08lh1RyygA hRRI85v8iRGRwMFanNVWnhuCwCRsHpX42oHLd/ozX9dHX9W4Dt7/kXRkPKKmnJJnAfSBJBvtVIBN 5sUEp44oR7gTLZgNaadIjvQ+OSA8iY4yrS12Rse7xrjIkX+IDHEe0r8Tgg2QNelFzIlis1SVg2Ag 3fbPvp7AOdSwgNN1XPmoiHZEAPwRY+Z+d2HsUL92Pu5Hod3atT67vZ7siP5Ab8MoK2Y3FlseJIP6 HnZThfFS5XeZW/5I1XPMJtJ9p795NbMpOj4l3AIuC88H5nNRwGPmknbF4ksg8/XxAvEXavDVC7zg 8rbHS6Gb0rsUVEvF5xl3xJlMNd8aiFbP/QMX5EjxeQ3F7JVEAZF4EMhLKOOpZNYU6uoV4pd15BU7 63wquRSb33DwMGHN5aSeQdLCUCxT029Y7NMhR+J+EBPfdXGg6UN+Nxs9KQio10QfWtvQkTE3RycL NdHKzZZV3gYn3R6CE3rGK/XGAjO1YytwnWB5dVF/dRab2YKeSoZQHJqSxsg/Ty+jhNtI2cTyD2BA wx7cUcDniK/5caBStQWlSZ97nFDC71d7/rxnBTg6OalwGoGvm8WnObrhE2moHA23knJc5ARzZHci LYq0HjuBxMFCumT9yMZA1vNHEqzbBRAuPGS3Q9mgazRhIN/4oFRD4b1Mr8QlTwmTCQYInc98XpG4 v5AuSeLUNpTVXbsZDRbRcgNm3msYtX0HyWR3ZLOcNo/BwKCpJCCzLyXLC6AEuKupjaralO14BPj/ YHIq7ePRJny3+yHnwWAdM9ah7etnraala6+oXvwPwODK08GOSj3YIzquFYX1T74PoxBcjSqYrwDS oAYjOptF7gyjMSEO7Xl6DZ9CChLHy21CkUwTzxavBc7lqXWhDMvGqN2cRkmr7OW3AK2TrFnVMD08 6DX0bIRhWrCVPkBzEIKivuXJ9CmtAfqzuCbr2L/kjjBnZbUHnHbZ4S1+40nfz6QcttGqn7RC5j90 H2Moop7xWST9B6ZyE6R5UVUQlOiSbmufmFmc9JyrMqII+UWrr+/kfW5/Dotfkxv16eEuBUz2ZHYu 5dHnEnBZcYt6b40/HG7W+EWdMXLhMuWNSXgSlOWewuVQnaC81EgRyiA5H+Cs+IKae8EeG8EFFg0O Kd699GIeaOLr1ZZcwX0YkU3b8WQqpikeOhWb4Dh4GAVjGwhs2Mx2ppKbPQeKEk+CEzJhex6lxd4A abl+T0recWkHZOrEA7mXXXPwcZ/gfT9IQywR/zrq+6em+Ds9amnRrw1YHrpmkoQvnNTXHd9b1cpP eszI4CDinGva7hqVaONEHQ+U3Xud3Yd5XkIAaAzIUPgzj4FAnT8uOW299ia8+o9oZedVNLYx7UAG Pn3em4tncDuLfFsXXmEsPKpDTtWsE7l4MhLESzqhvuJCyb3LEISqpPqwAOcWeHkuZ+VkLGISsE7G vCaIjfNhtCRN7fg9Q//IGJ5foTuUgJXLevKBt+MzL8knISSshad9NygyWhH0wF5VCZG0IK/0SFR+ IGT7vDremoDviP6r39v23w8nRFINfGJIMUS2BTc8v9tceifMP8pX2xPmhKnRf4Rv+s+RZsAnwx8F ngvIpHg/3n4ZXu6AcSAHhMPuTQEDHPKXIyRDOqHowrg5KF365PWnVsLcjfUNjw30ovENHYLDQxMu 6CTwzgXR1tDOaZN0CztNTaSOUr0IgsNL981NNfmjlii/IuHw5DJsY7dXJ2AuPSmr5ws+MD8SCMCt BDsn8W6LDW2D3KsDEqBXPKhSkT6d0CAaxaQPjZHwfrOzu/hAYdv1g5HUJVQAY6mm2/IxfIZIuZig 1xIQDdTOjFOy6PFfOuERmUHm3VjRIEx/Ke47bjQFVz6/OxFx3FQujG+/WlqGO2k9lJX/QIC64BUW T8Ql9vo9TIsAH5vOyWsujgu6bzjFe4Rh8EnonnyIw0re/FkH4/JIGQgamQSgTaBzgkW3SZ+CUezn i2x7Voj4xi4HGH3IQmmnflgsaX5Wn3sduBTXiR9eitnTO8S1Vcvp+km55ZneUBHXzAVVUVhiDpHx CNq4SFJPDPn5fQ2evnwcpiohELyWCo/EM+nfnAu1psXG3P+8ajnjjKjZTVSnC/EkTvIs0LgGdNkr NCJo10857vaCuNResQvR/ZpOMjFduMpGPKjHLANBKzR8k7rJoFLRIn//mgnRWac7SpK1E/LHDZ8y mbTcCj0px/jNllQboiH6ChIhcFFub3DMRxNH3P3e/fRY9AwfAhNrF24PX1GMZpnaDHZcNjubEw64 FjKhP5TKVGI18Q3l14IxYJff8S0iSAuOy+w0xfDQ2Ce0dJ4EwnM7WhArv8ViNRPasRmLFSJTGKZE wVNMEikaS0kS5RSVsUmIwDlkJ4zSQYEQpGaaoLkIDl/+gHyqc48fbtjnZFBCsYo4dlO0qYf0Fv6/ RQ+7rHe0eX4bpk6RCIDvkPI6DkBwEpFER7J2BICUma+noloPGvY9esWzeTmEfT7ekGLzBXxm6rwE 9Gt0ch0NK4aU4G3FOPYnF6WpezzDTemvDWgYOLoA91Qbm+t/57BGfWTEo+dvbAJuOtaWJKYs4qy1 yIZ4XJLsWrX0CH7I1fav5FElINGaaKKZQVqvdZvOiFuIrdabA+eGNgfFCbR4KPaWApL9s1dnIyZ+ dsV1ATOAT95WGT+bUnfNoecT3Ie547xQ6/wyoR6QStQNOhzslByU48R4JabbvUbvefBLSqXx2qbW El8bYcs3ZX7MA8P/M6RAkEtO2IapYBDe/AWXro9X0ei6ZDVD9lcqWOmUtsyuN8IO/ltOhYsmmYkA sOlCXxnrzAgoz2xymMhviff9v93qoEupkbDBWOWIiHagI/r2kC87h7ZDIj98YsuWRc/Ul/TnozkD 8DUHRF8ypVAFcfXiCG8OQs0UnwyY95RfvZI7/SnR7VB0/keE1GEMp7TUZTfini+0alNXBCvPYdKo kqQdjDmEYaIy4seQkHtxJtymgLaxkoGffE2TxIsypROmU0u/uxfXba7WG9wbw5YbDD6YoL2Ty1NZ qLerQlAn5f/sYKzLC7Iq0oTjmGAQyVBnuxKslZpGbWWWnCG2IMfzrVY4h/tK79d/1TgAirKfiODY b0ElqR75mqOKLjJTwf/RGaRTGCG9VPcGBx75GCJzKjYmkNkFqThbMDQngZicMZ2uNqIRTM3hHg+O JJufotmTKXiCKt/Fl4xLYptBJ83FZKtWT2IwgHsdi47JvDSGqzzpDdFAhZkvLKS6RFnDk91KDT5F 7n1n1HQySkeCitrrvZ72lKl1h7XRfd+xlnib0FqzW89F6orsxS2aOQmn0uicc7JxOHSBpUh2xa5S gUAlyts8YUC677RCa1O5a662ddu7u3wo3dB/KHaDf+lxH+GCNoT2KSw+OpxWKyHhdPfj2ek7PcuH PyviZeIZEmwsjW6IRLGbfwR0rq9qZLA0OGzOqwqlrryolcHalkidJNsilK4wnjJPdrvDRiGhFKiF irtSuciMEHJ4cX11k1HmrZBzVw0AL8oYlYcmQBM2Xdwd1dh7FoeaG6QOE9ccOl7MI/1+1/pv5rTJ M4mY5o0xatuadh+sZXbacmqmunYIhRMOTNUPNpYoOOYppFNg3JlCnLISFkjh+YUp6x+qx8cnX2Sy RQvBdLgx+PntpM1yzrFOlWJZDUypt9408veYRUQqQhFAlNMBh4MuaRBxZ2CAsVGP39zjdT6rSHUY QInKDDoqzpklGs4Yt58rtjFvm/laPqRK7lQ6LjEdn962tnqi9T02dABoAWMFSJMabmrrMR9h6JdZ baIsf+0imxsDjemtza7+HXj212gHiq3b3jpmab0PxVxmBZVFkh+/jReDmibYdUXEfqUFUHX0W9H8 XVG97G9+KarCjH6JYo3OsikFNjXTezkUd29Bee1+GzdHhysKMgl1AiYHrY8DiNJno4+DbyhWdOXR zjCI7ivRVnTh13UXlurVYSnIriuIax+b8/ZI+oYl3DW/Ma/WL1GmuJxY4nlqX2F+jjRQfBKhFhRD LR5tDvSw+tyd83yDsAY2ZsvquocBFLZQTUhlkr6xlPl4N4uf0+lh8AUYg/ESKt4o4eapnppm+X1O wd+R5kTc0pX6j1z1HIyTlo1ybkfRsP7GN4nieE4C91QWevV7HOwr/ETtU8UqC8yffOXVQwKxrKBg 6u56mCVn9yFcMdZmEyKDr7TCEGwp614k1dO440ochqL3gqQJXWfEPL0voXMNTRKMCklrUJ9jnp2Y ZDErOW8XNlfB8BCEYXVyBeoYy63ijBiAfU6TVUKZICiA9qMdHhI+QGHYqcKE1A7OQAwjIXIw57Jv dTeZ0PyDS5lA+EJZWfcY0g/2LzRecPx7mwOH9urXI1Y8RXBLIcsJMAadZYlTUjxQ1EoPXH1GLHWc wjRqcIN02qJTyHAM4251Qg/YiqMr9ELMuk3+fGdmMT6KV62n5kOZgdC23/B9I/jy+5WO9ex8Zp1q LnFeaR+Nto+KLGIFzwy/R4nLTcIsix2p8gcu+2CBZMtU1H9aq2SdQTDQ5xrjsyzik5xg6dHrQWOc gLMrLgGS6/iCcPi+xFWFzR+AgetWwXb7HLPUhv72tJrw6WA5ak/sRsl+W7Cf/fh8RWqK90K2vFVG w+gUNbdt22l8P/eRpspFvVk/T62TlF2lQqvzZWH6VH2XQiPIkYM2sHjwhLxJuREcDb3XbJyP8EQT htMQRcKRIZDQ4IfkO+v3cLOSKD1nFefv8hgK+l4GQLThZTKoU7w+/VJ1BUM4RTILRhGH7m1jDweC xSizhCCdXfRlSrhf/MITE1Xp/Jm/2hsENUygcpgpy6dfrPMcTLCCKgP4E62OrcAZcvAAulvYyxbL p+e3Sf0DWHHSS/DE8sc+VWnFVLlrKeDwpPFEfctBIRiWKK4hPm7qox/kt93jjqRIJFhSzhyt9K34 XgWf4cRfcYNBy99IKAFrGVQ8z7WFso4R6pG6CFMa5x/Um/v8VusiNkmjkCSZVBmokRSBTNY38Myc xofPLt3zYGgqSUscc6VmbwQ1T14shg2unSOHuJXzW2nvOVH0dITvf3bORWNq9r/EoRh5b6/TK2+G tQOKlMDs4tIn7pCaA2ogxwaPJVSbPDH1JwReK9H7gt8V3N/gLTBsSDpsODO8L+maAXa31vAoyH9U zoWaMjZ+3ZveFMG+xz5GsKAD28D9E9wp+P6t1qL2Tjja35x82vIeQUpbB1Zk0MN1Q3N/ALfLCRtb /kQ+w/BLSy2YFIh8Xfvy/pBNgp++ln9v11g8md8vVImg2/JfIbbWb33VCJz8vXQGeUemXXvzARCP Qt4yG1qBgQOhl+0TlPYXvQlG5jfpuAIYNHx6608uZWLrgp1UAR2Bs66YXos8AEPz/7tj1BumMxkT H5u3OYCygzHkPPdePdo3nHfyscjtPBA6dxSRT5U6uBS0EaE1368dV+gW7tMQ2ey6Sb6bL4MSWzor nre0TJWsPt0+ikkFcqNXluxCkOMtULT62cPK853gTDijLslfdtKTUnlc0MiilBnjpp2uFrU2czE+ Nfe+CrrZbeCddtiHL0DY1pFY9mNi3WYiUcBNAe2M4cyByyQ9CUPp3MMhgMvY+BrfwiVpryK2vXF7 c1MI9yx1RG6/guzAksCYcM0s0Iv2sd0EW2K14FZTeworXmR8eXqVu0cFvL6uuXLKXcLqe0qomkF7 6Y8KhbSoCDRIvWqN7n2aoH2k4Ubd7CmkL56eWZgYFa2xiGNP8A9kmY44L8eatu0ie72RzKaquuZL zY+uR0LZbe1/w51OCt9Cl/5Txm/wdn/YIN86pmQlTqCO/EEH8RypvQo3A8Ixqba1miS7rpciFMDK DR6YFZHYNpbo7SOVK/8y52agMprF66jy1WUdckyJoZUTixXkEnoSk2Mzrl4F3p1wI5uVuHUW6f49 OA5yFOOz1QYdSHQq8YKwJ5L0i8UxvO4lCm8zc2dCdq9xNuwuVkNcjmX8fIBXTtgaAfRJSCC/ghsx /Lieo5xIkuIC08hLuUbioqVDFMENrksg08E7XKS/tXRDFwMebm7n/Em3jcn/HcPjpXQ8NQb+hvKP NHwASQ++9tuXmXZMv6X0O/MTtxv+OF7+CAofVN8GRmkaA0SSBJpSBCzbdwD+BJ8yySpaJEfKeZ9J 9q1I7ogH1cvkELTeUkbscibB3Smf8A6dQEN+yOCSTVxLheWMt7PidhTI3t1sDFwCLQMNeVG1Vlh6 r5uOj/oV+zxQr+JB0lVbG7XKxY1b5lsQpENwyi3/nvrZRRCz/hMaJ6V9kmTodMcAhJajjEd3PYtm WJfGFTAqYllejHIhs08gREB2iRvdfMfHgktHeFdbGW1ED9PK76izDipzPvzknpP2kGW0G8rc2rFp agefETobzoNLqUQF91Zq2THSF7ImsG8o/C645+4Y1DCHbjZGjRG5h0/4jRfSQYPACnu8VhntAZTU yY/YJXoBMAOZ02+TJWpLnLL+1k7T8vG9fNqjGzAulp9HQLYYsod5IN58YDZ0jII1nMB/lvNbXP+Q RkO0EbihBCD38ydQfnln3VmGnKdxreBl3zoF+14fXzc0As6uZOpm30xc6j1BiLylUFYgMa8YIGQf POP/iuH4PkOs8ecwAS8v9/WOopwIssTwL2sfEv8iN53MRh0JFpX25fTJ2qIxIDLFgiTUuLdBT1Vg JD5BdB3ECktspvUtZtlEIuslnbzPRoL8kPeo++WeJ3ApII/tycsjVHHT1WczjousYIucnB8Mpp3J QMUMOAkmHqJx1y7VA9G/uuvZHowp79fOaD+MT5l/Oce6u8ZO8XNmzVrNxQCJPHYRPgKxZP/W0zZe tI0irBvQDKTaf/xohr+gIepcb29+5zQZeL2dQJTqPIRmutoyMVbajWPfptKOlyHEufdCRRG/teqy I+xFY//FrYmMZW82XeSeO/NVEfmFIKf1TEqCwLZhlQSXDv3m9SLW3HZ1eSdaO2gegud5sfIfEBsq jxGdI7Bggs8SPggTXEn8zDyTeU/W/F9+eVGFpRGiDeU5Qj5FFQwvvpKttyuIQJxNhok1pA9UfRw8 sk8KDM3EjzTBT1zzWMnLdW7PxqlfbxbFxEXZOBPCW24YMIeVQI+b/xczPJWk9giYb8eWNRF+pCKa BXtlBcKrQEzdSrw= `protect end_protected
architecture rtl of fifo is begin procedure_call_label : postponed wr_en(a, b); procedure_call_label : wr_en(a, b); process_label : process begin procedure_call_label : wr_en(a, b); end process; -- Violations below procedure_call_label : postponed wr_en(a, b); procedure_call_label : postponed wr_en(a, b); procedure_call_label : wr_en(a, b); procedure_call_label : wr_en(a, b); process_label : process begin procedure_call_label : wr_en(a, b); procedure_call_label : wr_en(a, b); end process; end architecture rtl;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity bit_cpx_cpy is port ( operation : in std_logic_vector(2 downto 0); enable : in std_logic := '1'; -- instruction(1 downto 0)="00" n_in : in std_logic; v_in : in std_logic; z_in : in std_logic; c_in : in std_logic; data_in : in std_logic_vector(7 downto 0); a_reg : in std_logic_vector(7 downto 0); x_reg : in std_logic_vector(7 downto 0); y_reg : in std_logic_vector(7 downto 0); n_out : out std_logic; v_out : out std_logic; z_out : out std_logic; c_out : out std_logic ); end bit_cpx_cpy; architecture gideon of bit_cpx_cpy is signal reg : std_logic_vector(7 downto 0) := (others => '0'); signal diff : std_logic_vector(8 downto 0) := (others => '0'); signal zero_cmp : std_logic; signal zero_ld : std_logic; signal zero_bit : std_logic; signal oper4 : std_logic_vector(3 downto 0); begin -- *** BIT *** *** STY LDY CPY CPX reg <= x_reg when operation(0)='1' else y_reg; diff <= ('1' & reg) - ('0' & data_in); zero_cmp <= '1' when diff(7 downto 0)=X"00" else '0'; zero_ld <= '1' when data_in=X"00" else '0'; zero_bit <= '1' when (data_in and a_reg)=X"00" else '0'; oper4 <= enable & operation; with oper4 select c_out <= diff(8) when "1110" | "1111", -- CPX / CPY c_in when others; with oper4 select z_out <= zero_cmp when "1110" | "1111", -- CPX / CPY zero_ld when "1101", zero_bit when "1001", z_in when others; with oper4 select n_out <= diff(7) when "1110" | "1111", -- CPX / CPY data_in(7) when "1101" | "1001", -- LDY / BIT n_in when others; with oper4 select v_out <= data_in(6) when "1001", -- BIT v_in when others; end gideon;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity bit_cpx_cpy is port ( operation : in std_logic_vector(2 downto 0); enable : in std_logic := '1'; -- instruction(1 downto 0)="00" n_in : in std_logic; v_in : in std_logic; z_in : in std_logic; c_in : in std_logic; data_in : in std_logic_vector(7 downto 0); a_reg : in std_logic_vector(7 downto 0); x_reg : in std_logic_vector(7 downto 0); y_reg : in std_logic_vector(7 downto 0); n_out : out std_logic; v_out : out std_logic; z_out : out std_logic; c_out : out std_logic ); end bit_cpx_cpy; architecture gideon of bit_cpx_cpy is signal reg : std_logic_vector(7 downto 0) := (others => '0'); signal diff : std_logic_vector(8 downto 0) := (others => '0'); signal zero_cmp : std_logic; signal zero_ld : std_logic; signal zero_bit : std_logic; signal oper4 : std_logic_vector(3 downto 0); begin -- *** BIT *** *** STY LDY CPY CPX reg <= x_reg when operation(0)='1' else y_reg; diff <= ('1' & reg) - ('0' & data_in); zero_cmp <= '1' when diff(7 downto 0)=X"00" else '0'; zero_ld <= '1' when data_in=X"00" else '0'; zero_bit <= '1' when (data_in and a_reg)=X"00" else '0'; oper4 <= enable & operation; with oper4 select c_out <= diff(8) when "1110" | "1111", -- CPX / CPY c_in when others; with oper4 select z_out <= zero_cmp when "1110" | "1111", -- CPX / CPY zero_ld when "1101", zero_bit when "1001", z_in when others; with oper4 select n_out <= diff(7) when "1110" | "1111", -- CPX / CPY data_in(7) when "1101" | "1001", -- LDY / BIT n_in when others; with oper4 select v_out <= data_in(6) when "1001", -- BIT v_in when others; end gideon;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity bit_cpx_cpy is port ( operation : in std_logic_vector(2 downto 0); enable : in std_logic := '1'; -- instruction(1 downto 0)="00" n_in : in std_logic; v_in : in std_logic; z_in : in std_logic; c_in : in std_logic; data_in : in std_logic_vector(7 downto 0); a_reg : in std_logic_vector(7 downto 0); x_reg : in std_logic_vector(7 downto 0); y_reg : in std_logic_vector(7 downto 0); n_out : out std_logic; v_out : out std_logic; z_out : out std_logic; c_out : out std_logic ); end bit_cpx_cpy; architecture gideon of bit_cpx_cpy is signal reg : std_logic_vector(7 downto 0) := (others => '0'); signal diff : std_logic_vector(8 downto 0) := (others => '0'); signal zero_cmp : std_logic; signal zero_ld : std_logic; signal zero_bit : std_logic; signal oper4 : std_logic_vector(3 downto 0); begin -- *** BIT *** *** STY LDY CPY CPX reg <= x_reg when operation(0)='1' else y_reg; diff <= ('1' & reg) - ('0' & data_in); zero_cmp <= '1' when diff(7 downto 0)=X"00" else '0'; zero_ld <= '1' when data_in=X"00" else '0'; zero_bit <= '1' when (data_in and a_reg)=X"00" else '0'; oper4 <= enable & operation; with oper4 select c_out <= diff(8) when "1110" | "1111", -- CPX / CPY c_in when others; with oper4 select z_out <= zero_cmp when "1110" | "1111", -- CPX / CPY zero_ld when "1101", zero_bit when "1001", z_in when others; with oper4 select n_out <= diff(7) when "1110" | "1111", -- CPX / CPY data_in(7) when "1101" | "1001", -- LDY / BIT n_in when others; with oper4 select v_out <= data_in(6) when "1001", -- BIT v_in when others; end gideon;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity bit_cpx_cpy is port ( operation : in std_logic_vector(2 downto 0); enable : in std_logic := '1'; -- instruction(1 downto 0)="00" n_in : in std_logic; v_in : in std_logic; z_in : in std_logic; c_in : in std_logic; data_in : in std_logic_vector(7 downto 0); a_reg : in std_logic_vector(7 downto 0); x_reg : in std_logic_vector(7 downto 0); y_reg : in std_logic_vector(7 downto 0); n_out : out std_logic; v_out : out std_logic; z_out : out std_logic; c_out : out std_logic ); end bit_cpx_cpy; architecture gideon of bit_cpx_cpy is signal reg : std_logic_vector(7 downto 0) := (others => '0'); signal diff : std_logic_vector(8 downto 0) := (others => '0'); signal zero_cmp : std_logic; signal zero_ld : std_logic; signal zero_bit : std_logic; signal oper4 : std_logic_vector(3 downto 0); begin -- *** BIT *** *** STY LDY CPY CPX reg <= x_reg when operation(0)='1' else y_reg; diff <= ('1' & reg) - ('0' & data_in); zero_cmp <= '1' when diff(7 downto 0)=X"00" else '0'; zero_ld <= '1' when data_in=X"00" else '0'; zero_bit <= '1' when (data_in and a_reg)=X"00" else '0'; oper4 <= enable & operation; with oper4 select c_out <= diff(8) when "1110" | "1111", -- CPX / CPY c_in when others; with oper4 select z_out <= zero_cmp when "1110" | "1111", -- CPX / CPY zero_ld when "1101", zero_bit when "1001", z_in when others; with oper4 select n_out <= diff(7) when "1110" | "1111", -- CPX / CPY data_in(7) when "1101" | "1001", -- LDY / BIT n_in when others; with oper4 select v_out <= data_in(6) when "1001", -- BIT v_in when others; end gideon;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity bit_cpx_cpy is port ( operation : in std_logic_vector(2 downto 0); enable : in std_logic := '1'; -- instruction(1 downto 0)="00" n_in : in std_logic; v_in : in std_logic; z_in : in std_logic; c_in : in std_logic; data_in : in std_logic_vector(7 downto 0); a_reg : in std_logic_vector(7 downto 0); x_reg : in std_logic_vector(7 downto 0); y_reg : in std_logic_vector(7 downto 0); n_out : out std_logic; v_out : out std_logic; z_out : out std_logic; c_out : out std_logic ); end bit_cpx_cpy; architecture gideon of bit_cpx_cpy is signal reg : std_logic_vector(7 downto 0) := (others => '0'); signal diff : std_logic_vector(8 downto 0) := (others => '0'); signal zero_cmp : std_logic; signal zero_ld : std_logic; signal zero_bit : std_logic; signal oper4 : std_logic_vector(3 downto 0); begin -- *** BIT *** *** STY LDY CPY CPX reg <= x_reg when operation(0)='1' else y_reg; diff <= ('1' & reg) - ('0' & data_in); zero_cmp <= '1' when diff(7 downto 0)=X"00" else '0'; zero_ld <= '1' when data_in=X"00" else '0'; zero_bit <= '1' when (data_in and a_reg)=X"00" else '0'; oper4 <= enable & operation; with oper4 select c_out <= diff(8) when "1110" | "1111", -- CPX / CPY c_in when others; with oper4 select z_out <= zero_cmp when "1110" | "1111", -- CPX / CPY zero_ld when "1101", zero_bit when "1001", z_in when others; with oper4 select n_out <= diff(7) when "1110" | "1111", -- CPX / CPY data_in(7) when "1101" | "1001", -- LDY / BIT n_in when others; with oper4 select v_out <= data_in(6) when "1001", -- BIT v_in when others; end gideon;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity A is port(x: in std_ulogic_vector(4 downto 0)); end entity; architecture test of A is begin end architecture; entity B is end entity; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; architecture test of B is function to_vector(signal d: unsigned(4 downto 0)) return std_ulogic_vector is begin return std_ulogic_vector(d); end function; signal s: unsigned(4 downto 0) := (others => '0'); begin test: entity work.A port map( x => to_vector(s) ); end architecture;
------------------------------------------------------------------------------- -- -- File: Transmit_Path.vhd -- Author: Gherman Tudor -- Original Project: USB Device IP on 7-series Xilinx FPGA -- Date: 2 May 2016 -- ------------------------------------------------------------------------------- -- (c) 2016 Copyright Digilent Incorporated -- All Rights Reserved -- -- This program is free software; distributed under the terms of BSD 3-clause -- license ("Revised BSD License", "New BSD License", or "Modified BSD License") -- -- Redistribution and use in source and binary forms, with or without modification, -- are permitted provided that the following conditions are met: -- -- 1. Redistributions of source code must retain the above copyright notice, this -- list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above copyright notice, -- this list of conditions and the following disclaimer in the documentation -- and/or other materials provided with the distribution. -- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names -- of its contributors may be used to endorse or promote products derived -- from this software without specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE -- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- -- -- Purpose: -- This module is responsible for buffering the data transfered through DMA, -- implementing the TX endpoints and sending the packet data on request from -- the protocol engine state machine request ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; Library UNISIM; use UNISIM.vcomponents.all; use ieee.numeric_std.all; use IEEE.std_logic_signed.all; entity Transmit_Path is generic ( C_S_AXI_DATA_WIDTH : integer := 3; MAX_NR_ENDP : integer := 1 ); PORT ( Axi_Resetn : IN STD_LOGIC; Axi_Clk : IN STD_LOGIC; Ulpi_Clk : in STD_LOGIC; u_Resetn : IN STD_LOGIC; u_PE_Endpt_Nr: in std_logic_vector(4 downto 0); a_Arb_Endpt_Nr : in std_logic_vector(4 downto 0); --!!!!! bits need to be synchronised Tx_Fifo_S_Aresetn : IN STD_LOGIC; a_Tx_Fifo_S_Aclk : IN STD_LOGIC; a_Tx_Fifo_S_Axis_Tvalid : IN STD_LOGIC; a_Tx_Fifo_S_Axis_Tready : OUT STD_LOGIC; a_Tx_Fifo_S_Axis_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); a_Tx_Fifo_S_Axis_Tlast : IN STD_LOGIC; a_Tx_Fifo_S_Axis_Tkeep : IN std_logic_vector(3 downto 0); a_Tx_Fifo_S_Axis_Tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); u_Send_Packet : in STD_LOGIC; u_Tx_Data_En : in STD_LOGIC; u_Tx_Data : out STD_LOGIC_VECTOR(7 downto 0); u_Send_Packet_Last : out STD_LOGIC; u_Endpt_Ready : out STD_LOGIC; latency_comp_in : in STD_LOGIC; latency_comp_out : out STD_LOGIC; tx_fifo_axis_overflow : OUT STD_LOGIC; tx_fifo_axis_underflow : OUT STD_LOGIC ); end Transmit_Path; architecture Behavioral of Transmit_Path is COMPONENT blk_mem_gen_1 PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); clkb : IN STD_LOGIC; enb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; COMPONENT TX_FIFO PORT ( s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC ); END COMPONENT; type a_BRAM_Base_AddrA_Array is array (MAX_NR_ENDP downto 0) of std_logic_vector(11 downto 0); constant a_BRAM_Base_AddrA : a_BRAM_Base_AddrA_Array := ("010000000000","000000000000"); constant u_BRAM_Base_AddrB : a_BRAM_Base_AddrA_Array := ("010000000000","000000000000"); type a_BRAM_Load_Array is array (MAX_NR_ENDP downto 0) of std_logic_vector(11 downto 0); signal a_BRAM_Load_Counter_Array : a_BRAM_Load_Array; type u_Cnt_Load_Bram_oData_Array is array (MAX_NR_ENDP downto 0) of std_logic_vector(11 downto 0); signal u_Cnt_Load_Bram_oData : u_Cnt_Load_Bram_oData_Array; type a_Cnt_Load_Bram_iPush_Array is array (MAX_NR_ENDP downto 0) of std_logic; signal a_Cnt_Load_Bram_iPush : a_Cnt_Load_Bram_iPush_Array; type a_Cnt_Load_Bram_iRdy_Array is array (MAX_NR_ENDP downto 0) of std_logic; signal a_Cnt_Load_Bram_iRdy : a_Cnt_Load_Bram_iRdy_Array; type u_Cnt_Load_Bram_oValid_Array is array (MAX_NR_ENDP downto 0) of std_logic; signal u_Cnt_Load_Bram_oValid : u_Cnt_Load_Bram_oValid_Array; type aReset_Handshake_Array is array (MAX_NR_ENDP downto 0) of std_logic; signal aReset_Handshake, aReset_Handshake_Loc : u_Cnt_Load_Bram_oValid_Array; signal u_Resetn_N : STD_LOGIC; signal a_BRAM_EnA : STD_LOGIC; signal a_BRAM_WeA : STD_LOGIC_VECTOR(0 DOWNTO 0); signal a_BRAM_AddrA, a_BRAM_AddrA_q : STD_LOGIC_VECTOR(11 DOWNTO 0); signal a_BRAM_Dina : STD_LOGIC_VECTOR(7 DOWNTO 0); signal u_BRAM_Enb, u_BRAM_Enb_Loc : STD_LOGIC; signal u_BRAM_AddrB : STD_LOGIC_VECTOR(11 DOWNTO 0); signal u_BRAM_DoutB, u_BRAM_DoutB_q : STD_LOGIC_VECTOR(7 DOWNTO 0); signal a_Tx_Fifo_M_Axis_Tvalid : STD_LOGIC; signal a_Tx_Fifo_M_Axis_Tready : STD_LOGIC; signal a_Tx_Fifo_M_Axis_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0); signal a_Tx_Fifo_M_Axis_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0); signal a_Tx_Fifo_M_Axis_Tlast : STD_LOGIC; signal a_Tx_Fifo_M_Load_Last : STD_LOGIC; --signal a_Tx_Fifo_M_Axis_Tuser : STD_LOGIC_VECTOR(3 DOWNTO 0); signal a_Byte_Index : integer range 0 to C_S_AXI_DATA_WIDTH; --signal a_Byte_Index_Rst : STD_LOGIC; signal a_Byte_Index_Inc : STD_LOGIC; signal a_Cnt_Load_Bram : STD_LOGIC_VECTOR(11 DOWNTO 0); signal a_Cnt_Load_Bram_Rst : STD_LOGIC; signal u_Cnt_Read_Bram : STD_LOGIC_VECTOR(11 DOWNTO 0); signal u_Cnt_Read_Bram_Rst : STD_LOGIC; signal a_DMA_Transfer_Start, a_DMA_Transfer_Start_Pulse, a_DMA_Transfer_Start_q : STD_LOGIC; signal a_Tx_Fifo_M_Axis_Tlast_q, a_Tx_Fifo_M_Axis_Tlast_NPulse, a_Tx_Fifo_M_Axis_Tlast_NPulse_q : STD_LOGIC; signal a_Tx_Fifo_S_Axis_Tlast_q, a_Tx_Fifo_S_Axis_Tlast_NPulse : STD_LOGIC; signal a_Load_BRAM_Start : STD_LOGIC; signal u_Send_Packet_Pulse, u_Send_Packet_PulseN, u_Send_Packet_q, u_Send_Packet_Pulse_q : STD_LOGIC; signal u_Tx_Data_En_q : STD_LOGIC; signal a_Arb_Endpt_Nr_Int, u_PE_Endpt_Nr_Int : integer range 0 to MAX_NR_ENDP; --attribute mark_debug : string; --attribute keep : string; --attribute mark_debug of a_Tx_Fifo_S_Axis_Tvalid : signal is "true"; --attribute keep of a_Tx_Fifo_S_Axis_Tvalid : signal is "true"; --attribute mark_debug of a_Tx_Fifo_S_Axis_Tdata : signal is "true"; --attribute keep of a_Tx_Fifo_S_Axis_Tdata : signal is "true"; --attribute mark_debug of a_Tx_Fifo_S_Axis_Tready : signal is "true"; --attribute keep of a_Tx_Fifo_S_Axis_Tready : signal is "true"; --attribute mark_debug of a_Tx_Fifo_S_Axis_Tlast : signal is "true"; --attribute keep of a_Tx_Fifo_S_Axis_Tlast : signal is "true"; --attribute mark_debug of a_Tx_Fifo_M_Axis_Tdata : signal is "true"; --attribute keep of a_Tx_Fifo_M_Axis_Tdata : signal is "true"; --attribute mark_debug of a_Tx_Fifo_M_Axis_Tvalid : signal is "true"; --attribute keep of a_Tx_Fifo_M_Axis_Tvalid : signal is "true"; --attribute mark_debug of a_Tx_Fifo_M_Axis_Tkeep : signal is "true"; --attribute keep of a_Tx_Fifo_M_Axis_Tkeep : signal is "true"; --attribute mark_debug of a_Tx_Fifo_M_Axis_Tlast : signal is "true"; --attribute keep of a_Tx_Fifo_M_Axis_Tlast : signal is "true"; --attribute mark_debug of a_Tx_Fifo_M_Axis_Tready : signal is "true"; --attribute keep of a_Tx_Fifo_M_Axis_Tready : signal is "true"; --attribute mark_debug of a_Byte_Index : signal is "true"; --attribute keep of a_Byte_Index : signal is "true"; --attribute mark_debug of a_BRAM_WeA : signal is "true"; --attribute keep of a_BRAM_WeA : signal is "true"; --attribute mark_debug of a_BRAM_AddrA_q : signal is "true"; --attribute keep of a_BRAM_AddrA_q : signal is "true"; --attribute mark_debug of a_BRAM_Dina : signal is "true"; --attribute keep of a_BRAM_Dina : signal is "true"; --attribute mark_debug of u_BRAM_Enb : signal is "true"; --attribute keep of u_BRAM_Enb : signal is "true"; --attribute mark_debug of u_BRAM_AddrB : signal is "true"; --attribute keep of u_BRAM_AddrB : signal is "true"; --attribute mark_debug of u_BRAM_DoutB : signal is "true"; --attribute keep of u_BRAM_DoutB : signal is "true"; --attribute mark_debug of u_BRAM_DoutB_q : signal is "true"; --attribute keep of u_BRAM_DoutB_q : signal is "true"; --attribute mark_debug of u_Send_Packet_Last : signal is "true"; --attribute keep of u_Send_Packet_Last : signal is "true"; --attribute mark_debug of u_Cnt_Read_Bram : signal is "true"; --attribute keep of u_Cnt_Read_Bram : signal is "true"; --attribute mark_debug of a_Tx_Fifo_M_Load_Last : signal is "true"; --attribute keep of a_Tx_Fifo_M_Load_Last : signal is "true"; --attribute mark_debug of a_Arb_Endpt_Nr_Int : signal is "true"; --attribute keep of a_Arb_Endpt_Nr_Int : signal is "true"; --attribute mark_debug of u_PE_Endpt_Nr_Int : signal is "true"; --attribute keep of u_PE_Endpt_Nr_Int : signal is "true"; --attribute mark_debug of a_Tx_Fifo_S_Axis_Tlast_NPulse : signal is "true"; --attribute keep of a_Tx_Fifo_S_Axis_Tlast_NPulse : signal is "true"; --attribute mark_debug of a_Cnt_Load_Bram : signal is "true"; --attribute keep of a_Cnt_Load_Bram : signal is "true"; --attribute mark_debug of u_Send_Packet_Pulse_q : signal is "true"; --attribute keep of u_Send_Packet_Pulse_q : signal is "true"; --attribute mark_debug of a_BRAM_Load_Counter_Array : signal is "true"; --attribute keep of a_BRAM_Load_Counter_Array : signal is "true"; --attribute mark_debug of u_Cnt_Load_Bram_oData : signal is "true"; --attribute keep of u_Cnt_Load_Bram_oData : signal is "true"; --attribute mark_debug of u_Cnt_Load_Bram_oValid : signal is "true"; --attribute keep of u_Cnt_Load_Bram_oValid : signal is "true"; --attribute mark_debug of a_Cnt_Load_Bram_iPush : signal is "true"; --attribute keep of a_Cnt_Load_Bram_iPush : signal is "true"; --attribute mark_debug of a_Cnt_Load_Bram_iRdy : signal is "true"; --attribute keep of a_Cnt_Load_Bram_iRdy : signal is "true"; --attribute mark_debug of aReset_Handshake : signal is "true"; --attribute keep of aReset_Handshake : signal is "true"; --attribute mark_debug of a_Tx_Fifo_M_Axis_Tlast_NPulse : signal is "true"; --attribute keep of a_Tx_Fifo_M_Axis_Tlast_NPulse : signal is "true"; --attribute mark_debug of u_Send_Packet_PulseN : signal is "true"; --attribute keep of u_Send_Packet_PulseN : signal is "true"; --attribute mark_debug of u_Send_Packet : signal is "true"; --attribute keep of u_Send_Packet : signal is "true"; begin u_Resetn_N <= not u_Resetn; a_Arb_Endpt_Nr_Int <= to_integer (unsigned (a_Arb_Endpt_Nr(4 downto 1))); u_PE_Endpt_Nr_Int <= to_integer (unsigned (u_PE_Endpt_Nr(4 downto 1))); a_BRAM_Dina <= a_Tx_Fifo_M_Axis_Tdata((a_Byte_Index *8 + 7) downto a_Byte_Index * 8); u_Endpt_Ready <= u_Cnt_Load_Bram_oValid(u_PE_Endpt_Nr_Int); TX_FIFO_INST: TX_FIFO PORT MAP ( s_aclk => a_Tx_Fifo_S_Aclk, s_aresetn => Tx_Fifo_S_Aresetn, s_axis_tvalid => a_Tx_Fifo_S_Axis_Tvalid, s_axis_tready => a_Tx_Fifo_S_Axis_Tready, s_axis_tdata => a_Tx_Fifo_S_Axis_Tdata, s_axis_tkeep => a_Tx_Fifo_S_Axis_Tkeep, s_axis_tlast => a_Tx_Fifo_S_Axis_Tlast, s_axis_tuser => a_Tx_Fifo_S_Axis_Tuser, m_axis_tvalid => a_Tx_Fifo_M_Axis_Tvalid, m_axis_tready => a_Tx_Fifo_M_Axis_Tready, m_axis_tdata => a_Tx_Fifo_M_Axis_Tdata, m_axis_tkeep => a_Tx_Fifo_M_Axis_Tkeep, m_axis_tlast => a_Tx_Fifo_M_Axis_Tlast, m_axis_tuser => open, axis_overflow => tx_fifo_axis_overflow, axis_underflow => tx_fifo_axis_underflow ); BRAM: blk_mem_gen_1 PORT MAP ( clka => Axi_Clk, ena => a_BRAM_EnA, wea => a_BRAM_WeA, addra => a_BRAM_AddrA_q, dina => a_BRAM_Dina, clkb => Ulpi_Clk, enb => u_BRAM_Enb, addrb => u_BRAM_AddrB, doutb => u_BRAM_DoutB ); u_BRAM_Enb <= u_BRAM_Enb_Loc or u_Send_Packet_Pulse_q; a_BRAM_EnA <= '1'; BYTE_INDEX_PROC: process(Axi_Clk) begin if (Axi_Clk 'event and Axi_Clk = '1') then if ((Axi_Resetn = '0') or (a_Tx_Fifo_M_Axis_Tlast_NPulse_q = '1')) then a_Byte_Index <= 0; elsif (a_Byte_Index_Inc = '1') then if (a_Byte_Index = (C_S_AXI_DATA_WIDTH)) then a_Byte_Index <= 0; else a_Byte_Index <= a_Byte_Index + 1; end if; end if; end if; end process; BRAM_WEA_PROC: process(Axi_Clk) begin if (Axi_Clk 'event and Axi_Clk = '1') then if (Axi_Resetn = '0') then a_BRAM_WeA <= "0"; else if ((a_Tx_Fifo_M_Axis_Tvalid = '1') and (a_Tx_Fifo_M_Axis_Tkeep(a_Byte_Index) = '1')and (a_Load_BRAM_Start = '1')) then a_BRAM_WeA <= "1"; else a_BRAM_WeA <= "0"; end if; end if; end if; end process; BRAM_READY_PROC: process(Axi_Clk) begin if (Axi_Clk 'event and Axi_Clk = '1') then if (Axi_Resetn = '0') then a_Tx_Fifo_M_Axis_Tready <= '0'; else if (a_Byte_Index = (C_S_AXI_DATA_WIDTH-1) ) then --if ((a_Byte_Index = (C_S_AXI_DATA_WIDTH-1)) or (a_Tx_Fifo_S_Axis_Tlast_NPulse = '1')) then a_Tx_Fifo_M_Axis_Tready <= '1'; else a_Tx_Fifo_M_Axis_Tready <= '0'; end if; end if; end if; end process; BYTE_INDEX_INC_PROC: process(Axi_Clk) begin if (Axi_Clk 'event and Axi_Clk = '1') then if (Axi_Resetn = '0') then a_Byte_Index_Inc <= '0'; else if ((a_Tx_Fifo_M_Axis_Tvalid = '1') and (a_Load_BRAM_Start = '1')) then a_Byte_Index_Inc <= '1'; else a_Byte_Index_Inc <= '0'; end if; end if; end if; end process; LOAD_BRAM_START_PROC: process(Axi_Clk) begin if (Axi_Clk 'event and Axi_Clk = '1') then if ((Axi_Resetn = '0') or (a_Tx_Fifo_M_Axis_Tlast_NPulse = '1')) then a_Load_BRAM_Start <= '0'; else if (a_Tx_Fifo_S_Axis_Tlast_NPulse = '1') then a_Load_BRAM_Start <= '1'; end if; end if; end if; end process; BRAM_ADDRESSA_PROC: process(Axi_Clk) begin if (Axi_Clk 'event and Axi_Clk = '1') then if (Axi_Resetn = '0') then a_BRAM_AddrA <= (others => '0'); a_BRAM_AddrA_q <= (others => '0'); else a_BRAM_AddrA_q <= a_BRAM_AddrA; if (a_DMA_Transfer_Start_Pulse = '1') then a_BRAM_AddrA <= a_BRAM_Base_AddrA(a_Arb_Endpt_Nr_Int); elsif ((a_Tx_Fifo_M_Axis_Tvalid = '1') and (a_Tx_Fifo_M_Axis_Tkeep(a_Byte_Index) = '1') and (a_Load_BRAM_Start = '1')) then a_BRAM_AddrA <= std_logic_vector( to_unsigned((to_integer(unsigned(a_BRAM_AddrA)) + 1),12) ); end if; end if; end if; end process; DMA_TRANSFER_START_PROC: process(Axi_Clk) begin if (Axi_Clk 'event and Axi_Clk = '1') then if (Axi_Resetn = '0' or a_Tx_Fifo_M_Axis_Tlast_q = '1') then a_DMA_Transfer_Start <= '0'; elsif (a_Tx_Fifo_S_Axis_Tvalid = '1') then a_DMA_Transfer_Start <= '1'; end if; end if; end process; DMA_TRANSFER_START_PULSE_PROC: process (Axi_Clk) begin if (Axi_Clk'event and Axi_Clk = '1') then if (Axi_Resetn = '0') then a_DMA_Transfer_Start_Pulse <= '0'; a_DMA_Transfer_Start_q <= '0'; else a_DMA_Transfer_Start_q <= a_DMA_Transfer_Start; a_DMA_Transfer_Start_Pulse <= a_DMA_Transfer_Start and (not a_DMA_Transfer_Start_q); end if; end if; end process; a_Tx_Fifo_M_Load_Last <= '1' when ((a_Tx_Fifo_M_Axis_Tlast = '1') and (a_Byte_Index = 3)) else '0'; M_LAST_NPULSE_PROC: process (Axi_Clk) begin if (Axi_Clk'event and Axi_Clk = '1') then if (Axi_Resetn = '0') then a_Tx_Fifo_M_Axis_Tlast_NPulse <= '0'; a_Tx_Fifo_M_Axis_Tlast_NPulse_q <= '0'; a_Tx_Fifo_M_Axis_Tlast_q <= '0'; a_Cnt_Load_Bram_Rst <= '0'; else a_Tx_Fifo_M_Axis_Tlast_q <= a_Tx_Fifo_M_Load_Last; a_Tx_Fifo_M_Axis_Tlast_NPulse <= a_Tx_Fifo_M_Load_Last and (not a_Tx_Fifo_M_Axis_Tlast_q); a_Cnt_Load_Bram_Rst <= a_Tx_Fifo_M_Axis_Tlast_NPulse_q; a_Tx_Fifo_M_Axis_Tlast_NPulse_q <= a_Tx_Fifo_M_Axis_Tlast_NPulse; end if; end if; end process; S_LAST_NPULSE_PROC: process (Axi_Clk) begin if (Axi_Clk'event and Axi_Clk = '1') then if (Axi_Resetn = '0') then a_Tx_Fifo_S_Axis_Tlast_NPulse <= '0'; a_Tx_Fifo_s_Axis_Tlast_q <= '0'; else a_Tx_Fifo_S_Axis_Tlast_q <= a_Tx_Fifo_S_Axis_Tlast; a_Tx_Fifo_S_Axis_Tlast_NPulse <= (not a_Tx_Fifo_S_Axis_Tlast) and a_Tx_Fifo_S_Axis_Tlast_q; end if; end if; end process; BRAM_LOAD_COUNTER_PROC: process (Axi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us begin if (Axi_Clk' event and Axi_Clk = '1') then if ((a_Cnt_Load_Bram_Rst = '1') or (Axi_Resetn = '0')) then a_Cnt_Load_Bram <= (others => '0'); elsif (a_BRAM_WeA = "1") then a_Cnt_Load_Bram <= a_Cnt_Load_Bram + '1'; end if; end if; end process; BRAM_LOAD_PROC: process (Axi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us begin if (Axi_Clk' event and Axi_Clk = '1') then if (Axi_Resetn = '0') then a_BRAM_Load_Counter_Array <= (others => (others => '0')); elsif (a_Tx_Fifo_M_Axis_Tlast_NPulse_q = '1') then a_BRAM_Load_Counter_Array(a_Arb_Endpt_Nr_Int) <= (a_Cnt_Load_Bram - '1'); end if; end if; end process; --------------------------------------------------------------------------------------------------- TDATA_PROC: process(u_Tx_Data_En, u_Tx_Data_En_q, u_BRAM_DoutB, u_BRAM_DoutB_q) begin if (u_Tx_Data_En = '0') then u_Tx_Data <= u_BRAM_DoutB_q; else u_Tx_Data <= u_BRAM_DoutB; end if; end process; REG_AXIS_TDATA_PROC: process(Ulpi_Clk) begin if (Ulpi_Clk 'event and Ulpi_Clk = '1') then if (u_Resetn = '0') then u_BRAM_DoutB_q <= (others => '0'); latency_comp_out <= '0'; else latency_comp_out <= latency_comp_in; if((u_BRAM_Enb = '1') or (u_Cnt_Read_Bram = u_Cnt_Load_Bram_oData(u_PE_Endpt_Nr_Int)) or (u_Send_Packet_Pulse_q = '1')) then u_BRAM_DoutB_q <= u_BRAM_DoutB; end if; end if; end if; end process; SEND_PACKET_PULSE_PROC: process (Ulpi_Clk) begin if (Ulpi_Clk'event and Ulpi_Clk = '1') then if (u_Resetn = '0') then u_Send_Packet_Pulse <= '0'; u_Send_Packet_PulseN <= '0'; u_Send_Packet_q <= '0'; u_Send_Packet_Pulse_q <= '0'; else u_Send_Packet_q <= u_Send_Packet; u_Send_Packet_Pulse <= u_Send_Packet and (not u_Send_Packet_q); u_Send_Packet_PulseN <= (not u_Send_Packet) and u_Send_Packet_q; u_Send_Packet_Pulse_q <= u_Send_Packet_Pulse; end if; end if; end process; DELAY_PROC: process (Ulpi_Clk) begin if (Ulpi_Clk'event and Ulpi_Clk = '1') then if (u_Resetn = '0') then u_Tx_Data_En_q <= '0'; else u_Tx_Data_En_q <= u_Tx_Data_En; end if; end if; end process; ENB_PROC: process (u_Send_Packet, u_Tx_Data_En, u_Tx_Data_En_q) begin --if (Axi_Clk'event and Axi_Clk = '1') then if (u_Send_Packet = '1') then if (u_Tx_Data_En = '1') then u_BRAM_Enb_Loc <= '1'; --elsif ((u_Tx_Data_En = '0') and (u_Tx_Data_En_q = '1')) then -- u_BRAM_Enb_Loc <= '1'; else u_BRAM_Enb_Loc <= '0'; end if; else u_BRAM_Enb_Loc <= '0'; end if; --end if; end process; BRAM_ADDRESSB_PROC: process(Ulpi_Clk) begin if (Ulpi_Clk 'event and Ulpi_Clk = '1') then if (u_Resetn = '0') then u_BRAM_AddrB <= (others => '0'); else if (u_Send_Packet_Pulse = '1') then u_BRAM_AddrB <= u_BRAM_Base_AddrB(u_PE_Endpt_Nr_Int); elsif ((u_Send_Packet = '1') and (u_BRAM_Enb = '1')) then u_BRAM_AddrB <= std_logic_vector( to_unsigned((to_integer(unsigned(u_BRAM_AddrB)) + 1),12) ); end if; end if; end if; end process; u_Cnt_Read_Bram_Rst <= u_Send_Packet_Pulse; BRAM_READ_COUNTER_PROC: process (Ulpi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us begin if (Ulpi_Clk' event and Ulpi_Clk = '1') then if ((u_Cnt_Read_Bram_Rst = '1') or (u_Resetn = '0')) then u_Cnt_Read_Bram <= (others => '0'); elsif (u_BRAM_Enb = '1') then u_Cnt_Read_Bram <= u_Cnt_Read_Bram + '1'; end if; end if; end process; LAST_PROC: process (Ulpi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us begin if (Ulpi_Clk' event and Ulpi_Clk = '1') then if (u_Resetn = '0') then u_Send_Packet_Last <= '0'; elsif((u_Send_Packet = '1') and (u_Tx_Data_En = '1')) then if ((u_Cnt_Load_Bram_oData(u_PE_Endpt_Nr_Int) - '1') = u_Cnt_Read_Bram) then-- std_logic_vector( to_unsigned((to_integer(unsigned(u_Cnt_Read_Bram)) - 3),12))) then u_Send_Packet_Last <= '1'; else u_Send_Packet_Last <= '0'; end if; elsif ((u_Send_Packet_Pulse = '1') and (u_Cnt_Load_Bram_oData(u_PE_Endpt_Nr_Int) = "0000000000000001")) then u_Send_Packet_Last <= '1'; else u_Send_Packet_Last <= '0'; end if; end if; end process; -- u_Cnt_Load_Bram_oValid(u_PE_Endpt_Nr_Int) MULTIPLE_HANDSHAKE : for i in 0 to MAX_NR_ENDP generate Inst_HandshakeData_Count: entity work.HandshakeData GENERIC MAP ( kDataWidth => 12) PORT MAP( InClk => Axi_Clk, OutClk => Ulpi_Clk, iData => a_BRAM_Load_Counter_Array(i), oData => u_Cnt_Load_Bram_oData(i), iPush => a_Cnt_Load_Bram_iPush(i), iRdy => a_Cnt_Load_Bram_iRdy(i), oAck => u_Cnt_Load_Bram_oValid(i), oValid => u_Cnt_Load_Bram_oValid(i), aReset => aReset_Handshake(i) ); end generate; --aReset_Handshake <= (u_Resetn_N or (u_Send_Packet_PulseN)); ARESETN_PROC: process (Axi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us begin if (Ulpi_Clk' event and Ulpi_Clk = '1') then if (u_Resetn = '0') then aReset_Handshake <= (others => ('1')); else for index in 0 to MAX_NR_ENDP loop aReset_Handshake(index) <= aReset_Handshake_Loc(index) or u_Resetn_N; end loop; end if; end if; end process; ARESETN_LOC_PROC: process (Axi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us begin if (Ulpi_Clk' event and Ulpi_Clk = '1') then if (u_Resetn = '0') then aReset_Handshake_Loc <= (others => ('0')); else aReset_Handshake_Loc(u_PE_Endpt_Nr_Int) <= u_Send_Packet_PulseN; end if; end if; end process; IPUSH_PROC: process (Axi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us begin if (Axi_Clk' event and Axi_Clk = '1') then if (Axi_Resetn = '0') then a_Cnt_Load_Bram_iPush <= (others => ('0')); else if ((a_Cnt_Load_Bram_iRdy(a_Arb_Endpt_Nr_Int) = '1') and (a_Tx_Fifo_M_Axis_Tlast_NPulse_q = '1'))then a_Cnt_Load_Bram_iPush(a_Arb_Endpt_Nr_Int) <= '1'; else a_Cnt_Load_Bram_iPush(a_Arb_Endpt_Nr_Int) <= '0'; end if; end if; end if; end process; end Behavioral;
------------------------------------------------------------------------------- -- -- File: Transmit_Path.vhd -- Author: Gherman Tudor -- Original Project: USB Device IP on 7-series Xilinx FPGA -- Date: 2 May 2016 -- ------------------------------------------------------------------------------- -- (c) 2016 Copyright Digilent Incorporated -- All Rights Reserved -- -- This program is free software; distributed under the terms of BSD 3-clause -- license ("Revised BSD License", "New BSD License", or "Modified BSD License") -- -- Redistribution and use in source and binary forms, with or without modification, -- are permitted provided that the following conditions are met: -- -- 1. Redistributions of source code must retain the above copyright notice, this -- list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above copyright notice, -- this list of conditions and the following disclaimer in the documentation -- and/or other materials provided with the distribution. -- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names -- of its contributors may be used to endorse or promote products derived -- from this software without specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE -- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- -- -- Purpose: -- This module is responsible for buffering the data transfered through DMA, -- implementing the TX endpoints and sending the packet data on request from -- the protocol engine state machine request ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; Library UNISIM; use UNISIM.vcomponents.all; use ieee.numeric_std.all; use IEEE.std_logic_signed.all; entity Transmit_Path is generic ( C_S_AXI_DATA_WIDTH : integer := 3; MAX_NR_ENDP : integer := 1 ); PORT ( Axi_Resetn : IN STD_LOGIC; Axi_Clk : IN STD_LOGIC; Ulpi_Clk : in STD_LOGIC; u_Resetn : IN STD_LOGIC; u_PE_Endpt_Nr: in std_logic_vector(4 downto 0); a_Arb_Endpt_Nr : in std_logic_vector(4 downto 0); --!!!!! bits need to be synchronised Tx_Fifo_S_Aresetn : IN STD_LOGIC; a_Tx_Fifo_S_Aclk : IN STD_LOGIC; a_Tx_Fifo_S_Axis_Tvalid : IN STD_LOGIC; a_Tx_Fifo_S_Axis_Tready : OUT STD_LOGIC; a_Tx_Fifo_S_Axis_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); a_Tx_Fifo_S_Axis_Tlast : IN STD_LOGIC; a_Tx_Fifo_S_Axis_Tkeep : IN std_logic_vector(3 downto 0); a_Tx_Fifo_S_Axis_Tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); u_Send_Packet : in STD_LOGIC; u_Tx_Data_En : in STD_LOGIC; u_Tx_Data : out STD_LOGIC_VECTOR(7 downto 0); u_Send_Packet_Last : out STD_LOGIC; u_Endpt_Ready : out STD_LOGIC; latency_comp_in : in STD_LOGIC; latency_comp_out : out STD_LOGIC; tx_fifo_axis_overflow : OUT STD_LOGIC; tx_fifo_axis_underflow : OUT STD_LOGIC ); end Transmit_Path; architecture Behavioral of Transmit_Path is COMPONENT blk_mem_gen_1 PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); clkb : IN STD_LOGIC; enb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; COMPONENT TX_FIFO PORT ( s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC ); END COMPONENT; type a_BRAM_Base_AddrA_Array is array (MAX_NR_ENDP downto 0) of std_logic_vector(11 downto 0); constant a_BRAM_Base_AddrA : a_BRAM_Base_AddrA_Array := ("010000000000","000000000000"); constant u_BRAM_Base_AddrB : a_BRAM_Base_AddrA_Array := ("010000000000","000000000000"); type a_BRAM_Load_Array is array (MAX_NR_ENDP downto 0) of std_logic_vector(11 downto 0); signal a_BRAM_Load_Counter_Array : a_BRAM_Load_Array; type u_Cnt_Load_Bram_oData_Array is array (MAX_NR_ENDP downto 0) of std_logic_vector(11 downto 0); signal u_Cnt_Load_Bram_oData : u_Cnt_Load_Bram_oData_Array; type a_Cnt_Load_Bram_iPush_Array is array (MAX_NR_ENDP downto 0) of std_logic; signal a_Cnt_Load_Bram_iPush : a_Cnt_Load_Bram_iPush_Array; type a_Cnt_Load_Bram_iRdy_Array is array (MAX_NR_ENDP downto 0) of std_logic; signal a_Cnt_Load_Bram_iRdy : a_Cnt_Load_Bram_iRdy_Array; type u_Cnt_Load_Bram_oValid_Array is array (MAX_NR_ENDP downto 0) of std_logic; signal u_Cnt_Load_Bram_oValid : u_Cnt_Load_Bram_oValid_Array; type aReset_Handshake_Array is array (MAX_NR_ENDP downto 0) of std_logic; signal aReset_Handshake, aReset_Handshake_Loc : u_Cnt_Load_Bram_oValid_Array; signal u_Resetn_N : STD_LOGIC; signal a_BRAM_EnA : STD_LOGIC; signal a_BRAM_WeA : STD_LOGIC_VECTOR(0 DOWNTO 0); signal a_BRAM_AddrA, a_BRAM_AddrA_q : STD_LOGIC_VECTOR(11 DOWNTO 0); signal a_BRAM_Dina : STD_LOGIC_VECTOR(7 DOWNTO 0); signal u_BRAM_Enb, u_BRAM_Enb_Loc : STD_LOGIC; signal u_BRAM_AddrB : STD_LOGIC_VECTOR(11 DOWNTO 0); signal u_BRAM_DoutB, u_BRAM_DoutB_q : STD_LOGIC_VECTOR(7 DOWNTO 0); signal a_Tx_Fifo_M_Axis_Tvalid : STD_LOGIC; signal a_Tx_Fifo_M_Axis_Tready : STD_LOGIC; signal a_Tx_Fifo_M_Axis_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0); signal a_Tx_Fifo_M_Axis_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0); signal a_Tx_Fifo_M_Axis_Tlast : STD_LOGIC; signal a_Tx_Fifo_M_Load_Last : STD_LOGIC; --signal a_Tx_Fifo_M_Axis_Tuser : STD_LOGIC_VECTOR(3 DOWNTO 0); signal a_Byte_Index : integer range 0 to C_S_AXI_DATA_WIDTH; --signal a_Byte_Index_Rst : STD_LOGIC; signal a_Byte_Index_Inc : STD_LOGIC; signal a_Cnt_Load_Bram : STD_LOGIC_VECTOR(11 DOWNTO 0); signal a_Cnt_Load_Bram_Rst : STD_LOGIC; signal u_Cnt_Read_Bram : STD_LOGIC_VECTOR(11 DOWNTO 0); signal u_Cnt_Read_Bram_Rst : STD_LOGIC; signal a_DMA_Transfer_Start, a_DMA_Transfer_Start_Pulse, a_DMA_Transfer_Start_q : STD_LOGIC; signal a_Tx_Fifo_M_Axis_Tlast_q, a_Tx_Fifo_M_Axis_Tlast_NPulse, a_Tx_Fifo_M_Axis_Tlast_NPulse_q : STD_LOGIC; signal a_Tx_Fifo_S_Axis_Tlast_q, a_Tx_Fifo_S_Axis_Tlast_NPulse : STD_LOGIC; signal a_Load_BRAM_Start : STD_LOGIC; signal u_Send_Packet_Pulse, u_Send_Packet_PulseN, u_Send_Packet_q, u_Send_Packet_Pulse_q : STD_LOGIC; signal u_Tx_Data_En_q : STD_LOGIC; signal a_Arb_Endpt_Nr_Int, u_PE_Endpt_Nr_Int : integer range 0 to MAX_NR_ENDP; --attribute mark_debug : string; --attribute keep : string; --attribute mark_debug of a_Tx_Fifo_S_Axis_Tvalid : signal is "true"; --attribute keep of a_Tx_Fifo_S_Axis_Tvalid : signal is "true"; --attribute mark_debug of a_Tx_Fifo_S_Axis_Tdata : signal is "true"; --attribute keep of a_Tx_Fifo_S_Axis_Tdata : signal is "true"; --attribute mark_debug of a_Tx_Fifo_S_Axis_Tready : signal is "true"; --attribute keep of a_Tx_Fifo_S_Axis_Tready : signal is "true"; --attribute mark_debug of a_Tx_Fifo_S_Axis_Tlast : signal is "true"; --attribute keep of a_Tx_Fifo_S_Axis_Tlast : signal is "true"; --attribute mark_debug of a_Tx_Fifo_M_Axis_Tdata : signal is "true"; --attribute keep of a_Tx_Fifo_M_Axis_Tdata : signal is "true"; --attribute mark_debug of a_Tx_Fifo_M_Axis_Tvalid : signal is "true"; --attribute keep of a_Tx_Fifo_M_Axis_Tvalid : signal is "true"; --attribute mark_debug of a_Tx_Fifo_M_Axis_Tkeep : signal is "true"; --attribute keep of a_Tx_Fifo_M_Axis_Tkeep : signal is "true"; --attribute mark_debug of a_Tx_Fifo_M_Axis_Tlast : signal is "true"; --attribute keep of a_Tx_Fifo_M_Axis_Tlast : signal is "true"; --attribute mark_debug of a_Tx_Fifo_M_Axis_Tready : signal is "true"; --attribute keep of a_Tx_Fifo_M_Axis_Tready : signal is "true"; --attribute mark_debug of a_Byte_Index : signal is "true"; --attribute keep of a_Byte_Index : signal is "true"; --attribute mark_debug of a_BRAM_WeA : signal is "true"; --attribute keep of a_BRAM_WeA : signal is "true"; --attribute mark_debug of a_BRAM_AddrA_q : signal is "true"; --attribute keep of a_BRAM_AddrA_q : signal is "true"; --attribute mark_debug of a_BRAM_Dina : signal is "true"; --attribute keep of a_BRAM_Dina : signal is "true"; --attribute mark_debug of u_BRAM_Enb : signal is "true"; --attribute keep of u_BRAM_Enb : signal is "true"; --attribute mark_debug of u_BRAM_AddrB : signal is "true"; --attribute keep of u_BRAM_AddrB : signal is "true"; --attribute mark_debug of u_BRAM_DoutB : signal is "true"; --attribute keep of u_BRAM_DoutB : signal is "true"; --attribute mark_debug of u_BRAM_DoutB_q : signal is "true"; --attribute keep of u_BRAM_DoutB_q : signal is "true"; --attribute mark_debug of u_Send_Packet_Last : signal is "true"; --attribute keep of u_Send_Packet_Last : signal is "true"; --attribute mark_debug of u_Cnt_Read_Bram : signal is "true"; --attribute keep of u_Cnt_Read_Bram : signal is "true"; --attribute mark_debug of a_Tx_Fifo_M_Load_Last : signal is "true"; --attribute keep of a_Tx_Fifo_M_Load_Last : signal is "true"; --attribute mark_debug of a_Arb_Endpt_Nr_Int : signal is "true"; --attribute keep of a_Arb_Endpt_Nr_Int : signal is "true"; --attribute mark_debug of u_PE_Endpt_Nr_Int : signal is "true"; --attribute keep of u_PE_Endpt_Nr_Int : signal is "true"; --attribute mark_debug of a_Tx_Fifo_S_Axis_Tlast_NPulse : signal is "true"; --attribute keep of a_Tx_Fifo_S_Axis_Tlast_NPulse : signal is "true"; --attribute mark_debug of a_Cnt_Load_Bram : signal is "true"; --attribute keep of a_Cnt_Load_Bram : signal is "true"; --attribute mark_debug of u_Send_Packet_Pulse_q : signal is "true"; --attribute keep of u_Send_Packet_Pulse_q : signal is "true"; --attribute mark_debug of a_BRAM_Load_Counter_Array : signal is "true"; --attribute keep of a_BRAM_Load_Counter_Array : signal is "true"; --attribute mark_debug of u_Cnt_Load_Bram_oData : signal is "true"; --attribute keep of u_Cnt_Load_Bram_oData : signal is "true"; --attribute mark_debug of u_Cnt_Load_Bram_oValid : signal is "true"; --attribute keep of u_Cnt_Load_Bram_oValid : signal is "true"; --attribute mark_debug of a_Cnt_Load_Bram_iPush : signal is "true"; --attribute keep of a_Cnt_Load_Bram_iPush : signal is "true"; --attribute mark_debug of a_Cnt_Load_Bram_iRdy : signal is "true"; --attribute keep of a_Cnt_Load_Bram_iRdy : signal is "true"; --attribute mark_debug of aReset_Handshake : signal is "true"; --attribute keep of aReset_Handshake : signal is "true"; --attribute mark_debug of a_Tx_Fifo_M_Axis_Tlast_NPulse : signal is "true"; --attribute keep of a_Tx_Fifo_M_Axis_Tlast_NPulse : signal is "true"; --attribute mark_debug of u_Send_Packet_PulseN : signal is "true"; --attribute keep of u_Send_Packet_PulseN : signal is "true"; --attribute mark_debug of u_Send_Packet : signal is "true"; --attribute keep of u_Send_Packet : signal is "true"; begin u_Resetn_N <= not u_Resetn; a_Arb_Endpt_Nr_Int <= to_integer (unsigned (a_Arb_Endpt_Nr(4 downto 1))); u_PE_Endpt_Nr_Int <= to_integer (unsigned (u_PE_Endpt_Nr(4 downto 1))); a_BRAM_Dina <= a_Tx_Fifo_M_Axis_Tdata((a_Byte_Index *8 + 7) downto a_Byte_Index * 8); u_Endpt_Ready <= u_Cnt_Load_Bram_oValid(u_PE_Endpt_Nr_Int); TX_FIFO_INST: TX_FIFO PORT MAP ( s_aclk => a_Tx_Fifo_S_Aclk, s_aresetn => Tx_Fifo_S_Aresetn, s_axis_tvalid => a_Tx_Fifo_S_Axis_Tvalid, s_axis_tready => a_Tx_Fifo_S_Axis_Tready, s_axis_tdata => a_Tx_Fifo_S_Axis_Tdata, s_axis_tkeep => a_Tx_Fifo_S_Axis_Tkeep, s_axis_tlast => a_Tx_Fifo_S_Axis_Tlast, s_axis_tuser => a_Tx_Fifo_S_Axis_Tuser, m_axis_tvalid => a_Tx_Fifo_M_Axis_Tvalid, m_axis_tready => a_Tx_Fifo_M_Axis_Tready, m_axis_tdata => a_Tx_Fifo_M_Axis_Tdata, m_axis_tkeep => a_Tx_Fifo_M_Axis_Tkeep, m_axis_tlast => a_Tx_Fifo_M_Axis_Tlast, m_axis_tuser => open, axis_overflow => tx_fifo_axis_overflow, axis_underflow => tx_fifo_axis_underflow ); BRAM: blk_mem_gen_1 PORT MAP ( clka => Axi_Clk, ena => a_BRAM_EnA, wea => a_BRAM_WeA, addra => a_BRAM_AddrA_q, dina => a_BRAM_Dina, clkb => Ulpi_Clk, enb => u_BRAM_Enb, addrb => u_BRAM_AddrB, doutb => u_BRAM_DoutB ); u_BRAM_Enb <= u_BRAM_Enb_Loc or u_Send_Packet_Pulse_q; a_BRAM_EnA <= '1'; BYTE_INDEX_PROC: process(Axi_Clk) begin if (Axi_Clk 'event and Axi_Clk = '1') then if ((Axi_Resetn = '0') or (a_Tx_Fifo_M_Axis_Tlast_NPulse_q = '1')) then a_Byte_Index <= 0; elsif (a_Byte_Index_Inc = '1') then if (a_Byte_Index = (C_S_AXI_DATA_WIDTH)) then a_Byte_Index <= 0; else a_Byte_Index <= a_Byte_Index + 1; end if; end if; end if; end process; BRAM_WEA_PROC: process(Axi_Clk) begin if (Axi_Clk 'event and Axi_Clk = '1') then if (Axi_Resetn = '0') then a_BRAM_WeA <= "0"; else if ((a_Tx_Fifo_M_Axis_Tvalid = '1') and (a_Tx_Fifo_M_Axis_Tkeep(a_Byte_Index) = '1')and (a_Load_BRAM_Start = '1')) then a_BRAM_WeA <= "1"; else a_BRAM_WeA <= "0"; end if; end if; end if; end process; BRAM_READY_PROC: process(Axi_Clk) begin if (Axi_Clk 'event and Axi_Clk = '1') then if (Axi_Resetn = '0') then a_Tx_Fifo_M_Axis_Tready <= '0'; else if (a_Byte_Index = (C_S_AXI_DATA_WIDTH-1) ) then --if ((a_Byte_Index = (C_S_AXI_DATA_WIDTH-1)) or (a_Tx_Fifo_S_Axis_Tlast_NPulse = '1')) then a_Tx_Fifo_M_Axis_Tready <= '1'; else a_Tx_Fifo_M_Axis_Tready <= '0'; end if; end if; end if; end process; BYTE_INDEX_INC_PROC: process(Axi_Clk) begin if (Axi_Clk 'event and Axi_Clk = '1') then if (Axi_Resetn = '0') then a_Byte_Index_Inc <= '0'; else if ((a_Tx_Fifo_M_Axis_Tvalid = '1') and (a_Load_BRAM_Start = '1')) then a_Byte_Index_Inc <= '1'; else a_Byte_Index_Inc <= '0'; end if; end if; end if; end process; LOAD_BRAM_START_PROC: process(Axi_Clk) begin if (Axi_Clk 'event and Axi_Clk = '1') then if ((Axi_Resetn = '0') or (a_Tx_Fifo_M_Axis_Tlast_NPulse = '1')) then a_Load_BRAM_Start <= '0'; else if (a_Tx_Fifo_S_Axis_Tlast_NPulse = '1') then a_Load_BRAM_Start <= '1'; end if; end if; end if; end process; BRAM_ADDRESSA_PROC: process(Axi_Clk) begin if (Axi_Clk 'event and Axi_Clk = '1') then if (Axi_Resetn = '0') then a_BRAM_AddrA <= (others => '0'); a_BRAM_AddrA_q <= (others => '0'); else a_BRAM_AddrA_q <= a_BRAM_AddrA; if (a_DMA_Transfer_Start_Pulse = '1') then a_BRAM_AddrA <= a_BRAM_Base_AddrA(a_Arb_Endpt_Nr_Int); elsif ((a_Tx_Fifo_M_Axis_Tvalid = '1') and (a_Tx_Fifo_M_Axis_Tkeep(a_Byte_Index) = '1') and (a_Load_BRAM_Start = '1')) then a_BRAM_AddrA <= std_logic_vector( to_unsigned((to_integer(unsigned(a_BRAM_AddrA)) + 1),12) ); end if; end if; end if; end process; DMA_TRANSFER_START_PROC: process(Axi_Clk) begin if (Axi_Clk 'event and Axi_Clk = '1') then if (Axi_Resetn = '0' or a_Tx_Fifo_M_Axis_Tlast_q = '1') then a_DMA_Transfer_Start <= '0'; elsif (a_Tx_Fifo_S_Axis_Tvalid = '1') then a_DMA_Transfer_Start <= '1'; end if; end if; end process; DMA_TRANSFER_START_PULSE_PROC: process (Axi_Clk) begin if (Axi_Clk'event and Axi_Clk = '1') then if (Axi_Resetn = '0') then a_DMA_Transfer_Start_Pulse <= '0'; a_DMA_Transfer_Start_q <= '0'; else a_DMA_Transfer_Start_q <= a_DMA_Transfer_Start; a_DMA_Transfer_Start_Pulse <= a_DMA_Transfer_Start and (not a_DMA_Transfer_Start_q); end if; end if; end process; a_Tx_Fifo_M_Load_Last <= '1' when ((a_Tx_Fifo_M_Axis_Tlast = '1') and (a_Byte_Index = 3)) else '0'; M_LAST_NPULSE_PROC: process (Axi_Clk) begin if (Axi_Clk'event and Axi_Clk = '1') then if (Axi_Resetn = '0') then a_Tx_Fifo_M_Axis_Tlast_NPulse <= '0'; a_Tx_Fifo_M_Axis_Tlast_NPulse_q <= '0'; a_Tx_Fifo_M_Axis_Tlast_q <= '0'; a_Cnt_Load_Bram_Rst <= '0'; else a_Tx_Fifo_M_Axis_Tlast_q <= a_Tx_Fifo_M_Load_Last; a_Tx_Fifo_M_Axis_Tlast_NPulse <= a_Tx_Fifo_M_Load_Last and (not a_Tx_Fifo_M_Axis_Tlast_q); a_Cnt_Load_Bram_Rst <= a_Tx_Fifo_M_Axis_Tlast_NPulse_q; a_Tx_Fifo_M_Axis_Tlast_NPulse_q <= a_Tx_Fifo_M_Axis_Tlast_NPulse; end if; end if; end process; S_LAST_NPULSE_PROC: process (Axi_Clk) begin if (Axi_Clk'event and Axi_Clk = '1') then if (Axi_Resetn = '0') then a_Tx_Fifo_S_Axis_Tlast_NPulse <= '0'; a_Tx_Fifo_s_Axis_Tlast_q <= '0'; else a_Tx_Fifo_S_Axis_Tlast_q <= a_Tx_Fifo_S_Axis_Tlast; a_Tx_Fifo_S_Axis_Tlast_NPulse <= (not a_Tx_Fifo_S_Axis_Tlast) and a_Tx_Fifo_S_Axis_Tlast_q; end if; end if; end process; BRAM_LOAD_COUNTER_PROC: process (Axi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us begin if (Axi_Clk' event and Axi_Clk = '1') then if ((a_Cnt_Load_Bram_Rst = '1') or (Axi_Resetn = '0')) then a_Cnt_Load_Bram <= (others => '0'); elsif (a_BRAM_WeA = "1") then a_Cnt_Load_Bram <= a_Cnt_Load_Bram + '1'; end if; end if; end process; BRAM_LOAD_PROC: process (Axi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us begin if (Axi_Clk' event and Axi_Clk = '1') then if (Axi_Resetn = '0') then a_BRAM_Load_Counter_Array <= (others => (others => '0')); elsif (a_Tx_Fifo_M_Axis_Tlast_NPulse_q = '1') then a_BRAM_Load_Counter_Array(a_Arb_Endpt_Nr_Int) <= (a_Cnt_Load_Bram - '1'); end if; end if; end process; --------------------------------------------------------------------------------------------------- TDATA_PROC: process(u_Tx_Data_En, u_Tx_Data_En_q, u_BRAM_DoutB, u_BRAM_DoutB_q) begin if (u_Tx_Data_En = '0') then u_Tx_Data <= u_BRAM_DoutB_q; else u_Tx_Data <= u_BRAM_DoutB; end if; end process; REG_AXIS_TDATA_PROC: process(Ulpi_Clk) begin if (Ulpi_Clk 'event and Ulpi_Clk = '1') then if (u_Resetn = '0') then u_BRAM_DoutB_q <= (others => '0'); latency_comp_out <= '0'; else latency_comp_out <= latency_comp_in; if((u_BRAM_Enb = '1') or (u_Cnt_Read_Bram = u_Cnt_Load_Bram_oData(u_PE_Endpt_Nr_Int)) or (u_Send_Packet_Pulse_q = '1')) then u_BRAM_DoutB_q <= u_BRAM_DoutB; end if; end if; end if; end process; SEND_PACKET_PULSE_PROC: process (Ulpi_Clk) begin if (Ulpi_Clk'event and Ulpi_Clk = '1') then if (u_Resetn = '0') then u_Send_Packet_Pulse <= '0'; u_Send_Packet_PulseN <= '0'; u_Send_Packet_q <= '0'; u_Send_Packet_Pulse_q <= '0'; else u_Send_Packet_q <= u_Send_Packet; u_Send_Packet_Pulse <= u_Send_Packet and (not u_Send_Packet_q); u_Send_Packet_PulseN <= (not u_Send_Packet) and u_Send_Packet_q; u_Send_Packet_Pulse_q <= u_Send_Packet_Pulse; end if; end if; end process; DELAY_PROC: process (Ulpi_Clk) begin if (Ulpi_Clk'event and Ulpi_Clk = '1') then if (u_Resetn = '0') then u_Tx_Data_En_q <= '0'; else u_Tx_Data_En_q <= u_Tx_Data_En; end if; end if; end process; ENB_PROC: process (u_Send_Packet, u_Tx_Data_En, u_Tx_Data_En_q) begin --if (Axi_Clk'event and Axi_Clk = '1') then if (u_Send_Packet = '1') then if (u_Tx_Data_En = '1') then u_BRAM_Enb_Loc <= '1'; --elsif ((u_Tx_Data_En = '0') and (u_Tx_Data_En_q = '1')) then -- u_BRAM_Enb_Loc <= '1'; else u_BRAM_Enb_Loc <= '0'; end if; else u_BRAM_Enb_Loc <= '0'; end if; --end if; end process; BRAM_ADDRESSB_PROC: process(Ulpi_Clk) begin if (Ulpi_Clk 'event and Ulpi_Clk = '1') then if (u_Resetn = '0') then u_BRAM_AddrB <= (others => '0'); else if (u_Send_Packet_Pulse = '1') then u_BRAM_AddrB <= u_BRAM_Base_AddrB(u_PE_Endpt_Nr_Int); elsif ((u_Send_Packet = '1') and (u_BRAM_Enb = '1')) then u_BRAM_AddrB <= std_logic_vector( to_unsigned((to_integer(unsigned(u_BRAM_AddrB)) + 1),12) ); end if; end if; end if; end process; u_Cnt_Read_Bram_Rst <= u_Send_Packet_Pulse; BRAM_READ_COUNTER_PROC: process (Ulpi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us begin if (Ulpi_Clk' event and Ulpi_Clk = '1') then if ((u_Cnt_Read_Bram_Rst = '1') or (u_Resetn = '0')) then u_Cnt_Read_Bram <= (others => '0'); elsif (u_BRAM_Enb = '1') then u_Cnt_Read_Bram <= u_Cnt_Read_Bram + '1'; end if; end if; end process; LAST_PROC: process (Ulpi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us begin if (Ulpi_Clk' event and Ulpi_Clk = '1') then if (u_Resetn = '0') then u_Send_Packet_Last <= '0'; elsif((u_Send_Packet = '1') and (u_Tx_Data_En = '1')) then if ((u_Cnt_Load_Bram_oData(u_PE_Endpt_Nr_Int) - '1') = u_Cnt_Read_Bram) then-- std_logic_vector( to_unsigned((to_integer(unsigned(u_Cnt_Read_Bram)) - 3),12))) then u_Send_Packet_Last <= '1'; else u_Send_Packet_Last <= '0'; end if; elsif ((u_Send_Packet_Pulse = '1') and (u_Cnt_Load_Bram_oData(u_PE_Endpt_Nr_Int) = "0000000000000001")) then u_Send_Packet_Last <= '1'; else u_Send_Packet_Last <= '0'; end if; end if; end process; -- u_Cnt_Load_Bram_oValid(u_PE_Endpt_Nr_Int) MULTIPLE_HANDSHAKE : for i in 0 to MAX_NR_ENDP generate Inst_HandshakeData_Count: entity work.HandshakeData GENERIC MAP ( kDataWidth => 12) PORT MAP( InClk => Axi_Clk, OutClk => Ulpi_Clk, iData => a_BRAM_Load_Counter_Array(i), oData => u_Cnt_Load_Bram_oData(i), iPush => a_Cnt_Load_Bram_iPush(i), iRdy => a_Cnt_Load_Bram_iRdy(i), oAck => u_Cnt_Load_Bram_oValid(i), oValid => u_Cnt_Load_Bram_oValid(i), aReset => aReset_Handshake(i) ); end generate; --aReset_Handshake <= (u_Resetn_N or (u_Send_Packet_PulseN)); ARESETN_PROC: process (Axi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us begin if (Ulpi_Clk' event and Ulpi_Clk = '1') then if (u_Resetn = '0') then aReset_Handshake <= (others => ('1')); else for index in 0 to MAX_NR_ENDP loop aReset_Handshake(index) <= aReset_Handshake_Loc(index) or u_Resetn_N; end loop; end if; end if; end process; ARESETN_LOC_PROC: process (Axi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us begin if (Ulpi_Clk' event and Ulpi_Clk = '1') then if (u_Resetn = '0') then aReset_Handshake_Loc <= (others => ('0')); else aReset_Handshake_Loc(u_PE_Endpt_Nr_Int) <= u_Send_Packet_PulseN; end if; end if; end process; IPUSH_PROC: process (Axi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us begin if (Axi_Clk' event and Axi_Clk = '1') then if (Axi_Resetn = '0') then a_Cnt_Load_Bram_iPush <= (others => ('0')); else if ((a_Cnt_Load_Bram_iRdy(a_Arb_Endpt_Nr_Int) = '1') and (a_Tx_Fifo_M_Axis_Tlast_NPulse_q = '1'))then a_Cnt_Load_Bram_iPush(a_Arb_Endpt_Nr_Int) <= '1'; else a_Cnt_Load_Bram_iPush(a_Arb_Endpt_Nr_Int) <= '0'; end if; end if; end if; end process; end Behavioral;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity oscint00 is port( osc_dis: in std_logic ; tmr_rst: in std_logic ; tmr_out: out std_logic ; osc_out: out std_logic ); attribute loc: string; attribute loc of osc_dis: signal is "p125"; attribute loc of tmr_rst: signal is "p110"; attribute loc of tmr_out: signal is "p58"; attribute loc of osc_out: signal is "p59"; end; architecture oscint0 of oscint00 is component osctimer generic(TIMER_DIV : string); port( DYNOSCDIS : in std_logic; TIMERRES : in std_logic; OSCOUT : out std_logic; TIMEROUT : out std_logic); end component; begin I1: OSCTIMER generic map (TIMER_DIV => "1048576") port map ( DYNOSCDIS => osc_dis, TIMERRES => tmr_rst, OSCOUT => osc_out, TIMEROUT => tmr_out); end oscint0;
------------------------------------------------------------------------------- -- Department of Computer Engineering and Communications -- Author: LPRS2 <lprs2@rt-rk.com> -- -- Module Name: graphics_mem -- -- Description: -- -- Dual-port RAM for graphics -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity graphics_mem is generic( MEM_ADDR_WIDTH : natural := 32; MEM_DATA_WIDTH : natural := 32; MEM_SIZE : natural := 4800 ); port( clk_i : in std_logic; reset_n_i : in std_logic; wr_addr_i : in std_logic_vector(MEM_ADDR_WIDTH-1 downto 0); -- write address input rd_addr_i : in std_logic_vector(MEM_ADDR_WIDTH-1 downto 0); -- read address input wr_data_i : in std_logic_vector(MEM_DATA_WIDTH-1 downto 0); -- Write data output we_i : in std_logic; -- 1 - write transaction rd_data_o : out std_logic -- read data output ); end entity; architecture arc_graphics_mem of graphics_mem is type t_graphics_mem is array (0 to MEM_SIZE/MEM_DATA_WIDTH-1) of std_logic_vector(MEM_DATA_WIDTH-1 downto 0); signal graphics_mem : t_graphics_mem := ( -- 0 => "000000", -- 1 => "000001", -- 2 => "000010", others => (others => '0') ); signal mem_up_addr : std_logic_vector(MEM_ADDR_WIDTH-1 downto 0); signal mem_lo_addr : std_logic_vector(5-1 downto 0); signal rd_value : std_logic_vector(MEM_DATA_WIDTH-1 downto 0); signal index_0_t : natural; signal index_0 : natural; signal index_1_t : natural; signal index_1 : natural; signal index_2_t : natural; signal index_2 : natural; begin -- get address for graphics mem based on memory format mem_up_addr <= "000" & rd_addr_i(MEM_ADDR_WIDTH-1 downto 3) when (MEM_DATA_WIDTH = 8) else "0000" & rd_addr_i(MEM_ADDR_WIDTH-1 downto 4) when (MEM_DATA_WIDTH = 16) else "00000" & rd_addr_i(MEM_ADDR_WIDTH-1 downto 5); mem_lo_addr <= "00" & rd_addr_i(3-1 downto 0) when (MEM_DATA_WIDTH = 8) else '0' & rd_addr_i(4-1 downto 0) when (MEM_DATA_WIDTH = 16) else rd_addr_i(5-1 downto 0); DP_GRAPHICS_MEM : process (clk_i) begin if (rising_edge(clk_i)) then if (we_i = '1') then graphics_mem(index_2) <= wr_data_i; end if; --rd_value <= graphics_mem(conv_integer(index_0)); end if; end process; DP_GRAPHICS_MEM_RD : process (clk_i) begin if (rising_edge(clk_i)) then rd_value <= graphics_mem(conv_integer(index_0)); end if; end process; rd_data_o <= rd_value(conv_integer(index_1)); index_0_t <= conv_integer(mem_up_addr); index_0 <= index_0_t when (index_0_t < graphics_mem'length) else 0; index_1_t <= conv_integer(mem_lo_addr); index_1 <= index_1_t when (index_1_t < graphics_mem'length) else 0; index_2_t <= conv_integer(wr_addr_i); index_2 <= index_2_t when (index_2_t < graphics_mem'length) else 0; end arc_graphics_mem;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc87.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c04s03b01x03p05n02i00087ent IS END c04s03b01x03p05n02i00087ent; ARCHITECTURE c04s03b01x03p05n02i00087arch OF c04s03b01x03p05n02i00087ent IS BEGIN TESTING: PROCESS type acc_type is access integer; variable x : acc_type ; -- No_failure_here BEGIN assert NOT( X=Null ) report "***PASSED TEST: c04s03b01x03p05n02i00087" severity NOTE; assert ( X=Null ) report "***FAILED TEST: c04s03b01x03p05n02i00087 - Variable default assignment failed." severity ERROR; wait; END PROCESS TESTING; END c04s03b01x03p05n02i00087arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc87.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c04s03b01x03p05n02i00087ent IS END c04s03b01x03p05n02i00087ent; ARCHITECTURE c04s03b01x03p05n02i00087arch OF c04s03b01x03p05n02i00087ent IS BEGIN TESTING: PROCESS type acc_type is access integer; variable x : acc_type ; -- No_failure_here BEGIN assert NOT( X=Null ) report "***PASSED TEST: c04s03b01x03p05n02i00087" severity NOTE; assert ( X=Null ) report "***FAILED TEST: c04s03b01x03p05n02i00087 - Variable default assignment failed." severity ERROR; wait; END PROCESS TESTING; END c04s03b01x03p05n02i00087arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc87.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c04s03b01x03p05n02i00087ent IS END c04s03b01x03p05n02i00087ent; ARCHITECTURE c04s03b01x03p05n02i00087arch OF c04s03b01x03p05n02i00087ent IS BEGIN TESTING: PROCESS type acc_type is access integer; variable x : acc_type ; -- No_failure_here BEGIN assert NOT( X=Null ) report "***PASSED TEST: c04s03b01x03p05n02i00087" severity NOTE; assert ( X=Null ) report "***FAILED TEST: c04s03b01x03p05n02i00087 - Variable default assignment failed." severity ERROR; wait; END PROCESS TESTING; END c04s03b01x03p05n02i00087arch;
------------------------------------------------------------------ -- Copyright 2011(c) Analog Devices, Inc. -- -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without modification, -- are permitted provided that the following conditions are met: --  - Redistributions of source code must retain the above copyright --    notice, this list of conditions and the following disclaimer. --  - Redistributions in binary form must reproduce the above copyright --    notice, this list of conditions and the following disclaimer in --    the documentation and/or other materials provided with the --    distribution. --  - Neither the name of Analog Devices, Inc. nor the names of its --    contributors may be used to endorse or promote products derived --    from this software without specific prior written permission. --  - The use of this software may or may not infringe the patent rights --    of one or more patent holders.  This license does not release you --    from the requirement that you obtain separate licenses from these --    patent holders to use this software. --  - Use of the software either in source or binary form, must be run --    on or directly connected to an Analog Devices Inc. component. -- -- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR -- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE -- ------------------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity adv7511_embed_syncs is Port ( clk : in std_logic; reset : in std_logic; -- Video Input vblank_i : in std_logic; hblank_i : in std_logic; active_video_i : in std_logic; video_data_i : in std_logic_vector(15 downto 0); -- Video Output video_data_o : out std_logic_vector(15 downto 0) ); end adv7511_embed_syncs; architecture rtl of adv7511_embed_syncs is -- -- Input Delay -- signal vblank_d : std_logic_vector(6 downto 1); signal hblank_d : std_logic_vector(6 downto 1); signal active_video_d : std_logic_vector(6 downto 1); signal video_data_d1 : std_logic_vector(15 downto 0); signal video_data_d2 : std_logic_vector(15 downto 0); signal video_data_d3 : std_logic_vector(15 downto 0); signal video_data_d4 : std_logic_vector(15 downto 0); signal video_data_d5 : std_logic_vector(15 downto 0); signal video_data_d6 : std_logic_vector(15 downto 0); -- signal vblank_df : std_logic; signal hblank_df : std_logic; signal active_video_df : std_logic; signal video_data_df : std_logic_vector(15 downto 0); -- -- SAV/EAV Codes -- signal sav : std_logic_vector(15 downto 0); signal eav : std_logic_vector(15 downto 0); begin -- -- Input Delay -- input_delay_l : process (clk) begin if Rising_Edge(clk) then -- vblank delay line vblank_d <= vblank_d(5 downto 1) & vblank_i; -- hblank delay line hblank_d <= hblank_d(5 downto 1) & hblank_i; -- active_video delay line active_video_d <= active_video_d(5 downto 1) & active_video_i; -- video_data delay line video_data_d1 <= video_data_i; case ( hblank_d(5 downto 1) ) is when "01111" => video_data_d2 <= eav; when "00111" => video_data_d2 <= X"0000"; when "00011" => video_data_d2 <= X"0000"; when "00001" => video_data_d2 <= X"FFFF"; when others => video_data_d2 <= video_data_d1; end case; video_data_d3 <= video_data_d2; video_data_d4 <= video_data_d3; video_data_d5 <= video_data_d4; video_data_d6 <= video_data_d5; -- vblank_df <= vblank_d(6); hblank_df <= hblank_d(6); active_video_df <= active_video_d(6); case ( hblank_d(6 downto 2) ) is when "10000" => video_data_df <= sav; when "11000" => video_data_df <= X"0000"; when "11100" => video_data_df <= X"0000"; when "11110" => video_data_df <= X"FFFF"; when others => video_data_df <= video_data_d6; end case; end if; end process; video_data_o <= video_data_df; -- -- SAV/EAV Codes -- sav <= X"8080" when (vblank_d(2) = '0') else X"ABAB"; eav <= X"9D9D" when (vblank_d(2) = '0') else X"B6B6"; end rtl;
-- NEED RESULT: ARCH00549: Constant declarations - composite static subtypes failed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00549 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.3.1.1 (5) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00549) -- ENT00549_Test_Bench(ARCH00549_Test_Bench) -- -- REVISION HISTORY: -- -- 19-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; architecture ARCH00549 of E00000 is begin process variable correct : boolean := true ; constant co_bit_vector_1 : bit_vector := c_st_bit_vector_1 ; constant co_string_1 : string := c_st_string_1 ; constant co_t_rec1_1 : t_rec1 := c_st_rec1_1 ; constant co_st_rec1_1 : st_rec1 := c_st_rec1_1 ; constant co_t_rec2_1 : t_rec2 := c_st_rec2_1 ; constant co_st_rec2_1 : st_rec2 := c_st_rec2_1 ; constant co_t_rec3_1 : t_rec3 := c_st_rec3_1 ; constant co_st_rec3_1 : st_rec3 := c_st_rec3_1 ; constant co_t_arr1_1 : t_arr1 := c_st_arr1_1 ; constant co_st_arr1_1 : st_arr1 := c_st_arr1_1 ; constant co_t_arr2_1 : t_arr2 := c_st_arr2_1 ; constant co_st_arr2_1 : st_arr2 := c_st_arr2_1 ; constant co_t_arr3_1 : t_arr3 := c_st_arr3_1 ; constant co_st_arr3_1 : st_arr3 := c_st_arr3_1 ; begin correct := correct and co_bit_vector_1 = c_st_bit_vector_1 ; correct := correct and co_string_1 = c_st_string_1 ; correct := correct and co_t_rec1_1 = c_t_rec1_1 ; correct := correct and co_st_rec1_1 = c_st_rec1_1 ; correct := correct and co_t_rec2_1 = c_t_rec2_1 ; correct := correct and co_st_rec2_1 = c_st_rec2_1 ; correct := correct and co_t_rec3_1 = c_t_rec3_1 ; correct := correct and co_st_rec3_1 = c_st_rec3_1 ; correct := correct and co_t_arr1_1 = c_t_arr1_1 ; correct := correct and co_st_arr1_1 = c_st_arr1_1 ; correct := correct and co_t_arr2_1 = c_t_arr2_1 ; correct := correct and co_st_arr2_1 = c_st_arr2_1 ; correct := correct and co_t_arr3_1 = c_t_arr3_1 ; correct := correct and co_st_arr3_1 = c_st_arr3_1 ; test_report ( "ARCH00549" , "Constant declarations - composite static subtypes" , correct) ; wait ; end process ; end ARCH00549 ; -- entity ENT00549_Test_Bench is end ENT00549_Test_Bench ; -- architecture ARCH00549_Test_Bench of ENT00549_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00549 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00549_Test_Bench ;
--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- --= Wonderfully Simple ISP1362 Altera DE2 Interface Thing =- --= VERSION 0.1 -- data can be sent from computer to board =- --= =- --= ...simple description goes here... after I figure out what this thing is going to do --= --= I'm currently too pressed for time to make this officially public domain=- --= or open licence but that will happen. I can't stop you from stealing my=- --= work and claiming it as your own, but if you do, try and remember me =- --= when the boss says you're looking to hire. Some credit and an email =- --= wouldn't hurt if you find this useful for any sort of official project. =- --=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- library ieee, wsiaUSBlib, wsiaDescriptors; use ieee.std_logic_1164.all; --use ieee.std_logic_arith.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; use wsiaUSBlib.wsiaUseful.all; use wsiaUSBlib.wsiaDescriptors.all; entity bus_as_cpu is port( CLOCK_50 : in std_logic; -- reset_n : in std_logic; -- instruction : in worker_states; -- w_data32 : in word32; -- w_length : in word; -- w_endpoint : in std_logic_vector(3 downto 0); -- w_execute : in std_logic; --'1' => start executing instruction. -- w_done : out std_logic; -- w_ctrl_xfer : out byte16; --registers -- wi_DcAddress : in byte; -- wi_DcMode : in byte; -- wi_DcHardwareConfiguration : in word; -- wi_DcEndpointConfiguration : in word; -- wi_DcInterruptEnable : in dWord; -- wo_DcAddress : buffer byte; -- wo_DcMode : buffer byte; -- wo_DcHardwareConfiguration : buffer word; -- wo_DcInterruptEnable : buffer dWord; -- wo_DcInterrupt : buffer dWord; -- wo_ESR : out byte; OTG_INT1 : in std_logic; --ISP1362 Interrupt 2 (Peripheral Interrupts) OTG_DATA : inout std_logic_vector(15 downto 0); --ISP1362 Data bus 16 bits OTG_RST_N : out std_logic; --ISP1362 Reset pin OTG_ADDR : out std_logic_vector(1 downto 0); --ISP1362 Address 2 Bits[peripheral,command] OTG_CS_N : out std_logic; --ISP1362 Chip Select OTG_RD_N : out std_logic; --ISP1362 Write OTG_WR_N : out std_logic; --ISP1362 Read --IGNORE/SET AND FORGET OTG_FSPEED : out std_logic:='0'; --USB Full Speed, 0 = Enable, Z = Disable OTG_LSPEED : out std_logic:='Z'; --USB Low Speed, 0 = Enable, Z = Disable OTG_INT0 : in std_logic; --ISP1362 Interrupt 1 (Host Interrupts) OTG_DREQ0 : in std_logic; --ISP1362 DMA Request 1 OTG_DREQ1 : in std_logic; --ISP1362 DMA Request 2 OTG_DACK0_N : out std_logic:='1'; --ISP1362 DMA Acknowledge 1 OTG_DACK1_N : out std_logic:='1'; --ISP1362 DMA Acknowledge 2 --DIAGNOSTICS STUFF... KEY : in std_logic_vector(3 downto 0); SW : in std_logic_vector(17 downto 0); LEDR : out std_logic_vector(17 downto 0); LEDG : out std_logic_vector(8 downto 0); HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7 : out std_logic_vector(0 to 6) ); end bus_as_cpu; architecture handler of bus_as_cpu is component SevenSeg is port( inNum :in std_logic_vector(3 downto 0); outSeg :out std_logic_vector(6 downto 0)); end component SevenSeg; signal w_count : integer; signal segs1 : std_logic_vector(15 downto 0); signal segs2, segs3 : std_logic_vector(7 downto 0); signal CLOCK_25 : std_logic; signal cur_instruction : worker_states; signal stack : word32; signal SENT_DATA : word32; signal IP, IP_JMP : word := x"0000"; signal JMP : std_logic := 'L'; --Weak 0 signal SP, SP_NEXT : unsigned(4 downto 0) := "00000"; signal EAX,EBX,ECX,EDX,nEAX,nEBX,nECX,nEDX : dword := x"00000000"; alias ax : word is eax(15 downto 0);alias bx : word is ebx(15 downto 0); alias cx : word is ecx(15 downto 0);alias dx : word is edx(15 downto 0); alias ah : byte is eax(15 downto 8);alias al : byte is eax(7 downto 0); alias bh : byte is ebx(15 downto 8);alias bl : byte is ebx(7 downto 0); alias ch : byte is ecx(15 downto 8);alias cl : byte is ecx(7 downto 0); alias dh : byte is edx(15 downto 8);alias dl : byte is edx(7 downto 0); alias nax : word is neax(15 downto 0);alias nbx : word is nebx(15 downto 0); alias ncx : word is necx(15 downto 0);alias ndx : word is nedx(15 downto 0); alias nah : byte is neax(15 downto 8);alias nal : byte is neax(7 downto 0); alias nbh : byte is nebx(15 downto 8);alias nbl : byte is nebx(7 downto 0); alias nch : byte is necx(15 downto 8);alias ncl : byte is necx(7 downto 0); alias ndh : byte is nedx(15 downto 8);alias ndl : byte is nedx(7 downto 0); --registers signal OTG_DcAddress : byte; signal OTG_DcMode : byte; signal OTG_DcHardwareConfiguration : word; signal OTG_DcEndpointConfiguration : word16; signal OTG_DcInterruptEnable : dWord; signal OTG_DcInterrupt : dWord; signal OTG_ESR : byte16; signal OTG_INT1_latch : std_logic; signal instruction : worker_states; signal which_interface : byte:=x"00"; signal what_config : byte:=x"00"; signal w_buffer64 : buffer64; signal w_data32 : word32;--w_data32<=(w_buffer64(0*16+8 to 0*16+15) & w_buffer64(0*16 to 0*16+7),w_buffer64(1*16+8 to 1*16+15) & w_buffer64(1*16 to 1*16+7),w_buffer64(2*16+8 to 2*16+15) & w_buffer64(2*16 to 2*16+7),w_buffer64(3*16+8 to 3*16+15) & w_buffer64(3*16 to 3*16+7),w_buffer64(4*16+8 to 4*16+15) & w_buffer64(4*16 to 4*16+7),w_buffer64(5*16+8 to 5*16+15) & w_buffer64(5*16 to 5*16+7),w_buffer64(6*16+8 to 6*16+15) & w_buffer64(6*16 to 6*16+7),w_buffer64(7*16+8 to 7*16+15) & w_buffer64(7*16 to 7*16+7),w_buffer64(8*16+8 to 8*16+15) & w_buffer64(8*16 to 8*16+7),w_buffer64(9*16+8 to 9*16+15) & w_buffer64(9*16 to 9*16+7),w_buffer64(10*16+8 to 10*16+15) & w_buffer64(10*16 to 10*16+7),w_buffer64(11*16+8 to 11*16+15) & w_buffer64(11*16 to 11*16+7),w_buffer64(12*16+8 to 12*16+15) & w_buffer64(12*16 to 12*16+7),w_buffer64(13*16+8 to 13*16+15) & w_buffer64(13*16 to 13*16+7),w_buffer64(14*16+8 to 14*16+15) & w_buffer64(14*16 to 14*16+7),w_buffer64(15*16+8 to 15*16+15) & w_buffer64(15*16 to 15*16+7),w_buffer64(16*16+8 to 16*16+15) & w_buffer64(16*16 to 16*16+7),w_buffer64(17*16+8 to 17*16+15) & w_buffer64(17*16 to 17*16+7),w_buffer64(18*16+8 to 18*16+15) & w_buffer64(18*16 to 18*16+7),w_buffer64(19*16+8 to 19*16+15) & w_buffer64(19*16 to 19*16+7),w_buffer64(20*16+8 to 20*16+15) & w_buffer64(20*16 to 20*16+7),w_buffer64(21*16+8 to 21*16+15) & w_buffer64(21*16 to 21*16+7),w_buffer64(22*16+8 to 22*16+15) & w_buffer64(22*16 to 22*16+7),w_buffer64(23*16+8 to 23*16+15) & w_buffer64(23*16 to 23*16+7),w_buffer64(24*16+8 to 24*16+15) & w_buffer64(24*16 to 24*16+7),w_buffer64(25*16+8 to 25*16+15) & w_buffer64(25*16 to 25*16+7),w_buffer64(26*16+8 to 26*16+15) & w_buffer64(26*16 to 26*16+7),w_buffer64(27*16+8 to 27*16+15) & w_buffer64(27*16 to 27*16+7),w_buffer64(28*16+8 to 28*16+15) & w_buffer64(28*16 to 28*16+7),w_buffer64(29*16+8 to 29*16+15) & w_buffer64(29*16 to 29*16+7),w_buffer64(30*16+8 to 30*16+15) & w_buffer64(30*16 to 30*16+7),w_buffer64(31*16+8 to 31*16+15) & w_buffer64(31*16 to 31*16+7)); signal w_length : word; signal w_endpoint : std_logic_vector(3 downto 0); signal w_execute : std_logic; --'1' => start executing instruction. signal w_done : std_logic; signal w_ctrl_xfer : setup_packet_type; type eight_ctrls is array(0 to 7) of setup_packet_type; signal raw_ctrl_xfers:eight_ctrls; signal e_state : enum_state; signal IP_History : word32; signal IP_H_View : boolean; signal IP_H_V_num : integer range 0 to 31; signal keylast : std_logic_vector(3 downto 0); signal EP1_Buffer : buffer64;--EP1 --64b Bulk Out signal EP1_Buff : word32; signal EP2_Buffer : buffer64:=x"5400680065002000620075006700670061007200200077006F0072006B0073002100210021002000490020004C00750076002000530061007200610021002100";--EP2 --64b Bulk In signal EP3_Buffer : buffer16;--EP3 --16b Int Out signal EP3_Buff : word8; signal EP4_Buffer : buffer16;--EP4 --16b Int In constant sub_reset_Dc : word := x"1000"; --resets the device controller of the ISP1362 constant sub_port_out_cmd : word := x"1100"; --writes a command from AX constant sub_port_out : word := x"1200"; --writes a word from AX constant sub_port_in : word := x"1300"; --reads a word into AX constant sub_send_data : word := x"1400"; --endpoint in DL, length in w_length, data in w_data32 constant sub_port_dump : word := x"1500"; --number of bytes in CX, data in w_data32 constant sub_rd_cfg_regs : word := x"1600"; --reads from chip to reg_DcRegisters (mode, hwcfg, intenable only) constant sub_CRwrite : word := x"1700"; --writes command from AX and corresponding Reg_DcRegister constant sub_rcv_setup : word := x"1800"; --recieves 8 bytes from ctrlOut to w_ctrl_xfer constant sub_init_isp1362 : word := x"1900"; --initilizes isp1362 configuration DcRegisters constant sub_disp_cfg_regs : word := x"1A00"; --displays masked Dcmode, DcHardwareConfiguration and last word of DcInterruptEnable constant sub_DcInterrupt : word := x"1B00"; --loads OTG_DcInterrupt from isp1362 constant sub_suspender : word := x"1C00"; --handles suspend state and wakeup constant sub_ctrlOut_handler: word := x"1D00"; -- constant sub_Get_ESR : word := x"1E00"; --reads ESR specified by command in AX into OTG_ESR register and AL constant sub_SET_ADDRESS : word := x"1F00"; --handles SET_ADDRESS setup packet constant sub_configureEps_n_ack:word:= x"2000"; --configures endpoints and acknowledges constant sub_sendEpStatus : word := x"2200"; --send EpStatus and ack constant sub_EP_Int_handler : word := x"2300"; --handles endpoint interrupts --constant sub_ : word := x"2200"; -- --constant sub_ : word := x"2300"; -- procedure reset_cpu is begin OTG_RST_N <= '1'; OTG_ADDR(0) <= '1'; OTG_CS_N <= '1'; OTG_RD_N <= '1'; OTG_WR_N <= '1'; nEAX <= x"00000000"; nEBX <= x"00000000"; nECX <= x"00000000"; nEDX <= x"00000000"; sp_next <= "00000"; w_done <= '1'; e_state <= default; w_count <= 0; end reset_cpu; procedure push(constant data : in word) is begin stack(to_integer(SP-1)) <= data; SP_NEXT <= SP-1; end push; procedure pop(signal data : out word) is begin data <= stack(to_integer(sp)); SP_NEXT <= SP+1; end pop; procedure jump(constant New_IP : in word) is begin JMP <= '1'; IP_JMP <= New_IP; end jump; procedure loopJump(constant New_IP : in word) is begin nCX <= to_vec(16,to_int(CX) - 1); if CX /= x"0000" then jump(New_IP); end if; end loopJump; procedure go_sub(constant new_ip : in word) is begin stack(to_integer(SP-1)) <= IP+1; --we'll return to next ip SP_NEXT <= SP-1; JMP <= '1'; IP_JMP <= new_ip; end go_sub; procedure ret_sub is begin IP_JMP <= stack(to_integer(SP)); --ip incremented by go_sub JMP <= '1'; SP_NEXT <= SP+1; end ret_sub; procedure wait_here(constant num_clocks : in unsigned) is --wait_here(x"0000") is same as NoOp begin if w_count < num_clocks then w_count <= w_count + 1; IP_JMP <= IP; JMP <= '1'; else w_count <= 0; end if; end wait_here; procedure wait_for_command is begin if w_execute = '1' then cur_instruction <= instruction; w_done <= '0'; else jump(IP); end if; end wait_for_command; procedure loadBuffer(constant with_me : in std_logic_vector) is begin w_buffer64(0 to with_me'Length-1)<=with_me; end loadBuffer; procedure port_dump(constant destination:in nibble; constant to_send :in std_logic_vector; constant length_limit :in word := x"FFFF") is begin w_length<=smaller(to_vec(16,(to_send'length)/8),length_limit); loadBuffer(to_send); nDL(3 downto 0)<=destination; go_sub(sub_send_data); end port_dump; begin Hexx0 : SevenSeg port map(segs1(3 downto 0),HEX0(0 to 6)); Hexx1 : SevenSeg port map(segs1(7 downto 4),HEX1(0 to 6)); Hexx2 : SevenSeg port map(segs1(11 downto 8),HEX2(0 to 6)); Hexx3 : SevenSeg port map(segs1(15 downto 12),HEX3(0 to 6)); Hexx4 : SevenSeg port map(segs2(3 downto 0),HEX4(0 to 6)); Hexx5 : SevenSeg port map(segs2(7 downto 4),HEX5(0 to 6)); Hexx6 : SevenSeg port map(segs3(3 downto 0),HEX6(0 to 6)); Hexx7 : SevenSeg port map(segs3(7 downto 4),HEX7(0 to 6)); --=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-CLOCK PROCESS-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-- clock_halfer: process begin wait until clock_50'EVENT and clock_50='1'; if clock_25 = '1' then clock_25 <= '0'; else clock_25 <= '1'; end if; end process; --=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-IP_Mover PROCESS-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-- IP_Mover : process --Increments IP on falling clock edge (IP stable for 20ns after clock rise) begin --If jmp = true then instead sets IP to IP_JMP --ALSO SETS SP = SP_NEXT --ALSO SETS EAX,EBX,ECX,EDX to nEAX,nEBX,nECX,nEDX --ALSO latches OTG_INT1_latch --ALSO translates w_buffer64 into w_data32 wait until CLOCK_25'EVENT and CLOCK_25 = '0'; if JMP = '1' then IP <= IP_JMP; else IP <= IP+1; end if; SP <= SP_NEXT; EAX <= nEAX; EBX <= nEBX; ECX <= nECX; EDX <= nEDX; OTG_INT1_latch <= OTG_INT1; w_data32<=(w_buffer64(0*16+8 to 0*16+15) & w_buffer64(0*16 to 0*16+7), w_buffer64(1*16+8 to 1*16+15) & w_buffer64(1*16 to 1*16+7), w_buffer64(2*16+8 to 2*16+15) & w_buffer64(2*16 to 2*16+7), w_buffer64(3*16+8 to 3*16+15) & w_buffer64(3*16 to 3*16+7), w_buffer64(4*16+8 to 4*16+15) & w_buffer64(4*16 to 4*16+7), w_buffer64(5*16+8 to 5*16+15) & w_buffer64(5*16 to 5*16+7), w_buffer64(6*16+8 to 6*16+15) & w_buffer64(6*16 to 6*16+7), w_buffer64(7*16+8 to 7*16+15) & w_buffer64(7*16 to 7*16+7), w_buffer64(8*16+8 to 8*16+15) & w_buffer64(8*16 to 8*16+7), w_buffer64(9*16+8 to 9*16+15) & w_buffer64(9*16 to 9*16+7), w_buffer64(10*16+8 to 10*16+15) & w_buffer64(10*16 to 10*16+7),w_buffer64(11*16+8 to 11*16+15) & w_buffer64(11*16 to 11*16+7),w_buffer64(12*16+8 to 12*16+15) & w_buffer64(12*16 to 12*16+7),w_buffer64(13*16+8 to 13*16+15) & w_buffer64(13*16 to 13*16+7),w_buffer64(14*16+8 to 14*16+15) & w_buffer64(14*16 to 14*16+7),w_buffer64(15*16+8 to 15*16+15) & w_buffer64(15*16 to 15*16+7),w_buffer64(16*16+8 to 16*16+15) & w_buffer64(16*16 to 16*16+7),w_buffer64(17*16+8 to 17*16+15) & w_buffer64(17*16 to 17*16+7),w_buffer64(18*16+8 to 18*16+15) & w_buffer64(18*16 to 18*16+7),w_buffer64(19*16+8 to 19*16+15) & w_buffer64(19*16 to 19*16+7),w_buffer64(20*16+8 to 20*16+15) & w_buffer64(20*16 to 20*16+7),w_buffer64(21*16+8 to 21*16+15) & w_buffer64(21*16 to 21*16+7),w_buffer64(22*16+8 to 22*16+15) & w_buffer64(22*16 to 22*16+7),w_buffer64(23*16+8 to 23*16+15) & w_buffer64(23*16 to 23*16+7),w_buffer64(24*16+8 to 24*16+15) & w_buffer64(24*16 to 24*16+7),w_buffer64(25*16+8 to 25*16+15) & w_buffer64(25*16 to 25*16+7),w_buffer64(26*16+8 to 26*16+15) & w_buffer64(26*16 to 26*16+7),w_buffer64(27*16+8 to 27*16+15) & w_buffer64(27*16 to 27*16+7),w_buffer64(28*16+8 to 28*16+15) & w_buffer64(28*16 to 28*16+7),w_buffer64(29*16+8 to 29*16+15) & w_buffer64(29*16 to 29*16+7),w_buffer64(30*16+8 to 30*16+15) & w_buffer64(30*16 to 30*16+7),w_buffer64(31*16+8 to 31*16+15) & w_buffer64(31*16 to 31*16+7)); end process; OTG_ADDR(1) <= '1'; --always talking to the peripheral --=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-WORKER PROCESS-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-- worker : process begin wait until clock_25'EVENT and clock_25 = '1'; JMP <= 'L'; --Weak Low If someone else wants to jump, force it with '1'; keylast<=key; if keylast(3)='0' and key(3)='1' then --start viewing ip history if IP_H_View then IP_H_View <= false; else IP_H_View <= true; IP_H_V_Num <= 0; end if; end if; if IP_H_View then LEDR(17)<='0'; SEGS1 <= IP_History(IP_H_V_Num); SEGS2 <= std_logic_vector(to_unsigned(IP_H_V_Num,8)); case sw(17 downto 15) is when "000" => SEGS3 <= raw_ctrl_xfers(to_int(sw(9 downto 7))).bmRequestType; when "001" => SEGS3 <= raw_ctrl_xfers(to_int(sw(9 downto 7))).bRequest; when "010" => SEGS3 <= raw_ctrl_xfers(to_int(sw(9 downto 7))).wValue(7 downto 0); when "011" => SEGS3 <= raw_ctrl_xfers(to_int(sw(9 downto 7))).wValue(15 downto 8); when "100" => SEGS3 <= raw_ctrl_xfers(to_int(sw(9 downto 7))).wIndex(7 downto 0); when "101" => SEGS3 <= raw_ctrl_xfers(to_int(sw(9 downto 7))).wIndex(15 downto 8); when "110" => SEGS3 <= raw_ctrl_xfers(to_int(sw(9 downto 7))).wLength(7 downto 0); when "111" => SEGS3 <= raw_ctrl_xfers(to_int(sw(9 downto 7))).wLength(15 downto 8); end case; if keylast(2)='0' and key(2) = '1' then IP_H_V_Num <= IP_H_V_Num+1; elsif keylast(1)='0' and key(1) = '1' then IP_H_V_Num <= IP_H_V_Num-1; end if; else LEDR(17)<='1'; if sw(1 downto 0) = "00" then SEGS1 <= w_data32(to_integer(unsigned(sw(14 downto 10))));--OTG_DcInterrupt(31 downto 16); elsif sw(1 downto 0) = "01" then SEGS1 <= sent_data(to_integer(unsigned(sw(14 downto 10)))); elsif sw(1 downto 0) = "10" then SEGS1 <= EP1_Buff(to_integer(unsigned(sw(14 downto 10))));-- end if; SEGS2 <= IP(7 downto 0); SEGS3 <= OTG_ESR(0); if IP/=IP_History(0) then IP_History(31)<=IP_History(30);IP_History(30)<=IP_History(29);IP_History(29)<=IP_History(28);IP_History(28)<=IP_History(27);IP_History(27)<=IP_History(26);IP_History(26)<=IP_History(25);IP_History(25)<=IP_History(24);IP_History(24)<=IP_History(23);IP_History(23)<=IP_History(22);IP_History(22)<=IP_History(21);IP_History(21)<=IP_History(20);IP_History(20)<=IP_History(19);IP_History(19)<=IP_History(18);IP_History(18)<=IP_History(17);IP_History(17)<=IP_History(16);IP_History(16)<=IP_History(15);IP_History(15)<=IP_History(14);IP_History(14)<=IP_History(13);IP_History(13)<=IP_History(12);IP_History(12)<=IP_History(11);IP_History(11)<=IP_History(10);IP_History(10)<=IP_History(9);IP_History(9) <=IP_History(8);IP_History(8) <=IP_History(7);IP_History(7) <=IP_History(6);IP_History(6) <=IP_History(5);IP_History(5) <=IP_History(4);IP_History(4) <=IP_History(3);IP_History(3) <=IP_History(2);IP_History(2) <=IP_History(1);IP_History(1) <=IP_History(0);IP_History(0) <=IP; end if; end if; LEDR(15 downto 0) <= OTG_DcInterrupt(15 downto 0); if SP = "00001" then LEDR(16) <= '1'; IP_H_View <= true; end if; if e_state = default then ledg(2 downto 0) <= "100"; elsif e_state = address then ledg(2 downto 0) <= "110"; else ledg(2 downto 0) <= "111"; end if; LEDG(8)<=OTG_INT1; if key(0) = '0' then jump(x"0000"); LEDR(16)<='0'; else case ip is --=-=-=-=-=-MAIN LOOP STARTS HERE-=-=-=-=-=-- when x"0000" => --reset cpu reset_cpu; when x"0001" => go_sub(sub_reset_Dc); when x"0002" => go_sub(sub_init_isp1362); when x"0003" => wait_here(x"09C4"); when x"0004" =>--0111111100000101 if OTG_INT1_latch = '1' then go_sub(sub_DcInterrupt); else jump(IP); --wait here; end if; when x"0005" =>--interrupt in ax if OTG_DcInterrupt(0) = '1' then --reset jump(x"0000");--0003"); elsif OTG_DcInterrupt(2) = '1' or OTG_DcInterrupt(7) = '1' then --suspend detected go_sub(sub_suspender); elsif OTG_DcInterrupt(8) = '1' then --ctrlOut is paging go_sub(sub_ctrlOut_handler); elsif OTG_DcInterrupt(14 downto 10)/="00000" then --endpoint paging go_sub(sub_ep_int_handler); else jump(IP); --i.e. Lock Up here end if; when x"0006" => jump(x"0004"); --=-=-=-=-=-PROGRAMMATIC SUBROUTINES-=-=-=-=-=-- --GO_SUB(x"1000");reset_dc--resets isp1362 when x"1000" => OTG_RST_N <= '0'; when x"1001" => wait_here(x"09C4"); --clock at 25MHz => cycle lasts 40ns. we need to wait 100us. 100/.04=2500 when x"1002" => OTG_RST_N <= '1'; when x"1003" => ret_sub; --GO_SUB(x"1100");port_out_cmd-- when x"1100" => --0ns OTG_ADDR(0) <= '1'; OTG_CS_N <= '0'; OTG_RD_N <= '1'; OTG_WR_N <= '0'; OTG_DATA <= AX; when x"1101" => --40ns OTG_WR_N <= '1'; when x"1102" => --80ns OTG_CS_N <= '1'; when x"1103" => --120ns when x"1104" => --160ns OTG_DATA <= "ZZZZZZZZZZZZZZZZ"; ret_sub; --GO_SUB(x"1200");port_out-- when x"1200" => --0ns OTG_ADDR(0) <= '0'; OTG_CS_N <= '0'; OTG_RD_N <= '1'; OTG_WR_N <= '0'; OTG_DATA <= AX; when x"1201" => --40ns OTG_WR_N <= '1'; when x"1202" => --80ns OTG_CS_N <= '1'; when x"1203" => --120ns OTG_DATA <= "ZZZZZZZZZZZZZZZZ"; ret_sub; --GO_SUB(x"1300");port_in-- when x"1300" => --0ns OTG_ADDR(0) <= '0'; OTG_CS_N <= '0'; OTG_RD_N <= '0'; OTG_WR_N <= '1'; when x"1301" => --40ns nAX <= OTG_DATA; when x"1302" => --80ns OTG_RD_N <= '1'; OTG_CS_N <= '1'; when x"1303" => --120ns OTG_DATA <= "ZZZZZZZZZZZZZZZZ"; ret_sub; --GO_SUB(x"1400");send_data_to_endpoint_in_DL(3 downto 0)-- when x"1400" => go_sub(sub_port_out_cmd); nAX <= Wr_Buffer & DL(3 downto 0); when x"1401" => go_sub(sub_port_out); nAX <= w_length; when x"1402" => go_sub(sub_port_dump); when x"1403" => go_sub(sub_port_out_cmd); nAX <= Validate & DL(3 downto 0); when x"1404" => ret_sub; --GO_SUB(x"1500");port_dump_from_data32 number of bytes in w_Length when x"1500" => w_count <= 0; nBX <= x"0000"; if w_Length = x"0000" then ret_sub; end if; when x"1501" => --0ns OTG_ADDR(0) <= '0'; OTG_CS_N <= '0'; OTG_RD_N <= '1'; OTG_WR_N <= '0'; OTG_DATA <= w_data32(w_count); when x"1502" => --40ns OTG_WR_N <= '1'; sent_data(w_count)<=OTG_DATA; when x"1503" => --80ns OTG_CS_N <= '1'; w_count<=w_count+1; when x"1504" => --120ns when x"1505" => --160ns if w_count < (to_int(w_length)+1)/2 then jump(x"1501"); end if; when x"1506" => w_count <= 0; OTG_DATA<= "ZZZZZZZZZZZZZZZZ"; ret_sub; --GO_SUB(x"1600");read_cfg_regs when x"1600" => go_sub(sub_port_out_cmd); nAX <= Rd_DcInterruptEnable; when x"1601" => go_sub(sub_port_in); when x"1602" => OTG_DcInterruptEnable(15 downto 0) <= AX; go_sub(sub_port_in); when x"1603" => OTG_DcInterruptEnable(31 downto 16) <= AX; go_sub(sub_port_out_cmd); nAX <= Rd_DcHardwareConfiguration; when x"1604" => go_sub(sub_port_in); when x"1605" => OTG_DcHardwareConfiguration <= AX; go_sub(sub_port_out_cmd); nAX <= Rd_DcMode; when x"1606" => go_sub(sub_port_in); when x"1607" => OTG_DcMode <= AL; ret_sub; --GO_SUB(x"1700");CRwrite --writes value from Reg_DcRegister commanded by AX into register when x"1700" => go_sub(sub_port_out_cmd); nDX <= AX; when x"1701" => go_sub(sub_port_out); case AX is when Wr_DcAddress => --byte nAL <= OTG_DcAddress; when Wr_DcMode => --byte nAL <= OTG_DcMode; when Wr_DcHardwareConfiguration => --word nAX <= OTG_DcHardwareConfiguration; when Wr_DcInterruptEnable => --dword nAX <= OTG_DcInterruptEnable(15 downto 0); when UnlockDevice => --byte (special) nAX <= x"AA37"; when others => if AX(15 downto 4)=Wr_DcEndpointConfiguration then nAX <= OTG_DcEndpointConfiguration(to_integer(unsigned(AX(3 downto 0)))); end if; end case; when x"1702" => if DX = Wr_DcInterruptEnable then nAX <= OTG_DcInterruptEnable(31 downto 16); go_sub(sub_port_out); else ret_sub; end if; when x"1703" => ret_sub; --GO_SUB(x"1800");rcv_setup --recieves 8 bytes from ctrlOut to w_ctrl_xfer when x"1800" => nAX <= Rd_Buffer & ctrlOut; go_sub(sub_port_out_cmd); when x"1801" => go_sub(sub_port_in); when x"1802" => go_sub(sub_port_in); raw_ctrl_xfers(7)<=raw_ctrl_xfers(6); raw_ctrl_xfers(6)<=raw_ctrl_xfers(5); raw_ctrl_xfers(5)<=raw_ctrl_xfers(4); raw_ctrl_xfers(4)<=raw_ctrl_xfers(3); raw_ctrl_xfers(3)<=raw_ctrl_xfers(2); raw_ctrl_xfers(2)<=raw_ctrl_xfers(1); raw_ctrl_xfers(1)<=raw_ctrl_xfers(0); when x"1803" => w_ctrl_xfer.bmRequestType <= AL; w_ctrl_xfer.bRequest <= AH; go_sub(sub_port_in); when x"1804" => w_ctrl_xfer.wValue <= AX; go_sub(sub_port_in); when x"1805" => w_ctrl_xfer.wIndex <= AX; go_sub(sub_port_in); when x"1806" => w_ctrl_xfer.wLength <= AX; nAX <= AcknowledgeSetup; go_sub(sub_port_out_cmd); when x"1807" => raw_ctrl_xfers(0)<=w_ctrl_xfer; nAX <= ClearBuffer & ctrlOut; go_sub(sub_port_out_cmd); when x"1808" => ret_sub; --GO_SUB(x"1900");init_isp1362 --initilizes isp1362 DcRegisters when x"1900" => go_sub(sub_rd_cfg_regs); when x"1901" => OTG_DcMode <= (OTG_DcMode and x"D2") or x"09"; OTG_DcHardwareConfiguration <= (OTG_DcHardwareConfiguration and x"8014") or x"20E1"; OTG_DcInterruptEnable <= (OTG_DcInterruptEnable and x"11000080") or x"00007D06"; go_sub(sub_CRwrite); nAX <= Wr_DcMode; when x"1902" => go_sub(sub_CRwrite); nAX <= Wr_DcHardwareConfiguration; when x"1903" => go_sub(sub_CRwrite); nAX <= Wr_DcInterruptEnable; when x"1904" => ret_sub; --GO_SUB(x"1A00");Disp_Cfg_Regs --displays masked Dcmode, DcHardwareConfiguration and last word of DcInterruptEnable when x"1A00" => go_sub(sub_rd_cfg_regs); when x"1A01" => -- segs1 <= (OTG_DcInterruptEnable(15 downto 0) and x"FF7F"); segs2 <= (OTG_DcHardwareConfiguration(7 downto 0) and x"EB"); segs3 <= (OTG_DcHardwareConfiguration(15 downto 8) and x"7F"); LEDR(15 downto 0)<= x"00" & (OTG_DcMode and x"2D"); ret_sub; --GO_SUB(x"");DcInterrupt --loads OTG_DcInterrupt from isp1362 when x"1B00" => go_sub(sub_port_out_cmd); nAX <= Rd_DcInterrupt; when x"1B01" => go_sub(sub_port_in); when x"1B02" => OTG_DcInterrupt(15 downto 0) <= AX; go_sub(sub_port_in); when x"1B03" => OTG_DcInterrupt(31 downto 16) <= AX; ret_sub; --GO_SUB(x"");sub_suspender when x"1C00" => go_sub(sub_DcInterrupt); when x"1C01" => if (OTG_DcInterrupt(2)='1' and OTG_DcInterrupt(7)='1') then go_sub(sub_rd_cfg_regs); else ret_sub; end if; when x"1C02" => go_sub(sub_CRwrite); nAX <= Wr_DcMode or "00100000"; when x"1C03" => go_sub(sub_CRwrite); nAX <= Wr_DcMode and "11011111"; when x"1C04" => wait_here(x"FFFF"); --5 ms before bus will wake up for sure when x"1C05" => wait_here(x"E847"); --(rest of 5ms) when x"1C06" => if OTG_INT1_latch = '1' then wait_here(x"09C4"); --100us to wake up else jump(IP);--MODIFIED MODIFIED MODIFIED!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!ADDED THIS end if; when x"1C07" => go_sub(sub_CRwrite); nAX <= UnlockDevice; when x"1C08" => go_sub(sub_DcInterrupt); when x"1C09" => if OTG_DcInterrupt(7)='1' then jump(x"1C06"); else ret_sub; end if; --GO_SUB(x"1D00");ctrlOut_handler --handles an interrupt by ctrlOut when x"1D00" => go_sub(sub_get_esr); nAX <= Rd_ESR & ctrlOut; when x"1D01" => if AL(2)='1' and AL(3)='0' and AL(5)='1' then --setup packet ready go_sub(sub_rcv_setup); else --error ret_sub; end if; when x"1D02" => case w_ctrl_xfer.bRequest is when GET_DESCRIPTOR => case w_ctrl_xfer.wValue(15 downto 8) is when desc_DEVICE => if (w_ctrl_xfer.bmRequestType=x"80" and w_ctrl_xfer.wIndex=x"0000" and w_ctrl_xfer.wValue(7 downto 0)=x"00" ) then port_dump(ctrlIn,byte_deviceDescriptor(CRD_devDesc),w_ctrl_xfer.wLength); else go_sub(sub_port_out_cmd); nAX <= Stall & ctrlIn; end if; when desc_STRING => ledg(7)<='1'; case w_ctrl_xfer.wValue(7 downto 0) is when x"00" => port_dump(ctrlIn,CRD_strDesc_00_Langs,w_ctrl_xfer.wLength); when x"01" => if w_ctrl_xfer.wIndex = x"0409" then port_dump(ctrlIn,CRD_strDesc_01_Vendor); else go_sub(sub_port_out_cmd); nAX <= Stall & ctrlIn; end if; when x"02" => if w_ctrl_xfer.wIndex = x"0409" then port_dump(ctrlIn,CRD_strDesc_02_Product,w_ctrl_xfer.wLength); else go_sub(sub_port_out_cmd); nAX <= Stall & ctrlIn; end if; when x"03" => if w_ctrl_xfer.wIndex = x"0409" then port_dump(ctrlIn,CRD_strDesc_03_Serial,w_ctrl_xfer.wLength); else go_sub(sub_port_out_cmd); nAX <= Stall & ctrlIn; end if; when others => --CRD_strDesc_03_Serial go_sub(sub_port_out_cmd); nAX <= Stall & ctrlIn; end case; when desc_CONFIGURATION => if w_ctrl_xfer.wValue(7 downto 0) = x"00" then -- port_dump(ctrlIn,CRD_Full_Cfg_Desc,w_ctrl_xfer.wLength); port_dump(ctrlIn,CRD_Full_Cfg1_Desc,w_ctrl_xfer.wLength); elsif w_ctrl_xfer.wValue(7 downto 0) = x"01" then port_dump(ctrlIn,CRD_Full_Cfg2_Desc,w_ctrl_xfer.wLength); else go_sub(sub_port_out_cmd); nAX <= Stall & ctrlIn; end if; when others => go_sub(sub_port_out_cmd); nAX <= Stall & ctrlIn; end case; when SET_ADDRESS => if e_state = configured then ret_sub; else go_sub(sub_SET_ADDRESS); end if; when SET_CONFIGURATION => if e_state = default then ret_sub; elsif w_ctrl_xfer.wValue = x"0000" then e_state <= address; port_dump(ctrlIn,x"0000",x"0000"); elsif w_ctrl_xfer.wValue = x"0001" or w_ctrl_xfer.wValue = x"0002" then what_config<=w_ctrl_xfer.wValue(7 downto 0); go_sub(sub_configureEps_n_ack); else go_sub(sub_port_out_cmd); nAX <= Stall & ctrlIn; end if; when GET_STATUS => if e_state = default then ret_sub; elsif w_ctrl_xfer.bmRequestType = x"80" then port_dump(ctrlIn, x"0001"); elsif w_ctrl_xfer.bmRequestType = x"81" and w_ctrl_xfer.wIndex = x"0000" then port_dump(ctrlIn, x"0000"); elsif ((e_state=address and w_ctrl_xfer.wIndex = x"0000") or (e_state = configured)) and (w_ctrl_xfer.bmRequestType=x"82") then go_sub(sub_sendEpStatus); else go_sub(sub_port_out_cmd); nAX <= Stall & ctrlIn; end if; when CLEAR_FEATURE => if e_state = default then ret_sub; elsif (w_ctrl_xfer.bmRequestType = x"02") and (w_ctrl_xfer.wValue=x"0000") then case(w_ctrl_xfer.wIndex(7 downto 0)) is when x"80"|x"00"=> --ctrlInOut nAX <=(Unstall & ctrlIn); when x"81" => --ep1 nAX <=(Unstall & ep1); when x"02" => --ep2 nAX <=(Unstall & ep2); when x"83" => --ep3 nAX <=(Unstall & ep3); when x"04" => --ep4 nAX <=(Unstall & ep4); when x"85" => --ep5 nAX <=(Unstall & ep5); when others => --unsupported or error nAX <=(Stall & ctrlIn); end case; go_sub(sub_port_out_cmd); else nAX <=(Stall & ctrlIn); go_sub(sub_port_out_cmd); end if; --NEED TO ACK AFTER SET AND CLEAR FEATURES!!!!!!!!!!1 when SET_FEATURE => if e_state = default then ret_sub; elsif (w_ctrl_xfer.bmRequestType = x"02") and (w_ctrl_xfer.wValue=x"0000") then case(w_ctrl_xfer.wIndex(7 downto 0)) is when x"81" => --ep1 nAX <=(Stall & ep1); when x"02" => --ep2 nAX <=(Stall & ep2); when x"83" => --ep3 nAX <=(Stall & ep3); when x"04" => --ep4 nAX <=(Stall & ep4); when x"85" => --ep5 nAX <=(Stall & ep5); when others => --unsupported or error nAX <=(Stall & ctrlIn); end case; go_sub(sub_port_out_cmd); else nAX <=(Stall & ctrlIn); go_sub(sub_port_out_cmd); end if; when GET_CONFIGURATION => if e_state = default then ret_sub; elsif e_state = address then port_dump(ctrlIn,x"00"); elsif e_state = configured then port_dump(ctrlIn,what_config); end if; when GET_INTERFACE|SET_INTERFACE => if (e_state=address)or((w_ctrl_xfer.wIndex(7 downto 0)/=x"00")) then nAX<=(Stall & ctrlIn); go_sub(sub_port_out_cmd); else if w_ctrl_xfer.bRequest = GET_INTERFACE then w_length<=x"0001"; loadBuffer(x"00"&which_interface); elsif w_ctrl_xfer.wValue(7 downto 1) = "0000000" then which_interface <= w_ctrl_xfer.wValue(7 downto 0); w_length<= x"0000"; go_sub(sub_send_data); else nAX<=(Stall & ctrlIn); go_sub(sub_port_out_cmd); end if; end if; when others => jump(x"FFFF");--LOCK UP and display unrecognized request end case; when x"1D03" => ret_sub; --GO_SUB(x"");get_ESR --reads an ESR specified by command in AL into its corresponding OTG_ESR register and AL when x"1E00" => --7:stall 6:2ndary full 5:primary full 4:PID 3:missed_setup go home 2:setup_pkt 1:2ndary selected 0:none go_sub(sub_port_out_cmd); nBX <= AX; when x"1E01" => go_sub(sub_port_in); when x"1E02" => OTG_ESR(to_integer(unsigned(BL(3 downto 0))))<= AL; ret_sub; --GO_SUB(x"1F00");sub_SET_ADDRESS when x"1F00" => if e_state = configured then ret_sub; else go_sub(sub_port_out_cmd); nAX <= Wr_DcAddress; end if; when x"1F01" => go_sub(sub_port_out); nAX <= x"0080" or w_ctrl_xfer.wValue; if w_ctrl_xfer.wValue = x"0000" then e_state <= default; else e_state <= address; end if; when x"1F02" => nAX <= Wr_Buffer & ctrlIn; go_sub(sub_port_out_cmd); when x"1F03" => nAX <= x"0000"; go_sub(sub_port_out); when x"1F04" => nAX <= Validate & ctrlIn; go_sub(sub_port_out_cmd); when x"1F05" => ret_sub; --GO_SUB(x"2000");sub_configureEps_n_ack when x"2000" => go_sub(sub_port_out_cmd); nAX <= Wr_DcEndpointConfiguration & ctrlOut; when x"2001" => go_sub(sub_port_out); nAL <= DcEndpointConfiguration(0); when x"2002" => go_sub(sub_port_out_cmd); nAX <= Wr_DcEndpointConfiguration & ctrlIn; when x"2003" => go_sub(sub_port_out); nAL <= DcEndpointConfiguration(1); when x"2004" => go_sub(sub_port_out_cmd); nAX <= Wr_DcEndpointConfiguration & ep1; when x"2005" => go_sub(sub_port_out); nAL <= DcEndpointConfiguration(2); when x"2006" => go_sub(sub_port_out_cmd); nAX <= Wr_DcEndpointConfiguration & ep2; when x"2007" => go_sub(sub_port_out); nAL <= DcEndpointConfiguration(3); when x"2008" => go_sub(sub_port_out_cmd); nAX <= Wr_DcEndpointConfiguration & ep3; when x"2009" => go_sub(sub_port_out); nAL <= DcEndpointConfiguration(4); when x"200A" => go_sub(sub_port_out_cmd); nAX <= Wr_DcEndpointConfiguration & ep4; when x"200B" => go_sub(sub_port_out); nAL <= DcEndpointConfiguration(5); when x"200C" => go_sub(sub_port_out_cmd); nAX <= Wr_DcEndpointConfiguration & ep5; when x"200D" => go_sub(sub_port_out); nAL <= DcEndpointConfiguration(6); when x"200E" => go_sub(sub_port_out_cmd); nAX <= Wr_DcEndpointConfiguration & ep6; when x"200F" => go_sub(sub_port_out); nAL <= DcEndpointConfiguration(7); when x"2010" => go_sub(sub_port_out_cmd); nAX <= Wr_DcEndpointConfiguration & ep7; when x"2011" => go_sub(sub_port_out); nAL <= DcEndpointConfiguration(8); when x"2012" => go_sub(sub_port_out_cmd); nAX <= Wr_DcEndpointConfiguration & ep8; when x"2013" => go_sub(sub_port_out); nAL <= DcEndpointConfiguration(9); when x"2014" => go_sub(sub_port_out_cmd); nAX <= Wr_DcEndpointConfiguration & ep9; when x"2015" => go_sub(sub_port_out); nAL <= DcEndpointConfiguration(10); when x"2016" => go_sub(sub_port_out_cmd); nAX <= Wr_DcEndpointConfiguration & ep10; when x"2017" => go_sub(sub_port_out); nAL <= DcEndpointConfiguration(11); when x"2018" => go_sub(sub_port_out_cmd); nAX <= Wr_DcEndpointConfiguration & ep11; when x"2019" => go_sub(sub_port_out); nAL <= DcEndpointConfiguration(12); when x"201A" => go_sub(sub_port_out_cmd); nAX <= Wr_DcEndpointConfiguration & ep12; when x"201B" => go_sub(sub_port_out); nAL <= DcEndpointConfiguration(13); when x"201C" => go_sub(sub_port_out_cmd); nAX <= Wr_DcEndpointConfiguration & ep13; when x"201D" => go_sub(sub_port_out); nAL <= DcEndpointConfiguration(14); when x"201E" => go_sub(sub_port_out_cmd); nAX <= Wr_DcEndpointConfiguration & ep14; when x"201F" => go_sub(sub_port_out); nAL <= DcEndpointConfiguration(15); when x"2020" => e_state <= configured; port_dump(ctrlIn,x"0000",x"0000"); when x"2021" => ret_sub; --GO_SUB(x"2200");sub_sendEpStatus when x"2200" => case w_ctrl_xfer.windex(7 downto 0) is when x"80"|x"00"=> --ctrlInOut go_sub(sub_port_out_cmd); nAX <= (Rd_DcEndpointStatusImage & ctrlIn); when x"81" => --ep1 go_sub(sub_port_out_cmd); nAX <= (Rd_DcEndpointStatusImage & ep1); when x"02" => --ep2 go_sub(sub_port_out_cmd); nAX <= (Rd_DcEndpointStatusImage & ep2); when x"83" => --ep3 go_sub(sub_port_out_cmd); nAX <= (Rd_DcEndpointStatusImage & ep3); when x"04" => --ep4 go_sub(sub_port_out_cmd); nAX <= (Rd_DcEndpointStatusImage & ep4); when x"85" => --ep5 go_sub(sub_port_out_cmd); nAX <= (Rd_DcEndpointStatusImage & ep5); when others => --unsupported or error jump(x"2210"); end case; when x"2201" => go_sub(sub_send_data); w_length<=x"0002"; loadBuffer(x"000"&"000"&AL(7)); when x"2202" => ret_sub; when x"2203" => when x"2204" => when x"2205" => when x"2206" => when x"2207" => when x"2208" => when x"2209" => when x"220A" => when x"220B" => when x"220C" => when x"220D" => when x"220E" => when x"220F" => when x"2210" => go_sub(sub_port_out_cmd); nAX <= (Stall & ctrlIn); when x"2211" => ret_sub; --GO_SUB(x"2300");sub_EP_Int_Handler handles endpoing interrupts OTG_DcInterrupt(14 downto 10)/="00000" when x"2300" => if OTG_DcInterrupt(10)='1' then --EP1 --64b Bulk Out signal EP1_Buffer : buffer64 go_sub(sub_get_esr); nAX <= Rd_ESR & ep1; elsif OTG_DcInterrupt(11)='1' then --EP2 --64b Bulk In signal EP2_Buffer : buffer64 go_sub(sub_get_esr); nAX <= Rd_ESR & ep2; elsif OTG_DcInterrupt(12)='1' then --EP3 --16b Int Out signal EP3_Buffer : buffer16 go_sub(sub_get_esr); nAX <= Rd_ESR & ep3; elsif OTG_DcInterrupt(13)='1' then --EP4 --16b Int In signal EP4_Buffer : buffer16 go_sub(sub_get_esr); nAX <= Rd_ESR & ep4; elsif OTG_DcInterrupt(14)='1' then --EP5 --1023b Iso In (dblBuff) (IMPLEMENT SRAM BUFFER) go_sub(sub_get_esr); nAX <= Rd_ESR & ep5; end if; when x"2301" => if OTG_DcInterrupt(10)='1' then --EP1 --64b Bulk Out signal EP1_Buffer : buffer64 if AX(5)='1' then go_sub(x"2310"); else ret_sub; end if; elsif OTG_DcInterrupt(11)='1' then --EP2 --64b Bulk In signal EP2_Buffer : buffer64 if AX(5)='0' then port_dump(ep2,EP2_Buffer); else ret_sub; end if; elsif OTG_DcInterrupt(12)='1' then --EP3 --16b Int Out signal EP3_Buffer : buffer16 if AX(5)='1' then go_sub(x"2320"); else ret_sub; end if; elsif OTG_DcInterrupt(13)='1' then --EP4 --16b Int In signal EP4_Buffer : buffer16 if AX(5)='0' then port_dump(ep4,EP4_Buffer); else ret_sub; end if; elsif OTG_DcInterrupt(14)='1' then --EP5 --1023b Iso In (dblBuff) (IMPLEMENT SRAM BUFFER) if AX(5)='0' then port_dump(ep5,EP2_Buffer); else ret_sub; end if; end if; when x"2302" => ret_sub; when x"2303" => when x"2304" => when x"2310" => nAX <= Rd_Buffer & ep1; go_sub(sub_port_out_cmd); when x"2311" => go_sub(sub_port_in); --read length when x"2312" => nCX <= to_vec(16,((to_int(AX)+1) / 2));--num words to read nBX <= x"0000"; when x"2313" => go_sub(sub_port_in); --THIS COULD BE IMPLEMENTED WAAAAAAAY FASTER (like sub_send_data) when x"2314" => EP1_Buff(to_int(BX))<=AX; --signal EP1_Buffer : buffer64 nBX<=to_vec(16,to_int(BX)+1); loopJump(x"2313"); when x"2315" => go_sub(sub_port_out_cmd); nAX <= ClearBuffer & ep1; when x"2316" => ret_sub; when x"2320" => nAX <= Rd_Buffer & ep3; go_sub(sub_port_out_cmd); when x"2321" => go_sub(sub_port_in); --read length when x"2322" => nCX <= to_vec(16,((to_int(AX)+1) / 2));--num words to read nBX <= x"0000"; when x"2323" => go_sub(sub_port_in); --THIS COULD BE IMPLEMENTED WAAAAAAAY FASTER (like sub_send_data) when x"2324" => EP3_Buff(to_int(BX))<=AX; --signal EP3_Buffer : buffer16 nBX<=to_vec(16,to_int(BX)+1); loopJump(x"2313"); when x"2325" => go_sub(sub_port_out_cmd); nAX <= ClearBuffer & ep3; when x"2326" => ret_sub; when x"2400" => when x"2401" => when x"2402" => when x"2403" => when x"2404" => when x"2405" => when x"2406" => when x"2407" => when x"2408" => when x"2409" => when x"240A" => when x"240B" => when x"240C" => when x"240D" => when x"240E" => when x"240F" => when x"2500" => when x"2501" => when x"2502" => when x"2503" => when x"2504" => when x"2505" => when x"2506" => when x"2507" => when x"2508" => when x"2509" => when x"250A" => when x"250B" => when x"250C" => when x"250D" => when x"250E" => when x"250F" => when x"2600" => when x"2601" => when x"2602" => when x"2603" => when x"2604" => when x"2605" => when x"2606" => when x"2607" => when x"2608" => when x"2609" => when x"260A" => when x"260B" => when x"260C" => when x"260D" => when x"260E" => when x"260F" => when x"2700" => when x"2701" => when x"2702" => when x"2703" => when x"2704" => when x"2705" => when x"2706" => when x"2707" => when x"2708" => when x"2709" => when x"270A" => when x"270B" => when x"270C" => when x"270D" => when x"270E" => when x"270F" => when x"FFFF" => jump(x"FFFF"); when others => jump(IP); end case; end if; end process worker; end handler;
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Reproducer: Experiments on custom attributes ended in a crash. -- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= -- -- Issue: -- I'm not sure if my experimental code is allowed in VHDL, but it let GHDL -- crash. So I'm reporting just an unhandled exception. -- -- GHDL's output is: -- .\attribute.vhdl:64:58: can't match 'image attribute with type character -- .\attribute.vhdl:64:53: (location of 'image attribute) -- finish_sem_name: cannot handle IIR_KIND_OVERLOAD_LIST (??:??:??) -- -- ******************** GHDL Bug occurred **************************** -- Please report this bug on https://github.com/tgingold/ghdl/issues -- GHDL release: GHDL 0.34dev (commit: 2016-02-11; git branch: paebbels/master'; hash: f24fdfb) [Dunoon edition] -- Compiled with GNAT Version: GPL 2015 (20150428-49) -- In directory: H:\Austausch\PoC\temp\ghdl\ -- Command line: -- C:\Tools\GHDL.new\bin\ghdl.exe -a --std=08 .\attribute.vhdl -- Exception TYPES.INTERNAL_ERROR raised -- Exception information: -- Exception name: TYPES.INTERNAL_ERROR -- Message: errorout.adb:66 -- ****************************************************************** -- -- GHDL calls: -- PS> ghdl.exe -a --std=93c .\attribute.vhdl -- PS> ghdl.exe -a --std=08 .\attribute.vhdl -- library IEEE; use IEEE.std_logic_1164.all; entity test is end entity; architecture tb of test is function to_string(slv : STD_LOGIC_VECTOR) return STRING is variable Result : STRING(slv'length - 1 downto 0); begin for i in slv'range loop Result(i + 1) := STD_LOGIC'image(slv(i)); end loop; return Result; end function; attribute serialize : to_string; signal mySignal : STD_LOGIC_VECTOR(7 downto 0); attribute serialize of mySignal : signal is to_string[STD_LOGIC_VECTOR return STRING]; begin mySignal <= x"24"; process begin report "mySignal=" & mySignal'serialize severity NOTE; wait; end process; end architecture;
------------------------------------------------------------------------------- -- Entity : OpenMAC_DMAFifo_Xilinx ------------------------------------------------------------------------------- -- -- (c) B&R, 2012 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact office@br-automation.com -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity openMAC_DMAfifo is generic( fifo_data_width_g : NATURAL := 16; fifo_word_size_g : NATURAL := 32; fifo_word_size_log2_g : NATURAL := 5 ); port( aclr : in std_logic; rd_clk : in std_logic; rd_req : in std_logic; wr_clk : in std_logic; wr_req : in std_logic; wr_data : in std_logic_vector(fifo_data_width_g - 1 downto 0); rd_empty : out std_logic; rd_full : out std_logic; wr_empty : out std_logic; wr_full : out std_logic; rd_data : out std_logic_vector(fifo_data_width_g - 1 downto 0); rd_usedw : out std_logic_vector(fifo_word_size_log2_g - 1 downto 0); wr_usedw : out std_logic_vector(fifo_word_size_log2_g - 1 downto 0) ); end openMAC_DMAfifo; architecture struct of openMAC_DMAfifo is ---- Component declarations ----- component async_fifo_ctrl generic( ADDR_WIDTH : natural := 5 ); port ( clkr : in std_logic; clkw : in std_logic; rd : in std_logic; resetr : in std_logic; resetw : in std_logic; wr : in std_logic; r_addr : out std_logic_vector(ADDR_WIDTH-1 downto 0); r_empty : out std_logic; r_full : out std_logic; rd_used_w : out std_logic_vector(ADDR_WIDTH-1 downto 0); w_addr : out std_logic_vector(ADDR_WIDTH-1 downto 0); w_empty : out std_logic; w_full : out std_logic; wd_used_w : out std_logic_vector(ADDR_WIDTH-1 downto 0) ); end component; component dc_dpr generic( ADDRWIDTH : integer := 7; WIDTH : integer := 16 ); port ( addrA : in std_logic_vector(ADDRWIDTH-1 downto 0); addrB : in std_logic_vector(ADDRWIDTH-1 downto 0); clkA : in std_logic; clkB : in std_logic; diA : in std_logic_vector(WIDTH-1 downto 0); diB : in std_logic_vector(WIDTH-1 downto 0); enA : in std_logic; enB : in std_logic; weA : in std_logic; weB : in std_logic; doA : out std_logic_vector(WIDTH-1 downto 0); doB : out std_logic_vector(WIDTH-1 downto 0) ); end component; ---- Signal declarations used on the diagram ---- signal enA : std_logic; signal enB : std_logic; signal wea : std_logic; signal weB : std_logic; signal wr_full_s : std_logic; signal diB : std_logic_vector (fifo_data_width_g-1 downto 0); signal rd_addr : std_logic_vector (fifo_word_size_log2_g-1 downto 0); signal wr_addr : std_logic_vector (fifo_word_size_log2_g-1 downto 0); begin ---- User Signal Assignments ---- --assignments ---port a writes only enA <= wea; ---port b reads only enB <= rd_req; weB <= '0'; diB <= (others => '0'); ---- Component instantiations ---- THE_FIFO_CONTROL : async_fifo_ctrl generic map ( ADDR_WIDTH => fifo_word_size_log2_g ) port map( clkr => rd_clk, clkw => wr_clk, r_addr => rd_addr( fifo_word_size_log2_g-1 downto 0 ), r_empty => rd_empty, r_full => rd_full, rd => rd_req, rd_used_w => rd_usedw( fifo_word_size_log2_g - 1 downto 0 ), resetr => aclr, resetw => aclr, w_addr => wr_addr( fifo_word_size_log2_g-1 downto 0 ), w_empty => wr_empty, w_full => wr_full_s, wd_used_w => wr_usedw( fifo_word_size_log2_g - 1 downto 0 ), wr => wr_req ); THE_FIFO_DPR : dc_dpr generic map ( ADDRWIDTH => fifo_word_size_log2_g, WIDTH => fifo_data_width_g ) port map( addrA => wr_addr( fifo_word_size_log2_g-1 downto 0 ), addrB => rd_addr( fifo_word_size_log2_g-1 downto 0 ), clkA => wr_clk, clkB => rd_clk, diA => wr_data( fifo_data_width_g - 1 downto 0 ), diB => diB( fifo_data_width_g-1 downto 0 ), doB => rd_data( fifo_data_width_g - 1 downto 0 ), enA => enA, enB => enB, weA => wea, weB => weB ); wea <= not(wr_full_s) and wr_req; ---- Terminal assignment ---- -- Output\buffer terminals wr_full <= wr_full_s; end struct;
------------------------------------------------------------------------------- -- Entity : OpenMAC_DMAFifo_Xilinx ------------------------------------------------------------------------------- -- -- (c) B&R, 2012 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact office@br-automation.com -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity openMAC_DMAfifo is generic( fifo_data_width_g : NATURAL := 16; fifo_word_size_g : NATURAL := 32; fifo_word_size_log2_g : NATURAL := 5 ); port( aclr : in std_logic; rd_clk : in std_logic; rd_req : in std_logic; wr_clk : in std_logic; wr_req : in std_logic; wr_data : in std_logic_vector(fifo_data_width_g - 1 downto 0); rd_empty : out std_logic; rd_full : out std_logic; wr_empty : out std_logic; wr_full : out std_logic; rd_data : out std_logic_vector(fifo_data_width_g - 1 downto 0); rd_usedw : out std_logic_vector(fifo_word_size_log2_g - 1 downto 0); wr_usedw : out std_logic_vector(fifo_word_size_log2_g - 1 downto 0) ); end openMAC_DMAfifo; architecture struct of openMAC_DMAfifo is ---- Component declarations ----- component async_fifo_ctrl generic( ADDR_WIDTH : natural := 5 ); port ( clkr : in std_logic; clkw : in std_logic; rd : in std_logic; resetr : in std_logic; resetw : in std_logic; wr : in std_logic; r_addr : out std_logic_vector(ADDR_WIDTH-1 downto 0); r_empty : out std_logic; r_full : out std_logic; rd_used_w : out std_logic_vector(ADDR_WIDTH-1 downto 0); w_addr : out std_logic_vector(ADDR_WIDTH-1 downto 0); w_empty : out std_logic; w_full : out std_logic; wd_used_w : out std_logic_vector(ADDR_WIDTH-1 downto 0) ); end component; component dc_dpr generic( ADDRWIDTH : integer := 7; WIDTH : integer := 16 ); port ( addrA : in std_logic_vector(ADDRWIDTH-1 downto 0); addrB : in std_logic_vector(ADDRWIDTH-1 downto 0); clkA : in std_logic; clkB : in std_logic; diA : in std_logic_vector(WIDTH-1 downto 0); diB : in std_logic_vector(WIDTH-1 downto 0); enA : in std_logic; enB : in std_logic; weA : in std_logic; weB : in std_logic; doA : out std_logic_vector(WIDTH-1 downto 0); doB : out std_logic_vector(WIDTH-1 downto 0) ); end component; ---- Signal declarations used on the diagram ---- signal enA : std_logic; signal enB : std_logic; signal wea : std_logic; signal weB : std_logic; signal wr_full_s : std_logic; signal diB : std_logic_vector (fifo_data_width_g-1 downto 0); signal rd_addr : std_logic_vector (fifo_word_size_log2_g-1 downto 0); signal wr_addr : std_logic_vector (fifo_word_size_log2_g-1 downto 0); begin ---- User Signal Assignments ---- --assignments ---port a writes only enA <= wea; ---port b reads only enB <= rd_req; weB <= '0'; diB <= (others => '0'); ---- Component instantiations ---- THE_FIFO_CONTROL : async_fifo_ctrl generic map ( ADDR_WIDTH => fifo_word_size_log2_g ) port map( clkr => rd_clk, clkw => wr_clk, r_addr => rd_addr( fifo_word_size_log2_g-1 downto 0 ), r_empty => rd_empty, r_full => rd_full, rd => rd_req, rd_used_w => rd_usedw( fifo_word_size_log2_g - 1 downto 0 ), resetr => aclr, resetw => aclr, w_addr => wr_addr( fifo_word_size_log2_g-1 downto 0 ), w_empty => wr_empty, w_full => wr_full_s, wd_used_w => wr_usedw( fifo_word_size_log2_g - 1 downto 0 ), wr => wr_req ); THE_FIFO_DPR : dc_dpr generic map ( ADDRWIDTH => fifo_word_size_log2_g, WIDTH => fifo_data_width_g ) port map( addrA => wr_addr( fifo_word_size_log2_g-1 downto 0 ), addrB => rd_addr( fifo_word_size_log2_g-1 downto 0 ), clkA => wr_clk, clkB => rd_clk, diA => wr_data( fifo_data_width_g - 1 downto 0 ), diB => diB( fifo_data_width_g-1 downto 0 ), doB => rd_data( fifo_data_width_g - 1 downto 0 ), enA => enA, enB => enB, weA => wea, weB => weB ); wea <= not(wr_full_s) and wr_req; ---- Terminal assignment ---- -- Output\buffer terminals wr_full <= wr_full_s; end struct;
entity case8 is end entity; library ieee; use ieee.std_logic_1164.all; architecture test of case8 is function toint32(b : std_logic_vector(31 downto 0)) return integer is begin -- This uses a non-exact case map as 4*32 > 64 case b is when X"00000000" => return 0; when X"00000100" => return 1; when X"00000101" => return 2; when X"00000011" => return 3; when X"00001001" => return 4; when X"00004141" => return 5; when X"00002521" => return 6; when X"10005211" => return 7; when X"ffff0001" => return 8; when X"ffff1000" => return 9; when X"ffff52af" => return 10; when X"ffffffff" => return 11; when X"ffffabcd" => return 12; when X"ffffabed" => return 13; when X"ffff1415" => return 14; when X"ffff5252" => return 15; -- These two have hash collisions when "LHH-HWUL-LHZ0UHH01WXXWXUUZX-WXUU" => return 555; when "0X0L0WWUHLX0Z1Z-L---L-LXZ0UHZ-0Z" => return 666; when others => return -1; end case; end function; begin process is variable b : std_logic_vector(31 downto 0); begin assert toint32(X"00000000") = 0; b := X"00004141"; assert toint32(b) = 5; b := X"00001001"; assert toint32(b) = 4; b := X"00000101"; assert toint32(b) = 2; b := X"abab1101"; assert toint32(b) = -1; b := X"ffff52af"; assert toint32(b) = 10; b := X"ffff52ae"; assert toint32(b) = -1; -- The following three cases all hash to the same value b := "LHH-HWUL-LHZ0UHH01WXXWXUUZX-WXUU"; assert toint32(b) = 555; b := "0X0L0WWUHLX0Z1Z-L---L-LXZ0UHZ-0Z"; assert toint32(b) = 666; b := "Z-LXHW0XH-0W1111ZXWW1XLLZULX-HU1"; assert toint32(b) = -1; wait; end process; end architecture;
-- wasca.vhd -- Generated using ACDS version 15.0 145 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity wasca is port ( altpll_0_areset_conduit_export : in std_logic := '0'; -- altpll_0_areset_conduit.export altpll_0_locked_conduit_export : out std_logic; -- altpll_0_locked_conduit.export altpll_0_phasedone_conduit_export : out std_logic; -- altpll_0_phasedone_conduit.export audio_out_BCLK : in std_logic := '0'; -- audio_out.BCLK audio_out_DACDAT : out std_logic; -- .DACDAT audio_out_DACLRCK : in std_logic := '0'; -- .DACLRCK clk_clk : in std_logic := '0'; -- clk.clk clock_116_mhz_clk : out std_logic; -- clock_116_mhz.clk external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n external_sdram_controller_wire_cke : out std_logic; -- .cke external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n external_sdram_controller_wire_we_n : out std_logic; -- .we_n sega_saturn_abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- sega_saturn_abus_slave_0_abus.address sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect sega_saturn_abus_slave_0_abus_read : in std_logic := '0'; -- .read sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest sega_saturn_abus_slave_0_abus_interrupt : out std_logic; -- .interrupt sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .addressdata sega_saturn_abus_slave_0_abus_direction : out std_logic; -- .direction sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- .muxing sega_saturn_abus_slave_0_abus_disableout : out std_logic; -- .disableout sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := '0'; -- sega_saturn_abus_slave_0_conduit_saturn_reset.saturn_reset spi_sd_card_MISO : in std_logic := '0'; -- spi_sd_card.MISO spi_sd_card_MOSI : out std_logic; -- .MOSI spi_sd_card_SCLK : out std_logic; -- .SCLK spi_sd_card_SS_n : out std_logic; -- .SS_n spi_stm32_MISO : out std_logic; -- spi_stm32.MISO spi_stm32_MOSI : in std_logic := '0'; -- .MOSI spi_stm32_SCLK : in std_logic := '0'; -- .SCLK spi_stm32_SS_n : in std_logic := '0'; -- .SS_n uart_0_external_connection_rxd : in std_logic := '0'; -- uart_0_external_connection.rxd uart_0_external_connection_txd : out std_logic -- .txd ); end entity wasca; architecture rtl of wasca is component wasca_altpll_0 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset read : in std_logic := 'X'; -- read write : in std_logic := 'X'; -- write address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address readdata : out std_logic_vector(31 downto 0); -- readdata writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata c0 : out std_logic; -- clk areset : in std_logic := 'X'; -- export c1 : out std_logic; -- export locked : out std_logic; -- export phasedone : out std_logic -- export ); end component wasca_altpll_0; component wasca_audio_0 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address chipselect : in std_logic := 'X'; -- chipselect read : in std_logic := 'X'; -- read write : in std_logic := 'X'; -- write writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata readdata : out std_logic_vector(31 downto 0); -- readdata irq : out std_logic; -- irq AUD_BCLK : in std_logic := 'X'; -- export AUD_DACDAT : out std_logic; -- export AUD_DACLRCK : in std_logic := 'X' -- export ); end component wasca_audio_0; component wasca_external_sdram_controller is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n az_addr : in std_logic_vector(23 downto 0) := (others => 'X'); -- address az_be_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable_n az_cs : in std_logic := 'X'; -- chipselect az_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata az_rd_n : in std_logic := 'X'; -- read_n az_wr_n : in std_logic := 'X'; -- write_n za_data : out std_logic_vector(15 downto 0); -- readdata za_valid : out std_logic; -- readdatavalid za_waitrequest : out std_logic; -- waitrequest zs_addr : out std_logic_vector(12 downto 0); -- export zs_ba : out std_logic_vector(1 downto 0); -- export zs_cas_n : out std_logic; -- export zs_cke : out std_logic; -- export zs_cs_n : out std_logic; -- export zs_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export zs_dqm : out std_logic_vector(1 downto 0); -- export zs_ras_n : out std_logic; -- export zs_we_n : out std_logic -- export ); end component wasca_external_sdram_controller; component wasca_nios2_gen2_0 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n d_address : out std_logic_vector(26 downto 0); -- address d_byteenable : out std_logic_vector(3 downto 0); -- byteenable d_read : out std_logic; -- read d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata d_waitrequest : in std_logic := 'X'; -- waitrequest d_write : out std_logic; -- write d_writedata : out std_logic_vector(31 downto 0); -- writedata debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess i_address : out std_logic_vector(26 downto 0); -- address i_read : out std_logic; -- read i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata i_waitrequest : in std_logic := 'X'; -- waitrequest irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq debug_reset_request : out std_logic; -- reset debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess debug_mem_slave_read : in std_logic := 'X'; -- read debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata debug_mem_slave_waitrequest : out std_logic; -- waitrequest debug_mem_slave_write : in std_logic := 'X'; -- write debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata dummy_ci_port : out std_logic -- readra ); end component wasca_nios2_gen2_0; component altera_onchip_flash is generic ( INIT_FILENAME : string := ""; INIT_FILENAME_SIM : string := ""; DEVICE_FAMILY : string := "Unknown"; PART_NAME : string := "Unknown"; DEVICE_ID : string := "Unknown"; SECTOR1_START_ADDR : integer := 0; SECTOR1_END_ADDR : integer := 0; SECTOR2_START_ADDR : integer := 0; SECTOR2_END_ADDR : integer := 0; SECTOR3_START_ADDR : integer := 0; SECTOR3_END_ADDR : integer := 0; SECTOR4_START_ADDR : integer := 0; SECTOR4_END_ADDR : integer := 0; SECTOR5_START_ADDR : integer := 0; SECTOR5_END_ADDR : integer := 0; MIN_VALID_ADDR : integer := 0; MAX_VALID_ADDR : integer := 0; MIN_UFM_VALID_ADDR : integer := 0; MAX_UFM_VALID_ADDR : integer := 0; SECTOR1_MAP : integer := 0; SECTOR2_MAP : integer := 0; SECTOR3_MAP : integer := 0; SECTOR4_MAP : integer := 0; SECTOR5_MAP : integer := 0; ADDR_RANGE1_END_ADDR : integer := 0; ADDR_RANGE1_OFFSET : integer := 0; ADDR_RANGE2_OFFSET : integer := 0; AVMM_DATA_ADDR_WIDTH : integer := 19; AVMM_DATA_DATA_WIDTH : integer := 32; AVMM_DATA_BURSTCOUNT_WIDTH : integer := 4; SECTOR_READ_PROTECTION_MODE : integer := 31; FLASH_SEQ_READ_DATA_COUNT : integer := 2; FLASH_ADDR_ALIGNMENT_BITS : integer := 1; FLASH_READ_CYCLE_MAX_INDEX : integer := 4; FLASH_RESET_CYCLE_MAX_INDEX : integer := 29; FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX : integer := 112; FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX : integer := 40603248; FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX : integer := 35382; PARALLEL_MODE : boolean := true; READ_AND_WRITE_MODE : boolean := true; WRAPPING_BURST_MODE : boolean := false; IS_DUAL_BOOT : string := "False"; IS_ERAM_SKIP : string := "False"; IS_COMPRESSED_IMAGE : string := "False" ); port ( clock : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n avmm_data_addr : in std_logic_vector(15 downto 0) := (others => 'X'); -- address avmm_data_read : in std_logic := 'X'; -- read avmm_data_readdata : out std_logic_vector(31 downto 0); -- readdata avmm_data_waitrequest : out std_logic; -- waitrequest avmm_data_readdatavalid : out std_logic; -- readdatavalid avmm_data_burstcount : in std_logic_vector(3 downto 0) := (others => 'X'); -- burstcount avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata avmm_data_write : in std_logic := 'X'; -- write avmm_csr_addr : in std_logic := 'X'; -- address avmm_csr_read : in std_logic := 'X'; -- read avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata avmm_csr_write : in std_logic := 'X'; -- write avmm_csr_readdata : out std_logic_vector(31 downto 0) -- readdata ); end component altera_onchip_flash; component wasca_onchip_memory2_0 is port ( clk : in std_logic := 'X'; -- clk address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address clken : in std_logic := 'X'; -- clken chipselect : in std_logic := 'X'; -- chipselect write : in std_logic := 'X'; -- write readdata : out std_logic_vector(31 downto 0); -- readdata writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable reset : in std_logic := 'X'; -- reset reset_req : in std_logic := 'X' -- reset_req ); end component wasca_onchip_memory2_0; component sega_saturn_abus_slave is port ( clock : in std_logic := 'X'; -- clk abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect abus_read : in std_logic := 'X'; -- read abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write abus_waitrequest : out std_logic; -- waitrequest abus_interrupt : out std_logic; -- interrupt abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata abus_direction : out std_logic; -- direction abus_muxing : out std_logic_vector(1 downto 0); -- muxing abus_disable_out : out std_logic; -- disableout avalon_read : out std_logic; -- read avalon_write : out std_logic; -- write avalon_waitrequest : in std_logic := 'X'; -- waitrequest avalon_address : out std_logic_vector(27 downto 0); -- address avalon_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata avalon_writedata : out std_logic_vector(15 downto 0); -- writedata avalon_readdatavalid : in std_logic := 'X'; -- readdatavalid avalon_burstcount : out std_logic; -- burstcount reset : in std_logic := 'X'; -- reset saturn_reset : in std_logic := 'X'; -- saturn_reset avalon_nios_read : in std_logic := 'X'; -- read avalon_nios_write : in std_logic := 'X'; -- write avalon_nios_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata avalon_nios_readdata : out std_logic_vector(15 downto 0); -- readdata avalon_nios_waitrequest : out std_logic; -- waitrequest avalon_nios_readdatavalid : out std_logic; -- readdatavalid avalon_nios_burstcount : in std_logic := 'X' -- burstcount ); end component sega_saturn_abus_slave; component wasca_spi_sd_card is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n data_from_cpu : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata data_to_cpu : out std_logic_vector(15 downto 0); -- readdata mem_addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- address read_n : in std_logic := 'X'; -- read_n spi_select : in std_logic := 'X'; -- chipselect write_n : in std_logic := 'X'; -- write_n irq : out std_logic; -- irq MISO : in std_logic := 'X'; -- export MOSI : out std_logic; -- export SCLK : out std_logic; -- export SS_n : out std_logic -- export ); end component wasca_spi_sd_card; component wasca_spi_stm32 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n data_from_cpu : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata data_to_cpu : out std_logic_vector(15 downto 0); -- readdata mem_addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- address read_n : in std_logic := 'X'; -- read_n spi_select : in std_logic := 'X'; -- chipselect write_n : in std_logic := 'X'; -- write_n irq : out std_logic; -- irq MISO : out std_logic; -- export MOSI : in std_logic := 'X'; -- export SCLK : in std_logic := 'X'; -- export SS_n : in std_logic := 'X' -- export ); end component wasca_spi_stm32; component wasca_uart_0 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address begintransfer : in std_logic := 'X'; -- begintransfer chipselect : in std_logic := 'X'; -- chipselect read_n : in std_logic := 'X'; -- read_n write_n : in std_logic := 'X'; -- write_n writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata readdata : out std_logic_vector(15 downto 0); -- readdata dataavailable : out std_logic; -- dataavailable readyfordata : out std_logic; -- readyfordata rxd : in std_logic := 'X'; -- export txd : out std_logic; -- export irq : out std_logic -- irq ); end component wasca_uart_0; component wasca_mm_interconnect_0 is port ( altpll_0_c0_clk : in std_logic := 'X'; -- clk clk_0_clk_clk : in std_logic := 'X'; -- clk altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset nios2_gen2_0_data_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess nios2_gen2_0_instruction_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata sega_saturn_abus_slave_0_avalon_master_address : in std_logic_vector(27 downto 0) := (others => 'X'); -- address sega_saturn_abus_slave_0_avalon_master_waitrequest : out std_logic; -- waitrequest sega_saturn_abus_slave_0_avalon_master_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount sega_saturn_abus_slave_0_avalon_master_read : in std_logic := 'X'; -- read sega_saturn_abus_slave_0_avalon_master_readdata : out std_logic_vector(15 downto 0); -- readdata sega_saturn_abus_slave_0_avalon_master_readdatavalid : out std_logic; -- readdatavalid sega_saturn_abus_slave_0_avalon_master_write : in std_logic := 'X'; -- write sega_saturn_abus_slave_0_avalon_master_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata altpll_0_pll_slave_address : out std_logic_vector(1 downto 0); -- address altpll_0_pll_slave_write : out std_logic; -- write altpll_0_pll_slave_read : out std_logic; -- read altpll_0_pll_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata altpll_0_pll_slave_writedata : out std_logic_vector(31 downto 0); -- writedata audio_0_avalon_audio_slave_address : out std_logic_vector(1 downto 0); -- address audio_0_avalon_audio_slave_write : out std_logic; -- write audio_0_avalon_audio_slave_read : out std_logic; -- read audio_0_avalon_audio_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata audio_0_avalon_audio_slave_writedata : out std_logic_vector(31 downto 0); -- writedata audio_0_avalon_audio_slave_chipselect : out std_logic; -- chipselect external_sdram_controller_s1_address : out std_logic_vector(23 downto 0); -- address external_sdram_controller_s1_write : out std_logic; -- write external_sdram_controller_s1_read : out std_logic; -- read external_sdram_controller_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata external_sdram_controller_s1_writedata : out std_logic_vector(15 downto 0); -- writedata external_sdram_controller_s1_byteenable : out std_logic_vector(1 downto 0); -- byteenable external_sdram_controller_s1_readdatavalid : in std_logic := 'X'; -- readdatavalid external_sdram_controller_s1_waitrequest : in std_logic := 'X'; -- waitrequest external_sdram_controller_s1_chipselect : out std_logic; -- chipselect nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess onchip_flash_0_data_address : out std_logic_vector(15 downto 0); -- address onchip_flash_0_data_read : out std_logic; -- read onchip_flash_0_data_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata onchip_flash_0_data_burstcount : out std_logic_vector(3 downto 0); -- burstcount onchip_flash_0_data_readdatavalid : in std_logic := 'X'; -- readdatavalid onchip_flash_0_data_waitrequest : in std_logic := 'X'; -- waitrequest onchip_memory2_0_s1_address : out std_logic_vector(11 downto 0); -- address onchip_memory2_0_s1_write : out std_logic; -- write onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect onchip_memory2_0_s1_clken : out std_logic; -- clken sega_saturn_abus_slave_0_avalon_nios_address : out std_logic_vector(7 downto 0); -- address sega_saturn_abus_slave_0_avalon_nios_write : out std_logic; -- write sega_saturn_abus_slave_0_avalon_nios_read : out std_logic; -- read sega_saturn_abus_slave_0_avalon_nios_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata sega_saturn_abus_slave_0_avalon_nios_writedata : out std_logic_vector(15 downto 0); -- writedata sega_saturn_abus_slave_0_avalon_nios_burstcount : out std_logic_vector(0 downto 0); -- burstcount sega_saturn_abus_slave_0_avalon_nios_readdatavalid : in std_logic := 'X'; -- readdatavalid sega_saturn_abus_slave_0_avalon_nios_waitrequest : in std_logic := 'X'; -- waitrequest spi_sd_card_spi_control_port_address : out std_logic_vector(2 downto 0); -- address spi_sd_card_spi_control_port_write : out std_logic; -- write spi_sd_card_spi_control_port_read : out std_logic; -- read spi_sd_card_spi_control_port_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata spi_sd_card_spi_control_port_writedata : out std_logic_vector(15 downto 0); -- writedata spi_sd_card_spi_control_port_chipselect : out std_logic; -- chipselect spi_stm32_spi_control_port_address : out std_logic_vector(2 downto 0); -- address spi_stm32_spi_control_port_write : out std_logic; -- write spi_stm32_spi_control_port_read : out std_logic; -- read spi_stm32_spi_control_port_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata spi_stm32_spi_control_port_writedata : out std_logic_vector(15 downto 0); -- writedata spi_stm32_spi_control_port_chipselect : out std_logic; -- chipselect uart_0_s1_address : out std_logic_vector(2 downto 0); -- address uart_0_s1_write : out std_logic; -- write uart_0_s1_read : out std_logic; -- read uart_0_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata uart_0_s1_writedata : out std_logic_vector(15 downto 0); -- writedata uart_0_s1_begintransfer : out std_logic; -- begintransfer uart_0_s1_chipselect : out std_logic -- chipselect ); end component wasca_mm_interconnect_0; component wasca_irq_mapper is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset receiver0_irq : in std_logic := 'X'; -- irq receiver1_irq : in std_logic := 'X'; -- irq receiver2_irq : in std_logic := 'X'; -- irq receiver3_irq : in std_logic := 'X'; -- irq sender_irq : out std_logic_vector(31 downto 0) -- irq ); end component wasca_irq_mapper; component wasca_rst_controller is generic ( NUM_RESET_INPUTS : integer := 6; OUTPUT_RESET_SYNC_EDGES : string := "deassert"; SYNC_DEPTH : integer := 2; RESET_REQUEST_PRESENT : integer := 0; RESET_REQ_WAIT_TIME : integer := 1; MIN_RST_ASSERTION_TIME : integer := 3; RESET_REQ_EARLY_DSRT_TIME : integer := 1; USE_RESET_REQUEST_IN0 : integer := 0; USE_RESET_REQUEST_IN1 : integer := 0; USE_RESET_REQUEST_IN2 : integer := 0; USE_RESET_REQUEST_IN3 : integer := 0; USE_RESET_REQUEST_IN4 : integer := 0; USE_RESET_REQUEST_IN5 : integer := 0; USE_RESET_REQUEST_IN6 : integer := 0; USE_RESET_REQUEST_IN7 : integer := 0; USE_RESET_REQUEST_IN8 : integer := 0; USE_RESET_REQUEST_IN9 : integer := 0; USE_RESET_REQUEST_IN10 : integer := 0; USE_RESET_REQUEST_IN11 : integer := 0; USE_RESET_REQUEST_IN12 : integer := 0; USE_RESET_REQUEST_IN13 : integer := 0; USE_RESET_REQUEST_IN14 : integer := 0; USE_RESET_REQUEST_IN15 : integer := 0; ADAPT_RESET_REQUEST : integer := 0 ); port ( reset_in0 : in std_logic := 'X'; -- reset clk : in std_logic := 'X'; -- clk reset_out : out std_logic; -- reset reset_req : out std_logic; -- reset_req reset_req_in0 : in std_logic := 'X'; -- reset_req reset_in1 : in std_logic := 'X'; -- reset reset_req_in1 : in std_logic := 'X'; -- reset_req reset_in2 : in std_logic := 'X'; -- reset reset_req_in2 : in std_logic := 'X'; -- reset_req reset_in3 : in std_logic := 'X'; -- reset reset_req_in3 : in std_logic := 'X'; -- reset_req reset_in4 : in std_logic := 'X'; -- reset reset_req_in4 : in std_logic := 'X'; -- reset_req reset_in5 : in std_logic := 'X'; -- reset reset_req_in5 : in std_logic := 'X'; -- reset_req reset_in6 : in std_logic := 'X'; -- reset reset_req_in6 : in std_logic := 'X'; -- reset_req reset_in7 : in std_logic := 'X'; -- reset reset_req_in7 : in std_logic := 'X'; -- reset_req reset_in8 : in std_logic := 'X'; -- reset reset_req_in8 : in std_logic := 'X'; -- reset_req reset_in9 : in std_logic := 'X'; -- reset reset_req_in9 : in std_logic := 'X'; -- reset_req reset_in10 : in std_logic := 'X'; -- reset reset_req_in10 : in std_logic := 'X'; -- reset_req reset_in11 : in std_logic := 'X'; -- reset reset_req_in11 : in std_logic := 'X'; -- reset_req reset_in12 : in std_logic := 'X'; -- reset reset_req_in12 : in std_logic := 'X'; -- reset_req reset_in13 : in std_logic := 'X'; -- reset reset_req_in13 : in std_logic := 'X'; -- reset_req reset_in14 : in std_logic := 'X'; -- reset reset_req_in14 : in std_logic := 'X'; -- reset_req reset_in15 : in std_logic := 'X'; -- reset reset_req_in15 : in std_logic := 'X' -- reset_req ); end component wasca_rst_controller; component wasca_rst_controller_001 is generic ( NUM_RESET_INPUTS : integer := 6; OUTPUT_RESET_SYNC_EDGES : string := "deassert"; SYNC_DEPTH : integer := 2; RESET_REQUEST_PRESENT : integer := 0; RESET_REQ_WAIT_TIME : integer := 1; MIN_RST_ASSERTION_TIME : integer := 3; RESET_REQ_EARLY_DSRT_TIME : integer := 1; USE_RESET_REQUEST_IN0 : integer := 0; USE_RESET_REQUEST_IN1 : integer := 0; USE_RESET_REQUEST_IN2 : integer := 0; USE_RESET_REQUEST_IN3 : integer := 0; USE_RESET_REQUEST_IN4 : integer := 0; USE_RESET_REQUEST_IN5 : integer := 0; USE_RESET_REQUEST_IN6 : integer := 0; USE_RESET_REQUEST_IN7 : integer := 0; USE_RESET_REQUEST_IN8 : integer := 0; USE_RESET_REQUEST_IN9 : integer := 0; USE_RESET_REQUEST_IN10 : integer := 0; USE_RESET_REQUEST_IN11 : integer := 0; USE_RESET_REQUEST_IN12 : integer := 0; USE_RESET_REQUEST_IN13 : integer := 0; USE_RESET_REQUEST_IN14 : integer := 0; USE_RESET_REQUEST_IN15 : integer := 0; ADAPT_RESET_REQUEST : integer := 0 ); port ( reset_in0 : in std_logic := 'X'; -- reset clk : in std_logic := 'X'; -- clk reset_out : out std_logic; -- reset reset_req : out std_logic; -- reset_req reset_req_in0 : in std_logic := 'X'; -- reset_req reset_in1 : in std_logic := 'X'; -- reset reset_req_in1 : in std_logic := 'X'; -- reset_req reset_in2 : in std_logic := 'X'; -- reset reset_req_in2 : in std_logic := 'X'; -- reset_req reset_in3 : in std_logic := 'X'; -- reset reset_req_in3 : in std_logic := 'X'; -- reset_req reset_in4 : in std_logic := 'X'; -- reset reset_req_in4 : in std_logic := 'X'; -- reset_req reset_in5 : in std_logic := 'X'; -- reset reset_req_in5 : in std_logic := 'X'; -- reset_req reset_in6 : in std_logic := 'X'; -- reset reset_req_in6 : in std_logic := 'X'; -- reset_req reset_in7 : in std_logic := 'X'; -- reset reset_req_in7 : in std_logic := 'X'; -- reset_req reset_in8 : in std_logic := 'X'; -- reset reset_req_in8 : in std_logic := 'X'; -- reset_req reset_in9 : in std_logic := 'X'; -- reset reset_req_in9 : in std_logic := 'X'; -- reset_req reset_in10 : in std_logic := 'X'; -- reset reset_req_in10 : in std_logic := 'X'; -- reset_req reset_in11 : in std_logic := 'X'; -- reset reset_req_in11 : in std_logic := 'X'; -- reset_req reset_in12 : in std_logic := 'X'; -- reset reset_req_in12 : in std_logic := 'X'; -- reset_req reset_in13 : in std_logic := 'X'; -- reset reset_req_in13 : in std_logic := 'X'; -- reset_req reset_in14 : in std_logic := 'X'; -- reset reset_req_in14 : in std_logic := 'X'; -- reset_req reset_in15 : in std_logic := 'X'; -- reset reset_req_in15 : in std_logic := 'X' -- reset_req ); end component wasca_rst_controller_001; signal altpll_0_c0_clk : std_logic; -- altpll_0:c0 -> [clock_116_mhz_clk, audio_0:clk, external_sdram_controller:clk, irq_mapper:clk, mm_interconnect_0:altpll_0_c0_clk, nios2_gen2_0:clk, onchip_flash_0:clock, onchip_memory2_0:clk, rst_controller_001:clk, rst_controller_002:clk, sega_saturn_abus_slave_0:clock, spi_sd_card:clk, spi_stm32:clk, uart_0:clk] signal nios2_gen2_0_debug_reset_request_reset : std_logic; -- nios2_gen2_0:debug_reset_request -> [rst_controller:reset_in0, rst_controller_001:reset_in0, rst_controller_002:reset_in0] signal sega_saturn_abus_slave_0_avalon_master_waitrequest : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_waitrequest -> sega_saturn_abus_slave_0:avalon_waitrequest signal sega_saturn_abus_slave_0_avalon_master_readdata : std_logic_vector(15 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_readdata -> sega_saturn_abus_slave_0:avalon_readdata signal sega_saturn_abus_slave_0_avalon_master_read : std_logic; -- sega_saturn_abus_slave_0:avalon_read -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_read signal sega_saturn_abus_slave_0_avalon_master_address : std_logic_vector(27 downto 0); -- sega_saturn_abus_slave_0:avalon_address -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_address signal sega_saturn_abus_slave_0_avalon_master_readdatavalid : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_readdatavalid -> sega_saturn_abus_slave_0:avalon_readdatavalid signal sega_saturn_abus_slave_0_avalon_master_write : std_logic; -- sega_saturn_abus_slave_0:avalon_write -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_write signal sega_saturn_abus_slave_0_avalon_master_writedata : std_logic_vector(15 downto 0); -- sega_saturn_abus_slave_0:avalon_writedata -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_writedata signal sega_saturn_abus_slave_0_avalon_master_burstcount : std_logic; -- sega_saturn_abus_slave_0:avalon_burstcount -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_burstcount signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess signal nios2_gen2_0_data_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest signal nios2_gen2_0_instruction_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read signal mm_interconnect_0_external_sdram_controller_s1_chipselect : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_chipselect -> external_sdram_controller:az_cs signal mm_interconnect_0_external_sdram_controller_s1_readdata : std_logic_vector(15 downto 0); -- external_sdram_controller:za_data -> mm_interconnect_0:external_sdram_controller_s1_readdata signal mm_interconnect_0_external_sdram_controller_s1_waitrequest : std_logic; -- external_sdram_controller:za_waitrequest -> mm_interconnect_0:external_sdram_controller_s1_waitrequest signal mm_interconnect_0_external_sdram_controller_s1_address : std_logic_vector(23 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_address -> external_sdram_controller:az_addr signal mm_interconnect_0_external_sdram_controller_s1_read : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_read -> mm_interconnect_0_external_sdram_controller_s1_read:in signal mm_interconnect_0_external_sdram_controller_s1_byteenable : std_logic_vector(1 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_byteenable -> mm_interconnect_0_external_sdram_controller_s1_byteenable:in signal mm_interconnect_0_external_sdram_controller_s1_readdatavalid : std_logic; -- external_sdram_controller:za_valid -> mm_interconnect_0:external_sdram_controller_s1_readdatavalid signal mm_interconnect_0_external_sdram_controller_s1_write : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_write -> mm_interconnect_0_external_sdram_controller_s1_write:in signal mm_interconnect_0_external_sdram_controller_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_writedata -> external_sdram_controller:az_data signal mm_interconnect_0_onchip_flash_0_data_readdata : std_logic_vector(31 downto 0); -- onchip_flash_0:avmm_data_readdata -> mm_interconnect_0:onchip_flash_0_data_readdata signal mm_interconnect_0_onchip_flash_0_data_waitrequest : std_logic; -- onchip_flash_0:avmm_data_waitrequest -> mm_interconnect_0:onchip_flash_0_data_waitrequest signal mm_interconnect_0_onchip_flash_0_data_address : std_logic_vector(15 downto 0); -- mm_interconnect_0:onchip_flash_0_data_address -> onchip_flash_0:avmm_data_addr signal mm_interconnect_0_onchip_flash_0_data_read : std_logic; -- mm_interconnect_0:onchip_flash_0_data_read -> onchip_flash_0:avmm_data_read signal mm_interconnect_0_onchip_flash_0_data_readdatavalid : std_logic; -- onchip_flash_0:avmm_data_readdatavalid -> mm_interconnect_0:onchip_flash_0_data_readdatavalid signal mm_interconnect_0_onchip_flash_0_data_burstcount : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_flash_0_data_burstcount -> onchip_flash_0:avmm_data_burstcount signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(11 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken signal mm_interconnect_0_audio_0_avalon_audio_slave_chipselect : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_chipselect -> audio_0:chipselect signal mm_interconnect_0_audio_0_avalon_audio_slave_readdata : std_logic_vector(31 downto 0); -- audio_0:readdata -> mm_interconnect_0:audio_0_avalon_audio_slave_readdata signal mm_interconnect_0_audio_0_avalon_audio_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:audio_0_avalon_audio_slave_address -> audio_0:address signal mm_interconnect_0_audio_0_avalon_audio_slave_read : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_read -> audio_0:read signal mm_interconnect_0_audio_0_avalon_audio_slave_write : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_write -> audio_0:write signal mm_interconnect_0_audio_0_avalon_audio_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:audio_0_avalon_audio_slave_writedata -> audio_0:writedata signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata : std_logic_vector(15 downto 0); -- sega_saturn_abus_slave_0:avalon_nios_readdata -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_readdata signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest : std_logic; -- sega_saturn_abus_slave_0:avalon_nios_waitrequest -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_waitrequest signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_address -> sega_saturn_abus_slave_0:avalon_nios_address signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_read -> sega_saturn_abus_slave_0:avalon_nios_read signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid : std_logic; -- sega_saturn_abus_slave_0:avalon_nios_readdatavalid -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_readdatavalid signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_write -> sega_saturn_abus_slave_0:avalon_nios_write signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_writedata -> sega_saturn_abus_slave_0:avalon_nios_writedata signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount : std_logic_vector(0 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_burstcount -> sega_saturn_abus_slave_0:avalon_nios_burstcount signal mm_interconnect_0_altpll_0_pll_slave_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> mm_interconnect_0:altpll_0_pll_slave_readdata signal mm_interconnect_0_altpll_0_pll_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_address -> altpll_0:address signal mm_interconnect_0_altpll_0_pll_slave_read : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_read -> altpll_0:read signal mm_interconnect_0_altpll_0_pll_slave_write : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_write -> altpll_0:write signal mm_interconnect_0_altpll_0_pll_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_writedata -> altpll_0:writedata signal mm_interconnect_0_uart_0_s1_chipselect : std_logic; -- mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect signal mm_interconnect_0_uart_0_s1_readdata : std_logic_vector(15 downto 0); -- uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata signal mm_interconnect_0_uart_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:uart_0_s1_address -> uart_0:address signal mm_interconnect_0_uart_0_s1_read : std_logic; -- mm_interconnect_0:uart_0_s1_read -> mm_interconnect_0_uart_0_s1_read:in signal mm_interconnect_0_uart_0_s1_begintransfer : std_logic; -- mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer signal mm_interconnect_0_uart_0_s1_write : std_logic; -- mm_interconnect_0:uart_0_s1_write -> mm_interconnect_0_uart_0_s1_write:in signal mm_interconnect_0_uart_0_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata signal mm_interconnect_0_spi_sd_card_spi_control_port_chipselect : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_chipselect -> spi_sd_card:spi_select signal mm_interconnect_0_spi_sd_card_spi_control_port_readdata : std_logic_vector(15 downto 0); -- spi_sd_card:data_to_cpu -> mm_interconnect_0:spi_sd_card_spi_control_port_readdata signal mm_interconnect_0_spi_sd_card_spi_control_port_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:spi_sd_card_spi_control_port_address -> spi_sd_card:mem_addr signal mm_interconnect_0_spi_sd_card_spi_control_port_read : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_read -> mm_interconnect_0_spi_sd_card_spi_control_port_read:in signal mm_interconnect_0_spi_sd_card_spi_control_port_write : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_write -> mm_interconnect_0_spi_sd_card_spi_control_port_write:in signal mm_interconnect_0_spi_sd_card_spi_control_port_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:spi_sd_card_spi_control_port_writedata -> spi_sd_card:data_from_cpu signal mm_interconnect_0_spi_stm32_spi_control_port_chipselect : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_chipselect -> spi_stm32:spi_select signal mm_interconnect_0_spi_stm32_spi_control_port_readdata : std_logic_vector(15 downto 0); -- spi_stm32:data_to_cpu -> mm_interconnect_0:spi_stm32_spi_control_port_readdata signal mm_interconnect_0_spi_stm32_spi_control_port_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:spi_stm32_spi_control_port_address -> spi_stm32:mem_addr signal mm_interconnect_0_spi_stm32_spi_control_port_read : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_read -> mm_interconnect_0_spi_stm32_spi_control_port_read:in signal mm_interconnect_0_spi_stm32_spi_control_port_write : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_write -> mm_interconnect_0_spi_stm32_spi_control_port_write:in signal mm_interconnect_0_spi_stm32_spi_control_port_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:spi_stm32_spi_control_port_writedata -> spi_stm32:data_from_cpu signal irq_mapper_receiver0_irq : std_logic; -- audio_0:irq -> irq_mapper:receiver0_irq signal irq_mapper_receiver1_irq : std_logic; -- uart_0:irq -> irq_mapper:receiver1_irq signal irq_mapper_receiver2_irq : std_logic; -- spi_sd_card:irq -> irq_mapper:receiver2_irq signal irq_mapper_receiver3_irq : std_logic; -- spi_stm32:irq -> irq_mapper:receiver3_irq signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [altpll_0:reset, mm_interconnect_0:altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset] signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [audio_0:reset, irq_mapper:reset, mm_interconnect_0:sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_001_reset_out_reset:in, rst_translator:in_reset, sega_saturn_abus_slave_0:reset] signal rst_controller_001_reset_out_reset_req : std_logic; -- rst_controller_001:reset_req -> [onchip_memory2_0:reset_req, rst_translator:reset_req_in] signal mm_interconnect_0_external_sdram_controller_s1_read_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_read:inv -> external_sdram_controller:az_rd_n signal mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv : std_logic_vector(1 downto 0); -- mm_interconnect_0_external_sdram_controller_s1_byteenable:inv -> external_sdram_controller:az_be_n signal mm_interconnect_0_external_sdram_controller_s1_write_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_write:inv -> external_sdram_controller:az_wr_n signal mm_interconnect_0_uart_0_s1_read_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_read:inv -> uart_0:read_n signal mm_interconnect_0_uart_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_write:inv -> uart_0:write_n signal mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv : std_logic; -- mm_interconnect_0_spi_sd_card_spi_control_port_read:inv -> spi_sd_card:read_n signal mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv : std_logic; -- mm_interconnect_0_spi_sd_card_spi_control_port_write:inv -> spi_sd_card:write_n signal mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv : std_logic; -- mm_interconnect_0_spi_stm32_spi_control_port_read:inv -> spi_stm32:read_n signal mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv : std_logic; -- mm_interconnect_0_spi_stm32_spi_control_port_write:inv -> spi_stm32:write_n signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> [external_sdram_controller:reset_n, nios2_gen2_0:reset_n, onchip_flash_0:reset_n, spi_sd_card:reset_n, spi_stm32:reset_n, uart_0:reset_n] begin altpll_0 : component wasca_altpll_0 port map ( clk => clk_clk, -- inclk_interface.clk reset => rst_controller_reset_out_reset, -- inclk_interface_reset.reset read => mm_interconnect_0_altpll_0_pll_slave_read, -- pll_slave.read write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write address => mm_interconnect_0_altpll_0_pll_slave_address, -- .address readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata c0 => altpll_0_c0_clk, -- c0.clk areset => altpll_0_areset_conduit_export, -- areset_conduit.export c1 => open, -- c1_conduit.export locked => altpll_0_locked_conduit_export, -- locked_conduit.export phasedone => altpll_0_phasedone_conduit_export -- phasedone_conduit.export ); audio_0 : component wasca_audio_0 port map ( clk => altpll_0_c0_clk, -- clk.clk reset => rst_controller_001_reset_out_reset, -- reset.reset address => mm_interconnect_0_audio_0_avalon_audio_slave_address, -- avalon_audio_slave.address chipselect => mm_interconnect_0_audio_0_avalon_audio_slave_chipselect, -- .chipselect read => mm_interconnect_0_audio_0_avalon_audio_slave_read, -- .read write => mm_interconnect_0_audio_0_avalon_audio_slave_write, -- .write writedata => mm_interconnect_0_audio_0_avalon_audio_slave_writedata, -- .writedata readdata => mm_interconnect_0_audio_0_avalon_audio_slave_readdata, -- .readdata irq => irq_mapper_receiver0_irq, -- interrupt.irq AUD_BCLK => audio_out_BCLK, -- external_interface.export AUD_DACDAT => audio_out_DACDAT, -- .export AUD_DACLRCK => audio_out_DACLRCK -- .export ); external_sdram_controller : component wasca_external_sdram_controller port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n az_addr => mm_interconnect_0_external_sdram_controller_s1_address, -- s1.address az_be_n => mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv, -- .byteenable_n az_cs => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect az_data => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata az_rd_n => mm_interconnect_0_external_sdram_controller_s1_read_ports_inv, -- .read_n az_wr_n => mm_interconnect_0_external_sdram_controller_s1_write_ports_inv, -- .write_n za_data => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata za_valid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid za_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest zs_addr => external_sdram_controller_wire_addr, -- wire.export zs_ba => external_sdram_controller_wire_ba, -- .export zs_cas_n => external_sdram_controller_wire_cas_n, -- .export zs_cke => external_sdram_controller_wire_cke, -- .export zs_cs_n => external_sdram_controller_wire_cs_n, -- .export zs_dq => external_sdram_controller_wire_dq, -- .export zs_dqm => external_sdram_controller_wire_dqm, -- .export zs_ras_n => external_sdram_controller_wire_ras_n, -- .export zs_we_n => external_sdram_controller_wire_we_n -- .export ); nios2_gen2_0 : component wasca_nios2_gen2_0 port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n d_address => nios2_gen2_0_data_master_address, -- data_master.address d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable d_read => nios2_gen2_0_data_master_read, -- .read d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest d_write => nios2_gen2_0_data_master_write, -- .write d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address i_read => nios2_gen2_0_instruction_master_read, -- .read i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest irq => nios2_gen2_0_irq_irq, -- irq.irq debug_reset_request => nios2_gen2_0_debug_reset_request_reset, -- debug_reset_request.reset debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata dummy_ci_port => open -- custom_instruction_master.readra ); onchip_flash_0 : component altera_onchip_flash generic map ( INIT_FILENAME => "", INIT_FILENAME_SIM => "", DEVICE_FAMILY => "MAX 10", PART_NAME => "10M08SAE144C8GES", DEVICE_ID => "08", SECTOR1_START_ADDR => 0, SECTOR1_END_ADDR => 4095, SECTOR2_START_ADDR => 4096, SECTOR2_END_ADDR => 8191, SECTOR3_START_ADDR => 8192, SECTOR3_END_ADDR => 29183, SECTOR4_START_ADDR => 29184, SECTOR4_END_ADDR => 44031, SECTOR5_START_ADDR => 0, SECTOR5_END_ADDR => 0, MIN_VALID_ADDR => 0, MAX_VALID_ADDR => 44031, MIN_UFM_VALID_ADDR => 0, MAX_UFM_VALID_ADDR => 44031, SECTOR1_MAP => 1, SECTOR2_MAP => 2, SECTOR3_MAP => 3, SECTOR4_MAP => 4, SECTOR5_MAP => 0, ADDR_RANGE1_END_ADDR => 44031, ADDR_RANGE1_OFFSET => 512, ADDR_RANGE2_OFFSET => 0, AVMM_DATA_ADDR_WIDTH => 16, AVMM_DATA_DATA_WIDTH => 32, AVMM_DATA_BURSTCOUNT_WIDTH => 4, SECTOR_READ_PROTECTION_MODE => 31, FLASH_SEQ_READ_DATA_COUNT => 2, FLASH_ADDR_ALIGNMENT_BITS => 1, FLASH_READ_CYCLE_MAX_INDEX => 3, FLASH_RESET_CYCLE_MAX_INDEX => 29, FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX => 111, FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX => 40603248, FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX => 35382, PARALLEL_MODE => true, READ_AND_WRITE_MODE => false, WRAPPING_BURST_MODE => false, IS_DUAL_BOOT => "False", IS_ERAM_SKIP => "True", IS_COMPRESSED_IMAGE => "True" ) port map ( clock => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- nreset.reset_n avmm_data_addr => mm_interconnect_0_onchip_flash_0_data_address, -- data.address avmm_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read avmm_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata avmm_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest avmm_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid avmm_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount avmm_data_writedata => "00000000000000000000000000000000", -- (terminated) avmm_data_write => '0', -- (terminated) avmm_csr_addr => '0', -- (terminated) avmm_csr_read => '0', -- (terminated) avmm_csr_writedata => "00000000000000000000000000000000", -- (terminated) avmm_csr_write => '0', -- (terminated) avmm_csr_readdata => open -- (terminated) ); onchip_memory2_0 : component wasca_onchip_memory2_0 port map ( clk => altpll_0_c0_clk, -- clk1.clk address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable reset => rst_controller_001_reset_out_reset, -- reset1.reset reset_req => rst_controller_001_reset_out_reset_req -- .reset_req ); sega_saturn_abus_slave_0 : component sega_saturn_abus_slave port map ( clock => altpll_0_c0_clk, -- clock.clk abus_address => sega_saturn_abus_slave_0_abus_address, -- abus.address abus_chipselect => sega_saturn_abus_slave_0_abus_chipselect, -- .chipselect abus_read => sega_saturn_abus_slave_0_abus_read, -- .read abus_write => sega_saturn_abus_slave_0_abus_write, -- .write abus_waitrequest => sega_saturn_abus_slave_0_abus_waitrequest, -- .waitrequest abus_interrupt => sega_saturn_abus_slave_0_abus_interrupt, -- .interrupt abus_addressdata => sega_saturn_abus_slave_0_abus_addressdata, -- .addressdata abus_direction => sega_saturn_abus_slave_0_abus_direction, -- .direction abus_muxing => sega_saturn_abus_slave_0_abus_muxing, -- .muxing abus_disable_out => sega_saturn_abus_slave_0_abus_disableout, -- .disableout avalon_read => sega_saturn_abus_slave_0_avalon_master_read, -- avalon_master.read avalon_write => sega_saturn_abus_slave_0_avalon_master_write, -- .write avalon_waitrequest => sega_saturn_abus_slave_0_avalon_master_waitrequest, -- .waitrequest avalon_address => sega_saturn_abus_slave_0_avalon_master_address, -- .address avalon_readdata => sega_saturn_abus_slave_0_avalon_master_readdata, -- .readdata avalon_writedata => sega_saturn_abus_slave_0_avalon_master_writedata, -- .writedata avalon_readdatavalid => sega_saturn_abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid avalon_burstcount => sega_saturn_abus_slave_0_avalon_master_burstcount, -- .burstcount reset => rst_controller_001_reset_out_reset, -- reset.reset saturn_reset => sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset, -- conduit_saturn_reset.saturn_reset avalon_nios_read => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read, -- avalon_nios.read avalon_nios_write => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write, -- .write avalon_nios_address => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address, -- .address avalon_nios_writedata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata, -- .writedata avalon_nios_readdata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata, -- .readdata avalon_nios_waitrequest => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest avalon_nios_readdatavalid => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid avalon_nios_burstcount => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount(0) -- .burstcount ); spi_sd_card : component wasca_spi_sd_card port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n data_from_cpu => mm_interconnect_0_spi_sd_card_spi_control_port_writedata, -- spi_control_port.writedata data_to_cpu => mm_interconnect_0_spi_sd_card_spi_control_port_readdata, -- .readdata mem_addr => mm_interconnect_0_spi_sd_card_spi_control_port_address, -- .address read_n => mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv, -- .read_n spi_select => mm_interconnect_0_spi_sd_card_spi_control_port_chipselect, -- .chipselect write_n => mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv, -- .write_n irq => irq_mapper_receiver2_irq, -- irq.irq MISO => spi_sd_card_MISO, -- external.export MOSI => spi_sd_card_MOSI, -- .export SCLK => spi_sd_card_SCLK, -- .export SS_n => spi_sd_card_SS_n -- .export ); spi_stm32 : component wasca_spi_stm32 port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n data_from_cpu => mm_interconnect_0_spi_stm32_spi_control_port_writedata, -- spi_control_port.writedata data_to_cpu => mm_interconnect_0_spi_stm32_spi_control_port_readdata, -- .readdata mem_addr => mm_interconnect_0_spi_stm32_spi_control_port_address, -- .address read_n => mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv, -- .read_n spi_select => mm_interconnect_0_spi_stm32_spi_control_port_chipselect, -- .chipselect write_n => mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv, -- .write_n irq => irq_mapper_receiver3_irq, -- irq.irq MISO => spi_stm32_MISO, -- external.export MOSI => spi_stm32_MOSI, -- .export SCLK => spi_stm32_SCLK, -- .export SS_n => spi_stm32_SS_n -- .export ); uart_0 : component wasca_uart_0 port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n address => mm_interconnect_0_uart_0_s1_address, -- s1.address begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer chipselect => mm_interconnect_0_uart_0_s1_chipselect, -- .chipselect read_n => mm_interconnect_0_uart_0_s1_read_ports_inv, -- .read_n write_n => mm_interconnect_0_uart_0_s1_write_ports_inv, -- .write_n writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata dataavailable => open, -- .dataavailable readyfordata => open, -- .readyfordata rxd => uart_0_external_connection_rxd, -- external_connection.export txd => uart_0_external_connection_txd, -- .export irq => irq_mapper_receiver1_irq -- irq.irq ); mm_interconnect_0 : component wasca_mm_interconnect_0 port map ( altpll_0_c0_clk => altpll_0_c0_clk, -- altpll_0_c0.clk clk_0_clk_clk => clk_clk, -- clk_0_clk.clk altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- sega_saturn_abus_slave_0_reset_reset_bridge_in_reset.reset nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata sega_saturn_abus_slave_0_avalon_master_address => sega_saturn_abus_slave_0_avalon_master_address, -- sega_saturn_abus_slave_0_avalon_master.address sega_saturn_abus_slave_0_avalon_master_waitrequest => sega_saturn_abus_slave_0_avalon_master_waitrequest, -- .waitrequest sega_saturn_abus_slave_0_avalon_master_burstcount(0) => sega_saturn_abus_slave_0_avalon_master_burstcount, -- .burstcount sega_saturn_abus_slave_0_avalon_master_read => sega_saturn_abus_slave_0_avalon_master_read, -- .read sega_saturn_abus_slave_0_avalon_master_readdata => sega_saturn_abus_slave_0_avalon_master_readdata, -- .readdata sega_saturn_abus_slave_0_avalon_master_readdatavalid => sega_saturn_abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid sega_saturn_abus_slave_0_avalon_master_write => sega_saturn_abus_slave_0_avalon_master_write, -- .write sega_saturn_abus_slave_0_avalon_master_writedata => sega_saturn_abus_slave_0_avalon_master_writedata, -- .writedata altpll_0_pll_slave_address => mm_interconnect_0_altpll_0_pll_slave_address, -- altpll_0_pll_slave.address altpll_0_pll_slave_write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write altpll_0_pll_slave_read => mm_interconnect_0_altpll_0_pll_slave_read, -- .read altpll_0_pll_slave_readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata altpll_0_pll_slave_writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata audio_0_avalon_audio_slave_address => mm_interconnect_0_audio_0_avalon_audio_slave_address, -- audio_0_avalon_audio_slave.address audio_0_avalon_audio_slave_write => mm_interconnect_0_audio_0_avalon_audio_slave_write, -- .write audio_0_avalon_audio_slave_read => mm_interconnect_0_audio_0_avalon_audio_slave_read, -- .read audio_0_avalon_audio_slave_readdata => mm_interconnect_0_audio_0_avalon_audio_slave_readdata, -- .readdata audio_0_avalon_audio_slave_writedata => mm_interconnect_0_audio_0_avalon_audio_slave_writedata, -- .writedata audio_0_avalon_audio_slave_chipselect => mm_interconnect_0_audio_0_avalon_audio_slave_chipselect, -- .chipselect external_sdram_controller_s1_address => mm_interconnect_0_external_sdram_controller_s1_address, -- external_sdram_controller_s1.address external_sdram_controller_s1_write => mm_interconnect_0_external_sdram_controller_s1_write, -- .write external_sdram_controller_s1_read => mm_interconnect_0_external_sdram_controller_s1_read, -- .read external_sdram_controller_s1_readdata => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata external_sdram_controller_s1_writedata => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata external_sdram_controller_s1_byteenable => mm_interconnect_0_external_sdram_controller_s1_byteenable, -- .byteenable external_sdram_controller_s1_readdatavalid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid external_sdram_controller_s1_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest external_sdram_controller_s1_chipselect => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess onchip_flash_0_data_address => mm_interconnect_0_onchip_flash_0_data_address, -- onchip_flash_0_data.address onchip_flash_0_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read onchip_flash_0_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata onchip_flash_0_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount onchip_flash_0_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid onchip_flash_0_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken sega_saturn_abus_slave_0_avalon_nios_address => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address, -- sega_saturn_abus_slave_0_avalon_nios.address sega_saturn_abus_slave_0_avalon_nios_write => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write, -- .write sega_saturn_abus_slave_0_avalon_nios_read => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read, -- .read sega_saturn_abus_slave_0_avalon_nios_readdata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata, -- .readdata sega_saturn_abus_slave_0_avalon_nios_writedata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata, -- .writedata sega_saturn_abus_slave_0_avalon_nios_burstcount => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount, -- .burstcount sega_saturn_abus_slave_0_avalon_nios_readdatavalid => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid sega_saturn_abus_slave_0_avalon_nios_waitrequest => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest spi_sd_card_spi_control_port_address => mm_interconnect_0_spi_sd_card_spi_control_port_address, -- spi_sd_card_spi_control_port.address spi_sd_card_spi_control_port_write => mm_interconnect_0_spi_sd_card_spi_control_port_write, -- .write spi_sd_card_spi_control_port_read => mm_interconnect_0_spi_sd_card_spi_control_port_read, -- .read spi_sd_card_spi_control_port_readdata => mm_interconnect_0_spi_sd_card_spi_control_port_readdata, -- .readdata spi_sd_card_spi_control_port_writedata => mm_interconnect_0_spi_sd_card_spi_control_port_writedata, -- .writedata spi_sd_card_spi_control_port_chipselect => mm_interconnect_0_spi_sd_card_spi_control_port_chipselect, -- .chipselect spi_stm32_spi_control_port_address => mm_interconnect_0_spi_stm32_spi_control_port_address, -- spi_stm32_spi_control_port.address spi_stm32_spi_control_port_write => mm_interconnect_0_spi_stm32_spi_control_port_write, -- .write spi_stm32_spi_control_port_read => mm_interconnect_0_spi_stm32_spi_control_port_read, -- .read spi_stm32_spi_control_port_readdata => mm_interconnect_0_spi_stm32_spi_control_port_readdata, -- .readdata spi_stm32_spi_control_port_writedata => mm_interconnect_0_spi_stm32_spi_control_port_writedata, -- .writedata spi_stm32_spi_control_port_chipselect => mm_interconnect_0_spi_stm32_spi_control_port_chipselect, -- .chipselect uart_0_s1_address => mm_interconnect_0_uart_0_s1_address, -- uart_0_s1.address uart_0_s1_write => mm_interconnect_0_uart_0_s1_write, -- .write uart_0_s1_read => mm_interconnect_0_uart_0_s1_read, -- .read uart_0_s1_readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata uart_0_s1_writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata uart_0_s1_begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer uart_0_s1_chipselect => mm_interconnect_0_uart_0_s1_chipselect -- .chipselect ); irq_mapper : component wasca_irq_mapper port map ( clk => altpll_0_c0_clk, -- clk.clk reset => rst_controller_001_reset_out_reset, -- clk_reset.reset receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq receiver2_irq => irq_mapper_receiver2_irq, -- receiver2.irq receiver3_irq => irq_mapper_receiver3_irq, -- receiver3.irq sender_irq => nios2_gen2_0_irq_irq -- sender.irq ); rst_controller : component wasca_rst_controller generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "deassert", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 0, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset clk => clk_clk, -- clk.clk reset_out => rst_controller_reset_out_reset, -- reset_out.reset reset_req => open, -- (terminated) reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); rst_controller_001 : component wasca_rst_controller_001 generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "deassert", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 1, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset clk => altpll_0_c0_clk, -- clk.clk reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); rst_controller_002 : component wasca_rst_controller generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "both", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 0, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset clk => altpll_0_c0_clk, -- clk.clk reset_out => open, -- reset_out.reset reset_req => open, -- (terminated) reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); mm_interconnect_0_external_sdram_controller_s1_read_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_read; mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_byteenable; mm_interconnect_0_external_sdram_controller_s1_write_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_write; mm_interconnect_0_uart_0_s1_read_ports_inv <= not mm_interconnect_0_uart_0_s1_read; mm_interconnect_0_uart_0_s1_write_ports_inv <= not mm_interconnect_0_uart_0_s1_write; mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv <= not mm_interconnect_0_spi_sd_card_spi_control_port_read; mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv <= not mm_interconnect_0_spi_sd_card_spi_control_port_write; mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv <= not mm_interconnect_0_spi_stm32_spi_control_port_read; mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv <= not mm_interconnect_0_spi_stm32_spi_control_port_write; rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset; clock_116_mhz_clk <= altpll_0_c0_clk; end architecture rtl; -- of wasca
-- wasca.vhd -- Generated using ACDS version 15.0 145 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity wasca is port ( altpll_0_areset_conduit_export : in std_logic := '0'; -- altpll_0_areset_conduit.export altpll_0_locked_conduit_export : out std_logic; -- altpll_0_locked_conduit.export altpll_0_phasedone_conduit_export : out std_logic; -- altpll_0_phasedone_conduit.export audio_out_BCLK : in std_logic := '0'; -- audio_out.BCLK audio_out_DACDAT : out std_logic; -- .DACDAT audio_out_DACLRCK : in std_logic := '0'; -- .DACLRCK clk_clk : in std_logic := '0'; -- clk.clk clock_116_mhz_clk : out std_logic; -- clock_116_mhz.clk external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n external_sdram_controller_wire_cke : out std_logic; -- .cke external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n external_sdram_controller_wire_we_n : out std_logic; -- .we_n sega_saturn_abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- sega_saturn_abus_slave_0_abus.address sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect sega_saturn_abus_slave_0_abus_read : in std_logic := '0'; -- .read sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest sega_saturn_abus_slave_0_abus_interrupt : out std_logic; -- .interrupt sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .addressdata sega_saturn_abus_slave_0_abus_direction : out std_logic; -- .direction sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- .muxing sega_saturn_abus_slave_0_abus_disableout : out std_logic; -- .disableout sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := '0'; -- sega_saturn_abus_slave_0_conduit_saturn_reset.saturn_reset spi_sd_card_MISO : in std_logic := '0'; -- spi_sd_card.MISO spi_sd_card_MOSI : out std_logic; -- .MOSI spi_sd_card_SCLK : out std_logic; -- .SCLK spi_sd_card_SS_n : out std_logic; -- .SS_n spi_stm32_MISO : out std_logic; -- spi_stm32.MISO spi_stm32_MOSI : in std_logic := '0'; -- .MOSI spi_stm32_SCLK : in std_logic := '0'; -- .SCLK spi_stm32_SS_n : in std_logic := '0'; -- .SS_n uart_0_external_connection_rxd : in std_logic := '0'; -- uart_0_external_connection.rxd uart_0_external_connection_txd : out std_logic -- .txd ); end entity wasca; architecture rtl of wasca is component wasca_altpll_0 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset read : in std_logic := 'X'; -- read write : in std_logic := 'X'; -- write address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address readdata : out std_logic_vector(31 downto 0); -- readdata writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata c0 : out std_logic; -- clk areset : in std_logic := 'X'; -- export c1 : out std_logic; -- export locked : out std_logic; -- export phasedone : out std_logic -- export ); end component wasca_altpll_0; component wasca_audio_0 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address chipselect : in std_logic := 'X'; -- chipselect read : in std_logic := 'X'; -- read write : in std_logic := 'X'; -- write writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata readdata : out std_logic_vector(31 downto 0); -- readdata irq : out std_logic; -- irq AUD_BCLK : in std_logic := 'X'; -- export AUD_DACDAT : out std_logic; -- export AUD_DACLRCK : in std_logic := 'X' -- export ); end component wasca_audio_0; component wasca_external_sdram_controller is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n az_addr : in std_logic_vector(23 downto 0) := (others => 'X'); -- address az_be_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable_n az_cs : in std_logic := 'X'; -- chipselect az_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata az_rd_n : in std_logic := 'X'; -- read_n az_wr_n : in std_logic := 'X'; -- write_n za_data : out std_logic_vector(15 downto 0); -- readdata za_valid : out std_logic; -- readdatavalid za_waitrequest : out std_logic; -- waitrequest zs_addr : out std_logic_vector(12 downto 0); -- export zs_ba : out std_logic_vector(1 downto 0); -- export zs_cas_n : out std_logic; -- export zs_cke : out std_logic; -- export zs_cs_n : out std_logic; -- export zs_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export zs_dqm : out std_logic_vector(1 downto 0); -- export zs_ras_n : out std_logic; -- export zs_we_n : out std_logic -- export ); end component wasca_external_sdram_controller; component wasca_nios2_gen2_0 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n d_address : out std_logic_vector(26 downto 0); -- address d_byteenable : out std_logic_vector(3 downto 0); -- byteenable d_read : out std_logic; -- read d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata d_waitrequest : in std_logic := 'X'; -- waitrequest d_write : out std_logic; -- write d_writedata : out std_logic_vector(31 downto 0); -- writedata debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess i_address : out std_logic_vector(26 downto 0); -- address i_read : out std_logic; -- read i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata i_waitrequest : in std_logic := 'X'; -- waitrequest irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq debug_reset_request : out std_logic; -- reset debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess debug_mem_slave_read : in std_logic := 'X'; -- read debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata debug_mem_slave_waitrequest : out std_logic; -- waitrequest debug_mem_slave_write : in std_logic := 'X'; -- write debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata dummy_ci_port : out std_logic -- readra ); end component wasca_nios2_gen2_0; component altera_onchip_flash is generic ( INIT_FILENAME : string := ""; INIT_FILENAME_SIM : string := ""; DEVICE_FAMILY : string := "Unknown"; PART_NAME : string := "Unknown"; DEVICE_ID : string := "Unknown"; SECTOR1_START_ADDR : integer := 0; SECTOR1_END_ADDR : integer := 0; SECTOR2_START_ADDR : integer := 0; SECTOR2_END_ADDR : integer := 0; SECTOR3_START_ADDR : integer := 0; SECTOR3_END_ADDR : integer := 0; SECTOR4_START_ADDR : integer := 0; SECTOR4_END_ADDR : integer := 0; SECTOR5_START_ADDR : integer := 0; SECTOR5_END_ADDR : integer := 0; MIN_VALID_ADDR : integer := 0; MAX_VALID_ADDR : integer := 0; MIN_UFM_VALID_ADDR : integer := 0; MAX_UFM_VALID_ADDR : integer := 0; SECTOR1_MAP : integer := 0; SECTOR2_MAP : integer := 0; SECTOR3_MAP : integer := 0; SECTOR4_MAP : integer := 0; SECTOR5_MAP : integer := 0; ADDR_RANGE1_END_ADDR : integer := 0; ADDR_RANGE1_OFFSET : integer := 0; ADDR_RANGE2_OFFSET : integer := 0; AVMM_DATA_ADDR_WIDTH : integer := 19; AVMM_DATA_DATA_WIDTH : integer := 32; AVMM_DATA_BURSTCOUNT_WIDTH : integer := 4; SECTOR_READ_PROTECTION_MODE : integer := 31; FLASH_SEQ_READ_DATA_COUNT : integer := 2; FLASH_ADDR_ALIGNMENT_BITS : integer := 1; FLASH_READ_CYCLE_MAX_INDEX : integer := 4; FLASH_RESET_CYCLE_MAX_INDEX : integer := 29; FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX : integer := 112; FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX : integer := 40603248; FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX : integer := 35382; PARALLEL_MODE : boolean := true; READ_AND_WRITE_MODE : boolean := true; WRAPPING_BURST_MODE : boolean := false; IS_DUAL_BOOT : string := "False"; IS_ERAM_SKIP : string := "False"; IS_COMPRESSED_IMAGE : string := "False" ); port ( clock : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n avmm_data_addr : in std_logic_vector(15 downto 0) := (others => 'X'); -- address avmm_data_read : in std_logic := 'X'; -- read avmm_data_readdata : out std_logic_vector(31 downto 0); -- readdata avmm_data_waitrequest : out std_logic; -- waitrequest avmm_data_readdatavalid : out std_logic; -- readdatavalid avmm_data_burstcount : in std_logic_vector(3 downto 0) := (others => 'X'); -- burstcount avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata avmm_data_write : in std_logic := 'X'; -- write avmm_csr_addr : in std_logic := 'X'; -- address avmm_csr_read : in std_logic := 'X'; -- read avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata avmm_csr_write : in std_logic := 'X'; -- write avmm_csr_readdata : out std_logic_vector(31 downto 0) -- readdata ); end component altera_onchip_flash; component wasca_onchip_memory2_0 is port ( clk : in std_logic := 'X'; -- clk address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address clken : in std_logic := 'X'; -- clken chipselect : in std_logic := 'X'; -- chipselect write : in std_logic := 'X'; -- write readdata : out std_logic_vector(31 downto 0); -- readdata writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable reset : in std_logic := 'X'; -- reset reset_req : in std_logic := 'X' -- reset_req ); end component wasca_onchip_memory2_0; component sega_saturn_abus_slave is port ( clock : in std_logic := 'X'; -- clk abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect abus_read : in std_logic := 'X'; -- read abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write abus_waitrequest : out std_logic; -- waitrequest abus_interrupt : out std_logic; -- interrupt abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata abus_direction : out std_logic; -- direction abus_muxing : out std_logic_vector(1 downto 0); -- muxing abus_disable_out : out std_logic; -- disableout avalon_read : out std_logic; -- read avalon_write : out std_logic; -- write avalon_waitrequest : in std_logic := 'X'; -- waitrequest avalon_address : out std_logic_vector(27 downto 0); -- address avalon_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata avalon_writedata : out std_logic_vector(15 downto 0); -- writedata avalon_readdatavalid : in std_logic := 'X'; -- readdatavalid avalon_burstcount : out std_logic; -- burstcount reset : in std_logic := 'X'; -- reset saturn_reset : in std_logic := 'X'; -- saturn_reset avalon_nios_read : in std_logic := 'X'; -- read avalon_nios_write : in std_logic := 'X'; -- write avalon_nios_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata avalon_nios_readdata : out std_logic_vector(15 downto 0); -- readdata avalon_nios_waitrequest : out std_logic; -- waitrequest avalon_nios_readdatavalid : out std_logic; -- readdatavalid avalon_nios_burstcount : in std_logic := 'X' -- burstcount ); end component sega_saturn_abus_slave; component wasca_spi_sd_card is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n data_from_cpu : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata data_to_cpu : out std_logic_vector(15 downto 0); -- readdata mem_addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- address read_n : in std_logic := 'X'; -- read_n spi_select : in std_logic := 'X'; -- chipselect write_n : in std_logic := 'X'; -- write_n irq : out std_logic; -- irq MISO : in std_logic := 'X'; -- export MOSI : out std_logic; -- export SCLK : out std_logic; -- export SS_n : out std_logic -- export ); end component wasca_spi_sd_card; component wasca_spi_stm32 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n data_from_cpu : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata data_to_cpu : out std_logic_vector(15 downto 0); -- readdata mem_addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- address read_n : in std_logic := 'X'; -- read_n spi_select : in std_logic := 'X'; -- chipselect write_n : in std_logic := 'X'; -- write_n irq : out std_logic; -- irq MISO : out std_logic; -- export MOSI : in std_logic := 'X'; -- export SCLK : in std_logic := 'X'; -- export SS_n : in std_logic := 'X' -- export ); end component wasca_spi_stm32; component wasca_uart_0 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address begintransfer : in std_logic := 'X'; -- begintransfer chipselect : in std_logic := 'X'; -- chipselect read_n : in std_logic := 'X'; -- read_n write_n : in std_logic := 'X'; -- write_n writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata readdata : out std_logic_vector(15 downto 0); -- readdata dataavailable : out std_logic; -- dataavailable readyfordata : out std_logic; -- readyfordata rxd : in std_logic := 'X'; -- export txd : out std_logic; -- export irq : out std_logic -- irq ); end component wasca_uart_0; component wasca_mm_interconnect_0 is port ( altpll_0_c0_clk : in std_logic := 'X'; -- clk clk_0_clk_clk : in std_logic := 'X'; -- clk altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset nios2_gen2_0_data_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess nios2_gen2_0_instruction_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata sega_saturn_abus_slave_0_avalon_master_address : in std_logic_vector(27 downto 0) := (others => 'X'); -- address sega_saturn_abus_slave_0_avalon_master_waitrequest : out std_logic; -- waitrequest sega_saturn_abus_slave_0_avalon_master_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount sega_saturn_abus_slave_0_avalon_master_read : in std_logic := 'X'; -- read sega_saturn_abus_slave_0_avalon_master_readdata : out std_logic_vector(15 downto 0); -- readdata sega_saturn_abus_slave_0_avalon_master_readdatavalid : out std_logic; -- readdatavalid sega_saturn_abus_slave_0_avalon_master_write : in std_logic := 'X'; -- write sega_saturn_abus_slave_0_avalon_master_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata altpll_0_pll_slave_address : out std_logic_vector(1 downto 0); -- address altpll_0_pll_slave_write : out std_logic; -- write altpll_0_pll_slave_read : out std_logic; -- read altpll_0_pll_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata altpll_0_pll_slave_writedata : out std_logic_vector(31 downto 0); -- writedata audio_0_avalon_audio_slave_address : out std_logic_vector(1 downto 0); -- address audio_0_avalon_audio_slave_write : out std_logic; -- write audio_0_avalon_audio_slave_read : out std_logic; -- read audio_0_avalon_audio_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata audio_0_avalon_audio_slave_writedata : out std_logic_vector(31 downto 0); -- writedata audio_0_avalon_audio_slave_chipselect : out std_logic; -- chipselect external_sdram_controller_s1_address : out std_logic_vector(23 downto 0); -- address external_sdram_controller_s1_write : out std_logic; -- write external_sdram_controller_s1_read : out std_logic; -- read external_sdram_controller_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata external_sdram_controller_s1_writedata : out std_logic_vector(15 downto 0); -- writedata external_sdram_controller_s1_byteenable : out std_logic_vector(1 downto 0); -- byteenable external_sdram_controller_s1_readdatavalid : in std_logic := 'X'; -- readdatavalid external_sdram_controller_s1_waitrequest : in std_logic := 'X'; -- waitrequest external_sdram_controller_s1_chipselect : out std_logic; -- chipselect nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess onchip_flash_0_data_address : out std_logic_vector(15 downto 0); -- address onchip_flash_0_data_read : out std_logic; -- read onchip_flash_0_data_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata onchip_flash_0_data_burstcount : out std_logic_vector(3 downto 0); -- burstcount onchip_flash_0_data_readdatavalid : in std_logic := 'X'; -- readdatavalid onchip_flash_0_data_waitrequest : in std_logic := 'X'; -- waitrequest onchip_memory2_0_s1_address : out std_logic_vector(11 downto 0); -- address onchip_memory2_0_s1_write : out std_logic; -- write onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect onchip_memory2_0_s1_clken : out std_logic; -- clken sega_saturn_abus_slave_0_avalon_nios_address : out std_logic_vector(7 downto 0); -- address sega_saturn_abus_slave_0_avalon_nios_write : out std_logic; -- write sega_saturn_abus_slave_0_avalon_nios_read : out std_logic; -- read sega_saturn_abus_slave_0_avalon_nios_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata sega_saturn_abus_slave_0_avalon_nios_writedata : out std_logic_vector(15 downto 0); -- writedata sega_saturn_abus_slave_0_avalon_nios_burstcount : out std_logic_vector(0 downto 0); -- burstcount sega_saturn_abus_slave_0_avalon_nios_readdatavalid : in std_logic := 'X'; -- readdatavalid sega_saturn_abus_slave_0_avalon_nios_waitrequest : in std_logic := 'X'; -- waitrequest spi_sd_card_spi_control_port_address : out std_logic_vector(2 downto 0); -- address spi_sd_card_spi_control_port_write : out std_logic; -- write spi_sd_card_spi_control_port_read : out std_logic; -- read spi_sd_card_spi_control_port_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata spi_sd_card_spi_control_port_writedata : out std_logic_vector(15 downto 0); -- writedata spi_sd_card_spi_control_port_chipselect : out std_logic; -- chipselect spi_stm32_spi_control_port_address : out std_logic_vector(2 downto 0); -- address spi_stm32_spi_control_port_write : out std_logic; -- write spi_stm32_spi_control_port_read : out std_logic; -- read spi_stm32_spi_control_port_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata spi_stm32_spi_control_port_writedata : out std_logic_vector(15 downto 0); -- writedata spi_stm32_spi_control_port_chipselect : out std_logic; -- chipselect uart_0_s1_address : out std_logic_vector(2 downto 0); -- address uart_0_s1_write : out std_logic; -- write uart_0_s1_read : out std_logic; -- read uart_0_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata uart_0_s1_writedata : out std_logic_vector(15 downto 0); -- writedata uart_0_s1_begintransfer : out std_logic; -- begintransfer uart_0_s1_chipselect : out std_logic -- chipselect ); end component wasca_mm_interconnect_0; component wasca_irq_mapper is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset receiver0_irq : in std_logic := 'X'; -- irq receiver1_irq : in std_logic := 'X'; -- irq receiver2_irq : in std_logic := 'X'; -- irq receiver3_irq : in std_logic := 'X'; -- irq sender_irq : out std_logic_vector(31 downto 0) -- irq ); end component wasca_irq_mapper; component wasca_rst_controller is generic ( NUM_RESET_INPUTS : integer := 6; OUTPUT_RESET_SYNC_EDGES : string := "deassert"; SYNC_DEPTH : integer := 2; RESET_REQUEST_PRESENT : integer := 0; RESET_REQ_WAIT_TIME : integer := 1; MIN_RST_ASSERTION_TIME : integer := 3; RESET_REQ_EARLY_DSRT_TIME : integer := 1; USE_RESET_REQUEST_IN0 : integer := 0; USE_RESET_REQUEST_IN1 : integer := 0; USE_RESET_REQUEST_IN2 : integer := 0; USE_RESET_REQUEST_IN3 : integer := 0; USE_RESET_REQUEST_IN4 : integer := 0; USE_RESET_REQUEST_IN5 : integer := 0; USE_RESET_REQUEST_IN6 : integer := 0; USE_RESET_REQUEST_IN7 : integer := 0; USE_RESET_REQUEST_IN8 : integer := 0; USE_RESET_REQUEST_IN9 : integer := 0; USE_RESET_REQUEST_IN10 : integer := 0; USE_RESET_REQUEST_IN11 : integer := 0; USE_RESET_REQUEST_IN12 : integer := 0; USE_RESET_REQUEST_IN13 : integer := 0; USE_RESET_REQUEST_IN14 : integer := 0; USE_RESET_REQUEST_IN15 : integer := 0; ADAPT_RESET_REQUEST : integer := 0 ); port ( reset_in0 : in std_logic := 'X'; -- reset clk : in std_logic := 'X'; -- clk reset_out : out std_logic; -- reset reset_req : out std_logic; -- reset_req reset_req_in0 : in std_logic := 'X'; -- reset_req reset_in1 : in std_logic := 'X'; -- reset reset_req_in1 : in std_logic := 'X'; -- reset_req reset_in2 : in std_logic := 'X'; -- reset reset_req_in2 : in std_logic := 'X'; -- reset_req reset_in3 : in std_logic := 'X'; -- reset reset_req_in3 : in std_logic := 'X'; -- reset_req reset_in4 : in std_logic := 'X'; -- reset reset_req_in4 : in std_logic := 'X'; -- reset_req reset_in5 : in std_logic := 'X'; -- reset reset_req_in5 : in std_logic := 'X'; -- reset_req reset_in6 : in std_logic := 'X'; -- reset reset_req_in6 : in std_logic := 'X'; -- reset_req reset_in7 : in std_logic := 'X'; -- reset reset_req_in7 : in std_logic := 'X'; -- reset_req reset_in8 : in std_logic := 'X'; -- reset reset_req_in8 : in std_logic := 'X'; -- reset_req reset_in9 : in std_logic := 'X'; -- reset reset_req_in9 : in std_logic := 'X'; -- reset_req reset_in10 : in std_logic := 'X'; -- reset reset_req_in10 : in std_logic := 'X'; -- reset_req reset_in11 : in std_logic := 'X'; -- reset reset_req_in11 : in std_logic := 'X'; -- reset_req reset_in12 : in std_logic := 'X'; -- reset reset_req_in12 : in std_logic := 'X'; -- reset_req reset_in13 : in std_logic := 'X'; -- reset reset_req_in13 : in std_logic := 'X'; -- reset_req reset_in14 : in std_logic := 'X'; -- reset reset_req_in14 : in std_logic := 'X'; -- reset_req reset_in15 : in std_logic := 'X'; -- reset reset_req_in15 : in std_logic := 'X' -- reset_req ); end component wasca_rst_controller; component wasca_rst_controller_001 is generic ( NUM_RESET_INPUTS : integer := 6; OUTPUT_RESET_SYNC_EDGES : string := "deassert"; SYNC_DEPTH : integer := 2; RESET_REQUEST_PRESENT : integer := 0; RESET_REQ_WAIT_TIME : integer := 1; MIN_RST_ASSERTION_TIME : integer := 3; RESET_REQ_EARLY_DSRT_TIME : integer := 1; USE_RESET_REQUEST_IN0 : integer := 0; USE_RESET_REQUEST_IN1 : integer := 0; USE_RESET_REQUEST_IN2 : integer := 0; USE_RESET_REQUEST_IN3 : integer := 0; USE_RESET_REQUEST_IN4 : integer := 0; USE_RESET_REQUEST_IN5 : integer := 0; USE_RESET_REQUEST_IN6 : integer := 0; USE_RESET_REQUEST_IN7 : integer := 0; USE_RESET_REQUEST_IN8 : integer := 0; USE_RESET_REQUEST_IN9 : integer := 0; USE_RESET_REQUEST_IN10 : integer := 0; USE_RESET_REQUEST_IN11 : integer := 0; USE_RESET_REQUEST_IN12 : integer := 0; USE_RESET_REQUEST_IN13 : integer := 0; USE_RESET_REQUEST_IN14 : integer := 0; USE_RESET_REQUEST_IN15 : integer := 0; ADAPT_RESET_REQUEST : integer := 0 ); port ( reset_in0 : in std_logic := 'X'; -- reset clk : in std_logic := 'X'; -- clk reset_out : out std_logic; -- reset reset_req : out std_logic; -- reset_req reset_req_in0 : in std_logic := 'X'; -- reset_req reset_in1 : in std_logic := 'X'; -- reset reset_req_in1 : in std_logic := 'X'; -- reset_req reset_in2 : in std_logic := 'X'; -- reset reset_req_in2 : in std_logic := 'X'; -- reset_req reset_in3 : in std_logic := 'X'; -- reset reset_req_in3 : in std_logic := 'X'; -- reset_req reset_in4 : in std_logic := 'X'; -- reset reset_req_in4 : in std_logic := 'X'; -- reset_req reset_in5 : in std_logic := 'X'; -- reset reset_req_in5 : in std_logic := 'X'; -- reset_req reset_in6 : in std_logic := 'X'; -- reset reset_req_in6 : in std_logic := 'X'; -- reset_req reset_in7 : in std_logic := 'X'; -- reset reset_req_in7 : in std_logic := 'X'; -- reset_req reset_in8 : in std_logic := 'X'; -- reset reset_req_in8 : in std_logic := 'X'; -- reset_req reset_in9 : in std_logic := 'X'; -- reset reset_req_in9 : in std_logic := 'X'; -- reset_req reset_in10 : in std_logic := 'X'; -- reset reset_req_in10 : in std_logic := 'X'; -- reset_req reset_in11 : in std_logic := 'X'; -- reset reset_req_in11 : in std_logic := 'X'; -- reset_req reset_in12 : in std_logic := 'X'; -- reset reset_req_in12 : in std_logic := 'X'; -- reset_req reset_in13 : in std_logic := 'X'; -- reset reset_req_in13 : in std_logic := 'X'; -- reset_req reset_in14 : in std_logic := 'X'; -- reset reset_req_in14 : in std_logic := 'X'; -- reset_req reset_in15 : in std_logic := 'X'; -- reset reset_req_in15 : in std_logic := 'X' -- reset_req ); end component wasca_rst_controller_001; signal altpll_0_c0_clk : std_logic; -- altpll_0:c0 -> [clock_116_mhz_clk, audio_0:clk, external_sdram_controller:clk, irq_mapper:clk, mm_interconnect_0:altpll_0_c0_clk, nios2_gen2_0:clk, onchip_flash_0:clock, onchip_memory2_0:clk, rst_controller_001:clk, rst_controller_002:clk, sega_saturn_abus_slave_0:clock, spi_sd_card:clk, spi_stm32:clk, uart_0:clk] signal nios2_gen2_0_debug_reset_request_reset : std_logic; -- nios2_gen2_0:debug_reset_request -> [rst_controller:reset_in0, rst_controller_001:reset_in0, rst_controller_002:reset_in0] signal sega_saturn_abus_slave_0_avalon_master_waitrequest : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_waitrequest -> sega_saturn_abus_slave_0:avalon_waitrequest signal sega_saturn_abus_slave_0_avalon_master_readdata : std_logic_vector(15 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_readdata -> sega_saturn_abus_slave_0:avalon_readdata signal sega_saturn_abus_slave_0_avalon_master_read : std_logic; -- sega_saturn_abus_slave_0:avalon_read -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_read signal sega_saturn_abus_slave_0_avalon_master_address : std_logic_vector(27 downto 0); -- sega_saturn_abus_slave_0:avalon_address -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_address signal sega_saturn_abus_slave_0_avalon_master_readdatavalid : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_readdatavalid -> sega_saturn_abus_slave_0:avalon_readdatavalid signal sega_saturn_abus_slave_0_avalon_master_write : std_logic; -- sega_saturn_abus_slave_0:avalon_write -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_write signal sega_saturn_abus_slave_0_avalon_master_writedata : std_logic_vector(15 downto 0); -- sega_saturn_abus_slave_0:avalon_writedata -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_writedata signal sega_saturn_abus_slave_0_avalon_master_burstcount : std_logic; -- sega_saturn_abus_slave_0:avalon_burstcount -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_burstcount signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess signal nios2_gen2_0_data_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest signal nios2_gen2_0_instruction_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read signal mm_interconnect_0_external_sdram_controller_s1_chipselect : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_chipselect -> external_sdram_controller:az_cs signal mm_interconnect_0_external_sdram_controller_s1_readdata : std_logic_vector(15 downto 0); -- external_sdram_controller:za_data -> mm_interconnect_0:external_sdram_controller_s1_readdata signal mm_interconnect_0_external_sdram_controller_s1_waitrequest : std_logic; -- external_sdram_controller:za_waitrequest -> mm_interconnect_0:external_sdram_controller_s1_waitrequest signal mm_interconnect_0_external_sdram_controller_s1_address : std_logic_vector(23 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_address -> external_sdram_controller:az_addr signal mm_interconnect_0_external_sdram_controller_s1_read : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_read -> mm_interconnect_0_external_sdram_controller_s1_read:in signal mm_interconnect_0_external_sdram_controller_s1_byteenable : std_logic_vector(1 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_byteenable -> mm_interconnect_0_external_sdram_controller_s1_byteenable:in signal mm_interconnect_0_external_sdram_controller_s1_readdatavalid : std_logic; -- external_sdram_controller:za_valid -> mm_interconnect_0:external_sdram_controller_s1_readdatavalid signal mm_interconnect_0_external_sdram_controller_s1_write : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_write -> mm_interconnect_0_external_sdram_controller_s1_write:in signal mm_interconnect_0_external_sdram_controller_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_writedata -> external_sdram_controller:az_data signal mm_interconnect_0_onchip_flash_0_data_readdata : std_logic_vector(31 downto 0); -- onchip_flash_0:avmm_data_readdata -> mm_interconnect_0:onchip_flash_0_data_readdata signal mm_interconnect_0_onchip_flash_0_data_waitrequest : std_logic; -- onchip_flash_0:avmm_data_waitrequest -> mm_interconnect_0:onchip_flash_0_data_waitrequest signal mm_interconnect_0_onchip_flash_0_data_address : std_logic_vector(15 downto 0); -- mm_interconnect_0:onchip_flash_0_data_address -> onchip_flash_0:avmm_data_addr signal mm_interconnect_0_onchip_flash_0_data_read : std_logic; -- mm_interconnect_0:onchip_flash_0_data_read -> onchip_flash_0:avmm_data_read signal mm_interconnect_0_onchip_flash_0_data_readdatavalid : std_logic; -- onchip_flash_0:avmm_data_readdatavalid -> mm_interconnect_0:onchip_flash_0_data_readdatavalid signal mm_interconnect_0_onchip_flash_0_data_burstcount : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_flash_0_data_burstcount -> onchip_flash_0:avmm_data_burstcount signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(11 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken signal mm_interconnect_0_audio_0_avalon_audio_slave_chipselect : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_chipselect -> audio_0:chipselect signal mm_interconnect_0_audio_0_avalon_audio_slave_readdata : std_logic_vector(31 downto 0); -- audio_0:readdata -> mm_interconnect_0:audio_0_avalon_audio_slave_readdata signal mm_interconnect_0_audio_0_avalon_audio_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:audio_0_avalon_audio_slave_address -> audio_0:address signal mm_interconnect_0_audio_0_avalon_audio_slave_read : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_read -> audio_0:read signal mm_interconnect_0_audio_0_avalon_audio_slave_write : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_write -> audio_0:write signal mm_interconnect_0_audio_0_avalon_audio_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:audio_0_avalon_audio_slave_writedata -> audio_0:writedata signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata : std_logic_vector(15 downto 0); -- sega_saturn_abus_slave_0:avalon_nios_readdata -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_readdata signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest : std_logic; -- sega_saturn_abus_slave_0:avalon_nios_waitrequest -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_waitrequest signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_address -> sega_saturn_abus_slave_0:avalon_nios_address signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_read -> sega_saturn_abus_slave_0:avalon_nios_read signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid : std_logic; -- sega_saturn_abus_slave_0:avalon_nios_readdatavalid -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_readdatavalid signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_write -> sega_saturn_abus_slave_0:avalon_nios_write signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_writedata -> sega_saturn_abus_slave_0:avalon_nios_writedata signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount : std_logic_vector(0 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_burstcount -> sega_saturn_abus_slave_0:avalon_nios_burstcount signal mm_interconnect_0_altpll_0_pll_slave_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> mm_interconnect_0:altpll_0_pll_slave_readdata signal mm_interconnect_0_altpll_0_pll_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_address -> altpll_0:address signal mm_interconnect_0_altpll_0_pll_slave_read : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_read -> altpll_0:read signal mm_interconnect_0_altpll_0_pll_slave_write : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_write -> altpll_0:write signal mm_interconnect_0_altpll_0_pll_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_writedata -> altpll_0:writedata signal mm_interconnect_0_uart_0_s1_chipselect : std_logic; -- mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect signal mm_interconnect_0_uart_0_s1_readdata : std_logic_vector(15 downto 0); -- uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata signal mm_interconnect_0_uart_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:uart_0_s1_address -> uart_0:address signal mm_interconnect_0_uart_0_s1_read : std_logic; -- mm_interconnect_0:uart_0_s1_read -> mm_interconnect_0_uart_0_s1_read:in signal mm_interconnect_0_uart_0_s1_begintransfer : std_logic; -- mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer signal mm_interconnect_0_uart_0_s1_write : std_logic; -- mm_interconnect_0:uart_0_s1_write -> mm_interconnect_0_uart_0_s1_write:in signal mm_interconnect_0_uart_0_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata signal mm_interconnect_0_spi_sd_card_spi_control_port_chipselect : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_chipselect -> spi_sd_card:spi_select signal mm_interconnect_0_spi_sd_card_spi_control_port_readdata : std_logic_vector(15 downto 0); -- spi_sd_card:data_to_cpu -> mm_interconnect_0:spi_sd_card_spi_control_port_readdata signal mm_interconnect_0_spi_sd_card_spi_control_port_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:spi_sd_card_spi_control_port_address -> spi_sd_card:mem_addr signal mm_interconnect_0_spi_sd_card_spi_control_port_read : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_read -> mm_interconnect_0_spi_sd_card_spi_control_port_read:in signal mm_interconnect_0_spi_sd_card_spi_control_port_write : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_write -> mm_interconnect_0_spi_sd_card_spi_control_port_write:in signal mm_interconnect_0_spi_sd_card_spi_control_port_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:spi_sd_card_spi_control_port_writedata -> spi_sd_card:data_from_cpu signal mm_interconnect_0_spi_stm32_spi_control_port_chipselect : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_chipselect -> spi_stm32:spi_select signal mm_interconnect_0_spi_stm32_spi_control_port_readdata : std_logic_vector(15 downto 0); -- spi_stm32:data_to_cpu -> mm_interconnect_0:spi_stm32_spi_control_port_readdata signal mm_interconnect_0_spi_stm32_spi_control_port_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:spi_stm32_spi_control_port_address -> spi_stm32:mem_addr signal mm_interconnect_0_spi_stm32_spi_control_port_read : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_read -> mm_interconnect_0_spi_stm32_spi_control_port_read:in signal mm_interconnect_0_spi_stm32_spi_control_port_write : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_write -> mm_interconnect_0_spi_stm32_spi_control_port_write:in signal mm_interconnect_0_spi_stm32_spi_control_port_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:spi_stm32_spi_control_port_writedata -> spi_stm32:data_from_cpu signal irq_mapper_receiver0_irq : std_logic; -- audio_0:irq -> irq_mapper:receiver0_irq signal irq_mapper_receiver1_irq : std_logic; -- uart_0:irq -> irq_mapper:receiver1_irq signal irq_mapper_receiver2_irq : std_logic; -- spi_sd_card:irq -> irq_mapper:receiver2_irq signal irq_mapper_receiver3_irq : std_logic; -- spi_stm32:irq -> irq_mapper:receiver3_irq signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [altpll_0:reset, mm_interconnect_0:altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset] signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [audio_0:reset, irq_mapper:reset, mm_interconnect_0:sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_001_reset_out_reset:in, rst_translator:in_reset, sega_saturn_abus_slave_0:reset] signal rst_controller_001_reset_out_reset_req : std_logic; -- rst_controller_001:reset_req -> [onchip_memory2_0:reset_req, rst_translator:reset_req_in] signal mm_interconnect_0_external_sdram_controller_s1_read_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_read:inv -> external_sdram_controller:az_rd_n signal mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv : std_logic_vector(1 downto 0); -- mm_interconnect_0_external_sdram_controller_s1_byteenable:inv -> external_sdram_controller:az_be_n signal mm_interconnect_0_external_sdram_controller_s1_write_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_write:inv -> external_sdram_controller:az_wr_n signal mm_interconnect_0_uart_0_s1_read_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_read:inv -> uart_0:read_n signal mm_interconnect_0_uart_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_write:inv -> uart_0:write_n signal mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv : std_logic; -- mm_interconnect_0_spi_sd_card_spi_control_port_read:inv -> spi_sd_card:read_n signal mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv : std_logic; -- mm_interconnect_0_spi_sd_card_spi_control_port_write:inv -> spi_sd_card:write_n signal mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv : std_logic; -- mm_interconnect_0_spi_stm32_spi_control_port_read:inv -> spi_stm32:read_n signal mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv : std_logic; -- mm_interconnect_0_spi_stm32_spi_control_port_write:inv -> spi_stm32:write_n signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> [external_sdram_controller:reset_n, nios2_gen2_0:reset_n, onchip_flash_0:reset_n, spi_sd_card:reset_n, spi_stm32:reset_n, uart_0:reset_n] begin altpll_0 : component wasca_altpll_0 port map ( clk => clk_clk, -- inclk_interface.clk reset => rst_controller_reset_out_reset, -- inclk_interface_reset.reset read => mm_interconnect_0_altpll_0_pll_slave_read, -- pll_slave.read write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write address => mm_interconnect_0_altpll_0_pll_slave_address, -- .address readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata c0 => altpll_0_c0_clk, -- c0.clk areset => altpll_0_areset_conduit_export, -- areset_conduit.export c1 => open, -- c1_conduit.export locked => altpll_0_locked_conduit_export, -- locked_conduit.export phasedone => altpll_0_phasedone_conduit_export -- phasedone_conduit.export ); audio_0 : component wasca_audio_0 port map ( clk => altpll_0_c0_clk, -- clk.clk reset => rst_controller_001_reset_out_reset, -- reset.reset address => mm_interconnect_0_audio_0_avalon_audio_slave_address, -- avalon_audio_slave.address chipselect => mm_interconnect_0_audio_0_avalon_audio_slave_chipselect, -- .chipselect read => mm_interconnect_0_audio_0_avalon_audio_slave_read, -- .read write => mm_interconnect_0_audio_0_avalon_audio_slave_write, -- .write writedata => mm_interconnect_0_audio_0_avalon_audio_slave_writedata, -- .writedata readdata => mm_interconnect_0_audio_0_avalon_audio_slave_readdata, -- .readdata irq => irq_mapper_receiver0_irq, -- interrupt.irq AUD_BCLK => audio_out_BCLK, -- external_interface.export AUD_DACDAT => audio_out_DACDAT, -- .export AUD_DACLRCK => audio_out_DACLRCK -- .export ); external_sdram_controller : component wasca_external_sdram_controller port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n az_addr => mm_interconnect_0_external_sdram_controller_s1_address, -- s1.address az_be_n => mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv, -- .byteenable_n az_cs => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect az_data => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata az_rd_n => mm_interconnect_0_external_sdram_controller_s1_read_ports_inv, -- .read_n az_wr_n => mm_interconnect_0_external_sdram_controller_s1_write_ports_inv, -- .write_n za_data => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata za_valid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid za_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest zs_addr => external_sdram_controller_wire_addr, -- wire.export zs_ba => external_sdram_controller_wire_ba, -- .export zs_cas_n => external_sdram_controller_wire_cas_n, -- .export zs_cke => external_sdram_controller_wire_cke, -- .export zs_cs_n => external_sdram_controller_wire_cs_n, -- .export zs_dq => external_sdram_controller_wire_dq, -- .export zs_dqm => external_sdram_controller_wire_dqm, -- .export zs_ras_n => external_sdram_controller_wire_ras_n, -- .export zs_we_n => external_sdram_controller_wire_we_n -- .export ); nios2_gen2_0 : component wasca_nios2_gen2_0 port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n d_address => nios2_gen2_0_data_master_address, -- data_master.address d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable d_read => nios2_gen2_0_data_master_read, -- .read d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest d_write => nios2_gen2_0_data_master_write, -- .write d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address i_read => nios2_gen2_0_instruction_master_read, -- .read i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest irq => nios2_gen2_0_irq_irq, -- irq.irq debug_reset_request => nios2_gen2_0_debug_reset_request_reset, -- debug_reset_request.reset debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata dummy_ci_port => open -- custom_instruction_master.readra ); onchip_flash_0 : component altera_onchip_flash generic map ( INIT_FILENAME => "", INIT_FILENAME_SIM => "", DEVICE_FAMILY => "MAX 10", PART_NAME => "10M08SAE144C8GES", DEVICE_ID => "08", SECTOR1_START_ADDR => 0, SECTOR1_END_ADDR => 4095, SECTOR2_START_ADDR => 4096, SECTOR2_END_ADDR => 8191, SECTOR3_START_ADDR => 8192, SECTOR3_END_ADDR => 29183, SECTOR4_START_ADDR => 29184, SECTOR4_END_ADDR => 44031, SECTOR5_START_ADDR => 0, SECTOR5_END_ADDR => 0, MIN_VALID_ADDR => 0, MAX_VALID_ADDR => 44031, MIN_UFM_VALID_ADDR => 0, MAX_UFM_VALID_ADDR => 44031, SECTOR1_MAP => 1, SECTOR2_MAP => 2, SECTOR3_MAP => 3, SECTOR4_MAP => 4, SECTOR5_MAP => 0, ADDR_RANGE1_END_ADDR => 44031, ADDR_RANGE1_OFFSET => 512, ADDR_RANGE2_OFFSET => 0, AVMM_DATA_ADDR_WIDTH => 16, AVMM_DATA_DATA_WIDTH => 32, AVMM_DATA_BURSTCOUNT_WIDTH => 4, SECTOR_READ_PROTECTION_MODE => 31, FLASH_SEQ_READ_DATA_COUNT => 2, FLASH_ADDR_ALIGNMENT_BITS => 1, FLASH_READ_CYCLE_MAX_INDEX => 3, FLASH_RESET_CYCLE_MAX_INDEX => 29, FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX => 111, FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX => 40603248, FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX => 35382, PARALLEL_MODE => true, READ_AND_WRITE_MODE => false, WRAPPING_BURST_MODE => false, IS_DUAL_BOOT => "False", IS_ERAM_SKIP => "True", IS_COMPRESSED_IMAGE => "True" ) port map ( clock => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- nreset.reset_n avmm_data_addr => mm_interconnect_0_onchip_flash_0_data_address, -- data.address avmm_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read avmm_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata avmm_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest avmm_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid avmm_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount avmm_data_writedata => "00000000000000000000000000000000", -- (terminated) avmm_data_write => '0', -- (terminated) avmm_csr_addr => '0', -- (terminated) avmm_csr_read => '0', -- (terminated) avmm_csr_writedata => "00000000000000000000000000000000", -- (terminated) avmm_csr_write => '0', -- (terminated) avmm_csr_readdata => open -- (terminated) ); onchip_memory2_0 : component wasca_onchip_memory2_0 port map ( clk => altpll_0_c0_clk, -- clk1.clk address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable reset => rst_controller_001_reset_out_reset, -- reset1.reset reset_req => rst_controller_001_reset_out_reset_req -- .reset_req ); sega_saturn_abus_slave_0 : component sega_saturn_abus_slave port map ( clock => altpll_0_c0_clk, -- clock.clk abus_address => sega_saturn_abus_slave_0_abus_address, -- abus.address abus_chipselect => sega_saturn_abus_slave_0_abus_chipselect, -- .chipselect abus_read => sega_saturn_abus_slave_0_abus_read, -- .read abus_write => sega_saturn_abus_slave_0_abus_write, -- .write abus_waitrequest => sega_saturn_abus_slave_0_abus_waitrequest, -- .waitrequest abus_interrupt => sega_saturn_abus_slave_0_abus_interrupt, -- .interrupt abus_addressdata => sega_saturn_abus_slave_0_abus_addressdata, -- .addressdata abus_direction => sega_saturn_abus_slave_0_abus_direction, -- .direction abus_muxing => sega_saturn_abus_slave_0_abus_muxing, -- .muxing abus_disable_out => sega_saturn_abus_slave_0_abus_disableout, -- .disableout avalon_read => sega_saturn_abus_slave_0_avalon_master_read, -- avalon_master.read avalon_write => sega_saturn_abus_slave_0_avalon_master_write, -- .write avalon_waitrequest => sega_saturn_abus_slave_0_avalon_master_waitrequest, -- .waitrequest avalon_address => sega_saturn_abus_slave_0_avalon_master_address, -- .address avalon_readdata => sega_saturn_abus_slave_0_avalon_master_readdata, -- .readdata avalon_writedata => sega_saturn_abus_slave_0_avalon_master_writedata, -- .writedata avalon_readdatavalid => sega_saturn_abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid avalon_burstcount => sega_saturn_abus_slave_0_avalon_master_burstcount, -- .burstcount reset => rst_controller_001_reset_out_reset, -- reset.reset saturn_reset => sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset, -- conduit_saturn_reset.saturn_reset avalon_nios_read => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read, -- avalon_nios.read avalon_nios_write => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write, -- .write avalon_nios_address => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address, -- .address avalon_nios_writedata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata, -- .writedata avalon_nios_readdata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata, -- .readdata avalon_nios_waitrequest => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest avalon_nios_readdatavalid => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid avalon_nios_burstcount => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount(0) -- .burstcount ); spi_sd_card : component wasca_spi_sd_card port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n data_from_cpu => mm_interconnect_0_spi_sd_card_spi_control_port_writedata, -- spi_control_port.writedata data_to_cpu => mm_interconnect_0_spi_sd_card_spi_control_port_readdata, -- .readdata mem_addr => mm_interconnect_0_spi_sd_card_spi_control_port_address, -- .address read_n => mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv, -- .read_n spi_select => mm_interconnect_0_spi_sd_card_spi_control_port_chipselect, -- .chipselect write_n => mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv, -- .write_n irq => irq_mapper_receiver2_irq, -- irq.irq MISO => spi_sd_card_MISO, -- external.export MOSI => spi_sd_card_MOSI, -- .export SCLK => spi_sd_card_SCLK, -- .export SS_n => spi_sd_card_SS_n -- .export ); spi_stm32 : component wasca_spi_stm32 port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n data_from_cpu => mm_interconnect_0_spi_stm32_spi_control_port_writedata, -- spi_control_port.writedata data_to_cpu => mm_interconnect_0_spi_stm32_spi_control_port_readdata, -- .readdata mem_addr => mm_interconnect_0_spi_stm32_spi_control_port_address, -- .address read_n => mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv, -- .read_n spi_select => mm_interconnect_0_spi_stm32_spi_control_port_chipselect, -- .chipselect write_n => mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv, -- .write_n irq => irq_mapper_receiver3_irq, -- irq.irq MISO => spi_stm32_MISO, -- external.export MOSI => spi_stm32_MOSI, -- .export SCLK => spi_stm32_SCLK, -- .export SS_n => spi_stm32_SS_n -- .export ); uart_0 : component wasca_uart_0 port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n address => mm_interconnect_0_uart_0_s1_address, -- s1.address begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer chipselect => mm_interconnect_0_uart_0_s1_chipselect, -- .chipselect read_n => mm_interconnect_0_uart_0_s1_read_ports_inv, -- .read_n write_n => mm_interconnect_0_uart_0_s1_write_ports_inv, -- .write_n writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata dataavailable => open, -- .dataavailable readyfordata => open, -- .readyfordata rxd => uart_0_external_connection_rxd, -- external_connection.export txd => uart_0_external_connection_txd, -- .export irq => irq_mapper_receiver1_irq -- irq.irq ); mm_interconnect_0 : component wasca_mm_interconnect_0 port map ( altpll_0_c0_clk => altpll_0_c0_clk, -- altpll_0_c0.clk clk_0_clk_clk => clk_clk, -- clk_0_clk.clk altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- sega_saturn_abus_slave_0_reset_reset_bridge_in_reset.reset nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata sega_saturn_abus_slave_0_avalon_master_address => sega_saturn_abus_slave_0_avalon_master_address, -- sega_saturn_abus_slave_0_avalon_master.address sega_saturn_abus_slave_0_avalon_master_waitrequest => sega_saturn_abus_slave_0_avalon_master_waitrequest, -- .waitrequest sega_saturn_abus_slave_0_avalon_master_burstcount(0) => sega_saturn_abus_slave_0_avalon_master_burstcount, -- .burstcount sega_saturn_abus_slave_0_avalon_master_read => sega_saturn_abus_slave_0_avalon_master_read, -- .read sega_saturn_abus_slave_0_avalon_master_readdata => sega_saturn_abus_slave_0_avalon_master_readdata, -- .readdata sega_saturn_abus_slave_0_avalon_master_readdatavalid => sega_saturn_abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid sega_saturn_abus_slave_0_avalon_master_write => sega_saturn_abus_slave_0_avalon_master_write, -- .write sega_saturn_abus_slave_0_avalon_master_writedata => sega_saturn_abus_slave_0_avalon_master_writedata, -- .writedata altpll_0_pll_slave_address => mm_interconnect_0_altpll_0_pll_slave_address, -- altpll_0_pll_slave.address altpll_0_pll_slave_write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write altpll_0_pll_slave_read => mm_interconnect_0_altpll_0_pll_slave_read, -- .read altpll_0_pll_slave_readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata altpll_0_pll_slave_writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata audio_0_avalon_audio_slave_address => mm_interconnect_0_audio_0_avalon_audio_slave_address, -- audio_0_avalon_audio_slave.address audio_0_avalon_audio_slave_write => mm_interconnect_0_audio_0_avalon_audio_slave_write, -- .write audio_0_avalon_audio_slave_read => mm_interconnect_0_audio_0_avalon_audio_slave_read, -- .read audio_0_avalon_audio_slave_readdata => mm_interconnect_0_audio_0_avalon_audio_slave_readdata, -- .readdata audio_0_avalon_audio_slave_writedata => mm_interconnect_0_audio_0_avalon_audio_slave_writedata, -- .writedata audio_0_avalon_audio_slave_chipselect => mm_interconnect_0_audio_0_avalon_audio_slave_chipselect, -- .chipselect external_sdram_controller_s1_address => mm_interconnect_0_external_sdram_controller_s1_address, -- external_sdram_controller_s1.address external_sdram_controller_s1_write => mm_interconnect_0_external_sdram_controller_s1_write, -- .write external_sdram_controller_s1_read => mm_interconnect_0_external_sdram_controller_s1_read, -- .read external_sdram_controller_s1_readdata => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata external_sdram_controller_s1_writedata => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata external_sdram_controller_s1_byteenable => mm_interconnect_0_external_sdram_controller_s1_byteenable, -- .byteenable external_sdram_controller_s1_readdatavalid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid external_sdram_controller_s1_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest external_sdram_controller_s1_chipselect => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess onchip_flash_0_data_address => mm_interconnect_0_onchip_flash_0_data_address, -- onchip_flash_0_data.address onchip_flash_0_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read onchip_flash_0_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata onchip_flash_0_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount onchip_flash_0_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid onchip_flash_0_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken sega_saturn_abus_slave_0_avalon_nios_address => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address, -- sega_saturn_abus_slave_0_avalon_nios.address sega_saturn_abus_slave_0_avalon_nios_write => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write, -- .write sega_saturn_abus_slave_0_avalon_nios_read => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read, -- .read sega_saturn_abus_slave_0_avalon_nios_readdata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata, -- .readdata sega_saturn_abus_slave_0_avalon_nios_writedata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata, -- .writedata sega_saturn_abus_slave_0_avalon_nios_burstcount => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount, -- .burstcount sega_saturn_abus_slave_0_avalon_nios_readdatavalid => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid sega_saturn_abus_slave_0_avalon_nios_waitrequest => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest spi_sd_card_spi_control_port_address => mm_interconnect_0_spi_sd_card_spi_control_port_address, -- spi_sd_card_spi_control_port.address spi_sd_card_spi_control_port_write => mm_interconnect_0_spi_sd_card_spi_control_port_write, -- .write spi_sd_card_spi_control_port_read => mm_interconnect_0_spi_sd_card_spi_control_port_read, -- .read spi_sd_card_spi_control_port_readdata => mm_interconnect_0_spi_sd_card_spi_control_port_readdata, -- .readdata spi_sd_card_spi_control_port_writedata => mm_interconnect_0_spi_sd_card_spi_control_port_writedata, -- .writedata spi_sd_card_spi_control_port_chipselect => mm_interconnect_0_spi_sd_card_spi_control_port_chipselect, -- .chipselect spi_stm32_spi_control_port_address => mm_interconnect_0_spi_stm32_spi_control_port_address, -- spi_stm32_spi_control_port.address spi_stm32_spi_control_port_write => mm_interconnect_0_spi_stm32_spi_control_port_write, -- .write spi_stm32_spi_control_port_read => mm_interconnect_0_spi_stm32_spi_control_port_read, -- .read spi_stm32_spi_control_port_readdata => mm_interconnect_0_spi_stm32_spi_control_port_readdata, -- .readdata spi_stm32_spi_control_port_writedata => mm_interconnect_0_spi_stm32_spi_control_port_writedata, -- .writedata spi_stm32_spi_control_port_chipselect => mm_interconnect_0_spi_stm32_spi_control_port_chipselect, -- .chipselect uart_0_s1_address => mm_interconnect_0_uart_0_s1_address, -- uart_0_s1.address uart_0_s1_write => mm_interconnect_0_uart_0_s1_write, -- .write uart_0_s1_read => mm_interconnect_0_uart_0_s1_read, -- .read uart_0_s1_readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata uart_0_s1_writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata uart_0_s1_begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer uart_0_s1_chipselect => mm_interconnect_0_uart_0_s1_chipselect -- .chipselect ); irq_mapper : component wasca_irq_mapper port map ( clk => altpll_0_c0_clk, -- clk.clk reset => rst_controller_001_reset_out_reset, -- clk_reset.reset receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq receiver2_irq => irq_mapper_receiver2_irq, -- receiver2.irq receiver3_irq => irq_mapper_receiver3_irq, -- receiver3.irq sender_irq => nios2_gen2_0_irq_irq -- sender.irq ); rst_controller : component wasca_rst_controller generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "deassert", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 0, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset clk => clk_clk, -- clk.clk reset_out => rst_controller_reset_out_reset, -- reset_out.reset reset_req => open, -- (terminated) reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); rst_controller_001 : component wasca_rst_controller_001 generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "deassert", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 1, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset clk => altpll_0_c0_clk, -- clk.clk reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); rst_controller_002 : component wasca_rst_controller generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "both", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 0, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset clk => altpll_0_c0_clk, -- clk.clk reset_out => open, -- reset_out.reset reset_req => open, -- (terminated) reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); mm_interconnect_0_external_sdram_controller_s1_read_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_read; mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_byteenable; mm_interconnect_0_external_sdram_controller_s1_write_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_write; mm_interconnect_0_uart_0_s1_read_ports_inv <= not mm_interconnect_0_uart_0_s1_read; mm_interconnect_0_uart_0_s1_write_ports_inv <= not mm_interconnect_0_uart_0_s1_write; mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv <= not mm_interconnect_0_spi_sd_card_spi_control_port_read; mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv <= not mm_interconnect_0_spi_sd_card_spi_control_port_write; mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv <= not mm_interconnect_0_spi_stm32_spi_control_port_read; mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv <= not mm_interconnect_0_spi_stm32_spi_control_port_write; rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset; clock_116_mhz_clk <= altpll_0_c0_clk; end architecture rtl; -- of wasca
-- wasca.vhd -- Generated using ACDS version 15.0 145 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity wasca is port ( altpll_0_areset_conduit_export : in std_logic := '0'; -- altpll_0_areset_conduit.export altpll_0_locked_conduit_export : out std_logic; -- altpll_0_locked_conduit.export altpll_0_phasedone_conduit_export : out std_logic; -- altpll_0_phasedone_conduit.export audio_out_BCLK : in std_logic := '0'; -- audio_out.BCLK audio_out_DACDAT : out std_logic; -- .DACDAT audio_out_DACLRCK : in std_logic := '0'; -- .DACLRCK clk_clk : in std_logic := '0'; -- clk.clk clock_116_mhz_clk : out std_logic; -- clock_116_mhz.clk external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n external_sdram_controller_wire_cke : out std_logic; -- .cke external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n external_sdram_controller_wire_we_n : out std_logic; -- .we_n sega_saturn_abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- sega_saturn_abus_slave_0_abus.address sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect sega_saturn_abus_slave_0_abus_read : in std_logic := '0'; -- .read sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest sega_saturn_abus_slave_0_abus_interrupt : out std_logic; -- .interrupt sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .addressdata sega_saturn_abus_slave_0_abus_direction : out std_logic; -- .direction sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- .muxing sega_saturn_abus_slave_0_abus_disableout : out std_logic; -- .disableout sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := '0'; -- sega_saturn_abus_slave_0_conduit_saturn_reset.saturn_reset spi_sd_card_MISO : in std_logic := '0'; -- spi_sd_card.MISO spi_sd_card_MOSI : out std_logic; -- .MOSI spi_sd_card_SCLK : out std_logic; -- .SCLK spi_sd_card_SS_n : out std_logic; -- .SS_n spi_stm32_MISO : out std_logic; -- spi_stm32.MISO spi_stm32_MOSI : in std_logic := '0'; -- .MOSI spi_stm32_SCLK : in std_logic := '0'; -- .SCLK spi_stm32_SS_n : in std_logic := '0'; -- .SS_n uart_0_external_connection_rxd : in std_logic := '0'; -- uart_0_external_connection.rxd uart_0_external_connection_txd : out std_logic -- .txd ); end entity wasca; architecture rtl of wasca is component wasca_altpll_0 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset read : in std_logic := 'X'; -- read write : in std_logic := 'X'; -- write address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address readdata : out std_logic_vector(31 downto 0); -- readdata writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata c0 : out std_logic; -- clk areset : in std_logic := 'X'; -- export c1 : out std_logic; -- export locked : out std_logic; -- export phasedone : out std_logic -- export ); end component wasca_altpll_0; component wasca_audio_0 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address chipselect : in std_logic := 'X'; -- chipselect read : in std_logic := 'X'; -- read write : in std_logic := 'X'; -- write writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata readdata : out std_logic_vector(31 downto 0); -- readdata irq : out std_logic; -- irq AUD_BCLK : in std_logic := 'X'; -- export AUD_DACDAT : out std_logic; -- export AUD_DACLRCK : in std_logic := 'X' -- export ); end component wasca_audio_0; component wasca_external_sdram_controller is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n az_addr : in std_logic_vector(23 downto 0) := (others => 'X'); -- address az_be_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable_n az_cs : in std_logic := 'X'; -- chipselect az_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata az_rd_n : in std_logic := 'X'; -- read_n az_wr_n : in std_logic := 'X'; -- write_n za_data : out std_logic_vector(15 downto 0); -- readdata za_valid : out std_logic; -- readdatavalid za_waitrequest : out std_logic; -- waitrequest zs_addr : out std_logic_vector(12 downto 0); -- export zs_ba : out std_logic_vector(1 downto 0); -- export zs_cas_n : out std_logic; -- export zs_cke : out std_logic; -- export zs_cs_n : out std_logic; -- export zs_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export zs_dqm : out std_logic_vector(1 downto 0); -- export zs_ras_n : out std_logic; -- export zs_we_n : out std_logic -- export ); end component wasca_external_sdram_controller; component wasca_nios2_gen2_0 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n d_address : out std_logic_vector(26 downto 0); -- address d_byteenable : out std_logic_vector(3 downto 0); -- byteenable d_read : out std_logic; -- read d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata d_waitrequest : in std_logic := 'X'; -- waitrequest d_write : out std_logic; -- write d_writedata : out std_logic_vector(31 downto 0); -- writedata debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess i_address : out std_logic_vector(26 downto 0); -- address i_read : out std_logic; -- read i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata i_waitrequest : in std_logic := 'X'; -- waitrequest irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq debug_reset_request : out std_logic; -- reset debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess debug_mem_slave_read : in std_logic := 'X'; -- read debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata debug_mem_slave_waitrequest : out std_logic; -- waitrequest debug_mem_slave_write : in std_logic := 'X'; -- write debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata dummy_ci_port : out std_logic -- readra ); end component wasca_nios2_gen2_0; component altera_onchip_flash is generic ( INIT_FILENAME : string := ""; INIT_FILENAME_SIM : string := ""; DEVICE_FAMILY : string := "Unknown"; PART_NAME : string := "Unknown"; DEVICE_ID : string := "Unknown"; SECTOR1_START_ADDR : integer := 0; SECTOR1_END_ADDR : integer := 0; SECTOR2_START_ADDR : integer := 0; SECTOR2_END_ADDR : integer := 0; SECTOR3_START_ADDR : integer := 0; SECTOR3_END_ADDR : integer := 0; SECTOR4_START_ADDR : integer := 0; SECTOR4_END_ADDR : integer := 0; SECTOR5_START_ADDR : integer := 0; SECTOR5_END_ADDR : integer := 0; MIN_VALID_ADDR : integer := 0; MAX_VALID_ADDR : integer := 0; MIN_UFM_VALID_ADDR : integer := 0; MAX_UFM_VALID_ADDR : integer := 0; SECTOR1_MAP : integer := 0; SECTOR2_MAP : integer := 0; SECTOR3_MAP : integer := 0; SECTOR4_MAP : integer := 0; SECTOR5_MAP : integer := 0; ADDR_RANGE1_END_ADDR : integer := 0; ADDR_RANGE1_OFFSET : integer := 0; ADDR_RANGE2_OFFSET : integer := 0; AVMM_DATA_ADDR_WIDTH : integer := 19; AVMM_DATA_DATA_WIDTH : integer := 32; AVMM_DATA_BURSTCOUNT_WIDTH : integer := 4; SECTOR_READ_PROTECTION_MODE : integer := 31; FLASH_SEQ_READ_DATA_COUNT : integer := 2; FLASH_ADDR_ALIGNMENT_BITS : integer := 1; FLASH_READ_CYCLE_MAX_INDEX : integer := 4; FLASH_RESET_CYCLE_MAX_INDEX : integer := 29; FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX : integer := 112; FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX : integer := 40603248; FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX : integer := 35382; PARALLEL_MODE : boolean := true; READ_AND_WRITE_MODE : boolean := true; WRAPPING_BURST_MODE : boolean := false; IS_DUAL_BOOT : string := "False"; IS_ERAM_SKIP : string := "False"; IS_COMPRESSED_IMAGE : string := "False" ); port ( clock : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n avmm_data_addr : in std_logic_vector(15 downto 0) := (others => 'X'); -- address avmm_data_read : in std_logic := 'X'; -- read avmm_data_readdata : out std_logic_vector(31 downto 0); -- readdata avmm_data_waitrequest : out std_logic; -- waitrequest avmm_data_readdatavalid : out std_logic; -- readdatavalid avmm_data_burstcount : in std_logic_vector(3 downto 0) := (others => 'X'); -- burstcount avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata avmm_data_write : in std_logic := 'X'; -- write avmm_csr_addr : in std_logic := 'X'; -- address avmm_csr_read : in std_logic := 'X'; -- read avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata avmm_csr_write : in std_logic := 'X'; -- write avmm_csr_readdata : out std_logic_vector(31 downto 0) -- readdata ); end component altera_onchip_flash; component wasca_onchip_memory2_0 is port ( clk : in std_logic := 'X'; -- clk address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address clken : in std_logic := 'X'; -- clken chipselect : in std_logic := 'X'; -- chipselect write : in std_logic := 'X'; -- write readdata : out std_logic_vector(31 downto 0); -- readdata writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable reset : in std_logic := 'X'; -- reset reset_req : in std_logic := 'X' -- reset_req ); end component wasca_onchip_memory2_0; component sega_saturn_abus_slave is port ( clock : in std_logic := 'X'; -- clk abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect abus_read : in std_logic := 'X'; -- read abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write abus_waitrequest : out std_logic; -- waitrequest abus_interrupt : out std_logic; -- interrupt abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata abus_direction : out std_logic; -- direction abus_muxing : out std_logic_vector(1 downto 0); -- muxing abus_disable_out : out std_logic; -- disableout avalon_read : out std_logic; -- read avalon_write : out std_logic; -- write avalon_waitrequest : in std_logic := 'X'; -- waitrequest avalon_address : out std_logic_vector(27 downto 0); -- address avalon_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata avalon_writedata : out std_logic_vector(15 downto 0); -- writedata avalon_readdatavalid : in std_logic := 'X'; -- readdatavalid avalon_burstcount : out std_logic; -- burstcount reset : in std_logic := 'X'; -- reset saturn_reset : in std_logic := 'X'; -- saturn_reset avalon_nios_read : in std_logic := 'X'; -- read avalon_nios_write : in std_logic := 'X'; -- write avalon_nios_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata avalon_nios_readdata : out std_logic_vector(15 downto 0); -- readdata avalon_nios_waitrequest : out std_logic; -- waitrequest avalon_nios_readdatavalid : out std_logic; -- readdatavalid avalon_nios_burstcount : in std_logic := 'X' -- burstcount ); end component sega_saturn_abus_slave; component wasca_spi_sd_card is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n data_from_cpu : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata data_to_cpu : out std_logic_vector(15 downto 0); -- readdata mem_addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- address read_n : in std_logic := 'X'; -- read_n spi_select : in std_logic := 'X'; -- chipselect write_n : in std_logic := 'X'; -- write_n irq : out std_logic; -- irq MISO : in std_logic := 'X'; -- export MOSI : out std_logic; -- export SCLK : out std_logic; -- export SS_n : out std_logic -- export ); end component wasca_spi_sd_card; component wasca_spi_stm32 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n data_from_cpu : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata data_to_cpu : out std_logic_vector(15 downto 0); -- readdata mem_addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- address read_n : in std_logic := 'X'; -- read_n spi_select : in std_logic := 'X'; -- chipselect write_n : in std_logic := 'X'; -- write_n irq : out std_logic; -- irq MISO : out std_logic; -- export MOSI : in std_logic := 'X'; -- export SCLK : in std_logic := 'X'; -- export SS_n : in std_logic := 'X' -- export ); end component wasca_spi_stm32; component wasca_uart_0 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address begintransfer : in std_logic := 'X'; -- begintransfer chipselect : in std_logic := 'X'; -- chipselect read_n : in std_logic := 'X'; -- read_n write_n : in std_logic := 'X'; -- write_n writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata readdata : out std_logic_vector(15 downto 0); -- readdata dataavailable : out std_logic; -- dataavailable readyfordata : out std_logic; -- readyfordata rxd : in std_logic := 'X'; -- export txd : out std_logic; -- export irq : out std_logic -- irq ); end component wasca_uart_0; component wasca_mm_interconnect_0 is port ( altpll_0_c0_clk : in std_logic := 'X'; -- clk clk_0_clk_clk : in std_logic := 'X'; -- clk altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset nios2_gen2_0_data_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess nios2_gen2_0_instruction_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata sega_saturn_abus_slave_0_avalon_master_address : in std_logic_vector(27 downto 0) := (others => 'X'); -- address sega_saturn_abus_slave_0_avalon_master_waitrequest : out std_logic; -- waitrequest sega_saturn_abus_slave_0_avalon_master_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount sega_saturn_abus_slave_0_avalon_master_read : in std_logic := 'X'; -- read sega_saturn_abus_slave_0_avalon_master_readdata : out std_logic_vector(15 downto 0); -- readdata sega_saturn_abus_slave_0_avalon_master_readdatavalid : out std_logic; -- readdatavalid sega_saturn_abus_slave_0_avalon_master_write : in std_logic := 'X'; -- write sega_saturn_abus_slave_0_avalon_master_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata altpll_0_pll_slave_address : out std_logic_vector(1 downto 0); -- address altpll_0_pll_slave_write : out std_logic; -- write altpll_0_pll_slave_read : out std_logic; -- read altpll_0_pll_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata altpll_0_pll_slave_writedata : out std_logic_vector(31 downto 0); -- writedata audio_0_avalon_audio_slave_address : out std_logic_vector(1 downto 0); -- address audio_0_avalon_audio_slave_write : out std_logic; -- write audio_0_avalon_audio_slave_read : out std_logic; -- read audio_0_avalon_audio_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata audio_0_avalon_audio_slave_writedata : out std_logic_vector(31 downto 0); -- writedata audio_0_avalon_audio_slave_chipselect : out std_logic; -- chipselect external_sdram_controller_s1_address : out std_logic_vector(23 downto 0); -- address external_sdram_controller_s1_write : out std_logic; -- write external_sdram_controller_s1_read : out std_logic; -- read external_sdram_controller_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata external_sdram_controller_s1_writedata : out std_logic_vector(15 downto 0); -- writedata external_sdram_controller_s1_byteenable : out std_logic_vector(1 downto 0); -- byteenable external_sdram_controller_s1_readdatavalid : in std_logic := 'X'; -- readdatavalid external_sdram_controller_s1_waitrequest : in std_logic := 'X'; -- waitrequest external_sdram_controller_s1_chipselect : out std_logic; -- chipselect nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess onchip_flash_0_data_address : out std_logic_vector(15 downto 0); -- address onchip_flash_0_data_read : out std_logic; -- read onchip_flash_0_data_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata onchip_flash_0_data_burstcount : out std_logic_vector(3 downto 0); -- burstcount onchip_flash_0_data_readdatavalid : in std_logic := 'X'; -- readdatavalid onchip_flash_0_data_waitrequest : in std_logic := 'X'; -- waitrequest onchip_memory2_0_s1_address : out std_logic_vector(11 downto 0); -- address onchip_memory2_0_s1_write : out std_logic; -- write onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect onchip_memory2_0_s1_clken : out std_logic; -- clken sega_saturn_abus_slave_0_avalon_nios_address : out std_logic_vector(7 downto 0); -- address sega_saturn_abus_slave_0_avalon_nios_write : out std_logic; -- write sega_saturn_abus_slave_0_avalon_nios_read : out std_logic; -- read sega_saturn_abus_slave_0_avalon_nios_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata sega_saturn_abus_slave_0_avalon_nios_writedata : out std_logic_vector(15 downto 0); -- writedata sega_saturn_abus_slave_0_avalon_nios_burstcount : out std_logic_vector(0 downto 0); -- burstcount sega_saturn_abus_slave_0_avalon_nios_readdatavalid : in std_logic := 'X'; -- readdatavalid sega_saturn_abus_slave_0_avalon_nios_waitrequest : in std_logic := 'X'; -- waitrequest spi_sd_card_spi_control_port_address : out std_logic_vector(2 downto 0); -- address spi_sd_card_spi_control_port_write : out std_logic; -- write spi_sd_card_spi_control_port_read : out std_logic; -- read spi_sd_card_spi_control_port_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata spi_sd_card_spi_control_port_writedata : out std_logic_vector(15 downto 0); -- writedata spi_sd_card_spi_control_port_chipselect : out std_logic; -- chipselect spi_stm32_spi_control_port_address : out std_logic_vector(2 downto 0); -- address spi_stm32_spi_control_port_write : out std_logic; -- write spi_stm32_spi_control_port_read : out std_logic; -- read spi_stm32_spi_control_port_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata spi_stm32_spi_control_port_writedata : out std_logic_vector(15 downto 0); -- writedata spi_stm32_spi_control_port_chipselect : out std_logic; -- chipselect uart_0_s1_address : out std_logic_vector(2 downto 0); -- address uart_0_s1_write : out std_logic; -- write uart_0_s1_read : out std_logic; -- read uart_0_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata uart_0_s1_writedata : out std_logic_vector(15 downto 0); -- writedata uart_0_s1_begintransfer : out std_logic; -- begintransfer uart_0_s1_chipselect : out std_logic -- chipselect ); end component wasca_mm_interconnect_0; component wasca_irq_mapper is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset receiver0_irq : in std_logic := 'X'; -- irq receiver1_irq : in std_logic := 'X'; -- irq receiver2_irq : in std_logic := 'X'; -- irq receiver3_irq : in std_logic := 'X'; -- irq sender_irq : out std_logic_vector(31 downto 0) -- irq ); end component wasca_irq_mapper; component wasca_rst_controller is generic ( NUM_RESET_INPUTS : integer := 6; OUTPUT_RESET_SYNC_EDGES : string := "deassert"; SYNC_DEPTH : integer := 2; RESET_REQUEST_PRESENT : integer := 0; RESET_REQ_WAIT_TIME : integer := 1; MIN_RST_ASSERTION_TIME : integer := 3; RESET_REQ_EARLY_DSRT_TIME : integer := 1; USE_RESET_REQUEST_IN0 : integer := 0; USE_RESET_REQUEST_IN1 : integer := 0; USE_RESET_REQUEST_IN2 : integer := 0; USE_RESET_REQUEST_IN3 : integer := 0; USE_RESET_REQUEST_IN4 : integer := 0; USE_RESET_REQUEST_IN5 : integer := 0; USE_RESET_REQUEST_IN6 : integer := 0; USE_RESET_REQUEST_IN7 : integer := 0; USE_RESET_REQUEST_IN8 : integer := 0; USE_RESET_REQUEST_IN9 : integer := 0; USE_RESET_REQUEST_IN10 : integer := 0; USE_RESET_REQUEST_IN11 : integer := 0; USE_RESET_REQUEST_IN12 : integer := 0; USE_RESET_REQUEST_IN13 : integer := 0; USE_RESET_REQUEST_IN14 : integer := 0; USE_RESET_REQUEST_IN15 : integer := 0; ADAPT_RESET_REQUEST : integer := 0 ); port ( reset_in0 : in std_logic := 'X'; -- reset clk : in std_logic := 'X'; -- clk reset_out : out std_logic; -- reset reset_req : out std_logic; -- reset_req reset_req_in0 : in std_logic := 'X'; -- reset_req reset_in1 : in std_logic := 'X'; -- reset reset_req_in1 : in std_logic := 'X'; -- reset_req reset_in2 : in std_logic := 'X'; -- reset reset_req_in2 : in std_logic := 'X'; -- reset_req reset_in3 : in std_logic := 'X'; -- reset reset_req_in3 : in std_logic := 'X'; -- reset_req reset_in4 : in std_logic := 'X'; -- reset reset_req_in4 : in std_logic := 'X'; -- reset_req reset_in5 : in std_logic := 'X'; -- reset reset_req_in5 : in std_logic := 'X'; -- reset_req reset_in6 : in std_logic := 'X'; -- reset reset_req_in6 : in std_logic := 'X'; -- reset_req reset_in7 : in std_logic := 'X'; -- reset reset_req_in7 : in std_logic := 'X'; -- reset_req reset_in8 : in std_logic := 'X'; -- reset reset_req_in8 : in std_logic := 'X'; -- reset_req reset_in9 : in std_logic := 'X'; -- reset reset_req_in9 : in std_logic := 'X'; -- reset_req reset_in10 : in std_logic := 'X'; -- reset reset_req_in10 : in std_logic := 'X'; -- reset_req reset_in11 : in std_logic := 'X'; -- reset reset_req_in11 : in std_logic := 'X'; -- reset_req reset_in12 : in std_logic := 'X'; -- reset reset_req_in12 : in std_logic := 'X'; -- reset_req reset_in13 : in std_logic := 'X'; -- reset reset_req_in13 : in std_logic := 'X'; -- reset_req reset_in14 : in std_logic := 'X'; -- reset reset_req_in14 : in std_logic := 'X'; -- reset_req reset_in15 : in std_logic := 'X'; -- reset reset_req_in15 : in std_logic := 'X' -- reset_req ); end component wasca_rst_controller; component wasca_rst_controller_001 is generic ( NUM_RESET_INPUTS : integer := 6; OUTPUT_RESET_SYNC_EDGES : string := "deassert"; SYNC_DEPTH : integer := 2; RESET_REQUEST_PRESENT : integer := 0; RESET_REQ_WAIT_TIME : integer := 1; MIN_RST_ASSERTION_TIME : integer := 3; RESET_REQ_EARLY_DSRT_TIME : integer := 1; USE_RESET_REQUEST_IN0 : integer := 0; USE_RESET_REQUEST_IN1 : integer := 0; USE_RESET_REQUEST_IN2 : integer := 0; USE_RESET_REQUEST_IN3 : integer := 0; USE_RESET_REQUEST_IN4 : integer := 0; USE_RESET_REQUEST_IN5 : integer := 0; USE_RESET_REQUEST_IN6 : integer := 0; USE_RESET_REQUEST_IN7 : integer := 0; USE_RESET_REQUEST_IN8 : integer := 0; USE_RESET_REQUEST_IN9 : integer := 0; USE_RESET_REQUEST_IN10 : integer := 0; USE_RESET_REQUEST_IN11 : integer := 0; USE_RESET_REQUEST_IN12 : integer := 0; USE_RESET_REQUEST_IN13 : integer := 0; USE_RESET_REQUEST_IN14 : integer := 0; USE_RESET_REQUEST_IN15 : integer := 0; ADAPT_RESET_REQUEST : integer := 0 ); port ( reset_in0 : in std_logic := 'X'; -- reset clk : in std_logic := 'X'; -- clk reset_out : out std_logic; -- reset reset_req : out std_logic; -- reset_req reset_req_in0 : in std_logic := 'X'; -- reset_req reset_in1 : in std_logic := 'X'; -- reset reset_req_in1 : in std_logic := 'X'; -- reset_req reset_in2 : in std_logic := 'X'; -- reset reset_req_in2 : in std_logic := 'X'; -- reset_req reset_in3 : in std_logic := 'X'; -- reset reset_req_in3 : in std_logic := 'X'; -- reset_req reset_in4 : in std_logic := 'X'; -- reset reset_req_in4 : in std_logic := 'X'; -- reset_req reset_in5 : in std_logic := 'X'; -- reset reset_req_in5 : in std_logic := 'X'; -- reset_req reset_in6 : in std_logic := 'X'; -- reset reset_req_in6 : in std_logic := 'X'; -- reset_req reset_in7 : in std_logic := 'X'; -- reset reset_req_in7 : in std_logic := 'X'; -- reset_req reset_in8 : in std_logic := 'X'; -- reset reset_req_in8 : in std_logic := 'X'; -- reset_req reset_in9 : in std_logic := 'X'; -- reset reset_req_in9 : in std_logic := 'X'; -- reset_req reset_in10 : in std_logic := 'X'; -- reset reset_req_in10 : in std_logic := 'X'; -- reset_req reset_in11 : in std_logic := 'X'; -- reset reset_req_in11 : in std_logic := 'X'; -- reset_req reset_in12 : in std_logic := 'X'; -- reset reset_req_in12 : in std_logic := 'X'; -- reset_req reset_in13 : in std_logic := 'X'; -- reset reset_req_in13 : in std_logic := 'X'; -- reset_req reset_in14 : in std_logic := 'X'; -- reset reset_req_in14 : in std_logic := 'X'; -- reset_req reset_in15 : in std_logic := 'X'; -- reset reset_req_in15 : in std_logic := 'X' -- reset_req ); end component wasca_rst_controller_001; signal altpll_0_c0_clk : std_logic; -- altpll_0:c0 -> [clock_116_mhz_clk, audio_0:clk, external_sdram_controller:clk, irq_mapper:clk, mm_interconnect_0:altpll_0_c0_clk, nios2_gen2_0:clk, onchip_flash_0:clock, onchip_memory2_0:clk, rst_controller_001:clk, rst_controller_002:clk, sega_saturn_abus_slave_0:clock, spi_sd_card:clk, spi_stm32:clk, uart_0:clk] signal nios2_gen2_0_debug_reset_request_reset : std_logic; -- nios2_gen2_0:debug_reset_request -> [rst_controller:reset_in0, rst_controller_001:reset_in0, rst_controller_002:reset_in0] signal sega_saturn_abus_slave_0_avalon_master_waitrequest : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_waitrequest -> sega_saturn_abus_slave_0:avalon_waitrequest signal sega_saturn_abus_slave_0_avalon_master_readdata : std_logic_vector(15 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_readdata -> sega_saturn_abus_slave_0:avalon_readdata signal sega_saturn_abus_slave_0_avalon_master_read : std_logic; -- sega_saturn_abus_slave_0:avalon_read -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_read signal sega_saturn_abus_slave_0_avalon_master_address : std_logic_vector(27 downto 0); -- sega_saturn_abus_slave_0:avalon_address -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_address signal sega_saturn_abus_slave_0_avalon_master_readdatavalid : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_readdatavalid -> sega_saturn_abus_slave_0:avalon_readdatavalid signal sega_saturn_abus_slave_0_avalon_master_write : std_logic; -- sega_saturn_abus_slave_0:avalon_write -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_write signal sega_saturn_abus_slave_0_avalon_master_writedata : std_logic_vector(15 downto 0); -- sega_saturn_abus_slave_0:avalon_writedata -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_writedata signal sega_saturn_abus_slave_0_avalon_master_burstcount : std_logic; -- sega_saturn_abus_slave_0:avalon_burstcount -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_burstcount signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess signal nios2_gen2_0_data_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest signal nios2_gen2_0_instruction_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read signal mm_interconnect_0_external_sdram_controller_s1_chipselect : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_chipselect -> external_sdram_controller:az_cs signal mm_interconnect_0_external_sdram_controller_s1_readdata : std_logic_vector(15 downto 0); -- external_sdram_controller:za_data -> mm_interconnect_0:external_sdram_controller_s1_readdata signal mm_interconnect_0_external_sdram_controller_s1_waitrequest : std_logic; -- external_sdram_controller:za_waitrequest -> mm_interconnect_0:external_sdram_controller_s1_waitrequest signal mm_interconnect_0_external_sdram_controller_s1_address : std_logic_vector(23 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_address -> external_sdram_controller:az_addr signal mm_interconnect_0_external_sdram_controller_s1_read : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_read -> mm_interconnect_0_external_sdram_controller_s1_read:in signal mm_interconnect_0_external_sdram_controller_s1_byteenable : std_logic_vector(1 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_byteenable -> mm_interconnect_0_external_sdram_controller_s1_byteenable:in signal mm_interconnect_0_external_sdram_controller_s1_readdatavalid : std_logic; -- external_sdram_controller:za_valid -> mm_interconnect_0:external_sdram_controller_s1_readdatavalid signal mm_interconnect_0_external_sdram_controller_s1_write : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_write -> mm_interconnect_0_external_sdram_controller_s1_write:in signal mm_interconnect_0_external_sdram_controller_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_writedata -> external_sdram_controller:az_data signal mm_interconnect_0_onchip_flash_0_data_readdata : std_logic_vector(31 downto 0); -- onchip_flash_0:avmm_data_readdata -> mm_interconnect_0:onchip_flash_0_data_readdata signal mm_interconnect_0_onchip_flash_0_data_waitrequest : std_logic; -- onchip_flash_0:avmm_data_waitrequest -> mm_interconnect_0:onchip_flash_0_data_waitrequest signal mm_interconnect_0_onchip_flash_0_data_address : std_logic_vector(15 downto 0); -- mm_interconnect_0:onchip_flash_0_data_address -> onchip_flash_0:avmm_data_addr signal mm_interconnect_0_onchip_flash_0_data_read : std_logic; -- mm_interconnect_0:onchip_flash_0_data_read -> onchip_flash_0:avmm_data_read signal mm_interconnect_0_onchip_flash_0_data_readdatavalid : std_logic; -- onchip_flash_0:avmm_data_readdatavalid -> mm_interconnect_0:onchip_flash_0_data_readdatavalid signal mm_interconnect_0_onchip_flash_0_data_burstcount : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_flash_0_data_burstcount -> onchip_flash_0:avmm_data_burstcount signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(11 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken signal mm_interconnect_0_audio_0_avalon_audio_slave_chipselect : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_chipselect -> audio_0:chipselect signal mm_interconnect_0_audio_0_avalon_audio_slave_readdata : std_logic_vector(31 downto 0); -- audio_0:readdata -> mm_interconnect_0:audio_0_avalon_audio_slave_readdata signal mm_interconnect_0_audio_0_avalon_audio_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:audio_0_avalon_audio_slave_address -> audio_0:address signal mm_interconnect_0_audio_0_avalon_audio_slave_read : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_read -> audio_0:read signal mm_interconnect_0_audio_0_avalon_audio_slave_write : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_write -> audio_0:write signal mm_interconnect_0_audio_0_avalon_audio_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:audio_0_avalon_audio_slave_writedata -> audio_0:writedata signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata : std_logic_vector(15 downto 0); -- sega_saturn_abus_slave_0:avalon_nios_readdata -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_readdata signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest : std_logic; -- sega_saturn_abus_slave_0:avalon_nios_waitrequest -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_waitrequest signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_address -> sega_saturn_abus_slave_0:avalon_nios_address signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_read -> sega_saturn_abus_slave_0:avalon_nios_read signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid : std_logic; -- sega_saturn_abus_slave_0:avalon_nios_readdatavalid -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_readdatavalid signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_write -> sega_saturn_abus_slave_0:avalon_nios_write signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_writedata -> sega_saturn_abus_slave_0:avalon_nios_writedata signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount : std_logic_vector(0 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_burstcount -> sega_saturn_abus_slave_0:avalon_nios_burstcount signal mm_interconnect_0_altpll_0_pll_slave_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> mm_interconnect_0:altpll_0_pll_slave_readdata signal mm_interconnect_0_altpll_0_pll_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_address -> altpll_0:address signal mm_interconnect_0_altpll_0_pll_slave_read : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_read -> altpll_0:read signal mm_interconnect_0_altpll_0_pll_slave_write : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_write -> altpll_0:write signal mm_interconnect_0_altpll_0_pll_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_writedata -> altpll_0:writedata signal mm_interconnect_0_uart_0_s1_chipselect : std_logic; -- mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect signal mm_interconnect_0_uart_0_s1_readdata : std_logic_vector(15 downto 0); -- uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata signal mm_interconnect_0_uart_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:uart_0_s1_address -> uart_0:address signal mm_interconnect_0_uart_0_s1_read : std_logic; -- mm_interconnect_0:uart_0_s1_read -> mm_interconnect_0_uart_0_s1_read:in signal mm_interconnect_0_uart_0_s1_begintransfer : std_logic; -- mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer signal mm_interconnect_0_uart_0_s1_write : std_logic; -- mm_interconnect_0:uart_0_s1_write -> mm_interconnect_0_uart_0_s1_write:in signal mm_interconnect_0_uart_0_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata signal mm_interconnect_0_spi_sd_card_spi_control_port_chipselect : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_chipselect -> spi_sd_card:spi_select signal mm_interconnect_0_spi_sd_card_spi_control_port_readdata : std_logic_vector(15 downto 0); -- spi_sd_card:data_to_cpu -> mm_interconnect_0:spi_sd_card_spi_control_port_readdata signal mm_interconnect_0_spi_sd_card_spi_control_port_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:spi_sd_card_spi_control_port_address -> spi_sd_card:mem_addr signal mm_interconnect_0_spi_sd_card_spi_control_port_read : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_read -> mm_interconnect_0_spi_sd_card_spi_control_port_read:in signal mm_interconnect_0_spi_sd_card_spi_control_port_write : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_write -> mm_interconnect_0_spi_sd_card_spi_control_port_write:in signal mm_interconnect_0_spi_sd_card_spi_control_port_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:spi_sd_card_spi_control_port_writedata -> spi_sd_card:data_from_cpu signal mm_interconnect_0_spi_stm32_spi_control_port_chipselect : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_chipselect -> spi_stm32:spi_select signal mm_interconnect_0_spi_stm32_spi_control_port_readdata : std_logic_vector(15 downto 0); -- spi_stm32:data_to_cpu -> mm_interconnect_0:spi_stm32_spi_control_port_readdata signal mm_interconnect_0_spi_stm32_spi_control_port_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:spi_stm32_spi_control_port_address -> spi_stm32:mem_addr signal mm_interconnect_0_spi_stm32_spi_control_port_read : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_read -> mm_interconnect_0_spi_stm32_spi_control_port_read:in signal mm_interconnect_0_spi_stm32_spi_control_port_write : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_write -> mm_interconnect_0_spi_stm32_spi_control_port_write:in signal mm_interconnect_0_spi_stm32_spi_control_port_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:spi_stm32_spi_control_port_writedata -> spi_stm32:data_from_cpu signal irq_mapper_receiver0_irq : std_logic; -- audio_0:irq -> irq_mapper:receiver0_irq signal irq_mapper_receiver1_irq : std_logic; -- uart_0:irq -> irq_mapper:receiver1_irq signal irq_mapper_receiver2_irq : std_logic; -- spi_sd_card:irq -> irq_mapper:receiver2_irq signal irq_mapper_receiver3_irq : std_logic; -- spi_stm32:irq -> irq_mapper:receiver3_irq signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [altpll_0:reset, mm_interconnect_0:altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset] signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [audio_0:reset, irq_mapper:reset, mm_interconnect_0:sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_001_reset_out_reset:in, rst_translator:in_reset, sega_saturn_abus_slave_0:reset] signal rst_controller_001_reset_out_reset_req : std_logic; -- rst_controller_001:reset_req -> [onchip_memory2_0:reset_req, rst_translator:reset_req_in] signal mm_interconnect_0_external_sdram_controller_s1_read_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_read:inv -> external_sdram_controller:az_rd_n signal mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv : std_logic_vector(1 downto 0); -- mm_interconnect_0_external_sdram_controller_s1_byteenable:inv -> external_sdram_controller:az_be_n signal mm_interconnect_0_external_sdram_controller_s1_write_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_write:inv -> external_sdram_controller:az_wr_n signal mm_interconnect_0_uart_0_s1_read_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_read:inv -> uart_0:read_n signal mm_interconnect_0_uart_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_write:inv -> uart_0:write_n signal mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv : std_logic; -- mm_interconnect_0_spi_sd_card_spi_control_port_read:inv -> spi_sd_card:read_n signal mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv : std_logic; -- mm_interconnect_0_spi_sd_card_spi_control_port_write:inv -> spi_sd_card:write_n signal mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv : std_logic; -- mm_interconnect_0_spi_stm32_spi_control_port_read:inv -> spi_stm32:read_n signal mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv : std_logic; -- mm_interconnect_0_spi_stm32_spi_control_port_write:inv -> spi_stm32:write_n signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> [external_sdram_controller:reset_n, nios2_gen2_0:reset_n, onchip_flash_0:reset_n, spi_sd_card:reset_n, spi_stm32:reset_n, uart_0:reset_n] begin altpll_0 : component wasca_altpll_0 port map ( clk => clk_clk, -- inclk_interface.clk reset => rst_controller_reset_out_reset, -- inclk_interface_reset.reset read => mm_interconnect_0_altpll_0_pll_slave_read, -- pll_slave.read write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write address => mm_interconnect_0_altpll_0_pll_slave_address, -- .address readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata c0 => altpll_0_c0_clk, -- c0.clk areset => altpll_0_areset_conduit_export, -- areset_conduit.export c1 => open, -- c1_conduit.export locked => altpll_0_locked_conduit_export, -- locked_conduit.export phasedone => altpll_0_phasedone_conduit_export -- phasedone_conduit.export ); audio_0 : component wasca_audio_0 port map ( clk => altpll_0_c0_clk, -- clk.clk reset => rst_controller_001_reset_out_reset, -- reset.reset address => mm_interconnect_0_audio_0_avalon_audio_slave_address, -- avalon_audio_slave.address chipselect => mm_interconnect_0_audio_0_avalon_audio_slave_chipselect, -- .chipselect read => mm_interconnect_0_audio_0_avalon_audio_slave_read, -- .read write => mm_interconnect_0_audio_0_avalon_audio_slave_write, -- .write writedata => mm_interconnect_0_audio_0_avalon_audio_slave_writedata, -- .writedata readdata => mm_interconnect_0_audio_0_avalon_audio_slave_readdata, -- .readdata irq => irq_mapper_receiver0_irq, -- interrupt.irq AUD_BCLK => audio_out_BCLK, -- external_interface.export AUD_DACDAT => audio_out_DACDAT, -- .export AUD_DACLRCK => audio_out_DACLRCK -- .export ); external_sdram_controller : component wasca_external_sdram_controller port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n az_addr => mm_interconnect_0_external_sdram_controller_s1_address, -- s1.address az_be_n => mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv, -- .byteenable_n az_cs => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect az_data => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata az_rd_n => mm_interconnect_0_external_sdram_controller_s1_read_ports_inv, -- .read_n az_wr_n => mm_interconnect_0_external_sdram_controller_s1_write_ports_inv, -- .write_n za_data => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata za_valid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid za_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest zs_addr => external_sdram_controller_wire_addr, -- wire.export zs_ba => external_sdram_controller_wire_ba, -- .export zs_cas_n => external_sdram_controller_wire_cas_n, -- .export zs_cke => external_sdram_controller_wire_cke, -- .export zs_cs_n => external_sdram_controller_wire_cs_n, -- .export zs_dq => external_sdram_controller_wire_dq, -- .export zs_dqm => external_sdram_controller_wire_dqm, -- .export zs_ras_n => external_sdram_controller_wire_ras_n, -- .export zs_we_n => external_sdram_controller_wire_we_n -- .export ); nios2_gen2_0 : component wasca_nios2_gen2_0 port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n d_address => nios2_gen2_0_data_master_address, -- data_master.address d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable d_read => nios2_gen2_0_data_master_read, -- .read d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest d_write => nios2_gen2_0_data_master_write, -- .write d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address i_read => nios2_gen2_0_instruction_master_read, -- .read i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest irq => nios2_gen2_0_irq_irq, -- irq.irq debug_reset_request => nios2_gen2_0_debug_reset_request_reset, -- debug_reset_request.reset debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata dummy_ci_port => open -- custom_instruction_master.readra ); onchip_flash_0 : component altera_onchip_flash generic map ( INIT_FILENAME => "", INIT_FILENAME_SIM => "", DEVICE_FAMILY => "MAX 10", PART_NAME => "10M08SAE144C8GES", DEVICE_ID => "08", SECTOR1_START_ADDR => 0, SECTOR1_END_ADDR => 4095, SECTOR2_START_ADDR => 4096, SECTOR2_END_ADDR => 8191, SECTOR3_START_ADDR => 8192, SECTOR3_END_ADDR => 29183, SECTOR4_START_ADDR => 29184, SECTOR4_END_ADDR => 44031, SECTOR5_START_ADDR => 0, SECTOR5_END_ADDR => 0, MIN_VALID_ADDR => 0, MAX_VALID_ADDR => 44031, MIN_UFM_VALID_ADDR => 0, MAX_UFM_VALID_ADDR => 44031, SECTOR1_MAP => 1, SECTOR2_MAP => 2, SECTOR3_MAP => 3, SECTOR4_MAP => 4, SECTOR5_MAP => 0, ADDR_RANGE1_END_ADDR => 44031, ADDR_RANGE1_OFFSET => 512, ADDR_RANGE2_OFFSET => 0, AVMM_DATA_ADDR_WIDTH => 16, AVMM_DATA_DATA_WIDTH => 32, AVMM_DATA_BURSTCOUNT_WIDTH => 4, SECTOR_READ_PROTECTION_MODE => 31, FLASH_SEQ_READ_DATA_COUNT => 2, FLASH_ADDR_ALIGNMENT_BITS => 1, FLASH_READ_CYCLE_MAX_INDEX => 3, FLASH_RESET_CYCLE_MAX_INDEX => 29, FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX => 111, FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX => 40603248, FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX => 35382, PARALLEL_MODE => true, READ_AND_WRITE_MODE => false, WRAPPING_BURST_MODE => false, IS_DUAL_BOOT => "False", IS_ERAM_SKIP => "True", IS_COMPRESSED_IMAGE => "True" ) port map ( clock => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- nreset.reset_n avmm_data_addr => mm_interconnect_0_onchip_flash_0_data_address, -- data.address avmm_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read avmm_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata avmm_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest avmm_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid avmm_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount avmm_data_writedata => "00000000000000000000000000000000", -- (terminated) avmm_data_write => '0', -- (terminated) avmm_csr_addr => '0', -- (terminated) avmm_csr_read => '0', -- (terminated) avmm_csr_writedata => "00000000000000000000000000000000", -- (terminated) avmm_csr_write => '0', -- (terminated) avmm_csr_readdata => open -- (terminated) ); onchip_memory2_0 : component wasca_onchip_memory2_0 port map ( clk => altpll_0_c0_clk, -- clk1.clk address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable reset => rst_controller_001_reset_out_reset, -- reset1.reset reset_req => rst_controller_001_reset_out_reset_req -- .reset_req ); sega_saturn_abus_slave_0 : component sega_saturn_abus_slave port map ( clock => altpll_0_c0_clk, -- clock.clk abus_address => sega_saturn_abus_slave_0_abus_address, -- abus.address abus_chipselect => sega_saturn_abus_slave_0_abus_chipselect, -- .chipselect abus_read => sega_saturn_abus_slave_0_abus_read, -- .read abus_write => sega_saturn_abus_slave_0_abus_write, -- .write abus_waitrequest => sega_saturn_abus_slave_0_abus_waitrequest, -- .waitrequest abus_interrupt => sega_saturn_abus_slave_0_abus_interrupt, -- .interrupt abus_addressdata => sega_saturn_abus_slave_0_abus_addressdata, -- .addressdata abus_direction => sega_saturn_abus_slave_0_abus_direction, -- .direction abus_muxing => sega_saturn_abus_slave_0_abus_muxing, -- .muxing abus_disable_out => sega_saturn_abus_slave_0_abus_disableout, -- .disableout avalon_read => sega_saturn_abus_slave_0_avalon_master_read, -- avalon_master.read avalon_write => sega_saturn_abus_slave_0_avalon_master_write, -- .write avalon_waitrequest => sega_saturn_abus_slave_0_avalon_master_waitrequest, -- .waitrequest avalon_address => sega_saturn_abus_slave_0_avalon_master_address, -- .address avalon_readdata => sega_saturn_abus_slave_0_avalon_master_readdata, -- .readdata avalon_writedata => sega_saturn_abus_slave_0_avalon_master_writedata, -- .writedata avalon_readdatavalid => sega_saturn_abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid avalon_burstcount => sega_saturn_abus_slave_0_avalon_master_burstcount, -- .burstcount reset => rst_controller_001_reset_out_reset, -- reset.reset saturn_reset => sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset, -- conduit_saturn_reset.saturn_reset avalon_nios_read => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read, -- avalon_nios.read avalon_nios_write => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write, -- .write avalon_nios_address => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address, -- .address avalon_nios_writedata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata, -- .writedata avalon_nios_readdata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata, -- .readdata avalon_nios_waitrequest => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest avalon_nios_readdatavalid => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid avalon_nios_burstcount => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount(0) -- .burstcount ); spi_sd_card : component wasca_spi_sd_card port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n data_from_cpu => mm_interconnect_0_spi_sd_card_spi_control_port_writedata, -- spi_control_port.writedata data_to_cpu => mm_interconnect_0_spi_sd_card_spi_control_port_readdata, -- .readdata mem_addr => mm_interconnect_0_spi_sd_card_spi_control_port_address, -- .address read_n => mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv, -- .read_n spi_select => mm_interconnect_0_spi_sd_card_spi_control_port_chipselect, -- .chipselect write_n => mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv, -- .write_n irq => irq_mapper_receiver2_irq, -- irq.irq MISO => spi_sd_card_MISO, -- external.export MOSI => spi_sd_card_MOSI, -- .export SCLK => spi_sd_card_SCLK, -- .export SS_n => spi_sd_card_SS_n -- .export ); spi_stm32 : component wasca_spi_stm32 port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n data_from_cpu => mm_interconnect_0_spi_stm32_spi_control_port_writedata, -- spi_control_port.writedata data_to_cpu => mm_interconnect_0_spi_stm32_spi_control_port_readdata, -- .readdata mem_addr => mm_interconnect_0_spi_stm32_spi_control_port_address, -- .address read_n => mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv, -- .read_n spi_select => mm_interconnect_0_spi_stm32_spi_control_port_chipselect, -- .chipselect write_n => mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv, -- .write_n irq => irq_mapper_receiver3_irq, -- irq.irq MISO => spi_stm32_MISO, -- external.export MOSI => spi_stm32_MOSI, -- .export SCLK => spi_stm32_SCLK, -- .export SS_n => spi_stm32_SS_n -- .export ); uart_0 : component wasca_uart_0 port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n address => mm_interconnect_0_uart_0_s1_address, -- s1.address begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer chipselect => mm_interconnect_0_uart_0_s1_chipselect, -- .chipselect read_n => mm_interconnect_0_uart_0_s1_read_ports_inv, -- .read_n write_n => mm_interconnect_0_uart_0_s1_write_ports_inv, -- .write_n writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata dataavailable => open, -- .dataavailable readyfordata => open, -- .readyfordata rxd => uart_0_external_connection_rxd, -- external_connection.export txd => uart_0_external_connection_txd, -- .export irq => irq_mapper_receiver1_irq -- irq.irq ); mm_interconnect_0 : component wasca_mm_interconnect_0 port map ( altpll_0_c0_clk => altpll_0_c0_clk, -- altpll_0_c0.clk clk_0_clk_clk => clk_clk, -- clk_0_clk.clk altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- sega_saturn_abus_slave_0_reset_reset_bridge_in_reset.reset nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata sega_saturn_abus_slave_0_avalon_master_address => sega_saturn_abus_slave_0_avalon_master_address, -- sega_saturn_abus_slave_0_avalon_master.address sega_saturn_abus_slave_0_avalon_master_waitrequest => sega_saturn_abus_slave_0_avalon_master_waitrequest, -- .waitrequest sega_saturn_abus_slave_0_avalon_master_burstcount(0) => sega_saturn_abus_slave_0_avalon_master_burstcount, -- .burstcount sega_saturn_abus_slave_0_avalon_master_read => sega_saturn_abus_slave_0_avalon_master_read, -- .read sega_saturn_abus_slave_0_avalon_master_readdata => sega_saturn_abus_slave_0_avalon_master_readdata, -- .readdata sega_saturn_abus_slave_0_avalon_master_readdatavalid => sega_saturn_abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid sega_saturn_abus_slave_0_avalon_master_write => sega_saturn_abus_slave_0_avalon_master_write, -- .write sega_saturn_abus_slave_0_avalon_master_writedata => sega_saturn_abus_slave_0_avalon_master_writedata, -- .writedata altpll_0_pll_slave_address => mm_interconnect_0_altpll_0_pll_slave_address, -- altpll_0_pll_slave.address altpll_0_pll_slave_write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write altpll_0_pll_slave_read => mm_interconnect_0_altpll_0_pll_slave_read, -- .read altpll_0_pll_slave_readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata altpll_0_pll_slave_writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata audio_0_avalon_audio_slave_address => mm_interconnect_0_audio_0_avalon_audio_slave_address, -- audio_0_avalon_audio_slave.address audio_0_avalon_audio_slave_write => mm_interconnect_0_audio_0_avalon_audio_slave_write, -- .write audio_0_avalon_audio_slave_read => mm_interconnect_0_audio_0_avalon_audio_slave_read, -- .read audio_0_avalon_audio_slave_readdata => mm_interconnect_0_audio_0_avalon_audio_slave_readdata, -- .readdata audio_0_avalon_audio_slave_writedata => mm_interconnect_0_audio_0_avalon_audio_slave_writedata, -- .writedata audio_0_avalon_audio_slave_chipselect => mm_interconnect_0_audio_0_avalon_audio_slave_chipselect, -- .chipselect external_sdram_controller_s1_address => mm_interconnect_0_external_sdram_controller_s1_address, -- external_sdram_controller_s1.address external_sdram_controller_s1_write => mm_interconnect_0_external_sdram_controller_s1_write, -- .write external_sdram_controller_s1_read => mm_interconnect_0_external_sdram_controller_s1_read, -- .read external_sdram_controller_s1_readdata => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata external_sdram_controller_s1_writedata => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata external_sdram_controller_s1_byteenable => mm_interconnect_0_external_sdram_controller_s1_byteenable, -- .byteenable external_sdram_controller_s1_readdatavalid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid external_sdram_controller_s1_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest external_sdram_controller_s1_chipselect => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess onchip_flash_0_data_address => mm_interconnect_0_onchip_flash_0_data_address, -- onchip_flash_0_data.address onchip_flash_0_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read onchip_flash_0_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata onchip_flash_0_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount onchip_flash_0_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid onchip_flash_0_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken sega_saturn_abus_slave_0_avalon_nios_address => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address, -- sega_saturn_abus_slave_0_avalon_nios.address sega_saturn_abus_slave_0_avalon_nios_write => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write, -- .write sega_saturn_abus_slave_0_avalon_nios_read => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read, -- .read sega_saturn_abus_slave_0_avalon_nios_readdata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata, -- .readdata sega_saturn_abus_slave_0_avalon_nios_writedata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata, -- .writedata sega_saturn_abus_slave_0_avalon_nios_burstcount => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount, -- .burstcount sega_saturn_abus_slave_0_avalon_nios_readdatavalid => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid sega_saturn_abus_slave_0_avalon_nios_waitrequest => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest spi_sd_card_spi_control_port_address => mm_interconnect_0_spi_sd_card_spi_control_port_address, -- spi_sd_card_spi_control_port.address spi_sd_card_spi_control_port_write => mm_interconnect_0_spi_sd_card_spi_control_port_write, -- .write spi_sd_card_spi_control_port_read => mm_interconnect_0_spi_sd_card_spi_control_port_read, -- .read spi_sd_card_spi_control_port_readdata => mm_interconnect_0_spi_sd_card_spi_control_port_readdata, -- .readdata spi_sd_card_spi_control_port_writedata => mm_interconnect_0_spi_sd_card_spi_control_port_writedata, -- .writedata spi_sd_card_spi_control_port_chipselect => mm_interconnect_0_spi_sd_card_spi_control_port_chipselect, -- .chipselect spi_stm32_spi_control_port_address => mm_interconnect_0_spi_stm32_spi_control_port_address, -- spi_stm32_spi_control_port.address spi_stm32_spi_control_port_write => mm_interconnect_0_spi_stm32_spi_control_port_write, -- .write spi_stm32_spi_control_port_read => mm_interconnect_0_spi_stm32_spi_control_port_read, -- .read spi_stm32_spi_control_port_readdata => mm_interconnect_0_spi_stm32_spi_control_port_readdata, -- .readdata spi_stm32_spi_control_port_writedata => mm_interconnect_0_spi_stm32_spi_control_port_writedata, -- .writedata spi_stm32_spi_control_port_chipselect => mm_interconnect_0_spi_stm32_spi_control_port_chipselect, -- .chipselect uart_0_s1_address => mm_interconnect_0_uart_0_s1_address, -- uart_0_s1.address uart_0_s1_write => mm_interconnect_0_uart_0_s1_write, -- .write uart_0_s1_read => mm_interconnect_0_uart_0_s1_read, -- .read uart_0_s1_readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata uart_0_s1_writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata uart_0_s1_begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer uart_0_s1_chipselect => mm_interconnect_0_uart_0_s1_chipselect -- .chipselect ); irq_mapper : component wasca_irq_mapper port map ( clk => altpll_0_c0_clk, -- clk.clk reset => rst_controller_001_reset_out_reset, -- clk_reset.reset receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq receiver2_irq => irq_mapper_receiver2_irq, -- receiver2.irq receiver3_irq => irq_mapper_receiver3_irq, -- receiver3.irq sender_irq => nios2_gen2_0_irq_irq -- sender.irq ); rst_controller : component wasca_rst_controller generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "deassert", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 0, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset clk => clk_clk, -- clk.clk reset_out => rst_controller_reset_out_reset, -- reset_out.reset reset_req => open, -- (terminated) reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); rst_controller_001 : component wasca_rst_controller_001 generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "deassert", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 1, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset clk => altpll_0_c0_clk, -- clk.clk reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); rst_controller_002 : component wasca_rst_controller generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "both", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 0, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset clk => altpll_0_c0_clk, -- clk.clk reset_out => open, -- reset_out.reset reset_req => open, -- (terminated) reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); mm_interconnect_0_external_sdram_controller_s1_read_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_read; mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_byteenable; mm_interconnect_0_external_sdram_controller_s1_write_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_write; mm_interconnect_0_uart_0_s1_read_ports_inv <= not mm_interconnect_0_uart_0_s1_read; mm_interconnect_0_uart_0_s1_write_ports_inv <= not mm_interconnect_0_uart_0_s1_write; mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv <= not mm_interconnect_0_spi_sd_card_spi_control_port_read; mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv <= not mm_interconnect_0_spi_sd_card_spi_control_port_write; mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv <= not mm_interconnect_0_spi_stm32_spi_control_port_read; mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv <= not mm_interconnect_0_spi_stm32_spi_control_port_write; rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset; clock_116_mhz_clk <= altpll_0_c0_clk; end architecture rtl; -- of wasca
-- wasca.vhd -- Generated using ACDS version 15.0 145 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity wasca is port ( altpll_0_areset_conduit_export : in std_logic := '0'; -- altpll_0_areset_conduit.export altpll_0_locked_conduit_export : out std_logic; -- altpll_0_locked_conduit.export altpll_0_phasedone_conduit_export : out std_logic; -- altpll_0_phasedone_conduit.export audio_out_BCLK : in std_logic := '0'; -- audio_out.BCLK audio_out_DACDAT : out std_logic; -- .DACDAT audio_out_DACLRCK : in std_logic := '0'; -- .DACLRCK clk_clk : in std_logic := '0'; -- clk.clk clock_116_mhz_clk : out std_logic; -- clock_116_mhz.clk external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n external_sdram_controller_wire_cke : out std_logic; -- .cke external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n external_sdram_controller_wire_we_n : out std_logic; -- .we_n sega_saturn_abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- sega_saturn_abus_slave_0_abus.address sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect sega_saturn_abus_slave_0_abus_read : in std_logic := '0'; -- .read sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest sega_saturn_abus_slave_0_abus_interrupt : out std_logic; -- .interrupt sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .addressdata sega_saturn_abus_slave_0_abus_direction : out std_logic; -- .direction sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- .muxing sega_saturn_abus_slave_0_abus_disableout : out std_logic; -- .disableout sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := '0'; -- sega_saturn_abus_slave_0_conduit_saturn_reset.saturn_reset spi_sd_card_MISO : in std_logic := '0'; -- spi_sd_card.MISO spi_sd_card_MOSI : out std_logic; -- .MOSI spi_sd_card_SCLK : out std_logic; -- .SCLK spi_sd_card_SS_n : out std_logic; -- .SS_n spi_stm32_MISO : out std_logic; -- spi_stm32.MISO spi_stm32_MOSI : in std_logic := '0'; -- .MOSI spi_stm32_SCLK : in std_logic := '0'; -- .SCLK spi_stm32_SS_n : in std_logic := '0'; -- .SS_n uart_0_external_connection_rxd : in std_logic := '0'; -- uart_0_external_connection.rxd uart_0_external_connection_txd : out std_logic -- .txd ); end entity wasca; architecture rtl of wasca is component wasca_altpll_0 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset read : in std_logic := 'X'; -- read write : in std_logic := 'X'; -- write address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address readdata : out std_logic_vector(31 downto 0); -- readdata writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata c0 : out std_logic; -- clk areset : in std_logic := 'X'; -- export c1 : out std_logic; -- export locked : out std_logic; -- export phasedone : out std_logic -- export ); end component wasca_altpll_0; component wasca_audio_0 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address chipselect : in std_logic := 'X'; -- chipselect read : in std_logic := 'X'; -- read write : in std_logic := 'X'; -- write writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata readdata : out std_logic_vector(31 downto 0); -- readdata irq : out std_logic; -- irq AUD_BCLK : in std_logic := 'X'; -- export AUD_DACDAT : out std_logic; -- export AUD_DACLRCK : in std_logic := 'X' -- export ); end component wasca_audio_0; component wasca_external_sdram_controller is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n az_addr : in std_logic_vector(23 downto 0) := (others => 'X'); -- address az_be_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable_n az_cs : in std_logic := 'X'; -- chipselect az_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata az_rd_n : in std_logic := 'X'; -- read_n az_wr_n : in std_logic := 'X'; -- write_n za_data : out std_logic_vector(15 downto 0); -- readdata za_valid : out std_logic; -- readdatavalid za_waitrequest : out std_logic; -- waitrequest zs_addr : out std_logic_vector(12 downto 0); -- export zs_ba : out std_logic_vector(1 downto 0); -- export zs_cas_n : out std_logic; -- export zs_cke : out std_logic; -- export zs_cs_n : out std_logic; -- export zs_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export zs_dqm : out std_logic_vector(1 downto 0); -- export zs_ras_n : out std_logic; -- export zs_we_n : out std_logic -- export ); end component wasca_external_sdram_controller; component wasca_nios2_gen2_0 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n d_address : out std_logic_vector(26 downto 0); -- address d_byteenable : out std_logic_vector(3 downto 0); -- byteenable d_read : out std_logic; -- read d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata d_waitrequest : in std_logic := 'X'; -- waitrequest d_write : out std_logic; -- write d_writedata : out std_logic_vector(31 downto 0); -- writedata debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess i_address : out std_logic_vector(26 downto 0); -- address i_read : out std_logic; -- read i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata i_waitrequest : in std_logic := 'X'; -- waitrequest irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq debug_reset_request : out std_logic; -- reset debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess debug_mem_slave_read : in std_logic := 'X'; -- read debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata debug_mem_slave_waitrequest : out std_logic; -- waitrequest debug_mem_slave_write : in std_logic := 'X'; -- write debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata dummy_ci_port : out std_logic -- readra ); end component wasca_nios2_gen2_0; component altera_onchip_flash is generic ( INIT_FILENAME : string := ""; INIT_FILENAME_SIM : string := ""; DEVICE_FAMILY : string := "Unknown"; PART_NAME : string := "Unknown"; DEVICE_ID : string := "Unknown"; SECTOR1_START_ADDR : integer := 0; SECTOR1_END_ADDR : integer := 0; SECTOR2_START_ADDR : integer := 0; SECTOR2_END_ADDR : integer := 0; SECTOR3_START_ADDR : integer := 0; SECTOR3_END_ADDR : integer := 0; SECTOR4_START_ADDR : integer := 0; SECTOR4_END_ADDR : integer := 0; SECTOR5_START_ADDR : integer := 0; SECTOR5_END_ADDR : integer := 0; MIN_VALID_ADDR : integer := 0; MAX_VALID_ADDR : integer := 0; MIN_UFM_VALID_ADDR : integer := 0; MAX_UFM_VALID_ADDR : integer := 0; SECTOR1_MAP : integer := 0; SECTOR2_MAP : integer := 0; SECTOR3_MAP : integer := 0; SECTOR4_MAP : integer := 0; SECTOR5_MAP : integer := 0; ADDR_RANGE1_END_ADDR : integer := 0; ADDR_RANGE1_OFFSET : integer := 0; ADDR_RANGE2_OFFSET : integer := 0; AVMM_DATA_ADDR_WIDTH : integer := 19; AVMM_DATA_DATA_WIDTH : integer := 32; AVMM_DATA_BURSTCOUNT_WIDTH : integer := 4; SECTOR_READ_PROTECTION_MODE : integer := 31; FLASH_SEQ_READ_DATA_COUNT : integer := 2; FLASH_ADDR_ALIGNMENT_BITS : integer := 1; FLASH_READ_CYCLE_MAX_INDEX : integer := 4; FLASH_RESET_CYCLE_MAX_INDEX : integer := 29; FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX : integer := 112; FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX : integer := 40603248; FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX : integer := 35382; PARALLEL_MODE : boolean := true; READ_AND_WRITE_MODE : boolean := true; WRAPPING_BURST_MODE : boolean := false; IS_DUAL_BOOT : string := "False"; IS_ERAM_SKIP : string := "False"; IS_COMPRESSED_IMAGE : string := "False" ); port ( clock : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n avmm_data_addr : in std_logic_vector(15 downto 0) := (others => 'X'); -- address avmm_data_read : in std_logic := 'X'; -- read avmm_data_readdata : out std_logic_vector(31 downto 0); -- readdata avmm_data_waitrequest : out std_logic; -- waitrequest avmm_data_readdatavalid : out std_logic; -- readdatavalid avmm_data_burstcount : in std_logic_vector(3 downto 0) := (others => 'X'); -- burstcount avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata avmm_data_write : in std_logic := 'X'; -- write avmm_csr_addr : in std_logic := 'X'; -- address avmm_csr_read : in std_logic := 'X'; -- read avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata avmm_csr_write : in std_logic := 'X'; -- write avmm_csr_readdata : out std_logic_vector(31 downto 0) -- readdata ); end component altera_onchip_flash; component wasca_onchip_memory2_0 is port ( clk : in std_logic := 'X'; -- clk address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address clken : in std_logic := 'X'; -- clken chipselect : in std_logic := 'X'; -- chipselect write : in std_logic := 'X'; -- write readdata : out std_logic_vector(31 downto 0); -- readdata writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable reset : in std_logic := 'X'; -- reset reset_req : in std_logic := 'X' -- reset_req ); end component wasca_onchip_memory2_0; component sega_saturn_abus_slave is port ( clock : in std_logic := 'X'; -- clk abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect abus_read : in std_logic := 'X'; -- read abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write abus_waitrequest : out std_logic; -- waitrequest abus_interrupt : out std_logic; -- interrupt abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata abus_direction : out std_logic; -- direction abus_muxing : out std_logic_vector(1 downto 0); -- muxing abus_disable_out : out std_logic; -- disableout avalon_read : out std_logic; -- read avalon_write : out std_logic; -- write avalon_waitrequest : in std_logic := 'X'; -- waitrequest avalon_address : out std_logic_vector(27 downto 0); -- address avalon_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata avalon_writedata : out std_logic_vector(15 downto 0); -- writedata avalon_readdatavalid : in std_logic := 'X'; -- readdatavalid avalon_burstcount : out std_logic; -- burstcount reset : in std_logic := 'X'; -- reset saturn_reset : in std_logic := 'X'; -- saturn_reset avalon_nios_read : in std_logic := 'X'; -- read avalon_nios_write : in std_logic := 'X'; -- write avalon_nios_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata avalon_nios_readdata : out std_logic_vector(15 downto 0); -- readdata avalon_nios_waitrequest : out std_logic; -- waitrequest avalon_nios_readdatavalid : out std_logic; -- readdatavalid avalon_nios_burstcount : in std_logic := 'X' -- burstcount ); end component sega_saturn_abus_slave; component wasca_spi_sd_card is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n data_from_cpu : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata data_to_cpu : out std_logic_vector(15 downto 0); -- readdata mem_addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- address read_n : in std_logic := 'X'; -- read_n spi_select : in std_logic := 'X'; -- chipselect write_n : in std_logic := 'X'; -- write_n irq : out std_logic; -- irq MISO : in std_logic := 'X'; -- export MOSI : out std_logic; -- export SCLK : out std_logic; -- export SS_n : out std_logic -- export ); end component wasca_spi_sd_card; component wasca_spi_stm32 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n data_from_cpu : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata data_to_cpu : out std_logic_vector(15 downto 0); -- readdata mem_addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- address read_n : in std_logic := 'X'; -- read_n spi_select : in std_logic := 'X'; -- chipselect write_n : in std_logic := 'X'; -- write_n irq : out std_logic; -- irq MISO : out std_logic; -- export MOSI : in std_logic := 'X'; -- export SCLK : in std_logic := 'X'; -- export SS_n : in std_logic := 'X' -- export ); end component wasca_spi_stm32; component wasca_uart_0 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address begintransfer : in std_logic := 'X'; -- begintransfer chipselect : in std_logic := 'X'; -- chipselect read_n : in std_logic := 'X'; -- read_n write_n : in std_logic := 'X'; -- write_n writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata readdata : out std_logic_vector(15 downto 0); -- readdata dataavailable : out std_logic; -- dataavailable readyfordata : out std_logic; -- readyfordata rxd : in std_logic := 'X'; -- export txd : out std_logic; -- export irq : out std_logic -- irq ); end component wasca_uart_0; component wasca_mm_interconnect_0 is port ( altpll_0_c0_clk : in std_logic := 'X'; -- clk clk_0_clk_clk : in std_logic := 'X'; -- clk altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset nios2_gen2_0_data_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess nios2_gen2_0_instruction_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata sega_saturn_abus_slave_0_avalon_master_address : in std_logic_vector(27 downto 0) := (others => 'X'); -- address sega_saturn_abus_slave_0_avalon_master_waitrequest : out std_logic; -- waitrequest sega_saturn_abus_slave_0_avalon_master_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount sega_saturn_abus_slave_0_avalon_master_read : in std_logic := 'X'; -- read sega_saturn_abus_slave_0_avalon_master_readdata : out std_logic_vector(15 downto 0); -- readdata sega_saturn_abus_slave_0_avalon_master_readdatavalid : out std_logic; -- readdatavalid sega_saturn_abus_slave_0_avalon_master_write : in std_logic := 'X'; -- write sega_saturn_abus_slave_0_avalon_master_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata altpll_0_pll_slave_address : out std_logic_vector(1 downto 0); -- address altpll_0_pll_slave_write : out std_logic; -- write altpll_0_pll_slave_read : out std_logic; -- read altpll_0_pll_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata altpll_0_pll_slave_writedata : out std_logic_vector(31 downto 0); -- writedata audio_0_avalon_audio_slave_address : out std_logic_vector(1 downto 0); -- address audio_0_avalon_audio_slave_write : out std_logic; -- write audio_0_avalon_audio_slave_read : out std_logic; -- read audio_0_avalon_audio_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata audio_0_avalon_audio_slave_writedata : out std_logic_vector(31 downto 0); -- writedata audio_0_avalon_audio_slave_chipselect : out std_logic; -- chipselect external_sdram_controller_s1_address : out std_logic_vector(23 downto 0); -- address external_sdram_controller_s1_write : out std_logic; -- write external_sdram_controller_s1_read : out std_logic; -- read external_sdram_controller_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata external_sdram_controller_s1_writedata : out std_logic_vector(15 downto 0); -- writedata external_sdram_controller_s1_byteenable : out std_logic_vector(1 downto 0); -- byteenable external_sdram_controller_s1_readdatavalid : in std_logic := 'X'; -- readdatavalid external_sdram_controller_s1_waitrequest : in std_logic := 'X'; -- waitrequest external_sdram_controller_s1_chipselect : out std_logic; -- chipselect nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess onchip_flash_0_data_address : out std_logic_vector(15 downto 0); -- address onchip_flash_0_data_read : out std_logic; -- read onchip_flash_0_data_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata onchip_flash_0_data_burstcount : out std_logic_vector(3 downto 0); -- burstcount onchip_flash_0_data_readdatavalid : in std_logic := 'X'; -- readdatavalid onchip_flash_0_data_waitrequest : in std_logic := 'X'; -- waitrequest onchip_memory2_0_s1_address : out std_logic_vector(11 downto 0); -- address onchip_memory2_0_s1_write : out std_logic; -- write onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect onchip_memory2_0_s1_clken : out std_logic; -- clken sega_saturn_abus_slave_0_avalon_nios_address : out std_logic_vector(7 downto 0); -- address sega_saturn_abus_slave_0_avalon_nios_write : out std_logic; -- write sega_saturn_abus_slave_0_avalon_nios_read : out std_logic; -- read sega_saturn_abus_slave_0_avalon_nios_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata sega_saturn_abus_slave_0_avalon_nios_writedata : out std_logic_vector(15 downto 0); -- writedata sega_saturn_abus_slave_0_avalon_nios_burstcount : out std_logic_vector(0 downto 0); -- burstcount sega_saturn_abus_slave_0_avalon_nios_readdatavalid : in std_logic := 'X'; -- readdatavalid sega_saturn_abus_slave_0_avalon_nios_waitrequest : in std_logic := 'X'; -- waitrequest spi_sd_card_spi_control_port_address : out std_logic_vector(2 downto 0); -- address spi_sd_card_spi_control_port_write : out std_logic; -- write spi_sd_card_spi_control_port_read : out std_logic; -- read spi_sd_card_spi_control_port_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata spi_sd_card_spi_control_port_writedata : out std_logic_vector(15 downto 0); -- writedata spi_sd_card_spi_control_port_chipselect : out std_logic; -- chipselect spi_stm32_spi_control_port_address : out std_logic_vector(2 downto 0); -- address spi_stm32_spi_control_port_write : out std_logic; -- write spi_stm32_spi_control_port_read : out std_logic; -- read spi_stm32_spi_control_port_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata spi_stm32_spi_control_port_writedata : out std_logic_vector(15 downto 0); -- writedata spi_stm32_spi_control_port_chipselect : out std_logic; -- chipselect uart_0_s1_address : out std_logic_vector(2 downto 0); -- address uart_0_s1_write : out std_logic; -- write uart_0_s1_read : out std_logic; -- read uart_0_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata uart_0_s1_writedata : out std_logic_vector(15 downto 0); -- writedata uart_0_s1_begintransfer : out std_logic; -- begintransfer uart_0_s1_chipselect : out std_logic -- chipselect ); end component wasca_mm_interconnect_0; component wasca_irq_mapper is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset receiver0_irq : in std_logic := 'X'; -- irq receiver1_irq : in std_logic := 'X'; -- irq receiver2_irq : in std_logic := 'X'; -- irq receiver3_irq : in std_logic := 'X'; -- irq sender_irq : out std_logic_vector(31 downto 0) -- irq ); end component wasca_irq_mapper; component wasca_rst_controller is generic ( NUM_RESET_INPUTS : integer := 6; OUTPUT_RESET_SYNC_EDGES : string := "deassert"; SYNC_DEPTH : integer := 2; RESET_REQUEST_PRESENT : integer := 0; RESET_REQ_WAIT_TIME : integer := 1; MIN_RST_ASSERTION_TIME : integer := 3; RESET_REQ_EARLY_DSRT_TIME : integer := 1; USE_RESET_REQUEST_IN0 : integer := 0; USE_RESET_REQUEST_IN1 : integer := 0; USE_RESET_REQUEST_IN2 : integer := 0; USE_RESET_REQUEST_IN3 : integer := 0; USE_RESET_REQUEST_IN4 : integer := 0; USE_RESET_REQUEST_IN5 : integer := 0; USE_RESET_REQUEST_IN6 : integer := 0; USE_RESET_REQUEST_IN7 : integer := 0; USE_RESET_REQUEST_IN8 : integer := 0; USE_RESET_REQUEST_IN9 : integer := 0; USE_RESET_REQUEST_IN10 : integer := 0; USE_RESET_REQUEST_IN11 : integer := 0; USE_RESET_REQUEST_IN12 : integer := 0; USE_RESET_REQUEST_IN13 : integer := 0; USE_RESET_REQUEST_IN14 : integer := 0; USE_RESET_REQUEST_IN15 : integer := 0; ADAPT_RESET_REQUEST : integer := 0 ); port ( reset_in0 : in std_logic := 'X'; -- reset clk : in std_logic := 'X'; -- clk reset_out : out std_logic; -- reset reset_req : out std_logic; -- reset_req reset_req_in0 : in std_logic := 'X'; -- reset_req reset_in1 : in std_logic := 'X'; -- reset reset_req_in1 : in std_logic := 'X'; -- reset_req reset_in2 : in std_logic := 'X'; -- reset reset_req_in2 : in std_logic := 'X'; -- reset_req reset_in3 : in std_logic := 'X'; -- reset reset_req_in3 : in std_logic := 'X'; -- reset_req reset_in4 : in std_logic := 'X'; -- reset reset_req_in4 : in std_logic := 'X'; -- reset_req reset_in5 : in std_logic := 'X'; -- reset reset_req_in5 : in std_logic := 'X'; -- reset_req reset_in6 : in std_logic := 'X'; -- reset reset_req_in6 : in std_logic := 'X'; -- reset_req reset_in7 : in std_logic := 'X'; -- reset reset_req_in7 : in std_logic := 'X'; -- reset_req reset_in8 : in std_logic := 'X'; -- reset reset_req_in8 : in std_logic := 'X'; -- reset_req reset_in9 : in std_logic := 'X'; -- reset reset_req_in9 : in std_logic := 'X'; -- reset_req reset_in10 : in std_logic := 'X'; -- reset reset_req_in10 : in std_logic := 'X'; -- reset_req reset_in11 : in std_logic := 'X'; -- reset reset_req_in11 : in std_logic := 'X'; -- reset_req reset_in12 : in std_logic := 'X'; -- reset reset_req_in12 : in std_logic := 'X'; -- reset_req reset_in13 : in std_logic := 'X'; -- reset reset_req_in13 : in std_logic := 'X'; -- reset_req reset_in14 : in std_logic := 'X'; -- reset reset_req_in14 : in std_logic := 'X'; -- reset_req reset_in15 : in std_logic := 'X'; -- reset reset_req_in15 : in std_logic := 'X' -- reset_req ); end component wasca_rst_controller; component wasca_rst_controller_001 is generic ( NUM_RESET_INPUTS : integer := 6; OUTPUT_RESET_SYNC_EDGES : string := "deassert"; SYNC_DEPTH : integer := 2; RESET_REQUEST_PRESENT : integer := 0; RESET_REQ_WAIT_TIME : integer := 1; MIN_RST_ASSERTION_TIME : integer := 3; RESET_REQ_EARLY_DSRT_TIME : integer := 1; USE_RESET_REQUEST_IN0 : integer := 0; USE_RESET_REQUEST_IN1 : integer := 0; USE_RESET_REQUEST_IN2 : integer := 0; USE_RESET_REQUEST_IN3 : integer := 0; USE_RESET_REQUEST_IN4 : integer := 0; USE_RESET_REQUEST_IN5 : integer := 0; USE_RESET_REQUEST_IN6 : integer := 0; USE_RESET_REQUEST_IN7 : integer := 0; USE_RESET_REQUEST_IN8 : integer := 0; USE_RESET_REQUEST_IN9 : integer := 0; USE_RESET_REQUEST_IN10 : integer := 0; USE_RESET_REQUEST_IN11 : integer := 0; USE_RESET_REQUEST_IN12 : integer := 0; USE_RESET_REQUEST_IN13 : integer := 0; USE_RESET_REQUEST_IN14 : integer := 0; USE_RESET_REQUEST_IN15 : integer := 0; ADAPT_RESET_REQUEST : integer := 0 ); port ( reset_in0 : in std_logic := 'X'; -- reset clk : in std_logic := 'X'; -- clk reset_out : out std_logic; -- reset reset_req : out std_logic; -- reset_req reset_req_in0 : in std_logic := 'X'; -- reset_req reset_in1 : in std_logic := 'X'; -- reset reset_req_in1 : in std_logic := 'X'; -- reset_req reset_in2 : in std_logic := 'X'; -- reset reset_req_in2 : in std_logic := 'X'; -- reset_req reset_in3 : in std_logic := 'X'; -- reset reset_req_in3 : in std_logic := 'X'; -- reset_req reset_in4 : in std_logic := 'X'; -- reset reset_req_in4 : in std_logic := 'X'; -- reset_req reset_in5 : in std_logic := 'X'; -- reset reset_req_in5 : in std_logic := 'X'; -- reset_req reset_in6 : in std_logic := 'X'; -- reset reset_req_in6 : in std_logic := 'X'; -- reset_req reset_in7 : in std_logic := 'X'; -- reset reset_req_in7 : in std_logic := 'X'; -- reset_req reset_in8 : in std_logic := 'X'; -- reset reset_req_in8 : in std_logic := 'X'; -- reset_req reset_in9 : in std_logic := 'X'; -- reset reset_req_in9 : in std_logic := 'X'; -- reset_req reset_in10 : in std_logic := 'X'; -- reset reset_req_in10 : in std_logic := 'X'; -- reset_req reset_in11 : in std_logic := 'X'; -- reset reset_req_in11 : in std_logic := 'X'; -- reset_req reset_in12 : in std_logic := 'X'; -- reset reset_req_in12 : in std_logic := 'X'; -- reset_req reset_in13 : in std_logic := 'X'; -- reset reset_req_in13 : in std_logic := 'X'; -- reset_req reset_in14 : in std_logic := 'X'; -- reset reset_req_in14 : in std_logic := 'X'; -- reset_req reset_in15 : in std_logic := 'X'; -- reset reset_req_in15 : in std_logic := 'X' -- reset_req ); end component wasca_rst_controller_001; signal altpll_0_c0_clk : std_logic; -- altpll_0:c0 -> [clock_116_mhz_clk, audio_0:clk, external_sdram_controller:clk, irq_mapper:clk, mm_interconnect_0:altpll_0_c0_clk, nios2_gen2_0:clk, onchip_flash_0:clock, onchip_memory2_0:clk, rst_controller_001:clk, rst_controller_002:clk, sega_saturn_abus_slave_0:clock, spi_sd_card:clk, spi_stm32:clk, uart_0:clk] signal nios2_gen2_0_debug_reset_request_reset : std_logic; -- nios2_gen2_0:debug_reset_request -> [rst_controller:reset_in0, rst_controller_001:reset_in0, rst_controller_002:reset_in0] signal sega_saturn_abus_slave_0_avalon_master_waitrequest : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_waitrequest -> sega_saturn_abus_slave_0:avalon_waitrequest signal sega_saturn_abus_slave_0_avalon_master_readdata : std_logic_vector(15 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_readdata -> sega_saturn_abus_slave_0:avalon_readdata signal sega_saturn_abus_slave_0_avalon_master_read : std_logic; -- sega_saturn_abus_slave_0:avalon_read -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_read signal sega_saturn_abus_slave_0_avalon_master_address : std_logic_vector(27 downto 0); -- sega_saturn_abus_slave_0:avalon_address -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_address signal sega_saturn_abus_slave_0_avalon_master_readdatavalid : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_readdatavalid -> sega_saturn_abus_slave_0:avalon_readdatavalid signal sega_saturn_abus_slave_0_avalon_master_write : std_logic; -- sega_saturn_abus_slave_0:avalon_write -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_write signal sega_saturn_abus_slave_0_avalon_master_writedata : std_logic_vector(15 downto 0); -- sega_saturn_abus_slave_0:avalon_writedata -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_writedata signal sega_saturn_abus_slave_0_avalon_master_burstcount : std_logic; -- sega_saturn_abus_slave_0:avalon_burstcount -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_burstcount signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess signal nios2_gen2_0_data_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest signal nios2_gen2_0_instruction_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read signal mm_interconnect_0_external_sdram_controller_s1_chipselect : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_chipselect -> external_sdram_controller:az_cs signal mm_interconnect_0_external_sdram_controller_s1_readdata : std_logic_vector(15 downto 0); -- external_sdram_controller:za_data -> mm_interconnect_0:external_sdram_controller_s1_readdata signal mm_interconnect_0_external_sdram_controller_s1_waitrequest : std_logic; -- external_sdram_controller:za_waitrequest -> mm_interconnect_0:external_sdram_controller_s1_waitrequest signal mm_interconnect_0_external_sdram_controller_s1_address : std_logic_vector(23 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_address -> external_sdram_controller:az_addr signal mm_interconnect_0_external_sdram_controller_s1_read : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_read -> mm_interconnect_0_external_sdram_controller_s1_read:in signal mm_interconnect_0_external_sdram_controller_s1_byteenable : std_logic_vector(1 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_byteenable -> mm_interconnect_0_external_sdram_controller_s1_byteenable:in signal mm_interconnect_0_external_sdram_controller_s1_readdatavalid : std_logic; -- external_sdram_controller:za_valid -> mm_interconnect_0:external_sdram_controller_s1_readdatavalid signal mm_interconnect_0_external_sdram_controller_s1_write : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_write -> mm_interconnect_0_external_sdram_controller_s1_write:in signal mm_interconnect_0_external_sdram_controller_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_writedata -> external_sdram_controller:az_data signal mm_interconnect_0_onchip_flash_0_data_readdata : std_logic_vector(31 downto 0); -- onchip_flash_0:avmm_data_readdata -> mm_interconnect_0:onchip_flash_0_data_readdata signal mm_interconnect_0_onchip_flash_0_data_waitrequest : std_logic; -- onchip_flash_0:avmm_data_waitrequest -> mm_interconnect_0:onchip_flash_0_data_waitrequest signal mm_interconnect_0_onchip_flash_0_data_address : std_logic_vector(15 downto 0); -- mm_interconnect_0:onchip_flash_0_data_address -> onchip_flash_0:avmm_data_addr signal mm_interconnect_0_onchip_flash_0_data_read : std_logic; -- mm_interconnect_0:onchip_flash_0_data_read -> onchip_flash_0:avmm_data_read signal mm_interconnect_0_onchip_flash_0_data_readdatavalid : std_logic; -- onchip_flash_0:avmm_data_readdatavalid -> mm_interconnect_0:onchip_flash_0_data_readdatavalid signal mm_interconnect_0_onchip_flash_0_data_burstcount : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_flash_0_data_burstcount -> onchip_flash_0:avmm_data_burstcount signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(11 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken signal mm_interconnect_0_audio_0_avalon_audio_slave_chipselect : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_chipselect -> audio_0:chipselect signal mm_interconnect_0_audio_0_avalon_audio_slave_readdata : std_logic_vector(31 downto 0); -- audio_0:readdata -> mm_interconnect_0:audio_0_avalon_audio_slave_readdata signal mm_interconnect_0_audio_0_avalon_audio_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:audio_0_avalon_audio_slave_address -> audio_0:address signal mm_interconnect_0_audio_0_avalon_audio_slave_read : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_read -> audio_0:read signal mm_interconnect_0_audio_0_avalon_audio_slave_write : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_write -> audio_0:write signal mm_interconnect_0_audio_0_avalon_audio_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:audio_0_avalon_audio_slave_writedata -> audio_0:writedata signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata : std_logic_vector(15 downto 0); -- sega_saturn_abus_slave_0:avalon_nios_readdata -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_readdata signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest : std_logic; -- sega_saturn_abus_slave_0:avalon_nios_waitrequest -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_waitrequest signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_address -> sega_saturn_abus_slave_0:avalon_nios_address signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_read -> sega_saturn_abus_slave_0:avalon_nios_read signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid : std_logic; -- sega_saturn_abus_slave_0:avalon_nios_readdatavalid -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_readdatavalid signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_write -> sega_saturn_abus_slave_0:avalon_nios_write signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_writedata -> sega_saturn_abus_slave_0:avalon_nios_writedata signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount : std_logic_vector(0 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_burstcount -> sega_saturn_abus_slave_0:avalon_nios_burstcount signal mm_interconnect_0_altpll_0_pll_slave_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> mm_interconnect_0:altpll_0_pll_slave_readdata signal mm_interconnect_0_altpll_0_pll_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_address -> altpll_0:address signal mm_interconnect_0_altpll_0_pll_slave_read : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_read -> altpll_0:read signal mm_interconnect_0_altpll_0_pll_slave_write : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_write -> altpll_0:write signal mm_interconnect_0_altpll_0_pll_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_writedata -> altpll_0:writedata signal mm_interconnect_0_uart_0_s1_chipselect : std_logic; -- mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect signal mm_interconnect_0_uart_0_s1_readdata : std_logic_vector(15 downto 0); -- uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata signal mm_interconnect_0_uart_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:uart_0_s1_address -> uart_0:address signal mm_interconnect_0_uart_0_s1_read : std_logic; -- mm_interconnect_0:uart_0_s1_read -> mm_interconnect_0_uart_0_s1_read:in signal mm_interconnect_0_uart_0_s1_begintransfer : std_logic; -- mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer signal mm_interconnect_0_uart_0_s1_write : std_logic; -- mm_interconnect_0:uart_0_s1_write -> mm_interconnect_0_uart_0_s1_write:in signal mm_interconnect_0_uart_0_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata signal mm_interconnect_0_spi_sd_card_spi_control_port_chipselect : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_chipselect -> spi_sd_card:spi_select signal mm_interconnect_0_spi_sd_card_spi_control_port_readdata : std_logic_vector(15 downto 0); -- spi_sd_card:data_to_cpu -> mm_interconnect_0:spi_sd_card_spi_control_port_readdata signal mm_interconnect_0_spi_sd_card_spi_control_port_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:spi_sd_card_spi_control_port_address -> spi_sd_card:mem_addr signal mm_interconnect_0_spi_sd_card_spi_control_port_read : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_read -> mm_interconnect_0_spi_sd_card_spi_control_port_read:in signal mm_interconnect_0_spi_sd_card_spi_control_port_write : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_write -> mm_interconnect_0_spi_sd_card_spi_control_port_write:in signal mm_interconnect_0_spi_sd_card_spi_control_port_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:spi_sd_card_spi_control_port_writedata -> spi_sd_card:data_from_cpu signal mm_interconnect_0_spi_stm32_spi_control_port_chipselect : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_chipselect -> spi_stm32:spi_select signal mm_interconnect_0_spi_stm32_spi_control_port_readdata : std_logic_vector(15 downto 0); -- spi_stm32:data_to_cpu -> mm_interconnect_0:spi_stm32_spi_control_port_readdata signal mm_interconnect_0_spi_stm32_spi_control_port_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:spi_stm32_spi_control_port_address -> spi_stm32:mem_addr signal mm_interconnect_0_spi_stm32_spi_control_port_read : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_read -> mm_interconnect_0_spi_stm32_spi_control_port_read:in signal mm_interconnect_0_spi_stm32_spi_control_port_write : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_write -> mm_interconnect_0_spi_stm32_spi_control_port_write:in signal mm_interconnect_0_spi_stm32_spi_control_port_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:spi_stm32_spi_control_port_writedata -> spi_stm32:data_from_cpu signal irq_mapper_receiver0_irq : std_logic; -- audio_0:irq -> irq_mapper:receiver0_irq signal irq_mapper_receiver1_irq : std_logic; -- uart_0:irq -> irq_mapper:receiver1_irq signal irq_mapper_receiver2_irq : std_logic; -- spi_sd_card:irq -> irq_mapper:receiver2_irq signal irq_mapper_receiver3_irq : std_logic; -- spi_stm32:irq -> irq_mapper:receiver3_irq signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [altpll_0:reset, mm_interconnect_0:altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset] signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [audio_0:reset, irq_mapper:reset, mm_interconnect_0:sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_001_reset_out_reset:in, rst_translator:in_reset, sega_saturn_abus_slave_0:reset] signal rst_controller_001_reset_out_reset_req : std_logic; -- rst_controller_001:reset_req -> [onchip_memory2_0:reset_req, rst_translator:reset_req_in] signal mm_interconnect_0_external_sdram_controller_s1_read_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_read:inv -> external_sdram_controller:az_rd_n signal mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv : std_logic_vector(1 downto 0); -- mm_interconnect_0_external_sdram_controller_s1_byteenable:inv -> external_sdram_controller:az_be_n signal mm_interconnect_0_external_sdram_controller_s1_write_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_write:inv -> external_sdram_controller:az_wr_n signal mm_interconnect_0_uart_0_s1_read_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_read:inv -> uart_0:read_n signal mm_interconnect_0_uart_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_write:inv -> uart_0:write_n signal mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv : std_logic; -- mm_interconnect_0_spi_sd_card_spi_control_port_read:inv -> spi_sd_card:read_n signal mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv : std_logic; -- mm_interconnect_0_spi_sd_card_spi_control_port_write:inv -> spi_sd_card:write_n signal mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv : std_logic; -- mm_interconnect_0_spi_stm32_spi_control_port_read:inv -> spi_stm32:read_n signal mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv : std_logic; -- mm_interconnect_0_spi_stm32_spi_control_port_write:inv -> spi_stm32:write_n signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> [external_sdram_controller:reset_n, nios2_gen2_0:reset_n, onchip_flash_0:reset_n, spi_sd_card:reset_n, spi_stm32:reset_n, uart_0:reset_n] begin altpll_0 : component wasca_altpll_0 port map ( clk => clk_clk, -- inclk_interface.clk reset => rst_controller_reset_out_reset, -- inclk_interface_reset.reset read => mm_interconnect_0_altpll_0_pll_slave_read, -- pll_slave.read write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write address => mm_interconnect_0_altpll_0_pll_slave_address, -- .address readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata c0 => altpll_0_c0_clk, -- c0.clk areset => altpll_0_areset_conduit_export, -- areset_conduit.export c1 => open, -- c1_conduit.export locked => altpll_0_locked_conduit_export, -- locked_conduit.export phasedone => altpll_0_phasedone_conduit_export -- phasedone_conduit.export ); audio_0 : component wasca_audio_0 port map ( clk => altpll_0_c0_clk, -- clk.clk reset => rst_controller_001_reset_out_reset, -- reset.reset address => mm_interconnect_0_audio_0_avalon_audio_slave_address, -- avalon_audio_slave.address chipselect => mm_interconnect_0_audio_0_avalon_audio_slave_chipselect, -- .chipselect read => mm_interconnect_0_audio_0_avalon_audio_slave_read, -- .read write => mm_interconnect_0_audio_0_avalon_audio_slave_write, -- .write writedata => mm_interconnect_0_audio_0_avalon_audio_slave_writedata, -- .writedata readdata => mm_interconnect_0_audio_0_avalon_audio_slave_readdata, -- .readdata irq => irq_mapper_receiver0_irq, -- interrupt.irq AUD_BCLK => audio_out_BCLK, -- external_interface.export AUD_DACDAT => audio_out_DACDAT, -- .export AUD_DACLRCK => audio_out_DACLRCK -- .export ); external_sdram_controller : component wasca_external_sdram_controller port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n az_addr => mm_interconnect_0_external_sdram_controller_s1_address, -- s1.address az_be_n => mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv, -- .byteenable_n az_cs => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect az_data => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata az_rd_n => mm_interconnect_0_external_sdram_controller_s1_read_ports_inv, -- .read_n az_wr_n => mm_interconnect_0_external_sdram_controller_s1_write_ports_inv, -- .write_n za_data => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata za_valid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid za_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest zs_addr => external_sdram_controller_wire_addr, -- wire.export zs_ba => external_sdram_controller_wire_ba, -- .export zs_cas_n => external_sdram_controller_wire_cas_n, -- .export zs_cke => external_sdram_controller_wire_cke, -- .export zs_cs_n => external_sdram_controller_wire_cs_n, -- .export zs_dq => external_sdram_controller_wire_dq, -- .export zs_dqm => external_sdram_controller_wire_dqm, -- .export zs_ras_n => external_sdram_controller_wire_ras_n, -- .export zs_we_n => external_sdram_controller_wire_we_n -- .export ); nios2_gen2_0 : component wasca_nios2_gen2_0 port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n d_address => nios2_gen2_0_data_master_address, -- data_master.address d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable d_read => nios2_gen2_0_data_master_read, -- .read d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest d_write => nios2_gen2_0_data_master_write, -- .write d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address i_read => nios2_gen2_0_instruction_master_read, -- .read i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest irq => nios2_gen2_0_irq_irq, -- irq.irq debug_reset_request => nios2_gen2_0_debug_reset_request_reset, -- debug_reset_request.reset debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata dummy_ci_port => open -- custom_instruction_master.readra ); onchip_flash_0 : component altera_onchip_flash generic map ( INIT_FILENAME => "", INIT_FILENAME_SIM => "", DEVICE_FAMILY => "MAX 10", PART_NAME => "10M08SAE144C8GES", DEVICE_ID => "08", SECTOR1_START_ADDR => 0, SECTOR1_END_ADDR => 4095, SECTOR2_START_ADDR => 4096, SECTOR2_END_ADDR => 8191, SECTOR3_START_ADDR => 8192, SECTOR3_END_ADDR => 29183, SECTOR4_START_ADDR => 29184, SECTOR4_END_ADDR => 44031, SECTOR5_START_ADDR => 0, SECTOR5_END_ADDR => 0, MIN_VALID_ADDR => 0, MAX_VALID_ADDR => 44031, MIN_UFM_VALID_ADDR => 0, MAX_UFM_VALID_ADDR => 44031, SECTOR1_MAP => 1, SECTOR2_MAP => 2, SECTOR3_MAP => 3, SECTOR4_MAP => 4, SECTOR5_MAP => 0, ADDR_RANGE1_END_ADDR => 44031, ADDR_RANGE1_OFFSET => 512, ADDR_RANGE2_OFFSET => 0, AVMM_DATA_ADDR_WIDTH => 16, AVMM_DATA_DATA_WIDTH => 32, AVMM_DATA_BURSTCOUNT_WIDTH => 4, SECTOR_READ_PROTECTION_MODE => 31, FLASH_SEQ_READ_DATA_COUNT => 2, FLASH_ADDR_ALIGNMENT_BITS => 1, FLASH_READ_CYCLE_MAX_INDEX => 3, FLASH_RESET_CYCLE_MAX_INDEX => 29, FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX => 111, FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX => 40603248, FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX => 35382, PARALLEL_MODE => true, READ_AND_WRITE_MODE => false, WRAPPING_BURST_MODE => false, IS_DUAL_BOOT => "False", IS_ERAM_SKIP => "True", IS_COMPRESSED_IMAGE => "True" ) port map ( clock => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- nreset.reset_n avmm_data_addr => mm_interconnect_0_onchip_flash_0_data_address, -- data.address avmm_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read avmm_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata avmm_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest avmm_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid avmm_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount avmm_data_writedata => "00000000000000000000000000000000", -- (terminated) avmm_data_write => '0', -- (terminated) avmm_csr_addr => '0', -- (terminated) avmm_csr_read => '0', -- (terminated) avmm_csr_writedata => "00000000000000000000000000000000", -- (terminated) avmm_csr_write => '0', -- (terminated) avmm_csr_readdata => open -- (terminated) ); onchip_memory2_0 : component wasca_onchip_memory2_0 port map ( clk => altpll_0_c0_clk, -- clk1.clk address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable reset => rst_controller_001_reset_out_reset, -- reset1.reset reset_req => rst_controller_001_reset_out_reset_req -- .reset_req ); sega_saturn_abus_slave_0 : component sega_saturn_abus_slave port map ( clock => altpll_0_c0_clk, -- clock.clk abus_address => sega_saturn_abus_slave_0_abus_address, -- abus.address abus_chipselect => sega_saturn_abus_slave_0_abus_chipselect, -- .chipselect abus_read => sega_saturn_abus_slave_0_abus_read, -- .read abus_write => sega_saturn_abus_slave_0_abus_write, -- .write abus_waitrequest => sega_saturn_abus_slave_0_abus_waitrequest, -- .waitrequest abus_interrupt => sega_saturn_abus_slave_0_abus_interrupt, -- .interrupt abus_addressdata => sega_saturn_abus_slave_0_abus_addressdata, -- .addressdata abus_direction => sega_saturn_abus_slave_0_abus_direction, -- .direction abus_muxing => sega_saturn_abus_slave_0_abus_muxing, -- .muxing abus_disable_out => sega_saturn_abus_slave_0_abus_disableout, -- .disableout avalon_read => sega_saturn_abus_slave_0_avalon_master_read, -- avalon_master.read avalon_write => sega_saturn_abus_slave_0_avalon_master_write, -- .write avalon_waitrequest => sega_saturn_abus_slave_0_avalon_master_waitrequest, -- .waitrequest avalon_address => sega_saturn_abus_slave_0_avalon_master_address, -- .address avalon_readdata => sega_saturn_abus_slave_0_avalon_master_readdata, -- .readdata avalon_writedata => sega_saturn_abus_slave_0_avalon_master_writedata, -- .writedata avalon_readdatavalid => sega_saturn_abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid avalon_burstcount => sega_saturn_abus_slave_0_avalon_master_burstcount, -- .burstcount reset => rst_controller_001_reset_out_reset, -- reset.reset saturn_reset => sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset, -- conduit_saturn_reset.saturn_reset avalon_nios_read => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read, -- avalon_nios.read avalon_nios_write => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write, -- .write avalon_nios_address => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address, -- .address avalon_nios_writedata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata, -- .writedata avalon_nios_readdata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata, -- .readdata avalon_nios_waitrequest => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest avalon_nios_readdatavalid => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid avalon_nios_burstcount => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount(0) -- .burstcount ); spi_sd_card : component wasca_spi_sd_card port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n data_from_cpu => mm_interconnect_0_spi_sd_card_spi_control_port_writedata, -- spi_control_port.writedata data_to_cpu => mm_interconnect_0_spi_sd_card_spi_control_port_readdata, -- .readdata mem_addr => mm_interconnect_0_spi_sd_card_spi_control_port_address, -- .address read_n => mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv, -- .read_n spi_select => mm_interconnect_0_spi_sd_card_spi_control_port_chipselect, -- .chipselect write_n => mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv, -- .write_n irq => irq_mapper_receiver2_irq, -- irq.irq MISO => spi_sd_card_MISO, -- external.export MOSI => spi_sd_card_MOSI, -- .export SCLK => spi_sd_card_SCLK, -- .export SS_n => spi_sd_card_SS_n -- .export ); spi_stm32 : component wasca_spi_stm32 port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n data_from_cpu => mm_interconnect_0_spi_stm32_spi_control_port_writedata, -- spi_control_port.writedata data_to_cpu => mm_interconnect_0_spi_stm32_spi_control_port_readdata, -- .readdata mem_addr => mm_interconnect_0_spi_stm32_spi_control_port_address, -- .address read_n => mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv, -- .read_n spi_select => mm_interconnect_0_spi_stm32_spi_control_port_chipselect, -- .chipselect write_n => mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv, -- .write_n irq => irq_mapper_receiver3_irq, -- irq.irq MISO => spi_stm32_MISO, -- external.export MOSI => spi_stm32_MOSI, -- .export SCLK => spi_stm32_SCLK, -- .export SS_n => spi_stm32_SS_n -- .export ); uart_0 : component wasca_uart_0 port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n address => mm_interconnect_0_uart_0_s1_address, -- s1.address begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer chipselect => mm_interconnect_0_uart_0_s1_chipselect, -- .chipselect read_n => mm_interconnect_0_uart_0_s1_read_ports_inv, -- .read_n write_n => mm_interconnect_0_uart_0_s1_write_ports_inv, -- .write_n writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata dataavailable => open, -- .dataavailable readyfordata => open, -- .readyfordata rxd => uart_0_external_connection_rxd, -- external_connection.export txd => uart_0_external_connection_txd, -- .export irq => irq_mapper_receiver1_irq -- irq.irq ); mm_interconnect_0 : component wasca_mm_interconnect_0 port map ( altpll_0_c0_clk => altpll_0_c0_clk, -- altpll_0_c0.clk clk_0_clk_clk => clk_clk, -- clk_0_clk.clk altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- sega_saturn_abus_slave_0_reset_reset_bridge_in_reset.reset nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata sega_saturn_abus_slave_0_avalon_master_address => sega_saturn_abus_slave_0_avalon_master_address, -- sega_saturn_abus_slave_0_avalon_master.address sega_saturn_abus_slave_0_avalon_master_waitrequest => sega_saturn_abus_slave_0_avalon_master_waitrequest, -- .waitrequest sega_saturn_abus_slave_0_avalon_master_burstcount(0) => sega_saturn_abus_slave_0_avalon_master_burstcount, -- .burstcount sega_saturn_abus_slave_0_avalon_master_read => sega_saturn_abus_slave_0_avalon_master_read, -- .read sega_saturn_abus_slave_0_avalon_master_readdata => sega_saturn_abus_slave_0_avalon_master_readdata, -- .readdata sega_saturn_abus_slave_0_avalon_master_readdatavalid => sega_saturn_abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid sega_saturn_abus_slave_0_avalon_master_write => sega_saturn_abus_slave_0_avalon_master_write, -- .write sega_saturn_abus_slave_0_avalon_master_writedata => sega_saturn_abus_slave_0_avalon_master_writedata, -- .writedata altpll_0_pll_slave_address => mm_interconnect_0_altpll_0_pll_slave_address, -- altpll_0_pll_slave.address altpll_0_pll_slave_write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write altpll_0_pll_slave_read => mm_interconnect_0_altpll_0_pll_slave_read, -- .read altpll_0_pll_slave_readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata altpll_0_pll_slave_writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata audio_0_avalon_audio_slave_address => mm_interconnect_0_audio_0_avalon_audio_slave_address, -- audio_0_avalon_audio_slave.address audio_0_avalon_audio_slave_write => mm_interconnect_0_audio_0_avalon_audio_slave_write, -- .write audio_0_avalon_audio_slave_read => mm_interconnect_0_audio_0_avalon_audio_slave_read, -- .read audio_0_avalon_audio_slave_readdata => mm_interconnect_0_audio_0_avalon_audio_slave_readdata, -- .readdata audio_0_avalon_audio_slave_writedata => mm_interconnect_0_audio_0_avalon_audio_slave_writedata, -- .writedata audio_0_avalon_audio_slave_chipselect => mm_interconnect_0_audio_0_avalon_audio_slave_chipselect, -- .chipselect external_sdram_controller_s1_address => mm_interconnect_0_external_sdram_controller_s1_address, -- external_sdram_controller_s1.address external_sdram_controller_s1_write => mm_interconnect_0_external_sdram_controller_s1_write, -- .write external_sdram_controller_s1_read => mm_interconnect_0_external_sdram_controller_s1_read, -- .read external_sdram_controller_s1_readdata => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata external_sdram_controller_s1_writedata => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata external_sdram_controller_s1_byteenable => mm_interconnect_0_external_sdram_controller_s1_byteenable, -- .byteenable external_sdram_controller_s1_readdatavalid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid external_sdram_controller_s1_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest external_sdram_controller_s1_chipselect => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess onchip_flash_0_data_address => mm_interconnect_0_onchip_flash_0_data_address, -- onchip_flash_0_data.address onchip_flash_0_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read onchip_flash_0_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata onchip_flash_0_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount onchip_flash_0_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid onchip_flash_0_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken sega_saturn_abus_slave_0_avalon_nios_address => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address, -- sega_saturn_abus_slave_0_avalon_nios.address sega_saturn_abus_slave_0_avalon_nios_write => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write, -- .write sega_saturn_abus_slave_0_avalon_nios_read => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read, -- .read sega_saturn_abus_slave_0_avalon_nios_readdata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata, -- .readdata sega_saturn_abus_slave_0_avalon_nios_writedata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata, -- .writedata sega_saturn_abus_slave_0_avalon_nios_burstcount => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount, -- .burstcount sega_saturn_abus_slave_0_avalon_nios_readdatavalid => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid sega_saturn_abus_slave_0_avalon_nios_waitrequest => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest spi_sd_card_spi_control_port_address => mm_interconnect_0_spi_sd_card_spi_control_port_address, -- spi_sd_card_spi_control_port.address spi_sd_card_spi_control_port_write => mm_interconnect_0_spi_sd_card_spi_control_port_write, -- .write spi_sd_card_spi_control_port_read => mm_interconnect_0_spi_sd_card_spi_control_port_read, -- .read spi_sd_card_spi_control_port_readdata => mm_interconnect_0_spi_sd_card_spi_control_port_readdata, -- .readdata spi_sd_card_spi_control_port_writedata => mm_interconnect_0_spi_sd_card_spi_control_port_writedata, -- .writedata spi_sd_card_spi_control_port_chipselect => mm_interconnect_0_spi_sd_card_spi_control_port_chipselect, -- .chipselect spi_stm32_spi_control_port_address => mm_interconnect_0_spi_stm32_spi_control_port_address, -- spi_stm32_spi_control_port.address spi_stm32_spi_control_port_write => mm_interconnect_0_spi_stm32_spi_control_port_write, -- .write spi_stm32_spi_control_port_read => mm_interconnect_0_spi_stm32_spi_control_port_read, -- .read spi_stm32_spi_control_port_readdata => mm_interconnect_0_spi_stm32_spi_control_port_readdata, -- .readdata spi_stm32_spi_control_port_writedata => mm_interconnect_0_spi_stm32_spi_control_port_writedata, -- .writedata spi_stm32_spi_control_port_chipselect => mm_interconnect_0_spi_stm32_spi_control_port_chipselect, -- .chipselect uart_0_s1_address => mm_interconnect_0_uart_0_s1_address, -- uart_0_s1.address uart_0_s1_write => mm_interconnect_0_uart_0_s1_write, -- .write uart_0_s1_read => mm_interconnect_0_uart_0_s1_read, -- .read uart_0_s1_readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata uart_0_s1_writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata uart_0_s1_begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer uart_0_s1_chipselect => mm_interconnect_0_uart_0_s1_chipselect -- .chipselect ); irq_mapper : component wasca_irq_mapper port map ( clk => altpll_0_c0_clk, -- clk.clk reset => rst_controller_001_reset_out_reset, -- clk_reset.reset receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq receiver2_irq => irq_mapper_receiver2_irq, -- receiver2.irq receiver3_irq => irq_mapper_receiver3_irq, -- receiver3.irq sender_irq => nios2_gen2_0_irq_irq -- sender.irq ); rst_controller : component wasca_rst_controller generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "deassert", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 0, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset clk => clk_clk, -- clk.clk reset_out => rst_controller_reset_out_reset, -- reset_out.reset reset_req => open, -- (terminated) reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); rst_controller_001 : component wasca_rst_controller_001 generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "deassert", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 1, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset clk => altpll_0_c0_clk, -- clk.clk reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); rst_controller_002 : component wasca_rst_controller generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "both", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 0, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset clk => altpll_0_c0_clk, -- clk.clk reset_out => open, -- reset_out.reset reset_req => open, -- (terminated) reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); mm_interconnect_0_external_sdram_controller_s1_read_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_read; mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_byteenable; mm_interconnect_0_external_sdram_controller_s1_write_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_write; mm_interconnect_0_uart_0_s1_read_ports_inv <= not mm_interconnect_0_uart_0_s1_read; mm_interconnect_0_uart_0_s1_write_ports_inv <= not mm_interconnect_0_uart_0_s1_write; mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv <= not mm_interconnect_0_spi_sd_card_spi_control_port_read; mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv <= not mm_interconnect_0_spi_sd_card_spi_control_port_write; mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv <= not mm_interconnect_0_spi_stm32_spi_control_port_read; mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv <= not mm_interconnect_0_spi_stm32_spi_control_port_write; rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset; clock_116_mhz_clk <= altpll_0_c0_clk; end architecture rtl; -- of wasca
-- wasca.vhd -- Generated using ACDS version 15.0 145 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity wasca is port ( altpll_0_areset_conduit_export : in std_logic := '0'; -- altpll_0_areset_conduit.export altpll_0_locked_conduit_export : out std_logic; -- altpll_0_locked_conduit.export altpll_0_phasedone_conduit_export : out std_logic; -- altpll_0_phasedone_conduit.export audio_out_BCLK : in std_logic := '0'; -- audio_out.BCLK audio_out_DACDAT : out std_logic; -- .DACDAT audio_out_DACLRCK : in std_logic := '0'; -- .DACLRCK clk_clk : in std_logic := '0'; -- clk.clk clock_116_mhz_clk : out std_logic; -- clock_116_mhz.clk external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n external_sdram_controller_wire_cke : out std_logic; -- .cke external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n external_sdram_controller_wire_we_n : out std_logic; -- .we_n sega_saturn_abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- sega_saturn_abus_slave_0_abus.address sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect sega_saturn_abus_slave_0_abus_read : in std_logic := '0'; -- .read sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest sega_saturn_abus_slave_0_abus_interrupt : out std_logic; -- .interrupt sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .addressdata sega_saturn_abus_slave_0_abus_direction : out std_logic; -- .direction sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- .muxing sega_saturn_abus_slave_0_abus_disableout : out std_logic; -- .disableout sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := '0'; -- sega_saturn_abus_slave_0_conduit_saturn_reset.saturn_reset spi_sd_card_MISO : in std_logic := '0'; -- spi_sd_card.MISO spi_sd_card_MOSI : out std_logic; -- .MOSI spi_sd_card_SCLK : out std_logic; -- .SCLK spi_sd_card_SS_n : out std_logic; -- .SS_n spi_stm32_MISO : out std_logic; -- spi_stm32.MISO spi_stm32_MOSI : in std_logic := '0'; -- .MOSI spi_stm32_SCLK : in std_logic := '0'; -- .SCLK spi_stm32_SS_n : in std_logic := '0'; -- .SS_n uart_0_external_connection_rxd : in std_logic := '0'; -- uart_0_external_connection.rxd uart_0_external_connection_txd : out std_logic -- .txd ); end entity wasca; architecture rtl of wasca is component wasca_altpll_0 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset read : in std_logic := 'X'; -- read write : in std_logic := 'X'; -- write address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address readdata : out std_logic_vector(31 downto 0); -- readdata writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata c0 : out std_logic; -- clk areset : in std_logic := 'X'; -- export c1 : out std_logic; -- export locked : out std_logic; -- export phasedone : out std_logic -- export ); end component wasca_altpll_0; component wasca_audio_0 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address chipselect : in std_logic := 'X'; -- chipselect read : in std_logic := 'X'; -- read write : in std_logic := 'X'; -- write writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata readdata : out std_logic_vector(31 downto 0); -- readdata irq : out std_logic; -- irq AUD_BCLK : in std_logic := 'X'; -- export AUD_DACDAT : out std_logic; -- export AUD_DACLRCK : in std_logic := 'X' -- export ); end component wasca_audio_0; component wasca_external_sdram_controller is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n az_addr : in std_logic_vector(23 downto 0) := (others => 'X'); -- address az_be_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable_n az_cs : in std_logic := 'X'; -- chipselect az_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata az_rd_n : in std_logic := 'X'; -- read_n az_wr_n : in std_logic := 'X'; -- write_n za_data : out std_logic_vector(15 downto 0); -- readdata za_valid : out std_logic; -- readdatavalid za_waitrequest : out std_logic; -- waitrequest zs_addr : out std_logic_vector(12 downto 0); -- export zs_ba : out std_logic_vector(1 downto 0); -- export zs_cas_n : out std_logic; -- export zs_cke : out std_logic; -- export zs_cs_n : out std_logic; -- export zs_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export zs_dqm : out std_logic_vector(1 downto 0); -- export zs_ras_n : out std_logic; -- export zs_we_n : out std_logic -- export ); end component wasca_external_sdram_controller; component wasca_nios2_gen2_0 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n d_address : out std_logic_vector(26 downto 0); -- address d_byteenable : out std_logic_vector(3 downto 0); -- byteenable d_read : out std_logic; -- read d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata d_waitrequest : in std_logic := 'X'; -- waitrequest d_write : out std_logic; -- write d_writedata : out std_logic_vector(31 downto 0); -- writedata debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess i_address : out std_logic_vector(26 downto 0); -- address i_read : out std_logic; -- read i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata i_waitrequest : in std_logic := 'X'; -- waitrequest irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq debug_reset_request : out std_logic; -- reset debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess debug_mem_slave_read : in std_logic := 'X'; -- read debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata debug_mem_slave_waitrequest : out std_logic; -- waitrequest debug_mem_slave_write : in std_logic := 'X'; -- write debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata dummy_ci_port : out std_logic -- readra ); end component wasca_nios2_gen2_0; component altera_onchip_flash is generic ( INIT_FILENAME : string := ""; INIT_FILENAME_SIM : string := ""; DEVICE_FAMILY : string := "Unknown"; PART_NAME : string := "Unknown"; DEVICE_ID : string := "Unknown"; SECTOR1_START_ADDR : integer := 0; SECTOR1_END_ADDR : integer := 0; SECTOR2_START_ADDR : integer := 0; SECTOR2_END_ADDR : integer := 0; SECTOR3_START_ADDR : integer := 0; SECTOR3_END_ADDR : integer := 0; SECTOR4_START_ADDR : integer := 0; SECTOR4_END_ADDR : integer := 0; SECTOR5_START_ADDR : integer := 0; SECTOR5_END_ADDR : integer := 0; MIN_VALID_ADDR : integer := 0; MAX_VALID_ADDR : integer := 0; MIN_UFM_VALID_ADDR : integer := 0; MAX_UFM_VALID_ADDR : integer := 0; SECTOR1_MAP : integer := 0; SECTOR2_MAP : integer := 0; SECTOR3_MAP : integer := 0; SECTOR4_MAP : integer := 0; SECTOR5_MAP : integer := 0; ADDR_RANGE1_END_ADDR : integer := 0; ADDR_RANGE1_OFFSET : integer := 0; ADDR_RANGE2_OFFSET : integer := 0; AVMM_DATA_ADDR_WIDTH : integer := 19; AVMM_DATA_DATA_WIDTH : integer := 32; AVMM_DATA_BURSTCOUNT_WIDTH : integer := 4; SECTOR_READ_PROTECTION_MODE : integer := 31; FLASH_SEQ_READ_DATA_COUNT : integer := 2; FLASH_ADDR_ALIGNMENT_BITS : integer := 1; FLASH_READ_CYCLE_MAX_INDEX : integer := 4; FLASH_RESET_CYCLE_MAX_INDEX : integer := 29; FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX : integer := 112; FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX : integer := 40603248; FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX : integer := 35382; PARALLEL_MODE : boolean := true; READ_AND_WRITE_MODE : boolean := true; WRAPPING_BURST_MODE : boolean := false; IS_DUAL_BOOT : string := "False"; IS_ERAM_SKIP : string := "False"; IS_COMPRESSED_IMAGE : string := "False" ); port ( clock : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n avmm_data_addr : in std_logic_vector(15 downto 0) := (others => 'X'); -- address avmm_data_read : in std_logic := 'X'; -- read avmm_data_readdata : out std_logic_vector(31 downto 0); -- readdata avmm_data_waitrequest : out std_logic; -- waitrequest avmm_data_readdatavalid : out std_logic; -- readdatavalid avmm_data_burstcount : in std_logic_vector(3 downto 0) := (others => 'X'); -- burstcount avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata avmm_data_write : in std_logic := 'X'; -- write avmm_csr_addr : in std_logic := 'X'; -- address avmm_csr_read : in std_logic := 'X'; -- read avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata avmm_csr_write : in std_logic := 'X'; -- write avmm_csr_readdata : out std_logic_vector(31 downto 0) -- readdata ); end component altera_onchip_flash; component wasca_onchip_memory2_0 is port ( clk : in std_logic := 'X'; -- clk address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address clken : in std_logic := 'X'; -- clken chipselect : in std_logic := 'X'; -- chipselect write : in std_logic := 'X'; -- write readdata : out std_logic_vector(31 downto 0); -- readdata writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable reset : in std_logic := 'X'; -- reset reset_req : in std_logic := 'X' -- reset_req ); end component wasca_onchip_memory2_0; component sega_saturn_abus_slave is port ( clock : in std_logic := 'X'; -- clk abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect abus_read : in std_logic := 'X'; -- read abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write abus_waitrequest : out std_logic; -- waitrequest abus_interrupt : out std_logic; -- interrupt abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata abus_direction : out std_logic; -- direction abus_muxing : out std_logic_vector(1 downto 0); -- muxing abus_disable_out : out std_logic; -- disableout avalon_read : out std_logic; -- read avalon_write : out std_logic; -- write avalon_waitrequest : in std_logic := 'X'; -- waitrequest avalon_address : out std_logic_vector(27 downto 0); -- address avalon_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata avalon_writedata : out std_logic_vector(15 downto 0); -- writedata avalon_readdatavalid : in std_logic := 'X'; -- readdatavalid avalon_burstcount : out std_logic; -- burstcount reset : in std_logic := 'X'; -- reset saturn_reset : in std_logic := 'X'; -- saturn_reset avalon_nios_read : in std_logic := 'X'; -- read avalon_nios_write : in std_logic := 'X'; -- write avalon_nios_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata avalon_nios_readdata : out std_logic_vector(15 downto 0); -- readdata avalon_nios_waitrequest : out std_logic; -- waitrequest avalon_nios_readdatavalid : out std_logic; -- readdatavalid avalon_nios_burstcount : in std_logic := 'X' -- burstcount ); end component sega_saturn_abus_slave; component wasca_spi_sd_card is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n data_from_cpu : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata data_to_cpu : out std_logic_vector(15 downto 0); -- readdata mem_addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- address read_n : in std_logic := 'X'; -- read_n spi_select : in std_logic := 'X'; -- chipselect write_n : in std_logic := 'X'; -- write_n irq : out std_logic; -- irq MISO : in std_logic := 'X'; -- export MOSI : out std_logic; -- export SCLK : out std_logic; -- export SS_n : out std_logic -- export ); end component wasca_spi_sd_card; component wasca_spi_stm32 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n data_from_cpu : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata data_to_cpu : out std_logic_vector(15 downto 0); -- readdata mem_addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- address read_n : in std_logic := 'X'; -- read_n spi_select : in std_logic := 'X'; -- chipselect write_n : in std_logic := 'X'; -- write_n irq : out std_logic; -- irq MISO : out std_logic; -- export MOSI : in std_logic := 'X'; -- export SCLK : in std_logic := 'X'; -- export SS_n : in std_logic := 'X' -- export ); end component wasca_spi_stm32; component wasca_uart_0 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address begintransfer : in std_logic := 'X'; -- begintransfer chipselect : in std_logic := 'X'; -- chipselect read_n : in std_logic := 'X'; -- read_n write_n : in std_logic := 'X'; -- write_n writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata readdata : out std_logic_vector(15 downto 0); -- readdata dataavailable : out std_logic; -- dataavailable readyfordata : out std_logic; -- readyfordata rxd : in std_logic := 'X'; -- export txd : out std_logic; -- export irq : out std_logic -- irq ); end component wasca_uart_0; component wasca_mm_interconnect_0 is port ( altpll_0_c0_clk : in std_logic := 'X'; -- clk clk_0_clk_clk : in std_logic := 'X'; -- clk altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset nios2_gen2_0_data_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess nios2_gen2_0_instruction_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata sega_saturn_abus_slave_0_avalon_master_address : in std_logic_vector(27 downto 0) := (others => 'X'); -- address sega_saturn_abus_slave_0_avalon_master_waitrequest : out std_logic; -- waitrequest sega_saturn_abus_slave_0_avalon_master_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount sega_saturn_abus_slave_0_avalon_master_read : in std_logic := 'X'; -- read sega_saturn_abus_slave_0_avalon_master_readdata : out std_logic_vector(15 downto 0); -- readdata sega_saturn_abus_slave_0_avalon_master_readdatavalid : out std_logic; -- readdatavalid sega_saturn_abus_slave_0_avalon_master_write : in std_logic := 'X'; -- write sega_saturn_abus_slave_0_avalon_master_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata altpll_0_pll_slave_address : out std_logic_vector(1 downto 0); -- address altpll_0_pll_slave_write : out std_logic; -- write altpll_0_pll_slave_read : out std_logic; -- read altpll_0_pll_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata altpll_0_pll_slave_writedata : out std_logic_vector(31 downto 0); -- writedata audio_0_avalon_audio_slave_address : out std_logic_vector(1 downto 0); -- address audio_0_avalon_audio_slave_write : out std_logic; -- write audio_0_avalon_audio_slave_read : out std_logic; -- read audio_0_avalon_audio_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata audio_0_avalon_audio_slave_writedata : out std_logic_vector(31 downto 0); -- writedata audio_0_avalon_audio_slave_chipselect : out std_logic; -- chipselect external_sdram_controller_s1_address : out std_logic_vector(23 downto 0); -- address external_sdram_controller_s1_write : out std_logic; -- write external_sdram_controller_s1_read : out std_logic; -- read external_sdram_controller_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata external_sdram_controller_s1_writedata : out std_logic_vector(15 downto 0); -- writedata external_sdram_controller_s1_byteenable : out std_logic_vector(1 downto 0); -- byteenable external_sdram_controller_s1_readdatavalid : in std_logic := 'X'; -- readdatavalid external_sdram_controller_s1_waitrequest : in std_logic := 'X'; -- waitrequest external_sdram_controller_s1_chipselect : out std_logic; -- chipselect nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess onchip_flash_0_data_address : out std_logic_vector(15 downto 0); -- address onchip_flash_0_data_read : out std_logic; -- read onchip_flash_0_data_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata onchip_flash_0_data_burstcount : out std_logic_vector(3 downto 0); -- burstcount onchip_flash_0_data_readdatavalid : in std_logic := 'X'; -- readdatavalid onchip_flash_0_data_waitrequest : in std_logic := 'X'; -- waitrequest onchip_memory2_0_s1_address : out std_logic_vector(11 downto 0); -- address onchip_memory2_0_s1_write : out std_logic; -- write onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect onchip_memory2_0_s1_clken : out std_logic; -- clken sega_saturn_abus_slave_0_avalon_nios_address : out std_logic_vector(7 downto 0); -- address sega_saturn_abus_slave_0_avalon_nios_write : out std_logic; -- write sega_saturn_abus_slave_0_avalon_nios_read : out std_logic; -- read sega_saturn_abus_slave_0_avalon_nios_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata sega_saturn_abus_slave_0_avalon_nios_writedata : out std_logic_vector(15 downto 0); -- writedata sega_saturn_abus_slave_0_avalon_nios_burstcount : out std_logic_vector(0 downto 0); -- burstcount sega_saturn_abus_slave_0_avalon_nios_readdatavalid : in std_logic := 'X'; -- readdatavalid sega_saturn_abus_slave_0_avalon_nios_waitrequest : in std_logic := 'X'; -- waitrequest spi_sd_card_spi_control_port_address : out std_logic_vector(2 downto 0); -- address spi_sd_card_spi_control_port_write : out std_logic; -- write spi_sd_card_spi_control_port_read : out std_logic; -- read spi_sd_card_spi_control_port_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata spi_sd_card_spi_control_port_writedata : out std_logic_vector(15 downto 0); -- writedata spi_sd_card_spi_control_port_chipselect : out std_logic; -- chipselect spi_stm32_spi_control_port_address : out std_logic_vector(2 downto 0); -- address spi_stm32_spi_control_port_write : out std_logic; -- write spi_stm32_spi_control_port_read : out std_logic; -- read spi_stm32_spi_control_port_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata spi_stm32_spi_control_port_writedata : out std_logic_vector(15 downto 0); -- writedata spi_stm32_spi_control_port_chipselect : out std_logic; -- chipselect uart_0_s1_address : out std_logic_vector(2 downto 0); -- address uart_0_s1_write : out std_logic; -- write uart_0_s1_read : out std_logic; -- read uart_0_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata uart_0_s1_writedata : out std_logic_vector(15 downto 0); -- writedata uart_0_s1_begintransfer : out std_logic; -- begintransfer uart_0_s1_chipselect : out std_logic -- chipselect ); end component wasca_mm_interconnect_0; component wasca_irq_mapper is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset receiver0_irq : in std_logic := 'X'; -- irq receiver1_irq : in std_logic := 'X'; -- irq receiver2_irq : in std_logic := 'X'; -- irq receiver3_irq : in std_logic := 'X'; -- irq sender_irq : out std_logic_vector(31 downto 0) -- irq ); end component wasca_irq_mapper; component wasca_rst_controller is generic ( NUM_RESET_INPUTS : integer := 6; OUTPUT_RESET_SYNC_EDGES : string := "deassert"; SYNC_DEPTH : integer := 2; RESET_REQUEST_PRESENT : integer := 0; RESET_REQ_WAIT_TIME : integer := 1; MIN_RST_ASSERTION_TIME : integer := 3; RESET_REQ_EARLY_DSRT_TIME : integer := 1; USE_RESET_REQUEST_IN0 : integer := 0; USE_RESET_REQUEST_IN1 : integer := 0; USE_RESET_REQUEST_IN2 : integer := 0; USE_RESET_REQUEST_IN3 : integer := 0; USE_RESET_REQUEST_IN4 : integer := 0; USE_RESET_REQUEST_IN5 : integer := 0; USE_RESET_REQUEST_IN6 : integer := 0; USE_RESET_REQUEST_IN7 : integer := 0; USE_RESET_REQUEST_IN8 : integer := 0; USE_RESET_REQUEST_IN9 : integer := 0; USE_RESET_REQUEST_IN10 : integer := 0; USE_RESET_REQUEST_IN11 : integer := 0; USE_RESET_REQUEST_IN12 : integer := 0; USE_RESET_REQUEST_IN13 : integer := 0; USE_RESET_REQUEST_IN14 : integer := 0; USE_RESET_REQUEST_IN15 : integer := 0; ADAPT_RESET_REQUEST : integer := 0 ); port ( reset_in0 : in std_logic := 'X'; -- reset clk : in std_logic := 'X'; -- clk reset_out : out std_logic; -- reset reset_req : out std_logic; -- reset_req reset_req_in0 : in std_logic := 'X'; -- reset_req reset_in1 : in std_logic := 'X'; -- reset reset_req_in1 : in std_logic := 'X'; -- reset_req reset_in2 : in std_logic := 'X'; -- reset reset_req_in2 : in std_logic := 'X'; -- reset_req reset_in3 : in std_logic := 'X'; -- reset reset_req_in3 : in std_logic := 'X'; -- reset_req reset_in4 : in std_logic := 'X'; -- reset reset_req_in4 : in std_logic := 'X'; -- reset_req reset_in5 : in std_logic := 'X'; -- reset reset_req_in5 : in std_logic := 'X'; -- reset_req reset_in6 : in std_logic := 'X'; -- reset reset_req_in6 : in std_logic := 'X'; -- reset_req reset_in7 : in std_logic := 'X'; -- reset reset_req_in7 : in std_logic := 'X'; -- reset_req reset_in8 : in std_logic := 'X'; -- reset reset_req_in8 : in std_logic := 'X'; -- reset_req reset_in9 : in std_logic := 'X'; -- reset reset_req_in9 : in std_logic := 'X'; -- reset_req reset_in10 : in std_logic := 'X'; -- reset reset_req_in10 : in std_logic := 'X'; -- reset_req reset_in11 : in std_logic := 'X'; -- reset reset_req_in11 : in std_logic := 'X'; -- reset_req reset_in12 : in std_logic := 'X'; -- reset reset_req_in12 : in std_logic := 'X'; -- reset_req reset_in13 : in std_logic := 'X'; -- reset reset_req_in13 : in std_logic := 'X'; -- reset_req reset_in14 : in std_logic := 'X'; -- reset reset_req_in14 : in std_logic := 'X'; -- reset_req reset_in15 : in std_logic := 'X'; -- reset reset_req_in15 : in std_logic := 'X' -- reset_req ); end component wasca_rst_controller; component wasca_rst_controller_001 is generic ( NUM_RESET_INPUTS : integer := 6; OUTPUT_RESET_SYNC_EDGES : string := "deassert"; SYNC_DEPTH : integer := 2; RESET_REQUEST_PRESENT : integer := 0; RESET_REQ_WAIT_TIME : integer := 1; MIN_RST_ASSERTION_TIME : integer := 3; RESET_REQ_EARLY_DSRT_TIME : integer := 1; USE_RESET_REQUEST_IN0 : integer := 0; USE_RESET_REQUEST_IN1 : integer := 0; USE_RESET_REQUEST_IN2 : integer := 0; USE_RESET_REQUEST_IN3 : integer := 0; USE_RESET_REQUEST_IN4 : integer := 0; USE_RESET_REQUEST_IN5 : integer := 0; USE_RESET_REQUEST_IN6 : integer := 0; USE_RESET_REQUEST_IN7 : integer := 0; USE_RESET_REQUEST_IN8 : integer := 0; USE_RESET_REQUEST_IN9 : integer := 0; USE_RESET_REQUEST_IN10 : integer := 0; USE_RESET_REQUEST_IN11 : integer := 0; USE_RESET_REQUEST_IN12 : integer := 0; USE_RESET_REQUEST_IN13 : integer := 0; USE_RESET_REQUEST_IN14 : integer := 0; USE_RESET_REQUEST_IN15 : integer := 0; ADAPT_RESET_REQUEST : integer := 0 ); port ( reset_in0 : in std_logic := 'X'; -- reset clk : in std_logic := 'X'; -- clk reset_out : out std_logic; -- reset reset_req : out std_logic; -- reset_req reset_req_in0 : in std_logic := 'X'; -- reset_req reset_in1 : in std_logic := 'X'; -- reset reset_req_in1 : in std_logic := 'X'; -- reset_req reset_in2 : in std_logic := 'X'; -- reset reset_req_in2 : in std_logic := 'X'; -- reset_req reset_in3 : in std_logic := 'X'; -- reset reset_req_in3 : in std_logic := 'X'; -- reset_req reset_in4 : in std_logic := 'X'; -- reset reset_req_in4 : in std_logic := 'X'; -- reset_req reset_in5 : in std_logic := 'X'; -- reset reset_req_in5 : in std_logic := 'X'; -- reset_req reset_in6 : in std_logic := 'X'; -- reset reset_req_in6 : in std_logic := 'X'; -- reset_req reset_in7 : in std_logic := 'X'; -- reset reset_req_in7 : in std_logic := 'X'; -- reset_req reset_in8 : in std_logic := 'X'; -- reset reset_req_in8 : in std_logic := 'X'; -- reset_req reset_in9 : in std_logic := 'X'; -- reset reset_req_in9 : in std_logic := 'X'; -- reset_req reset_in10 : in std_logic := 'X'; -- reset reset_req_in10 : in std_logic := 'X'; -- reset_req reset_in11 : in std_logic := 'X'; -- reset reset_req_in11 : in std_logic := 'X'; -- reset_req reset_in12 : in std_logic := 'X'; -- reset reset_req_in12 : in std_logic := 'X'; -- reset_req reset_in13 : in std_logic := 'X'; -- reset reset_req_in13 : in std_logic := 'X'; -- reset_req reset_in14 : in std_logic := 'X'; -- reset reset_req_in14 : in std_logic := 'X'; -- reset_req reset_in15 : in std_logic := 'X'; -- reset reset_req_in15 : in std_logic := 'X' -- reset_req ); end component wasca_rst_controller_001; signal altpll_0_c0_clk : std_logic; -- altpll_0:c0 -> [clock_116_mhz_clk, audio_0:clk, external_sdram_controller:clk, irq_mapper:clk, mm_interconnect_0:altpll_0_c0_clk, nios2_gen2_0:clk, onchip_flash_0:clock, onchip_memory2_0:clk, rst_controller_001:clk, rst_controller_002:clk, sega_saturn_abus_slave_0:clock, spi_sd_card:clk, spi_stm32:clk, uart_0:clk] signal nios2_gen2_0_debug_reset_request_reset : std_logic; -- nios2_gen2_0:debug_reset_request -> [rst_controller:reset_in0, rst_controller_001:reset_in0, rst_controller_002:reset_in0] signal sega_saturn_abus_slave_0_avalon_master_waitrequest : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_waitrequest -> sega_saturn_abus_slave_0:avalon_waitrequest signal sega_saturn_abus_slave_0_avalon_master_readdata : std_logic_vector(15 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_readdata -> sega_saturn_abus_slave_0:avalon_readdata signal sega_saturn_abus_slave_0_avalon_master_read : std_logic; -- sega_saturn_abus_slave_0:avalon_read -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_read signal sega_saturn_abus_slave_0_avalon_master_address : std_logic_vector(27 downto 0); -- sega_saturn_abus_slave_0:avalon_address -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_address signal sega_saturn_abus_slave_0_avalon_master_readdatavalid : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_readdatavalid -> sega_saturn_abus_slave_0:avalon_readdatavalid signal sega_saturn_abus_slave_0_avalon_master_write : std_logic; -- sega_saturn_abus_slave_0:avalon_write -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_write signal sega_saturn_abus_slave_0_avalon_master_writedata : std_logic_vector(15 downto 0); -- sega_saturn_abus_slave_0:avalon_writedata -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_writedata signal sega_saturn_abus_slave_0_avalon_master_burstcount : std_logic; -- sega_saturn_abus_slave_0:avalon_burstcount -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_burstcount signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess signal nios2_gen2_0_data_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest signal nios2_gen2_0_instruction_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read signal mm_interconnect_0_external_sdram_controller_s1_chipselect : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_chipselect -> external_sdram_controller:az_cs signal mm_interconnect_0_external_sdram_controller_s1_readdata : std_logic_vector(15 downto 0); -- external_sdram_controller:za_data -> mm_interconnect_0:external_sdram_controller_s1_readdata signal mm_interconnect_0_external_sdram_controller_s1_waitrequest : std_logic; -- external_sdram_controller:za_waitrequest -> mm_interconnect_0:external_sdram_controller_s1_waitrequest signal mm_interconnect_0_external_sdram_controller_s1_address : std_logic_vector(23 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_address -> external_sdram_controller:az_addr signal mm_interconnect_0_external_sdram_controller_s1_read : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_read -> mm_interconnect_0_external_sdram_controller_s1_read:in signal mm_interconnect_0_external_sdram_controller_s1_byteenable : std_logic_vector(1 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_byteenable -> mm_interconnect_0_external_sdram_controller_s1_byteenable:in signal mm_interconnect_0_external_sdram_controller_s1_readdatavalid : std_logic; -- external_sdram_controller:za_valid -> mm_interconnect_0:external_sdram_controller_s1_readdatavalid signal mm_interconnect_0_external_sdram_controller_s1_write : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_write -> mm_interconnect_0_external_sdram_controller_s1_write:in signal mm_interconnect_0_external_sdram_controller_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_writedata -> external_sdram_controller:az_data signal mm_interconnect_0_onchip_flash_0_data_readdata : std_logic_vector(31 downto 0); -- onchip_flash_0:avmm_data_readdata -> mm_interconnect_0:onchip_flash_0_data_readdata signal mm_interconnect_0_onchip_flash_0_data_waitrequest : std_logic; -- onchip_flash_0:avmm_data_waitrequest -> mm_interconnect_0:onchip_flash_0_data_waitrequest signal mm_interconnect_0_onchip_flash_0_data_address : std_logic_vector(15 downto 0); -- mm_interconnect_0:onchip_flash_0_data_address -> onchip_flash_0:avmm_data_addr signal mm_interconnect_0_onchip_flash_0_data_read : std_logic; -- mm_interconnect_0:onchip_flash_0_data_read -> onchip_flash_0:avmm_data_read signal mm_interconnect_0_onchip_flash_0_data_readdatavalid : std_logic; -- onchip_flash_0:avmm_data_readdatavalid -> mm_interconnect_0:onchip_flash_0_data_readdatavalid signal mm_interconnect_0_onchip_flash_0_data_burstcount : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_flash_0_data_burstcount -> onchip_flash_0:avmm_data_burstcount signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(11 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken signal mm_interconnect_0_audio_0_avalon_audio_slave_chipselect : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_chipselect -> audio_0:chipselect signal mm_interconnect_0_audio_0_avalon_audio_slave_readdata : std_logic_vector(31 downto 0); -- audio_0:readdata -> mm_interconnect_0:audio_0_avalon_audio_slave_readdata signal mm_interconnect_0_audio_0_avalon_audio_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:audio_0_avalon_audio_slave_address -> audio_0:address signal mm_interconnect_0_audio_0_avalon_audio_slave_read : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_read -> audio_0:read signal mm_interconnect_0_audio_0_avalon_audio_slave_write : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_write -> audio_0:write signal mm_interconnect_0_audio_0_avalon_audio_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:audio_0_avalon_audio_slave_writedata -> audio_0:writedata signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata : std_logic_vector(15 downto 0); -- sega_saturn_abus_slave_0:avalon_nios_readdata -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_readdata signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest : std_logic; -- sega_saturn_abus_slave_0:avalon_nios_waitrequest -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_waitrequest signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_address -> sega_saturn_abus_slave_0:avalon_nios_address signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_read -> sega_saturn_abus_slave_0:avalon_nios_read signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid : std_logic; -- sega_saturn_abus_slave_0:avalon_nios_readdatavalid -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_readdatavalid signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_write -> sega_saturn_abus_slave_0:avalon_nios_write signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_writedata -> sega_saturn_abus_slave_0:avalon_nios_writedata signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount : std_logic_vector(0 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_burstcount -> sega_saturn_abus_slave_0:avalon_nios_burstcount signal mm_interconnect_0_altpll_0_pll_slave_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> mm_interconnect_0:altpll_0_pll_slave_readdata signal mm_interconnect_0_altpll_0_pll_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_address -> altpll_0:address signal mm_interconnect_0_altpll_0_pll_slave_read : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_read -> altpll_0:read signal mm_interconnect_0_altpll_0_pll_slave_write : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_write -> altpll_0:write signal mm_interconnect_0_altpll_0_pll_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_writedata -> altpll_0:writedata signal mm_interconnect_0_uart_0_s1_chipselect : std_logic; -- mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect signal mm_interconnect_0_uart_0_s1_readdata : std_logic_vector(15 downto 0); -- uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata signal mm_interconnect_0_uart_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:uart_0_s1_address -> uart_0:address signal mm_interconnect_0_uart_0_s1_read : std_logic; -- mm_interconnect_0:uart_0_s1_read -> mm_interconnect_0_uart_0_s1_read:in signal mm_interconnect_0_uart_0_s1_begintransfer : std_logic; -- mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer signal mm_interconnect_0_uart_0_s1_write : std_logic; -- mm_interconnect_0:uart_0_s1_write -> mm_interconnect_0_uart_0_s1_write:in signal mm_interconnect_0_uart_0_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata signal mm_interconnect_0_spi_sd_card_spi_control_port_chipselect : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_chipselect -> spi_sd_card:spi_select signal mm_interconnect_0_spi_sd_card_spi_control_port_readdata : std_logic_vector(15 downto 0); -- spi_sd_card:data_to_cpu -> mm_interconnect_0:spi_sd_card_spi_control_port_readdata signal mm_interconnect_0_spi_sd_card_spi_control_port_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:spi_sd_card_spi_control_port_address -> spi_sd_card:mem_addr signal mm_interconnect_0_spi_sd_card_spi_control_port_read : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_read -> mm_interconnect_0_spi_sd_card_spi_control_port_read:in signal mm_interconnect_0_spi_sd_card_spi_control_port_write : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_write -> mm_interconnect_0_spi_sd_card_spi_control_port_write:in signal mm_interconnect_0_spi_sd_card_spi_control_port_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:spi_sd_card_spi_control_port_writedata -> spi_sd_card:data_from_cpu signal mm_interconnect_0_spi_stm32_spi_control_port_chipselect : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_chipselect -> spi_stm32:spi_select signal mm_interconnect_0_spi_stm32_spi_control_port_readdata : std_logic_vector(15 downto 0); -- spi_stm32:data_to_cpu -> mm_interconnect_0:spi_stm32_spi_control_port_readdata signal mm_interconnect_0_spi_stm32_spi_control_port_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:spi_stm32_spi_control_port_address -> spi_stm32:mem_addr signal mm_interconnect_0_spi_stm32_spi_control_port_read : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_read -> mm_interconnect_0_spi_stm32_spi_control_port_read:in signal mm_interconnect_0_spi_stm32_spi_control_port_write : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_write -> mm_interconnect_0_spi_stm32_spi_control_port_write:in signal mm_interconnect_0_spi_stm32_spi_control_port_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:spi_stm32_spi_control_port_writedata -> spi_stm32:data_from_cpu signal irq_mapper_receiver0_irq : std_logic; -- audio_0:irq -> irq_mapper:receiver0_irq signal irq_mapper_receiver1_irq : std_logic; -- uart_0:irq -> irq_mapper:receiver1_irq signal irq_mapper_receiver2_irq : std_logic; -- spi_sd_card:irq -> irq_mapper:receiver2_irq signal irq_mapper_receiver3_irq : std_logic; -- spi_stm32:irq -> irq_mapper:receiver3_irq signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [altpll_0:reset, mm_interconnect_0:altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset] signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [audio_0:reset, irq_mapper:reset, mm_interconnect_0:sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_001_reset_out_reset:in, rst_translator:in_reset, sega_saturn_abus_slave_0:reset] signal rst_controller_001_reset_out_reset_req : std_logic; -- rst_controller_001:reset_req -> [onchip_memory2_0:reset_req, rst_translator:reset_req_in] signal mm_interconnect_0_external_sdram_controller_s1_read_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_read:inv -> external_sdram_controller:az_rd_n signal mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv : std_logic_vector(1 downto 0); -- mm_interconnect_0_external_sdram_controller_s1_byteenable:inv -> external_sdram_controller:az_be_n signal mm_interconnect_0_external_sdram_controller_s1_write_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_write:inv -> external_sdram_controller:az_wr_n signal mm_interconnect_0_uart_0_s1_read_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_read:inv -> uart_0:read_n signal mm_interconnect_0_uart_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_write:inv -> uart_0:write_n signal mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv : std_logic; -- mm_interconnect_0_spi_sd_card_spi_control_port_read:inv -> spi_sd_card:read_n signal mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv : std_logic; -- mm_interconnect_0_spi_sd_card_spi_control_port_write:inv -> spi_sd_card:write_n signal mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv : std_logic; -- mm_interconnect_0_spi_stm32_spi_control_port_read:inv -> spi_stm32:read_n signal mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv : std_logic; -- mm_interconnect_0_spi_stm32_spi_control_port_write:inv -> spi_stm32:write_n signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> [external_sdram_controller:reset_n, nios2_gen2_0:reset_n, onchip_flash_0:reset_n, spi_sd_card:reset_n, spi_stm32:reset_n, uart_0:reset_n] begin altpll_0 : component wasca_altpll_0 port map ( clk => clk_clk, -- inclk_interface.clk reset => rst_controller_reset_out_reset, -- inclk_interface_reset.reset read => mm_interconnect_0_altpll_0_pll_slave_read, -- pll_slave.read write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write address => mm_interconnect_0_altpll_0_pll_slave_address, -- .address readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata c0 => altpll_0_c0_clk, -- c0.clk areset => altpll_0_areset_conduit_export, -- areset_conduit.export c1 => open, -- c1_conduit.export locked => altpll_0_locked_conduit_export, -- locked_conduit.export phasedone => altpll_0_phasedone_conduit_export -- phasedone_conduit.export ); audio_0 : component wasca_audio_0 port map ( clk => altpll_0_c0_clk, -- clk.clk reset => rst_controller_001_reset_out_reset, -- reset.reset address => mm_interconnect_0_audio_0_avalon_audio_slave_address, -- avalon_audio_slave.address chipselect => mm_interconnect_0_audio_0_avalon_audio_slave_chipselect, -- .chipselect read => mm_interconnect_0_audio_0_avalon_audio_slave_read, -- .read write => mm_interconnect_0_audio_0_avalon_audio_slave_write, -- .write writedata => mm_interconnect_0_audio_0_avalon_audio_slave_writedata, -- .writedata readdata => mm_interconnect_0_audio_0_avalon_audio_slave_readdata, -- .readdata irq => irq_mapper_receiver0_irq, -- interrupt.irq AUD_BCLK => audio_out_BCLK, -- external_interface.export AUD_DACDAT => audio_out_DACDAT, -- .export AUD_DACLRCK => audio_out_DACLRCK -- .export ); external_sdram_controller : component wasca_external_sdram_controller port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n az_addr => mm_interconnect_0_external_sdram_controller_s1_address, -- s1.address az_be_n => mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv, -- .byteenable_n az_cs => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect az_data => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata az_rd_n => mm_interconnect_0_external_sdram_controller_s1_read_ports_inv, -- .read_n az_wr_n => mm_interconnect_0_external_sdram_controller_s1_write_ports_inv, -- .write_n za_data => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata za_valid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid za_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest zs_addr => external_sdram_controller_wire_addr, -- wire.export zs_ba => external_sdram_controller_wire_ba, -- .export zs_cas_n => external_sdram_controller_wire_cas_n, -- .export zs_cke => external_sdram_controller_wire_cke, -- .export zs_cs_n => external_sdram_controller_wire_cs_n, -- .export zs_dq => external_sdram_controller_wire_dq, -- .export zs_dqm => external_sdram_controller_wire_dqm, -- .export zs_ras_n => external_sdram_controller_wire_ras_n, -- .export zs_we_n => external_sdram_controller_wire_we_n -- .export ); nios2_gen2_0 : component wasca_nios2_gen2_0 port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n d_address => nios2_gen2_0_data_master_address, -- data_master.address d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable d_read => nios2_gen2_0_data_master_read, -- .read d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest d_write => nios2_gen2_0_data_master_write, -- .write d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address i_read => nios2_gen2_0_instruction_master_read, -- .read i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest irq => nios2_gen2_0_irq_irq, -- irq.irq debug_reset_request => nios2_gen2_0_debug_reset_request_reset, -- debug_reset_request.reset debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata dummy_ci_port => open -- custom_instruction_master.readra ); onchip_flash_0 : component altera_onchip_flash generic map ( INIT_FILENAME => "", INIT_FILENAME_SIM => "", DEVICE_FAMILY => "MAX 10", PART_NAME => "10M08SAE144C8GES", DEVICE_ID => "08", SECTOR1_START_ADDR => 0, SECTOR1_END_ADDR => 4095, SECTOR2_START_ADDR => 4096, SECTOR2_END_ADDR => 8191, SECTOR3_START_ADDR => 8192, SECTOR3_END_ADDR => 29183, SECTOR4_START_ADDR => 29184, SECTOR4_END_ADDR => 44031, SECTOR5_START_ADDR => 0, SECTOR5_END_ADDR => 0, MIN_VALID_ADDR => 0, MAX_VALID_ADDR => 44031, MIN_UFM_VALID_ADDR => 0, MAX_UFM_VALID_ADDR => 44031, SECTOR1_MAP => 1, SECTOR2_MAP => 2, SECTOR3_MAP => 3, SECTOR4_MAP => 4, SECTOR5_MAP => 0, ADDR_RANGE1_END_ADDR => 44031, ADDR_RANGE1_OFFSET => 512, ADDR_RANGE2_OFFSET => 0, AVMM_DATA_ADDR_WIDTH => 16, AVMM_DATA_DATA_WIDTH => 32, AVMM_DATA_BURSTCOUNT_WIDTH => 4, SECTOR_READ_PROTECTION_MODE => 31, FLASH_SEQ_READ_DATA_COUNT => 2, FLASH_ADDR_ALIGNMENT_BITS => 1, FLASH_READ_CYCLE_MAX_INDEX => 3, FLASH_RESET_CYCLE_MAX_INDEX => 29, FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX => 111, FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX => 40603248, FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX => 35382, PARALLEL_MODE => true, READ_AND_WRITE_MODE => false, WRAPPING_BURST_MODE => false, IS_DUAL_BOOT => "False", IS_ERAM_SKIP => "True", IS_COMPRESSED_IMAGE => "True" ) port map ( clock => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- nreset.reset_n avmm_data_addr => mm_interconnect_0_onchip_flash_0_data_address, -- data.address avmm_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read avmm_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata avmm_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest avmm_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid avmm_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount avmm_data_writedata => "00000000000000000000000000000000", -- (terminated) avmm_data_write => '0', -- (terminated) avmm_csr_addr => '0', -- (terminated) avmm_csr_read => '0', -- (terminated) avmm_csr_writedata => "00000000000000000000000000000000", -- (terminated) avmm_csr_write => '0', -- (terminated) avmm_csr_readdata => open -- (terminated) ); onchip_memory2_0 : component wasca_onchip_memory2_0 port map ( clk => altpll_0_c0_clk, -- clk1.clk address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable reset => rst_controller_001_reset_out_reset, -- reset1.reset reset_req => rst_controller_001_reset_out_reset_req -- .reset_req ); sega_saturn_abus_slave_0 : component sega_saturn_abus_slave port map ( clock => altpll_0_c0_clk, -- clock.clk abus_address => sega_saturn_abus_slave_0_abus_address, -- abus.address abus_chipselect => sega_saturn_abus_slave_0_abus_chipselect, -- .chipselect abus_read => sega_saturn_abus_slave_0_abus_read, -- .read abus_write => sega_saturn_abus_slave_0_abus_write, -- .write abus_waitrequest => sega_saturn_abus_slave_0_abus_waitrequest, -- .waitrequest abus_interrupt => sega_saturn_abus_slave_0_abus_interrupt, -- .interrupt abus_addressdata => sega_saturn_abus_slave_0_abus_addressdata, -- .addressdata abus_direction => sega_saturn_abus_slave_0_abus_direction, -- .direction abus_muxing => sega_saturn_abus_slave_0_abus_muxing, -- .muxing abus_disable_out => sega_saturn_abus_slave_0_abus_disableout, -- .disableout avalon_read => sega_saturn_abus_slave_0_avalon_master_read, -- avalon_master.read avalon_write => sega_saturn_abus_slave_0_avalon_master_write, -- .write avalon_waitrequest => sega_saturn_abus_slave_0_avalon_master_waitrequest, -- .waitrequest avalon_address => sega_saturn_abus_slave_0_avalon_master_address, -- .address avalon_readdata => sega_saturn_abus_slave_0_avalon_master_readdata, -- .readdata avalon_writedata => sega_saturn_abus_slave_0_avalon_master_writedata, -- .writedata avalon_readdatavalid => sega_saturn_abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid avalon_burstcount => sega_saturn_abus_slave_0_avalon_master_burstcount, -- .burstcount reset => rst_controller_001_reset_out_reset, -- reset.reset saturn_reset => sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset, -- conduit_saturn_reset.saturn_reset avalon_nios_read => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read, -- avalon_nios.read avalon_nios_write => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write, -- .write avalon_nios_address => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address, -- .address avalon_nios_writedata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata, -- .writedata avalon_nios_readdata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata, -- .readdata avalon_nios_waitrequest => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest avalon_nios_readdatavalid => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid avalon_nios_burstcount => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount(0) -- .burstcount ); spi_sd_card : component wasca_spi_sd_card port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n data_from_cpu => mm_interconnect_0_spi_sd_card_spi_control_port_writedata, -- spi_control_port.writedata data_to_cpu => mm_interconnect_0_spi_sd_card_spi_control_port_readdata, -- .readdata mem_addr => mm_interconnect_0_spi_sd_card_spi_control_port_address, -- .address read_n => mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv, -- .read_n spi_select => mm_interconnect_0_spi_sd_card_spi_control_port_chipselect, -- .chipselect write_n => mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv, -- .write_n irq => irq_mapper_receiver2_irq, -- irq.irq MISO => spi_sd_card_MISO, -- external.export MOSI => spi_sd_card_MOSI, -- .export SCLK => spi_sd_card_SCLK, -- .export SS_n => spi_sd_card_SS_n -- .export ); spi_stm32 : component wasca_spi_stm32 port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n data_from_cpu => mm_interconnect_0_spi_stm32_spi_control_port_writedata, -- spi_control_port.writedata data_to_cpu => mm_interconnect_0_spi_stm32_spi_control_port_readdata, -- .readdata mem_addr => mm_interconnect_0_spi_stm32_spi_control_port_address, -- .address read_n => mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv, -- .read_n spi_select => mm_interconnect_0_spi_stm32_spi_control_port_chipselect, -- .chipselect write_n => mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv, -- .write_n irq => irq_mapper_receiver3_irq, -- irq.irq MISO => spi_stm32_MISO, -- external.export MOSI => spi_stm32_MOSI, -- .export SCLK => spi_stm32_SCLK, -- .export SS_n => spi_stm32_SS_n -- .export ); uart_0 : component wasca_uart_0 port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n address => mm_interconnect_0_uart_0_s1_address, -- s1.address begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer chipselect => mm_interconnect_0_uart_0_s1_chipselect, -- .chipselect read_n => mm_interconnect_0_uart_0_s1_read_ports_inv, -- .read_n write_n => mm_interconnect_0_uart_0_s1_write_ports_inv, -- .write_n writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata dataavailable => open, -- .dataavailable readyfordata => open, -- .readyfordata rxd => uart_0_external_connection_rxd, -- external_connection.export txd => uart_0_external_connection_txd, -- .export irq => irq_mapper_receiver1_irq -- irq.irq ); mm_interconnect_0 : component wasca_mm_interconnect_0 port map ( altpll_0_c0_clk => altpll_0_c0_clk, -- altpll_0_c0.clk clk_0_clk_clk => clk_clk, -- clk_0_clk.clk altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- sega_saturn_abus_slave_0_reset_reset_bridge_in_reset.reset nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata sega_saturn_abus_slave_0_avalon_master_address => sega_saturn_abus_slave_0_avalon_master_address, -- sega_saturn_abus_slave_0_avalon_master.address sega_saturn_abus_slave_0_avalon_master_waitrequest => sega_saturn_abus_slave_0_avalon_master_waitrequest, -- .waitrequest sega_saturn_abus_slave_0_avalon_master_burstcount(0) => sega_saturn_abus_slave_0_avalon_master_burstcount, -- .burstcount sega_saturn_abus_slave_0_avalon_master_read => sega_saturn_abus_slave_0_avalon_master_read, -- .read sega_saturn_abus_slave_0_avalon_master_readdata => sega_saturn_abus_slave_0_avalon_master_readdata, -- .readdata sega_saturn_abus_slave_0_avalon_master_readdatavalid => sega_saturn_abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid sega_saturn_abus_slave_0_avalon_master_write => sega_saturn_abus_slave_0_avalon_master_write, -- .write sega_saturn_abus_slave_0_avalon_master_writedata => sega_saturn_abus_slave_0_avalon_master_writedata, -- .writedata altpll_0_pll_slave_address => mm_interconnect_0_altpll_0_pll_slave_address, -- altpll_0_pll_slave.address altpll_0_pll_slave_write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write altpll_0_pll_slave_read => mm_interconnect_0_altpll_0_pll_slave_read, -- .read altpll_0_pll_slave_readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata altpll_0_pll_slave_writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata audio_0_avalon_audio_slave_address => mm_interconnect_0_audio_0_avalon_audio_slave_address, -- audio_0_avalon_audio_slave.address audio_0_avalon_audio_slave_write => mm_interconnect_0_audio_0_avalon_audio_slave_write, -- .write audio_0_avalon_audio_slave_read => mm_interconnect_0_audio_0_avalon_audio_slave_read, -- .read audio_0_avalon_audio_slave_readdata => mm_interconnect_0_audio_0_avalon_audio_slave_readdata, -- .readdata audio_0_avalon_audio_slave_writedata => mm_interconnect_0_audio_0_avalon_audio_slave_writedata, -- .writedata audio_0_avalon_audio_slave_chipselect => mm_interconnect_0_audio_0_avalon_audio_slave_chipselect, -- .chipselect external_sdram_controller_s1_address => mm_interconnect_0_external_sdram_controller_s1_address, -- external_sdram_controller_s1.address external_sdram_controller_s1_write => mm_interconnect_0_external_sdram_controller_s1_write, -- .write external_sdram_controller_s1_read => mm_interconnect_0_external_sdram_controller_s1_read, -- .read external_sdram_controller_s1_readdata => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata external_sdram_controller_s1_writedata => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata external_sdram_controller_s1_byteenable => mm_interconnect_0_external_sdram_controller_s1_byteenable, -- .byteenable external_sdram_controller_s1_readdatavalid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid external_sdram_controller_s1_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest external_sdram_controller_s1_chipselect => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess onchip_flash_0_data_address => mm_interconnect_0_onchip_flash_0_data_address, -- onchip_flash_0_data.address onchip_flash_0_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read onchip_flash_0_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata onchip_flash_0_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount onchip_flash_0_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid onchip_flash_0_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken sega_saturn_abus_slave_0_avalon_nios_address => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address, -- sega_saturn_abus_slave_0_avalon_nios.address sega_saturn_abus_slave_0_avalon_nios_write => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write, -- .write sega_saturn_abus_slave_0_avalon_nios_read => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read, -- .read sega_saturn_abus_slave_0_avalon_nios_readdata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata, -- .readdata sega_saturn_abus_slave_0_avalon_nios_writedata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata, -- .writedata sega_saturn_abus_slave_0_avalon_nios_burstcount => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount, -- .burstcount sega_saturn_abus_slave_0_avalon_nios_readdatavalid => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid sega_saturn_abus_slave_0_avalon_nios_waitrequest => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest spi_sd_card_spi_control_port_address => mm_interconnect_0_spi_sd_card_spi_control_port_address, -- spi_sd_card_spi_control_port.address spi_sd_card_spi_control_port_write => mm_interconnect_0_spi_sd_card_spi_control_port_write, -- .write spi_sd_card_spi_control_port_read => mm_interconnect_0_spi_sd_card_spi_control_port_read, -- .read spi_sd_card_spi_control_port_readdata => mm_interconnect_0_spi_sd_card_spi_control_port_readdata, -- .readdata spi_sd_card_spi_control_port_writedata => mm_interconnect_0_spi_sd_card_spi_control_port_writedata, -- .writedata spi_sd_card_spi_control_port_chipselect => mm_interconnect_0_spi_sd_card_spi_control_port_chipselect, -- .chipselect spi_stm32_spi_control_port_address => mm_interconnect_0_spi_stm32_spi_control_port_address, -- spi_stm32_spi_control_port.address spi_stm32_spi_control_port_write => mm_interconnect_0_spi_stm32_spi_control_port_write, -- .write spi_stm32_spi_control_port_read => mm_interconnect_0_spi_stm32_spi_control_port_read, -- .read spi_stm32_spi_control_port_readdata => mm_interconnect_0_spi_stm32_spi_control_port_readdata, -- .readdata spi_stm32_spi_control_port_writedata => mm_interconnect_0_spi_stm32_spi_control_port_writedata, -- .writedata spi_stm32_spi_control_port_chipselect => mm_interconnect_0_spi_stm32_spi_control_port_chipselect, -- .chipselect uart_0_s1_address => mm_interconnect_0_uart_0_s1_address, -- uart_0_s1.address uart_0_s1_write => mm_interconnect_0_uart_0_s1_write, -- .write uart_0_s1_read => mm_interconnect_0_uart_0_s1_read, -- .read uart_0_s1_readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata uart_0_s1_writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata uart_0_s1_begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer uart_0_s1_chipselect => mm_interconnect_0_uart_0_s1_chipselect -- .chipselect ); irq_mapper : component wasca_irq_mapper port map ( clk => altpll_0_c0_clk, -- clk.clk reset => rst_controller_001_reset_out_reset, -- clk_reset.reset receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq receiver2_irq => irq_mapper_receiver2_irq, -- receiver2.irq receiver3_irq => irq_mapper_receiver3_irq, -- receiver3.irq sender_irq => nios2_gen2_0_irq_irq -- sender.irq ); rst_controller : component wasca_rst_controller generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "deassert", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 0, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset clk => clk_clk, -- clk.clk reset_out => rst_controller_reset_out_reset, -- reset_out.reset reset_req => open, -- (terminated) reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); rst_controller_001 : component wasca_rst_controller_001 generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "deassert", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 1, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset clk => altpll_0_c0_clk, -- clk.clk reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); rst_controller_002 : component wasca_rst_controller generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "both", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 0, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset clk => altpll_0_c0_clk, -- clk.clk reset_out => open, -- reset_out.reset reset_req => open, -- (terminated) reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); mm_interconnect_0_external_sdram_controller_s1_read_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_read; mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_byteenable; mm_interconnect_0_external_sdram_controller_s1_write_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_write; mm_interconnect_0_uart_0_s1_read_ports_inv <= not mm_interconnect_0_uart_0_s1_read; mm_interconnect_0_uart_0_s1_write_ports_inv <= not mm_interconnect_0_uart_0_s1_write; mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv <= not mm_interconnect_0_spi_sd_card_spi_control_port_read; mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv <= not mm_interconnect_0_spi_sd_card_spi_control_port_write; mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv <= not mm_interconnect_0_spi_stm32_spi_control_port_read; mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv <= not mm_interconnect_0_spi_stm32_spi_control_port_write; rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset; clock_116_mhz_clk <= altpll_0_c0_clk; end architecture rtl; -- of wasca
-- wasca.vhd -- Generated using ACDS version 15.0 145 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity wasca is port ( altpll_0_areset_conduit_export : in std_logic := '0'; -- altpll_0_areset_conduit.export altpll_0_locked_conduit_export : out std_logic; -- altpll_0_locked_conduit.export altpll_0_phasedone_conduit_export : out std_logic; -- altpll_0_phasedone_conduit.export audio_out_BCLK : in std_logic := '0'; -- audio_out.BCLK audio_out_DACDAT : out std_logic; -- .DACDAT audio_out_DACLRCK : in std_logic := '0'; -- .DACLRCK clk_clk : in std_logic := '0'; -- clk.clk clock_116_mhz_clk : out std_logic; -- clock_116_mhz.clk external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n external_sdram_controller_wire_cke : out std_logic; -- .cke external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n external_sdram_controller_wire_we_n : out std_logic; -- .we_n sega_saturn_abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- sega_saturn_abus_slave_0_abus.address sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect sega_saturn_abus_slave_0_abus_read : in std_logic := '0'; -- .read sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest sega_saturn_abus_slave_0_abus_interrupt : out std_logic; -- .interrupt sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .addressdata sega_saturn_abus_slave_0_abus_direction : out std_logic; -- .direction sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- .muxing sega_saturn_abus_slave_0_abus_disableout : out std_logic; -- .disableout sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := '0'; -- sega_saturn_abus_slave_0_conduit_saturn_reset.saturn_reset spi_sd_card_MISO : in std_logic := '0'; -- spi_sd_card.MISO spi_sd_card_MOSI : out std_logic; -- .MOSI spi_sd_card_SCLK : out std_logic; -- .SCLK spi_sd_card_SS_n : out std_logic; -- .SS_n spi_stm32_MISO : out std_logic; -- spi_stm32.MISO spi_stm32_MOSI : in std_logic := '0'; -- .MOSI spi_stm32_SCLK : in std_logic := '0'; -- .SCLK spi_stm32_SS_n : in std_logic := '0'; -- .SS_n uart_0_external_connection_rxd : in std_logic := '0'; -- uart_0_external_connection.rxd uart_0_external_connection_txd : out std_logic -- .txd ); end entity wasca; architecture rtl of wasca is component wasca_altpll_0 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset read : in std_logic := 'X'; -- read write : in std_logic := 'X'; -- write address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address readdata : out std_logic_vector(31 downto 0); -- readdata writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata c0 : out std_logic; -- clk areset : in std_logic := 'X'; -- export c1 : out std_logic; -- export locked : out std_logic; -- export phasedone : out std_logic -- export ); end component wasca_altpll_0; component wasca_audio_0 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address chipselect : in std_logic := 'X'; -- chipselect read : in std_logic := 'X'; -- read write : in std_logic := 'X'; -- write writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata readdata : out std_logic_vector(31 downto 0); -- readdata irq : out std_logic; -- irq AUD_BCLK : in std_logic := 'X'; -- export AUD_DACDAT : out std_logic; -- export AUD_DACLRCK : in std_logic := 'X' -- export ); end component wasca_audio_0; component wasca_external_sdram_controller is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n az_addr : in std_logic_vector(23 downto 0) := (others => 'X'); -- address az_be_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable_n az_cs : in std_logic := 'X'; -- chipselect az_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata az_rd_n : in std_logic := 'X'; -- read_n az_wr_n : in std_logic := 'X'; -- write_n za_data : out std_logic_vector(15 downto 0); -- readdata za_valid : out std_logic; -- readdatavalid za_waitrequest : out std_logic; -- waitrequest zs_addr : out std_logic_vector(12 downto 0); -- export zs_ba : out std_logic_vector(1 downto 0); -- export zs_cas_n : out std_logic; -- export zs_cke : out std_logic; -- export zs_cs_n : out std_logic; -- export zs_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export zs_dqm : out std_logic_vector(1 downto 0); -- export zs_ras_n : out std_logic; -- export zs_we_n : out std_logic -- export ); end component wasca_external_sdram_controller; component wasca_nios2_gen2_0 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n d_address : out std_logic_vector(26 downto 0); -- address d_byteenable : out std_logic_vector(3 downto 0); -- byteenable d_read : out std_logic; -- read d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata d_waitrequest : in std_logic := 'X'; -- waitrequest d_write : out std_logic; -- write d_writedata : out std_logic_vector(31 downto 0); -- writedata debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess i_address : out std_logic_vector(26 downto 0); -- address i_read : out std_logic; -- read i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata i_waitrequest : in std_logic := 'X'; -- waitrequest irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq debug_reset_request : out std_logic; -- reset debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess debug_mem_slave_read : in std_logic := 'X'; -- read debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata debug_mem_slave_waitrequest : out std_logic; -- waitrequest debug_mem_slave_write : in std_logic := 'X'; -- write debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata dummy_ci_port : out std_logic -- readra ); end component wasca_nios2_gen2_0; component altera_onchip_flash is generic ( INIT_FILENAME : string := ""; INIT_FILENAME_SIM : string := ""; DEVICE_FAMILY : string := "Unknown"; PART_NAME : string := "Unknown"; DEVICE_ID : string := "Unknown"; SECTOR1_START_ADDR : integer := 0; SECTOR1_END_ADDR : integer := 0; SECTOR2_START_ADDR : integer := 0; SECTOR2_END_ADDR : integer := 0; SECTOR3_START_ADDR : integer := 0; SECTOR3_END_ADDR : integer := 0; SECTOR4_START_ADDR : integer := 0; SECTOR4_END_ADDR : integer := 0; SECTOR5_START_ADDR : integer := 0; SECTOR5_END_ADDR : integer := 0; MIN_VALID_ADDR : integer := 0; MAX_VALID_ADDR : integer := 0; MIN_UFM_VALID_ADDR : integer := 0; MAX_UFM_VALID_ADDR : integer := 0; SECTOR1_MAP : integer := 0; SECTOR2_MAP : integer := 0; SECTOR3_MAP : integer := 0; SECTOR4_MAP : integer := 0; SECTOR5_MAP : integer := 0; ADDR_RANGE1_END_ADDR : integer := 0; ADDR_RANGE1_OFFSET : integer := 0; ADDR_RANGE2_OFFSET : integer := 0; AVMM_DATA_ADDR_WIDTH : integer := 19; AVMM_DATA_DATA_WIDTH : integer := 32; AVMM_DATA_BURSTCOUNT_WIDTH : integer := 4; SECTOR_READ_PROTECTION_MODE : integer := 31; FLASH_SEQ_READ_DATA_COUNT : integer := 2; FLASH_ADDR_ALIGNMENT_BITS : integer := 1; FLASH_READ_CYCLE_MAX_INDEX : integer := 4; FLASH_RESET_CYCLE_MAX_INDEX : integer := 29; FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX : integer := 112; FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX : integer := 40603248; FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX : integer := 35382; PARALLEL_MODE : boolean := true; READ_AND_WRITE_MODE : boolean := true; WRAPPING_BURST_MODE : boolean := false; IS_DUAL_BOOT : string := "False"; IS_ERAM_SKIP : string := "False"; IS_COMPRESSED_IMAGE : string := "False" ); port ( clock : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n avmm_data_addr : in std_logic_vector(15 downto 0) := (others => 'X'); -- address avmm_data_read : in std_logic := 'X'; -- read avmm_data_readdata : out std_logic_vector(31 downto 0); -- readdata avmm_data_waitrequest : out std_logic; -- waitrequest avmm_data_readdatavalid : out std_logic; -- readdatavalid avmm_data_burstcount : in std_logic_vector(3 downto 0) := (others => 'X'); -- burstcount avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata avmm_data_write : in std_logic := 'X'; -- write avmm_csr_addr : in std_logic := 'X'; -- address avmm_csr_read : in std_logic := 'X'; -- read avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata avmm_csr_write : in std_logic := 'X'; -- write avmm_csr_readdata : out std_logic_vector(31 downto 0) -- readdata ); end component altera_onchip_flash; component wasca_onchip_memory2_0 is port ( clk : in std_logic := 'X'; -- clk address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address clken : in std_logic := 'X'; -- clken chipselect : in std_logic := 'X'; -- chipselect write : in std_logic := 'X'; -- write readdata : out std_logic_vector(31 downto 0); -- readdata writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable reset : in std_logic := 'X'; -- reset reset_req : in std_logic := 'X' -- reset_req ); end component wasca_onchip_memory2_0; component sega_saturn_abus_slave is port ( clock : in std_logic := 'X'; -- clk abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect abus_read : in std_logic := 'X'; -- read abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write abus_waitrequest : out std_logic; -- waitrequest abus_interrupt : out std_logic; -- interrupt abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata abus_direction : out std_logic; -- direction abus_muxing : out std_logic_vector(1 downto 0); -- muxing abus_disable_out : out std_logic; -- disableout avalon_read : out std_logic; -- read avalon_write : out std_logic; -- write avalon_waitrequest : in std_logic := 'X'; -- waitrequest avalon_address : out std_logic_vector(27 downto 0); -- address avalon_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata avalon_writedata : out std_logic_vector(15 downto 0); -- writedata avalon_readdatavalid : in std_logic := 'X'; -- readdatavalid avalon_burstcount : out std_logic; -- burstcount reset : in std_logic := 'X'; -- reset saturn_reset : in std_logic := 'X'; -- saturn_reset avalon_nios_read : in std_logic := 'X'; -- read avalon_nios_write : in std_logic := 'X'; -- write avalon_nios_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata avalon_nios_readdata : out std_logic_vector(15 downto 0); -- readdata avalon_nios_waitrequest : out std_logic; -- waitrequest avalon_nios_readdatavalid : out std_logic; -- readdatavalid avalon_nios_burstcount : in std_logic := 'X' -- burstcount ); end component sega_saturn_abus_slave; component wasca_spi_sd_card is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n data_from_cpu : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata data_to_cpu : out std_logic_vector(15 downto 0); -- readdata mem_addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- address read_n : in std_logic := 'X'; -- read_n spi_select : in std_logic := 'X'; -- chipselect write_n : in std_logic := 'X'; -- write_n irq : out std_logic; -- irq MISO : in std_logic := 'X'; -- export MOSI : out std_logic; -- export SCLK : out std_logic; -- export SS_n : out std_logic -- export ); end component wasca_spi_sd_card; component wasca_spi_stm32 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n data_from_cpu : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata data_to_cpu : out std_logic_vector(15 downto 0); -- readdata mem_addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- address read_n : in std_logic := 'X'; -- read_n spi_select : in std_logic := 'X'; -- chipselect write_n : in std_logic := 'X'; -- write_n irq : out std_logic; -- irq MISO : out std_logic; -- export MOSI : in std_logic := 'X'; -- export SCLK : in std_logic := 'X'; -- export SS_n : in std_logic := 'X' -- export ); end component wasca_spi_stm32; component wasca_uart_0 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address begintransfer : in std_logic := 'X'; -- begintransfer chipselect : in std_logic := 'X'; -- chipselect read_n : in std_logic := 'X'; -- read_n write_n : in std_logic := 'X'; -- write_n writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata readdata : out std_logic_vector(15 downto 0); -- readdata dataavailable : out std_logic; -- dataavailable readyfordata : out std_logic; -- readyfordata rxd : in std_logic := 'X'; -- export txd : out std_logic; -- export irq : out std_logic -- irq ); end component wasca_uart_0; component wasca_mm_interconnect_0 is port ( altpll_0_c0_clk : in std_logic := 'X'; -- clk clk_0_clk_clk : in std_logic := 'X'; -- clk altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset nios2_gen2_0_data_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess nios2_gen2_0_instruction_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata sega_saturn_abus_slave_0_avalon_master_address : in std_logic_vector(27 downto 0) := (others => 'X'); -- address sega_saturn_abus_slave_0_avalon_master_waitrequest : out std_logic; -- waitrequest sega_saturn_abus_slave_0_avalon_master_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount sega_saturn_abus_slave_0_avalon_master_read : in std_logic := 'X'; -- read sega_saturn_abus_slave_0_avalon_master_readdata : out std_logic_vector(15 downto 0); -- readdata sega_saturn_abus_slave_0_avalon_master_readdatavalid : out std_logic; -- readdatavalid sega_saturn_abus_slave_0_avalon_master_write : in std_logic := 'X'; -- write sega_saturn_abus_slave_0_avalon_master_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata altpll_0_pll_slave_address : out std_logic_vector(1 downto 0); -- address altpll_0_pll_slave_write : out std_logic; -- write altpll_0_pll_slave_read : out std_logic; -- read altpll_0_pll_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata altpll_0_pll_slave_writedata : out std_logic_vector(31 downto 0); -- writedata audio_0_avalon_audio_slave_address : out std_logic_vector(1 downto 0); -- address audio_0_avalon_audio_slave_write : out std_logic; -- write audio_0_avalon_audio_slave_read : out std_logic; -- read audio_0_avalon_audio_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata audio_0_avalon_audio_slave_writedata : out std_logic_vector(31 downto 0); -- writedata audio_0_avalon_audio_slave_chipselect : out std_logic; -- chipselect external_sdram_controller_s1_address : out std_logic_vector(23 downto 0); -- address external_sdram_controller_s1_write : out std_logic; -- write external_sdram_controller_s1_read : out std_logic; -- read external_sdram_controller_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata external_sdram_controller_s1_writedata : out std_logic_vector(15 downto 0); -- writedata external_sdram_controller_s1_byteenable : out std_logic_vector(1 downto 0); -- byteenable external_sdram_controller_s1_readdatavalid : in std_logic := 'X'; -- readdatavalid external_sdram_controller_s1_waitrequest : in std_logic := 'X'; -- waitrequest external_sdram_controller_s1_chipselect : out std_logic; -- chipselect nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess onchip_flash_0_data_address : out std_logic_vector(15 downto 0); -- address onchip_flash_0_data_read : out std_logic; -- read onchip_flash_0_data_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata onchip_flash_0_data_burstcount : out std_logic_vector(3 downto 0); -- burstcount onchip_flash_0_data_readdatavalid : in std_logic := 'X'; -- readdatavalid onchip_flash_0_data_waitrequest : in std_logic := 'X'; -- waitrequest onchip_memory2_0_s1_address : out std_logic_vector(11 downto 0); -- address onchip_memory2_0_s1_write : out std_logic; -- write onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect onchip_memory2_0_s1_clken : out std_logic; -- clken sega_saturn_abus_slave_0_avalon_nios_address : out std_logic_vector(7 downto 0); -- address sega_saturn_abus_slave_0_avalon_nios_write : out std_logic; -- write sega_saturn_abus_slave_0_avalon_nios_read : out std_logic; -- read sega_saturn_abus_slave_0_avalon_nios_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata sega_saturn_abus_slave_0_avalon_nios_writedata : out std_logic_vector(15 downto 0); -- writedata sega_saturn_abus_slave_0_avalon_nios_burstcount : out std_logic_vector(0 downto 0); -- burstcount sega_saturn_abus_slave_0_avalon_nios_readdatavalid : in std_logic := 'X'; -- readdatavalid sega_saturn_abus_slave_0_avalon_nios_waitrequest : in std_logic := 'X'; -- waitrequest spi_sd_card_spi_control_port_address : out std_logic_vector(2 downto 0); -- address spi_sd_card_spi_control_port_write : out std_logic; -- write spi_sd_card_spi_control_port_read : out std_logic; -- read spi_sd_card_spi_control_port_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata spi_sd_card_spi_control_port_writedata : out std_logic_vector(15 downto 0); -- writedata spi_sd_card_spi_control_port_chipselect : out std_logic; -- chipselect spi_stm32_spi_control_port_address : out std_logic_vector(2 downto 0); -- address spi_stm32_spi_control_port_write : out std_logic; -- write spi_stm32_spi_control_port_read : out std_logic; -- read spi_stm32_spi_control_port_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata spi_stm32_spi_control_port_writedata : out std_logic_vector(15 downto 0); -- writedata spi_stm32_spi_control_port_chipselect : out std_logic; -- chipselect uart_0_s1_address : out std_logic_vector(2 downto 0); -- address uart_0_s1_write : out std_logic; -- write uart_0_s1_read : out std_logic; -- read uart_0_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata uart_0_s1_writedata : out std_logic_vector(15 downto 0); -- writedata uart_0_s1_begintransfer : out std_logic; -- begintransfer uart_0_s1_chipselect : out std_logic -- chipselect ); end component wasca_mm_interconnect_0; component wasca_irq_mapper is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset receiver0_irq : in std_logic := 'X'; -- irq receiver1_irq : in std_logic := 'X'; -- irq receiver2_irq : in std_logic := 'X'; -- irq receiver3_irq : in std_logic := 'X'; -- irq sender_irq : out std_logic_vector(31 downto 0) -- irq ); end component wasca_irq_mapper; component wasca_rst_controller is generic ( NUM_RESET_INPUTS : integer := 6; OUTPUT_RESET_SYNC_EDGES : string := "deassert"; SYNC_DEPTH : integer := 2; RESET_REQUEST_PRESENT : integer := 0; RESET_REQ_WAIT_TIME : integer := 1; MIN_RST_ASSERTION_TIME : integer := 3; RESET_REQ_EARLY_DSRT_TIME : integer := 1; USE_RESET_REQUEST_IN0 : integer := 0; USE_RESET_REQUEST_IN1 : integer := 0; USE_RESET_REQUEST_IN2 : integer := 0; USE_RESET_REQUEST_IN3 : integer := 0; USE_RESET_REQUEST_IN4 : integer := 0; USE_RESET_REQUEST_IN5 : integer := 0; USE_RESET_REQUEST_IN6 : integer := 0; USE_RESET_REQUEST_IN7 : integer := 0; USE_RESET_REQUEST_IN8 : integer := 0; USE_RESET_REQUEST_IN9 : integer := 0; USE_RESET_REQUEST_IN10 : integer := 0; USE_RESET_REQUEST_IN11 : integer := 0; USE_RESET_REQUEST_IN12 : integer := 0; USE_RESET_REQUEST_IN13 : integer := 0; USE_RESET_REQUEST_IN14 : integer := 0; USE_RESET_REQUEST_IN15 : integer := 0; ADAPT_RESET_REQUEST : integer := 0 ); port ( reset_in0 : in std_logic := 'X'; -- reset clk : in std_logic := 'X'; -- clk reset_out : out std_logic; -- reset reset_req : out std_logic; -- reset_req reset_req_in0 : in std_logic := 'X'; -- reset_req reset_in1 : in std_logic := 'X'; -- reset reset_req_in1 : in std_logic := 'X'; -- reset_req reset_in2 : in std_logic := 'X'; -- reset reset_req_in2 : in std_logic := 'X'; -- reset_req reset_in3 : in std_logic := 'X'; -- reset reset_req_in3 : in std_logic := 'X'; -- reset_req reset_in4 : in std_logic := 'X'; -- reset reset_req_in4 : in std_logic := 'X'; -- reset_req reset_in5 : in std_logic := 'X'; -- reset reset_req_in5 : in std_logic := 'X'; -- reset_req reset_in6 : in std_logic := 'X'; -- reset reset_req_in6 : in std_logic := 'X'; -- reset_req reset_in7 : in std_logic := 'X'; -- reset reset_req_in7 : in std_logic := 'X'; -- reset_req reset_in8 : in std_logic := 'X'; -- reset reset_req_in8 : in std_logic := 'X'; -- reset_req reset_in9 : in std_logic := 'X'; -- reset reset_req_in9 : in std_logic := 'X'; -- reset_req reset_in10 : in std_logic := 'X'; -- reset reset_req_in10 : in std_logic := 'X'; -- reset_req reset_in11 : in std_logic := 'X'; -- reset reset_req_in11 : in std_logic := 'X'; -- reset_req reset_in12 : in std_logic := 'X'; -- reset reset_req_in12 : in std_logic := 'X'; -- reset_req reset_in13 : in std_logic := 'X'; -- reset reset_req_in13 : in std_logic := 'X'; -- reset_req reset_in14 : in std_logic := 'X'; -- reset reset_req_in14 : in std_logic := 'X'; -- reset_req reset_in15 : in std_logic := 'X'; -- reset reset_req_in15 : in std_logic := 'X' -- reset_req ); end component wasca_rst_controller; component wasca_rst_controller_001 is generic ( NUM_RESET_INPUTS : integer := 6; OUTPUT_RESET_SYNC_EDGES : string := "deassert"; SYNC_DEPTH : integer := 2; RESET_REQUEST_PRESENT : integer := 0; RESET_REQ_WAIT_TIME : integer := 1; MIN_RST_ASSERTION_TIME : integer := 3; RESET_REQ_EARLY_DSRT_TIME : integer := 1; USE_RESET_REQUEST_IN0 : integer := 0; USE_RESET_REQUEST_IN1 : integer := 0; USE_RESET_REQUEST_IN2 : integer := 0; USE_RESET_REQUEST_IN3 : integer := 0; USE_RESET_REQUEST_IN4 : integer := 0; USE_RESET_REQUEST_IN5 : integer := 0; USE_RESET_REQUEST_IN6 : integer := 0; USE_RESET_REQUEST_IN7 : integer := 0; USE_RESET_REQUEST_IN8 : integer := 0; USE_RESET_REQUEST_IN9 : integer := 0; USE_RESET_REQUEST_IN10 : integer := 0; USE_RESET_REQUEST_IN11 : integer := 0; USE_RESET_REQUEST_IN12 : integer := 0; USE_RESET_REQUEST_IN13 : integer := 0; USE_RESET_REQUEST_IN14 : integer := 0; USE_RESET_REQUEST_IN15 : integer := 0; ADAPT_RESET_REQUEST : integer := 0 ); port ( reset_in0 : in std_logic := 'X'; -- reset clk : in std_logic := 'X'; -- clk reset_out : out std_logic; -- reset reset_req : out std_logic; -- reset_req reset_req_in0 : in std_logic := 'X'; -- reset_req reset_in1 : in std_logic := 'X'; -- reset reset_req_in1 : in std_logic := 'X'; -- reset_req reset_in2 : in std_logic := 'X'; -- reset reset_req_in2 : in std_logic := 'X'; -- reset_req reset_in3 : in std_logic := 'X'; -- reset reset_req_in3 : in std_logic := 'X'; -- reset_req reset_in4 : in std_logic := 'X'; -- reset reset_req_in4 : in std_logic := 'X'; -- reset_req reset_in5 : in std_logic := 'X'; -- reset reset_req_in5 : in std_logic := 'X'; -- reset_req reset_in6 : in std_logic := 'X'; -- reset reset_req_in6 : in std_logic := 'X'; -- reset_req reset_in7 : in std_logic := 'X'; -- reset reset_req_in7 : in std_logic := 'X'; -- reset_req reset_in8 : in std_logic := 'X'; -- reset reset_req_in8 : in std_logic := 'X'; -- reset_req reset_in9 : in std_logic := 'X'; -- reset reset_req_in9 : in std_logic := 'X'; -- reset_req reset_in10 : in std_logic := 'X'; -- reset reset_req_in10 : in std_logic := 'X'; -- reset_req reset_in11 : in std_logic := 'X'; -- reset reset_req_in11 : in std_logic := 'X'; -- reset_req reset_in12 : in std_logic := 'X'; -- reset reset_req_in12 : in std_logic := 'X'; -- reset_req reset_in13 : in std_logic := 'X'; -- reset reset_req_in13 : in std_logic := 'X'; -- reset_req reset_in14 : in std_logic := 'X'; -- reset reset_req_in14 : in std_logic := 'X'; -- reset_req reset_in15 : in std_logic := 'X'; -- reset reset_req_in15 : in std_logic := 'X' -- reset_req ); end component wasca_rst_controller_001; signal altpll_0_c0_clk : std_logic; -- altpll_0:c0 -> [clock_116_mhz_clk, audio_0:clk, external_sdram_controller:clk, irq_mapper:clk, mm_interconnect_0:altpll_0_c0_clk, nios2_gen2_0:clk, onchip_flash_0:clock, onchip_memory2_0:clk, rst_controller_001:clk, rst_controller_002:clk, sega_saturn_abus_slave_0:clock, spi_sd_card:clk, spi_stm32:clk, uart_0:clk] signal nios2_gen2_0_debug_reset_request_reset : std_logic; -- nios2_gen2_0:debug_reset_request -> [rst_controller:reset_in0, rst_controller_001:reset_in0, rst_controller_002:reset_in0] signal sega_saturn_abus_slave_0_avalon_master_waitrequest : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_waitrequest -> sega_saturn_abus_slave_0:avalon_waitrequest signal sega_saturn_abus_slave_0_avalon_master_readdata : std_logic_vector(15 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_readdata -> sega_saturn_abus_slave_0:avalon_readdata signal sega_saturn_abus_slave_0_avalon_master_read : std_logic; -- sega_saturn_abus_slave_0:avalon_read -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_read signal sega_saturn_abus_slave_0_avalon_master_address : std_logic_vector(27 downto 0); -- sega_saturn_abus_slave_0:avalon_address -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_address signal sega_saturn_abus_slave_0_avalon_master_readdatavalid : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_readdatavalid -> sega_saturn_abus_slave_0:avalon_readdatavalid signal sega_saturn_abus_slave_0_avalon_master_write : std_logic; -- sega_saturn_abus_slave_0:avalon_write -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_write signal sega_saturn_abus_slave_0_avalon_master_writedata : std_logic_vector(15 downto 0); -- sega_saturn_abus_slave_0:avalon_writedata -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_writedata signal sega_saturn_abus_slave_0_avalon_master_burstcount : std_logic; -- sega_saturn_abus_slave_0:avalon_burstcount -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_burstcount signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess signal nios2_gen2_0_data_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest signal nios2_gen2_0_instruction_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read signal mm_interconnect_0_external_sdram_controller_s1_chipselect : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_chipselect -> external_sdram_controller:az_cs signal mm_interconnect_0_external_sdram_controller_s1_readdata : std_logic_vector(15 downto 0); -- external_sdram_controller:za_data -> mm_interconnect_0:external_sdram_controller_s1_readdata signal mm_interconnect_0_external_sdram_controller_s1_waitrequest : std_logic; -- external_sdram_controller:za_waitrequest -> mm_interconnect_0:external_sdram_controller_s1_waitrequest signal mm_interconnect_0_external_sdram_controller_s1_address : std_logic_vector(23 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_address -> external_sdram_controller:az_addr signal mm_interconnect_0_external_sdram_controller_s1_read : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_read -> mm_interconnect_0_external_sdram_controller_s1_read:in signal mm_interconnect_0_external_sdram_controller_s1_byteenable : std_logic_vector(1 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_byteenable -> mm_interconnect_0_external_sdram_controller_s1_byteenable:in signal mm_interconnect_0_external_sdram_controller_s1_readdatavalid : std_logic; -- external_sdram_controller:za_valid -> mm_interconnect_0:external_sdram_controller_s1_readdatavalid signal mm_interconnect_0_external_sdram_controller_s1_write : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_write -> mm_interconnect_0_external_sdram_controller_s1_write:in signal mm_interconnect_0_external_sdram_controller_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_writedata -> external_sdram_controller:az_data signal mm_interconnect_0_onchip_flash_0_data_readdata : std_logic_vector(31 downto 0); -- onchip_flash_0:avmm_data_readdata -> mm_interconnect_0:onchip_flash_0_data_readdata signal mm_interconnect_0_onchip_flash_0_data_waitrequest : std_logic; -- onchip_flash_0:avmm_data_waitrequest -> mm_interconnect_0:onchip_flash_0_data_waitrequest signal mm_interconnect_0_onchip_flash_0_data_address : std_logic_vector(15 downto 0); -- mm_interconnect_0:onchip_flash_0_data_address -> onchip_flash_0:avmm_data_addr signal mm_interconnect_0_onchip_flash_0_data_read : std_logic; -- mm_interconnect_0:onchip_flash_0_data_read -> onchip_flash_0:avmm_data_read signal mm_interconnect_0_onchip_flash_0_data_readdatavalid : std_logic; -- onchip_flash_0:avmm_data_readdatavalid -> mm_interconnect_0:onchip_flash_0_data_readdatavalid signal mm_interconnect_0_onchip_flash_0_data_burstcount : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_flash_0_data_burstcount -> onchip_flash_0:avmm_data_burstcount signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(11 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken signal mm_interconnect_0_audio_0_avalon_audio_slave_chipselect : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_chipselect -> audio_0:chipselect signal mm_interconnect_0_audio_0_avalon_audio_slave_readdata : std_logic_vector(31 downto 0); -- audio_0:readdata -> mm_interconnect_0:audio_0_avalon_audio_slave_readdata signal mm_interconnect_0_audio_0_avalon_audio_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:audio_0_avalon_audio_slave_address -> audio_0:address signal mm_interconnect_0_audio_0_avalon_audio_slave_read : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_read -> audio_0:read signal mm_interconnect_0_audio_0_avalon_audio_slave_write : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_write -> audio_0:write signal mm_interconnect_0_audio_0_avalon_audio_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:audio_0_avalon_audio_slave_writedata -> audio_0:writedata signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata : std_logic_vector(15 downto 0); -- sega_saturn_abus_slave_0:avalon_nios_readdata -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_readdata signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest : std_logic; -- sega_saturn_abus_slave_0:avalon_nios_waitrequest -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_waitrequest signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_address -> sega_saturn_abus_slave_0:avalon_nios_address signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_read -> sega_saturn_abus_slave_0:avalon_nios_read signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid : std_logic; -- sega_saturn_abus_slave_0:avalon_nios_readdatavalid -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_readdatavalid signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_write -> sega_saturn_abus_slave_0:avalon_nios_write signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_writedata -> sega_saturn_abus_slave_0:avalon_nios_writedata signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount : std_logic_vector(0 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_burstcount -> sega_saturn_abus_slave_0:avalon_nios_burstcount signal mm_interconnect_0_altpll_0_pll_slave_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> mm_interconnect_0:altpll_0_pll_slave_readdata signal mm_interconnect_0_altpll_0_pll_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_address -> altpll_0:address signal mm_interconnect_0_altpll_0_pll_slave_read : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_read -> altpll_0:read signal mm_interconnect_0_altpll_0_pll_slave_write : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_write -> altpll_0:write signal mm_interconnect_0_altpll_0_pll_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_writedata -> altpll_0:writedata signal mm_interconnect_0_uart_0_s1_chipselect : std_logic; -- mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect signal mm_interconnect_0_uart_0_s1_readdata : std_logic_vector(15 downto 0); -- uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata signal mm_interconnect_0_uart_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:uart_0_s1_address -> uart_0:address signal mm_interconnect_0_uart_0_s1_read : std_logic; -- mm_interconnect_0:uart_0_s1_read -> mm_interconnect_0_uart_0_s1_read:in signal mm_interconnect_0_uart_0_s1_begintransfer : std_logic; -- mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer signal mm_interconnect_0_uart_0_s1_write : std_logic; -- mm_interconnect_0:uart_0_s1_write -> mm_interconnect_0_uart_0_s1_write:in signal mm_interconnect_0_uart_0_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata signal mm_interconnect_0_spi_sd_card_spi_control_port_chipselect : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_chipselect -> spi_sd_card:spi_select signal mm_interconnect_0_spi_sd_card_spi_control_port_readdata : std_logic_vector(15 downto 0); -- spi_sd_card:data_to_cpu -> mm_interconnect_0:spi_sd_card_spi_control_port_readdata signal mm_interconnect_0_spi_sd_card_spi_control_port_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:spi_sd_card_spi_control_port_address -> spi_sd_card:mem_addr signal mm_interconnect_0_spi_sd_card_spi_control_port_read : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_read -> mm_interconnect_0_spi_sd_card_spi_control_port_read:in signal mm_interconnect_0_spi_sd_card_spi_control_port_write : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_write -> mm_interconnect_0_spi_sd_card_spi_control_port_write:in signal mm_interconnect_0_spi_sd_card_spi_control_port_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:spi_sd_card_spi_control_port_writedata -> spi_sd_card:data_from_cpu signal mm_interconnect_0_spi_stm32_spi_control_port_chipselect : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_chipselect -> spi_stm32:spi_select signal mm_interconnect_0_spi_stm32_spi_control_port_readdata : std_logic_vector(15 downto 0); -- spi_stm32:data_to_cpu -> mm_interconnect_0:spi_stm32_spi_control_port_readdata signal mm_interconnect_0_spi_stm32_spi_control_port_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:spi_stm32_spi_control_port_address -> spi_stm32:mem_addr signal mm_interconnect_0_spi_stm32_spi_control_port_read : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_read -> mm_interconnect_0_spi_stm32_spi_control_port_read:in signal mm_interconnect_0_spi_stm32_spi_control_port_write : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_write -> mm_interconnect_0_spi_stm32_spi_control_port_write:in signal mm_interconnect_0_spi_stm32_spi_control_port_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:spi_stm32_spi_control_port_writedata -> spi_stm32:data_from_cpu signal irq_mapper_receiver0_irq : std_logic; -- audio_0:irq -> irq_mapper:receiver0_irq signal irq_mapper_receiver1_irq : std_logic; -- uart_0:irq -> irq_mapper:receiver1_irq signal irq_mapper_receiver2_irq : std_logic; -- spi_sd_card:irq -> irq_mapper:receiver2_irq signal irq_mapper_receiver3_irq : std_logic; -- spi_stm32:irq -> irq_mapper:receiver3_irq signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [altpll_0:reset, mm_interconnect_0:altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset] signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [audio_0:reset, irq_mapper:reset, mm_interconnect_0:sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_001_reset_out_reset:in, rst_translator:in_reset, sega_saturn_abus_slave_0:reset] signal rst_controller_001_reset_out_reset_req : std_logic; -- rst_controller_001:reset_req -> [onchip_memory2_0:reset_req, rst_translator:reset_req_in] signal mm_interconnect_0_external_sdram_controller_s1_read_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_read:inv -> external_sdram_controller:az_rd_n signal mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv : std_logic_vector(1 downto 0); -- mm_interconnect_0_external_sdram_controller_s1_byteenable:inv -> external_sdram_controller:az_be_n signal mm_interconnect_0_external_sdram_controller_s1_write_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_write:inv -> external_sdram_controller:az_wr_n signal mm_interconnect_0_uart_0_s1_read_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_read:inv -> uart_0:read_n signal mm_interconnect_0_uart_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_write:inv -> uart_0:write_n signal mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv : std_logic; -- mm_interconnect_0_spi_sd_card_spi_control_port_read:inv -> spi_sd_card:read_n signal mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv : std_logic; -- mm_interconnect_0_spi_sd_card_spi_control_port_write:inv -> spi_sd_card:write_n signal mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv : std_logic; -- mm_interconnect_0_spi_stm32_spi_control_port_read:inv -> spi_stm32:read_n signal mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv : std_logic; -- mm_interconnect_0_spi_stm32_spi_control_port_write:inv -> spi_stm32:write_n signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> [external_sdram_controller:reset_n, nios2_gen2_0:reset_n, onchip_flash_0:reset_n, spi_sd_card:reset_n, spi_stm32:reset_n, uart_0:reset_n] begin altpll_0 : component wasca_altpll_0 port map ( clk => clk_clk, -- inclk_interface.clk reset => rst_controller_reset_out_reset, -- inclk_interface_reset.reset read => mm_interconnect_0_altpll_0_pll_slave_read, -- pll_slave.read write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write address => mm_interconnect_0_altpll_0_pll_slave_address, -- .address readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata c0 => altpll_0_c0_clk, -- c0.clk areset => altpll_0_areset_conduit_export, -- areset_conduit.export c1 => open, -- c1_conduit.export locked => altpll_0_locked_conduit_export, -- locked_conduit.export phasedone => altpll_0_phasedone_conduit_export -- phasedone_conduit.export ); audio_0 : component wasca_audio_0 port map ( clk => altpll_0_c0_clk, -- clk.clk reset => rst_controller_001_reset_out_reset, -- reset.reset address => mm_interconnect_0_audio_0_avalon_audio_slave_address, -- avalon_audio_slave.address chipselect => mm_interconnect_0_audio_0_avalon_audio_slave_chipselect, -- .chipselect read => mm_interconnect_0_audio_0_avalon_audio_slave_read, -- .read write => mm_interconnect_0_audio_0_avalon_audio_slave_write, -- .write writedata => mm_interconnect_0_audio_0_avalon_audio_slave_writedata, -- .writedata readdata => mm_interconnect_0_audio_0_avalon_audio_slave_readdata, -- .readdata irq => irq_mapper_receiver0_irq, -- interrupt.irq AUD_BCLK => audio_out_BCLK, -- external_interface.export AUD_DACDAT => audio_out_DACDAT, -- .export AUD_DACLRCK => audio_out_DACLRCK -- .export ); external_sdram_controller : component wasca_external_sdram_controller port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n az_addr => mm_interconnect_0_external_sdram_controller_s1_address, -- s1.address az_be_n => mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv, -- .byteenable_n az_cs => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect az_data => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata az_rd_n => mm_interconnect_0_external_sdram_controller_s1_read_ports_inv, -- .read_n az_wr_n => mm_interconnect_0_external_sdram_controller_s1_write_ports_inv, -- .write_n za_data => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata za_valid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid za_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest zs_addr => external_sdram_controller_wire_addr, -- wire.export zs_ba => external_sdram_controller_wire_ba, -- .export zs_cas_n => external_sdram_controller_wire_cas_n, -- .export zs_cke => external_sdram_controller_wire_cke, -- .export zs_cs_n => external_sdram_controller_wire_cs_n, -- .export zs_dq => external_sdram_controller_wire_dq, -- .export zs_dqm => external_sdram_controller_wire_dqm, -- .export zs_ras_n => external_sdram_controller_wire_ras_n, -- .export zs_we_n => external_sdram_controller_wire_we_n -- .export ); nios2_gen2_0 : component wasca_nios2_gen2_0 port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n d_address => nios2_gen2_0_data_master_address, -- data_master.address d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable d_read => nios2_gen2_0_data_master_read, -- .read d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest d_write => nios2_gen2_0_data_master_write, -- .write d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address i_read => nios2_gen2_0_instruction_master_read, -- .read i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest irq => nios2_gen2_0_irq_irq, -- irq.irq debug_reset_request => nios2_gen2_0_debug_reset_request_reset, -- debug_reset_request.reset debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata dummy_ci_port => open -- custom_instruction_master.readra ); onchip_flash_0 : component altera_onchip_flash generic map ( INIT_FILENAME => "", INIT_FILENAME_SIM => "", DEVICE_FAMILY => "MAX 10", PART_NAME => "10M08SAE144C8GES", DEVICE_ID => "08", SECTOR1_START_ADDR => 0, SECTOR1_END_ADDR => 4095, SECTOR2_START_ADDR => 4096, SECTOR2_END_ADDR => 8191, SECTOR3_START_ADDR => 8192, SECTOR3_END_ADDR => 29183, SECTOR4_START_ADDR => 29184, SECTOR4_END_ADDR => 44031, SECTOR5_START_ADDR => 0, SECTOR5_END_ADDR => 0, MIN_VALID_ADDR => 0, MAX_VALID_ADDR => 44031, MIN_UFM_VALID_ADDR => 0, MAX_UFM_VALID_ADDR => 44031, SECTOR1_MAP => 1, SECTOR2_MAP => 2, SECTOR3_MAP => 3, SECTOR4_MAP => 4, SECTOR5_MAP => 0, ADDR_RANGE1_END_ADDR => 44031, ADDR_RANGE1_OFFSET => 512, ADDR_RANGE2_OFFSET => 0, AVMM_DATA_ADDR_WIDTH => 16, AVMM_DATA_DATA_WIDTH => 32, AVMM_DATA_BURSTCOUNT_WIDTH => 4, SECTOR_READ_PROTECTION_MODE => 31, FLASH_SEQ_READ_DATA_COUNT => 2, FLASH_ADDR_ALIGNMENT_BITS => 1, FLASH_READ_CYCLE_MAX_INDEX => 3, FLASH_RESET_CYCLE_MAX_INDEX => 29, FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX => 111, FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX => 40603248, FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX => 35382, PARALLEL_MODE => true, READ_AND_WRITE_MODE => false, WRAPPING_BURST_MODE => false, IS_DUAL_BOOT => "False", IS_ERAM_SKIP => "True", IS_COMPRESSED_IMAGE => "True" ) port map ( clock => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- nreset.reset_n avmm_data_addr => mm_interconnect_0_onchip_flash_0_data_address, -- data.address avmm_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read avmm_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata avmm_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest avmm_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid avmm_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount avmm_data_writedata => "00000000000000000000000000000000", -- (terminated) avmm_data_write => '0', -- (terminated) avmm_csr_addr => '0', -- (terminated) avmm_csr_read => '0', -- (terminated) avmm_csr_writedata => "00000000000000000000000000000000", -- (terminated) avmm_csr_write => '0', -- (terminated) avmm_csr_readdata => open -- (terminated) ); onchip_memory2_0 : component wasca_onchip_memory2_0 port map ( clk => altpll_0_c0_clk, -- clk1.clk address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable reset => rst_controller_001_reset_out_reset, -- reset1.reset reset_req => rst_controller_001_reset_out_reset_req -- .reset_req ); sega_saturn_abus_slave_0 : component sega_saturn_abus_slave port map ( clock => altpll_0_c0_clk, -- clock.clk abus_address => sega_saturn_abus_slave_0_abus_address, -- abus.address abus_chipselect => sega_saturn_abus_slave_0_abus_chipselect, -- .chipselect abus_read => sega_saturn_abus_slave_0_abus_read, -- .read abus_write => sega_saturn_abus_slave_0_abus_write, -- .write abus_waitrequest => sega_saturn_abus_slave_0_abus_waitrequest, -- .waitrequest abus_interrupt => sega_saturn_abus_slave_0_abus_interrupt, -- .interrupt abus_addressdata => sega_saturn_abus_slave_0_abus_addressdata, -- .addressdata abus_direction => sega_saturn_abus_slave_0_abus_direction, -- .direction abus_muxing => sega_saturn_abus_slave_0_abus_muxing, -- .muxing abus_disable_out => sega_saturn_abus_slave_0_abus_disableout, -- .disableout avalon_read => sega_saturn_abus_slave_0_avalon_master_read, -- avalon_master.read avalon_write => sega_saturn_abus_slave_0_avalon_master_write, -- .write avalon_waitrequest => sega_saturn_abus_slave_0_avalon_master_waitrequest, -- .waitrequest avalon_address => sega_saturn_abus_slave_0_avalon_master_address, -- .address avalon_readdata => sega_saturn_abus_slave_0_avalon_master_readdata, -- .readdata avalon_writedata => sega_saturn_abus_slave_0_avalon_master_writedata, -- .writedata avalon_readdatavalid => sega_saturn_abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid avalon_burstcount => sega_saturn_abus_slave_0_avalon_master_burstcount, -- .burstcount reset => rst_controller_001_reset_out_reset, -- reset.reset saturn_reset => sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset, -- conduit_saturn_reset.saturn_reset avalon_nios_read => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read, -- avalon_nios.read avalon_nios_write => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write, -- .write avalon_nios_address => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address, -- .address avalon_nios_writedata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata, -- .writedata avalon_nios_readdata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata, -- .readdata avalon_nios_waitrequest => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest avalon_nios_readdatavalid => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid avalon_nios_burstcount => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount(0) -- .burstcount ); spi_sd_card : component wasca_spi_sd_card port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n data_from_cpu => mm_interconnect_0_spi_sd_card_spi_control_port_writedata, -- spi_control_port.writedata data_to_cpu => mm_interconnect_0_spi_sd_card_spi_control_port_readdata, -- .readdata mem_addr => mm_interconnect_0_spi_sd_card_spi_control_port_address, -- .address read_n => mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv, -- .read_n spi_select => mm_interconnect_0_spi_sd_card_spi_control_port_chipselect, -- .chipselect write_n => mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv, -- .write_n irq => irq_mapper_receiver2_irq, -- irq.irq MISO => spi_sd_card_MISO, -- external.export MOSI => spi_sd_card_MOSI, -- .export SCLK => spi_sd_card_SCLK, -- .export SS_n => spi_sd_card_SS_n -- .export ); spi_stm32 : component wasca_spi_stm32 port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n data_from_cpu => mm_interconnect_0_spi_stm32_spi_control_port_writedata, -- spi_control_port.writedata data_to_cpu => mm_interconnect_0_spi_stm32_spi_control_port_readdata, -- .readdata mem_addr => mm_interconnect_0_spi_stm32_spi_control_port_address, -- .address read_n => mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv, -- .read_n spi_select => mm_interconnect_0_spi_stm32_spi_control_port_chipselect, -- .chipselect write_n => mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv, -- .write_n irq => irq_mapper_receiver3_irq, -- irq.irq MISO => spi_stm32_MISO, -- external.export MOSI => spi_stm32_MOSI, -- .export SCLK => spi_stm32_SCLK, -- .export SS_n => spi_stm32_SS_n -- .export ); uart_0 : component wasca_uart_0 port map ( clk => altpll_0_c0_clk, -- clk.clk reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n address => mm_interconnect_0_uart_0_s1_address, -- s1.address begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer chipselect => mm_interconnect_0_uart_0_s1_chipselect, -- .chipselect read_n => mm_interconnect_0_uart_0_s1_read_ports_inv, -- .read_n write_n => mm_interconnect_0_uart_0_s1_write_ports_inv, -- .write_n writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata dataavailable => open, -- .dataavailable readyfordata => open, -- .readyfordata rxd => uart_0_external_connection_rxd, -- external_connection.export txd => uart_0_external_connection_txd, -- .export irq => irq_mapper_receiver1_irq -- irq.irq ); mm_interconnect_0 : component wasca_mm_interconnect_0 port map ( altpll_0_c0_clk => altpll_0_c0_clk, -- altpll_0_c0.clk clk_0_clk_clk => clk_clk, -- clk_0_clk.clk altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- sega_saturn_abus_slave_0_reset_reset_bridge_in_reset.reset nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata sega_saturn_abus_slave_0_avalon_master_address => sega_saturn_abus_slave_0_avalon_master_address, -- sega_saturn_abus_slave_0_avalon_master.address sega_saturn_abus_slave_0_avalon_master_waitrequest => sega_saturn_abus_slave_0_avalon_master_waitrequest, -- .waitrequest sega_saturn_abus_slave_0_avalon_master_burstcount(0) => sega_saturn_abus_slave_0_avalon_master_burstcount, -- .burstcount sega_saturn_abus_slave_0_avalon_master_read => sega_saturn_abus_slave_0_avalon_master_read, -- .read sega_saturn_abus_slave_0_avalon_master_readdata => sega_saturn_abus_slave_0_avalon_master_readdata, -- .readdata sega_saturn_abus_slave_0_avalon_master_readdatavalid => sega_saturn_abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid sega_saturn_abus_slave_0_avalon_master_write => sega_saturn_abus_slave_0_avalon_master_write, -- .write sega_saturn_abus_slave_0_avalon_master_writedata => sega_saturn_abus_slave_0_avalon_master_writedata, -- .writedata altpll_0_pll_slave_address => mm_interconnect_0_altpll_0_pll_slave_address, -- altpll_0_pll_slave.address altpll_0_pll_slave_write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write altpll_0_pll_slave_read => mm_interconnect_0_altpll_0_pll_slave_read, -- .read altpll_0_pll_slave_readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata altpll_0_pll_slave_writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata audio_0_avalon_audio_slave_address => mm_interconnect_0_audio_0_avalon_audio_slave_address, -- audio_0_avalon_audio_slave.address audio_0_avalon_audio_slave_write => mm_interconnect_0_audio_0_avalon_audio_slave_write, -- .write audio_0_avalon_audio_slave_read => mm_interconnect_0_audio_0_avalon_audio_slave_read, -- .read audio_0_avalon_audio_slave_readdata => mm_interconnect_0_audio_0_avalon_audio_slave_readdata, -- .readdata audio_0_avalon_audio_slave_writedata => mm_interconnect_0_audio_0_avalon_audio_slave_writedata, -- .writedata audio_0_avalon_audio_slave_chipselect => mm_interconnect_0_audio_0_avalon_audio_slave_chipselect, -- .chipselect external_sdram_controller_s1_address => mm_interconnect_0_external_sdram_controller_s1_address, -- external_sdram_controller_s1.address external_sdram_controller_s1_write => mm_interconnect_0_external_sdram_controller_s1_write, -- .write external_sdram_controller_s1_read => mm_interconnect_0_external_sdram_controller_s1_read, -- .read external_sdram_controller_s1_readdata => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata external_sdram_controller_s1_writedata => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata external_sdram_controller_s1_byteenable => mm_interconnect_0_external_sdram_controller_s1_byteenable, -- .byteenable external_sdram_controller_s1_readdatavalid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid external_sdram_controller_s1_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest external_sdram_controller_s1_chipselect => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess onchip_flash_0_data_address => mm_interconnect_0_onchip_flash_0_data_address, -- onchip_flash_0_data.address onchip_flash_0_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read onchip_flash_0_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata onchip_flash_0_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount onchip_flash_0_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid onchip_flash_0_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken sega_saturn_abus_slave_0_avalon_nios_address => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address, -- sega_saturn_abus_slave_0_avalon_nios.address sega_saturn_abus_slave_0_avalon_nios_write => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write, -- .write sega_saturn_abus_slave_0_avalon_nios_read => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read, -- .read sega_saturn_abus_slave_0_avalon_nios_readdata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata, -- .readdata sega_saturn_abus_slave_0_avalon_nios_writedata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata, -- .writedata sega_saturn_abus_slave_0_avalon_nios_burstcount => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount, -- .burstcount sega_saturn_abus_slave_0_avalon_nios_readdatavalid => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid sega_saturn_abus_slave_0_avalon_nios_waitrequest => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest spi_sd_card_spi_control_port_address => mm_interconnect_0_spi_sd_card_spi_control_port_address, -- spi_sd_card_spi_control_port.address spi_sd_card_spi_control_port_write => mm_interconnect_0_spi_sd_card_spi_control_port_write, -- .write spi_sd_card_spi_control_port_read => mm_interconnect_0_spi_sd_card_spi_control_port_read, -- .read spi_sd_card_spi_control_port_readdata => mm_interconnect_0_spi_sd_card_spi_control_port_readdata, -- .readdata spi_sd_card_spi_control_port_writedata => mm_interconnect_0_spi_sd_card_spi_control_port_writedata, -- .writedata spi_sd_card_spi_control_port_chipselect => mm_interconnect_0_spi_sd_card_spi_control_port_chipselect, -- .chipselect spi_stm32_spi_control_port_address => mm_interconnect_0_spi_stm32_spi_control_port_address, -- spi_stm32_spi_control_port.address spi_stm32_spi_control_port_write => mm_interconnect_0_spi_stm32_spi_control_port_write, -- .write spi_stm32_spi_control_port_read => mm_interconnect_0_spi_stm32_spi_control_port_read, -- .read spi_stm32_spi_control_port_readdata => mm_interconnect_0_spi_stm32_spi_control_port_readdata, -- .readdata spi_stm32_spi_control_port_writedata => mm_interconnect_0_spi_stm32_spi_control_port_writedata, -- .writedata spi_stm32_spi_control_port_chipselect => mm_interconnect_0_spi_stm32_spi_control_port_chipselect, -- .chipselect uart_0_s1_address => mm_interconnect_0_uart_0_s1_address, -- uart_0_s1.address uart_0_s1_write => mm_interconnect_0_uart_0_s1_write, -- .write uart_0_s1_read => mm_interconnect_0_uart_0_s1_read, -- .read uart_0_s1_readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata uart_0_s1_writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata uart_0_s1_begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer uart_0_s1_chipselect => mm_interconnect_0_uart_0_s1_chipselect -- .chipselect ); irq_mapper : component wasca_irq_mapper port map ( clk => altpll_0_c0_clk, -- clk.clk reset => rst_controller_001_reset_out_reset, -- clk_reset.reset receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq receiver2_irq => irq_mapper_receiver2_irq, -- receiver2.irq receiver3_irq => irq_mapper_receiver3_irq, -- receiver3.irq sender_irq => nios2_gen2_0_irq_irq -- sender.irq ); rst_controller : component wasca_rst_controller generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "deassert", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 0, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset clk => clk_clk, -- clk.clk reset_out => rst_controller_reset_out_reset, -- reset_out.reset reset_req => open, -- (terminated) reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); rst_controller_001 : component wasca_rst_controller_001 generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "deassert", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 1, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset clk => altpll_0_c0_clk, -- clk.clk reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); rst_controller_002 : component wasca_rst_controller generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "both", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 0, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset clk => altpll_0_c0_clk, -- clk.clk reset_out => open, -- reset_out.reset reset_req => open, -- (terminated) reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); mm_interconnect_0_external_sdram_controller_s1_read_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_read; mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_byteenable; mm_interconnect_0_external_sdram_controller_s1_write_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_write; mm_interconnect_0_uart_0_s1_read_ports_inv <= not mm_interconnect_0_uart_0_s1_read; mm_interconnect_0_uart_0_s1_write_ports_inv <= not mm_interconnect_0_uart_0_s1_write; mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv <= not mm_interconnect_0_spi_sd_card_spi_control_port_read; mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv <= not mm_interconnect_0_spi_sd_card_spi_control_port_write; mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv <= not mm_interconnect_0_spi_stm32_spi_control_port_read; mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv <= not mm_interconnect_0_spi_stm32_spi_control_port_write; rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset; clock_116_mhz_clk <= altpll_0_c0_clk; end architecture rtl; -- of wasca
-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_EXPLUTPOS.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_explutpos IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 1); mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1) ); END fp_explutpos; ARCHITECTURE rtl OF fp_explutpos IS BEGIN pca: PROCESS (address) BEGIN CASE address IS WHEN "0000000" => mantissa <= conv_std_logic_vector(0,23); exponent <= conv_std_logic_vector(127,8); WHEN "0000001" => mantissa <= conv_std_logic_vector(3012692,23); exponent <= conv_std_logic_vector(128,8); WHEN "0000010" => mantissa <= conv_std_logic_vector(7107366,23); exponent <= conv_std_logic_vector(129,8); WHEN "0000011" => mantissa <= conv_std_logic_vector(2141998,23); exponent <= conv_std_logic_vector(131,8); WHEN "0000100" => mantissa <= conv_std_logic_vector(5923969,23); exponent <= conv_std_logic_vector(132,8); WHEN "0000101" => mantissa <= conv_std_logic_vector(1337797,23); exponent <= conv_std_logic_vector(134,8); WHEN "0000110" => mantissa <= conv_std_logic_vector(4830947,23); exponent <= conv_std_logic_vector(135,8); WHEN "0000111" => mantissa <= conv_std_logic_vector(595011,23); exponent <= conv_std_logic_vector(137,8); WHEN "0001000" => mantissa <= conv_std_logic_vector(3821396,23); exponent <= conv_std_logic_vector(138,8); WHEN "0001001" => mantissa <= conv_std_logic_vector(8206508,23); exponent <= conv_std_logic_vector(139,8); WHEN "0001010" => mantissa <= conv_std_logic_vector(2888942,23); exponent <= conv_std_logic_vector(141,8); WHEN "0001011" => mantissa <= conv_std_logic_vector(6939172,23); exponent <= conv_std_logic_vector(142,8); WHEN "0001100" => mantissa <= conv_std_logic_vector(2027699,23); exponent <= conv_std_logic_vector(144,8); WHEN "0001101" => mantissa <= conv_std_logic_vector(5768621,23); exponent <= conv_std_logic_vector(145,8); WHEN "0001110" => mantissa <= conv_std_logic_vector(1232226,23); exponent <= conv_std_logic_vector(147,8); WHEN "0001111" => mantissa <= conv_std_logic_vector(4687461,23); exponent <= conv_std_logic_vector(148,8); WHEN "0010000" => mantissa <= conv_std_logic_vector(497503,23); exponent <= conv_std_logic_vector(150,8); WHEN "0010001" => mantissa <= conv_std_logic_vector(3688868,23); exponent <= conv_std_logic_vector(151,8); WHEN "0010010" => mantissa <= conv_std_logic_vector(8026384,23); exponent <= conv_std_logic_vector(152,8); WHEN "0010011" => mantissa <= conv_std_logic_vector(2766536,23); exponent <= conv_std_logic_vector(154,8); WHEN "0010100" => mantissa <= conv_std_logic_vector(6772804,23); exponent <= conv_std_logic_vector(155,8); WHEN "0010101" => mantissa <= conv_std_logic_vector(1914640,23); exponent <= conv_std_logic_vector(157,8); WHEN "0010110" => mantissa <= conv_std_logic_vector(5614958,23); exponent <= conv_std_logic_vector(158,8); WHEN "0010111" => mantissa <= conv_std_logic_vector(1127802,23); exponent <= conv_std_logic_vector(160,8); WHEN "0011000" => mantissa <= conv_std_logic_vector(4545534,23); exponent <= conv_std_logic_vector(161,8); WHEN "0011001" => mantissa <= conv_std_logic_vector(401053,23); exponent <= conv_std_logic_vector(163,8); WHEN "0011010" => mantissa <= conv_std_logic_vector(3557779,23); exponent <= conv_std_logic_vector(164,8); WHEN "0011011" => mantissa <= conv_std_logic_vector(7848216,23); exponent <= conv_std_logic_vector(165,8); WHEN "0011100" => mantissa <= conv_std_logic_vector(2645458,23); exponent <= conv_std_logic_vector(167,8); WHEN "0011101" => mantissa <= conv_std_logic_vector(6608242,23); exponent <= conv_std_logic_vector(168,8); WHEN "0011110" => mantissa <= conv_std_logic_vector(1802808,23); exponent <= conv_std_logic_vector(170,8); WHEN "0011111" => mantissa <= conv_std_logic_vector(5462963,23); exponent <= conv_std_logic_vector(171,8); WHEN "0100000" => mantissa <= conv_std_logic_vector(1024510,23); exponent <= conv_std_logic_vector(173,8); WHEN "0100001" => mantissa <= conv_std_logic_vector(4405146,23); exponent <= conv_std_logic_vector(174,8); WHEN "0100010" => mantissa <= conv_std_logic_vector(305649,23); exponent <= conv_std_logic_vector(176,8); WHEN "0100011" => mantissa <= conv_std_logic_vector(3428113,23); exponent <= conv_std_logic_vector(177,8); WHEN "0100100" => mantissa <= conv_std_logic_vector(7671981,23); exponent <= conv_std_logic_vector(178,8); WHEN "0100101" => mantissa <= conv_std_logic_vector(2525694,23); exponent <= conv_std_logic_vector(180,8); WHEN "0100110" => mantissa <= conv_std_logic_vector(6445466,23); exponent <= conv_std_logic_vector(181,8); WHEN "0100111" => mantissa <= conv_std_logic_vector(1692191,23); exponent <= conv_std_logic_vector(183,8); WHEN "0101000" => mantissa <= conv_std_logic_vector(5312618,23); exponent <= conv_std_logic_vector(184,8); WHEN "0101001" => mantissa <= conv_std_logic_vector(922340,23); exponent <= conv_std_logic_vector(186,8); WHEN "0101010" => mantissa <= conv_std_logic_vector(4266283,23); exponent <= conv_std_logic_vector(187,8); WHEN "0101011" => mantissa <= conv_std_logic_vector(211282,23); exponent <= conv_std_logic_vector(189,8); WHEN "0101100" => mantissa <= conv_std_logic_vector(3299854,23); exponent <= conv_std_logic_vector(190,8); WHEN "0101101" => mantissa <= conv_std_logic_vector(7497659,23); exponent <= conv_std_logic_vector(191,8); WHEN "0101110" => mantissa <= conv_std_logic_vector(2407230,23); exponent <= conv_std_logic_vector(193,8); WHEN "0101111" => mantissa <= conv_std_logic_vector(6284457,23); exponent <= conv_std_logic_vector(194,8); WHEN "0110000" => mantissa <= conv_std_logic_vector(1582773,23); exponent <= conv_std_logic_vector(196,8); WHEN "0110001" => mantissa <= conv_std_logic_vector(5163905,23); exponent <= conv_std_logic_vector(197,8); WHEN "0110010" => mantissa <= conv_std_logic_vector(821279,23); exponent <= conv_std_logic_vector(199,8); WHEN "0110011" => mantissa <= conv_std_logic_vector(4128926,23); exponent <= conv_std_logic_vector(200,8); WHEN "0110100" => mantissa <= conv_std_logic_vector(117939,23); exponent <= conv_std_logic_vector(202,8); WHEN "0110101" => mantissa <= conv_std_logic_vector(3172987,23); exponent <= conv_std_logic_vector(203,8); WHEN "0110110" => mantissa <= conv_std_logic_vector(7325229,23); exponent <= conv_std_logic_vector(204,8); WHEN "0110111" => mantissa <= conv_std_logic_vector(2290052,23); exponent <= conv_std_logic_vector(206,8); WHEN "0111000" => mantissa <= conv_std_logic_vector(6125195,23); exponent <= conv_std_logic_vector(207,8); WHEN "0111001" => mantissa <= conv_std_logic_vector(1474544,23); exponent <= conv_std_logic_vector(209,8); WHEN "0111010" => mantissa <= conv_std_logic_vector(5016805,23); exponent <= conv_std_logic_vector(210,8); WHEN "0111011" => mantissa <= conv_std_logic_vector(721315,23); exponent <= conv_std_logic_vector(212,8); WHEN "0111100" => mantissa <= conv_std_logic_vector(3993061,23); exponent <= conv_std_logic_vector(213,8); WHEN "0111101" => mantissa <= conv_std_logic_vector(25608,23); exponent <= conv_std_logic_vector(215,8); WHEN "0111110" => mantissa <= conv_std_logic_vector(3047498,23); exponent <= conv_std_logic_vector(216,8); WHEN "0111111" => mantissa <= conv_std_logic_vector(7154671,23); exponent <= conv_std_logic_vector(217,8); WHEN "1000000" => mantissa <= conv_std_logic_vector(2174145,23); exponent <= conv_std_logic_vector(219,8); WHEN "1000001" => mantissa <= conv_std_logic_vector(5967662,23); exponent <= conv_std_logic_vector(220,8); WHEN "1000010" => mantissa <= conv_std_logic_vector(1367489,23); exponent <= conv_std_logic_vector(222,8); WHEN "1000011" => mantissa <= conv_std_logic_vector(4871303,23); exponent <= conv_std_logic_vector(223,8); WHEN "1000100" => mantissa <= conv_std_logic_vector(622436,23); exponent <= conv_std_logic_vector(225,8); WHEN "1000101" => mantissa <= conv_std_logic_vector(3858670,23); exponent <= conv_std_logic_vector(226,8); WHEN "1000110" => mantissa <= conv_std_logic_vector(8257169,23); exponent <= conv_std_logic_vector(227,8); WHEN "1000111" => mantissa <= conv_std_logic_vector(2923370,23); exponent <= conv_std_logic_vector(229,8); WHEN "1001000" => mantissa <= conv_std_logic_vector(6985964,23); exponent <= conv_std_logic_vector(230,8); WHEN "1001001" => mantissa <= conv_std_logic_vector(2059497,23); exponent <= conv_std_logic_vector(232,8); WHEN "1001010" => mantissa <= conv_std_logic_vector(5811839,23); exponent <= conv_std_logic_vector(233,8); WHEN "1001011" => mantissa <= conv_std_logic_vector(1261596,23); exponent <= conv_std_logic_vector(235,8); WHEN "1001100" => mantissa <= conv_std_logic_vector(4727380,23); exponent <= conv_std_logic_vector(236,8); WHEN "1001101" => mantissa <= conv_std_logic_vector(524630,23); exponent <= conv_std_logic_vector(238,8); WHEN "1001110" => mantissa <= conv_std_logic_vector(3725738,23); exponent <= conv_std_logic_vector(239,8); WHEN "1001111" => mantissa <= conv_std_logic_vector(8076495,23); exponent <= conv_std_logic_vector(240,8); WHEN "1010000" => mantissa <= conv_std_logic_vector(2800590,23); exponent <= conv_std_logic_vector(242,8); WHEN "1010001" => mantissa <= conv_std_logic_vector(6819089,23); exponent <= conv_std_logic_vector(243,8); WHEN "1010010" => mantissa <= conv_std_logic_vector(1946093,23); exponent <= conv_std_logic_vector(245,8); WHEN "1010011" => mantissa <= conv_std_logic_vector(5657707,23); exponent <= conv_std_logic_vector(246,8); WHEN "1010100" => mantissa <= conv_std_logic_vector(1156853,23); exponent <= conv_std_logic_vector(248,8); WHEN "1010101" => mantissa <= conv_std_logic_vector(4585019,23); exponent <= conv_std_logic_vector(249,8); WHEN "1010110" => mantissa <= conv_std_logic_vector(427885,23); exponent <= conv_std_logic_vector(251,8); WHEN "1010111" => mantissa <= conv_std_logic_vector(3594249,23); exponent <= conv_std_logic_vector(252,8); WHEN "1011000" => mantissa <= conv_std_logic_vector(7897783,23); exponent <= conv_std_logic_vector(253,8); WHEN "1011001" => mantissa <= conv_std_logic_vector(2679142,23); exponent <= conv_std_logic_vector(255,8); WHEN others => mantissa <= conv_std_logic_vector(0,23); exponent <= conv_std_logic_vector(0,8); END CASE; END PROCESS; END rtl;
-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_EXPLUTPOS.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_explutpos IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 1); mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1) ); END fp_explutpos; ARCHITECTURE rtl OF fp_explutpos IS BEGIN pca: PROCESS (address) BEGIN CASE address IS WHEN "0000000" => mantissa <= conv_std_logic_vector(0,23); exponent <= conv_std_logic_vector(127,8); WHEN "0000001" => mantissa <= conv_std_logic_vector(3012692,23); exponent <= conv_std_logic_vector(128,8); WHEN "0000010" => mantissa <= conv_std_logic_vector(7107366,23); exponent <= conv_std_logic_vector(129,8); WHEN "0000011" => mantissa <= conv_std_logic_vector(2141998,23); exponent <= conv_std_logic_vector(131,8); WHEN "0000100" => mantissa <= conv_std_logic_vector(5923969,23); exponent <= conv_std_logic_vector(132,8); WHEN "0000101" => mantissa <= conv_std_logic_vector(1337797,23); exponent <= conv_std_logic_vector(134,8); WHEN "0000110" => mantissa <= conv_std_logic_vector(4830947,23); exponent <= conv_std_logic_vector(135,8); WHEN "0000111" => mantissa <= conv_std_logic_vector(595011,23); exponent <= conv_std_logic_vector(137,8); WHEN "0001000" => mantissa <= conv_std_logic_vector(3821396,23); exponent <= conv_std_logic_vector(138,8); WHEN "0001001" => mantissa <= conv_std_logic_vector(8206508,23); exponent <= conv_std_logic_vector(139,8); WHEN "0001010" => mantissa <= conv_std_logic_vector(2888942,23); exponent <= conv_std_logic_vector(141,8); WHEN "0001011" => mantissa <= conv_std_logic_vector(6939172,23); exponent <= conv_std_logic_vector(142,8); WHEN "0001100" => mantissa <= conv_std_logic_vector(2027699,23); exponent <= conv_std_logic_vector(144,8); WHEN "0001101" => mantissa <= conv_std_logic_vector(5768621,23); exponent <= conv_std_logic_vector(145,8); WHEN "0001110" => mantissa <= conv_std_logic_vector(1232226,23); exponent <= conv_std_logic_vector(147,8); WHEN "0001111" => mantissa <= conv_std_logic_vector(4687461,23); exponent <= conv_std_logic_vector(148,8); WHEN "0010000" => mantissa <= conv_std_logic_vector(497503,23); exponent <= conv_std_logic_vector(150,8); WHEN "0010001" => mantissa <= conv_std_logic_vector(3688868,23); exponent <= conv_std_logic_vector(151,8); WHEN "0010010" => mantissa <= conv_std_logic_vector(8026384,23); exponent <= conv_std_logic_vector(152,8); WHEN "0010011" => mantissa <= conv_std_logic_vector(2766536,23); exponent <= conv_std_logic_vector(154,8); WHEN "0010100" => mantissa <= conv_std_logic_vector(6772804,23); exponent <= conv_std_logic_vector(155,8); WHEN "0010101" => mantissa <= conv_std_logic_vector(1914640,23); exponent <= conv_std_logic_vector(157,8); WHEN "0010110" => mantissa <= conv_std_logic_vector(5614958,23); exponent <= conv_std_logic_vector(158,8); WHEN "0010111" => mantissa <= conv_std_logic_vector(1127802,23); exponent <= conv_std_logic_vector(160,8); WHEN "0011000" => mantissa <= conv_std_logic_vector(4545534,23); exponent <= conv_std_logic_vector(161,8); WHEN "0011001" => mantissa <= conv_std_logic_vector(401053,23); exponent <= conv_std_logic_vector(163,8); WHEN "0011010" => mantissa <= conv_std_logic_vector(3557779,23); exponent <= conv_std_logic_vector(164,8); WHEN "0011011" => mantissa <= conv_std_logic_vector(7848216,23); exponent <= conv_std_logic_vector(165,8); WHEN "0011100" => mantissa <= conv_std_logic_vector(2645458,23); exponent <= conv_std_logic_vector(167,8); WHEN "0011101" => mantissa <= conv_std_logic_vector(6608242,23); exponent <= conv_std_logic_vector(168,8); WHEN "0011110" => mantissa <= conv_std_logic_vector(1802808,23); exponent <= conv_std_logic_vector(170,8); WHEN "0011111" => mantissa <= conv_std_logic_vector(5462963,23); exponent <= conv_std_logic_vector(171,8); WHEN "0100000" => mantissa <= conv_std_logic_vector(1024510,23); exponent <= conv_std_logic_vector(173,8); WHEN "0100001" => mantissa <= conv_std_logic_vector(4405146,23); exponent <= conv_std_logic_vector(174,8); WHEN "0100010" => mantissa <= conv_std_logic_vector(305649,23); exponent <= conv_std_logic_vector(176,8); WHEN "0100011" => mantissa <= conv_std_logic_vector(3428113,23); exponent <= conv_std_logic_vector(177,8); WHEN "0100100" => mantissa <= conv_std_logic_vector(7671981,23); exponent <= conv_std_logic_vector(178,8); WHEN "0100101" => mantissa <= conv_std_logic_vector(2525694,23); exponent <= conv_std_logic_vector(180,8); WHEN "0100110" => mantissa <= conv_std_logic_vector(6445466,23); exponent <= conv_std_logic_vector(181,8); WHEN "0100111" => mantissa <= conv_std_logic_vector(1692191,23); exponent <= conv_std_logic_vector(183,8); WHEN "0101000" => mantissa <= conv_std_logic_vector(5312618,23); exponent <= conv_std_logic_vector(184,8); WHEN "0101001" => mantissa <= conv_std_logic_vector(922340,23); exponent <= conv_std_logic_vector(186,8); WHEN "0101010" => mantissa <= conv_std_logic_vector(4266283,23); exponent <= conv_std_logic_vector(187,8); WHEN "0101011" => mantissa <= conv_std_logic_vector(211282,23); exponent <= conv_std_logic_vector(189,8); WHEN "0101100" => mantissa <= conv_std_logic_vector(3299854,23); exponent <= conv_std_logic_vector(190,8); WHEN "0101101" => mantissa <= conv_std_logic_vector(7497659,23); exponent <= conv_std_logic_vector(191,8); WHEN "0101110" => mantissa <= conv_std_logic_vector(2407230,23); exponent <= conv_std_logic_vector(193,8); WHEN "0101111" => mantissa <= conv_std_logic_vector(6284457,23); exponent <= conv_std_logic_vector(194,8); WHEN "0110000" => mantissa <= conv_std_logic_vector(1582773,23); exponent <= conv_std_logic_vector(196,8); WHEN "0110001" => mantissa <= conv_std_logic_vector(5163905,23); exponent <= conv_std_logic_vector(197,8); WHEN "0110010" => mantissa <= conv_std_logic_vector(821279,23); exponent <= conv_std_logic_vector(199,8); WHEN "0110011" => mantissa <= conv_std_logic_vector(4128926,23); exponent <= conv_std_logic_vector(200,8); WHEN "0110100" => mantissa <= conv_std_logic_vector(117939,23); exponent <= conv_std_logic_vector(202,8); WHEN "0110101" => mantissa <= conv_std_logic_vector(3172987,23); exponent <= conv_std_logic_vector(203,8); WHEN "0110110" => mantissa <= conv_std_logic_vector(7325229,23); exponent <= conv_std_logic_vector(204,8); WHEN "0110111" => mantissa <= conv_std_logic_vector(2290052,23); exponent <= conv_std_logic_vector(206,8); WHEN "0111000" => mantissa <= conv_std_logic_vector(6125195,23); exponent <= conv_std_logic_vector(207,8); WHEN "0111001" => mantissa <= conv_std_logic_vector(1474544,23); exponent <= conv_std_logic_vector(209,8); WHEN "0111010" => mantissa <= conv_std_logic_vector(5016805,23); exponent <= conv_std_logic_vector(210,8); WHEN "0111011" => mantissa <= conv_std_logic_vector(721315,23); exponent <= conv_std_logic_vector(212,8); WHEN "0111100" => mantissa <= conv_std_logic_vector(3993061,23); exponent <= conv_std_logic_vector(213,8); WHEN "0111101" => mantissa <= conv_std_logic_vector(25608,23); exponent <= conv_std_logic_vector(215,8); WHEN "0111110" => mantissa <= conv_std_logic_vector(3047498,23); exponent <= conv_std_logic_vector(216,8); WHEN "0111111" => mantissa <= conv_std_logic_vector(7154671,23); exponent <= conv_std_logic_vector(217,8); WHEN "1000000" => mantissa <= conv_std_logic_vector(2174145,23); exponent <= conv_std_logic_vector(219,8); WHEN "1000001" => mantissa <= conv_std_logic_vector(5967662,23); exponent <= conv_std_logic_vector(220,8); WHEN "1000010" => mantissa <= conv_std_logic_vector(1367489,23); exponent <= conv_std_logic_vector(222,8); WHEN "1000011" => mantissa <= conv_std_logic_vector(4871303,23); exponent <= conv_std_logic_vector(223,8); WHEN "1000100" => mantissa <= conv_std_logic_vector(622436,23); exponent <= conv_std_logic_vector(225,8); WHEN "1000101" => mantissa <= conv_std_logic_vector(3858670,23); exponent <= conv_std_logic_vector(226,8); WHEN "1000110" => mantissa <= conv_std_logic_vector(8257169,23); exponent <= conv_std_logic_vector(227,8); WHEN "1000111" => mantissa <= conv_std_logic_vector(2923370,23); exponent <= conv_std_logic_vector(229,8); WHEN "1001000" => mantissa <= conv_std_logic_vector(6985964,23); exponent <= conv_std_logic_vector(230,8); WHEN "1001001" => mantissa <= conv_std_logic_vector(2059497,23); exponent <= conv_std_logic_vector(232,8); WHEN "1001010" => mantissa <= conv_std_logic_vector(5811839,23); exponent <= conv_std_logic_vector(233,8); WHEN "1001011" => mantissa <= conv_std_logic_vector(1261596,23); exponent <= conv_std_logic_vector(235,8); WHEN "1001100" => mantissa <= conv_std_logic_vector(4727380,23); exponent <= conv_std_logic_vector(236,8); WHEN "1001101" => mantissa <= conv_std_logic_vector(524630,23); exponent <= conv_std_logic_vector(238,8); WHEN "1001110" => mantissa <= conv_std_logic_vector(3725738,23); exponent <= conv_std_logic_vector(239,8); WHEN "1001111" => mantissa <= conv_std_logic_vector(8076495,23); exponent <= conv_std_logic_vector(240,8); WHEN "1010000" => mantissa <= conv_std_logic_vector(2800590,23); exponent <= conv_std_logic_vector(242,8); WHEN "1010001" => mantissa <= conv_std_logic_vector(6819089,23); exponent <= conv_std_logic_vector(243,8); WHEN "1010010" => mantissa <= conv_std_logic_vector(1946093,23); exponent <= conv_std_logic_vector(245,8); WHEN "1010011" => mantissa <= conv_std_logic_vector(5657707,23); exponent <= conv_std_logic_vector(246,8); WHEN "1010100" => mantissa <= conv_std_logic_vector(1156853,23); exponent <= conv_std_logic_vector(248,8); WHEN "1010101" => mantissa <= conv_std_logic_vector(4585019,23); exponent <= conv_std_logic_vector(249,8); WHEN "1010110" => mantissa <= conv_std_logic_vector(427885,23); exponent <= conv_std_logic_vector(251,8); WHEN "1010111" => mantissa <= conv_std_logic_vector(3594249,23); exponent <= conv_std_logic_vector(252,8); WHEN "1011000" => mantissa <= conv_std_logic_vector(7897783,23); exponent <= conv_std_logic_vector(253,8); WHEN "1011001" => mantissa <= conv_std_logic_vector(2679142,23); exponent <= conv_std_logic_vector(255,8); WHEN others => mantissa <= conv_std_logic_vector(0,23); exponent <= conv_std_logic_vector(0,8); END CASE; END PROCESS; END rtl;
-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_EXPLUTPOS.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_explutpos IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 1); mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1) ); END fp_explutpos; ARCHITECTURE rtl OF fp_explutpos IS BEGIN pca: PROCESS (address) BEGIN CASE address IS WHEN "0000000" => mantissa <= conv_std_logic_vector(0,23); exponent <= conv_std_logic_vector(127,8); WHEN "0000001" => mantissa <= conv_std_logic_vector(3012692,23); exponent <= conv_std_logic_vector(128,8); WHEN "0000010" => mantissa <= conv_std_logic_vector(7107366,23); exponent <= conv_std_logic_vector(129,8); WHEN "0000011" => mantissa <= conv_std_logic_vector(2141998,23); exponent <= conv_std_logic_vector(131,8); WHEN "0000100" => mantissa <= conv_std_logic_vector(5923969,23); exponent <= conv_std_logic_vector(132,8); WHEN "0000101" => mantissa <= conv_std_logic_vector(1337797,23); exponent <= conv_std_logic_vector(134,8); WHEN "0000110" => mantissa <= conv_std_logic_vector(4830947,23); exponent <= conv_std_logic_vector(135,8); WHEN "0000111" => mantissa <= conv_std_logic_vector(595011,23); exponent <= conv_std_logic_vector(137,8); WHEN "0001000" => mantissa <= conv_std_logic_vector(3821396,23); exponent <= conv_std_logic_vector(138,8); WHEN "0001001" => mantissa <= conv_std_logic_vector(8206508,23); exponent <= conv_std_logic_vector(139,8); WHEN "0001010" => mantissa <= conv_std_logic_vector(2888942,23); exponent <= conv_std_logic_vector(141,8); WHEN "0001011" => mantissa <= conv_std_logic_vector(6939172,23); exponent <= conv_std_logic_vector(142,8); WHEN "0001100" => mantissa <= conv_std_logic_vector(2027699,23); exponent <= conv_std_logic_vector(144,8); WHEN "0001101" => mantissa <= conv_std_logic_vector(5768621,23); exponent <= conv_std_logic_vector(145,8); WHEN "0001110" => mantissa <= conv_std_logic_vector(1232226,23); exponent <= conv_std_logic_vector(147,8); WHEN "0001111" => mantissa <= conv_std_logic_vector(4687461,23); exponent <= conv_std_logic_vector(148,8); WHEN "0010000" => mantissa <= conv_std_logic_vector(497503,23); exponent <= conv_std_logic_vector(150,8); WHEN "0010001" => mantissa <= conv_std_logic_vector(3688868,23); exponent <= conv_std_logic_vector(151,8); WHEN "0010010" => mantissa <= conv_std_logic_vector(8026384,23); exponent <= conv_std_logic_vector(152,8); WHEN "0010011" => mantissa <= conv_std_logic_vector(2766536,23); exponent <= conv_std_logic_vector(154,8); WHEN "0010100" => mantissa <= conv_std_logic_vector(6772804,23); exponent <= conv_std_logic_vector(155,8); WHEN "0010101" => mantissa <= conv_std_logic_vector(1914640,23); exponent <= conv_std_logic_vector(157,8); WHEN "0010110" => mantissa <= conv_std_logic_vector(5614958,23); exponent <= conv_std_logic_vector(158,8); WHEN "0010111" => mantissa <= conv_std_logic_vector(1127802,23); exponent <= conv_std_logic_vector(160,8); WHEN "0011000" => mantissa <= conv_std_logic_vector(4545534,23); exponent <= conv_std_logic_vector(161,8); WHEN "0011001" => mantissa <= conv_std_logic_vector(401053,23); exponent <= conv_std_logic_vector(163,8); WHEN "0011010" => mantissa <= conv_std_logic_vector(3557779,23); exponent <= conv_std_logic_vector(164,8); WHEN "0011011" => mantissa <= conv_std_logic_vector(7848216,23); exponent <= conv_std_logic_vector(165,8); WHEN "0011100" => mantissa <= conv_std_logic_vector(2645458,23); exponent <= conv_std_logic_vector(167,8); WHEN "0011101" => mantissa <= conv_std_logic_vector(6608242,23); exponent <= conv_std_logic_vector(168,8); WHEN "0011110" => mantissa <= conv_std_logic_vector(1802808,23); exponent <= conv_std_logic_vector(170,8); WHEN "0011111" => mantissa <= conv_std_logic_vector(5462963,23); exponent <= conv_std_logic_vector(171,8); WHEN "0100000" => mantissa <= conv_std_logic_vector(1024510,23); exponent <= conv_std_logic_vector(173,8); WHEN "0100001" => mantissa <= conv_std_logic_vector(4405146,23); exponent <= conv_std_logic_vector(174,8); WHEN "0100010" => mantissa <= conv_std_logic_vector(305649,23); exponent <= conv_std_logic_vector(176,8); WHEN "0100011" => mantissa <= conv_std_logic_vector(3428113,23); exponent <= conv_std_logic_vector(177,8); WHEN "0100100" => mantissa <= conv_std_logic_vector(7671981,23); exponent <= conv_std_logic_vector(178,8); WHEN "0100101" => mantissa <= conv_std_logic_vector(2525694,23); exponent <= conv_std_logic_vector(180,8); WHEN "0100110" => mantissa <= conv_std_logic_vector(6445466,23); exponent <= conv_std_logic_vector(181,8); WHEN "0100111" => mantissa <= conv_std_logic_vector(1692191,23); exponent <= conv_std_logic_vector(183,8); WHEN "0101000" => mantissa <= conv_std_logic_vector(5312618,23); exponent <= conv_std_logic_vector(184,8); WHEN "0101001" => mantissa <= conv_std_logic_vector(922340,23); exponent <= conv_std_logic_vector(186,8); WHEN "0101010" => mantissa <= conv_std_logic_vector(4266283,23); exponent <= conv_std_logic_vector(187,8); WHEN "0101011" => mantissa <= conv_std_logic_vector(211282,23); exponent <= conv_std_logic_vector(189,8); WHEN "0101100" => mantissa <= conv_std_logic_vector(3299854,23); exponent <= conv_std_logic_vector(190,8); WHEN "0101101" => mantissa <= conv_std_logic_vector(7497659,23); exponent <= conv_std_logic_vector(191,8); WHEN "0101110" => mantissa <= conv_std_logic_vector(2407230,23); exponent <= conv_std_logic_vector(193,8); WHEN "0101111" => mantissa <= conv_std_logic_vector(6284457,23); exponent <= conv_std_logic_vector(194,8); WHEN "0110000" => mantissa <= conv_std_logic_vector(1582773,23); exponent <= conv_std_logic_vector(196,8); WHEN "0110001" => mantissa <= conv_std_logic_vector(5163905,23); exponent <= conv_std_logic_vector(197,8); WHEN "0110010" => mantissa <= conv_std_logic_vector(821279,23); exponent <= conv_std_logic_vector(199,8); WHEN "0110011" => mantissa <= conv_std_logic_vector(4128926,23); exponent <= conv_std_logic_vector(200,8); WHEN "0110100" => mantissa <= conv_std_logic_vector(117939,23); exponent <= conv_std_logic_vector(202,8); WHEN "0110101" => mantissa <= conv_std_logic_vector(3172987,23); exponent <= conv_std_logic_vector(203,8); WHEN "0110110" => mantissa <= conv_std_logic_vector(7325229,23); exponent <= conv_std_logic_vector(204,8); WHEN "0110111" => mantissa <= conv_std_logic_vector(2290052,23); exponent <= conv_std_logic_vector(206,8); WHEN "0111000" => mantissa <= conv_std_logic_vector(6125195,23); exponent <= conv_std_logic_vector(207,8); WHEN "0111001" => mantissa <= conv_std_logic_vector(1474544,23); exponent <= conv_std_logic_vector(209,8); WHEN "0111010" => mantissa <= conv_std_logic_vector(5016805,23); exponent <= conv_std_logic_vector(210,8); WHEN "0111011" => mantissa <= conv_std_logic_vector(721315,23); exponent <= conv_std_logic_vector(212,8); WHEN "0111100" => mantissa <= conv_std_logic_vector(3993061,23); exponent <= conv_std_logic_vector(213,8); WHEN "0111101" => mantissa <= conv_std_logic_vector(25608,23); exponent <= conv_std_logic_vector(215,8); WHEN "0111110" => mantissa <= conv_std_logic_vector(3047498,23); exponent <= conv_std_logic_vector(216,8); WHEN "0111111" => mantissa <= conv_std_logic_vector(7154671,23); exponent <= conv_std_logic_vector(217,8); WHEN "1000000" => mantissa <= conv_std_logic_vector(2174145,23); exponent <= conv_std_logic_vector(219,8); WHEN "1000001" => mantissa <= conv_std_logic_vector(5967662,23); exponent <= conv_std_logic_vector(220,8); WHEN "1000010" => mantissa <= conv_std_logic_vector(1367489,23); exponent <= conv_std_logic_vector(222,8); WHEN "1000011" => mantissa <= conv_std_logic_vector(4871303,23); exponent <= conv_std_logic_vector(223,8); WHEN "1000100" => mantissa <= conv_std_logic_vector(622436,23); exponent <= conv_std_logic_vector(225,8); WHEN "1000101" => mantissa <= conv_std_logic_vector(3858670,23); exponent <= conv_std_logic_vector(226,8); WHEN "1000110" => mantissa <= conv_std_logic_vector(8257169,23); exponent <= conv_std_logic_vector(227,8); WHEN "1000111" => mantissa <= conv_std_logic_vector(2923370,23); exponent <= conv_std_logic_vector(229,8); WHEN "1001000" => mantissa <= conv_std_logic_vector(6985964,23); exponent <= conv_std_logic_vector(230,8); WHEN "1001001" => mantissa <= conv_std_logic_vector(2059497,23); exponent <= conv_std_logic_vector(232,8); WHEN "1001010" => mantissa <= conv_std_logic_vector(5811839,23); exponent <= conv_std_logic_vector(233,8); WHEN "1001011" => mantissa <= conv_std_logic_vector(1261596,23); exponent <= conv_std_logic_vector(235,8); WHEN "1001100" => mantissa <= conv_std_logic_vector(4727380,23); exponent <= conv_std_logic_vector(236,8); WHEN "1001101" => mantissa <= conv_std_logic_vector(524630,23); exponent <= conv_std_logic_vector(238,8); WHEN "1001110" => mantissa <= conv_std_logic_vector(3725738,23); exponent <= conv_std_logic_vector(239,8); WHEN "1001111" => mantissa <= conv_std_logic_vector(8076495,23); exponent <= conv_std_logic_vector(240,8); WHEN "1010000" => mantissa <= conv_std_logic_vector(2800590,23); exponent <= conv_std_logic_vector(242,8); WHEN "1010001" => mantissa <= conv_std_logic_vector(6819089,23); exponent <= conv_std_logic_vector(243,8); WHEN "1010010" => mantissa <= conv_std_logic_vector(1946093,23); exponent <= conv_std_logic_vector(245,8); WHEN "1010011" => mantissa <= conv_std_logic_vector(5657707,23); exponent <= conv_std_logic_vector(246,8); WHEN "1010100" => mantissa <= conv_std_logic_vector(1156853,23); exponent <= conv_std_logic_vector(248,8); WHEN "1010101" => mantissa <= conv_std_logic_vector(4585019,23); exponent <= conv_std_logic_vector(249,8); WHEN "1010110" => mantissa <= conv_std_logic_vector(427885,23); exponent <= conv_std_logic_vector(251,8); WHEN "1010111" => mantissa <= conv_std_logic_vector(3594249,23); exponent <= conv_std_logic_vector(252,8); WHEN "1011000" => mantissa <= conv_std_logic_vector(7897783,23); exponent <= conv_std_logic_vector(253,8); WHEN "1011001" => mantissa <= conv_std_logic_vector(2679142,23); exponent <= conv_std_logic_vector(255,8); WHEN others => mantissa <= conv_std_logic_vector(0,23); exponent <= conv_std_logic_vector(0,8); END CASE; END PROCESS; END rtl;
-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_EXPLUTPOS.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_explutpos IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 1); mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1) ); END fp_explutpos; ARCHITECTURE rtl OF fp_explutpos IS BEGIN pca: PROCESS (address) BEGIN CASE address IS WHEN "0000000" => mantissa <= conv_std_logic_vector(0,23); exponent <= conv_std_logic_vector(127,8); WHEN "0000001" => mantissa <= conv_std_logic_vector(3012692,23); exponent <= conv_std_logic_vector(128,8); WHEN "0000010" => mantissa <= conv_std_logic_vector(7107366,23); exponent <= conv_std_logic_vector(129,8); WHEN "0000011" => mantissa <= conv_std_logic_vector(2141998,23); exponent <= conv_std_logic_vector(131,8); WHEN "0000100" => mantissa <= conv_std_logic_vector(5923969,23); exponent <= conv_std_logic_vector(132,8); WHEN "0000101" => mantissa <= conv_std_logic_vector(1337797,23); exponent <= conv_std_logic_vector(134,8); WHEN "0000110" => mantissa <= conv_std_logic_vector(4830947,23); exponent <= conv_std_logic_vector(135,8); WHEN "0000111" => mantissa <= conv_std_logic_vector(595011,23); exponent <= conv_std_logic_vector(137,8); WHEN "0001000" => mantissa <= conv_std_logic_vector(3821396,23); exponent <= conv_std_logic_vector(138,8); WHEN "0001001" => mantissa <= conv_std_logic_vector(8206508,23); exponent <= conv_std_logic_vector(139,8); WHEN "0001010" => mantissa <= conv_std_logic_vector(2888942,23); exponent <= conv_std_logic_vector(141,8); WHEN "0001011" => mantissa <= conv_std_logic_vector(6939172,23); exponent <= conv_std_logic_vector(142,8); WHEN "0001100" => mantissa <= conv_std_logic_vector(2027699,23); exponent <= conv_std_logic_vector(144,8); WHEN "0001101" => mantissa <= conv_std_logic_vector(5768621,23); exponent <= conv_std_logic_vector(145,8); WHEN "0001110" => mantissa <= conv_std_logic_vector(1232226,23); exponent <= conv_std_logic_vector(147,8); WHEN "0001111" => mantissa <= conv_std_logic_vector(4687461,23); exponent <= conv_std_logic_vector(148,8); WHEN "0010000" => mantissa <= conv_std_logic_vector(497503,23); exponent <= conv_std_logic_vector(150,8); WHEN "0010001" => mantissa <= conv_std_logic_vector(3688868,23); exponent <= conv_std_logic_vector(151,8); WHEN "0010010" => mantissa <= conv_std_logic_vector(8026384,23); exponent <= conv_std_logic_vector(152,8); WHEN "0010011" => mantissa <= conv_std_logic_vector(2766536,23); exponent <= conv_std_logic_vector(154,8); WHEN "0010100" => mantissa <= conv_std_logic_vector(6772804,23); exponent <= conv_std_logic_vector(155,8); WHEN "0010101" => mantissa <= conv_std_logic_vector(1914640,23); exponent <= conv_std_logic_vector(157,8); WHEN "0010110" => mantissa <= conv_std_logic_vector(5614958,23); exponent <= conv_std_logic_vector(158,8); WHEN "0010111" => mantissa <= conv_std_logic_vector(1127802,23); exponent <= conv_std_logic_vector(160,8); WHEN "0011000" => mantissa <= conv_std_logic_vector(4545534,23); exponent <= conv_std_logic_vector(161,8); WHEN "0011001" => mantissa <= conv_std_logic_vector(401053,23); exponent <= conv_std_logic_vector(163,8); WHEN "0011010" => mantissa <= conv_std_logic_vector(3557779,23); exponent <= conv_std_logic_vector(164,8); WHEN "0011011" => mantissa <= conv_std_logic_vector(7848216,23); exponent <= conv_std_logic_vector(165,8); WHEN "0011100" => mantissa <= conv_std_logic_vector(2645458,23); exponent <= conv_std_logic_vector(167,8); WHEN "0011101" => mantissa <= conv_std_logic_vector(6608242,23); exponent <= conv_std_logic_vector(168,8); WHEN "0011110" => mantissa <= conv_std_logic_vector(1802808,23); exponent <= conv_std_logic_vector(170,8); WHEN "0011111" => mantissa <= conv_std_logic_vector(5462963,23); exponent <= conv_std_logic_vector(171,8); WHEN "0100000" => mantissa <= conv_std_logic_vector(1024510,23); exponent <= conv_std_logic_vector(173,8); WHEN "0100001" => mantissa <= conv_std_logic_vector(4405146,23); exponent <= conv_std_logic_vector(174,8); WHEN "0100010" => mantissa <= conv_std_logic_vector(305649,23); exponent <= conv_std_logic_vector(176,8); WHEN "0100011" => mantissa <= conv_std_logic_vector(3428113,23); exponent <= conv_std_logic_vector(177,8); WHEN "0100100" => mantissa <= conv_std_logic_vector(7671981,23); exponent <= conv_std_logic_vector(178,8); WHEN "0100101" => mantissa <= conv_std_logic_vector(2525694,23); exponent <= conv_std_logic_vector(180,8); WHEN "0100110" => mantissa <= conv_std_logic_vector(6445466,23); exponent <= conv_std_logic_vector(181,8); WHEN "0100111" => mantissa <= conv_std_logic_vector(1692191,23); exponent <= conv_std_logic_vector(183,8); WHEN "0101000" => mantissa <= conv_std_logic_vector(5312618,23); exponent <= conv_std_logic_vector(184,8); WHEN "0101001" => mantissa <= conv_std_logic_vector(922340,23); exponent <= conv_std_logic_vector(186,8); WHEN "0101010" => mantissa <= conv_std_logic_vector(4266283,23); exponent <= conv_std_logic_vector(187,8); WHEN "0101011" => mantissa <= conv_std_logic_vector(211282,23); exponent <= conv_std_logic_vector(189,8); WHEN "0101100" => mantissa <= conv_std_logic_vector(3299854,23); exponent <= conv_std_logic_vector(190,8); WHEN "0101101" => mantissa <= conv_std_logic_vector(7497659,23); exponent <= conv_std_logic_vector(191,8); WHEN "0101110" => mantissa <= conv_std_logic_vector(2407230,23); exponent <= conv_std_logic_vector(193,8); WHEN "0101111" => mantissa <= conv_std_logic_vector(6284457,23); exponent <= conv_std_logic_vector(194,8); WHEN "0110000" => mantissa <= conv_std_logic_vector(1582773,23); exponent <= conv_std_logic_vector(196,8); WHEN "0110001" => mantissa <= conv_std_logic_vector(5163905,23); exponent <= conv_std_logic_vector(197,8); WHEN "0110010" => mantissa <= conv_std_logic_vector(821279,23); exponent <= conv_std_logic_vector(199,8); WHEN "0110011" => mantissa <= conv_std_logic_vector(4128926,23); exponent <= conv_std_logic_vector(200,8); WHEN "0110100" => mantissa <= conv_std_logic_vector(117939,23); exponent <= conv_std_logic_vector(202,8); WHEN "0110101" => mantissa <= conv_std_logic_vector(3172987,23); exponent <= conv_std_logic_vector(203,8); WHEN "0110110" => mantissa <= conv_std_logic_vector(7325229,23); exponent <= conv_std_logic_vector(204,8); WHEN "0110111" => mantissa <= conv_std_logic_vector(2290052,23); exponent <= conv_std_logic_vector(206,8); WHEN "0111000" => mantissa <= conv_std_logic_vector(6125195,23); exponent <= conv_std_logic_vector(207,8); WHEN "0111001" => mantissa <= conv_std_logic_vector(1474544,23); exponent <= conv_std_logic_vector(209,8); WHEN "0111010" => mantissa <= conv_std_logic_vector(5016805,23); exponent <= conv_std_logic_vector(210,8); WHEN "0111011" => mantissa <= conv_std_logic_vector(721315,23); exponent <= conv_std_logic_vector(212,8); WHEN "0111100" => mantissa <= conv_std_logic_vector(3993061,23); exponent <= conv_std_logic_vector(213,8); WHEN "0111101" => mantissa <= conv_std_logic_vector(25608,23); exponent <= conv_std_logic_vector(215,8); WHEN "0111110" => mantissa <= conv_std_logic_vector(3047498,23); exponent <= conv_std_logic_vector(216,8); WHEN "0111111" => mantissa <= conv_std_logic_vector(7154671,23); exponent <= conv_std_logic_vector(217,8); WHEN "1000000" => mantissa <= conv_std_logic_vector(2174145,23); exponent <= conv_std_logic_vector(219,8); WHEN "1000001" => mantissa <= conv_std_logic_vector(5967662,23); exponent <= conv_std_logic_vector(220,8); WHEN "1000010" => mantissa <= conv_std_logic_vector(1367489,23); exponent <= conv_std_logic_vector(222,8); WHEN "1000011" => mantissa <= conv_std_logic_vector(4871303,23); exponent <= conv_std_logic_vector(223,8); WHEN "1000100" => mantissa <= conv_std_logic_vector(622436,23); exponent <= conv_std_logic_vector(225,8); WHEN "1000101" => mantissa <= conv_std_logic_vector(3858670,23); exponent <= conv_std_logic_vector(226,8); WHEN "1000110" => mantissa <= conv_std_logic_vector(8257169,23); exponent <= conv_std_logic_vector(227,8); WHEN "1000111" => mantissa <= conv_std_logic_vector(2923370,23); exponent <= conv_std_logic_vector(229,8); WHEN "1001000" => mantissa <= conv_std_logic_vector(6985964,23); exponent <= conv_std_logic_vector(230,8); WHEN "1001001" => mantissa <= conv_std_logic_vector(2059497,23); exponent <= conv_std_logic_vector(232,8); WHEN "1001010" => mantissa <= conv_std_logic_vector(5811839,23); exponent <= conv_std_logic_vector(233,8); WHEN "1001011" => mantissa <= conv_std_logic_vector(1261596,23); exponent <= conv_std_logic_vector(235,8); WHEN "1001100" => mantissa <= conv_std_logic_vector(4727380,23); exponent <= conv_std_logic_vector(236,8); WHEN "1001101" => mantissa <= conv_std_logic_vector(524630,23); exponent <= conv_std_logic_vector(238,8); WHEN "1001110" => mantissa <= conv_std_logic_vector(3725738,23); exponent <= conv_std_logic_vector(239,8); WHEN "1001111" => mantissa <= conv_std_logic_vector(8076495,23); exponent <= conv_std_logic_vector(240,8); WHEN "1010000" => mantissa <= conv_std_logic_vector(2800590,23); exponent <= conv_std_logic_vector(242,8); WHEN "1010001" => mantissa <= conv_std_logic_vector(6819089,23); exponent <= conv_std_logic_vector(243,8); WHEN "1010010" => mantissa <= conv_std_logic_vector(1946093,23); exponent <= conv_std_logic_vector(245,8); WHEN "1010011" => mantissa <= conv_std_logic_vector(5657707,23); exponent <= conv_std_logic_vector(246,8); WHEN "1010100" => mantissa <= conv_std_logic_vector(1156853,23); exponent <= conv_std_logic_vector(248,8); WHEN "1010101" => mantissa <= conv_std_logic_vector(4585019,23); exponent <= conv_std_logic_vector(249,8); WHEN "1010110" => mantissa <= conv_std_logic_vector(427885,23); exponent <= conv_std_logic_vector(251,8); WHEN "1010111" => mantissa <= conv_std_logic_vector(3594249,23); exponent <= conv_std_logic_vector(252,8); WHEN "1011000" => mantissa <= conv_std_logic_vector(7897783,23); exponent <= conv_std_logic_vector(253,8); WHEN "1011001" => mantissa <= conv_std_logic_vector(2679142,23); exponent <= conv_std_logic_vector(255,8); WHEN others => mantissa <= conv_std_logic_vector(0,23); exponent <= conv_std_logic_vector(0,8); END CASE; END PROCESS; END rtl;
-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_EXPLUTPOS.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_explutpos IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 1); mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1) ); END fp_explutpos; ARCHITECTURE rtl OF fp_explutpos IS BEGIN pca: PROCESS (address) BEGIN CASE address IS WHEN "0000000" => mantissa <= conv_std_logic_vector(0,23); exponent <= conv_std_logic_vector(127,8); WHEN "0000001" => mantissa <= conv_std_logic_vector(3012692,23); exponent <= conv_std_logic_vector(128,8); WHEN "0000010" => mantissa <= conv_std_logic_vector(7107366,23); exponent <= conv_std_logic_vector(129,8); WHEN "0000011" => mantissa <= conv_std_logic_vector(2141998,23); exponent <= conv_std_logic_vector(131,8); WHEN "0000100" => mantissa <= conv_std_logic_vector(5923969,23); exponent <= conv_std_logic_vector(132,8); WHEN "0000101" => mantissa <= conv_std_logic_vector(1337797,23); exponent <= conv_std_logic_vector(134,8); WHEN "0000110" => mantissa <= conv_std_logic_vector(4830947,23); exponent <= conv_std_logic_vector(135,8); WHEN "0000111" => mantissa <= conv_std_logic_vector(595011,23); exponent <= conv_std_logic_vector(137,8); WHEN "0001000" => mantissa <= conv_std_logic_vector(3821396,23); exponent <= conv_std_logic_vector(138,8); WHEN "0001001" => mantissa <= conv_std_logic_vector(8206508,23); exponent <= conv_std_logic_vector(139,8); WHEN "0001010" => mantissa <= conv_std_logic_vector(2888942,23); exponent <= conv_std_logic_vector(141,8); WHEN "0001011" => mantissa <= conv_std_logic_vector(6939172,23); exponent <= conv_std_logic_vector(142,8); WHEN "0001100" => mantissa <= conv_std_logic_vector(2027699,23); exponent <= conv_std_logic_vector(144,8); WHEN "0001101" => mantissa <= conv_std_logic_vector(5768621,23); exponent <= conv_std_logic_vector(145,8); WHEN "0001110" => mantissa <= conv_std_logic_vector(1232226,23); exponent <= conv_std_logic_vector(147,8); WHEN "0001111" => mantissa <= conv_std_logic_vector(4687461,23); exponent <= conv_std_logic_vector(148,8); WHEN "0010000" => mantissa <= conv_std_logic_vector(497503,23); exponent <= conv_std_logic_vector(150,8); WHEN "0010001" => mantissa <= conv_std_logic_vector(3688868,23); exponent <= conv_std_logic_vector(151,8); WHEN "0010010" => mantissa <= conv_std_logic_vector(8026384,23); exponent <= conv_std_logic_vector(152,8); WHEN "0010011" => mantissa <= conv_std_logic_vector(2766536,23); exponent <= conv_std_logic_vector(154,8); WHEN "0010100" => mantissa <= conv_std_logic_vector(6772804,23); exponent <= conv_std_logic_vector(155,8); WHEN "0010101" => mantissa <= conv_std_logic_vector(1914640,23); exponent <= conv_std_logic_vector(157,8); WHEN "0010110" => mantissa <= conv_std_logic_vector(5614958,23); exponent <= conv_std_logic_vector(158,8); WHEN "0010111" => mantissa <= conv_std_logic_vector(1127802,23); exponent <= conv_std_logic_vector(160,8); WHEN "0011000" => mantissa <= conv_std_logic_vector(4545534,23); exponent <= conv_std_logic_vector(161,8); WHEN "0011001" => mantissa <= conv_std_logic_vector(401053,23); exponent <= conv_std_logic_vector(163,8); WHEN "0011010" => mantissa <= conv_std_logic_vector(3557779,23); exponent <= conv_std_logic_vector(164,8); WHEN "0011011" => mantissa <= conv_std_logic_vector(7848216,23); exponent <= conv_std_logic_vector(165,8); WHEN "0011100" => mantissa <= conv_std_logic_vector(2645458,23); exponent <= conv_std_logic_vector(167,8); WHEN "0011101" => mantissa <= conv_std_logic_vector(6608242,23); exponent <= conv_std_logic_vector(168,8); WHEN "0011110" => mantissa <= conv_std_logic_vector(1802808,23); exponent <= conv_std_logic_vector(170,8); WHEN "0011111" => mantissa <= conv_std_logic_vector(5462963,23); exponent <= conv_std_logic_vector(171,8); WHEN "0100000" => mantissa <= conv_std_logic_vector(1024510,23); exponent <= conv_std_logic_vector(173,8); WHEN "0100001" => mantissa <= conv_std_logic_vector(4405146,23); exponent <= conv_std_logic_vector(174,8); WHEN "0100010" => mantissa <= conv_std_logic_vector(305649,23); exponent <= conv_std_logic_vector(176,8); WHEN "0100011" => mantissa <= conv_std_logic_vector(3428113,23); exponent <= conv_std_logic_vector(177,8); WHEN "0100100" => mantissa <= conv_std_logic_vector(7671981,23); exponent <= conv_std_logic_vector(178,8); WHEN "0100101" => mantissa <= conv_std_logic_vector(2525694,23); exponent <= conv_std_logic_vector(180,8); WHEN "0100110" => mantissa <= conv_std_logic_vector(6445466,23); exponent <= conv_std_logic_vector(181,8); WHEN "0100111" => mantissa <= conv_std_logic_vector(1692191,23); exponent <= conv_std_logic_vector(183,8); WHEN "0101000" => mantissa <= conv_std_logic_vector(5312618,23); exponent <= conv_std_logic_vector(184,8); WHEN "0101001" => mantissa <= conv_std_logic_vector(922340,23); exponent <= conv_std_logic_vector(186,8); WHEN "0101010" => mantissa <= conv_std_logic_vector(4266283,23); exponent <= conv_std_logic_vector(187,8); WHEN "0101011" => mantissa <= conv_std_logic_vector(211282,23); exponent <= conv_std_logic_vector(189,8); WHEN "0101100" => mantissa <= conv_std_logic_vector(3299854,23); exponent <= conv_std_logic_vector(190,8); WHEN "0101101" => mantissa <= conv_std_logic_vector(7497659,23); exponent <= conv_std_logic_vector(191,8); WHEN "0101110" => mantissa <= conv_std_logic_vector(2407230,23); exponent <= conv_std_logic_vector(193,8); WHEN "0101111" => mantissa <= conv_std_logic_vector(6284457,23); exponent <= conv_std_logic_vector(194,8); WHEN "0110000" => mantissa <= conv_std_logic_vector(1582773,23); exponent <= conv_std_logic_vector(196,8); WHEN "0110001" => mantissa <= conv_std_logic_vector(5163905,23); exponent <= conv_std_logic_vector(197,8); WHEN "0110010" => mantissa <= conv_std_logic_vector(821279,23); exponent <= conv_std_logic_vector(199,8); WHEN "0110011" => mantissa <= conv_std_logic_vector(4128926,23); exponent <= conv_std_logic_vector(200,8); WHEN "0110100" => mantissa <= conv_std_logic_vector(117939,23); exponent <= conv_std_logic_vector(202,8); WHEN "0110101" => mantissa <= conv_std_logic_vector(3172987,23); exponent <= conv_std_logic_vector(203,8); WHEN "0110110" => mantissa <= conv_std_logic_vector(7325229,23); exponent <= conv_std_logic_vector(204,8); WHEN "0110111" => mantissa <= conv_std_logic_vector(2290052,23); exponent <= conv_std_logic_vector(206,8); WHEN "0111000" => mantissa <= conv_std_logic_vector(6125195,23); exponent <= conv_std_logic_vector(207,8); WHEN "0111001" => mantissa <= conv_std_logic_vector(1474544,23); exponent <= conv_std_logic_vector(209,8); WHEN "0111010" => mantissa <= conv_std_logic_vector(5016805,23); exponent <= conv_std_logic_vector(210,8); WHEN "0111011" => mantissa <= conv_std_logic_vector(721315,23); exponent <= conv_std_logic_vector(212,8); WHEN "0111100" => mantissa <= conv_std_logic_vector(3993061,23); exponent <= conv_std_logic_vector(213,8); WHEN "0111101" => mantissa <= conv_std_logic_vector(25608,23); exponent <= conv_std_logic_vector(215,8); WHEN "0111110" => mantissa <= conv_std_logic_vector(3047498,23); exponent <= conv_std_logic_vector(216,8); WHEN "0111111" => mantissa <= conv_std_logic_vector(7154671,23); exponent <= conv_std_logic_vector(217,8); WHEN "1000000" => mantissa <= conv_std_logic_vector(2174145,23); exponent <= conv_std_logic_vector(219,8); WHEN "1000001" => mantissa <= conv_std_logic_vector(5967662,23); exponent <= conv_std_logic_vector(220,8); WHEN "1000010" => mantissa <= conv_std_logic_vector(1367489,23); exponent <= conv_std_logic_vector(222,8); WHEN "1000011" => mantissa <= conv_std_logic_vector(4871303,23); exponent <= conv_std_logic_vector(223,8); WHEN "1000100" => mantissa <= conv_std_logic_vector(622436,23); exponent <= conv_std_logic_vector(225,8); WHEN "1000101" => mantissa <= conv_std_logic_vector(3858670,23); exponent <= conv_std_logic_vector(226,8); WHEN "1000110" => mantissa <= conv_std_logic_vector(8257169,23); exponent <= conv_std_logic_vector(227,8); WHEN "1000111" => mantissa <= conv_std_logic_vector(2923370,23); exponent <= conv_std_logic_vector(229,8); WHEN "1001000" => mantissa <= conv_std_logic_vector(6985964,23); exponent <= conv_std_logic_vector(230,8); WHEN "1001001" => mantissa <= conv_std_logic_vector(2059497,23); exponent <= conv_std_logic_vector(232,8); WHEN "1001010" => mantissa <= conv_std_logic_vector(5811839,23); exponent <= conv_std_logic_vector(233,8); WHEN "1001011" => mantissa <= conv_std_logic_vector(1261596,23); exponent <= conv_std_logic_vector(235,8); WHEN "1001100" => mantissa <= conv_std_logic_vector(4727380,23); exponent <= conv_std_logic_vector(236,8); WHEN "1001101" => mantissa <= conv_std_logic_vector(524630,23); exponent <= conv_std_logic_vector(238,8); WHEN "1001110" => mantissa <= conv_std_logic_vector(3725738,23); exponent <= conv_std_logic_vector(239,8); WHEN "1001111" => mantissa <= conv_std_logic_vector(8076495,23); exponent <= conv_std_logic_vector(240,8); WHEN "1010000" => mantissa <= conv_std_logic_vector(2800590,23); exponent <= conv_std_logic_vector(242,8); WHEN "1010001" => mantissa <= conv_std_logic_vector(6819089,23); exponent <= conv_std_logic_vector(243,8); WHEN "1010010" => mantissa <= conv_std_logic_vector(1946093,23); exponent <= conv_std_logic_vector(245,8); WHEN "1010011" => mantissa <= conv_std_logic_vector(5657707,23); exponent <= conv_std_logic_vector(246,8); WHEN "1010100" => mantissa <= conv_std_logic_vector(1156853,23); exponent <= conv_std_logic_vector(248,8); WHEN "1010101" => mantissa <= conv_std_logic_vector(4585019,23); exponent <= conv_std_logic_vector(249,8); WHEN "1010110" => mantissa <= conv_std_logic_vector(427885,23); exponent <= conv_std_logic_vector(251,8); WHEN "1010111" => mantissa <= conv_std_logic_vector(3594249,23); exponent <= conv_std_logic_vector(252,8); WHEN "1011000" => mantissa <= conv_std_logic_vector(7897783,23); exponent <= conv_std_logic_vector(253,8); WHEN "1011001" => mantissa <= conv_std_logic_vector(2679142,23); exponent <= conv_std_logic_vector(255,8); WHEN others => mantissa <= conv_std_logic_vector(0,23); exponent <= conv_std_logic_vector(0,8); END CASE; END PROCESS; END rtl;
-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_EXPLUTPOS.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_explutpos IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 1); mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1) ); END fp_explutpos; ARCHITECTURE rtl OF fp_explutpos IS BEGIN pca: PROCESS (address) BEGIN CASE address IS WHEN "0000000" => mantissa <= conv_std_logic_vector(0,23); exponent <= conv_std_logic_vector(127,8); WHEN "0000001" => mantissa <= conv_std_logic_vector(3012692,23); exponent <= conv_std_logic_vector(128,8); WHEN "0000010" => mantissa <= conv_std_logic_vector(7107366,23); exponent <= conv_std_logic_vector(129,8); WHEN "0000011" => mantissa <= conv_std_logic_vector(2141998,23); exponent <= conv_std_logic_vector(131,8); WHEN "0000100" => mantissa <= conv_std_logic_vector(5923969,23); exponent <= conv_std_logic_vector(132,8); WHEN "0000101" => mantissa <= conv_std_logic_vector(1337797,23); exponent <= conv_std_logic_vector(134,8); WHEN "0000110" => mantissa <= conv_std_logic_vector(4830947,23); exponent <= conv_std_logic_vector(135,8); WHEN "0000111" => mantissa <= conv_std_logic_vector(595011,23); exponent <= conv_std_logic_vector(137,8); WHEN "0001000" => mantissa <= conv_std_logic_vector(3821396,23); exponent <= conv_std_logic_vector(138,8); WHEN "0001001" => mantissa <= conv_std_logic_vector(8206508,23); exponent <= conv_std_logic_vector(139,8); WHEN "0001010" => mantissa <= conv_std_logic_vector(2888942,23); exponent <= conv_std_logic_vector(141,8); WHEN "0001011" => mantissa <= conv_std_logic_vector(6939172,23); exponent <= conv_std_logic_vector(142,8); WHEN "0001100" => mantissa <= conv_std_logic_vector(2027699,23); exponent <= conv_std_logic_vector(144,8); WHEN "0001101" => mantissa <= conv_std_logic_vector(5768621,23); exponent <= conv_std_logic_vector(145,8); WHEN "0001110" => mantissa <= conv_std_logic_vector(1232226,23); exponent <= conv_std_logic_vector(147,8); WHEN "0001111" => mantissa <= conv_std_logic_vector(4687461,23); exponent <= conv_std_logic_vector(148,8); WHEN "0010000" => mantissa <= conv_std_logic_vector(497503,23); exponent <= conv_std_logic_vector(150,8); WHEN "0010001" => mantissa <= conv_std_logic_vector(3688868,23); exponent <= conv_std_logic_vector(151,8); WHEN "0010010" => mantissa <= conv_std_logic_vector(8026384,23); exponent <= conv_std_logic_vector(152,8); WHEN "0010011" => mantissa <= conv_std_logic_vector(2766536,23); exponent <= conv_std_logic_vector(154,8); WHEN "0010100" => mantissa <= conv_std_logic_vector(6772804,23); exponent <= conv_std_logic_vector(155,8); WHEN "0010101" => mantissa <= conv_std_logic_vector(1914640,23); exponent <= conv_std_logic_vector(157,8); WHEN "0010110" => mantissa <= conv_std_logic_vector(5614958,23); exponent <= conv_std_logic_vector(158,8); WHEN "0010111" => mantissa <= conv_std_logic_vector(1127802,23); exponent <= conv_std_logic_vector(160,8); WHEN "0011000" => mantissa <= conv_std_logic_vector(4545534,23); exponent <= conv_std_logic_vector(161,8); WHEN "0011001" => mantissa <= conv_std_logic_vector(401053,23); exponent <= conv_std_logic_vector(163,8); WHEN "0011010" => mantissa <= conv_std_logic_vector(3557779,23); exponent <= conv_std_logic_vector(164,8); WHEN "0011011" => mantissa <= conv_std_logic_vector(7848216,23); exponent <= conv_std_logic_vector(165,8); WHEN "0011100" => mantissa <= conv_std_logic_vector(2645458,23); exponent <= conv_std_logic_vector(167,8); WHEN "0011101" => mantissa <= conv_std_logic_vector(6608242,23); exponent <= conv_std_logic_vector(168,8); WHEN "0011110" => mantissa <= conv_std_logic_vector(1802808,23); exponent <= conv_std_logic_vector(170,8); WHEN "0011111" => mantissa <= conv_std_logic_vector(5462963,23); exponent <= conv_std_logic_vector(171,8); WHEN "0100000" => mantissa <= conv_std_logic_vector(1024510,23); exponent <= conv_std_logic_vector(173,8); WHEN "0100001" => mantissa <= conv_std_logic_vector(4405146,23); exponent <= conv_std_logic_vector(174,8); WHEN "0100010" => mantissa <= conv_std_logic_vector(305649,23); exponent <= conv_std_logic_vector(176,8); WHEN "0100011" => mantissa <= conv_std_logic_vector(3428113,23); exponent <= conv_std_logic_vector(177,8); WHEN "0100100" => mantissa <= conv_std_logic_vector(7671981,23); exponent <= conv_std_logic_vector(178,8); WHEN "0100101" => mantissa <= conv_std_logic_vector(2525694,23); exponent <= conv_std_logic_vector(180,8); WHEN "0100110" => mantissa <= conv_std_logic_vector(6445466,23); exponent <= conv_std_logic_vector(181,8); WHEN "0100111" => mantissa <= conv_std_logic_vector(1692191,23); exponent <= conv_std_logic_vector(183,8); WHEN "0101000" => mantissa <= conv_std_logic_vector(5312618,23); exponent <= conv_std_logic_vector(184,8); WHEN "0101001" => mantissa <= conv_std_logic_vector(922340,23); exponent <= conv_std_logic_vector(186,8); WHEN "0101010" => mantissa <= conv_std_logic_vector(4266283,23); exponent <= conv_std_logic_vector(187,8); WHEN "0101011" => mantissa <= conv_std_logic_vector(211282,23); exponent <= conv_std_logic_vector(189,8); WHEN "0101100" => mantissa <= conv_std_logic_vector(3299854,23); exponent <= conv_std_logic_vector(190,8); WHEN "0101101" => mantissa <= conv_std_logic_vector(7497659,23); exponent <= conv_std_logic_vector(191,8); WHEN "0101110" => mantissa <= conv_std_logic_vector(2407230,23); exponent <= conv_std_logic_vector(193,8); WHEN "0101111" => mantissa <= conv_std_logic_vector(6284457,23); exponent <= conv_std_logic_vector(194,8); WHEN "0110000" => mantissa <= conv_std_logic_vector(1582773,23); exponent <= conv_std_logic_vector(196,8); WHEN "0110001" => mantissa <= conv_std_logic_vector(5163905,23); exponent <= conv_std_logic_vector(197,8); WHEN "0110010" => mantissa <= conv_std_logic_vector(821279,23); exponent <= conv_std_logic_vector(199,8); WHEN "0110011" => mantissa <= conv_std_logic_vector(4128926,23); exponent <= conv_std_logic_vector(200,8); WHEN "0110100" => mantissa <= conv_std_logic_vector(117939,23); exponent <= conv_std_logic_vector(202,8); WHEN "0110101" => mantissa <= conv_std_logic_vector(3172987,23); exponent <= conv_std_logic_vector(203,8); WHEN "0110110" => mantissa <= conv_std_logic_vector(7325229,23); exponent <= conv_std_logic_vector(204,8); WHEN "0110111" => mantissa <= conv_std_logic_vector(2290052,23); exponent <= conv_std_logic_vector(206,8); WHEN "0111000" => mantissa <= conv_std_logic_vector(6125195,23); exponent <= conv_std_logic_vector(207,8); WHEN "0111001" => mantissa <= conv_std_logic_vector(1474544,23); exponent <= conv_std_logic_vector(209,8); WHEN "0111010" => mantissa <= conv_std_logic_vector(5016805,23); exponent <= conv_std_logic_vector(210,8); WHEN "0111011" => mantissa <= conv_std_logic_vector(721315,23); exponent <= conv_std_logic_vector(212,8); WHEN "0111100" => mantissa <= conv_std_logic_vector(3993061,23); exponent <= conv_std_logic_vector(213,8); WHEN "0111101" => mantissa <= conv_std_logic_vector(25608,23); exponent <= conv_std_logic_vector(215,8); WHEN "0111110" => mantissa <= conv_std_logic_vector(3047498,23); exponent <= conv_std_logic_vector(216,8); WHEN "0111111" => mantissa <= conv_std_logic_vector(7154671,23); exponent <= conv_std_logic_vector(217,8); WHEN "1000000" => mantissa <= conv_std_logic_vector(2174145,23); exponent <= conv_std_logic_vector(219,8); WHEN "1000001" => mantissa <= conv_std_logic_vector(5967662,23); exponent <= conv_std_logic_vector(220,8); WHEN "1000010" => mantissa <= conv_std_logic_vector(1367489,23); exponent <= conv_std_logic_vector(222,8); WHEN "1000011" => mantissa <= conv_std_logic_vector(4871303,23); exponent <= conv_std_logic_vector(223,8); WHEN "1000100" => mantissa <= conv_std_logic_vector(622436,23); exponent <= conv_std_logic_vector(225,8); WHEN "1000101" => mantissa <= conv_std_logic_vector(3858670,23); exponent <= conv_std_logic_vector(226,8); WHEN "1000110" => mantissa <= conv_std_logic_vector(8257169,23); exponent <= conv_std_logic_vector(227,8); WHEN "1000111" => mantissa <= conv_std_logic_vector(2923370,23); exponent <= conv_std_logic_vector(229,8); WHEN "1001000" => mantissa <= conv_std_logic_vector(6985964,23); exponent <= conv_std_logic_vector(230,8); WHEN "1001001" => mantissa <= conv_std_logic_vector(2059497,23); exponent <= conv_std_logic_vector(232,8); WHEN "1001010" => mantissa <= conv_std_logic_vector(5811839,23); exponent <= conv_std_logic_vector(233,8); WHEN "1001011" => mantissa <= conv_std_logic_vector(1261596,23); exponent <= conv_std_logic_vector(235,8); WHEN "1001100" => mantissa <= conv_std_logic_vector(4727380,23); exponent <= conv_std_logic_vector(236,8); WHEN "1001101" => mantissa <= conv_std_logic_vector(524630,23); exponent <= conv_std_logic_vector(238,8); WHEN "1001110" => mantissa <= conv_std_logic_vector(3725738,23); exponent <= conv_std_logic_vector(239,8); WHEN "1001111" => mantissa <= conv_std_logic_vector(8076495,23); exponent <= conv_std_logic_vector(240,8); WHEN "1010000" => mantissa <= conv_std_logic_vector(2800590,23); exponent <= conv_std_logic_vector(242,8); WHEN "1010001" => mantissa <= conv_std_logic_vector(6819089,23); exponent <= conv_std_logic_vector(243,8); WHEN "1010010" => mantissa <= conv_std_logic_vector(1946093,23); exponent <= conv_std_logic_vector(245,8); WHEN "1010011" => mantissa <= conv_std_logic_vector(5657707,23); exponent <= conv_std_logic_vector(246,8); WHEN "1010100" => mantissa <= conv_std_logic_vector(1156853,23); exponent <= conv_std_logic_vector(248,8); WHEN "1010101" => mantissa <= conv_std_logic_vector(4585019,23); exponent <= conv_std_logic_vector(249,8); WHEN "1010110" => mantissa <= conv_std_logic_vector(427885,23); exponent <= conv_std_logic_vector(251,8); WHEN "1010111" => mantissa <= conv_std_logic_vector(3594249,23); exponent <= conv_std_logic_vector(252,8); WHEN "1011000" => mantissa <= conv_std_logic_vector(7897783,23); exponent <= conv_std_logic_vector(253,8); WHEN "1011001" => mantissa <= conv_std_logic_vector(2679142,23); exponent <= conv_std_logic_vector(255,8); WHEN others => mantissa <= conv_std_logic_vector(0,23); exponent <= conv_std_logic_vector(0,8); END CASE; END PROCESS; END rtl;
-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_EXPLUTPOS.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_explutpos IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 1); mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1) ); END fp_explutpos; ARCHITECTURE rtl OF fp_explutpos IS BEGIN pca: PROCESS (address) BEGIN CASE address IS WHEN "0000000" => mantissa <= conv_std_logic_vector(0,23); exponent <= conv_std_logic_vector(127,8); WHEN "0000001" => mantissa <= conv_std_logic_vector(3012692,23); exponent <= conv_std_logic_vector(128,8); WHEN "0000010" => mantissa <= conv_std_logic_vector(7107366,23); exponent <= conv_std_logic_vector(129,8); WHEN "0000011" => mantissa <= conv_std_logic_vector(2141998,23); exponent <= conv_std_logic_vector(131,8); WHEN "0000100" => mantissa <= conv_std_logic_vector(5923969,23); exponent <= conv_std_logic_vector(132,8); WHEN "0000101" => mantissa <= conv_std_logic_vector(1337797,23); exponent <= conv_std_logic_vector(134,8); WHEN "0000110" => mantissa <= conv_std_logic_vector(4830947,23); exponent <= conv_std_logic_vector(135,8); WHEN "0000111" => mantissa <= conv_std_logic_vector(595011,23); exponent <= conv_std_logic_vector(137,8); WHEN "0001000" => mantissa <= conv_std_logic_vector(3821396,23); exponent <= conv_std_logic_vector(138,8); WHEN "0001001" => mantissa <= conv_std_logic_vector(8206508,23); exponent <= conv_std_logic_vector(139,8); WHEN "0001010" => mantissa <= conv_std_logic_vector(2888942,23); exponent <= conv_std_logic_vector(141,8); WHEN "0001011" => mantissa <= conv_std_logic_vector(6939172,23); exponent <= conv_std_logic_vector(142,8); WHEN "0001100" => mantissa <= conv_std_logic_vector(2027699,23); exponent <= conv_std_logic_vector(144,8); WHEN "0001101" => mantissa <= conv_std_logic_vector(5768621,23); exponent <= conv_std_logic_vector(145,8); WHEN "0001110" => mantissa <= conv_std_logic_vector(1232226,23); exponent <= conv_std_logic_vector(147,8); WHEN "0001111" => mantissa <= conv_std_logic_vector(4687461,23); exponent <= conv_std_logic_vector(148,8); WHEN "0010000" => mantissa <= conv_std_logic_vector(497503,23); exponent <= conv_std_logic_vector(150,8); WHEN "0010001" => mantissa <= conv_std_logic_vector(3688868,23); exponent <= conv_std_logic_vector(151,8); WHEN "0010010" => mantissa <= conv_std_logic_vector(8026384,23); exponent <= conv_std_logic_vector(152,8); WHEN "0010011" => mantissa <= conv_std_logic_vector(2766536,23); exponent <= conv_std_logic_vector(154,8); WHEN "0010100" => mantissa <= conv_std_logic_vector(6772804,23); exponent <= conv_std_logic_vector(155,8); WHEN "0010101" => mantissa <= conv_std_logic_vector(1914640,23); exponent <= conv_std_logic_vector(157,8); WHEN "0010110" => mantissa <= conv_std_logic_vector(5614958,23); exponent <= conv_std_logic_vector(158,8); WHEN "0010111" => mantissa <= conv_std_logic_vector(1127802,23); exponent <= conv_std_logic_vector(160,8); WHEN "0011000" => mantissa <= conv_std_logic_vector(4545534,23); exponent <= conv_std_logic_vector(161,8); WHEN "0011001" => mantissa <= conv_std_logic_vector(401053,23); exponent <= conv_std_logic_vector(163,8); WHEN "0011010" => mantissa <= conv_std_logic_vector(3557779,23); exponent <= conv_std_logic_vector(164,8); WHEN "0011011" => mantissa <= conv_std_logic_vector(7848216,23); exponent <= conv_std_logic_vector(165,8); WHEN "0011100" => mantissa <= conv_std_logic_vector(2645458,23); exponent <= conv_std_logic_vector(167,8); WHEN "0011101" => mantissa <= conv_std_logic_vector(6608242,23); exponent <= conv_std_logic_vector(168,8); WHEN "0011110" => mantissa <= conv_std_logic_vector(1802808,23); exponent <= conv_std_logic_vector(170,8); WHEN "0011111" => mantissa <= conv_std_logic_vector(5462963,23); exponent <= conv_std_logic_vector(171,8); WHEN "0100000" => mantissa <= conv_std_logic_vector(1024510,23); exponent <= conv_std_logic_vector(173,8); WHEN "0100001" => mantissa <= conv_std_logic_vector(4405146,23); exponent <= conv_std_logic_vector(174,8); WHEN "0100010" => mantissa <= conv_std_logic_vector(305649,23); exponent <= conv_std_logic_vector(176,8); WHEN "0100011" => mantissa <= conv_std_logic_vector(3428113,23); exponent <= conv_std_logic_vector(177,8); WHEN "0100100" => mantissa <= conv_std_logic_vector(7671981,23); exponent <= conv_std_logic_vector(178,8); WHEN "0100101" => mantissa <= conv_std_logic_vector(2525694,23); exponent <= conv_std_logic_vector(180,8); WHEN "0100110" => mantissa <= conv_std_logic_vector(6445466,23); exponent <= conv_std_logic_vector(181,8); WHEN "0100111" => mantissa <= conv_std_logic_vector(1692191,23); exponent <= conv_std_logic_vector(183,8); WHEN "0101000" => mantissa <= conv_std_logic_vector(5312618,23); exponent <= conv_std_logic_vector(184,8); WHEN "0101001" => mantissa <= conv_std_logic_vector(922340,23); exponent <= conv_std_logic_vector(186,8); WHEN "0101010" => mantissa <= conv_std_logic_vector(4266283,23); exponent <= conv_std_logic_vector(187,8); WHEN "0101011" => mantissa <= conv_std_logic_vector(211282,23); exponent <= conv_std_logic_vector(189,8); WHEN "0101100" => mantissa <= conv_std_logic_vector(3299854,23); exponent <= conv_std_logic_vector(190,8); WHEN "0101101" => mantissa <= conv_std_logic_vector(7497659,23); exponent <= conv_std_logic_vector(191,8); WHEN "0101110" => mantissa <= conv_std_logic_vector(2407230,23); exponent <= conv_std_logic_vector(193,8); WHEN "0101111" => mantissa <= conv_std_logic_vector(6284457,23); exponent <= conv_std_logic_vector(194,8); WHEN "0110000" => mantissa <= conv_std_logic_vector(1582773,23); exponent <= conv_std_logic_vector(196,8); WHEN "0110001" => mantissa <= conv_std_logic_vector(5163905,23); exponent <= conv_std_logic_vector(197,8); WHEN "0110010" => mantissa <= conv_std_logic_vector(821279,23); exponent <= conv_std_logic_vector(199,8); WHEN "0110011" => mantissa <= conv_std_logic_vector(4128926,23); exponent <= conv_std_logic_vector(200,8); WHEN "0110100" => mantissa <= conv_std_logic_vector(117939,23); exponent <= conv_std_logic_vector(202,8); WHEN "0110101" => mantissa <= conv_std_logic_vector(3172987,23); exponent <= conv_std_logic_vector(203,8); WHEN "0110110" => mantissa <= conv_std_logic_vector(7325229,23); exponent <= conv_std_logic_vector(204,8); WHEN "0110111" => mantissa <= conv_std_logic_vector(2290052,23); exponent <= conv_std_logic_vector(206,8); WHEN "0111000" => mantissa <= conv_std_logic_vector(6125195,23); exponent <= conv_std_logic_vector(207,8); WHEN "0111001" => mantissa <= conv_std_logic_vector(1474544,23); exponent <= conv_std_logic_vector(209,8); WHEN "0111010" => mantissa <= conv_std_logic_vector(5016805,23); exponent <= conv_std_logic_vector(210,8); WHEN "0111011" => mantissa <= conv_std_logic_vector(721315,23); exponent <= conv_std_logic_vector(212,8); WHEN "0111100" => mantissa <= conv_std_logic_vector(3993061,23); exponent <= conv_std_logic_vector(213,8); WHEN "0111101" => mantissa <= conv_std_logic_vector(25608,23); exponent <= conv_std_logic_vector(215,8); WHEN "0111110" => mantissa <= conv_std_logic_vector(3047498,23); exponent <= conv_std_logic_vector(216,8); WHEN "0111111" => mantissa <= conv_std_logic_vector(7154671,23); exponent <= conv_std_logic_vector(217,8); WHEN "1000000" => mantissa <= conv_std_logic_vector(2174145,23); exponent <= conv_std_logic_vector(219,8); WHEN "1000001" => mantissa <= conv_std_logic_vector(5967662,23); exponent <= conv_std_logic_vector(220,8); WHEN "1000010" => mantissa <= conv_std_logic_vector(1367489,23); exponent <= conv_std_logic_vector(222,8); WHEN "1000011" => mantissa <= conv_std_logic_vector(4871303,23); exponent <= conv_std_logic_vector(223,8); WHEN "1000100" => mantissa <= conv_std_logic_vector(622436,23); exponent <= conv_std_logic_vector(225,8); WHEN "1000101" => mantissa <= conv_std_logic_vector(3858670,23); exponent <= conv_std_logic_vector(226,8); WHEN "1000110" => mantissa <= conv_std_logic_vector(8257169,23); exponent <= conv_std_logic_vector(227,8); WHEN "1000111" => mantissa <= conv_std_logic_vector(2923370,23); exponent <= conv_std_logic_vector(229,8); WHEN "1001000" => mantissa <= conv_std_logic_vector(6985964,23); exponent <= conv_std_logic_vector(230,8); WHEN "1001001" => mantissa <= conv_std_logic_vector(2059497,23); exponent <= conv_std_logic_vector(232,8); WHEN "1001010" => mantissa <= conv_std_logic_vector(5811839,23); exponent <= conv_std_logic_vector(233,8); WHEN "1001011" => mantissa <= conv_std_logic_vector(1261596,23); exponent <= conv_std_logic_vector(235,8); WHEN "1001100" => mantissa <= conv_std_logic_vector(4727380,23); exponent <= conv_std_logic_vector(236,8); WHEN "1001101" => mantissa <= conv_std_logic_vector(524630,23); exponent <= conv_std_logic_vector(238,8); WHEN "1001110" => mantissa <= conv_std_logic_vector(3725738,23); exponent <= conv_std_logic_vector(239,8); WHEN "1001111" => mantissa <= conv_std_logic_vector(8076495,23); exponent <= conv_std_logic_vector(240,8); WHEN "1010000" => mantissa <= conv_std_logic_vector(2800590,23); exponent <= conv_std_logic_vector(242,8); WHEN "1010001" => mantissa <= conv_std_logic_vector(6819089,23); exponent <= conv_std_logic_vector(243,8); WHEN "1010010" => mantissa <= conv_std_logic_vector(1946093,23); exponent <= conv_std_logic_vector(245,8); WHEN "1010011" => mantissa <= conv_std_logic_vector(5657707,23); exponent <= conv_std_logic_vector(246,8); WHEN "1010100" => mantissa <= conv_std_logic_vector(1156853,23); exponent <= conv_std_logic_vector(248,8); WHEN "1010101" => mantissa <= conv_std_logic_vector(4585019,23); exponent <= conv_std_logic_vector(249,8); WHEN "1010110" => mantissa <= conv_std_logic_vector(427885,23); exponent <= conv_std_logic_vector(251,8); WHEN "1010111" => mantissa <= conv_std_logic_vector(3594249,23); exponent <= conv_std_logic_vector(252,8); WHEN "1011000" => mantissa <= conv_std_logic_vector(7897783,23); exponent <= conv_std_logic_vector(253,8); WHEN "1011001" => mantissa <= conv_std_logic_vector(2679142,23); exponent <= conv_std_logic_vector(255,8); WHEN others => mantissa <= conv_std_logic_vector(0,23); exponent <= conv_std_logic_vector(0,8); END CASE; END PROCESS; END rtl;
-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_EXPLUTPOS.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_explutpos IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 1); mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1) ); END fp_explutpos; ARCHITECTURE rtl OF fp_explutpos IS BEGIN pca: PROCESS (address) BEGIN CASE address IS WHEN "0000000" => mantissa <= conv_std_logic_vector(0,23); exponent <= conv_std_logic_vector(127,8); WHEN "0000001" => mantissa <= conv_std_logic_vector(3012692,23); exponent <= conv_std_logic_vector(128,8); WHEN "0000010" => mantissa <= conv_std_logic_vector(7107366,23); exponent <= conv_std_logic_vector(129,8); WHEN "0000011" => mantissa <= conv_std_logic_vector(2141998,23); exponent <= conv_std_logic_vector(131,8); WHEN "0000100" => mantissa <= conv_std_logic_vector(5923969,23); exponent <= conv_std_logic_vector(132,8); WHEN "0000101" => mantissa <= conv_std_logic_vector(1337797,23); exponent <= conv_std_logic_vector(134,8); WHEN "0000110" => mantissa <= conv_std_logic_vector(4830947,23); exponent <= conv_std_logic_vector(135,8); WHEN "0000111" => mantissa <= conv_std_logic_vector(595011,23); exponent <= conv_std_logic_vector(137,8); WHEN "0001000" => mantissa <= conv_std_logic_vector(3821396,23); exponent <= conv_std_logic_vector(138,8); WHEN "0001001" => mantissa <= conv_std_logic_vector(8206508,23); exponent <= conv_std_logic_vector(139,8); WHEN "0001010" => mantissa <= conv_std_logic_vector(2888942,23); exponent <= conv_std_logic_vector(141,8); WHEN "0001011" => mantissa <= conv_std_logic_vector(6939172,23); exponent <= conv_std_logic_vector(142,8); WHEN "0001100" => mantissa <= conv_std_logic_vector(2027699,23); exponent <= conv_std_logic_vector(144,8); WHEN "0001101" => mantissa <= conv_std_logic_vector(5768621,23); exponent <= conv_std_logic_vector(145,8); WHEN "0001110" => mantissa <= conv_std_logic_vector(1232226,23); exponent <= conv_std_logic_vector(147,8); WHEN "0001111" => mantissa <= conv_std_logic_vector(4687461,23); exponent <= conv_std_logic_vector(148,8); WHEN "0010000" => mantissa <= conv_std_logic_vector(497503,23); exponent <= conv_std_logic_vector(150,8); WHEN "0010001" => mantissa <= conv_std_logic_vector(3688868,23); exponent <= conv_std_logic_vector(151,8); WHEN "0010010" => mantissa <= conv_std_logic_vector(8026384,23); exponent <= conv_std_logic_vector(152,8); WHEN "0010011" => mantissa <= conv_std_logic_vector(2766536,23); exponent <= conv_std_logic_vector(154,8); WHEN "0010100" => mantissa <= conv_std_logic_vector(6772804,23); exponent <= conv_std_logic_vector(155,8); WHEN "0010101" => mantissa <= conv_std_logic_vector(1914640,23); exponent <= conv_std_logic_vector(157,8); WHEN "0010110" => mantissa <= conv_std_logic_vector(5614958,23); exponent <= conv_std_logic_vector(158,8); WHEN "0010111" => mantissa <= conv_std_logic_vector(1127802,23); exponent <= conv_std_logic_vector(160,8); WHEN "0011000" => mantissa <= conv_std_logic_vector(4545534,23); exponent <= conv_std_logic_vector(161,8); WHEN "0011001" => mantissa <= conv_std_logic_vector(401053,23); exponent <= conv_std_logic_vector(163,8); WHEN "0011010" => mantissa <= conv_std_logic_vector(3557779,23); exponent <= conv_std_logic_vector(164,8); WHEN "0011011" => mantissa <= conv_std_logic_vector(7848216,23); exponent <= conv_std_logic_vector(165,8); WHEN "0011100" => mantissa <= conv_std_logic_vector(2645458,23); exponent <= conv_std_logic_vector(167,8); WHEN "0011101" => mantissa <= conv_std_logic_vector(6608242,23); exponent <= conv_std_logic_vector(168,8); WHEN "0011110" => mantissa <= conv_std_logic_vector(1802808,23); exponent <= conv_std_logic_vector(170,8); WHEN "0011111" => mantissa <= conv_std_logic_vector(5462963,23); exponent <= conv_std_logic_vector(171,8); WHEN "0100000" => mantissa <= conv_std_logic_vector(1024510,23); exponent <= conv_std_logic_vector(173,8); WHEN "0100001" => mantissa <= conv_std_logic_vector(4405146,23); exponent <= conv_std_logic_vector(174,8); WHEN "0100010" => mantissa <= conv_std_logic_vector(305649,23); exponent <= conv_std_logic_vector(176,8); WHEN "0100011" => mantissa <= conv_std_logic_vector(3428113,23); exponent <= conv_std_logic_vector(177,8); WHEN "0100100" => mantissa <= conv_std_logic_vector(7671981,23); exponent <= conv_std_logic_vector(178,8); WHEN "0100101" => mantissa <= conv_std_logic_vector(2525694,23); exponent <= conv_std_logic_vector(180,8); WHEN "0100110" => mantissa <= conv_std_logic_vector(6445466,23); exponent <= conv_std_logic_vector(181,8); WHEN "0100111" => mantissa <= conv_std_logic_vector(1692191,23); exponent <= conv_std_logic_vector(183,8); WHEN "0101000" => mantissa <= conv_std_logic_vector(5312618,23); exponent <= conv_std_logic_vector(184,8); WHEN "0101001" => mantissa <= conv_std_logic_vector(922340,23); exponent <= conv_std_logic_vector(186,8); WHEN "0101010" => mantissa <= conv_std_logic_vector(4266283,23); exponent <= conv_std_logic_vector(187,8); WHEN "0101011" => mantissa <= conv_std_logic_vector(211282,23); exponent <= conv_std_logic_vector(189,8); WHEN "0101100" => mantissa <= conv_std_logic_vector(3299854,23); exponent <= conv_std_logic_vector(190,8); WHEN "0101101" => mantissa <= conv_std_logic_vector(7497659,23); exponent <= conv_std_logic_vector(191,8); WHEN "0101110" => mantissa <= conv_std_logic_vector(2407230,23); exponent <= conv_std_logic_vector(193,8); WHEN "0101111" => mantissa <= conv_std_logic_vector(6284457,23); exponent <= conv_std_logic_vector(194,8); WHEN "0110000" => mantissa <= conv_std_logic_vector(1582773,23); exponent <= conv_std_logic_vector(196,8); WHEN "0110001" => mantissa <= conv_std_logic_vector(5163905,23); exponent <= conv_std_logic_vector(197,8); WHEN "0110010" => mantissa <= conv_std_logic_vector(821279,23); exponent <= conv_std_logic_vector(199,8); WHEN "0110011" => mantissa <= conv_std_logic_vector(4128926,23); exponent <= conv_std_logic_vector(200,8); WHEN "0110100" => mantissa <= conv_std_logic_vector(117939,23); exponent <= conv_std_logic_vector(202,8); WHEN "0110101" => mantissa <= conv_std_logic_vector(3172987,23); exponent <= conv_std_logic_vector(203,8); WHEN "0110110" => mantissa <= conv_std_logic_vector(7325229,23); exponent <= conv_std_logic_vector(204,8); WHEN "0110111" => mantissa <= conv_std_logic_vector(2290052,23); exponent <= conv_std_logic_vector(206,8); WHEN "0111000" => mantissa <= conv_std_logic_vector(6125195,23); exponent <= conv_std_logic_vector(207,8); WHEN "0111001" => mantissa <= conv_std_logic_vector(1474544,23); exponent <= conv_std_logic_vector(209,8); WHEN "0111010" => mantissa <= conv_std_logic_vector(5016805,23); exponent <= conv_std_logic_vector(210,8); WHEN "0111011" => mantissa <= conv_std_logic_vector(721315,23); exponent <= conv_std_logic_vector(212,8); WHEN "0111100" => mantissa <= conv_std_logic_vector(3993061,23); exponent <= conv_std_logic_vector(213,8); WHEN "0111101" => mantissa <= conv_std_logic_vector(25608,23); exponent <= conv_std_logic_vector(215,8); WHEN "0111110" => mantissa <= conv_std_logic_vector(3047498,23); exponent <= conv_std_logic_vector(216,8); WHEN "0111111" => mantissa <= conv_std_logic_vector(7154671,23); exponent <= conv_std_logic_vector(217,8); WHEN "1000000" => mantissa <= conv_std_logic_vector(2174145,23); exponent <= conv_std_logic_vector(219,8); WHEN "1000001" => mantissa <= conv_std_logic_vector(5967662,23); exponent <= conv_std_logic_vector(220,8); WHEN "1000010" => mantissa <= conv_std_logic_vector(1367489,23); exponent <= conv_std_logic_vector(222,8); WHEN "1000011" => mantissa <= conv_std_logic_vector(4871303,23); exponent <= conv_std_logic_vector(223,8); WHEN "1000100" => mantissa <= conv_std_logic_vector(622436,23); exponent <= conv_std_logic_vector(225,8); WHEN "1000101" => mantissa <= conv_std_logic_vector(3858670,23); exponent <= conv_std_logic_vector(226,8); WHEN "1000110" => mantissa <= conv_std_logic_vector(8257169,23); exponent <= conv_std_logic_vector(227,8); WHEN "1000111" => mantissa <= conv_std_logic_vector(2923370,23); exponent <= conv_std_logic_vector(229,8); WHEN "1001000" => mantissa <= conv_std_logic_vector(6985964,23); exponent <= conv_std_logic_vector(230,8); WHEN "1001001" => mantissa <= conv_std_logic_vector(2059497,23); exponent <= conv_std_logic_vector(232,8); WHEN "1001010" => mantissa <= conv_std_logic_vector(5811839,23); exponent <= conv_std_logic_vector(233,8); WHEN "1001011" => mantissa <= conv_std_logic_vector(1261596,23); exponent <= conv_std_logic_vector(235,8); WHEN "1001100" => mantissa <= conv_std_logic_vector(4727380,23); exponent <= conv_std_logic_vector(236,8); WHEN "1001101" => mantissa <= conv_std_logic_vector(524630,23); exponent <= conv_std_logic_vector(238,8); WHEN "1001110" => mantissa <= conv_std_logic_vector(3725738,23); exponent <= conv_std_logic_vector(239,8); WHEN "1001111" => mantissa <= conv_std_logic_vector(8076495,23); exponent <= conv_std_logic_vector(240,8); WHEN "1010000" => mantissa <= conv_std_logic_vector(2800590,23); exponent <= conv_std_logic_vector(242,8); WHEN "1010001" => mantissa <= conv_std_logic_vector(6819089,23); exponent <= conv_std_logic_vector(243,8); WHEN "1010010" => mantissa <= conv_std_logic_vector(1946093,23); exponent <= conv_std_logic_vector(245,8); WHEN "1010011" => mantissa <= conv_std_logic_vector(5657707,23); exponent <= conv_std_logic_vector(246,8); WHEN "1010100" => mantissa <= conv_std_logic_vector(1156853,23); exponent <= conv_std_logic_vector(248,8); WHEN "1010101" => mantissa <= conv_std_logic_vector(4585019,23); exponent <= conv_std_logic_vector(249,8); WHEN "1010110" => mantissa <= conv_std_logic_vector(427885,23); exponent <= conv_std_logic_vector(251,8); WHEN "1010111" => mantissa <= conv_std_logic_vector(3594249,23); exponent <= conv_std_logic_vector(252,8); WHEN "1011000" => mantissa <= conv_std_logic_vector(7897783,23); exponent <= conv_std_logic_vector(253,8); WHEN "1011001" => mantissa <= conv_std_logic_vector(2679142,23); exponent <= conv_std_logic_vector(255,8); WHEN others => mantissa <= conv_std_logic_vector(0,23); exponent <= conv_std_logic_vector(0,8); END CASE; END PROCESS; END rtl;
-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_EXPLUTPOS.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_explutpos IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 1); mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1) ); END fp_explutpos; ARCHITECTURE rtl OF fp_explutpos IS BEGIN pca: PROCESS (address) BEGIN CASE address IS WHEN "0000000" => mantissa <= conv_std_logic_vector(0,23); exponent <= conv_std_logic_vector(127,8); WHEN "0000001" => mantissa <= conv_std_logic_vector(3012692,23); exponent <= conv_std_logic_vector(128,8); WHEN "0000010" => mantissa <= conv_std_logic_vector(7107366,23); exponent <= conv_std_logic_vector(129,8); WHEN "0000011" => mantissa <= conv_std_logic_vector(2141998,23); exponent <= conv_std_logic_vector(131,8); WHEN "0000100" => mantissa <= conv_std_logic_vector(5923969,23); exponent <= conv_std_logic_vector(132,8); WHEN "0000101" => mantissa <= conv_std_logic_vector(1337797,23); exponent <= conv_std_logic_vector(134,8); WHEN "0000110" => mantissa <= conv_std_logic_vector(4830947,23); exponent <= conv_std_logic_vector(135,8); WHEN "0000111" => mantissa <= conv_std_logic_vector(595011,23); exponent <= conv_std_logic_vector(137,8); WHEN "0001000" => mantissa <= conv_std_logic_vector(3821396,23); exponent <= conv_std_logic_vector(138,8); WHEN "0001001" => mantissa <= conv_std_logic_vector(8206508,23); exponent <= conv_std_logic_vector(139,8); WHEN "0001010" => mantissa <= conv_std_logic_vector(2888942,23); exponent <= conv_std_logic_vector(141,8); WHEN "0001011" => mantissa <= conv_std_logic_vector(6939172,23); exponent <= conv_std_logic_vector(142,8); WHEN "0001100" => mantissa <= conv_std_logic_vector(2027699,23); exponent <= conv_std_logic_vector(144,8); WHEN "0001101" => mantissa <= conv_std_logic_vector(5768621,23); exponent <= conv_std_logic_vector(145,8); WHEN "0001110" => mantissa <= conv_std_logic_vector(1232226,23); exponent <= conv_std_logic_vector(147,8); WHEN "0001111" => mantissa <= conv_std_logic_vector(4687461,23); exponent <= conv_std_logic_vector(148,8); WHEN "0010000" => mantissa <= conv_std_logic_vector(497503,23); exponent <= conv_std_logic_vector(150,8); WHEN "0010001" => mantissa <= conv_std_logic_vector(3688868,23); exponent <= conv_std_logic_vector(151,8); WHEN "0010010" => mantissa <= conv_std_logic_vector(8026384,23); exponent <= conv_std_logic_vector(152,8); WHEN "0010011" => mantissa <= conv_std_logic_vector(2766536,23); exponent <= conv_std_logic_vector(154,8); WHEN "0010100" => mantissa <= conv_std_logic_vector(6772804,23); exponent <= conv_std_logic_vector(155,8); WHEN "0010101" => mantissa <= conv_std_logic_vector(1914640,23); exponent <= conv_std_logic_vector(157,8); WHEN "0010110" => mantissa <= conv_std_logic_vector(5614958,23); exponent <= conv_std_logic_vector(158,8); WHEN "0010111" => mantissa <= conv_std_logic_vector(1127802,23); exponent <= conv_std_logic_vector(160,8); WHEN "0011000" => mantissa <= conv_std_logic_vector(4545534,23); exponent <= conv_std_logic_vector(161,8); WHEN "0011001" => mantissa <= conv_std_logic_vector(401053,23); exponent <= conv_std_logic_vector(163,8); WHEN "0011010" => mantissa <= conv_std_logic_vector(3557779,23); exponent <= conv_std_logic_vector(164,8); WHEN "0011011" => mantissa <= conv_std_logic_vector(7848216,23); exponent <= conv_std_logic_vector(165,8); WHEN "0011100" => mantissa <= conv_std_logic_vector(2645458,23); exponent <= conv_std_logic_vector(167,8); WHEN "0011101" => mantissa <= conv_std_logic_vector(6608242,23); exponent <= conv_std_logic_vector(168,8); WHEN "0011110" => mantissa <= conv_std_logic_vector(1802808,23); exponent <= conv_std_logic_vector(170,8); WHEN "0011111" => mantissa <= conv_std_logic_vector(5462963,23); exponent <= conv_std_logic_vector(171,8); WHEN "0100000" => mantissa <= conv_std_logic_vector(1024510,23); exponent <= conv_std_logic_vector(173,8); WHEN "0100001" => mantissa <= conv_std_logic_vector(4405146,23); exponent <= conv_std_logic_vector(174,8); WHEN "0100010" => mantissa <= conv_std_logic_vector(305649,23); exponent <= conv_std_logic_vector(176,8); WHEN "0100011" => mantissa <= conv_std_logic_vector(3428113,23); exponent <= conv_std_logic_vector(177,8); WHEN "0100100" => mantissa <= conv_std_logic_vector(7671981,23); exponent <= conv_std_logic_vector(178,8); WHEN "0100101" => mantissa <= conv_std_logic_vector(2525694,23); exponent <= conv_std_logic_vector(180,8); WHEN "0100110" => mantissa <= conv_std_logic_vector(6445466,23); exponent <= conv_std_logic_vector(181,8); WHEN "0100111" => mantissa <= conv_std_logic_vector(1692191,23); exponent <= conv_std_logic_vector(183,8); WHEN "0101000" => mantissa <= conv_std_logic_vector(5312618,23); exponent <= conv_std_logic_vector(184,8); WHEN "0101001" => mantissa <= conv_std_logic_vector(922340,23); exponent <= conv_std_logic_vector(186,8); WHEN "0101010" => mantissa <= conv_std_logic_vector(4266283,23); exponent <= conv_std_logic_vector(187,8); WHEN "0101011" => mantissa <= conv_std_logic_vector(211282,23); exponent <= conv_std_logic_vector(189,8); WHEN "0101100" => mantissa <= conv_std_logic_vector(3299854,23); exponent <= conv_std_logic_vector(190,8); WHEN "0101101" => mantissa <= conv_std_logic_vector(7497659,23); exponent <= conv_std_logic_vector(191,8); WHEN "0101110" => mantissa <= conv_std_logic_vector(2407230,23); exponent <= conv_std_logic_vector(193,8); WHEN "0101111" => mantissa <= conv_std_logic_vector(6284457,23); exponent <= conv_std_logic_vector(194,8); WHEN "0110000" => mantissa <= conv_std_logic_vector(1582773,23); exponent <= conv_std_logic_vector(196,8); WHEN "0110001" => mantissa <= conv_std_logic_vector(5163905,23); exponent <= conv_std_logic_vector(197,8); WHEN "0110010" => mantissa <= conv_std_logic_vector(821279,23); exponent <= conv_std_logic_vector(199,8); WHEN "0110011" => mantissa <= conv_std_logic_vector(4128926,23); exponent <= conv_std_logic_vector(200,8); WHEN "0110100" => mantissa <= conv_std_logic_vector(117939,23); exponent <= conv_std_logic_vector(202,8); WHEN "0110101" => mantissa <= conv_std_logic_vector(3172987,23); exponent <= conv_std_logic_vector(203,8); WHEN "0110110" => mantissa <= conv_std_logic_vector(7325229,23); exponent <= conv_std_logic_vector(204,8); WHEN "0110111" => mantissa <= conv_std_logic_vector(2290052,23); exponent <= conv_std_logic_vector(206,8); WHEN "0111000" => mantissa <= conv_std_logic_vector(6125195,23); exponent <= conv_std_logic_vector(207,8); WHEN "0111001" => mantissa <= conv_std_logic_vector(1474544,23); exponent <= conv_std_logic_vector(209,8); WHEN "0111010" => mantissa <= conv_std_logic_vector(5016805,23); exponent <= conv_std_logic_vector(210,8); WHEN "0111011" => mantissa <= conv_std_logic_vector(721315,23); exponent <= conv_std_logic_vector(212,8); WHEN "0111100" => mantissa <= conv_std_logic_vector(3993061,23); exponent <= conv_std_logic_vector(213,8); WHEN "0111101" => mantissa <= conv_std_logic_vector(25608,23); exponent <= conv_std_logic_vector(215,8); WHEN "0111110" => mantissa <= conv_std_logic_vector(3047498,23); exponent <= conv_std_logic_vector(216,8); WHEN "0111111" => mantissa <= conv_std_logic_vector(7154671,23); exponent <= conv_std_logic_vector(217,8); WHEN "1000000" => mantissa <= conv_std_logic_vector(2174145,23); exponent <= conv_std_logic_vector(219,8); WHEN "1000001" => mantissa <= conv_std_logic_vector(5967662,23); exponent <= conv_std_logic_vector(220,8); WHEN "1000010" => mantissa <= conv_std_logic_vector(1367489,23); exponent <= conv_std_logic_vector(222,8); WHEN "1000011" => mantissa <= conv_std_logic_vector(4871303,23); exponent <= conv_std_logic_vector(223,8); WHEN "1000100" => mantissa <= conv_std_logic_vector(622436,23); exponent <= conv_std_logic_vector(225,8); WHEN "1000101" => mantissa <= conv_std_logic_vector(3858670,23); exponent <= conv_std_logic_vector(226,8); WHEN "1000110" => mantissa <= conv_std_logic_vector(8257169,23); exponent <= conv_std_logic_vector(227,8); WHEN "1000111" => mantissa <= conv_std_logic_vector(2923370,23); exponent <= conv_std_logic_vector(229,8); WHEN "1001000" => mantissa <= conv_std_logic_vector(6985964,23); exponent <= conv_std_logic_vector(230,8); WHEN "1001001" => mantissa <= conv_std_logic_vector(2059497,23); exponent <= conv_std_logic_vector(232,8); WHEN "1001010" => mantissa <= conv_std_logic_vector(5811839,23); exponent <= conv_std_logic_vector(233,8); WHEN "1001011" => mantissa <= conv_std_logic_vector(1261596,23); exponent <= conv_std_logic_vector(235,8); WHEN "1001100" => mantissa <= conv_std_logic_vector(4727380,23); exponent <= conv_std_logic_vector(236,8); WHEN "1001101" => mantissa <= conv_std_logic_vector(524630,23); exponent <= conv_std_logic_vector(238,8); WHEN "1001110" => mantissa <= conv_std_logic_vector(3725738,23); exponent <= conv_std_logic_vector(239,8); WHEN "1001111" => mantissa <= conv_std_logic_vector(8076495,23); exponent <= conv_std_logic_vector(240,8); WHEN "1010000" => mantissa <= conv_std_logic_vector(2800590,23); exponent <= conv_std_logic_vector(242,8); WHEN "1010001" => mantissa <= conv_std_logic_vector(6819089,23); exponent <= conv_std_logic_vector(243,8); WHEN "1010010" => mantissa <= conv_std_logic_vector(1946093,23); exponent <= conv_std_logic_vector(245,8); WHEN "1010011" => mantissa <= conv_std_logic_vector(5657707,23); exponent <= conv_std_logic_vector(246,8); WHEN "1010100" => mantissa <= conv_std_logic_vector(1156853,23); exponent <= conv_std_logic_vector(248,8); WHEN "1010101" => mantissa <= conv_std_logic_vector(4585019,23); exponent <= conv_std_logic_vector(249,8); WHEN "1010110" => mantissa <= conv_std_logic_vector(427885,23); exponent <= conv_std_logic_vector(251,8); WHEN "1010111" => mantissa <= conv_std_logic_vector(3594249,23); exponent <= conv_std_logic_vector(252,8); WHEN "1011000" => mantissa <= conv_std_logic_vector(7897783,23); exponent <= conv_std_logic_vector(253,8); WHEN "1011001" => mantissa <= conv_std_logic_vector(2679142,23); exponent <= conv_std_logic_vector(255,8); WHEN others => mantissa <= conv_std_logic_vector(0,23); exponent <= conv_std_logic_vector(0,8); END CASE; END PROCESS; END rtl;