content stringlengths 1 1.04M ⌀ |
|---|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247a
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following con... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--libra... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- file: clock_manager_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue is
generic (N : natural := 3);
port (data : out signed(N-1 downto 0));
end issue;
architecture rtl of issue is
subtype my_type is signed(N-1 downto 0);
begin
data <= to_signed(1,my_type'length);
end architecture;... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: CLK4Hz
-- Project Name: CLOCK COUNTER
-- Target Devices: Spartan-3E
-- Tool v... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: CLK4Hz
-- Project Name: CLOCK COUNTER
-- Target Devices: Spartan-3E
-- Tool v... |
----------------------------------------------------------------------------------
-- Company: CPE233
-- Engineer: Jacob Hladky
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library unisim;
use unisim.vcomponents.all;
entity prog_ram is
... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 17:40:25 2017
-- Host : EffulgentTome running 64-bit major... |
------------------------------------------------------------------------------
-- radio_controller.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMIN... |
------------------------------------------------------------------------------
-- radio_controller.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMIN... |
------------------------------------------------------------------------------
-- Copyright (c) 2012 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Dmemory module (implements the data
-- memory for the MIPS computer)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY dmemory IS
PORT( read_data : OUT STD_LOGIC_VEC... |
LIBRARY ieee;
-- LIBRARY arithmetic;
PACKAGE BODY std_logic_arith IS
USE ieee.std_logic_1164.ALL;
-- USE arithmetic.utils.all;
-------------------------------------------------------------------
-- Local Types
-------------------------------------------------------------------
TYP... |
LIBRARY ieee;
-- LIBRARY arithmetic;
PACKAGE BODY std_logic_arith IS
USE ieee.std_logic_1164.ALL;
-- USE arithmetic.utils.all;
-------------------------------------------------------------------
-- Local Types
-------------------------------------------------------------------
TYP... |
LIBRARY ieee;
-- LIBRARY arithmetic;
PACKAGE BODY std_logic_arith IS
USE ieee.std_logic_1164.ALL;
-- USE arithmetic.utils.all;
-------------------------------------------------------------------
-- Local Types
-------------------------------------------------------------------
TYP... |
LIBRARY ieee;
-- LIBRARY arithmetic;
PACKAGE BODY std_logic_arith IS
USE ieee.std_logic_1164.ALL;
-- USE arithmetic.utils.all;
-------------------------------------------------------------------
-- Local Types
-------------------------------------------------------------------
TYP... |
LIBRARY ieee;
-- LIBRARY arithmetic;
PACKAGE BODY std_logic_arith IS
USE ieee.std_logic_1164.ALL;
-- USE arithmetic.utils.all;
-------------------------------------------------------------------
-- Local Types
-------------------------------------------------------------------
TYP... |
LIBRARY ieee;
-- LIBRARY arithmetic;
PACKAGE BODY std_logic_arith IS
USE ieee.std_logic_1164.ALL;
-- USE arithmetic.utils.all;
-------------------------------------------------------------------
-- Local Types
-------------------------------------------------------------------
TYP... |
LIBRARY ieee;
-- LIBRARY arithmetic;
PACKAGE BODY std_logic_arith IS
USE ieee.std_logic_1164.ALL;
-- USE arithmetic.utils.all;
-------------------------------------------------------------------
-- Local Types
-------------------------------------------------------------------
TYP... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity cse_jed is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end cse_jed;
architecture behaviour of cse_jed is
constant st0: std_logic_vector(3 downto 0) := "010... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: ... |
architecture a of e is
attribute foo : integer;
attribute foo of x : signal is 5;
attribute foo of x : component is 5;
attribute foo of x : label is 6;
attribute foo of x : type is 4;
begin
assert x'foo(5);
end architecture;
|
architecture a of e is
attribute foo : integer;
attribute foo of x : signal is 5;
attribute foo of x : component is 5;
attribute foo of x : label is 6;
attribute foo of x : type is 4;
begin
assert x'foo(5);
end architecture;
|
architecture a of e is
attribute foo : integer;
attribute foo of x : signal is 5;
attribute foo of x : component is 5;
attribute foo of x : label is 6;
attribute foo of x : type is 4;
begin
assert x'foo(5);
end architecture;
|
architecture a of e is
attribute foo : integer;
attribute foo of x : signal is 5;
attribute foo of x : component is 5;
attribute foo of x : label is 6;
attribute foo of x : type is 4;
begin
assert x'foo(5);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity fifo_control_unit is
port (
clkA : out std_logic;
clkB : out std_logic;
enA : out std_logic;
enB : out std_logic;
weA : out std_logic := '1';
--weB : out st... |
---------------------------------------------------------------------------
--
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- l... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : CS8900A bus interface module
-- Author : Gideon Zweijtzer <gideon.zweijtze... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : CS8900A bus interface module
-- Author : Gideon Zweijtzer <gideon.zweijtze... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : CS8900A bus interface module
-- Author : Gideon Zweijtzer <gideon.zweijtze... |
---------------------------------------------------------------------------
-- Copyright 2012 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity contador_mod8 is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
contagem : out std_logic_vector(2 downto 0);
fim : out std_logic);
end contador_mod8;
archite... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.filter_shared_package.all;
entity filter_mac_mem_controller is
generic
(
BIQUADS : natural := B;
MAC_FILTER_CH : natural := MC; -- MAC operations per channel for Main filte... |
library IEEE;
use IEEE.std_logic_1164.all;
entity invalid is
port
(
i_ip0: in std_logic;
i_clock: in std_logic;
i_o: in std_logic;
i_o_reset: in std_logic;
i_o_b_reset: in std_logic;
i_i_reset: in std_logic;
o_ip0: out std_logic;
o_clock: out std_logic;
o_o:... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/29/2015 11:08:18 AM
-- Design Name:
-- Module Name: dsp_32x32Mul_block - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
... |
-- file: clock_manager.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
Entity hamming_decoder is
port
(hamming_in : in std_logic_vector(38 downto 0); --d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d2... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--
-- File Name: MessagePkg.vhd
-- Design Unit Name: MessagePkg
-- Revision: STANDARD VERSION, revision 2015.01
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for multi-li... |
--
-- File Name: MessagePkg.vhd
-- Design Unit Name: MessagePkg
-- Revision: STANDARD VERSION, revision 2015.01
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for multi-li... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map(
G_GEN_1 => 3,
... |
----------------------------------------------------------------------------------
-- Author: Jonny Doin, jdoin@opencores.org
--
-- Create Date: 15:36:20 05/15/2011
-- Module Name: SPI_SLAVE - RTL
-- Project Name: SPI INTERFACE
-- Target Devices: Spartan-6
-- Tool versions: ISE 13.1
-- Descripti... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_n... |
architecture RTL of ENTITY1 is
subtype read_size is integer range 0 to 9;
subtype write_size is integer range 0 to 9;
signal read : read_size;
signal write : write_size;
constant read_sz : read_size := 8;
constant write_sz : write_size := 1;
begin
end architecture RTL;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/31/2017 03:31:33 PM
-- Design Name:
-- Module Name: Debug_Controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencie... |
-- *************************
-- Message Manager
-- (Prototype)
--
-- Written by Jason Agron
-- *************************
-- FIXMEs:
-- * Add in support for full-handshaking (user -> queue -> back to user)
-- * Change underlying queue structure to be faster (eliminate useless states)
library ieee;
use ieee.std_logic_11... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.std_logic_textio.all; -- I/O for logic types
library work;
use work.rv_components.all;
use work.utils.all;
use work.constants_pkg.all;
library STD;
use STD.textio.all; -- basic I/O
entity execute is
generic (... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.arith_dsp48e.all;
use work.utilities.all;
entity div_tb is
end div_tb;
architecture behavioral of div_tb is
constant C_DATAIN_WIDTH : integer := 32;
constant C_PRECISION : natural... |
-----------------------------------------------------------------------------------------
-- --
-- This file is part of the CAPH Compiler distribution --
-- http://caph.univ-bpc... |
package fifo_pkg is
end PACKAGE;
package fifo_pkg is
end PACKAGE;
|
entity tb_var01a is
end tb_var01a;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_var01a is
signal clk : std_logic;
signal mask : std_logic_vector (1 downto 0);
signal val : std_logic_vector (7 downto 0);
signal res : std_logic_vector (7 downto 0);
begin
dut: entity work.var01a
port... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "reg_file"
-------------------------------------------------------------------------------
-- Author : Calle <calle@Alukiste>
-- Standard : VHDL'87
------------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "reg_file"
-------------------------------------------------------------------------------
-- Author : Calle <calle@Alukiste>
-- Standard : VHDL'87
------------------------------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
entity prn32 is
generic(
n: integer:= 4;
seed: std_logic_vector:= X"12345678"
);
port(
clk: in std_logic;
pn_val: out std_logic_vector(n-1 downto 0)
);
end prn32;
architecture break_out of prn32 is
signal pn: std_logic... |
library ieee;
use ieee.std_logic_1164.all;
entity tristate_32 is
PORT(
my_in : in std_logic_vector(31 downto 0);
sel : in std_logic;
my_out : out std_logic_vector(31 downto 0)
);
end tristate_32;
architecture control of tristate_32 is
begin
my_out <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" when (s... |
library ieee;
use ieee.std_logic_1164.all;
entity tristate_32 is
PORT(
my_in : in std_logic_vector(31 downto 0);
sel : in std_logic;
my_out : out std_logic_vector(31 downto 0)
);
end tristate_32;
architecture control of tristate_32 is
begin
my_out <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" when (s... |
library ieee;
use ieee.std_logic_1164.all;
entity tristate_32 is
PORT(
my_in : in std_logic_vector(31 downto 0);
sel : in std_logic;
my_out : out std_logic_vector(31 downto 0)
);
end tristate_32;
architecture control of tristate_32 is
begin
my_out <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" when (s... |
library ieee;
use ieee.std_logic_1164.all;
entity tristate_32 is
PORT(
my_in : in std_logic_vector(31 downto 0);
sel : in std_logic;
my_out : out std_logic_vector(31 downto 0)
);
end tristate_32;
architecture control of tristate_32 is
begin
my_out <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" when (s... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity cnt01 is
port (
clock : in STD_LOGIC;
reset : in STD_LOGIC;
clear_count : in STD_LOGIC;
enable : in STD_LOGIC;
counter_out : out STD_LOGIC_VECTOR (9 downto 0)
);
end cnt01;
architecture behav of cn... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.procedures.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity r6w2mem1k8 is
port(
clk : in std_logic;
clk2x : in std_logic;
addra : in std_logic_vector(9 downto 0);
... |
--Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
--Date : Fri Sep 30 18:09:05 2016
--Host : graviton running 64-bit Debian GNU/Linux ... |
use work.p.all;
entity ent is
generic (
WIDTH : natural := 8
);
port (
test : in bit_vector(id(WIDTH)-1 downto 0)
);
end ent;
architecture a of ent is
begin
end a;
|
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_sha256
-- sha256.vhd is part of DS_sha256.
-- DS_sha256 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Pub... |
--!
--! \file first.vhd
--!
--! \author Ariane Keller
--! \date 29.07.2009
-- Demo file for the multibus. This file will be executed in slot 1.
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_b
--
-- Generated
-- by: wig
-- on: Tue Jun 27 05:23:07 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_MIXED ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated... |
library verilog;
use verilog.vl_types.all;
entity LVDS_AD is
port(
rx_in : in vl_logic_vector(7 downto 0);
rx_inclock : in vl_logic;
rx_locked : out vl_logic;
rx_out : out vl_logic_vector(95 downto 0);
rx_outclock : out vl_lo... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- used for address width calculation
use ieee.math_real.log2;
use ieee.math_real.ceil;
package aua_types is
constant ADDR_SIZE : natural := 16;
constant WORD_SIZE : natural := ADDR_SIZE;
subtype word_t is std_logic_vector(ADDR_SIZE-1 downto 0... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =========================================================================================================================================================... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =========================================================================================================================================================... |
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