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-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPLUTPOS.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_explutpos IS
PORT (
address : IN STD_LOGIC_VECTOR (7 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_explutpos;
ARCHITECTURE rtl OF fp_explutpos IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "0000000" =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "0000001" =>
mantissa <= conv_std_logic_vector(3012692,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "0000010" =>
mantissa <= conv_std_logic_vector(7107366,23);
exponent <= conv_std_logic_vector(129,8);
WHEN "0000011" =>
mantissa <= conv_std_logic_vector(2141998,23);
exponent <= conv_std_logic_vector(131,8);
WHEN "0000100" =>
mantissa <= conv_std_logic_vector(5923969,23);
exponent <= conv_std_logic_vector(132,8);
WHEN "0000101" =>
mantissa <= conv_std_logic_vector(1337797,23);
exponent <= conv_std_logic_vector(134,8);
WHEN "0000110" =>
mantissa <= conv_std_logic_vector(4830947,23);
exponent <= conv_std_logic_vector(135,8);
WHEN "0000111" =>
mantissa <= conv_std_logic_vector(595011,23);
exponent <= conv_std_logic_vector(137,8);
WHEN "0001000" =>
mantissa <= conv_std_logic_vector(3821396,23);
exponent <= conv_std_logic_vector(138,8);
WHEN "0001001" =>
mantissa <= conv_std_logic_vector(8206508,23);
exponent <= conv_std_logic_vector(139,8);
WHEN "0001010" =>
mantissa <= conv_std_logic_vector(2888942,23);
exponent <= conv_std_logic_vector(141,8);
WHEN "0001011" =>
mantissa <= conv_std_logic_vector(6939172,23);
exponent <= conv_std_logic_vector(142,8);
WHEN "0001100" =>
mantissa <= conv_std_logic_vector(2027699,23);
exponent <= conv_std_logic_vector(144,8);
WHEN "0001101" =>
mantissa <= conv_std_logic_vector(5768621,23);
exponent <= conv_std_logic_vector(145,8);
WHEN "0001110" =>
mantissa <= conv_std_logic_vector(1232226,23);
exponent <= conv_std_logic_vector(147,8);
WHEN "0001111" =>
mantissa <= conv_std_logic_vector(4687461,23);
exponent <= conv_std_logic_vector(148,8);
WHEN "0010000" =>
mantissa <= conv_std_logic_vector(497503,23);
exponent <= conv_std_logic_vector(150,8);
WHEN "0010001" =>
mantissa <= conv_std_logic_vector(3688868,23);
exponent <= conv_std_logic_vector(151,8);
WHEN "0010010" =>
mantissa <= conv_std_logic_vector(8026384,23);
exponent <= conv_std_logic_vector(152,8);
WHEN "0010011" =>
mantissa <= conv_std_logic_vector(2766536,23);
exponent <= conv_std_logic_vector(154,8);
WHEN "0010100" =>
mantissa <= conv_std_logic_vector(6772804,23);
exponent <= conv_std_logic_vector(155,8);
WHEN "0010101" =>
mantissa <= conv_std_logic_vector(1914640,23);
exponent <= conv_std_logic_vector(157,8);
WHEN "0010110" =>
mantissa <= conv_std_logic_vector(5614958,23);
exponent <= conv_std_logic_vector(158,8);
WHEN "0010111" =>
mantissa <= conv_std_logic_vector(1127802,23);
exponent <= conv_std_logic_vector(160,8);
WHEN "0011000" =>
mantissa <= conv_std_logic_vector(4545534,23);
exponent <= conv_std_logic_vector(161,8);
WHEN "0011001" =>
mantissa <= conv_std_logic_vector(401053,23);
exponent <= conv_std_logic_vector(163,8);
WHEN "0011010" =>
mantissa <= conv_std_logic_vector(3557779,23);
exponent <= conv_std_logic_vector(164,8);
WHEN "0011011" =>
mantissa <= conv_std_logic_vector(7848216,23);
exponent <= conv_std_logic_vector(165,8);
WHEN "0011100" =>
mantissa <= conv_std_logic_vector(2645458,23);
exponent <= conv_std_logic_vector(167,8);
WHEN "0011101" =>
mantissa <= conv_std_logic_vector(6608242,23);
exponent <= conv_std_logic_vector(168,8);
WHEN "0011110" =>
mantissa <= conv_std_logic_vector(1802808,23);
exponent <= conv_std_logic_vector(170,8);
WHEN "0011111" =>
mantissa <= conv_std_logic_vector(5462963,23);
exponent <= conv_std_logic_vector(171,8);
WHEN "0100000" =>
mantissa <= conv_std_logic_vector(1024510,23);
exponent <= conv_std_logic_vector(173,8);
WHEN "0100001" =>
mantissa <= conv_std_logic_vector(4405146,23);
exponent <= conv_std_logic_vector(174,8);
WHEN "0100010" =>
mantissa <= conv_std_logic_vector(305649,23);
exponent <= conv_std_logic_vector(176,8);
WHEN "0100011" =>
mantissa <= conv_std_logic_vector(3428113,23);
exponent <= conv_std_logic_vector(177,8);
WHEN "0100100" =>
mantissa <= conv_std_logic_vector(7671981,23);
exponent <= conv_std_logic_vector(178,8);
WHEN "0100101" =>
mantissa <= conv_std_logic_vector(2525694,23);
exponent <= conv_std_logic_vector(180,8);
WHEN "0100110" =>
mantissa <= conv_std_logic_vector(6445466,23);
exponent <= conv_std_logic_vector(181,8);
WHEN "0100111" =>
mantissa <= conv_std_logic_vector(1692191,23);
exponent <= conv_std_logic_vector(183,8);
WHEN "0101000" =>
mantissa <= conv_std_logic_vector(5312618,23);
exponent <= conv_std_logic_vector(184,8);
WHEN "0101001" =>
mantissa <= conv_std_logic_vector(922340,23);
exponent <= conv_std_logic_vector(186,8);
WHEN "0101010" =>
mantissa <= conv_std_logic_vector(4266283,23);
exponent <= conv_std_logic_vector(187,8);
WHEN "0101011" =>
mantissa <= conv_std_logic_vector(211282,23);
exponent <= conv_std_logic_vector(189,8);
WHEN "0101100" =>
mantissa <= conv_std_logic_vector(3299854,23);
exponent <= conv_std_logic_vector(190,8);
WHEN "0101101" =>
mantissa <= conv_std_logic_vector(7497659,23);
exponent <= conv_std_logic_vector(191,8);
WHEN "0101110" =>
mantissa <= conv_std_logic_vector(2407230,23);
exponent <= conv_std_logic_vector(193,8);
WHEN "0101111" =>
mantissa <= conv_std_logic_vector(6284457,23);
exponent <= conv_std_logic_vector(194,8);
WHEN "0110000" =>
mantissa <= conv_std_logic_vector(1582773,23);
exponent <= conv_std_logic_vector(196,8);
WHEN "0110001" =>
mantissa <= conv_std_logic_vector(5163905,23);
exponent <= conv_std_logic_vector(197,8);
WHEN "0110010" =>
mantissa <= conv_std_logic_vector(821279,23);
exponent <= conv_std_logic_vector(199,8);
WHEN "0110011" =>
mantissa <= conv_std_logic_vector(4128926,23);
exponent <= conv_std_logic_vector(200,8);
WHEN "0110100" =>
mantissa <= conv_std_logic_vector(117939,23);
exponent <= conv_std_logic_vector(202,8);
WHEN "0110101" =>
mantissa <= conv_std_logic_vector(3172987,23);
exponent <= conv_std_logic_vector(203,8);
WHEN "0110110" =>
mantissa <= conv_std_logic_vector(7325229,23);
exponent <= conv_std_logic_vector(204,8);
WHEN "0110111" =>
mantissa <= conv_std_logic_vector(2290052,23);
exponent <= conv_std_logic_vector(206,8);
WHEN "0111000" =>
mantissa <= conv_std_logic_vector(6125195,23);
exponent <= conv_std_logic_vector(207,8);
WHEN "0111001" =>
mantissa <= conv_std_logic_vector(1474544,23);
exponent <= conv_std_logic_vector(209,8);
WHEN "0111010" =>
mantissa <= conv_std_logic_vector(5016805,23);
exponent <= conv_std_logic_vector(210,8);
WHEN "0111011" =>
mantissa <= conv_std_logic_vector(721315,23);
exponent <= conv_std_logic_vector(212,8);
WHEN "0111100" =>
mantissa <= conv_std_logic_vector(3993061,23);
exponent <= conv_std_logic_vector(213,8);
WHEN "0111101" =>
mantissa <= conv_std_logic_vector(25608,23);
exponent <= conv_std_logic_vector(215,8);
WHEN "0111110" =>
mantissa <= conv_std_logic_vector(3047498,23);
exponent <= conv_std_logic_vector(216,8);
WHEN "0111111" =>
mantissa <= conv_std_logic_vector(7154671,23);
exponent <= conv_std_logic_vector(217,8);
WHEN "1000000" =>
mantissa <= conv_std_logic_vector(2174145,23);
exponent <= conv_std_logic_vector(219,8);
WHEN "1000001" =>
mantissa <= conv_std_logic_vector(5967662,23);
exponent <= conv_std_logic_vector(220,8);
WHEN "1000010" =>
mantissa <= conv_std_logic_vector(1367489,23);
exponent <= conv_std_logic_vector(222,8);
WHEN "1000011" =>
mantissa <= conv_std_logic_vector(4871303,23);
exponent <= conv_std_logic_vector(223,8);
WHEN "1000100" =>
mantissa <= conv_std_logic_vector(622436,23);
exponent <= conv_std_logic_vector(225,8);
WHEN "1000101" =>
mantissa <= conv_std_logic_vector(3858670,23);
exponent <= conv_std_logic_vector(226,8);
WHEN "1000110" =>
mantissa <= conv_std_logic_vector(8257169,23);
exponent <= conv_std_logic_vector(227,8);
WHEN "1000111" =>
mantissa <= conv_std_logic_vector(2923370,23);
exponent <= conv_std_logic_vector(229,8);
WHEN "1001000" =>
mantissa <= conv_std_logic_vector(6985964,23);
exponent <= conv_std_logic_vector(230,8);
WHEN "1001001" =>
mantissa <= conv_std_logic_vector(2059497,23);
exponent <= conv_std_logic_vector(232,8);
WHEN "1001010" =>
mantissa <= conv_std_logic_vector(5811839,23);
exponent <= conv_std_logic_vector(233,8);
WHEN "1001011" =>
mantissa <= conv_std_logic_vector(1261596,23);
exponent <= conv_std_logic_vector(235,8);
WHEN "1001100" =>
mantissa <= conv_std_logic_vector(4727380,23);
exponent <= conv_std_logic_vector(236,8);
WHEN "1001101" =>
mantissa <= conv_std_logic_vector(524630,23);
exponent <= conv_std_logic_vector(238,8);
WHEN "1001110" =>
mantissa <= conv_std_logic_vector(3725738,23);
exponent <= conv_std_logic_vector(239,8);
WHEN "1001111" =>
mantissa <= conv_std_logic_vector(8076495,23);
exponent <= conv_std_logic_vector(240,8);
WHEN "1010000" =>
mantissa <= conv_std_logic_vector(2800590,23);
exponent <= conv_std_logic_vector(242,8);
WHEN "1010001" =>
mantissa <= conv_std_logic_vector(6819089,23);
exponent <= conv_std_logic_vector(243,8);
WHEN "1010010" =>
mantissa <= conv_std_logic_vector(1946093,23);
exponent <= conv_std_logic_vector(245,8);
WHEN "1010011" =>
mantissa <= conv_std_logic_vector(5657707,23);
exponent <= conv_std_logic_vector(246,8);
WHEN "1010100" =>
mantissa <= conv_std_logic_vector(1156853,23);
exponent <= conv_std_logic_vector(248,8);
WHEN "1010101" =>
mantissa <= conv_std_logic_vector(4585019,23);
exponent <= conv_std_logic_vector(249,8);
WHEN "1010110" =>
mantissa <= conv_std_logic_vector(427885,23);
exponent <= conv_std_logic_vector(251,8);
WHEN "1010111" =>
mantissa <= conv_std_logic_vector(3594249,23);
exponent <= conv_std_logic_vector(252,8);
WHEN "1011000" =>
mantissa <= conv_std_logic_vector(7897783,23);
exponent <= conv_std_logic_vector(253,8);
WHEN "1011001" =>
mantissa <= conv_std_logic_vector(2679142,23);
exponent <= conv_std_logic_vector(255,8);
WHEN others =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
--
-- NOTE: In addition to being a VVC for the SBI, this module is also used as a template
-- and a well commented example of the VVC structure and functionality
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.sbi_bfm_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
--=================================================================================================
entity sbi_vvc is
generic (
GC_ADDR_WIDTH : integer range 1 to C_VVC_CMD_ADDR_MAX_LENGTH := 8; -- SBI address bus
GC_DATA_WIDTH : integer range 1 to C_VVC_CMD_DATA_MAX_LENGTH := 32; -- SBI data bus
GC_INSTANCE_IDX : natural := 1; -- Instance index for this SBI_VVCT instance
GC_SBI_CONFIG : t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT; -- Behavior specification for BFM
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning
);
port (
clk : in std_logic;
sbi_vvc_master_if : inout t_sbi_if := init_sbi_if_signals(GC_ADDR_WIDTH, GC_DATA_WIDTH)
);
begin
-- Check the interface widths to assure that the interface was correctly set up
assert (sbi_vvc_master_if.addr'length = GC_ADDR_WIDTH) report "sbi_vvc_master_if.addr'length =/ GC_ADDR_WIDTH" severity failure;
assert (sbi_vvc_master_if.wdata'length = GC_DATA_WIDTH) report "sbi_vvc_master_if.wdata'length =/ GC_DATA_WIDTH" severity failure;
assert (sbi_vvc_master_if.rdata'length = GC_DATA_WIDTH) report "sbi_vvc_master_if.rdata'length =/ GC_DATA_WIDTH" severity failure;
end entity sbi_vvc;
--=================================================================================================
--=================================================================================================
architecture behave of sbi_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of the element dedicated Queue
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_sbi_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_sbi_vvc_status(GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_sbi_transaction_info(GC_INSTANCE_IDX);
begin
--===============================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--===============================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_SBI_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--===============================================================================================
--===============================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--===============================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, shared_vvc_cmd, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command executor
-- - Fetch and execute the commands
--===============================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_read_data : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean;
variable v_normalised_addr : unsigned(GC_ADDR_WIDTH-1 downto 0) := (others => '0');
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
loop
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- Set the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
transaction_info.operation := v_cmd.operation;
transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length);
-- Check if command is a BFM access
if v_cmd.operation = WRITE or v_cmd.operation = READ or v_cmd.operation = CHECK or v_cmd.operation = POLL_UNTIL then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_command_is_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
scope => C_SCOPE);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when WRITE =>
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "sbi_write() called with to wide addrress. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "sbi_write() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
sbi_write(addr_value => v_normalised_addr,
data_value => v_normalised_data,
msg => format_msg(v_cmd),
clk => clk,
sbi_if => sbi_vvc_master_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
when READ =>
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "sbi_read() called with to wide addrress. " & v_cmd.msg);
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
sbi_read(addr_value => v_normalised_addr,
data_value => v_read_data(GC_DATA_WIDTH - 1 downto 0),
msg => format_msg(v_cmd),
clk => clk,
sbi_if => sbi_vvc_master_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result(result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_read_data);
when CHECK =>
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "sbi_check() called with to wide addrress. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "sbi_check() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
sbi_check(addr_value => v_normalised_addr,
data_exp => v_normalised_data,
msg => format_msg(v_cmd),
clk => clk,
sbi_if => sbi_vvc_master_if,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
when POLL_UNTIL =>
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "sbi_poll_until() called with to wide addrress. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "sbi_poll_until() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
sbi_poll_until(addr_value => v_normalised_addr,
data_exp => v_normalised_data,
max_polls => v_cmd.max_polls,
timeout => v_cmd.timeout,
msg => format_msg(v_cmd),
clk => clk,
sbi_if => sbi_vvc_master_if,
terminate_loop => terminate_current_cmd.is_active,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, vvc_config.msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, vvc_config.msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--===============================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--===============================================================================================
end behave;
|
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247a
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
-- 0247a: 7th of September, 2003 by Kazuhiro Tsujikawa (tujikawa@hat.hi-ho.ne.jp)
-- Fixed IORQ_n, RD_n, WR_n bus timing
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80a is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
-- Additions
TS : out std_logic_vector(2 downto 0);
Regs : out std_logic_vector(255 downto 0);
PdcData : out std_logic_vector(7 downto 0);
-- Original Signals
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
Din : in std_logic_vector(7 downto 0);
Dout : out std_logic_vector(7 downto 0);
Den : out std_logic
);
end T80a;
architecture rtl of T80a is
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal NMICycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal IReq_Inhibit : std_logic; -- 0247a
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal WR_n_j : std_logic; -- 0247a
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
signal HALT_n_int : std_logic;
signal iack1 : std_logic;
signal iack2 : std_logic;
begin
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or (IORQ and IReq_Inhibit) or Req_Inhibit; -- DMB
WR_n_j <= WR_n_i or (IORQ and IReq_Inhibit); -- DMB
HALT_n <= HALT_n_int;
--Remove tristate as in ICE-Z80 this is implmeneted in Z80CpuMon
--MREQ_n <= MREQ_n_i; when BUSAK_n_i = '1' else 'Z';
--IORQ_n <= IORQ_n_i or IReq_Inhibit when BUSAK_n_i = '1' else 'Z'; -- 0247a
--RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
--WR_n <= WR_n_j when BUSAK_n_i = '1' else 'Z'; -- 0247a
--RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
--A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
MREQ_n <= MREQ_n_i;
IORQ_n <= IORQ_n_i or IReq_Inhibit or Req_inhibit; --DMB
RD_n <= RD_n_i;
WR_n <= WR_n_j; -- 0247a
RFSH_n <= RFSH_n_i;
A <= A_i;
Dout <= DO;
Den <= Write and BUSAK_n_i;
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n_int,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
DInst => Din,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n,
NMICycle_n => NMICycle_n,
REG => Regs(211 downto 0),
DIRSet => '0',
DIR => (others => '0')
);
Regs(255 downto 212) <= (others => '0');
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
if CEN = '1' then
Wait_s <= WAIT_n or (IORQ_n_i and MREQ_n_i);
if TState = "011" and BUSAK_n_i = '1' then
DI_Reg <= to_x01(Din);
end if;
end if;
end if;
end process;
process (CLK_n) -- 0247a
begin
if CLK_n'event and CLK_n = '1' then
IReq_Inhibit <= (not IORQ) and IntCycle_n;
end if;
end process;
process (Reset_s,CLK_n) -- 0247a
begin
if Reset_s = '0' then
WR_n_i <= '1';
elsif CLK_n'event and CLK_n = '0' then
if CEN = '1' then
if (IORQ = '0') then
if TState = "010" then
WR_n_i <= not Write;
elsif Tstate = "011" then
WR_n_i <= '1';
end if;
else
if TState = "001" then -- DMB
WR_n_i <= not Write;
elsif Tstate = "011" then
WR_n_i <= '1';
end if;
end if;
end if;
end if;
end process;
process (Reset_s,CLK_n) -- 0247a
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
if MCycle = "001" and TState = "010" and wait_s = '1' then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if CEN = '1' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end if;
end process;
process(Reset_s,CLK_n) -- 0247a
begin
if Reset_s = '0' then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
iack1 <= '0';
iack2 <= '0';
elsif CLK_n'event and CLK_n = '0' then
if CEN = '1' then
if MCycle = "001" then
if IntCycle_n = '1' then
-- Normal M1 Cycle
if TState = "001" then
RD <= '1';
MREQ <= '1';
IORQ_n_i <= '1';
end if;
else
-- Interupt Ack Cycle
-- 5 T-states: T1 T1 (auto wait) T1 (auto wait) T2 T3
-- Assert IORQ in middle of third T1
if TState = "001" then
iack1 <= '1';
iack2 <= iack1;
else
iack1 <= '0';
iack2 <= '0';
end if;
if iack2 = '1' then
IORQ_n_i <= '0';
end if;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
IORQ_n_i <= not IORQ;
MREQ <= not IORQ;
RD <= not Write; -- DMB
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
end if;
end if;
end if;
end if;
end process;
TS <= TState;
PdcData <= (not HALT_n_int) & (not NMICycle_n) & (not IntCycle_n) & "00000";
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity onebitvoter is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
y : out STD_LOGIC;
status : out STD_LOGIC_VECTOR(2 downto 0)
);
end onebitvoter;
architecture Behavioral of onebitvoter is
signal state_a: STD_LOGIC := '1';
signal state_b: STD_LOGIC := '1';
signal state_c: STD_LOGIC := '1';
signal state_d: STD_LOGIC := '1';
signal status_internal: STD_LOGIC_VECTOR(2 downto 0);
signal last_status: STD_LOGIC_VECTOR(2 downto 0) := "000";
signal voted_data: STD_LOGIC;
signal sum_of_inputs: STD_LOGIC_VECTOR(2 downto 0);
signal number_of_winning_votes: STD_LOGIC_VECTOR(2 downto 0);
signal extended_a: STD_LOGIC_VECTOR(2 downto 0);
signal extended_b: STD_LOGIC_VECTOR(2 downto 0);
signal extended_c: STD_LOGIC_VECTOR(2 downto 0);
signal extended_d: STD_LOGIC_VECTOR(2 downto 0);
signal extended_vote_a: STD_LOGIC_VECTOR(2 downto 0);
signal extended_vote_b: STD_LOGIC_VECTOR(2 downto 0);
signal extended_vote_c: STD_LOGIC_VECTOR(2 downto 0);
signal extended_vote_d: STD_LOGIC_VECTOR(2 downto 0);
begin
-- Start of state machine back end
-- Update outputs when the clock tick occur
process (clk)
begin
if (rising_edge(clk)) then
if(reset='1') then
state_a <= '1'; --default state on reset.
state_b <= '1'; --default state on reset.
state_c <= '1'; --default state on reset.
state_d <= '1'; --default state on reset.
last_status <= "000";
else
status <= status_internal;
last_status <= status_internal;
y <= voted_data;
state_a <= state_a and (voted_data xnor a);
state_b <= state_b and (voted_data xnor b);
state_c <= state_c and (voted_data xnor c);
state_d <= state_d and (voted_data xnor d);
end if;
end if;
end process;
-- End of state machine back end
-- Start of state machine front end
-- Filter out votes from failed micro controllers and extend the vote result to a 3 bit number
process (a, b, c, d, state_a, state_b, state_c, state_d)
begin
extended_a <= "00"&(a and state_a);
extended_b <= "00"&(b and state_b);
extended_c <= "00"&(c and state_c);
extended_d <= "00"&(d and state_d);
end process;
-- Calculate the sum of the inputs from all the non broken controllers
process (extended_a, extended_b, extended_c, extended_d)
begin
sum_of_inputs <= std_logic_vector(
unsigned(extended_a) +
unsigned(extended_b) +
unsigned(extended_c) +
unsigned(extended_d));
end process;
-- Set the voted data based on the status and the sum of the input data
-- This is the core of the state machine driving the system
process (sum_of_inputs, last_status)
begin
case last_status is
when "000" =>
case sum_of_inputs is
when "100" =>
voted_data <= '1';
when "011" =>
voted_data <= '1';
when "010" =>
voted_data <= '1'; -- in 2v2 votes the data doesn't matter, we are going to status 111 anyway
when "001" =>
voted_data <= '0';
when "000" =>
voted_data <= '0';
when others =>
voted_data <= 'X'; -- This is never reached
end case;
when "001" =>
case sum_of_inputs is
when "011" =>
voted_data <= '1';
when "010" =>
voted_data <= '1';
when "001" =>
voted_data <= '0';
when "000" =>
voted_data <= '0';
when others =>
voted_data <= 'X'; -- This is never reached
end case;
when "010" =>
case sum_of_inputs is
when "010" =>
voted_data <= '1';
when "001" =>
voted_data <= '1'; -- in 2v2 votes the data doesn't matter, we are going to status 111 anyway
when "000" =>
voted_data <= '0';
when others =>
voted_data <= 'X'; -- This is never reached
end case;
when "111" =>
voted_data <= '1';
when others =>
voted_data <= 'Z'; -- This is never reached, Z is used instead of X because it is more efficient here
end case;
end process;
-- Filter out the votes that did not match the winning vote and extend them to a 3 bit number
process(voted_data, a, b, c, d, state_a, state_b, state_c, state_d)
begin
extended_vote_a <= "00"&(state_a and (voted_data xnor a));
extended_vote_b <= "00"&(state_b and (voted_data xnor b));
extended_vote_c <= "00"&(state_c and (voted_data xnor c));
extended_vote_d <= "00"&(state_d and (voted_data xnor d));
end process;
-- Calculate the number of votes that matched the vote outcome which came from an input with state '1'
process(extended_vote_a, extended_vote_b, extended_vote_c, extended_vote_d)
begin
number_of_winning_votes <= std_logic_vector(
unsigned( extended_vote_a ) +
unsigned( extended_vote_b ) +
unsigned( extended_vote_c ) +
unsigned( extended_vote_d )
);
end process;
-- Calculate the internal status field based on the inputs matched with the voted data
process (number_of_winning_votes, last_status)
begin
if(number_of_winning_votes = "010" and last_status = "000") then
status_internal <= "111";
else
case number_of_winning_votes is
when "100"=>
status_internal <= "000";
when "011"=>
status_internal <= "001";
when "010"=>
status_internal <= "010";
when "001"=>
status_internal <= "111";
when "000"=>
status_internal <= "111";
when others =>
-- This should never be reached
status_internal <= "XXX";
end case;
end if;
end process;
-- End of state machine front end
end Behavioral; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library project;
entity inline_02 is
end entity inline_02;
architecture test of inline_02 is
begin
process is
use project.mem_pkg;
use project.mem_pkg.all;
variable words : word_array(0 to 3);
begin
assert
-- code from book (in text)
mem_pkg'path_name = ":project:mem_pkg:"
-- end code from book
;
report mem_pkg'path_name;
assert
-- code from book (in text)
word'path_name = ":project:mem_pkg:word"
-- end code from book
;
report word'path_name;
assert
-- code from book (in text)
word_array'path_name = ":project:mem_pkg:word_array"
-- end code from book
;
report word_array'path_name;
assert
-- code from book (in text)
load_array'path_name = ":project:mem_pkg:load_array"
-- end code from book
;
report load_array'path_name;
load_array(words, "/dev/null");
wait;
end process;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library project;
entity inline_02 is
end entity inline_02;
architecture test of inline_02 is
begin
process is
use project.mem_pkg;
use project.mem_pkg.all;
variable words : word_array(0 to 3);
begin
assert
-- code from book (in text)
mem_pkg'path_name = ":project:mem_pkg:"
-- end code from book
;
report mem_pkg'path_name;
assert
-- code from book (in text)
word'path_name = ":project:mem_pkg:word"
-- end code from book
;
report word'path_name;
assert
-- code from book (in text)
word_array'path_name = ":project:mem_pkg:word_array"
-- end code from book
;
report word_array'path_name;
assert
-- code from book (in text)
load_array'path_name = ":project:mem_pkg:load_array"
-- end code from book
;
report load_array'path_name;
load_array(words, "/dev/null");
wait;
end process;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library project;
entity inline_02 is
end entity inline_02;
architecture test of inline_02 is
begin
process is
use project.mem_pkg;
use project.mem_pkg.all;
variable words : word_array(0 to 3);
begin
assert
-- code from book (in text)
mem_pkg'path_name = ":project:mem_pkg:"
-- end code from book
;
report mem_pkg'path_name;
assert
-- code from book (in text)
word'path_name = ":project:mem_pkg:word"
-- end code from book
;
report word'path_name;
assert
-- code from book (in text)
word_array'path_name = ":project:mem_pkg:word_array"
-- end code from book
;
report word_array'path_name;
assert
-- code from book (in text)
load_array'path_name = ":project:mem_pkg:load_array"
-- end code from book
;
report load_array'path_name;
load_array(words, "/dev/null");
wait;
end process;
end architecture test;
|
-- file: clock_manager_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clock_manager_tb is
end clock_manager_tb;
architecture test of clock_manager_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.25 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component clock_manager_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clock_manager_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue is
generic (N : natural := 3);
port (data : out signed(N-1 downto 0));
end issue;
architecture rtl of issue is
subtype my_type is signed(N-1 downto 0);
begin
data <= to_signed(1,my_type'length);
end architecture;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: CLK4Hz
-- Project Name: CLOCK COUNTER
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Clock Divider
-- Lower the Clock frequency from
-- 50 Mhz to 4 hz
-- 50Mhz = 50,000,000/12,500,000 = 2 Hz
-- 4Hz ~= 1/2 second
-- Actually 2 KHz, divide by 25,000
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk4Hz is
Port ( CLK_IN : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_OUT : out STD_LOGIC);
end clk4Hz;
architecture Behavioral of clk4Hz is
signal clkdv: STD_LOGIC:='0';
signal counter : integer range 0 to 25000 := 0;
begin
frequency_divider: process (RST, CLK_IN) begin
if (RST = '1') then
clkdv <= '0';
counter <= 0;
elsif rising_edge(CLK_IN) then
if (counter = 25000) then
if(clkdv='0') then
clkdv <= '1';
else
clkdv <= '0';
end if;
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
CLK_OUT <= clkdv;
end Behavioral;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: CLK4Hz
-- Project Name: CLOCK COUNTER
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Clock Divider
-- Lower the Clock frequency from
-- 50 Mhz to 4 hz
-- 50Mhz = 50,000,000/12,500,000 = 2 Hz
-- 4Hz ~= 1/2 second
-- Actually 2 KHz, divide by 25,000
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk4Hz is
Port ( CLK_IN : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_OUT : out STD_LOGIC);
end clk4Hz;
architecture Behavioral of clk4Hz is
signal clkdv: STD_LOGIC:='0';
signal counter : integer range 0 to 25000 := 0;
begin
frequency_divider: process (RST, CLK_IN) begin
if (RST = '1') then
clkdv <= '0';
counter <= 0;
elsif rising_edge(CLK_IN) then
if (counter = 25000) then
if(clkdv='0') then
clkdv <= '1';
else
clkdv <= '0';
end if;
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
CLK_OUT <= clkdv;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: CPE233
-- Engineer: Jacob Hladky
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library unisim;
use unisim.vcomponents.all;
entity prog_ram is
Port( clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR(9 downto 0);
instruction : out STD_LOGIC_VECTOR(17 downto 0);
ins_prog : in STD_LOGIC_VECTOR(17 downto 0);
we, oe : in STD_LOGIC);
end prog_ram;
architecture prog_ram_a of prog_ram is
-- type memory is array (0 to 1023) of std_logic_vector(17 downto 0);
-- signal prog_ram_data : memory := (others => (others => '0'));
component RAMB16_S18
-- pragma translate_on
port (
DI : in std_logic_vector (15 downto 0);
DIP : in std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (9 downto 0);
EN : in std_logic;
WE : in std_logic;
SSR : in std_logic;
CLK : in std_logic;
DO : out std_logic_vector (15 downto 0);
DOP : out std_logic_vector (1 downto 0));
end component;
begin
--process(clk, address, we)
-- variable ins_cnt : integer range 0 to 1023 := 0;
--begin
-- if(rising_edge(clk)) then
-- if(we = '1') then
-- prog_ram_data(ins_cnt) <= ins_prog;
-- ins_cnt := ins_cnt + 1;
-- end if;
-- end if;
--end process;
--instruction <= prog_ram_data(conv_integer(address));
-- Block SelectRAM Instantiation
U_RAMB16_S18: RAMB16_S18 port map(
DI => ins_prog(15 downto 0), -- 16 bits data in bus (<15 downto 0>)
DIP => ins_prog(17 downto 16), -- 2 bits parity data in bus (<17 downto 16>)
ADDR => address, -- 10 bits address bus
EN => oe, -- enable signal
WE => we, -- write enable signal
SSR => '0', -- set/reset signal
CLK => clk, -- clock signal
DO => instruction(15 downto 0), -- 16 bits data out bus (<15 downto 0>)
DOP => instruction(17 downto 16)); -- 2 bits parity data out bus (<17 downto 16>)
end prog_ram_a;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-conf-c.vhd,v 1.1 2004/04/06 10:50:57 wig Exp $
-- $Date: 2004/04/06 10:50:57 $
-- $Log: inst_t_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2004/04/06 10:50:57 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_t_e_rtl_conf / inst_t_e
--
configuration inst_t_e_rtl_conf of inst_t_e is
for rtl
-- Generated Configuration
for inst_a : inst_a_e
use configuration work.inst_a_e_rtl_conf;
end for;
for inst_b : inst_b_e
use configuration work.inst_b_e_rtl_conf;
end for;
for inst_c : inst_c_e
use configuration work.inst_c_e_rtl_conf;
end for;
for inst_d : inst_d_e
use configuration work.inst_d_e_rtl_conf;
end for;
for inst_e : inst_e_e
use configuration work.inst_e_e_rtl_conf;
end for;
end for;
end inst_t_e_rtl_conf;
--
-- End of Generated Configuration inst_t_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 17:40:25 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_processing_system7_0_1_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_processing_system7_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "zqynq_lab_1_design_processing_system7_0_1.hwdef";
attribute POWER : string;
attribute POWER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2);
M_AXI_GP0_ARCACHE(1) <= \<const1>\;
M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0);
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2);
M_AXI_GP0_AWCACHE(1) <= \<const1>\;
M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2);
M_AXI_GP1_ARCACHE(1) <= \<const1>\;
M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2);
M_AXI_GP1_AWCACHE(1) <= \<const1>\;
M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 2) => B"00000000000000",
IRQF2P(1 downto 0) => IRQ_F2P(1 downto 0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2),
MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1),
MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2),
MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1),
MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2),
MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1),
MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2),
MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1),
MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_processing_system7_0_1,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.2.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 2;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "zqynq_lab_1_design_processing_system7_0_1.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(1 downto 0) => IRQ_F2P(1 downto 0),
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
|
------------------------------------------------------------------------------
-- radio_controller.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: radio_controller.vhd
-- Version: 1.20.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed Feb 06 13:11:09 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_00_a;
use plbv46_slave_single_v1_00_a.plbv46_slave_single;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity radio_controller is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
controller_logic_clk : out std_logic;
spi_clk : out std_logic;
data_out : out std_logic;
radio1_cs : out std_logic;
radio2_cs : out std_logic;
radio3_cs : out std_logic;
radio4_cs : out std_logic;
dac1_cs : out std_logic;
dac2_cs : out std_logic;
dac3_cs : out std_logic;
dac4_cs : out std_logic;
radio1_interpfiltbypass : out std_logic;
radio1_decfiltbypass : out std_logic;
radio1_SHDN : out std_logic;
radio1_TxEn : out std_logic;
radio1_RxEn : out std_logic;
radio1_RxHP : out std_logic;
radio1_LD : in std_logic;
radio1_24PA : out std_logic;
radio1_5PA : out std_logic;
radio1_ANTSW : out std_logic_vector(0 to 1);
radio1_LED : out std_logic_vector(0 to 2);
radio1_ADC_RX_DCS : out std_logic;
radio1_ADC_RX_DFS : out std_logic;
radio1_ADC_RX_OTRA : in std_logic;
radio1_ADC_RX_OTRB : in std_logic;
radio1_ADC_RX_PWDNA : out std_logic;
radio1_ADC_RX_PWDNB : out std_logic;
radio1_DIPSW : in std_logic_vector(0 to 3);
radio1_RSSI_ADC_CLAMP : out std_logic;
radio1_RSSI_ADC_HIZ : out std_logic;
radio1_RSSI_ADC_OTR : in std_logic;
radio1_RSSI_ADC_SLEEP : out std_logic;
radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio1_TX_DAC_PLL_LOCK : in std_logic;
radio1_TX_DAC_RESET : out std_logic;
radio1_SHDN_external : in std_logic;
radio1_TxEn_external : in std_logic;
radio1_RxEn_external : in std_logic;
radio1_RxHP_external : in std_logic;
radio1_TxGain : out std_logic_vector(0 to 5);
radio1_TxStart : out std_logic;
radio2_interpfiltbypass : out std_logic;
radio2_decfiltbypass : out std_logic;
radio2_SHDN : out std_logic;
radio2_TxEn : out std_logic;
radio2_RxEn : out std_logic;
radio2_RxHP : out std_logic;
radio2_LD : in std_logic;
radio2_24PA : out std_logic;
radio2_5PA : out std_logic;
radio2_ANTSW : out std_logic_vector(0 to 1);
radio2_LED : out std_logic_vector(0 to 2);
radio2_ADC_RX_DCS : out std_logic;
radio2_ADC_RX_DFS : out std_logic;
radio2_ADC_RX_OTRA : in std_logic;
radio2_ADC_RX_OTRB : in std_logic;
radio2_ADC_RX_PWDNA : out std_logic;
radio2_ADC_RX_PWDNB : out std_logic;
radio2_DIPSW : in std_logic_vector(0 to 3);
radio2_RSSI_ADC_CLAMP : out std_logic;
radio2_RSSI_ADC_HIZ : out std_logic;
radio2_RSSI_ADC_OTR : in std_logic;
radio2_RSSI_ADC_SLEEP : out std_logic;
radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio2_TX_DAC_PLL_LOCK : in std_logic;
radio2_TX_DAC_RESET : out std_logic;
radio2_SHDN_external : in std_logic;
radio2_TxEn_external : in std_logic;
radio2_RxEn_external : in std_logic;
radio2_RxHP_external : in std_logic;
radio2_TxGain : out std_logic_vector(0 to 5);
radio2_TxStart : out std_logic;
radio3_interpfiltbypass : out std_logic;
radio3_decfiltbypass : out std_logic;
radio3_SHDN : out std_logic;
radio3_TxEn : out std_logic;
radio3_RxEn : out std_logic;
radio3_RxHP : out std_logic;
radio3_LD : in std_logic;
radio3_24PA : out std_logic;
radio3_5PA : out std_logic;
radio3_ANTSW : out std_logic_vector(0 to 1);
radio3_LED : out std_logic_vector(0 to 2);
radio3_ADC_RX_DCS : out std_logic;
radio3_ADC_RX_DFS : out std_logic;
radio3_ADC_RX_OTRA : in std_logic;
radio3_ADC_RX_OTRB : in std_logic;
radio3_ADC_RX_PWDNA : out std_logic;
radio3_ADC_RX_PWDNB : out std_logic;
radio3_DIPSW : in std_logic_vector(0 to 3);
radio3_RSSI_ADC_CLAMP : out std_logic;
radio3_RSSI_ADC_HIZ : out std_logic;
radio3_RSSI_ADC_OTR : in std_logic;
radio3_RSSI_ADC_SLEEP : out std_logic;
radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio3_TX_DAC_PLL_LOCK : in std_logic;
radio3_TX_DAC_RESET : out std_logic;
radio3_SHDN_external : in std_logic;
radio3_TxEn_external : in std_logic;
radio3_RxEn_external : in std_logic;
radio3_RxHP_external : in std_logic;
radio3_TxGain : out std_logic_vector(0 to 5);
radio3_TxStart : out std_logic;
radio4_interpfiltbypass : out std_logic;
radio4_decfiltbypass : out std_logic;
radio4_SHDN : out std_logic;
radio4_TxEn : out std_logic;
radio4_RxEn : out std_logic;
radio4_RxHP : out std_logic;
radio4_LD : in std_logic;
radio4_24PA : out std_logic;
radio4_5PA : out std_logic;
radio4_ANTSW : out std_logic_vector(0 to 1);
radio4_LED : out std_logic_vector(0 to 2);
radio4_ADC_RX_DCS : out std_logic;
radio4_ADC_RX_DFS : out std_logic;
radio4_ADC_RX_OTRA : in std_logic;
radio4_ADC_RX_OTRB : in std_logic;
radio4_ADC_RX_PWDNA : out std_logic;
radio4_ADC_RX_PWDNB : out std_logic;
radio4_DIPSW : in std_logic_vector(0 to 3);
radio4_RSSI_ADC_CLAMP : out std_logic;
radio4_RSSI_ADC_HIZ : out std_logic;
radio4_RSSI_ADC_OTR : in std_logic;
radio4_RSSI_ADC_SLEEP : out std_logic;
radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio4_TX_DAC_PLL_LOCK : in std_logic;
radio4_TX_DAC_RESET : out std_logic;
radio4_SHDN_external : in std_logic;
radio4_TxEn_external : in std_logic;
radio4_RxEn_external : in std_logic;
radio4_RxHP_external : in std_logic;
radio4_TxGain : out std_logic_vector(0 to 5);
radio4_TxStart : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity radio_controller;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of radio_controller is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 17;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 17
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
controller_logic_clk : out std_logic;
spi_clk : out std_logic;
data_out : out std_logic;
Radio1_cs : out std_logic;
Radio2_cs : out std_logic;
Radio3_cs : out std_logic;
Radio4_cs : out std_logic;
Dac1_cs : out std_logic;
Dac2_cs : out std_logic;
Dac3_cs : out std_logic;
Dac4_cs : out std_logic;
Radio1_interpfiltbypass : out std_logic;
Radio1_decfiltbypass : out std_logic;
Radio1_SHDN : out std_logic;
Radio1_TxEn : out std_logic;
Radio1_RxEn : out std_logic;
Radio1_RxHP : out std_logic;
Radio1_LD : in std_logic;
Radio1_24PA : out std_logic;
Radio1_5PA : out std_logic;
Radio1_ANTSW : out std_logic_vector(0 to 1);
Radio1_LED : out std_logic_vector(0 to 2);
Radio1_ADC_RX_DCS : out std_logic;
Radio1_ADC_RX_DFS : out std_logic;
Radio1_ADC_RX_OTRA : in std_logic;
Radio1_ADC_RX_OTRB : in std_logic;
Radio1_ADC_RX_PWDNA : out std_logic;
Radio1_ADC_RX_PWDNB : out std_logic;
Radio1_DIPSW : in std_logic_vector(0 to 3);
Radio1_RSSI_ADC_CLAMP : out std_logic;
Radio1_RSSI_ADC_HIZ : out std_logic;
Radio1_RSSI_ADC_OTR : in std_logic;
Radio1_RSSI_ADC_SLEEP : out std_logic;
Radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio1_TX_DAC_PLL_LOCK : in std_logic;
Radio1_TX_DAC_RESET : out std_logic;
Radio1_SHDN_external : in std_logic;
Radio1_TxEn_external : in std_logic;
Radio1_RxEn_external : in std_logic;
Radio1_RxHP_external : in std_logic;
Radio1_TxGain : out std_logic_vector(0 to 5);
Radio1_TxStart : out std_logic;
Radio2_interpfiltbypass : out std_logic;
Radio2_decfiltbypass : out std_logic;
Radio2_SHDN : out std_logic;
Radio2_TxEn : out std_logic;
Radio2_RxEn : out std_logic;
Radio2_RxHP : out std_logic;
Radio2_LD : in std_logic;
Radio2_24PA : out std_logic;
Radio2_5PA : out std_logic;
Radio2_ANTSW : out std_logic_vector(0 to 1);
Radio2_LED : out std_logic_vector(0 to 2);
Radio2_ADC_RX_DCS : out std_logic;
Radio2_ADC_RX_DFS : out std_logic;
Radio2_ADC_RX_OTRA : in std_logic;
Radio2_ADC_RX_OTRB : in std_logic;
Radio2_ADC_RX_PWDNA : out std_logic;
Radio2_ADC_RX_PWDNB : out std_logic;
Radio2_DIPSW : in std_logic_vector(0 to 3);
Radio2_RSSI_ADC_CLAMP : out std_logic;
Radio2_RSSI_ADC_HIZ : out std_logic;
Radio2_RSSI_ADC_OTR : in std_logic;
Radio2_RSSI_ADC_SLEEP : out std_logic;
Radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio2_TX_DAC_PLL_LOCK : in std_logic;
Radio2_TX_DAC_RESET : out std_logic;
Radio2_SHDN_external : in std_logic;
Radio2_TxEn_external : in std_logic;
Radio2_RxEn_external : in std_logic;
Radio2_RxHP_external : in std_logic;
Radio2_TxGain : out std_logic_vector(0 to 5);
Radio2_TxStart : out std_logic;
Radio3_interpfiltbypass : out std_logic;
Radio3_decfiltbypass : out std_logic;
Radio3_SHDN : out std_logic;
Radio3_TxEn : out std_logic;
Radio3_RxEn : out std_logic;
Radio3_RxHP : out std_logic;
Radio3_LD : in std_logic;
Radio3_24PA : out std_logic;
Radio3_5PA : out std_logic;
Radio3_ANTSW : out std_logic_vector(0 to 1);
Radio3_LED : out std_logic_vector(0 to 2);
Radio3_ADC_RX_DCS : out std_logic;
Radio3_ADC_RX_DFS : out std_logic;
Radio3_ADC_RX_OTRA : in std_logic;
Radio3_ADC_RX_OTRB : in std_logic;
Radio3_ADC_RX_PWDNA : out std_logic;
Radio3_ADC_RX_PWDNB : out std_logic;
Radio3_DIPSW : in std_logic_vector(0 to 3);
Radio3_RSSI_ADC_CLAMP : out std_logic;
Radio3_RSSI_ADC_HIZ : out std_logic;
Radio3_RSSI_ADC_OTR : in std_logic;
Radio3_RSSI_ADC_SLEEP : out std_logic;
Radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio3_TX_DAC_PLL_LOCK : in std_logic;
Radio3_TX_DAC_RESET : out std_logic;
Radio3_SHDN_external : in std_logic;
Radio3_TxEn_external : in std_logic;
Radio3_RxEn_external : in std_logic;
Radio3_RxHP_external : in std_logic;
Radio3_TxGain : out std_logic_vector(0 to 5);
Radio3_TxStart : out std_logic;
Radio4_interpfiltbypass : out std_logic;
Radio4_decfiltbypass : out std_logic;
Radio4_SHDN : out std_logic;
Radio4_TxEn : out std_logic;
Radio4_RxEn : out std_logic;
Radio4_RxHP : out std_logic;
Radio4_LD : in std_logic;
Radio4_24PA : out std_logic;
Radio4_5PA : out std_logic;
Radio4_ANTSW : out std_logic_vector(0 to 1);
Radio4_LED : out std_logic_vector(0 to 2);
Radio4_ADC_RX_DCS : out std_logic;
Radio4_ADC_RX_DFS : out std_logic;
Radio4_ADC_RX_OTRA : in std_logic;
Radio4_ADC_RX_OTRB : in std_logic;
Radio4_ADC_RX_PWDNA : out std_logic;
Radio4_ADC_RX_PWDNB : out std_logic;
Radio4_DIPSW : in std_logic_vector(0 to 3);
Radio4_RSSI_ADC_CLAMP : out std_logic;
Radio4_RSSI_ADC_HIZ : out std_logic;
Radio4_RSSI_ADC_OTR : in std_logic;
Radio4_RSSI_ADC_SLEEP : out std_logic;
Radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio4_TX_DAC_PLL_LOCK : in std_logic;
Radio4_TX_DAC_RESET : out std_logic;
Radio4_SHDN_external : in std_logic;
Radio4_TxEn_external : in std_logic;
Radio4_RxEn_external : in std_logic;
Radio4_RxHP_external : in std_logic;
Radio4_TxGain : out std_logic_vector(0 to 5);
Radio4_TxStart : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_00_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
controller_logic_clk => controller_logic_clk,
spi_clk => spi_clk,
data_out => data_out,
Radio1_cs => radio1_cs,
Radio2_cs => radio2_cs,
Radio3_cs => radio3_cs,
Radio4_cs => radio4_cs,
Dac1_cs => dac1_cs,
Dac2_cs => dac2_cs,
Dac3_cs => dac3_cs,
Dac4_cs => dac4_cs,
Radio1_interpfiltbypass => radio1_interpfiltbypass,
Radio1_decfiltbypass => radio1_decfiltbypass,
Radio1_SHDN => radio1_SHDN,
Radio1_TxEn => radio1_TxEn,
Radio1_RxEn => radio1_RxEn,
Radio1_RxHP => radio1_RxHP,
Radio1_LD => radio1_LD,
Radio1_24PA => radio1_24PA,
Radio1_5PA => radio1_5PA,
Radio1_ANTSW => radio1_ANTSW,
Radio1_LED => radio1_LED,
Radio1_ADC_RX_DCS => radio1_ADC_RX_DCS,
Radio1_ADC_RX_DFS => radio1_ADC_RX_DFS,
Radio1_ADC_RX_OTRA => radio1_ADC_RX_OTRA,
Radio1_ADC_RX_OTRB => radio1_ADC_RX_OTRB,
Radio1_ADC_RX_PWDNA => radio1_ADC_RX_PWDNA,
Radio1_ADC_RX_PWDNB => radio1_ADC_RX_PWDNB,
Radio1_DIPSW => radio1_DIPSW,
Radio1_RSSI_ADC_CLAMP => radio1_RSSI_ADC_CLAMP,
Radio1_RSSI_ADC_HIZ => radio1_RSSI_ADC_HIZ,
Radio1_RSSI_ADC_OTR => radio1_RSSI_ADC_OTR,
Radio1_RSSI_ADC_SLEEP => radio1_RSSI_ADC_SLEEP,
Radio1_RSSI_ADC_D => radio1_RSSI_ADC_D,
Radio1_TX_DAC_PLL_LOCK => radio1_TX_DAC_PLL_LOCK,
Radio1_TX_DAC_RESET => radio1_TX_DAC_RESET,
Radio1_SHDN_external => radio1_SHDN_external,
Radio1_TxEn_external => radio1_TxEn_external,
Radio1_RxEn_external => radio1_RxEn_external,
Radio1_RxHP_external => radio1_RxHP_external,
Radio1_TxGain => radio1_TxGain,
Radio1_TxStart => radio1_TxStart,
Radio2_interpfiltbypass => radio2_interpfiltbypass,
Radio2_decfiltbypass => radio2_decfiltbypass,
Radio2_SHDN => radio2_SHDN,
Radio2_TxEn => radio2_TxEn,
Radio2_RxEn => radio2_RxEn,
Radio2_RxHP => radio2_RxHP,
Radio2_LD => radio2_LD,
Radio2_24PA => radio2_24PA,
Radio2_5PA => radio2_5PA,
Radio2_ANTSW => radio2_ANTSW,
Radio2_LED => radio2_LED,
Radio2_ADC_RX_DCS => radio2_ADC_RX_DCS,
Radio2_ADC_RX_DFS => radio2_ADC_RX_DFS,
Radio2_ADC_RX_OTRA => radio2_ADC_RX_OTRA,
Radio2_ADC_RX_OTRB => radio2_ADC_RX_OTRB,
Radio2_ADC_RX_PWDNA => radio2_ADC_RX_PWDNA,
Radio2_ADC_RX_PWDNB => radio2_ADC_RX_PWDNB,
Radio2_DIPSW => radio2_DIPSW,
Radio2_RSSI_ADC_CLAMP => radio2_RSSI_ADC_CLAMP,
Radio2_RSSI_ADC_HIZ => radio2_RSSI_ADC_HIZ,
Radio2_RSSI_ADC_OTR => radio2_RSSI_ADC_OTR,
Radio2_RSSI_ADC_SLEEP => radio2_RSSI_ADC_SLEEP,
Radio2_RSSI_ADC_D => radio2_RSSI_ADC_D,
Radio2_TX_DAC_PLL_LOCK => radio2_TX_DAC_PLL_LOCK,
Radio2_TX_DAC_RESET => radio2_TX_DAC_RESET,
Radio2_SHDN_external => radio2_SHDN_external,
Radio2_TxEn_external => radio2_TxEn_external,
Radio2_RxEn_external => radio2_RxEn_external,
Radio2_RxHP_external => radio2_RxHP_external,
Radio2_TxGain => radio2_TxGain,
Radio2_TxStart => radio2_TxStart,
Radio3_interpfiltbypass => radio3_interpfiltbypass,
Radio3_decfiltbypass => radio3_decfiltbypass,
Radio3_SHDN => radio3_SHDN,
Radio3_TxEn => radio3_TxEn,
Radio3_RxEn => radio3_RxEn,
Radio3_RxHP => radio3_RxHP,
Radio3_LD => radio3_LD,
Radio3_24PA => radio3_24PA,
Radio3_5PA => radio3_5PA,
Radio3_ANTSW => radio3_ANTSW,
Radio3_LED => radio3_LED,
Radio3_ADC_RX_DCS => radio3_ADC_RX_DCS,
Radio3_ADC_RX_DFS => radio3_ADC_RX_DFS,
Radio3_ADC_RX_OTRA => radio3_ADC_RX_OTRA,
Radio3_ADC_RX_OTRB => radio3_ADC_RX_OTRB,
Radio3_ADC_RX_PWDNA => radio3_ADC_RX_PWDNA,
Radio3_ADC_RX_PWDNB => radio3_ADC_RX_PWDNB,
Radio3_DIPSW => radio3_DIPSW,
Radio3_RSSI_ADC_CLAMP => radio3_RSSI_ADC_CLAMP,
Radio3_RSSI_ADC_HIZ => radio3_RSSI_ADC_HIZ,
Radio3_RSSI_ADC_OTR => radio3_RSSI_ADC_OTR,
Radio3_RSSI_ADC_SLEEP => radio3_RSSI_ADC_SLEEP,
Radio3_RSSI_ADC_D => radio3_RSSI_ADC_D,
Radio3_TX_DAC_PLL_LOCK => radio3_TX_DAC_PLL_LOCK,
Radio3_TX_DAC_RESET => radio3_TX_DAC_RESET,
Radio3_SHDN_external => radio3_SHDN_external,
Radio3_TxEn_external => radio3_TxEn_external,
Radio3_RxEn_external => radio3_RxEn_external,
Radio3_RxHP_external => radio3_RxHP_external,
Radio3_TxGain => radio3_TxGain,
Radio3_TxStart => radio3_TxStart,
Radio4_interpfiltbypass => radio4_interpfiltbypass,
Radio4_decfiltbypass => radio4_decfiltbypass,
Radio4_SHDN => radio4_SHDN,
Radio4_TxEn => radio4_TxEn,
Radio4_RxEn => radio4_RxEn,
Radio4_RxHP => radio4_RxHP,
Radio4_LD => radio4_LD,
Radio4_24PA => radio4_24PA,
Radio4_5PA => radio4_5PA,
Radio4_ANTSW => radio4_ANTSW,
Radio4_LED => radio4_LED,
Radio4_ADC_RX_DCS => radio4_ADC_RX_DCS,
Radio4_ADC_RX_DFS => radio4_ADC_RX_DFS,
Radio4_ADC_RX_OTRA => radio4_ADC_RX_OTRA,
Radio4_ADC_RX_OTRB => radio4_ADC_RX_OTRB,
Radio4_ADC_RX_PWDNA => radio4_ADC_RX_PWDNA,
Radio4_ADC_RX_PWDNB => radio4_ADC_RX_PWDNB,
Radio4_DIPSW => radio4_DIPSW,
Radio4_RSSI_ADC_CLAMP => radio4_RSSI_ADC_CLAMP,
Radio4_RSSI_ADC_HIZ => radio4_RSSI_ADC_HIZ,
Radio4_RSSI_ADC_OTR => radio4_RSSI_ADC_OTR,
Radio4_RSSI_ADC_SLEEP => radio4_RSSI_ADC_SLEEP,
Radio4_RSSI_ADC_D => radio4_RSSI_ADC_D,
Radio4_TX_DAC_PLL_LOCK => radio4_TX_DAC_PLL_LOCK,
Radio4_TX_DAC_RESET => radio4_TX_DAC_RESET,
Radio4_SHDN_external => radio4_SHDN_external,
Radio4_TxEn_external => radio4_TxEn_external,
Radio4_RxEn_external => radio4_RxEn_external,
Radio4_RxHP_external => radio4_RxHP_external,
Radio4_TxGain => radio4_TxGain,
Radio4_TxStart => radio4_TxStart,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
------------------------------------------------------------------------------
-- radio_controller.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: radio_controller.vhd
-- Version: 1.20.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed Feb 06 13:11:09 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_00_a;
use plbv46_slave_single_v1_00_a.plbv46_slave_single;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity radio_controller is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
controller_logic_clk : out std_logic;
spi_clk : out std_logic;
data_out : out std_logic;
radio1_cs : out std_logic;
radio2_cs : out std_logic;
radio3_cs : out std_logic;
radio4_cs : out std_logic;
dac1_cs : out std_logic;
dac2_cs : out std_logic;
dac3_cs : out std_logic;
dac4_cs : out std_logic;
radio1_interpfiltbypass : out std_logic;
radio1_decfiltbypass : out std_logic;
radio1_SHDN : out std_logic;
radio1_TxEn : out std_logic;
radio1_RxEn : out std_logic;
radio1_RxHP : out std_logic;
radio1_LD : in std_logic;
radio1_24PA : out std_logic;
radio1_5PA : out std_logic;
radio1_ANTSW : out std_logic_vector(0 to 1);
radio1_LED : out std_logic_vector(0 to 2);
radio1_ADC_RX_DCS : out std_logic;
radio1_ADC_RX_DFS : out std_logic;
radio1_ADC_RX_OTRA : in std_logic;
radio1_ADC_RX_OTRB : in std_logic;
radio1_ADC_RX_PWDNA : out std_logic;
radio1_ADC_RX_PWDNB : out std_logic;
radio1_DIPSW : in std_logic_vector(0 to 3);
radio1_RSSI_ADC_CLAMP : out std_logic;
radio1_RSSI_ADC_HIZ : out std_logic;
radio1_RSSI_ADC_OTR : in std_logic;
radio1_RSSI_ADC_SLEEP : out std_logic;
radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio1_TX_DAC_PLL_LOCK : in std_logic;
radio1_TX_DAC_RESET : out std_logic;
radio1_SHDN_external : in std_logic;
radio1_TxEn_external : in std_logic;
radio1_RxEn_external : in std_logic;
radio1_RxHP_external : in std_logic;
radio1_TxGain : out std_logic_vector(0 to 5);
radio1_TxStart : out std_logic;
radio2_interpfiltbypass : out std_logic;
radio2_decfiltbypass : out std_logic;
radio2_SHDN : out std_logic;
radio2_TxEn : out std_logic;
radio2_RxEn : out std_logic;
radio2_RxHP : out std_logic;
radio2_LD : in std_logic;
radio2_24PA : out std_logic;
radio2_5PA : out std_logic;
radio2_ANTSW : out std_logic_vector(0 to 1);
radio2_LED : out std_logic_vector(0 to 2);
radio2_ADC_RX_DCS : out std_logic;
radio2_ADC_RX_DFS : out std_logic;
radio2_ADC_RX_OTRA : in std_logic;
radio2_ADC_RX_OTRB : in std_logic;
radio2_ADC_RX_PWDNA : out std_logic;
radio2_ADC_RX_PWDNB : out std_logic;
radio2_DIPSW : in std_logic_vector(0 to 3);
radio2_RSSI_ADC_CLAMP : out std_logic;
radio2_RSSI_ADC_HIZ : out std_logic;
radio2_RSSI_ADC_OTR : in std_logic;
radio2_RSSI_ADC_SLEEP : out std_logic;
radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio2_TX_DAC_PLL_LOCK : in std_logic;
radio2_TX_DAC_RESET : out std_logic;
radio2_SHDN_external : in std_logic;
radio2_TxEn_external : in std_logic;
radio2_RxEn_external : in std_logic;
radio2_RxHP_external : in std_logic;
radio2_TxGain : out std_logic_vector(0 to 5);
radio2_TxStart : out std_logic;
radio3_interpfiltbypass : out std_logic;
radio3_decfiltbypass : out std_logic;
radio3_SHDN : out std_logic;
radio3_TxEn : out std_logic;
radio3_RxEn : out std_logic;
radio3_RxHP : out std_logic;
radio3_LD : in std_logic;
radio3_24PA : out std_logic;
radio3_5PA : out std_logic;
radio3_ANTSW : out std_logic_vector(0 to 1);
radio3_LED : out std_logic_vector(0 to 2);
radio3_ADC_RX_DCS : out std_logic;
radio3_ADC_RX_DFS : out std_logic;
radio3_ADC_RX_OTRA : in std_logic;
radio3_ADC_RX_OTRB : in std_logic;
radio3_ADC_RX_PWDNA : out std_logic;
radio3_ADC_RX_PWDNB : out std_logic;
radio3_DIPSW : in std_logic_vector(0 to 3);
radio3_RSSI_ADC_CLAMP : out std_logic;
radio3_RSSI_ADC_HIZ : out std_logic;
radio3_RSSI_ADC_OTR : in std_logic;
radio3_RSSI_ADC_SLEEP : out std_logic;
radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio3_TX_DAC_PLL_LOCK : in std_logic;
radio3_TX_DAC_RESET : out std_logic;
radio3_SHDN_external : in std_logic;
radio3_TxEn_external : in std_logic;
radio3_RxEn_external : in std_logic;
radio3_RxHP_external : in std_logic;
radio3_TxGain : out std_logic_vector(0 to 5);
radio3_TxStart : out std_logic;
radio4_interpfiltbypass : out std_logic;
radio4_decfiltbypass : out std_logic;
radio4_SHDN : out std_logic;
radio4_TxEn : out std_logic;
radio4_RxEn : out std_logic;
radio4_RxHP : out std_logic;
radio4_LD : in std_logic;
radio4_24PA : out std_logic;
radio4_5PA : out std_logic;
radio4_ANTSW : out std_logic_vector(0 to 1);
radio4_LED : out std_logic_vector(0 to 2);
radio4_ADC_RX_DCS : out std_logic;
radio4_ADC_RX_DFS : out std_logic;
radio4_ADC_RX_OTRA : in std_logic;
radio4_ADC_RX_OTRB : in std_logic;
radio4_ADC_RX_PWDNA : out std_logic;
radio4_ADC_RX_PWDNB : out std_logic;
radio4_DIPSW : in std_logic_vector(0 to 3);
radio4_RSSI_ADC_CLAMP : out std_logic;
radio4_RSSI_ADC_HIZ : out std_logic;
radio4_RSSI_ADC_OTR : in std_logic;
radio4_RSSI_ADC_SLEEP : out std_logic;
radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio4_TX_DAC_PLL_LOCK : in std_logic;
radio4_TX_DAC_RESET : out std_logic;
radio4_SHDN_external : in std_logic;
radio4_TxEn_external : in std_logic;
radio4_RxEn_external : in std_logic;
radio4_RxHP_external : in std_logic;
radio4_TxGain : out std_logic_vector(0 to 5);
radio4_TxStart : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity radio_controller;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of radio_controller is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 17;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 17
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
controller_logic_clk : out std_logic;
spi_clk : out std_logic;
data_out : out std_logic;
Radio1_cs : out std_logic;
Radio2_cs : out std_logic;
Radio3_cs : out std_logic;
Radio4_cs : out std_logic;
Dac1_cs : out std_logic;
Dac2_cs : out std_logic;
Dac3_cs : out std_logic;
Dac4_cs : out std_logic;
Radio1_interpfiltbypass : out std_logic;
Radio1_decfiltbypass : out std_logic;
Radio1_SHDN : out std_logic;
Radio1_TxEn : out std_logic;
Radio1_RxEn : out std_logic;
Radio1_RxHP : out std_logic;
Radio1_LD : in std_logic;
Radio1_24PA : out std_logic;
Radio1_5PA : out std_logic;
Radio1_ANTSW : out std_logic_vector(0 to 1);
Radio1_LED : out std_logic_vector(0 to 2);
Radio1_ADC_RX_DCS : out std_logic;
Radio1_ADC_RX_DFS : out std_logic;
Radio1_ADC_RX_OTRA : in std_logic;
Radio1_ADC_RX_OTRB : in std_logic;
Radio1_ADC_RX_PWDNA : out std_logic;
Radio1_ADC_RX_PWDNB : out std_logic;
Radio1_DIPSW : in std_logic_vector(0 to 3);
Radio1_RSSI_ADC_CLAMP : out std_logic;
Radio1_RSSI_ADC_HIZ : out std_logic;
Radio1_RSSI_ADC_OTR : in std_logic;
Radio1_RSSI_ADC_SLEEP : out std_logic;
Radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio1_TX_DAC_PLL_LOCK : in std_logic;
Radio1_TX_DAC_RESET : out std_logic;
Radio1_SHDN_external : in std_logic;
Radio1_TxEn_external : in std_logic;
Radio1_RxEn_external : in std_logic;
Radio1_RxHP_external : in std_logic;
Radio1_TxGain : out std_logic_vector(0 to 5);
Radio1_TxStart : out std_logic;
Radio2_interpfiltbypass : out std_logic;
Radio2_decfiltbypass : out std_logic;
Radio2_SHDN : out std_logic;
Radio2_TxEn : out std_logic;
Radio2_RxEn : out std_logic;
Radio2_RxHP : out std_logic;
Radio2_LD : in std_logic;
Radio2_24PA : out std_logic;
Radio2_5PA : out std_logic;
Radio2_ANTSW : out std_logic_vector(0 to 1);
Radio2_LED : out std_logic_vector(0 to 2);
Radio2_ADC_RX_DCS : out std_logic;
Radio2_ADC_RX_DFS : out std_logic;
Radio2_ADC_RX_OTRA : in std_logic;
Radio2_ADC_RX_OTRB : in std_logic;
Radio2_ADC_RX_PWDNA : out std_logic;
Radio2_ADC_RX_PWDNB : out std_logic;
Radio2_DIPSW : in std_logic_vector(0 to 3);
Radio2_RSSI_ADC_CLAMP : out std_logic;
Radio2_RSSI_ADC_HIZ : out std_logic;
Radio2_RSSI_ADC_OTR : in std_logic;
Radio2_RSSI_ADC_SLEEP : out std_logic;
Radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio2_TX_DAC_PLL_LOCK : in std_logic;
Radio2_TX_DAC_RESET : out std_logic;
Radio2_SHDN_external : in std_logic;
Radio2_TxEn_external : in std_logic;
Radio2_RxEn_external : in std_logic;
Radio2_RxHP_external : in std_logic;
Radio2_TxGain : out std_logic_vector(0 to 5);
Radio2_TxStart : out std_logic;
Radio3_interpfiltbypass : out std_logic;
Radio3_decfiltbypass : out std_logic;
Radio3_SHDN : out std_logic;
Radio3_TxEn : out std_logic;
Radio3_RxEn : out std_logic;
Radio3_RxHP : out std_logic;
Radio3_LD : in std_logic;
Radio3_24PA : out std_logic;
Radio3_5PA : out std_logic;
Radio3_ANTSW : out std_logic_vector(0 to 1);
Radio3_LED : out std_logic_vector(0 to 2);
Radio3_ADC_RX_DCS : out std_logic;
Radio3_ADC_RX_DFS : out std_logic;
Radio3_ADC_RX_OTRA : in std_logic;
Radio3_ADC_RX_OTRB : in std_logic;
Radio3_ADC_RX_PWDNA : out std_logic;
Radio3_ADC_RX_PWDNB : out std_logic;
Radio3_DIPSW : in std_logic_vector(0 to 3);
Radio3_RSSI_ADC_CLAMP : out std_logic;
Radio3_RSSI_ADC_HIZ : out std_logic;
Radio3_RSSI_ADC_OTR : in std_logic;
Radio3_RSSI_ADC_SLEEP : out std_logic;
Radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio3_TX_DAC_PLL_LOCK : in std_logic;
Radio3_TX_DAC_RESET : out std_logic;
Radio3_SHDN_external : in std_logic;
Radio3_TxEn_external : in std_logic;
Radio3_RxEn_external : in std_logic;
Radio3_RxHP_external : in std_logic;
Radio3_TxGain : out std_logic_vector(0 to 5);
Radio3_TxStart : out std_logic;
Radio4_interpfiltbypass : out std_logic;
Radio4_decfiltbypass : out std_logic;
Radio4_SHDN : out std_logic;
Radio4_TxEn : out std_logic;
Radio4_RxEn : out std_logic;
Radio4_RxHP : out std_logic;
Radio4_LD : in std_logic;
Radio4_24PA : out std_logic;
Radio4_5PA : out std_logic;
Radio4_ANTSW : out std_logic_vector(0 to 1);
Radio4_LED : out std_logic_vector(0 to 2);
Radio4_ADC_RX_DCS : out std_logic;
Radio4_ADC_RX_DFS : out std_logic;
Radio4_ADC_RX_OTRA : in std_logic;
Radio4_ADC_RX_OTRB : in std_logic;
Radio4_ADC_RX_PWDNA : out std_logic;
Radio4_ADC_RX_PWDNB : out std_logic;
Radio4_DIPSW : in std_logic_vector(0 to 3);
Radio4_RSSI_ADC_CLAMP : out std_logic;
Radio4_RSSI_ADC_HIZ : out std_logic;
Radio4_RSSI_ADC_OTR : in std_logic;
Radio4_RSSI_ADC_SLEEP : out std_logic;
Radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio4_TX_DAC_PLL_LOCK : in std_logic;
Radio4_TX_DAC_RESET : out std_logic;
Radio4_SHDN_external : in std_logic;
Radio4_TxEn_external : in std_logic;
Radio4_RxEn_external : in std_logic;
Radio4_RxHP_external : in std_logic;
Radio4_TxGain : out std_logic_vector(0 to 5);
Radio4_TxStart : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_00_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
controller_logic_clk => controller_logic_clk,
spi_clk => spi_clk,
data_out => data_out,
Radio1_cs => radio1_cs,
Radio2_cs => radio2_cs,
Radio3_cs => radio3_cs,
Radio4_cs => radio4_cs,
Dac1_cs => dac1_cs,
Dac2_cs => dac2_cs,
Dac3_cs => dac3_cs,
Dac4_cs => dac4_cs,
Radio1_interpfiltbypass => radio1_interpfiltbypass,
Radio1_decfiltbypass => radio1_decfiltbypass,
Radio1_SHDN => radio1_SHDN,
Radio1_TxEn => radio1_TxEn,
Radio1_RxEn => radio1_RxEn,
Radio1_RxHP => radio1_RxHP,
Radio1_LD => radio1_LD,
Radio1_24PA => radio1_24PA,
Radio1_5PA => radio1_5PA,
Radio1_ANTSW => radio1_ANTSW,
Radio1_LED => radio1_LED,
Radio1_ADC_RX_DCS => radio1_ADC_RX_DCS,
Radio1_ADC_RX_DFS => radio1_ADC_RX_DFS,
Radio1_ADC_RX_OTRA => radio1_ADC_RX_OTRA,
Radio1_ADC_RX_OTRB => radio1_ADC_RX_OTRB,
Radio1_ADC_RX_PWDNA => radio1_ADC_RX_PWDNA,
Radio1_ADC_RX_PWDNB => radio1_ADC_RX_PWDNB,
Radio1_DIPSW => radio1_DIPSW,
Radio1_RSSI_ADC_CLAMP => radio1_RSSI_ADC_CLAMP,
Radio1_RSSI_ADC_HIZ => radio1_RSSI_ADC_HIZ,
Radio1_RSSI_ADC_OTR => radio1_RSSI_ADC_OTR,
Radio1_RSSI_ADC_SLEEP => radio1_RSSI_ADC_SLEEP,
Radio1_RSSI_ADC_D => radio1_RSSI_ADC_D,
Radio1_TX_DAC_PLL_LOCK => radio1_TX_DAC_PLL_LOCK,
Radio1_TX_DAC_RESET => radio1_TX_DAC_RESET,
Radio1_SHDN_external => radio1_SHDN_external,
Radio1_TxEn_external => radio1_TxEn_external,
Radio1_RxEn_external => radio1_RxEn_external,
Radio1_RxHP_external => radio1_RxHP_external,
Radio1_TxGain => radio1_TxGain,
Radio1_TxStart => radio1_TxStart,
Radio2_interpfiltbypass => radio2_interpfiltbypass,
Radio2_decfiltbypass => radio2_decfiltbypass,
Radio2_SHDN => radio2_SHDN,
Radio2_TxEn => radio2_TxEn,
Radio2_RxEn => radio2_RxEn,
Radio2_RxHP => radio2_RxHP,
Radio2_LD => radio2_LD,
Radio2_24PA => radio2_24PA,
Radio2_5PA => radio2_5PA,
Radio2_ANTSW => radio2_ANTSW,
Radio2_LED => radio2_LED,
Radio2_ADC_RX_DCS => radio2_ADC_RX_DCS,
Radio2_ADC_RX_DFS => radio2_ADC_RX_DFS,
Radio2_ADC_RX_OTRA => radio2_ADC_RX_OTRA,
Radio2_ADC_RX_OTRB => radio2_ADC_RX_OTRB,
Radio2_ADC_RX_PWDNA => radio2_ADC_RX_PWDNA,
Radio2_ADC_RX_PWDNB => radio2_ADC_RX_PWDNB,
Radio2_DIPSW => radio2_DIPSW,
Radio2_RSSI_ADC_CLAMP => radio2_RSSI_ADC_CLAMP,
Radio2_RSSI_ADC_HIZ => radio2_RSSI_ADC_HIZ,
Radio2_RSSI_ADC_OTR => radio2_RSSI_ADC_OTR,
Radio2_RSSI_ADC_SLEEP => radio2_RSSI_ADC_SLEEP,
Radio2_RSSI_ADC_D => radio2_RSSI_ADC_D,
Radio2_TX_DAC_PLL_LOCK => radio2_TX_DAC_PLL_LOCK,
Radio2_TX_DAC_RESET => radio2_TX_DAC_RESET,
Radio2_SHDN_external => radio2_SHDN_external,
Radio2_TxEn_external => radio2_TxEn_external,
Radio2_RxEn_external => radio2_RxEn_external,
Radio2_RxHP_external => radio2_RxHP_external,
Radio2_TxGain => radio2_TxGain,
Radio2_TxStart => radio2_TxStart,
Radio3_interpfiltbypass => radio3_interpfiltbypass,
Radio3_decfiltbypass => radio3_decfiltbypass,
Radio3_SHDN => radio3_SHDN,
Radio3_TxEn => radio3_TxEn,
Radio3_RxEn => radio3_RxEn,
Radio3_RxHP => radio3_RxHP,
Radio3_LD => radio3_LD,
Radio3_24PA => radio3_24PA,
Radio3_5PA => radio3_5PA,
Radio3_ANTSW => radio3_ANTSW,
Radio3_LED => radio3_LED,
Radio3_ADC_RX_DCS => radio3_ADC_RX_DCS,
Radio3_ADC_RX_DFS => radio3_ADC_RX_DFS,
Radio3_ADC_RX_OTRA => radio3_ADC_RX_OTRA,
Radio3_ADC_RX_OTRB => radio3_ADC_RX_OTRB,
Radio3_ADC_RX_PWDNA => radio3_ADC_RX_PWDNA,
Radio3_ADC_RX_PWDNB => radio3_ADC_RX_PWDNB,
Radio3_DIPSW => radio3_DIPSW,
Radio3_RSSI_ADC_CLAMP => radio3_RSSI_ADC_CLAMP,
Radio3_RSSI_ADC_HIZ => radio3_RSSI_ADC_HIZ,
Radio3_RSSI_ADC_OTR => radio3_RSSI_ADC_OTR,
Radio3_RSSI_ADC_SLEEP => radio3_RSSI_ADC_SLEEP,
Radio3_RSSI_ADC_D => radio3_RSSI_ADC_D,
Radio3_TX_DAC_PLL_LOCK => radio3_TX_DAC_PLL_LOCK,
Radio3_TX_DAC_RESET => radio3_TX_DAC_RESET,
Radio3_SHDN_external => radio3_SHDN_external,
Radio3_TxEn_external => radio3_TxEn_external,
Radio3_RxEn_external => radio3_RxEn_external,
Radio3_RxHP_external => radio3_RxHP_external,
Radio3_TxGain => radio3_TxGain,
Radio3_TxStart => radio3_TxStart,
Radio4_interpfiltbypass => radio4_interpfiltbypass,
Radio4_decfiltbypass => radio4_decfiltbypass,
Radio4_SHDN => radio4_SHDN,
Radio4_TxEn => radio4_TxEn,
Radio4_RxEn => radio4_RxEn,
Radio4_RxHP => radio4_RxHP,
Radio4_LD => radio4_LD,
Radio4_24PA => radio4_24PA,
Radio4_5PA => radio4_5PA,
Radio4_ANTSW => radio4_ANTSW,
Radio4_LED => radio4_LED,
Radio4_ADC_RX_DCS => radio4_ADC_RX_DCS,
Radio4_ADC_RX_DFS => radio4_ADC_RX_DFS,
Radio4_ADC_RX_OTRA => radio4_ADC_RX_OTRA,
Radio4_ADC_RX_OTRB => radio4_ADC_RX_OTRB,
Radio4_ADC_RX_PWDNA => radio4_ADC_RX_PWDNA,
Radio4_ADC_RX_PWDNB => radio4_ADC_RX_PWDNB,
Radio4_DIPSW => radio4_DIPSW,
Radio4_RSSI_ADC_CLAMP => radio4_RSSI_ADC_CLAMP,
Radio4_RSSI_ADC_HIZ => radio4_RSSI_ADC_HIZ,
Radio4_RSSI_ADC_OTR => radio4_RSSI_ADC_OTR,
Radio4_RSSI_ADC_SLEEP => radio4_RSSI_ADC_SLEEP,
Radio4_RSSI_ADC_D => radio4_RSSI_ADC_D,
Radio4_TX_DAC_PLL_LOCK => radio4_TX_DAC_PLL_LOCK,
Radio4_TX_DAC_RESET => radio4_TX_DAC_RESET,
Radio4_SHDN_external => radio4_SHDN_external,
Radio4_TxEn_external => radio4_TxEn_external,
Radio4_RxEn_external => radio4_RxEn_external,
Radio4_RxHP_external => radio4_RxHP_external,
Radio4_TxGain => radio4_TxGain,
Radio4_TxStart => radio4_TxStart,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
------------------------------------------------------------------------------
-- Copyright (c) 2012 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: delay_controller_wrap.vhd
-- / / Date Last Modified: Mar 30, 2016
-- /___/ /\ Date Created: Jan 8, 2013
-- \ \ / \
-- \___\/\___\
--
--Device: 7 Series
--Purpose: Controls delays on a per-bit basis
-- Number of bits from each seres set via an attribute
--
--Reference: XAPP585.pdf
--
--Revision History:
-- Rev 1.0 - First created (nicks)
--
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity delay_controller_wrap is generic (
S : integer := 4) ; -- Set the number of bits
port (
m_datain : in std_logic_vector(S-1 downto 0) ; -- Inputs from master serdes
s_datain : in std_logic_vector(S-1 downto 0) ; -- Inputs from slave serdes
enable_phase_detector : in std_logic ; -- Enables the phase detector logic when high
enable_monitor : in std_logic ; -- Enables the eye monitoring logic when high
reset : in std_logic ; -- Reset line synchronous to clk
clk : in std_logic ; -- Global/Regional clock
c_delay_in : in std_logic_vector(4 downto 0) ; -- delay value found on clock line
m_delay_out : out std_logic_vector(4 downto 0) ; -- Master delay control value
s_delay_out : out std_logic_vector(4 downto 0) ; -- Master delay control value
data_out : out std_logic_vector(S-1 downto 0) ; -- Output data
results : out std_logic_vector(31 downto 0) ; -- eye monitor result data
m_delay_1hot : out std_logic_vector(31 downto 0) ; -- Master delay control value as a one-hot vector
debug : out std_logic_vector(1 downto 0) ; -- debug data
del_mech : in std_logic ; -- changes delay mechanism slightly at higher bit rates
bt_val : in std_logic_vector(4 downto 0)) ; -- Calculated bit time value for slave devices
end delay_controller_wrap ;
architecture arch_delay_controller_wrap of delay_controller_wrap is
signal mdataouta : std_logic_vector(S-1 downto 0) ;
signal mdataoutb : std_logic ;
signal mdataoutc : std_logic_vector(S-1 downto 0) ;
signal sdataouta : std_logic_vector(S-1 downto 0) ;
signal sdataoutb : std_logic ;
signal sdataoutc : std_logic_vector(S-1 downto 0) ;
signal s_ovflw : std_logic ;
signal m_delay_mux : std_logic_vector(1 downto 0) ;
signal s_delay_mux : std_logic_vector(1 downto 0) ;
signal data_mux : std_logic ;
signal dec_run : std_logic ;
signal inc_run : std_logic ;
signal eye_run : std_logic ;
signal s_state : std_logic_vector(4 downto 0) ;
signal pdcount : std_logic_vector(5 downto 0) ;
signal m_delay_val_int : std_logic_vector(4 downto 0) ;
signal s_delay_val_int : std_logic_vector(4 downto 0) ;
signal s_delay_val_eye : std_logic_vector(4 downto 0) ;
signal meq_max : std_logic ;
signal meq_min : std_logic ;
signal pd_max : std_logic ;
signal pd_min : std_logic ;
signal delay_change : std_logic ;
signal msxoria : std_logic_vector(7 downto 0) ;
signal msxorda : std_logic_vector(7 downto 0) ;
signal action : std_logic_vector(1 downto 0) ;
signal msxor_cti : std_logic_vector(1 downto 0) ;
signal msxor_ctd : std_logic_vector(1 downto 0) ;
signal msxor_ctix : std_logic_vector(1 downto 0) ;
signal msxor_ctdx : std_logic_vector(1 downto 0) ;
signal msxor_ctiy : std_logic_vector(2 downto 0) ;
signal msxor_ctdy : std_logic_vector(2 downto 0) ;
signal match : std_logic_vector(7 downto 0) ;
signal shifter : std_logic_vector(31 downto 0) := (0=>'1', others => '0') ;
signal pd_hold : std_logic_vector(7 downto 0) ;
signal res_int : std_logic_vector(31 downto 0) := (others => '0') ;
signal bt_val_d2 : std_logic_vector(4 downto 0) ;
begin
m_delay_out <= m_delay_val_int ;
s_delay_out <= s_delay_val_int ;
results <= res_int ;
debug <= action ;
bt_val_d2 <= '0' & bt_val(4 downto 1) ;
loop2 : if S /= 8 generate -- phase detector filter, works on changes in data only
loop3 : for i in S to 7 generate
msxoria(i) <= '0' ; -- unused early bits
msxorda(i) <= '0' ; -- unused late bits
end generate ;
end generate ;
loop0 : for i in 0 to S-2 generate
msxoria(i+1) <= ((not s_ovflw and ((mdataouta(i) and not mdataouta(i+1) and not sdataouta(i)) or (not mdataouta(i) and mdataouta(i+1) and sdataouta(i)))) or
( s_ovflw and ((mdataouta(i) and not mdataouta(i+1) and not sdataouta(i+1)) or (not mdataouta(i) and mdataouta(i+1) and sdataouta(i+1))))) ; -- early bits
msxorda(i+1) <= ((not s_ovflw and ((mdataouta(i) and not mdataouta(i+1) and sdataouta(i)) or (not mdataouta(i) and mdataouta(i+1) and not sdataouta(i))))) or
( s_ovflw and ((mdataouta(i) and not mdataouta(i+1) and sdataouta(i+1)) or (not mdataouta(i) and mdataouta(i+1) and not sdataouta(i+1)))) ; -- late bits
end generate ;
msxoria(0) <= ((not s_ovflw and ((mdataoutb and not mdataouta(0) and not sdataoutb) or (not mdataoutb and mdataouta(0) and sdataoutb))) or -- first early bit
( s_ovflw and ((mdataoutb and not mdataouta(0) and not sdataouta(0)) or (not mdataoutb and mdataouta(0) and sdataouta(0))))) ;
msxorda(0) <= ((not s_ovflw and ((mdataoutb and not mdataouta(0) and sdataoutb) or (not mdataoutb and mdataouta(0) and not sdataoutb)))) or -- first late bit
( s_ovflw and ((mdataoutb and not mdataouta(0) and sdataouta(0)) or (not mdataoutb and mdataouta(0) and not sdataouta(0)))) ;
process (clk) begin
if clk'event and clk = '1' then -- generate number of incs or decs for low 4 bits
case (msxoria(3 downto 0)) is
when X"0" => msxor_cti <= "00" ;
when X"1" => msxor_cti <= "01" ;
when X"2" => msxor_cti <= "01" ;
when X"3" => msxor_cti <= "10" ;
when X"4" => msxor_cti <= "01" ;
when X"5" => msxor_cti <= "10" ;
when X"6" => msxor_cti <= "10" ;
when X"8" => msxor_cti <= "01" ;
when X"9" => msxor_cti <= "10" ;
when X"A" => msxor_cti <= "10" ;
when X"C" => msxor_cti <= "10" ;
when others => msxor_cti <= "11" ;
end case ;
case (msxorda(3 downto 0)) is
when X"0" => msxor_ctd <= "00" ;
when X"1" => msxor_ctd <= "01" ;
when X"2" => msxor_ctd <= "01" ;
when X"3" => msxor_ctd <= "10" ;
when X"4" => msxor_ctd <= "01" ;
when X"5" => msxor_ctd <= "10" ;
when X"6" => msxor_ctd <= "10" ;
when X"8" => msxor_ctd <= "01" ;
when X"9" => msxor_ctd <= "10" ;
when X"A" => msxor_ctd <= "10" ;
when X"C" => msxor_ctd <= "10" ;
when others => msxor_ctd <= "11" ;
end case ;
case (msxoria(7 downto 4)) is -- generate number of incs or decs for high n bits, max 4
when X"0" => msxor_ctix <= "00" ;
when X"1" => msxor_ctix <= "01" ;
when X"2" => msxor_ctix <= "01" ;
when X"3" => msxor_ctix <= "10" ;
when X"4" => msxor_ctix <= "01" ;
when X"5" => msxor_ctix <= "10" ;
when X"6" => msxor_ctix <= "10" ;
when X"8" => msxor_ctix <= "01" ;
when X"9" => msxor_ctix <= "10" ;
when X"A" => msxor_ctix <= "10" ;
when X"C" => msxor_ctix <= "10" ;
when others => msxor_ctix <= "11" ;
end case ;
case (msxorda(7 downto 4)) is
when X"0" => msxor_ctdx <= "00" ;
when X"1" => msxor_ctdx <= "01" ;
when X"2" => msxor_ctdx <= "01" ;
when X"3" => msxor_ctdx <= "10" ;
when X"4" => msxor_ctdx <= "01" ;
when X"5" => msxor_ctdx <= "10" ;
when X"6" => msxor_ctdx <= "10" ;
when X"8" => msxor_ctdx <= "01" ;
when X"9" => msxor_ctdx <= "10" ;
when X"A" => msxor_ctdx <= "10" ;
when X"C" => msxor_ctdx <= "10" ;
when others => msxor_ctdx <= "11" ;
end case ;
end if ;
end process ;
msxor_ctiy <= ('0' & msxor_cti) + ('0' & msxor_ctix) ;
msxor_ctdy <= ('0' & msxor_ctd) + ('0' & msxor_ctdx) ;
process (clk) begin
if clk'event and clk = '1' then
if msxor_ctiy = msxor_ctdy then
action <= "00" ;
elsif msxor_ctiy > msxor_ctdy then
action <= "01" ;
else
action <= "10" ;
end if ;
end if ;
end process ;
process (clk) begin
if clk'event and clk = '1' then
mdataouta <= m_datain ;
mdataoutb <= mdataouta(S-1) ;
sdataouta <= s_datain ;
sdataoutb <= sdataouta(S-1) ;
end if ;
end process ;
process (clk) begin
if clk'event and clk = '1' then -- per bit delay shift state machine
if reset = '1' then
s_ovflw <= '0' ;
pdcount <= "100000" ;
m_delay_val_int <= c_delay_in ; -- initial master delay
s_delay_val_int <= "00000" ; -- initial slave delay
data_mux <= '0' ;
m_delay_mux <= "01" ;
s_delay_mux <= "01" ;
s_state <= "00000" ;
inc_run <= '0' ;
dec_run <= '0' ;
eye_run <= '0' ;
pd_hold <= "00000000" ;
s_delay_val_eye <= "00000" ;
else
case (m_delay_mux) is
when "00" => mdataoutc <= mdataouta(S-2 downto 0) & mdataoutb ;
when "10" => mdataoutc <= m_datain(0) & mdataouta(S-1 downto 1) ;
when others => mdataoutc <= mdataouta ;
end case ;
case (s_delay_mux) is
when "00" => sdataoutc <= sdataouta(S-2 downto 0) & sdataoutb ;
when "10" => sdataoutc <= s_datain(0) & sdataouta(S-1 downto 1) ;
when others => sdataoutc <= sdataouta ;
end case ;
if m_delay_val_int = bt_val then
meq_max <= '1' ;
else
meq_max <= '0' ;
end if ;
if m_delay_val_int = "00000" then
meq_min <= '1' ;
else
meq_min <= '0' ;
end if ;
if pdcount = "111111" and pd_max = '0' and delay_change = '0' then
pd_max <= '1' ;
else
pd_max <= '0' ;
end if ;
if pdcount = "000000" and pd_min = '0' and delay_change = '0' then
pd_min <= '1' ;
else
pd_min <= '0' ;
end if ;
if delay_change = '1' or inc_run = '1' or dec_run = '1' or eye_run = '1' then
pd_hold <= "11111111" ;
pdcount <= "100000" ;
elsif pd_hold(7) = '1' then
pdcount <= "100000" ;
pd_hold <= pd_hold(6 downto 0) & '0' ;
elsif action(0) = '1' and pdcount /= "111111" then -- increment filter count
pdcount <= pdcount + 1 ;
elsif action(1) = '1' and pdcount /= "000000" then -- decrement filter count
pdcount <= pdcount - 1 ;
end if ;
if ((enable_phase_detector = '1' and pd_max = '1' and delay_change = '0') or inc_run = '1') then -- increment delays, check for master delay = max
delay_change <= '1' ;
if meq_max = '0' and inc_run = '0' then
m_delay_val_int <= m_delay_val_int + 1 ;
else -- master is max
s_state(3 downto 0) <= s_state(3 downto 0) + 1 ;
case (s_state(3 downto 0)) is
when "0000" => inc_run <= '1' ; s_delay_val_int <= bt_val ; -- indicate state machine running and set slave delay to bit time
when "0110" => data_mux <= '1' ; m_delay_val_int <= "00000" ; -- change data mux over to forward slave data and set master delay to zero
when "1001" => m_delay_mux <= m_delay_mux - 1 ; -- change master delay mux over to forward with a 1-bit less advance
when "1110" => data_mux <= '0' ; -- change data mux over to forward master data
when "1111" => s_delay_mux <= m_delay_mux ; inc_run <= '0' ; -- change slave delay mux over to forward with a 1-bit less advance
when others => inc_run <= '1' ;
end case ;
end if ;
elsif ((enable_phase_detector = '1' and pd_min = '1' and delay_change = '0') or dec_run = '1') then -- decrement delays, check for master delay = 0
delay_change <= '1' ;
if meq_min = '0' and dec_run = '0' then
m_delay_val_int <= m_delay_val_int - 1 ;
else -- master is zero
s_state(3 downto 0) <= s_state(3 downto 0) + 1 ;
case (s_state(3 downto 0)) is
when "0000" => dec_run <= '1' ; s_delay_val_int <= "00000" ; -- indicate state machine running and set slave delay to zero
when "0110" => data_mux <= '1' ; m_delay_val_int <= bt_val ; -- change data mux over to forward slave data and set master delay to bit time
when "1001" => m_delay_mux <= m_delay_mux + 1 ; -- change master delay mux over to forward with a 1-bit more advance
when "1110" => data_mux <= '0' ; -- change data mux over to forward master data
when "1111" => s_delay_mux <= m_delay_mux ; dec_run <= '0' ; -- change slave delay mux over to forward with a 1-bit less advance
when others => dec_run <= '1' ;
end case ;
end if ;
elsif enable_monitor = '1' and (eye_run = '1' or delay_change = '1') then
delay_change <= '0' ;
s_state <= s_state + 1 ;
case (s_state) is
when "00000" => eye_run <= '1' ; s_delay_val_int <= s_delay_val_eye ; -- indicate state machine running and set slave delay to monitor value
when "10110" => if match = "11111111" then res_int <= res_int or shifter ; -- set or clear result bit
else res_int <= res_int and not shifter ; end if ;
if s_delay_val_eye = bt_val then -- only monitor active taps, ie as far as btval
shifter <= (0=>'1',others=>'0') ; s_delay_val_eye <= "00000" ;
else shifter <= shifter(30 downto 0) & shifter(31) ;
s_delay_val_eye <= s_delay_val_eye + 1 ; end if ;
eye_run <= '0' ; s_state <= "00000" ;
when others => eye_run <= '1' ;
end case ;
else
delay_change <= '0' ;
if (m_delay_val_int >= bt_val_d2) and del_mech = '0' then -- set slave delay to 1/2 bit period beyond or behind the master delay
s_delay_val_int <= m_delay_val_int - bt_val_d2 ;
s_ovflw <= '0' ;
else
s_delay_val_int <= m_delay_val_int + bt_val_d2 ; -- slave always ahead when del_mech is '1'
s_ovflw <= '1' ;
end if ;
end if ;
if enable_phase_detector = '0' and delay_change = '0' then
delay_change <= '1' ;
end if ;
end if ;
if enable_phase_detector = '1' then
if data_mux = '0' then
data_out <= mdataoutc ;
else
data_out <= sdataoutc ;
end if ;
else
data_out <= m_datain ;
end if ;
end if ;
end process ;
process (clk) begin
if clk'event and clk = '1' then
if mdataouta = sdataouta then
match <= match(6 downto 0) & '1' ;
else
match <= match(6 downto 0) & '0' ;
end if ;
end if ;
end process ;
m_delay_1hot <= X"00000001" when m_delay_val_int = "00000" else
X"00000002" when m_delay_val_int = "00001" else
X"00000004" when m_delay_val_int = "00010" else
X"00000008" when m_delay_val_int = "00011" else
X"00000010" when m_delay_val_int = "00100" else
X"00000020" when m_delay_val_int = "00101" else
X"00000040" when m_delay_val_int = "00110" else
X"00000080" when m_delay_val_int = "00111" else
X"00000100" when m_delay_val_int = "01000" else
X"00000200" when m_delay_val_int = "01001" else
X"00000400" when m_delay_val_int = "01010" else
X"00000800" when m_delay_val_int = "01011" else
X"00001000" when m_delay_val_int = "01100" else
X"00002000" when m_delay_val_int = "01101" else
X"00004000" when m_delay_val_int = "01110" else
X"00008000" when m_delay_val_int = "01111" else
X"00010000" when m_delay_val_int = "10000" else
X"00020000" when m_delay_val_int = "10001" else
X"00040000" when m_delay_val_int = "10010" else
X"00080000" when m_delay_val_int = "10011" else
X"00100000" when m_delay_val_int = "10100" else
X"00200000" when m_delay_val_int = "10101" else
X"00400000" when m_delay_val_int = "10110" else
X"00800000" when m_delay_val_int = "10111" else
X"01000000" when m_delay_val_int = "11000" else
X"02000000" when m_delay_val_int = "11001" else
X"04000000" when m_delay_val_int = "11010" else
X"08000000" when m_delay_val_int = "11011" else
X"10000000" when m_delay_val_int = "11100" else
X"20000000" when m_delay_val_int = "11101" else
X"40000000" when m_delay_val_int = "11110" else
X"80000000" ;
end arch_delay_controller_wrap ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2589.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02589ent IS
END c13s03b01x00p02n01i02589ent;
ARCHITECTURE c13s03b01x00p02n01i02589arch OF c13s03b01x00p02n01i02589ent IS
BEGIN
TESTING: PROCESS
variable k+ : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02589 - Identifier can not end with '+'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02589arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2589.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02589ent IS
END c13s03b01x00p02n01i02589ent;
ARCHITECTURE c13s03b01x00p02n01i02589arch OF c13s03b01x00p02n01i02589ent IS
BEGIN
TESTING: PROCESS
variable k+ : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02589 - Identifier can not end with '+'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02589arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2589.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02589ent IS
END c13s03b01x00p02n01i02589ent;
ARCHITECTURE c13s03b01x00p02n01i02589arch OF c13s03b01x00p02n01i02589ent IS
BEGIN
TESTING: PROCESS
variable k+ : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02589 - Identifier can not end with '+'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02589arch;
|
-- Dmemory module (implements the data
-- memory for the MIPS computer)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY dmemory IS
PORT( read_data : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
address : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
write_data : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
MemRead, Memwrite : IN STD_LOGIC;
clock,reset : IN STD_LOGIC );
END dmemory;
ARCHITECTURE behavior OF dmemory IS
SIGNAL D_read_data : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL write_clock : STD_LOGIC;
BEGIN
data_memory : altsyncram
GENERIC MAP (
operation_mode => "SINGLE_PORT",
width_a => 32,
widthad_a => 8,
lpm_type => "altsyncram",
outdata_reg_a => "UNREGISTERED",
init_file => "dmemory.mif",
intended_device_family => "Cyclone"
)
PORT MAP (
wren_a => memwrite,
clock0 => write_clock,
address_a => address,
data_a => write_data,
q_a => D_read_data );
-- Load memory address register with write clock
write_clock <= NOT clock;
PROCESS
BEGIN
WAIT UNTIL clock'EVENT AND clock='1';
read_data <= D_read_data;
END PROCESS;
END behavior;
|
LIBRARY ieee;
-- LIBRARY arithmetic;
PACKAGE BODY std_logic_arith IS
USE ieee.std_logic_1164.ALL;
-- USE arithmetic.utils.all;
-------------------------------------------------------------------
-- Local Types
-------------------------------------------------------------------
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
TYPE stdlogic_boolean_table IS ARRAY(std_ulogic, std_ulogic) OF BOOLEAN;
--------------------------------------------------------------------
--------------------------------------------------------------------
-- FUNCTIONS DEFINED FOR SYNTHESIS
--------------------------------------------------------------------
--------------------------------------------------------------------
FUNCTION std_ulogic_wired_or ( input : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := '-'; -- weakest state default
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ---------------------------------------------------------
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | U |
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'X', 'X', '0', '1', '0', 'X', '0', '1', '0' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ), -- | Z |
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'X', 'X', '0', '1', '0', 'X', '0', '1', '0' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ) -- | D |
);
BEGIN
-- Iterate through all inputs
FOR i IN input'range LOOP
result := resolution_table(result, input(i));
END LOOP;
-- Return the resultant value
RETURN result;
END std_ulogic_wired_or;
FUNCTION std_ulogic_wired_and ( input : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := '-'; -- weakest state default
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ---------------------------------------------------------
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | U |
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'X', 'X', '0', '1', '1', 'X', '0', '1', '1' ), -- | 1 |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ), -- | Z |
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'X', 'X', '0', '1', '1', 'X', '0', '1', '1' ), -- | H |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ) -- | D |
);
BEGIN
-- Iterate through all inputs
FOR i IN input'range LOOP
result := resolution_table(result, input(i));
END LOOP;
-- Return the resultant value
RETURN result;
END std_ulogic_wired_and;
--
-- MGC base level functions
--
--
-- Convert Base Type to Integer
--
FUNCTION to_integer (arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION to_integer (arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION to_integer (arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL IS
VARIABLE tmp : SIGNED( arg1'length DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : NATURAL;
BEGIN
tmp := '0' & SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION TO_INTEGER (arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE return_int,x_tmp : INTEGER := 0;
BEGIN
ASSERT arg1'length > 0
REPORT "NULL vector, returning 0"
SEVERITY NOTE;
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT arg1'length <= 32 -- implementation dependent limit
REPORT "vector too large, conversion may cause overflow"
SEVERITY WARNING;
IF x /= 0 THEN
x_tmp := 1;
END IF;
IF arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L' OR -- positive value
( x_tmp = 0 AND arg1(arg1'left) /= '1' AND arg1(arg1'left) /= 'H') THEN
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => NULL;
WHEN '1'|'H' => return_int := return_int + 1;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
ELSE -- negative value
IF (x_tmp = 0) THEN
x_tmp := 1;
ELSE
x_tmp := 0;
END IF;
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => return_int := return_int + 1;
WHEN '1'|'H' => NULL;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
return_int := (-return_int) - 1;
END IF;
RETURN return_int;
END TO_INTEGER;
FUNCTION to_integer (arg1:STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL IS
BEGIN
IF(arg1 = '0' OR arg1 = 'L' OR (x = 0 AND arg1 /= '1' AND arg1 /= 'H')) THEN
RETURN(0);
ELSE
RETURN(1) ;
END IF ;
END ;
FUNCTION conv_integer (arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_integer (arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length -1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_integer (arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL IS
VARIABLE tmp : SIGNED( arg1'length DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : NATURAL;
BEGIN
tmp := '0' & SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_INTEGER (arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE return_int,x_tmp : INTEGER := 0;
BEGIN
ASSERT arg1'length > 0
REPORT "NULL vector, returning 0"
SEVERITY NOTE;
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT arg1'length <= 32 -- implementation dependent limit
REPORT "vector too large, conversion may cause overflow"
SEVERITY WARNING;
IF x /= 0 THEN
x_tmp := 1;
END IF;
IF arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L' OR -- positive value
( x_tmp = 0 AND arg1(arg1'left) /= '1' AND arg1(arg1'left) /= 'H') THEN
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => NULL;
WHEN '1'|'H' => return_int := return_int + 1;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
ELSE -- negative value
IF (x_tmp = 0) THEN
x_tmp := 1;
ELSE
x_tmp := 0;
END IF;
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => return_int := return_int + 1;
WHEN '1'|'H' => NULL;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
return_int := (-return_int) - 1;
END IF;
RETURN return_int;
END ;
FUNCTION conv_integer (arg1:STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL IS
BEGIN
IF(arg1 = '0' OR arg1 = 'L' OR (x = 0 AND arg1 /= '1' AND arg1 /= 'H')) THEN
RETURN(0);
ELSE
RETURN(1) ;
END IF ;
END ;
--
-- Convert Base Type to STD_LOGIC
--
FUNCTION to_stdlogic (arg1:BOOLEAN) RETURN STD_LOGIC IS
BEGIN
IF(arg1) THEN
RETURN('1') ;
ELSE
RETURN('0') ;
END IF ;
END ;
--
-- Convert Base Type to STD_LOGIC_VECTOR
--
FUNCTION To_StdlogicVector (arg1 : integer; size : NATURAL) RETURN std_logic_vector IS
VARIABLE vector : std_logic_vector(0 TO size-1);
VARIABLE tmp_int : integer := arg1;
VARIABLE carry : std_logic := '1'; -- setup to add 1 if needed
VARIABLE carry2 : std_logic;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END To_StdlogicVector;
FUNCTION To_StdUlogicVector (arg1 : integer; size : NATURAL) RETURN std_ulogic_vector IS
VARIABLE vector : std_ulogic_vector(0 TO size-1);
VARIABLE tmp_int : integer := arg1;
VARIABLE carry : std_ulogic := '1'; -- setup to add 1 if needed
VARIABLE carry2 : std_ulogic;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END To_StdUlogicVector;
--
-- Convert Base Type to UNSIGNED
--
FUNCTION to_unsigned (arg1:NATURAL ; size:NATURAL) RETURN UNSIGNED IS
VARIABLE vector : UNSIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
RETURN vector;
END ;
FUNCTION conv_unsigned (arg1:NATURAL ; size:NATURAL) RETURN UNSIGNED IS
VARIABLE vector : UNSIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
RETURN vector;
END ;
--
-- Convert Base Type to SIGNED
--
FUNCTION to_signed (arg1:INTEGER ; size : NATURAL) RETURN SIGNED IS
VARIABLE vector : SIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
VARIABLE carry : STD_LOGIC := '1'; -- setup to add 1 if needed
VARIABLE carry2 : STD_LOGIC := '0';
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END ;
FUNCTION conv_signed (arg1:INTEGER ; size : NATURAL) RETURN SIGNED IS
VARIABLE vector : SIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
VARIABLE carry : STD_LOGIC := '1'; -- setup to add 1 if needed
VARIABLE carry2 : STD_LOGIC := '0';
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END ;
-- sign/zero extend functions
--
FUNCTION zero_extend ( arg1 : STD_ULOGIC_VECTOR; size : NATURAL ) RETURN STD_ULOGIC_VECTOR
IS
VARIABLE answer : STD_ULOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length-1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : STD_LOGIC_VECTOR; size : NATURAL ) RETURN STD_LOGIC_VECTOR
IS
VARIABLE answer : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length-1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : STD_LOGIC; size : NATURAL ) RETURN STD_LOGIC_VECTOR
IS
VARIABLE answer : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
answer := (OTHERS => '0') ;
answer(0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : UNSIGNED; size : NATURAL ) RETURN UNSIGNED IS
VARIABLE answer : UNSIGNED(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length - 1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION sign_extend ( arg1 : SIGNED; size : NATURAL ) RETURN SIGNED IS
VARIABLE answer : SIGNED(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => arg1(arg1'left)) ;
answer(arg1'length - 1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
-- Some useful generic functions
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : STD_ULOGIC_VECTOR; i : INTEGER ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE qs : STD_ULOGIC_VECTOR (1 TO i);
VARIABLE qt : STD_ULOGIC_VECTOR (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : STD_LOGIC_VECTOR; i : INTEGER ) RETURN STD_LOGIC_VECTOR IS
VARIABLE qs : STD_LOGIC_VECTOR (1 TO i);
VARIABLE qt : STD_LOGIC_VECTOR (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : UNSIGNED; i : INTEGER ) RETURN UNSIGNED IS
VARIABLE qs : UNSIGNED (1 TO i);
VARIABLE qt : UNSIGNED (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--------------------------------------
-- Synthesizable addition Functions --
--------------------------------------
FUNCTION "+" ( arg1, arg2 : STD_LOGIC ) RETURN STD_LOGIC IS
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
BEGIN
RETURN xor_table( arg1, arg2 );
END "+";
function maximum (arg1, arg2: integer) return integer is
begin
if arg1 > arg2 then
return arg1;
else
return arg2;
end if;
end;
FUNCTION "+" (arg1, arg2 :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE carry : STD_ULOGIC := '0';
VARIABLE a,b,s1 : STD_ULOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2 :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE carry : STD_LOGIC := '0';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE res : UNSIGNED(1 TO ml);
VARIABLE carry : STD_LOGIC := '0';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2:SIGNED) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a + b);
RETURN (answer);
END ;
-----------------------------------------
-- Synthesizable subtraction Functions --
-----------------------------------------
FUNCTION "-" ( arg1, arg2 : std_logic ) RETURN std_logic IS
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
BEGIN
RETURN xor_table( arg1, arg2 );
END "-";
FUNCTION "-" (arg1, arg2:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE borrow : STD_ULOGIC := '1';
VARIABLE a,b,s1 : STD_ULOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE borrow : STD_LOGIC := '1';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE res : UNSIGNED(1 TO ml);
VARIABLE borrow : STD_LOGIC := '1';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:SIGNED) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED( a - b );
RETURN (answer);
END ;
-----------------------------------------
-- Unary subtract and add Functions --
-----------------------------------------
FUNCTION "+" (arg1:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:UNSIGNED) RETURN UNSIGNED IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:SIGNED) RETURN SIGNED IS
BEGIN
RETURN (arg1);
END;
FUNCTION hasx( v : SIGNED ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION "-" (arg1:SIGNED) RETURN SIGNED IS
constant len : integer := arg1'length;
VARIABLE answer, tmp : SIGNED( len-1 downto 0 ) := (others=>'0');
VARIABLE index : integer := len;
BEGIN
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
IF hasx(arg1) THEN
answer := (OTHERS => 'X');
ELSE
tmp := arg1;
lp1 : FOR i IN answer'REVERSE_RANGE LOOP
IF (tmp(i) = '1' OR tmp(i) = 'H') THEN
index := i+1;
answer(i downto 0) := tmp(i downto 0);
exit;
END IF;
END LOOP lp1;
answer(len-1 downto index) := NOT tmp(len-1 downto index);
end if;
RETURN (answer);
END ;
--------------------------------------------
-- Synthesizable multiplication Functions --
--------------------------------------------
FUNCTION shift( v : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE v1 : STD_ULOGIC_VECTOR( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN STD_ULOGIC_VECTOR; b : OUT STD_ULOGIC_VECTOR) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR IS
VARIABLE v1 : STD_LOGIC_VECTOR( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN STD_LOGIC_VECTOR; b : OUT STD_LOGIC_VECTOR) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : SIGNED ) RETURN SIGNED IS
VARIABLE v1 : SIGNED( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN SIGNED; b : OUT SIGNED) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE v1 : UNSIGNED( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN UNSIGNED; b : OUT UNSIGNED) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION "*" (arg1, arg2:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE prod : STD_ULOGIC_VECTOR(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION "*" (arg1, arg2:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE prod : STD_LOGIC_VECTOR(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION "*" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE prod : UNSIGNED(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
--//// Sign Extend ////
--
-- Function sxt
--
FUNCTION sxt( q : SIGNED; i : INTEGER ) RETURN SIGNED IS
VARIABLE qs : SIGNED (1 TO i);
VARIABLE qt : SIGNED (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>q(q'left));
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
FUNCTION "*" (arg1, arg2:SIGNED) RETURN SIGNED IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : SIGNED(1 TO ml);
VARIABLE rt : SIGNED(1 TO ml);
VARIABLE prod : SIGNED(1 TO ml) := (OTHERS=>'0');
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := sxt( arg1, ml );
rt := sxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION rshift( v : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE v1 : STD_ULOGIC_VECTOR( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR IS
VARIABLE v1 : STD_LOGIC_VECTOR( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE v1 : UNSIGNED( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : UNSIGNED ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : SIGNED ) RETURN SIGNED IS
VARIABLE v1 : SIGNED( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION "/" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :SIGNED) RETURN SIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : SIGNED(0 TO ml+1);
VARIABLE rt : SIGNED(0 TO ml+1);
VARIABLE quote : SIGNED(1 TO ml);
VARIABLE tmp : SIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : SIGNED(0 TO ml+1) := (OTHERS=>'0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := sxt( l, ml+2 );
WHILE lt >= r LOOP
rt := sxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "MOD" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "MOD" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "MOD" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "REM" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "REM" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "REM" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "**" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
VARIABLE return_vector : STD_ULOGIC_VECTOR(l'range) := (OTHERS=>'0');
VARIABLE tmp : STD_ULOGIC_VECTOR(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
FUNCTION "**" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE return_vector : STD_LOGIC_VECTOR(l'range) := (OTHERS=>'0');
VARIABLE tmp : STD_LOGIC_VECTOR(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
FUNCTION "**" (l, r :UNSIGNED) RETURN UNSIGNED IS
VARIABLE return_vector : UNSIGNED(l'range) := (OTHERS=>'0');
VARIABLE tmp : UNSIGNED(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
--
-- Absolute Value Functions
--
FUNCTION "abs" (arg1:SIGNED) RETURN SIGNED IS
constant len : integer := arg1'length;
VARIABLE answer, tmp : SIGNED( len-1 downto 0 ) := (others=>'0');
VARIABLE index : integer := len;
BEGIN
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
IF hasx(arg1) THEN
answer := (OTHERS => 'X');
ELSIF (arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L') THEN
answer := arg1;
ELSE
tmp := arg1;
lp1 : FOR i IN answer'REVERSE_RANGE LOOP
IF (tmp(i) = '1' OR tmp(i) = 'H') THEN
index := i+1;
answer(i downto 0) := tmp(i downto 0);
exit;
END IF;
END LOOP lp1;
answer(len-1 downto index) := NOT tmp(len-1 downto index);
end if;
RETURN (answer);
END ;
--
-- Shift Left (arithmetic) Functions
--
FUNCTION "sla" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
--
-- Shift Right (arithmetics) Functions
--
FUNCTION "sra" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
--
-- Shift Left (logical) Functions
--
FUNCTION "sll" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others =>'0');
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others =>'0');
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others =>'0');
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others =>'0');
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
--
-- Shift Right (logical) Functions
--
FUNCTION "srl" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => '0');
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => '0');
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => '0');
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => '0');
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
--
-- Rotate Left (Logical) Functions
--
FUNCTION "rol" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
--
-- Rotate Right (Logical) Functions
--
FUNCTION "ror" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
--
-- Equal functions.
--
CONSTANT eq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION eq ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN eq_table( l, r );
END;
FUNCTION eq ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (eq( lt, rt ));
END;
FUNCTION "=" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION "=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (eq( lt, rt ));
END;
--
-- Not Equal function.
--
CONSTANT neq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION ne ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN neq_table( l, r );
END;
FUNCTION ne ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (ne( lt, rt ));
END;
FUNCTION "/=" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION "/=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (ne( lt, rt ));
END;
--
-- Less Than functions.
--
CONSTANT ltb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION lt ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN ltb_table( l, r );
END;
FUNCTION lt ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rtt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rtt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : UNSIGNED ( 1 TO ml );
VARIABLE rtt : UNSIGNED ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE ltt, rtt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ltt := (OTHERS => l(l'left)) ;
ltt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rtt := (OTHERS => r(r'left)) ;
rtt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(ltt(ltt'left) = '1' AND rtt(rtt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(ltt(ltt'left) = '0' AND rtt(rtt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (lt( ltt, rtt ));
END IF ;
END;
FUNCTION "<" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : UNSIGNED ( 1 TO ml );
VARIABLE rtt : UNSIGNED ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION "<" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE ltt, rtt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ltt := (OTHERS => l(l'left)) ;
ltt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rtt := (OTHERS => r(r'left)) ;
rtt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(ltt(ltt'left) = '1' AND rtt(rtt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(ltt(ltt'left) = '0' AND rtt(rtt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (lt( ltt, rtt ));
END IF ;
END;
--
-- Greater Than functions.
--
CONSTANT gtb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION gt ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN gtb_table( l, r );
END ;
FUNCTION gt ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (gt( lt, rt ));
END IF ;
END;
FUNCTION ">" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ">" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (gt( lt, rt ));
END IF ;
END;
--
-- Less Than or Equal to functions.
--
CONSTANT leb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | X |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | W |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ) -- | D |
);
FUNCTION le ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN leb_table( l, r );
END ;
TYPE std_ulogic_fuzzy_state IS ('U', 'X', 'T', 'F', 'N');
TYPE std_ulogic_fuzzy_state_table IS ARRAY ( std_ulogic, std_ulogic ) OF std_ulogic_fuzzy_state;
CONSTANT le_fuzzy_table : std_ulogic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U' ), -- | U |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | X |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | 0 |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | Z |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | W |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | L |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | H |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ) -- | D |
);
FUNCTION le ( L,R : std_ulogic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_fuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
TYPE std_logic_fuzzy_state IS ('U', 'X', 'T', 'F', 'N');
TYPE std_logic_fuzzy_state_table IS ARRAY ( std_logic, std_logic ) OF std_logic_fuzzy_state;
CONSTANT le_lfuzzy_table : std_logic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U' ), -- | U |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | X |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | 0 |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | Z |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | W |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | L |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | H |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ) -- | D |
);
FUNCTION le ( L,R : std_logic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION le ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION le (l, r:SIGNED) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (le( lt, rt ));
END IF ;
END;
FUNCTION "<=" ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION "<=" (l, r:SIGNED) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (le( lt, rt ));
END IF ;
END;
--
-- Greater Than or Equal to functions.
--
CONSTANT geb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 1 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | H |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ) -- | D |
);
FUNCTION ge ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN geb_table( l, r );
END ;
CONSTANT ge_fuzzy_table : std_ulogic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U', 'U' ), -- | U |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | X |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | 0 |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | 1 |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | Z |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | W |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | L |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | H |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ) -- | D |
);
FUNCTION ge ( L,R : std_ulogic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_fuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
CONSTANT ge_lfuzzy_table : std_logic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U', 'U' ), -- | U |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | X |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | 0 |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | 1 |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | Z |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | W |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | L |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | H |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ) -- | D |
);
FUNCTION ge ( L,R : std_logic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ge ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ge ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (ge( lt, rt ));
END IF ;
END;
FUNCTION ">=" ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ">=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (ge( lt, rt ));
END IF ;
END;
-------------------------------------------------------------------------------
-- Logical Operations
-------------------------------------------------------------------------------
-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | D |
);
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | D |
);
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
-- truth table for "not" function
CONSTANT not_table: stdlogic_1D :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H D |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
FUNCTION "and" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := and_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "and";
FUNCTION "nand" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( and_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "nand";
FUNCTION "or" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := or_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "or";
FUNCTION "nor" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( or_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "nor";
FUNCTION "xor" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := xor_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "xor";
FUNCTION "not" ( arg1 : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE result : UNSIGNED ( arg1'RANGE ) := (Others => 'X');
begin
for i in result'range loop
result(i) := not_table( arg1(i) );
end loop;
return result;
end "not";
FUNCTION "and" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a and b);
RETURN (answer);
end "and";
FUNCTION "nand" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a nand b);
RETURN (answer);
end "nand";
FUNCTION "or" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a or b);
RETURN (answer);
end "or";
FUNCTION "nor" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a nor b);
RETURN (answer);
end "nor";
FUNCTION "xor" ( arg1, arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a xor b);
RETURN (answer);
end "xor";
FUNCTION "not" ( arg1 : SIGNED ) RETURN SIGNED IS
VARIABLE result : SIGNED ( arg1'RANGE ) := (Others => 'X');
begin
for i in result'range loop
result(i) := not_table( arg1(i) );
end loop;
return result;
end "not";
FUNCTION "xnor" ( arg1, arg2 : std_ulogic_vector ) RETURN std_ulogic_vector IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_vector ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : std_logic_vector ) RETURN std_logic_vector IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_vector ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a xnor b);
RETURN (answer);
end "xnor";
END ;
|
LIBRARY ieee;
-- LIBRARY arithmetic;
PACKAGE BODY std_logic_arith IS
USE ieee.std_logic_1164.ALL;
-- USE arithmetic.utils.all;
-------------------------------------------------------------------
-- Local Types
-------------------------------------------------------------------
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
TYPE stdlogic_boolean_table IS ARRAY(std_ulogic, std_ulogic) OF BOOLEAN;
--------------------------------------------------------------------
--------------------------------------------------------------------
-- FUNCTIONS DEFINED FOR SYNTHESIS
--------------------------------------------------------------------
--------------------------------------------------------------------
FUNCTION std_ulogic_wired_or ( input : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := '-'; -- weakest state default
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ---------------------------------------------------------
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | U |
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'X', 'X', '0', '1', '0', 'X', '0', '1', '0' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ), -- | Z |
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'X', 'X', '0', '1', '0', 'X', '0', '1', '0' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ) -- | D |
);
BEGIN
-- Iterate through all inputs
FOR i IN input'range LOOP
result := resolution_table(result, input(i));
END LOOP;
-- Return the resultant value
RETURN result;
END std_ulogic_wired_or;
FUNCTION std_ulogic_wired_and ( input : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := '-'; -- weakest state default
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ---------------------------------------------------------
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | U |
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'X', 'X', '0', '1', '1', 'X', '0', '1', '1' ), -- | 1 |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ), -- | Z |
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'X', 'X', '0', '1', '1', 'X', '0', '1', '1' ), -- | H |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ) -- | D |
);
BEGIN
-- Iterate through all inputs
FOR i IN input'range LOOP
result := resolution_table(result, input(i));
END LOOP;
-- Return the resultant value
RETURN result;
END std_ulogic_wired_and;
--
-- MGC base level functions
--
--
-- Convert Base Type to Integer
--
FUNCTION to_integer (arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION to_integer (arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION to_integer (arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL IS
VARIABLE tmp : SIGNED( arg1'length DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : NATURAL;
BEGIN
tmp := '0' & SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION TO_INTEGER (arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE return_int,x_tmp : INTEGER := 0;
BEGIN
ASSERT arg1'length > 0
REPORT "NULL vector, returning 0"
SEVERITY NOTE;
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT arg1'length <= 32 -- implementation dependent limit
REPORT "vector too large, conversion may cause overflow"
SEVERITY WARNING;
IF x /= 0 THEN
x_tmp := 1;
END IF;
IF arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L' OR -- positive value
( x_tmp = 0 AND arg1(arg1'left) /= '1' AND arg1(arg1'left) /= 'H') THEN
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => NULL;
WHEN '1'|'H' => return_int := return_int + 1;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
ELSE -- negative value
IF (x_tmp = 0) THEN
x_tmp := 1;
ELSE
x_tmp := 0;
END IF;
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => return_int := return_int + 1;
WHEN '1'|'H' => NULL;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
return_int := (-return_int) - 1;
END IF;
RETURN return_int;
END TO_INTEGER;
FUNCTION to_integer (arg1:STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL IS
BEGIN
IF(arg1 = '0' OR arg1 = 'L' OR (x = 0 AND arg1 /= '1' AND arg1 /= 'H')) THEN
RETURN(0);
ELSE
RETURN(1) ;
END IF ;
END ;
FUNCTION conv_integer (arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_integer (arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length -1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_integer (arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL IS
VARIABLE tmp : SIGNED( arg1'length DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : NATURAL;
BEGIN
tmp := '0' & SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_INTEGER (arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE return_int,x_tmp : INTEGER := 0;
BEGIN
ASSERT arg1'length > 0
REPORT "NULL vector, returning 0"
SEVERITY NOTE;
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT arg1'length <= 32 -- implementation dependent limit
REPORT "vector too large, conversion may cause overflow"
SEVERITY WARNING;
IF x /= 0 THEN
x_tmp := 1;
END IF;
IF arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L' OR -- positive value
( x_tmp = 0 AND arg1(arg1'left) /= '1' AND arg1(arg1'left) /= 'H') THEN
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => NULL;
WHEN '1'|'H' => return_int := return_int + 1;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
ELSE -- negative value
IF (x_tmp = 0) THEN
x_tmp := 1;
ELSE
x_tmp := 0;
END IF;
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => return_int := return_int + 1;
WHEN '1'|'H' => NULL;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
return_int := (-return_int) - 1;
END IF;
RETURN return_int;
END ;
FUNCTION conv_integer (arg1:STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL IS
BEGIN
IF(arg1 = '0' OR arg1 = 'L' OR (x = 0 AND arg1 /= '1' AND arg1 /= 'H')) THEN
RETURN(0);
ELSE
RETURN(1) ;
END IF ;
END ;
--
-- Convert Base Type to STD_LOGIC
--
FUNCTION to_stdlogic (arg1:BOOLEAN) RETURN STD_LOGIC IS
BEGIN
IF(arg1) THEN
RETURN('1') ;
ELSE
RETURN('0') ;
END IF ;
END ;
--
-- Convert Base Type to STD_LOGIC_VECTOR
--
FUNCTION To_StdlogicVector (arg1 : integer; size : NATURAL) RETURN std_logic_vector IS
VARIABLE vector : std_logic_vector(0 TO size-1);
VARIABLE tmp_int : integer := arg1;
VARIABLE carry : std_logic := '1'; -- setup to add 1 if needed
VARIABLE carry2 : std_logic;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END To_StdlogicVector;
FUNCTION To_StdUlogicVector (arg1 : integer; size : NATURAL) RETURN std_ulogic_vector IS
VARIABLE vector : std_ulogic_vector(0 TO size-1);
VARIABLE tmp_int : integer := arg1;
VARIABLE carry : std_ulogic := '1'; -- setup to add 1 if needed
VARIABLE carry2 : std_ulogic;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END To_StdUlogicVector;
--
-- Convert Base Type to UNSIGNED
--
FUNCTION to_unsigned (arg1:NATURAL ; size:NATURAL) RETURN UNSIGNED IS
VARIABLE vector : UNSIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
RETURN vector;
END ;
FUNCTION conv_unsigned (arg1:NATURAL ; size:NATURAL) RETURN UNSIGNED IS
VARIABLE vector : UNSIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
RETURN vector;
END ;
--
-- Convert Base Type to SIGNED
--
FUNCTION to_signed (arg1:INTEGER ; size : NATURAL) RETURN SIGNED IS
VARIABLE vector : SIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
VARIABLE carry : STD_LOGIC := '1'; -- setup to add 1 if needed
VARIABLE carry2 : STD_LOGIC := '0';
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END ;
FUNCTION conv_signed (arg1:INTEGER ; size : NATURAL) RETURN SIGNED IS
VARIABLE vector : SIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
VARIABLE carry : STD_LOGIC := '1'; -- setup to add 1 if needed
VARIABLE carry2 : STD_LOGIC := '0';
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END ;
-- sign/zero extend functions
--
FUNCTION zero_extend ( arg1 : STD_ULOGIC_VECTOR; size : NATURAL ) RETURN STD_ULOGIC_VECTOR
IS
VARIABLE answer : STD_ULOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length-1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : STD_LOGIC_VECTOR; size : NATURAL ) RETURN STD_LOGIC_VECTOR
IS
VARIABLE answer : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length-1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : STD_LOGIC; size : NATURAL ) RETURN STD_LOGIC_VECTOR
IS
VARIABLE answer : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
answer := (OTHERS => '0') ;
answer(0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : UNSIGNED; size : NATURAL ) RETURN UNSIGNED IS
VARIABLE answer : UNSIGNED(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length - 1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION sign_extend ( arg1 : SIGNED; size : NATURAL ) RETURN SIGNED IS
VARIABLE answer : SIGNED(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => arg1(arg1'left)) ;
answer(arg1'length - 1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
-- Some useful generic functions
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : STD_ULOGIC_VECTOR; i : INTEGER ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE qs : STD_ULOGIC_VECTOR (1 TO i);
VARIABLE qt : STD_ULOGIC_VECTOR (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : STD_LOGIC_VECTOR; i : INTEGER ) RETURN STD_LOGIC_VECTOR IS
VARIABLE qs : STD_LOGIC_VECTOR (1 TO i);
VARIABLE qt : STD_LOGIC_VECTOR (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : UNSIGNED; i : INTEGER ) RETURN UNSIGNED IS
VARIABLE qs : UNSIGNED (1 TO i);
VARIABLE qt : UNSIGNED (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--------------------------------------
-- Synthesizable addition Functions --
--------------------------------------
FUNCTION "+" ( arg1, arg2 : STD_LOGIC ) RETURN STD_LOGIC IS
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
BEGIN
RETURN xor_table( arg1, arg2 );
END "+";
function maximum (arg1, arg2: integer) return integer is
begin
if arg1 > arg2 then
return arg1;
else
return arg2;
end if;
end;
FUNCTION "+" (arg1, arg2 :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE carry : STD_ULOGIC := '0';
VARIABLE a,b,s1 : STD_ULOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2 :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE carry : STD_LOGIC := '0';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE res : UNSIGNED(1 TO ml);
VARIABLE carry : STD_LOGIC := '0';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2:SIGNED) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a + b);
RETURN (answer);
END ;
-----------------------------------------
-- Synthesizable subtraction Functions --
-----------------------------------------
FUNCTION "-" ( arg1, arg2 : std_logic ) RETURN std_logic IS
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
BEGIN
RETURN xor_table( arg1, arg2 );
END "-";
FUNCTION "-" (arg1, arg2:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE borrow : STD_ULOGIC := '1';
VARIABLE a,b,s1 : STD_ULOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE borrow : STD_LOGIC := '1';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE res : UNSIGNED(1 TO ml);
VARIABLE borrow : STD_LOGIC := '1';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:SIGNED) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED( a - b );
RETURN (answer);
END ;
-----------------------------------------
-- Unary subtract and add Functions --
-----------------------------------------
FUNCTION "+" (arg1:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:UNSIGNED) RETURN UNSIGNED IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:SIGNED) RETURN SIGNED IS
BEGIN
RETURN (arg1);
END;
FUNCTION hasx( v : SIGNED ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION "-" (arg1:SIGNED) RETURN SIGNED IS
constant len : integer := arg1'length;
VARIABLE answer, tmp : SIGNED( len-1 downto 0 ) := (others=>'0');
VARIABLE index : integer := len;
BEGIN
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
IF hasx(arg1) THEN
answer := (OTHERS => 'X');
ELSE
tmp := arg1;
lp1 : FOR i IN answer'REVERSE_RANGE LOOP
IF (tmp(i) = '1' OR tmp(i) = 'H') THEN
index := i+1;
answer(i downto 0) := tmp(i downto 0);
exit;
END IF;
END LOOP lp1;
answer(len-1 downto index) := NOT tmp(len-1 downto index);
end if;
RETURN (answer);
END ;
--------------------------------------------
-- Synthesizable multiplication Functions --
--------------------------------------------
FUNCTION shift( v : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE v1 : STD_ULOGIC_VECTOR( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN STD_ULOGIC_VECTOR; b : OUT STD_ULOGIC_VECTOR) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR IS
VARIABLE v1 : STD_LOGIC_VECTOR( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN STD_LOGIC_VECTOR; b : OUT STD_LOGIC_VECTOR) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : SIGNED ) RETURN SIGNED IS
VARIABLE v1 : SIGNED( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN SIGNED; b : OUT SIGNED) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE v1 : UNSIGNED( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN UNSIGNED; b : OUT UNSIGNED) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION "*" (arg1, arg2:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE prod : STD_ULOGIC_VECTOR(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION "*" (arg1, arg2:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE prod : STD_LOGIC_VECTOR(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION "*" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE prod : UNSIGNED(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
--//// Sign Extend ////
--
-- Function sxt
--
FUNCTION sxt( q : SIGNED; i : INTEGER ) RETURN SIGNED IS
VARIABLE qs : SIGNED (1 TO i);
VARIABLE qt : SIGNED (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>q(q'left));
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
FUNCTION "*" (arg1, arg2:SIGNED) RETURN SIGNED IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : SIGNED(1 TO ml);
VARIABLE rt : SIGNED(1 TO ml);
VARIABLE prod : SIGNED(1 TO ml) := (OTHERS=>'0');
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := sxt( arg1, ml );
rt := sxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION rshift( v : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE v1 : STD_ULOGIC_VECTOR( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR IS
VARIABLE v1 : STD_LOGIC_VECTOR( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE v1 : UNSIGNED( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : UNSIGNED ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : SIGNED ) RETURN SIGNED IS
VARIABLE v1 : SIGNED( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION "/" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :SIGNED) RETURN SIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : SIGNED(0 TO ml+1);
VARIABLE rt : SIGNED(0 TO ml+1);
VARIABLE quote : SIGNED(1 TO ml);
VARIABLE tmp : SIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : SIGNED(0 TO ml+1) := (OTHERS=>'0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := sxt( l, ml+2 );
WHILE lt >= r LOOP
rt := sxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "MOD" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "MOD" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "MOD" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "REM" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "REM" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "REM" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "**" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
VARIABLE return_vector : STD_ULOGIC_VECTOR(l'range) := (OTHERS=>'0');
VARIABLE tmp : STD_ULOGIC_VECTOR(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
FUNCTION "**" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE return_vector : STD_LOGIC_VECTOR(l'range) := (OTHERS=>'0');
VARIABLE tmp : STD_LOGIC_VECTOR(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
FUNCTION "**" (l, r :UNSIGNED) RETURN UNSIGNED IS
VARIABLE return_vector : UNSIGNED(l'range) := (OTHERS=>'0');
VARIABLE tmp : UNSIGNED(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
--
-- Absolute Value Functions
--
FUNCTION "abs" (arg1:SIGNED) RETURN SIGNED IS
constant len : integer := arg1'length;
VARIABLE answer, tmp : SIGNED( len-1 downto 0 ) := (others=>'0');
VARIABLE index : integer := len;
BEGIN
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
IF hasx(arg1) THEN
answer := (OTHERS => 'X');
ELSIF (arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L') THEN
answer := arg1;
ELSE
tmp := arg1;
lp1 : FOR i IN answer'REVERSE_RANGE LOOP
IF (tmp(i) = '1' OR tmp(i) = 'H') THEN
index := i+1;
answer(i downto 0) := tmp(i downto 0);
exit;
END IF;
END LOOP lp1;
answer(len-1 downto index) := NOT tmp(len-1 downto index);
end if;
RETURN (answer);
END ;
--
-- Shift Left (arithmetic) Functions
--
FUNCTION "sla" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
--
-- Shift Right (arithmetics) Functions
--
FUNCTION "sra" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
--
-- Shift Left (logical) Functions
--
FUNCTION "sll" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others =>'0');
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others =>'0');
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others =>'0');
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others =>'0');
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
--
-- Shift Right (logical) Functions
--
FUNCTION "srl" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => '0');
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => '0');
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => '0');
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => '0');
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
--
-- Rotate Left (Logical) Functions
--
FUNCTION "rol" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
--
-- Rotate Right (Logical) Functions
--
FUNCTION "ror" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
--
-- Equal functions.
--
CONSTANT eq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION eq ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN eq_table( l, r );
END;
FUNCTION eq ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (eq( lt, rt ));
END;
FUNCTION "=" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION "=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (eq( lt, rt ));
END;
--
-- Not Equal function.
--
CONSTANT neq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION ne ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN neq_table( l, r );
END;
FUNCTION ne ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (ne( lt, rt ));
END;
FUNCTION "/=" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION "/=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (ne( lt, rt ));
END;
--
-- Less Than functions.
--
CONSTANT ltb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION lt ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN ltb_table( l, r );
END;
FUNCTION lt ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rtt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rtt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : UNSIGNED ( 1 TO ml );
VARIABLE rtt : UNSIGNED ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE ltt, rtt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ltt := (OTHERS => l(l'left)) ;
ltt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rtt := (OTHERS => r(r'left)) ;
rtt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(ltt(ltt'left) = '1' AND rtt(rtt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(ltt(ltt'left) = '0' AND rtt(rtt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (lt( ltt, rtt ));
END IF ;
END;
FUNCTION "<" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : UNSIGNED ( 1 TO ml );
VARIABLE rtt : UNSIGNED ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION "<" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE ltt, rtt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ltt := (OTHERS => l(l'left)) ;
ltt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rtt := (OTHERS => r(r'left)) ;
rtt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(ltt(ltt'left) = '1' AND rtt(rtt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(ltt(ltt'left) = '0' AND rtt(rtt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (lt( ltt, rtt ));
END IF ;
END;
--
-- Greater Than functions.
--
CONSTANT gtb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION gt ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN gtb_table( l, r );
END ;
FUNCTION gt ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (gt( lt, rt ));
END IF ;
END;
FUNCTION ">" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ">" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (gt( lt, rt ));
END IF ;
END;
--
-- Less Than or Equal to functions.
--
CONSTANT leb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | X |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | W |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ) -- | D |
);
FUNCTION le ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN leb_table( l, r );
END ;
TYPE std_ulogic_fuzzy_state IS ('U', 'X', 'T', 'F', 'N');
TYPE std_ulogic_fuzzy_state_table IS ARRAY ( std_ulogic, std_ulogic ) OF std_ulogic_fuzzy_state;
CONSTANT le_fuzzy_table : std_ulogic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U' ), -- | U |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | X |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | 0 |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | Z |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | W |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | L |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | H |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ) -- | D |
);
FUNCTION le ( L,R : std_ulogic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_fuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
TYPE std_logic_fuzzy_state IS ('U', 'X', 'T', 'F', 'N');
TYPE std_logic_fuzzy_state_table IS ARRAY ( std_logic, std_logic ) OF std_logic_fuzzy_state;
CONSTANT le_lfuzzy_table : std_logic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U' ), -- | U |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | X |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | 0 |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | Z |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | W |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | L |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | H |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ) -- | D |
);
FUNCTION le ( L,R : std_logic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION le ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION le (l, r:SIGNED) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (le( lt, rt ));
END IF ;
END;
FUNCTION "<=" ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION "<=" (l, r:SIGNED) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (le( lt, rt ));
END IF ;
END;
--
-- Greater Than or Equal to functions.
--
CONSTANT geb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 1 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | H |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ) -- | D |
);
FUNCTION ge ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN geb_table( l, r );
END ;
CONSTANT ge_fuzzy_table : std_ulogic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U', 'U' ), -- | U |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | X |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | 0 |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | 1 |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | Z |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | W |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | L |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | H |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ) -- | D |
);
FUNCTION ge ( L,R : std_ulogic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_fuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
CONSTANT ge_lfuzzy_table : std_logic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U', 'U' ), -- | U |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | X |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | 0 |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | 1 |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | Z |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | W |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | L |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | H |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ) -- | D |
);
FUNCTION ge ( L,R : std_logic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ge ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ge ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (ge( lt, rt ));
END IF ;
END;
FUNCTION ">=" ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ">=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (ge( lt, rt ));
END IF ;
END;
-------------------------------------------------------------------------------
-- Logical Operations
-------------------------------------------------------------------------------
-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | D |
);
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | D |
);
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
-- truth table for "not" function
CONSTANT not_table: stdlogic_1D :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H D |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
FUNCTION "and" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := and_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "and";
FUNCTION "nand" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( and_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "nand";
FUNCTION "or" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := or_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "or";
FUNCTION "nor" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( or_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "nor";
FUNCTION "xor" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := xor_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "xor";
FUNCTION "not" ( arg1 : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE result : UNSIGNED ( arg1'RANGE ) := (Others => 'X');
begin
for i in result'range loop
result(i) := not_table( arg1(i) );
end loop;
return result;
end "not";
FUNCTION "and" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a and b);
RETURN (answer);
end "and";
FUNCTION "nand" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a nand b);
RETURN (answer);
end "nand";
FUNCTION "or" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a or b);
RETURN (answer);
end "or";
FUNCTION "nor" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a nor b);
RETURN (answer);
end "nor";
FUNCTION "xor" ( arg1, arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a xor b);
RETURN (answer);
end "xor";
FUNCTION "not" ( arg1 : SIGNED ) RETURN SIGNED IS
VARIABLE result : SIGNED ( arg1'RANGE ) := (Others => 'X');
begin
for i in result'range loop
result(i) := not_table( arg1(i) );
end loop;
return result;
end "not";
FUNCTION "xnor" ( arg1, arg2 : std_ulogic_vector ) RETURN std_ulogic_vector IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_vector ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : std_logic_vector ) RETURN std_logic_vector IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_vector ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a xnor b);
RETURN (answer);
end "xnor";
END ;
|
LIBRARY ieee;
-- LIBRARY arithmetic;
PACKAGE BODY std_logic_arith IS
USE ieee.std_logic_1164.ALL;
-- USE arithmetic.utils.all;
-------------------------------------------------------------------
-- Local Types
-------------------------------------------------------------------
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
TYPE stdlogic_boolean_table IS ARRAY(std_ulogic, std_ulogic) OF BOOLEAN;
--------------------------------------------------------------------
--------------------------------------------------------------------
-- FUNCTIONS DEFINED FOR SYNTHESIS
--------------------------------------------------------------------
--------------------------------------------------------------------
FUNCTION std_ulogic_wired_or ( input : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := '-'; -- weakest state default
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ---------------------------------------------------------
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | U |
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'X', 'X', '0', '1', '0', 'X', '0', '1', '0' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ), -- | Z |
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'X', 'X', '0', '1', '0', 'X', '0', '1', '0' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ) -- | D |
);
BEGIN
-- Iterate through all inputs
FOR i IN input'range LOOP
result := resolution_table(result, input(i));
END LOOP;
-- Return the resultant value
RETURN result;
END std_ulogic_wired_or;
FUNCTION std_ulogic_wired_and ( input : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := '-'; -- weakest state default
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ---------------------------------------------------------
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | U |
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'X', 'X', '0', '1', '1', 'X', '0', '1', '1' ), -- | 1 |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ), -- | Z |
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'X', 'X', '0', '1', '1', 'X', '0', '1', '1' ), -- | H |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ) -- | D |
);
BEGIN
-- Iterate through all inputs
FOR i IN input'range LOOP
result := resolution_table(result, input(i));
END LOOP;
-- Return the resultant value
RETURN result;
END std_ulogic_wired_and;
--
-- MGC base level functions
--
--
-- Convert Base Type to Integer
--
FUNCTION to_integer (arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION to_integer (arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION to_integer (arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL IS
VARIABLE tmp : SIGNED( arg1'length DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : NATURAL;
BEGIN
tmp := '0' & SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION TO_INTEGER (arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE return_int,x_tmp : INTEGER := 0;
BEGIN
ASSERT arg1'length > 0
REPORT "NULL vector, returning 0"
SEVERITY NOTE;
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT arg1'length <= 32 -- implementation dependent limit
REPORT "vector too large, conversion may cause overflow"
SEVERITY WARNING;
IF x /= 0 THEN
x_tmp := 1;
END IF;
IF arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L' OR -- positive value
( x_tmp = 0 AND arg1(arg1'left) /= '1' AND arg1(arg1'left) /= 'H') THEN
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => NULL;
WHEN '1'|'H' => return_int := return_int + 1;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
ELSE -- negative value
IF (x_tmp = 0) THEN
x_tmp := 1;
ELSE
x_tmp := 0;
END IF;
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => return_int := return_int + 1;
WHEN '1'|'H' => NULL;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
return_int := (-return_int) - 1;
END IF;
RETURN return_int;
END TO_INTEGER;
FUNCTION to_integer (arg1:STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL IS
BEGIN
IF(arg1 = '0' OR arg1 = 'L' OR (x = 0 AND arg1 /= '1' AND arg1 /= 'H')) THEN
RETURN(0);
ELSE
RETURN(1) ;
END IF ;
END ;
FUNCTION conv_integer (arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_integer (arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length -1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_integer (arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL IS
VARIABLE tmp : SIGNED( arg1'length DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : NATURAL;
BEGIN
tmp := '0' & SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_INTEGER (arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE return_int,x_tmp : INTEGER := 0;
BEGIN
ASSERT arg1'length > 0
REPORT "NULL vector, returning 0"
SEVERITY NOTE;
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT arg1'length <= 32 -- implementation dependent limit
REPORT "vector too large, conversion may cause overflow"
SEVERITY WARNING;
IF x /= 0 THEN
x_tmp := 1;
END IF;
IF arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L' OR -- positive value
( x_tmp = 0 AND arg1(arg1'left) /= '1' AND arg1(arg1'left) /= 'H') THEN
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => NULL;
WHEN '1'|'H' => return_int := return_int + 1;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
ELSE -- negative value
IF (x_tmp = 0) THEN
x_tmp := 1;
ELSE
x_tmp := 0;
END IF;
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => return_int := return_int + 1;
WHEN '1'|'H' => NULL;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
return_int := (-return_int) - 1;
END IF;
RETURN return_int;
END ;
FUNCTION conv_integer (arg1:STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL IS
BEGIN
IF(arg1 = '0' OR arg1 = 'L' OR (x = 0 AND arg1 /= '1' AND arg1 /= 'H')) THEN
RETURN(0);
ELSE
RETURN(1) ;
END IF ;
END ;
--
-- Convert Base Type to STD_LOGIC
--
FUNCTION to_stdlogic (arg1:BOOLEAN) RETURN STD_LOGIC IS
BEGIN
IF(arg1) THEN
RETURN('1') ;
ELSE
RETURN('0') ;
END IF ;
END ;
--
-- Convert Base Type to STD_LOGIC_VECTOR
--
FUNCTION To_StdlogicVector (arg1 : integer; size : NATURAL) RETURN std_logic_vector IS
VARIABLE vector : std_logic_vector(0 TO size-1);
VARIABLE tmp_int : integer := arg1;
VARIABLE carry : std_logic := '1'; -- setup to add 1 if needed
VARIABLE carry2 : std_logic;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END To_StdlogicVector;
FUNCTION To_StdUlogicVector (arg1 : integer; size : NATURAL) RETURN std_ulogic_vector IS
VARIABLE vector : std_ulogic_vector(0 TO size-1);
VARIABLE tmp_int : integer := arg1;
VARIABLE carry : std_ulogic := '1'; -- setup to add 1 if needed
VARIABLE carry2 : std_ulogic;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END To_StdUlogicVector;
--
-- Convert Base Type to UNSIGNED
--
FUNCTION to_unsigned (arg1:NATURAL ; size:NATURAL) RETURN UNSIGNED IS
VARIABLE vector : UNSIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
RETURN vector;
END ;
FUNCTION conv_unsigned (arg1:NATURAL ; size:NATURAL) RETURN UNSIGNED IS
VARIABLE vector : UNSIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
RETURN vector;
END ;
--
-- Convert Base Type to SIGNED
--
FUNCTION to_signed (arg1:INTEGER ; size : NATURAL) RETURN SIGNED IS
VARIABLE vector : SIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
VARIABLE carry : STD_LOGIC := '1'; -- setup to add 1 if needed
VARIABLE carry2 : STD_LOGIC := '0';
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END ;
FUNCTION conv_signed (arg1:INTEGER ; size : NATURAL) RETURN SIGNED IS
VARIABLE vector : SIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
VARIABLE carry : STD_LOGIC := '1'; -- setup to add 1 if needed
VARIABLE carry2 : STD_LOGIC := '0';
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END ;
-- sign/zero extend functions
--
FUNCTION zero_extend ( arg1 : STD_ULOGIC_VECTOR; size : NATURAL ) RETURN STD_ULOGIC_VECTOR
IS
VARIABLE answer : STD_ULOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length-1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : STD_LOGIC_VECTOR; size : NATURAL ) RETURN STD_LOGIC_VECTOR
IS
VARIABLE answer : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length-1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : STD_LOGIC; size : NATURAL ) RETURN STD_LOGIC_VECTOR
IS
VARIABLE answer : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
answer := (OTHERS => '0') ;
answer(0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : UNSIGNED; size : NATURAL ) RETURN UNSIGNED IS
VARIABLE answer : UNSIGNED(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length - 1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION sign_extend ( arg1 : SIGNED; size : NATURAL ) RETURN SIGNED IS
VARIABLE answer : SIGNED(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => arg1(arg1'left)) ;
answer(arg1'length - 1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
-- Some useful generic functions
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : STD_ULOGIC_VECTOR; i : INTEGER ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE qs : STD_ULOGIC_VECTOR (1 TO i);
VARIABLE qt : STD_ULOGIC_VECTOR (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : STD_LOGIC_VECTOR; i : INTEGER ) RETURN STD_LOGIC_VECTOR IS
VARIABLE qs : STD_LOGIC_VECTOR (1 TO i);
VARIABLE qt : STD_LOGIC_VECTOR (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : UNSIGNED; i : INTEGER ) RETURN UNSIGNED IS
VARIABLE qs : UNSIGNED (1 TO i);
VARIABLE qt : UNSIGNED (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--------------------------------------
-- Synthesizable addition Functions --
--------------------------------------
FUNCTION "+" ( arg1, arg2 : STD_LOGIC ) RETURN STD_LOGIC IS
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
BEGIN
RETURN xor_table( arg1, arg2 );
END "+";
function maximum (arg1, arg2: integer) return integer is
begin
if arg1 > arg2 then
return arg1;
else
return arg2;
end if;
end;
FUNCTION "+" (arg1, arg2 :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE carry : STD_ULOGIC := '0';
VARIABLE a,b,s1 : STD_ULOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2 :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE carry : STD_LOGIC := '0';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE res : UNSIGNED(1 TO ml);
VARIABLE carry : STD_LOGIC := '0';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2:SIGNED) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a + b);
RETURN (answer);
END ;
-----------------------------------------
-- Synthesizable subtraction Functions --
-----------------------------------------
FUNCTION "-" ( arg1, arg2 : std_logic ) RETURN std_logic IS
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
BEGIN
RETURN xor_table( arg1, arg2 );
END "-";
FUNCTION "-" (arg1, arg2:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE borrow : STD_ULOGIC := '1';
VARIABLE a,b,s1 : STD_ULOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE borrow : STD_LOGIC := '1';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE res : UNSIGNED(1 TO ml);
VARIABLE borrow : STD_LOGIC := '1';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:SIGNED) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED( a - b );
RETURN (answer);
END ;
-----------------------------------------
-- Unary subtract and add Functions --
-----------------------------------------
FUNCTION "+" (arg1:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:UNSIGNED) RETURN UNSIGNED IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:SIGNED) RETURN SIGNED IS
BEGIN
RETURN (arg1);
END;
FUNCTION hasx( v : SIGNED ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION "-" (arg1:SIGNED) RETURN SIGNED IS
constant len : integer := arg1'length;
VARIABLE answer, tmp : SIGNED( len-1 downto 0 ) := (others=>'0');
VARIABLE index : integer := len;
BEGIN
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
IF hasx(arg1) THEN
answer := (OTHERS => 'X');
ELSE
tmp := arg1;
lp1 : FOR i IN answer'REVERSE_RANGE LOOP
IF (tmp(i) = '1' OR tmp(i) = 'H') THEN
index := i+1;
answer(i downto 0) := tmp(i downto 0);
exit;
END IF;
END LOOP lp1;
answer(len-1 downto index) := NOT tmp(len-1 downto index);
end if;
RETURN (answer);
END ;
--------------------------------------------
-- Synthesizable multiplication Functions --
--------------------------------------------
FUNCTION shift( v : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE v1 : STD_ULOGIC_VECTOR( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN STD_ULOGIC_VECTOR; b : OUT STD_ULOGIC_VECTOR) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR IS
VARIABLE v1 : STD_LOGIC_VECTOR( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN STD_LOGIC_VECTOR; b : OUT STD_LOGIC_VECTOR) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : SIGNED ) RETURN SIGNED IS
VARIABLE v1 : SIGNED( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN SIGNED; b : OUT SIGNED) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE v1 : UNSIGNED( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN UNSIGNED; b : OUT UNSIGNED) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION "*" (arg1, arg2:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE prod : STD_ULOGIC_VECTOR(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION "*" (arg1, arg2:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE prod : STD_LOGIC_VECTOR(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION "*" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE prod : UNSIGNED(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
--//// Sign Extend ////
--
-- Function sxt
--
FUNCTION sxt( q : SIGNED; i : INTEGER ) RETURN SIGNED IS
VARIABLE qs : SIGNED (1 TO i);
VARIABLE qt : SIGNED (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>q(q'left));
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
FUNCTION "*" (arg1, arg2:SIGNED) RETURN SIGNED IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : SIGNED(1 TO ml);
VARIABLE rt : SIGNED(1 TO ml);
VARIABLE prod : SIGNED(1 TO ml) := (OTHERS=>'0');
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := sxt( arg1, ml );
rt := sxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION rshift( v : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE v1 : STD_ULOGIC_VECTOR( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR IS
VARIABLE v1 : STD_LOGIC_VECTOR( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE v1 : UNSIGNED( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : UNSIGNED ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : SIGNED ) RETURN SIGNED IS
VARIABLE v1 : SIGNED( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION "/" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :SIGNED) RETURN SIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : SIGNED(0 TO ml+1);
VARIABLE rt : SIGNED(0 TO ml+1);
VARIABLE quote : SIGNED(1 TO ml);
VARIABLE tmp : SIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : SIGNED(0 TO ml+1) := (OTHERS=>'0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := sxt( l, ml+2 );
WHILE lt >= r LOOP
rt := sxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "MOD" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "MOD" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "MOD" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "REM" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "REM" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "REM" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "**" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
VARIABLE return_vector : STD_ULOGIC_VECTOR(l'range) := (OTHERS=>'0');
VARIABLE tmp : STD_ULOGIC_VECTOR(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
FUNCTION "**" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE return_vector : STD_LOGIC_VECTOR(l'range) := (OTHERS=>'0');
VARIABLE tmp : STD_LOGIC_VECTOR(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
FUNCTION "**" (l, r :UNSIGNED) RETURN UNSIGNED IS
VARIABLE return_vector : UNSIGNED(l'range) := (OTHERS=>'0');
VARIABLE tmp : UNSIGNED(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
--
-- Absolute Value Functions
--
FUNCTION "abs" (arg1:SIGNED) RETURN SIGNED IS
constant len : integer := arg1'length;
VARIABLE answer, tmp : SIGNED( len-1 downto 0 ) := (others=>'0');
VARIABLE index : integer := len;
BEGIN
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
IF hasx(arg1) THEN
answer := (OTHERS => 'X');
ELSIF (arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L') THEN
answer := arg1;
ELSE
tmp := arg1;
lp1 : FOR i IN answer'REVERSE_RANGE LOOP
IF (tmp(i) = '1' OR tmp(i) = 'H') THEN
index := i+1;
answer(i downto 0) := tmp(i downto 0);
exit;
END IF;
END LOOP lp1;
answer(len-1 downto index) := NOT tmp(len-1 downto index);
end if;
RETURN (answer);
END ;
--
-- Shift Left (arithmetic) Functions
--
FUNCTION "sla" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
--
-- Shift Right (arithmetics) Functions
--
FUNCTION "sra" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
--
-- Shift Left (logical) Functions
--
FUNCTION "sll" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others =>'0');
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others =>'0');
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others =>'0');
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others =>'0');
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
--
-- Shift Right (logical) Functions
--
FUNCTION "srl" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => '0');
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => '0');
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => '0');
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => '0');
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
--
-- Rotate Left (Logical) Functions
--
FUNCTION "rol" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
--
-- Rotate Right (Logical) Functions
--
FUNCTION "ror" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
--
-- Equal functions.
--
CONSTANT eq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION eq ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN eq_table( l, r );
END;
FUNCTION eq ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (eq( lt, rt ));
END;
FUNCTION "=" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION "=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (eq( lt, rt ));
END;
--
-- Not Equal function.
--
CONSTANT neq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION ne ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN neq_table( l, r );
END;
FUNCTION ne ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (ne( lt, rt ));
END;
FUNCTION "/=" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION "/=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (ne( lt, rt ));
END;
--
-- Less Than functions.
--
CONSTANT ltb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION lt ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN ltb_table( l, r );
END;
FUNCTION lt ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rtt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rtt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : UNSIGNED ( 1 TO ml );
VARIABLE rtt : UNSIGNED ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE ltt, rtt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ltt := (OTHERS => l(l'left)) ;
ltt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rtt := (OTHERS => r(r'left)) ;
rtt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(ltt(ltt'left) = '1' AND rtt(rtt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(ltt(ltt'left) = '0' AND rtt(rtt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (lt( ltt, rtt ));
END IF ;
END;
FUNCTION "<" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : UNSIGNED ( 1 TO ml );
VARIABLE rtt : UNSIGNED ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION "<" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE ltt, rtt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ltt := (OTHERS => l(l'left)) ;
ltt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rtt := (OTHERS => r(r'left)) ;
rtt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(ltt(ltt'left) = '1' AND rtt(rtt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(ltt(ltt'left) = '0' AND rtt(rtt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (lt( ltt, rtt ));
END IF ;
END;
--
-- Greater Than functions.
--
CONSTANT gtb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION gt ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN gtb_table( l, r );
END ;
FUNCTION gt ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (gt( lt, rt ));
END IF ;
END;
FUNCTION ">" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ">" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (gt( lt, rt ));
END IF ;
END;
--
-- Less Than or Equal to functions.
--
CONSTANT leb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | X |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | W |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ) -- | D |
);
FUNCTION le ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN leb_table( l, r );
END ;
TYPE std_ulogic_fuzzy_state IS ('U', 'X', 'T', 'F', 'N');
TYPE std_ulogic_fuzzy_state_table IS ARRAY ( std_ulogic, std_ulogic ) OF std_ulogic_fuzzy_state;
CONSTANT le_fuzzy_table : std_ulogic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U' ), -- | U |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | X |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | 0 |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | Z |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | W |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | L |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | H |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ) -- | D |
);
FUNCTION le ( L,R : std_ulogic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_fuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
TYPE std_logic_fuzzy_state IS ('U', 'X', 'T', 'F', 'N');
TYPE std_logic_fuzzy_state_table IS ARRAY ( std_logic, std_logic ) OF std_logic_fuzzy_state;
CONSTANT le_lfuzzy_table : std_logic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U' ), -- | U |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | X |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | 0 |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | Z |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | W |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | L |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | H |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ) -- | D |
);
FUNCTION le ( L,R : std_logic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION le ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION le (l, r:SIGNED) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (le( lt, rt ));
END IF ;
END;
FUNCTION "<=" ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION "<=" (l, r:SIGNED) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (le( lt, rt ));
END IF ;
END;
--
-- Greater Than or Equal to functions.
--
CONSTANT geb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 1 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | H |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ) -- | D |
);
FUNCTION ge ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN geb_table( l, r );
END ;
CONSTANT ge_fuzzy_table : std_ulogic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U', 'U' ), -- | U |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | X |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | 0 |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | 1 |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | Z |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | W |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | L |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | H |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ) -- | D |
);
FUNCTION ge ( L,R : std_ulogic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_fuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
CONSTANT ge_lfuzzy_table : std_logic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U', 'U' ), -- | U |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | X |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | 0 |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | 1 |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | Z |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | W |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | L |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | H |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ) -- | D |
);
FUNCTION ge ( L,R : std_logic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ge ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ge ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (ge( lt, rt ));
END IF ;
END;
FUNCTION ">=" ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ">=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (ge( lt, rt ));
END IF ;
END;
-------------------------------------------------------------------------------
-- Logical Operations
-------------------------------------------------------------------------------
-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | D |
);
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | D |
);
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
-- truth table for "not" function
CONSTANT not_table: stdlogic_1D :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H D |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
FUNCTION "and" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := and_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "and";
FUNCTION "nand" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( and_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "nand";
FUNCTION "or" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := or_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "or";
FUNCTION "nor" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( or_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "nor";
FUNCTION "xor" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := xor_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "xor";
FUNCTION "not" ( arg1 : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE result : UNSIGNED ( arg1'RANGE ) := (Others => 'X');
begin
for i in result'range loop
result(i) := not_table( arg1(i) );
end loop;
return result;
end "not";
FUNCTION "and" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a and b);
RETURN (answer);
end "and";
FUNCTION "nand" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a nand b);
RETURN (answer);
end "nand";
FUNCTION "or" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a or b);
RETURN (answer);
end "or";
FUNCTION "nor" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a nor b);
RETURN (answer);
end "nor";
FUNCTION "xor" ( arg1, arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a xor b);
RETURN (answer);
end "xor";
FUNCTION "not" ( arg1 : SIGNED ) RETURN SIGNED IS
VARIABLE result : SIGNED ( arg1'RANGE ) := (Others => 'X');
begin
for i in result'range loop
result(i) := not_table( arg1(i) );
end loop;
return result;
end "not";
FUNCTION "xnor" ( arg1, arg2 : std_ulogic_vector ) RETURN std_ulogic_vector IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_vector ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : std_logic_vector ) RETURN std_logic_vector IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_vector ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a xnor b);
RETURN (answer);
end "xnor";
END ;
|
LIBRARY ieee;
-- LIBRARY arithmetic;
PACKAGE BODY std_logic_arith IS
USE ieee.std_logic_1164.ALL;
-- USE arithmetic.utils.all;
-------------------------------------------------------------------
-- Local Types
-------------------------------------------------------------------
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
TYPE stdlogic_boolean_table IS ARRAY(std_ulogic, std_ulogic) OF BOOLEAN;
--------------------------------------------------------------------
--------------------------------------------------------------------
-- FUNCTIONS DEFINED FOR SYNTHESIS
--------------------------------------------------------------------
--------------------------------------------------------------------
FUNCTION std_ulogic_wired_or ( input : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := '-'; -- weakest state default
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ---------------------------------------------------------
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | U |
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'X', 'X', '0', '1', '0', 'X', '0', '1', '0' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ), -- | Z |
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'X', 'X', '0', '1', '0', 'X', '0', '1', '0' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ) -- | D |
);
BEGIN
-- Iterate through all inputs
FOR i IN input'range LOOP
result := resolution_table(result, input(i));
END LOOP;
-- Return the resultant value
RETURN result;
END std_ulogic_wired_or;
FUNCTION std_ulogic_wired_and ( input : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := '-'; -- weakest state default
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ---------------------------------------------------------
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | U |
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'X', 'X', '0', '1', '1', 'X', '0', '1', '1' ), -- | 1 |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ), -- | Z |
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'X', 'X', '0', '1', '1', 'X', '0', '1', '1' ), -- | H |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ) -- | D |
);
BEGIN
-- Iterate through all inputs
FOR i IN input'range LOOP
result := resolution_table(result, input(i));
END LOOP;
-- Return the resultant value
RETURN result;
END std_ulogic_wired_and;
--
-- MGC base level functions
--
--
-- Convert Base Type to Integer
--
FUNCTION to_integer (arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION to_integer (arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION to_integer (arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL IS
VARIABLE tmp : SIGNED( arg1'length DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : NATURAL;
BEGIN
tmp := '0' & SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION TO_INTEGER (arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE return_int,x_tmp : INTEGER := 0;
BEGIN
ASSERT arg1'length > 0
REPORT "NULL vector, returning 0"
SEVERITY NOTE;
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT arg1'length <= 32 -- implementation dependent limit
REPORT "vector too large, conversion may cause overflow"
SEVERITY WARNING;
IF x /= 0 THEN
x_tmp := 1;
END IF;
IF arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L' OR -- positive value
( x_tmp = 0 AND arg1(arg1'left) /= '1' AND arg1(arg1'left) /= 'H') THEN
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => NULL;
WHEN '1'|'H' => return_int := return_int + 1;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
ELSE -- negative value
IF (x_tmp = 0) THEN
x_tmp := 1;
ELSE
x_tmp := 0;
END IF;
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => return_int := return_int + 1;
WHEN '1'|'H' => NULL;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
return_int := (-return_int) - 1;
END IF;
RETURN return_int;
END TO_INTEGER;
FUNCTION to_integer (arg1:STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL IS
BEGIN
IF(arg1 = '0' OR arg1 = 'L' OR (x = 0 AND arg1 /= '1' AND arg1 /= 'H')) THEN
RETURN(0);
ELSE
RETURN(1) ;
END IF ;
END ;
FUNCTION conv_integer (arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_integer (arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length -1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_integer (arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL IS
VARIABLE tmp : SIGNED( arg1'length DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : NATURAL;
BEGIN
tmp := '0' & SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_INTEGER (arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE return_int,x_tmp : INTEGER := 0;
BEGIN
ASSERT arg1'length > 0
REPORT "NULL vector, returning 0"
SEVERITY NOTE;
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT arg1'length <= 32 -- implementation dependent limit
REPORT "vector too large, conversion may cause overflow"
SEVERITY WARNING;
IF x /= 0 THEN
x_tmp := 1;
END IF;
IF arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L' OR -- positive value
( x_tmp = 0 AND arg1(arg1'left) /= '1' AND arg1(arg1'left) /= 'H') THEN
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => NULL;
WHEN '1'|'H' => return_int := return_int + 1;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
ELSE -- negative value
IF (x_tmp = 0) THEN
x_tmp := 1;
ELSE
x_tmp := 0;
END IF;
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => return_int := return_int + 1;
WHEN '1'|'H' => NULL;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
return_int := (-return_int) - 1;
END IF;
RETURN return_int;
END ;
FUNCTION conv_integer (arg1:STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL IS
BEGIN
IF(arg1 = '0' OR arg1 = 'L' OR (x = 0 AND arg1 /= '1' AND arg1 /= 'H')) THEN
RETURN(0);
ELSE
RETURN(1) ;
END IF ;
END ;
--
-- Convert Base Type to STD_LOGIC
--
FUNCTION to_stdlogic (arg1:BOOLEAN) RETURN STD_LOGIC IS
BEGIN
IF(arg1) THEN
RETURN('1') ;
ELSE
RETURN('0') ;
END IF ;
END ;
--
-- Convert Base Type to STD_LOGIC_VECTOR
--
FUNCTION To_StdlogicVector (arg1 : integer; size : NATURAL) RETURN std_logic_vector IS
VARIABLE vector : std_logic_vector(0 TO size-1);
VARIABLE tmp_int : integer := arg1;
VARIABLE carry : std_logic := '1'; -- setup to add 1 if needed
VARIABLE carry2 : std_logic;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END To_StdlogicVector;
FUNCTION To_StdUlogicVector (arg1 : integer; size : NATURAL) RETURN std_ulogic_vector IS
VARIABLE vector : std_ulogic_vector(0 TO size-1);
VARIABLE tmp_int : integer := arg1;
VARIABLE carry : std_ulogic := '1'; -- setup to add 1 if needed
VARIABLE carry2 : std_ulogic;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END To_StdUlogicVector;
--
-- Convert Base Type to UNSIGNED
--
FUNCTION to_unsigned (arg1:NATURAL ; size:NATURAL) RETURN UNSIGNED IS
VARIABLE vector : UNSIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
RETURN vector;
END ;
FUNCTION conv_unsigned (arg1:NATURAL ; size:NATURAL) RETURN UNSIGNED IS
VARIABLE vector : UNSIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
RETURN vector;
END ;
--
-- Convert Base Type to SIGNED
--
FUNCTION to_signed (arg1:INTEGER ; size : NATURAL) RETURN SIGNED IS
VARIABLE vector : SIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
VARIABLE carry : STD_LOGIC := '1'; -- setup to add 1 if needed
VARIABLE carry2 : STD_LOGIC := '0';
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END ;
FUNCTION conv_signed (arg1:INTEGER ; size : NATURAL) RETURN SIGNED IS
VARIABLE vector : SIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
VARIABLE carry : STD_LOGIC := '1'; -- setup to add 1 if needed
VARIABLE carry2 : STD_LOGIC := '0';
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END ;
-- sign/zero extend functions
--
FUNCTION zero_extend ( arg1 : STD_ULOGIC_VECTOR; size : NATURAL ) RETURN STD_ULOGIC_VECTOR
IS
VARIABLE answer : STD_ULOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length-1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : STD_LOGIC_VECTOR; size : NATURAL ) RETURN STD_LOGIC_VECTOR
IS
VARIABLE answer : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length-1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : STD_LOGIC; size : NATURAL ) RETURN STD_LOGIC_VECTOR
IS
VARIABLE answer : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
answer := (OTHERS => '0') ;
answer(0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : UNSIGNED; size : NATURAL ) RETURN UNSIGNED IS
VARIABLE answer : UNSIGNED(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length - 1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION sign_extend ( arg1 : SIGNED; size : NATURAL ) RETURN SIGNED IS
VARIABLE answer : SIGNED(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => arg1(arg1'left)) ;
answer(arg1'length - 1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
-- Some useful generic functions
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : STD_ULOGIC_VECTOR; i : INTEGER ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE qs : STD_ULOGIC_VECTOR (1 TO i);
VARIABLE qt : STD_ULOGIC_VECTOR (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : STD_LOGIC_VECTOR; i : INTEGER ) RETURN STD_LOGIC_VECTOR IS
VARIABLE qs : STD_LOGIC_VECTOR (1 TO i);
VARIABLE qt : STD_LOGIC_VECTOR (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : UNSIGNED; i : INTEGER ) RETURN UNSIGNED IS
VARIABLE qs : UNSIGNED (1 TO i);
VARIABLE qt : UNSIGNED (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--------------------------------------
-- Synthesizable addition Functions --
--------------------------------------
FUNCTION "+" ( arg1, arg2 : STD_LOGIC ) RETURN STD_LOGIC IS
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
BEGIN
RETURN xor_table( arg1, arg2 );
END "+";
function maximum (arg1, arg2: integer) return integer is
begin
if arg1 > arg2 then
return arg1;
else
return arg2;
end if;
end;
FUNCTION "+" (arg1, arg2 :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE carry : STD_ULOGIC := '0';
VARIABLE a,b,s1 : STD_ULOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2 :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE carry : STD_LOGIC := '0';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE res : UNSIGNED(1 TO ml);
VARIABLE carry : STD_LOGIC := '0';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2:SIGNED) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a + b);
RETURN (answer);
END ;
-----------------------------------------
-- Synthesizable subtraction Functions --
-----------------------------------------
FUNCTION "-" ( arg1, arg2 : std_logic ) RETURN std_logic IS
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
BEGIN
RETURN xor_table( arg1, arg2 );
END "-";
FUNCTION "-" (arg1, arg2:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE borrow : STD_ULOGIC := '1';
VARIABLE a,b,s1 : STD_ULOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE borrow : STD_LOGIC := '1';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE res : UNSIGNED(1 TO ml);
VARIABLE borrow : STD_LOGIC := '1';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:SIGNED) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED( a - b );
RETURN (answer);
END ;
-----------------------------------------
-- Unary subtract and add Functions --
-----------------------------------------
FUNCTION "+" (arg1:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:UNSIGNED) RETURN UNSIGNED IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:SIGNED) RETURN SIGNED IS
BEGIN
RETURN (arg1);
END;
FUNCTION hasx( v : SIGNED ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION "-" (arg1:SIGNED) RETURN SIGNED IS
constant len : integer := arg1'length;
VARIABLE answer, tmp : SIGNED( len-1 downto 0 ) := (others=>'0');
VARIABLE index : integer := len;
BEGIN
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
IF hasx(arg1) THEN
answer := (OTHERS => 'X');
ELSE
tmp := arg1;
lp1 : FOR i IN answer'REVERSE_RANGE LOOP
IF (tmp(i) = '1' OR tmp(i) = 'H') THEN
index := i+1;
answer(i downto 0) := tmp(i downto 0);
exit;
END IF;
END LOOP lp1;
answer(len-1 downto index) := NOT tmp(len-1 downto index);
end if;
RETURN (answer);
END ;
--------------------------------------------
-- Synthesizable multiplication Functions --
--------------------------------------------
FUNCTION shift( v : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE v1 : STD_ULOGIC_VECTOR( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN STD_ULOGIC_VECTOR; b : OUT STD_ULOGIC_VECTOR) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR IS
VARIABLE v1 : STD_LOGIC_VECTOR( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN STD_LOGIC_VECTOR; b : OUT STD_LOGIC_VECTOR) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : SIGNED ) RETURN SIGNED IS
VARIABLE v1 : SIGNED( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN SIGNED; b : OUT SIGNED) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE v1 : UNSIGNED( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN UNSIGNED; b : OUT UNSIGNED) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION "*" (arg1, arg2:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE prod : STD_ULOGIC_VECTOR(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION "*" (arg1, arg2:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE prod : STD_LOGIC_VECTOR(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION "*" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE prod : UNSIGNED(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
--//// Sign Extend ////
--
-- Function sxt
--
FUNCTION sxt( q : SIGNED; i : INTEGER ) RETURN SIGNED IS
VARIABLE qs : SIGNED (1 TO i);
VARIABLE qt : SIGNED (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>q(q'left));
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
FUNCTION "*" (arg1, arg2:SIGNED) RETURN SIGNED IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : SIGNED(1 TO ml);
VARIABLE rt : SIGNED(1 TO ml);
VARIABLE prod : SIGNED(1 TO ml) := (OTHERS=>'0');
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := sxt( arg1, ml );
rt := sxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION rshift( v : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE v1 : STD_ULOGIC_VECTOR( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR IS
VARIABLE v1 : STD_LOGIC_VECTOR( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE v1 : UNSIGNED( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : UNSIGNED ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : SIGNED ) RETURN SIGNED IS
VARIABLE v1 : SIGNED( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION "/" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :SIGNED) RETURN SIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : SIGNED(0 TO ml+1);
VARIABLE rt : SIGNED(0 TO ml+1);
VARIABLE quote : SIGNED(1 TO ml);
VARIABLE tmp : SIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : SIGNED(0 TO ml+1) := (OTHERS=>'0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := sxt( l, ml+2 );
WHILE lt >= r LOOP
rt := sxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "MOD" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "MOD" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "MOD" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "REM" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "REM" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "REM" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "**" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
VARIABLE return_vector : STD_ULOGIC_VECTOR(l'range) := (OTHERS=>'0');
VARIABLE tmp : STD_ULOGIC_VECTOR(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
FUNCTION "**" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE return_vector : STD_LOGIC_VECTOR(l'range) := (OTHERS=>'0');
VARIABLE tmp : STD_LOGIC_VECTOR(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
FUNCTION "**" (l, r :UNSIGNED) RETURN UNSIGNED IS
VARIABLE return_vector : UNSIGNED(l'range) := (OTHERS=>'0');
VARIABLE tmp : UNSIGNED(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
--
-- Absolute Value Functions
--
FUNCTION "abs" (arg1:SIGNED) RETURN SIGNED IS
constant len : integer := arg1'length;
VARIABLE answer, tmp : SIGNED( len-1 downto 0 ) := (others=>'0');
VARIABLE index : integer := len;
BEGIN
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
IF hasx(arg1) THEN
answer := (OTHERS => 'X');
ELSIF (arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L') THEN
answer := arg1;
ELSE
tmp := arg1;
lp1 : FOR i IN answer'REVERSE_RANGE LOOP
IF (tmp(i) = '1' OR tmp(i) = 'H') THEN
index := i+1;
answer(i downto 0) := tmp(i downto 0);
exit;
END IF;
END LOOP lp1;
answer(len-1 downto index) := NOT tmp(len-1 downto index);
end if;
RETURN (answer);
END ;
--
-- Shift Left (arithmetic) Functions
--
FUNCTION "sla" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
--
-- Shift Right (arithmetics) Functions
--
FUNCTION "sra" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
--
-- Shift Left (logical) Functions
--
FUNCTION "sll" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others =>'0');
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others =>'0');
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others =>'0');
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others =>'0');
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
--
-- Shift Right (logical) Functions
--
FUNCTION "srl" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => '0');
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => '0');
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => '0');
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => '0');
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
--
-- Rotate Left (Logical) Functions
--
FUNCTION "rol" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
--
-- Rotate Right (Logical) Functions
--
FUNCTION "ror" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
--
-- Equal functions.
--
CONSTANT eq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION eq ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN eq_table( l, r );
END;
FUNCTION eq ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (eq( lt, rt ));
END;
FUNCTION "=" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION "=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (eq( lt, rt ));
END;
--
-- Not Equal function.
--
CONSTANT neq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION ne ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN neq_table( l, r );
END;
FUNCTION ne ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (ne( lt, rt ));
END;
FUNCTION "/=" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION "/=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (ne( lt, rt ));
END;
--
-- Less Than functions.
--
CONSTANT ltb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION lt ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN ltb_table( l, r );
END;
FUNCTION lt ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rtt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rtt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : UNSIGNED ( 1 TO ml );
VARIABLE rtt : UNSIGNED ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE ltt, rtt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ltt := (OTHERS => l(l'left)) ;
ltt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rtt := (OTHERS => r(r'left)) ;
rtt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(ltt(ltt'left) = '1' AND rtt(rtt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(ltt(ltt'left) = '0' AND rtt(rtt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (lt( ltt, rtt ));
END IF ;
END;
FUNCTION "<" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : UNSIGNED ( 1 TO ml );
VARIABLE rtt : UNSIGNED ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION "<" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE ltt, rtt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ltt := (OTHERS => l(l'left)) ;
ltt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rtt := (OTHERS => r(r'left)) ;
rtt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(ltt(ltt'left) = '1' AND rtt(rtt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(ltt(ltt'left) = '0' AND rtt(rtt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (lt( ltt, rtt ));
END IF ;
END;
--
-- Greater Than functions.
--
CONSTANT gtb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION gt ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN gtb_table( l, r );
END ;
FUNCTION gt ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (gt( lt, rt ));
END IF ;
END;
FUNCTION ">" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ">" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (gt( lt, rt ));
END IF ;
END;
--
-- Less Than or Equal to functions.
--
CONSTANT leb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | X |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | W |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ) -- | D |
);
FUNCTION le ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN leb_table( l, r );
END ;
TYPE std_ulogic_fuzzy_state IS ('U', 'X', 'T', 'F', 'N');
TYPE std_ulogic_fuzzy_state_table IS ARRAY ( std_ulogic, std_ulogic ) OF std_ulogic_fuzzy_state;
CONSTANT le_fuzzy_table : std_ulogic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U' ), -- | U |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | X |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | 0 |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | Z |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | W |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | L |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | H |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ) -- | D |
);
FUNCTION le ( L,R : std_ulogic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_fuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
TYPE std_logic_fuzzy_state IS ('U', 'X', 'T', 'F', 'N');
TYPE std_logic_fuzzy_state_table IS ARRAY ( std_logic, std_logic ) OF std_logic_fuzzy_state;
CONSTANT le_lfuzzy_table : std_logic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U' ), -- | U |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | X |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | 0 |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | Z |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | W |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | L |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | H |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ) -- | D |
);
FUNCTION le ( L,R : std_logic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION le ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION le (l, r:SIGNED) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (le( lt, rt ));
END IF ;
END;
FUNCTION "<=" ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION "<=" (l, r:SIGNED) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (le( lt, rt ));
END IF ;
END;
--
-- Greater Than or Equal to functions.
--
CONSTANT geb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 1 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | H |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ) -- | D |
);
FUNCTION ge ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN geb_table( l, r );
END ;
CONSTANT ge_fuzzy_table : std_ulogic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U', 'U' ), -- | U |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | X |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | 0 |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | 1 |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | Z |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | W |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | L |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | H |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ) -- | D |
);
FUNCTION ge ( L,R : std_ulogic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_fuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
CONSTANT ge_lfuzzy_table : std_logic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U', 'U' ), -- | U |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | X |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | 0 |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | 1 |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | Z |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | W |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | L |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | H |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ) -- | D |
);
FUNCTION ge ( L,R : std_logic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ge ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ge ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (ge( lt, rt ));
END IF ;
END;
FUNCTION ">=" ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ">=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (ge( lt, rt ));
END IF ;
END;
-------------------------------------------------------------------------------
-- Logical Operations
-------------------------------------------------------------------------------
-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | D |
);
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | D |
);
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
-- truth table for "not" function
CONSTANT not_table: stdlogic_1D :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H D |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
FUNCTION "and" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := and_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "and";
FUNCTION "nand" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( and_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "nand";
FUNCTION "or" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := or_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "or";
FUNCTION "nor" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( or_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "nor";
FUNCTION "xor" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := xor_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "xor";
FUNCTION "not" ( arg1 : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE result : UNSIGNED ( arg1'RANGE ) := (Others => 'X');
begin
for i in result'range loop
result(i) := not_table( arg1(i) );
end loop;
return result;
end "not";
FUNCTION "and" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a and b);
RETURN (answer);
end "and";
FUNCTION "nand" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a nand b);
RETURN (answer);
end "nand";
FUNCTION "or" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a or b);
RETURN (answer);
end "or";
FUNCTION "nor" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a nor b);
RETURN (answer);
end "nor";
FUNCTION "xor" ( arg1, arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a xor b);
RETURN (answer);
end "xor";
FUNCTION "not" ( arg1 : SIGNED ) RETURN SIGNED IS
VARIABLE result : SIGNED ( arg1'RANGE ) := (Others => 'X');
begin
for i in result'range loop
result(i) := not_table( arg1(i) );
end loop;
return result;
end "not";
FUNCTION "xnor" ( arg1, arg2 : std_ulogic_vector ) RETURN std_ulogic_vector IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_vector ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : std_logic_vector ) RETURN std_logic_vector IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_vector ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a xnor b);
RETURN (answer);
end "xnor";
END ;
|
LIBRARY ieee;
-- LIBRARY arithmetic;
PACKAGE BODY std_logic_arith IS
USE ieee.std_logic_1164.ALL;
-- USE arithmetic.utils.all;
-------------------------------------------------------------------
-- Local Types
-------------------------------------------------------------------
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
TYPE stdlogic_boolean_table IS ARRAY(std_ulogic, std_ulogic) OF BOOLEAN;
--------------------------------------------------------------------
--------------------------------------------------------------------
-- FUNCTIONS DEFINED FOR SYNTHESIS
--------------------------------------------------------------------
--------------------------------------------------------------------
FUNCTION std_ulogic_wired_or ( input : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := '-'; -- weakest state default
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ---------------------------------------------------------
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | U |
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'X', 'X', '0', '1', '0', 'X', '0', '1', '0' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ), -- | Z |
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'X', 'X', '0', '1', '0', 'X', '0', '1', '0' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ) -- | D |
);
BEGIN
-- Iterate through all inputs
FOR i IN input'range LOOP
result := resolution_table(result, input(i));
END LOOP;
-- Return the resultant value
RETURN result;
END std_ulogic_wired_or;
FUNCTION std_ulogic_wired_and ( input : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := '-'; -- weakest state default
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ---------------------------------------------------------
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | U |
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'X', 'X', '0', '1', '1', 'X', '0', '1', '1' ), -- | 1 |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ), -- | Z |
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'X', 'X', '0', '1', '1', 'X', '0', '1', '1' ), -- | H |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ) -- | D |
);
BEGIN
-- Iterate through all inputs
FOR i IN input'range LOOP
result := resolution_table(result, input(i));
END LOOP;
-- Return the resultant value
RETURN result;
END std_ulogic_wired_and;
--
-- MGC base level functions
--
--
-- Convert Base Type to Integer
--
FUNCTION to_integer (arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION to_integer (arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION to_integer (arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL IS
VARIABLE tmp : SIGNED( arg1'length DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : NATURAL;
BEGIN
tmp := '0' & SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION TO_INTEGER (arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE return_int,x_tmp : INTEGER := 0;
BEGIN
ASSERT arg1'length > 0
REPORT "NULL vector, returning 0"
SEVERITY NOTE;
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT arg1'length <= 32 -- implementation dependent limit
REPORT "vector too large, conversion may cause overflow"
SEVERITY WARNING;
IF x /= 0 THEN
x_tmp := 1;
END IF;
IF arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L' OR -- positive value
( x_tmp = 0 AND arg1(arg1'left) /= '1' AND arg1(arg1'left) /= 'H') THEN
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => NULL;
WHEN '1'|'H' => return_int := return_int + 1;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
ELSE -- negative value
IF (x_tmp = 0) THEN
x_tmp := 1;
ELSE
x_tmp := 0;
END IF;
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => return_int := return_int + 1;
WHEN '1'|'H' => NULL;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
return_int := (-return_int) - 1;
END IF;
RETURN return_int;
END TO_INTEGER;
FUNCTION to_integer (arg1:STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL IS
BEGIN
IF(arg1 = '0' OR arg1 = 'L' OR (x = 0 AND arg1 /= '1' AND arg1 /= 'H')) THEN
RETURN(0);
ELSE
RETURN(1) ;
END IF ;
END ;
FUNCTION conv_integer (arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_integer (arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length -1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_integer (arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL IS
VARIABLE tmp : SIGNED( arg1'length DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : NATURAL;
BEGIN
tmp := '0' & SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_INTEGER (arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE return_int,x_tmp : INTEGER := 0;
BEGIN
ASSERT arg1'length > 0
REPORT "NULL vector, returning 0"
SEVERITY NOTE;
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT arg1'length <= 32 -- implementation dependent limit
REPORT "vector too large, conversion may cause overflow"
SEVERITY WARNING;
IF x /= 0 THEN
x_tmp := 1;
END IF;
IF arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L' OR -- positive value
( x_tmp = 0 AND arg1(arg1'left) /= '1' AND arg1(arg1'left) /= 'H') THEN
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => NULL;
WHEN '1'|'H' => return_int := return_int + 1;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
ELSE -- negative value
IF (x_tmp = 0) THEN
x_tmp := 1;
ELSE
x_tmp := 0;
END IF;
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => return_int := return_int + 1;
WHEN '1'|'H' => NULL;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
return_int := (-return_int) - 1;
END IF;
RETURN return_int;
END ;
FUNCTION conv_integer (arg1:STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL IS
BEGIN
IF(arg1 = '0' OR arg1 = 'L' OR (x = 0 AND arg1 /= '1' AND arg1 /= 'H')) THEN
RETURN(0);
ELSE
RETURN(1) ;
END IF ;
END ;
--
-- Convert Base Type to STD_LOGIC
--
FUNCTION to_stdlogic (arg1:BOOLEAN) RETURN STD_LOGIC IS
BEGIN
IF(arg1) THEN
RETURN('1') ;
ELSE
RETURN('0') ;
END IF ;
END ;
--
-- Convert Base Type to STD_LOGIC_VECTOR
--
FUNCTION To_StdlogicVector (arg1 : integer; size : NATURAL) RETURN std_logic_vector IS
VARIABLE vector : std_logic_vector(0 TO size-1);
VARIABLE tmp_int : integer := arg1;
VARIABLE carry : std_logic := '1'; -- setup to add 1 if needed
VARIABLE carry2 : std_logic;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END To_StdlogicVector;
FUNCTION To_StdUlogicVector (arg1 : integer; size : NATURAL) RETURN std_ulogic_vector IS
VARIABLE vector : std_ulogic_vector(0 TO size-1);
VARIABLE tmp_int : integer := arg1;
VARIABLE carry : std_ulogic := '1'; -- setup to add 1 if needed
VARIABLE carry2 : std_ulogic;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END To_StdUlogicVector;
--
-- Convert Base Type to UNSIGNED
--
FUNCTION to_unsigned (arg1:NATURAL ; size:NATURAL) RETURN UNSIGNED IS
VARIABLE vector : UNSIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
RETURN vector;
END ;
FUNCTION conv_unsigned (arg1:NATURAL ; size:NATURAL) RETURN UNSIGNED IS
VARIABLE vector : UNSIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
RETURN vector;
END ;
--
-- Convert Base Type to SIGNED
--
FUNCTION to_signed (arg1:INTEGER ; size : NATURAL) RETURN SIGNED IS
VARIABLE vector : SIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
VARIABLE carry : STD_LOGIC := '1'; -- setup to add 1 if needed
VARIABLE carry2 : STD_LOGIC := '0';
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END ;
FUNCTION conv_signed (arg1:INTEGER ; size : NATURAL) RETURN SIGNED IS
VARIABLE vector : SIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
VARIABLE carry : STD_LOGIC := '1'; -- setup to add 1 if needed
VARIABLE carry2 : STD_LOGIC := '0';
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END ;
-- sign/zero extend functions
--
FUNCTION zero_extend ( arg1 : STD_ULOGIC_VECTOR; size : NATURAL ) RETURN STD_ULOGIC_VECTOR
IS
VARIABLE answer : STD_ULOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length-1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : STD_LOGIC_VECTOR; size : NATURAL ) RETURN STD_LOGIC_VECTOR
IS
VARIABLE answer : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length-1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : STD_LOGIC; size : NATURAL ) RETURN STD_LOGIC_VECTOR
IS
VARIABLE answer : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
answer := (OTHERS => '0') ;
answer(0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : UNSIGNED; size : NATURAL ) RETURN UNSIGNED IS
VARIABLE answer : UNSIGNED(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length - 1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION sign_extend ( arg1 : SIGNED; size : NATURAL ) RETURN SIGNED IS
VARIABLE answer : SIGNED(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => arg1(arg1'left)) ;
answer(arg1'length - 1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
-- Some useful generic functions
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : STD_ULOGIC_VECTOR; i : INTEGER ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE qs : STD_ULOGIC_VECTOR (1 TO i);
VARIABLE qt : STD_ULOGIC_VECTOR (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : STD_LOGIC_VECTOR; i : INTEGER ) RETURN STD_LOGIC_VECTOR IS
VARIABLE qs : STD_LOGIC_VECTOR (1 TO i);
VARIABLE qt : STD_LOGIC_VECTOR (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : UNSIGNED; i : INTEGER ) RETURN UNSIGNED IS
VARIABLE qs : UNSIGNED (1 TO i);
VARIABLE qt : UNSIGNED (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--------------------------------------
-- Synthesizable addition Functions --
--------------------------------------
FUNCTION "+" ( arg1, arg2 : STD_LOGIC ) RETURN STD_LOGIC IS
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
BEGIN
RETURN xor_table( arg1, arg2 );
END "+";
function maximum (arg1, arg2: integer) return integer is
begin
if arg1 > arg2 then
return arg1;
else
return arg2;
end if;
end;
FUNCTION "+" (arg1, arg2 :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE carry : STD_ULOGIC := '0';
VARIABLE a,b,s1 : STD_ULOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2 :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE carry : STD_LOGIC := '0';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE res : UNSIGNED(1 TO ml);
VARIABLE carry : STD_LOGIC := '0';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2:SIGNED) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a + b);
RETURN (answer);
END ;
-----------------------------------------
-- Synthesizable subtraction Functions --
-----------------------------------------
FUNCTION "-" ( arg1, arg2 : std_logic ) RETURN std_logic IS
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
BEGIN
RETURN xor_table( arg1, arg2 );
END "-";
FUNCTION "-" (arg1, arg2:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE borrow : STD_ULOGIC := '1';
VARIABLE a,b,s1 : STD_ULOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE borrow : STD_LOGIC := '1';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE res : UNSIGNED(1 TO ml);
VARIABLE borrow : STD_LOGIC := '1';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:SIGNED) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED( a - b );
RETURN (answer);
END ;
-----------------------------------------
-- Unary subtract and add Functions --
-----------------------------------------
FUNCTION "+" (arg1:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:UNSIGNED) RETURN UNSIGNED IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:SIGNED) RETURN SIGNED IS
BEGIN
RETURN (arg1);
END;
FUNCTION hasx( v : SIGNED ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION "-" (arg1:SIGNED) RETURN SIGNED IS
constant len : integer := arg1'length;
VARIABLE answer, tmp : SIGNED( len-1 downto 0 ) := (others=>'0');
VARIABLE index : integer := len;
BEGIN
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
IF hasx(arg1) THEN
answer := (OTHERS => 'X');
ELSE
tmp := arg1;
lp1 : FOR i IN answer'REVERSE_RANGE LOOP
IF (tmp(i) = '1' OR tmp(i) = 'H') THEN
index := i+1;
answer(i downto 0) := tmp(i downto 0);
exit;
END IF;
END LOOP lp1;
answer(len-1 downto index) := NOT tmp(len-1 downto index);
end if;
RETURN (answer);
END ;
--------------------------------------------
-- Synthesizable multiplication Functions --
--------------------------------------------
FUNCTION shift( v : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE v1 : STD_ULOGIC_VECTOR( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN STD_ULOGIC_VECTOR; b : OUT STD_ULOGIC_VECTOR) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR IS
VARIABLE v1 : STD_LOGIC_VECTOR( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN STD_LOGIC_VECTOR; b : OUT STD_LOGIC_VECTOR) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : SIGNED ) RETURN SIGNED IS
VARIABLE v1 : SIGNED( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN SIGNED; b : OUT SIGNED) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE v1 : UNSIGNED( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN UNSIGNED; b : OUT UNSIGNED) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION "*" (arg1, arg2:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE prod : STD_ULOGIC_VECTOR(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION "*" (arg1, arg2:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE prod : STD_LOGIC_VECTOR(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION "*" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE prod : UNSIGNED(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
--//// Sign Extend ////
--
-- Function sxt
--
FUNCTION sxt( q : SIGNED; i : INTEGER ) RETURN SIGNED IS
VARIABLE qs : SIGNED (1 TO i);
VARIABLE qt : SIGNED (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>q(q'left));
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
FUNCTION "*" (arg1, arg2:SIGNED) RETURN SIGNED IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : SIGNED(1 TO ml);
VARIABLE rt : SIGNED(1 TO ml);
VARIABLE prod : SIGNED(1 TO ml) := (OTHERS=>'0');
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := sxt( arg1, ml );
rt := sxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION rshift( v : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE v1 : STD_ULOGIC_VECTOR( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR IS
VARIABLE v1 : STD_LOGIC_VECTOR( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE v1 : UNSIGNED( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : UNSIGNED ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : SIGNED ) RETURN SIGNED IS
VARIABLE v1 : SIGNED( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION "/" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :SIGNED) RETURN SIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : SIGNED(0 TO ml+1);
VARIABLE rt : SIGNED(0 TO ml+1);
VARIABLE quote : SIGNED(1 TO ml);
VARIABLE tmp : SIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : SIGNED(0 TO ml+1) := (OTHERS=>'0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := sxt( l, ml+2 );
WHILE lt >= r LOOP
rt := sxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "MOD" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "MOD" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "MOD" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "REM" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "REM" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "REM" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "**" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
VARIABLE return_vector : STD_ULOGIC_VECTOR(l'range) := (OTHERS=>'0');
VARIABLE tmp : STD_ULOGIC_VECTOR(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
FUNCTION "**" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE return_vector : STD_LOGIC_VECTOR(l'range) := (OTHERS=>'0');
VARIABLE tmp : STD_LOGIC_VECTOR(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
FUNCTION "**" (l, r :UNSIGNED) RETURN UNSIGNED IS
VARIABLE return_vector : UNSIGNED(l'range) := (OTHERS=>'0');
VARIABLE tmp : UNSIGNED(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
--
-- Absolute Value Functions
--
FUNCTION "abs" (arg1:SIGNED) RETURN SIGNED IS
constant len : integer := arg1'length;
VARIABLE answer, tmp : SIGNED( len-1 downto 0 ) := (others=>'0');
VARIABLE index : integer := len;
BEGIN
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
IF hasx(arg1) THEN
answer := (OTHERS => 'X');
ELSIF (arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L') THEN
answer := arg1;
ELSE
tmp := arg1;
lp1 : FOR i IN answer'REVERSE_RANGE LOOP
IF (tmp(i) = '1' OR tmp(i) = 'H') THEN
index := i+1;
answer(i downto 0) := tmp(i downto 0);
exit;
END IF;
END LOOP lp1;
answer(len-1 downto index) := NOT tmp(len-1 downto index);
end if;
RETURN (answer);
END ;
--
-- Shift Left (arithmetic) Functions
--
FUNCTION "sla" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
--
-- Shift Right (arithmetics) Functions
--
FUNCTION "sra" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
--
-- Shift Left (logical) Functions
--
FUNCTION "sll" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others =>'0');
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others =>'0');
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others =>'0');
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others =>'0');
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
--
-- Shift Right (logical) Functions
--
FUNCTION "srl" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => '0');
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => '0');
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => '0');
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => '0');
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
--
-- Rotate Left (Logical) Functions
--
FUNCTION "rol" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
--
-- Rotate Right (Logical) Functions
--
FUNCTION "ror" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
--
-- Equal functions.
--
CONSTANT eq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION eq ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN eq_table( l, r );
END;
FUNCTION eq ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (eq( lt, rt ));
END;
FUNCTION "=" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION "=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (eq( lt, rt ));
END;
--
-- Not Equal function.
--
CONSTANT neq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION ne ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN neq_table( l, r );
END;
FUNCTION ne ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (ne( lt, rt ));
END;
FUNCTION "/=" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION "/=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (ne( lt, rt ));
END;
--
-- Less Than functions.
--
CONSTANT ltb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION lt ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN ltb_table( l, r );
END;
FUNCTION lt ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rtt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rtt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : UNSIGNED ( 1 TO ml );
VARIABLE rtt : UNSIGNED ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE ltt, rtt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ltt := (OTHERS => l(l'left)) ;
ltt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rtt := (OTHERS => r(r'left)) ;
rtt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(ltt(ltt'left) = '1' AND rtt(rtt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(ltt(ltt'left) = '0' AND rtt(rtt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (lt( ltt, rtt ));
END IF ;
END;
FUNCTION "<" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : UNSIGNED ( 1 TO ml );
VARIABLE rtt : UNSIGNED ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION "<" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE ltt, rtt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ltt := (OTHERS => l(l'left)) ;
ltt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rtt := (OTHERS => r(r'left)) ;
rtt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(ltt(ltt'left) = '1' AND rtt(rtt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(ltt(ltt'left) = '0' AND rtt(rtt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (lt( ltt, rtt ));
END IF ;
END;
--
-- Greater Than functions.
--
CONSTANT gtb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION gt ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN gtb_table( l, r );
END ;
FUNCTION gt ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (gt( lt, rt ));
END IF ;
END;
FUNCTION ">" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ">" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (gt( lt, rt ));
END IF ;
END;
--
-- Less Than or Equal to functions.
--
CONSTANT leb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | X |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | W |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ) -- | D |
);
FUNCTION le ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN leb_table( l, r );
END ;
TYPE std_ulogic_fuzzy_state IS ('U', 'X', 'T', 'F', 'N');
TYPE std_ulogic_fuzzy_state_table IS ARRAY ( std_ulogic, std_ulogic ) OF std_ulogic_fuzzy_state;
CONSTANT le_fuzzy_table : std_ulogic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U' ), -- | U |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | X |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | 0 |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | Z |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | W |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | L |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | H |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ) -- | D |
);
FUNCTION le ( L,R : std_ulogic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_fuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
TYPE std_logic_fuzzy_state IS ('U', 'X', 'T', 'F', 'N');
TYPE std_logic_fuzzy_state_table IS ARRAY ( std_logic, std_logic ) OF std_logic_fuzzy_state;
CONSTANT le_lfuzzy_table : std_logic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U' ), -- | U |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | X |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | 0 |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | Z |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | W |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | L |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | H |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ) -- | D |
);
FUNCTION le ( L,R : std_logic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION le ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION le (l, r:SIGNED) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (le( lt, rt ));
END IF ;
END;
FUNCTION "<=" ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION "<=" (l, r:SIGNED) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (le( lt, rt ));
END IF ;
END;
--
-- Greater Than or Equal to functions.
--
CONSTANT geb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 1 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | H |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ) -- | D |
);
FUNCTION ge ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN geb_table( l, r );
END ;
CONSTANT ge_fuzzy_table : std_ulogic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U', 'U' ), -- | U |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | X |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | 0 |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | 1 |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | Z |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | W |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | L |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | H |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ) -- | D |
);
FUNCTION ge ( L,R : std_ulogic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_fuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
CONSTANT ge_lfuzzy_table : std_logic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U', 'U' ), -- | U |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | X |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | 0 |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | 1 |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | Z |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | W |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | L |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | H |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ) -- | D |
);
FUNCTION ge ( L,R : std_logic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ge ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ge ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (ge( lt, rt ));
END IF ;
END;
FUNCTION ">=" ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ">=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (ge( lt, rt ));
END IF ;
END;
-------------------------------------------------------------------------------
-- Logical Operations
-------------------------------------------------------------------------------
-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | D |
);
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | D |
);
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
-- truth table for "not" function
CONSTANT not_table: stdlogic_1D :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H D |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
FUNCTION "and" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := and_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "and";
FUNCTION "nand" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( and_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "nand";
FUNCTION "or" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := or_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "or";
FUNCTION "nor" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( or_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "nor";
FUNCTION "xor" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := xor_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "xor";
FUNCTION "not" ( arg1 : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE result : UNSIGNED ( arg1'RANGE ) := (Others => 'X');
begin
for i in result'range loop
result(i) := not_table( arg1(i) );
end loop;
return result;
end "not";
FUNCTION "and" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a and b);
RETURN (answer);
end "and";
FUNCTION "nand" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a nand b);
RETURN (answer);
end "nand";
FUNCTION "or" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a or b);
RETURN (answer);
end "or";
FUNCTION "nor" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a nor b);
RETURN (answer);
end "nor";
FUNCTION "xor" ( arg1, arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a xor b);
RETURN (answer);
end "xor";
FUNCTION "not" ( arg1 : SIGNED ) RETURN SIGNED IS
VARIABLE result : SIGNED ( arg1'RANGE ) := (Others => 'X');
begin
for i in result'range loop
result(i) := not_table( arg1(i) );
end loop;
return result;
end "not";
FUNCTION "xnor" ( arg1, arg2 : std_ulogic_vector ) RETURN std_ulogic_vector IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_vector ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : std_logic_vector ) RETURN std_logic_vector IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_vector ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a xnor b);
RETURN (answer);
end "xnor";
END ;
|
LIBRARY ieee;
-- LIBRARY arithmetic;
PACKAGE BODY std_logic_arith IS
USE ieee.std_logic_1164.ALL;
-- USE arithmetic.utils.all;
-------------------------------------------------------------------
-- Local Types
-------------------------------------------------------------------
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
TYPE stdlogic_boolean_table IS ARRAY(std_ulogic, std_ulogic) OF BOOLEAN;
--------------------------------------------------------------------
--------------------------------------------------------------------
-- FUNCTIONS DEFINED FOR SYNTHESIS
--------------------------------------------------------------------
--------------------------------------------------------------------
FUNCTION std_ulogic_wired_or ( input : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := '-'; -- weakest state default
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ---------------------------------------------------------
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | U |
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'X', 'X', '0', '1', '0', 'X', '0', '1', '0' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ), -- | Z |
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'X', 'X', '0', '1', '0', 'X', '0', '1', '0' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ) -- | D |
);
BEGIN
-- Iterate through all inputs
FOR i IN input'range LOOP
result := resolution_table(result, input(i));
END LOOP;
-- Return the resultant value
RETURN result;
END std_ulogic_wired_or;
FUNCTION std_ulogic_wired_and ( input : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := '-'; -- weakest state default
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ---------------------------------------------------------
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | U |
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'X', 'X', '0', '1', '1', 'X', '0', '1', '1' ), -- | 1 |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ), -- | Z |
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'X', 'X', '0', '1', '1', 'X', '0', '1', '1' ), -- | H |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ) -- | D |
);
BEGIN
-- Iterate through all inputs
FOR i IN input'range LOOP
result := resolution_table(result, input(i));
END LOOP;
-- Return the resultant value
RETURN result;
END std_ulogic_wired_and;
--
-- MGC base level functions
--
--
-- Convert Base Type to Integer
--
FUNCTION to_integer (arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION to_integer (arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION to_integer (arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL IS
VARIABLE tmp : SIGNED( arg1'length DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : NATURAL;
BEGIN
tmp := '0' & SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION TO_INTEGER (arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE return_int,x_tmp : INTEGER := 0;
BEGIN
ASSERT arg1'length > 0
REPORT "NULL vector, returning 0"
SEVERITY NOTE;
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT arg1'length <= 32 -- implementation dependent limit
REPORT "vector too large, conversion may cause overflow"
SEVERITY WARNING;
IF x /= 0 THEN
x_tmp := 1;
END IF;
IF arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L' OR -- positive value
( x_tmp = 0 AND arg1(arg1'left) /= '1' AND arg1(arg1'left) /= 'H') THEN
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => NULL;
WHEN '1'|'H' => return_int := return_int + 1;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
ELSE -- negative value
IF (x_tmp = 0) THEN
x_tmp := 1;
ELSE
x_tmp := 0;
END IF;
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => return_int := return_int + 1;
WHEN '1'|'H' => NULL;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
return_int := (-return_int) - 1;
END IF;
RETURN return_int;
END TO_INTEGER;
FUNCTION to_integer (arg1:STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL IS
BEGIN
IF(arg1 = '0' OR arg1 = 'L' OR (x = 0 AND arg1 /= '1' AND arg1 /= 'H')) THEN
RETURN(0);
ELSE
RETURN(1) ;
END IF ;
END ;
FUNCTION conv_integer (arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_integer (arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length -1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_integer (arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL IS
VARIABLE tmp : SIGNED( arg1'length DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : NATURAL;
BEGIN
tmp := '0' & SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_INTEGER (arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE return_int,x_tmp : INTEGER := 0;
BEGIN
ASSERT arg1'length > 0
REPORT "NULL vector, returning 0"
SEVERITY NOTE;
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT arg1'length <= 32 -- implementation dependent limit
REPORT "vector too large, conversion may cause overflow"
SEVERITY WARNING;
IF x /= 0 THEN
x_tmp := 1;
END IF;
IF arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L' OR -- positive value
( x_tmp = 0 AND arg1(arg1'left) /= '1' AND arg1(arg1'left) /= 'H') THEN
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => NULL;
WHEN '1'|'H' => return_int := return_int + 1;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
ELSE -- negative value
IF (x_tmp = 0) THEN
x_tmp := 1;
ELSE
x_tmp := 0;
END IF;
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => return_int := return_int + 1;
WHEN '1'|'H' => NULL;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
return_int := (-return_int) - 1;
END IF;
RETURN return_int;
END ;
FUNCTION conv_integer (arg1:STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL IS
BEGIN
IF(arg1 = '0' OR arg1 = 'L' OR (x = 0 AND arg1 /= '1' AND arg1 /= 'H')) THEN
RETURN(0);
ELSE
RETURN(1) ;
END IF ;
END ;
--
-- Convert Base Type to STD_LOGIC
--
FUNCTION to_stdlogic (arg1:BOOLEAN) RETURN STD_LOGIC IS
BEGIN
IF(arg1) THEN
RETURN('1') ;
ELSE
RETURN('0') ;
END IF ;
END ;
--
-- Convert Base Type to STD_LOGIC_VECTOR
--
FUNCTION To_StdlogicVector (arg1 : integer; size : NATURAL) RETURN std_logic_vector IS
VARIABLE vector : std_logic_vector(0 TO size-1);
VARIABLE tmp_int : integer := arg1;
VARIABLE carry : std_logic := '1'; -- setup to add 1 if needed
VARIABLE carry2 : std_logic;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END To_StdlogicVector;
FUNCTION To_StdUlogicVector (arg1 : integer; size : NATURAL) RETURN std_ulogic_vector IS
VARIABLE vector : std_ulogic_vector(0 TO size-1);
VARIABLE tmp_int : integer := arg1;
VARIABLE carry : std_ulogic := '1'; -- setup to add 1 if needed
VARIABLE carry2 : std_ulogic;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END To_StdUlogicVector;
--
-- Convert Base Type to UNSIGNED
--
FUNCTION to_unsigned (arg1:NATURAL ; size:NATURAL) RETURN UNSIGNED IS
VARIABLE vector : UNSIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
RETURN vector;
END ;
FUNCTION conv_unsigned (arg1:NATURAL ; size:NATURAL) RETURN UNSIGNED IS
VARIABLE vector : UNSIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
RETURN vector;
END ;
--
-- Convert Base Type to SIGNED
--
FUNCTION to_signed (arg1:INTEGER ; size : NATURAL) RETURN SIGNED IS
VARIABLE vector : SIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
VARIABLE carry : STD_LOGIC := '1'; -- setup to add 1 if needed
VARIABLE carry2 : STD_LOGIC := '0';
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END ;
FUNCTION conv_signed (arg1:INTEGER ; size : NATURAL) RETURN SIGNED IS
VARIABLE vector : SIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
VARIABLE carry : STD_LOGIC := '1'; -- setup to add 1 if needed
VARIABLE carry2 : STD_LOGIC := '0';
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END ;
-- sign/zero extend functions
--
FUNCTION zero_extend ( arg1 : STD_ULOGIC_VECTOR; size : NATURAL ) RETURN STD_ULOGIC_VECTOR
IS
VARIABLE answer : STD_ULOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length-1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : STD_LOGIC_VECTOR; size : NATURAL ) RETURN STD_LOGIC_VECTOR
IS
VARIABLE answer : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length-1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : STD_LOGIC; size : NATURAL ) RETURN STD_LOGIC_VECTOR
IS
VARIABLE answer : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
answer := (OTHERS => '0') ;
answer(0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : UNSIGNED; size : NATURAL ) RETURN UNSIGNED IS
VARIABLE answer : UNSIGNED(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length - 1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION sign_extend ( arg1 : SIGNED; size : NATURAL ) RETURN SIGNED IS
VARIABLE answer : SIGNED(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => arg1(arg1'left)) ;
answer(arg1'length - 1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
-- Some useful generic functions
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : STD_ULOGIC_VECTOR; i : INTEGER ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE qs : STD_ULOGIC_VECTOR (1 TO i);
VARIABLE qt : STD_ULOGIC_VECTOR (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : STD_LOGIC_VECTOR; i : INTEGER ) RETURN STD_LOGIC_VECTOR IS
VARIABLE qs : STD_LOGIC_VECTOR (1 TO i);
VARIABLE qt : STD_LOGIC_VECTOR (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : UNSIGNED; i : INTEGER ) RETURN UNSIGNED IS
VARIABLE qs : UNSIGNED (1 TO i);
VARIABLE qt : UNSIGNED (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--------------------------------------
-- Synthesizable addition Functions --
--------------------------------------
FUNCTION "+" ( arg1, arg2 : STD_LOGIC ) RETURN STD_LOGIC IS
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
BEGIN
RETURN xor_table( arg1, arg2 );
END "+";
function maximum (arg1, arg2: integer) return integer is
begin
if arg1 > arg2 then
return arg1;
else
return arg2;
end if;
end;
FUNCTION "+" (arg1, arg2 :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE carry : STD_ULOGIC := '0';
VARIABLE a,b,s1 : STD_ULOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2 :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE carry : STD_LOGIC := '0';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE res : UNSIGNED(1 TO ml);
VARIABLE carry : STD_LOGIC := '0';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2:SIGNED) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a + b);
RETURN (answer);
END ;
-----------------------------------------
-- Synthesizable subtraction Functions --
-----------------------------------------
FUNCTION "-" ( arg1, arg2 : std_logic ) RETURN std_logic IS
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
BEGIN
RETURN xor_table( arg1, arg2 );
END "-";
FUNCTION "-" (arg1, arg2:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE borrow : STD_ULOGIC := '1';
VARIABLE a,b,s1 : STD_ULOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE borrow : STD_LOGIC := '1';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE res : UNSIGNED(1 TO ml);
VARIABLE borrow : STD_LOGIC := '1';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:SIGNED) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED( a - b );
RETURN (answer);
END ;
-----------------------------------------
-- Unary subtract and add Functions --
-----------------------------------------
FUNCTION "+" (arg1:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:UNSIGNED) RETURN UNSIGNED IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:SIGNED) RETURN SIGNED IS
BEGIN
RETURN (arg1);
END;
FUNCTION hasx( v : SIGNED ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION "-" (arg1:SIGNED) RETURN SIGNED IS
constant len : integer := arg1'length;
VARIABLE answer, tmp : SIGNED( len-1 downto 0 ) := (others=>'0');
VARIABLE index : integer := len;
BEGIN
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
IF hasx(arg1) THEN
answer := (OTHERS => 'X');
ELSE
tmp := arg1;
lp1 : FOR i IN answer'REVERSE_RANGE LOOP
IF (tmp(i) = '1' OR tmp(i) = 'H') THEN
index := i+1;
answer(i downto 0) := tmp(i downto 0);
exit;
END IF;
END LOOP lp1;
answer(len-1 downto index) := NOT tmp(len-1 downto index);
end if;
RETURN (answer);
END ;
--------------------------------------------
-- Synthesizable multiplication Functions --
--------------------------------------------
FUNCTION shift( v : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE v1 : STD_ULOGIC_VECTOR( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN STD_ULOGIC_VECTOR; b : OUT STD_ULOGIC_VECTOR) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR IS
VARIABLE v1 : STD_LOGIC_VECTOR( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN STD_LOGIC_VECTOR; b : OUT STD_LOGIC_VECTOR) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : SIGNED ) RETURN SIGNED IS
VARIABLE v1 : SIGNED( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN SIGNED; b : OUT SIGNED) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE v1 : UNSIGNED( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN UNSIGNED; b : OUT UNSIGNED) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION "*" (arg1, arg2:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE prod : STD_ULOGIC_VECTOR(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION "*" (arg1, arg2:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE prod : STD_LOGIC_VECTOR(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION "*" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE prod : UNSIGNED(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
--//// Sign Extend ////
--
-- Function sxt
--
FUNCTION sxt( q : SIGNED; i : INTEGER ) RETURN SIGNED IS
VARIABLE qs : SIGNED (1 TO i);
VARIABLE qt : SIGNED (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>q(q'left));
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
FUNCTION "*" (arg1, arg2:SIGNED) RETURN SIGNED IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : SIGNED(1 TO ml);
VARIABLE rt : SIGNED(1 TO ml);
VARIABLE prod : SIGNED(1 TO ml) := (OTHERS=>'0');
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := sxt( arg1, ml );
rt := sxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION rshift( v : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE v1 : STD_ULOGIC_VECTOR( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR IS
VARIABLE v1 : STD_LOGIC_VECTOR( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE v1 : UNSIGNED( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : UNSIGNED ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : SIGNED ) RETURN SIGNED IS
VARIABLE v1 : SIGNED( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION "/" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :SIGNED) RETURN SIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : SIGNED(0 TO ml+1);
VARIABLE rt : SIGNED(0 TO ml+1);
VARIABLE quote : SIGNED(1 TO ml);
VARIABLE tmp : SIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : SIGNED(0 TO ml+1) := (OTHERS=>'0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := sxt( l, ml+2 );
WHILE lt >= r LOOP
rt := sxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "MOD" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "MOD" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "MOD" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "REM" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "REM" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "REM" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "**" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
VARIABLE return_vector : STD_ULOGIC_VECTOR(l'range) := (OTHERS=>'0');
VARIABLE tmp : STD_ULOGIC_VECTOR(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
FUNCTION "**" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE return_vector : STD_LOGIC_VECTOR(l'range) := (OTHERS=>'0');
VARIABLE tmp : STD_LOGIC_VECTOR(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
FUNCTION "**" (l, r :UNSIGNED) RETURN UNSIGNED IS
VARIABLE return_vector : UNSIGNED(l'range) := (OTHERS=>'0');
VARIABLE tmp : UNSIGNED(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
--
-- Absolute Value Functions
--
FUNCTION "abs" (arg1:SIGNED) RETURN SIGNED IS
constant len : integer := arg1'length;
VARIABLE answer, tmp : SIGNED( len-1 downto 0 ) := (others=>'0');
VARIABLE index : integer := len;
BEGIN
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
IF hasx(arg1) THEN
answer := (OTHERS => 'X');
ELSIF (arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L') THEN
answer := arg1;
ELSE
tmp := arg1;
lp1 : FOR i IN answer'REVERSE_RANGE LOOP
IF (tmp(i) = '1' OR tmp(i) = 'H') THEN
index := i+1;
answer(i downto 0) := tmp(i downto 0);
exit;
END IF;
END LOOP lp1;
answer(len-1 downto index) := NOT tmp(len-1 downto index);
end if;
RETURN (answer);
END ;
--
-- Shift Left (arithmetic) Functions
--
FUNCTION "sla" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
--
-- Shift Right (arithmetics) Functions
--
FUNCTION "sra" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
--
-- Shift Left (logical) Functions
--
FUNCTION "sll" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others =>'0');
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others =>'0');
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others =>'0');
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others =>'0');
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
--
-- Shift Right (logical) Functions
--
FUNCTION "srl" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => '0');
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => '0');
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => '0');
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => '0');
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
--
-- Rotate Left (Logical) Functions
--
FUNCTION "rol" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
--
-- Rotate Right (Logical) Functions
--
FUNCTION "ror" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
--
-- Equal functions.
--
CONSTANT eq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION eq ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN eq_table( l, r );
END;
FUNCTION eq ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (eq( lt, rt ));
END;
FUNCTION "=" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION "=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (eq( lt, rt ));
END;
--
-- Not Equal function.
--
CONSTANT neq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION ne ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN neq_table( l, r );
END;
FUNCTION ne ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (ne( lt, rt ));
END;
FUNCTION "/=" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION "/=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (ne( lt, rt ));
END;
--
-- Less Than functions.
--
CONSTANT ltb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION lt ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN ltb_table( l, r );
END;
FUNCTION lt ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rtt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rtt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : UNSIGNED ( 1 TO ml );
VARIABLE rtt : UNSIGNED ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE ltt, rtt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ltt := (OTHERS => l(l'left)) ;
ltt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rtt := (OTHERS => r(r'left)) ;
rtt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(ltt(ltt'left) = '1' AND rtt(rtt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(ltt(ltt'left) = '0' AND rtt(rtt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (lt( ltt, rtt ));
END IF ;
END;
FUNCTION "<" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : UNSIGNED ( 1 TO ml );
VARIABLE rtt : UNSIGNED ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION "<" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE ltt, rtt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ltt := (OTHERS => l(l'left)) ;
ltt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rtt := (OTHERS => r(r'left)) ;
rtt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(ltt(ltt'left) = '1' AND rtt(rtt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(ltt(ltt'left) = '0' AND rtt(rtt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (lt( ltt, rtt ));
END IF ;
END;
--
-- Greater Than functions.
--
CONSTANT gtb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION gt ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN gtb_table( l, r );
END ;
FUNCTION gt ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (gt( lt, rt ));
END IF ;
END;
FUNCTION ">" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ">" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (gt( lt, rt ));
END IF ;
END;
--
-- Less Than or Equal to functions.
--
CONSTANT leb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | X |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | W |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ) -- | D |
);
FUNCTION le ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN leb_table( l, r );
END ;
TYPE std_ulogic_fuzzy_state IS ('U', 'X', 'T', 'F', 'N');
TYPE std_ulogic_fuzzy_state_table IS ARRAY ( std_ulogic, std_ulogic ) OF std_ulogic_fuzzy_state;
CONSTANT le_fuzzy_table : std_ulogic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U' ), -- | U |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | X |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | 0 |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | Z |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | W |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | L |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | H |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ) -- | D |
);
FUNCTION le ( L,R : std_ulogic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_fuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
TYPE std_logic_fuzzy_state IS ('U', 'X', 'T', 'F', 'N');
TYPE std_logic_fuzzy_state_table IS ARRAY ( std_logic, std_logic ) OF std_logic_fuzzy_state;
CONSTANT le_lfuzzy_table : std_logic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U' ), -- | U |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | X |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | 0 |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | Z |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | W |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | L |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | H |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ) -- | D |
);
FUNCTION le ( L,R : std_logic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION le ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION le (l, r:SIGNED) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (le( lt, rt ));
END IF ;
END;
FUNCTION "<=" ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION "<=" (l, r:SIGNED) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (le( lt, rt ));
END IF ;
END;
--
-- Greater Than or Equal to functions.
--
CONSTANT geb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 1 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | H |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ) -- | D |
);
FUNCTION ge ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN geb_table( l, r );
END ;
CONSTANT ge_fuzzy_table : std_ulogic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U', 'U' ), -- | U |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | X |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | 0 |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | 1 |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | Z |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | W |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | L |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | H |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ) -- | D |
);
FUNCTION ge ( L,R : std_ulogic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_fuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
CONSTANT ge_lfuzzy_table : std_logic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U', 'U' ), -- | U |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | X |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | 0 |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | 1 |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | Z |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | W |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | L |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | H |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ) -- | D |
);
FUNCTION ge ( L,R : std_logic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ge ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ge ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (ge( lt, rt ));
END IF ;
END;
FUNCTION ">=" ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ">=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (ge( lt, rt ));
END IF ;
END;
-------------------------------------------------------------------------------
-- Logical Operations
-------------------------------------------------------------------------------
-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | D |
);
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | D |
);
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
-- truth table for "not" function
CONSTANT not_table: stdlogic_1D :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H D |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
FUNCTION "and" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := and_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "and";
FUNCTION "nand" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( and_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "nand";
FUNCTION "or" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := or_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "or";
FUNCTION "nor" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( or_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "nor";
FUNCTION "xor" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := xor_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "xor";
FUNCTION "not" ( arg1 : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE result : UNSIGNED ( arg1'RANGE ) := (Others => 'X');
begin
for i in result'range loop
result(i) := not_table( arg1(i) );
end loop;
return result;
end "not";
FUNCTION "and" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a and b);
RETURN (answer);
end "and";
FUNCTION "nand" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a nand b);
RETURN (answer);
end "nand";
FUNCTION "or" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a or b);
RETURN (answer);
end "or";
FUNCTION "nor" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a nor b);
RETURN (answer);
end "nor";
FUNCTION "xor" ( arg1, arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a xor b);
RETURN (answer);
end "xor";
FUNCTION "not" ( arg1 : SIGNED ) RETURN SIGNED IS
VARIABLE result : SIGNED ( arg1'RANGE ) := (Others => 'X');
begin
for i in result'range loop
result(i) := not_table( arg1(i) );
end loop;
return result;
end "not";
FUNCTION "xnor" ( arg1, arg2 : std_ulogic_vector ) RETURN std_ulogic_vector IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_vector ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : std_logic_vector ) RETURN std_logic_vector IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_vector ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a xnor b);
RETURN (answer);
end "xnor";
END ;
|
LIBRARY ieee;
-- LIBRARY arithmetic;
PACKAGE BODY std_logic_arith IS
USE ieee.std_logic_1164.ALL;
-- USE arithmetic.utils.all;
-------------------------------------------------------------------
-- Local Types
-------------------------------------------------------------------
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
TYPE stdlogic_boolean_table IS ARRAY(std_ulogic, std_ulogic) OF BOOLEAN;
--------------------------------------------------------------------
--------------------------------------------------------------------
-- FUNCTIONS DEFINED FOR SYNTHESIS
--------------------------------------------------------------------
--------------------------------------------------------------------
FUNCTION std_ulogic_wired_or ( input : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := '-'; -- weakest state default
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ---------------------------------------------------------
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | U |
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'X', 'X', '0', '1', '0', 'X', '0', '1', '0' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ), -- | Z |
( 'X', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'X', 'X', '0', '1', '0', 'X', '0', '1', '0' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ) -- | D |
);
BEGIN
-- Iterate through all inputs
FOR i IN input'range LOOP
result := resolution_table(result, input(i));
END LOOP;
-- Return the resultant value
RETURN result;
END std_ulogic_wired_or;
FUNCTION std_ulogic_wired_and ( input : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := '-'; -- weakest state default
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ---------------------------------------------------------
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | U |
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'X', 'X', '0', '1', '1', 'X', '0', '1', '1' ), -- | 1 |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ), -- | Z |
( 'X', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'X', 'X', '0', '1', '1', 'X', '0', '1', '1' ), -- | H |
( 'X', 'X', '0', '1', 'Z', 'X', '0', '1', 'Z' ) -- | D |
);
BEGIN
-- Iterate through all inputs
FOR i IN input'range LOOP
result := resolution_table(result, input(i));
END LOOP;
-- Return the resultant value
RETURN result;
END std_ulogic_wired_and;
--
-- MGC base level functions
--
--
-- Convert Base Type to Integer
--
FUNCTION to_integer (arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION to_integer (arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION to_integer (arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL IS
VARIABLE tmp : SIGNED( arg1'length DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : NATURAL;
BEGIN
tmp := '0' & SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END to_integer;
FUNCTION TO_INTEGER (arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE return_int,x_tmp : INTEGER := 0;
BEGIN
ASSERT arg1'length > 0
REPORT "NULL vector, returning 0"
SEVERITY NOTE;
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT arg1'length <= 32 -- implementation dependent limit
REPORT "vector too large, conversion may cause overflow"
SEVERITY WARNING;
IF x /= 0 THEN
x_tmp := 1;
END IF;
IF arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L' OR -- positive value
( x_tmp = 0 AND arg1(arg1'left) /= '1' AND arg1(arg1'left) /= 'H') THEN
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => NULL;
WHEN '1'|'H' => return_int := return_int + 1;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
ELSE -- negative value
IF (x_tmp = 0) THEN
x_tmp := 1;
ELSE
x_tmp := 0;
END IF;
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => return_int := return_int + 1;
WHEN '1'|'H' => NULL;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
return_int := (-return_int) - 1;
END IF;
RETURN return_int;
END TO_INTEGER;
FUNCTION to_integer (arg1:STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL IS
BEGIN
IF(arg1 = '0' OR arg1 = 'L' OR (x = 0 AND arg1 /= '1' AND arg1 /= 'H')) THEN
RETURN(0);
ELSE
RETURN(1) ;
END IF ;
END ;
FUNCTION conv_integer (arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length - 1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_integer (arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE tmp : SIGNED( arg1'length -1 DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : INTEGER;
BEGIN
tmp := SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_integer (arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL IS
VARIABLE tmp : SIGNED( arg1'length DOWNTO 0 ) := (OTHERS => '0');
VARIABLE result : NATURAL;
BEGIN
tmp := '0' & SIGNED(arg1);
result := TO_INTEGER( tmp, x );
RETURN (result);
END ;
FUNCTION conv_INTEGER (arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER IS
VARIABLE return_int,x_tmp : INTEGER := 0;
BEGIN
ASSERT arg1'length > 0
REPORT "NULL vector, returning 0"
SEVERITY NOTE;
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT arg1'length <= 32 -- implementation dependent limit
REPORT "vector too large, conversion may cause overflow"
SEVERITY WARNING;
IF x /= 0 THEN
x_tmp := 1;
END IF;
IF arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L' OR -- positive value
( x_tmp = 0 AND arg1(arg1'left) /= '1' AND arg1(arg1'left) /= 'H') THEN
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => NULL;
WHEN '1'|'H' => return_int := return_int + 1;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
ELSE -- negative value
IF (x_tmp = 0) THEN
x_tmp := 1;
ELSE
x_tmp := 0;
END IF;
FOR i IN arg1'range LOOP
return_int := return_int * 2;
CASE arg1(i) IS
WHEN '0'|'L' => return_int := return_int + 1;
WHEN '1'|'H' => NULL;
WHEN OTHERS => return_int := return_int + x_tmp;
END CASE;
END LOOP;
return_int := (-return_int) - 1;
END IF;
RETURN return_int;
END ;
FUNCTION conv_integer (arg1:STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL IS
BEGIN
IF(arg1 = '0' OR arg1 = 'L' OR (x = 0 AND arg1 /= '1' AND arg1 /= 'H')) THEN
RETURN(0);
ELSE
RETURN(1) ;
END IF ;
END ;
--
-- Convert Base Type to STD_LOGIC
--
FUNCTION to_stdlogic (arg1:BOOLEAN) RETURN STD_LOGIC IS
BEGIN
IF(arg1) THEN
RETURN('1') ;
ELSE
RETURN('0') ;
END IF ;
END ;
--
-- Convert Base Type to STD_LOGIC_VECTOR
--
FUNCTION To_StdlogicVector (arg1 : integer; size : NATURAL) RETURN std_logic_vector IS
VARIABLE vector : std_logic_vector(0 TO size-1);
VARIABLE tmp_int : integer := arg1;
VARIABLE carry : std_logic := '1'; -- setup to add 1 if needed
VARIABLE carry2 : std_logic;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END To_StdlogicVector;
FUNCTION To_StdUlogicVector (arg1 : integer; size : NATURAL) RETURN std_ulogic_vector IS
VARIABLE vector : std_ulogic_vector(0 TO size-1);
VARIABLE tmp_int : integer := arg1;
VARIABLE carry : std_ulogic := '1'; -- setup to add 1 if needed
VARIABLE carry2 : std_ulogic;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END To_StdUlogicVector;
--
-- Convert Base Type to UNSIGNED
--
FUNCTION to_unsigned (arg1:NATURAL ; size:NATURAL) RETURN UNSIGNED IS
VARIABLE vector : UNSIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
RETURN vector;
END ;
FUNCTION conv_unsigned (arg1:NATURAL ; size:NATURAL) RETURN UNSIGNED IS
VARIABLE vector : UNSIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
RETURN vector;
END ;
--
-- Convert Base Type to SIGNED
--
FUNCTION to_signed (arg1:INTEGER ; size : NATURAL) RETURN SIGNED IS
VARIABLE vector : SIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
VARIABLE carry : STD_LOGIC := '1'; -- setup to add 1 if needed
VARIABLE carry2 : STD_LOGIC := '0';
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END ;
FUNCTION conv_signed (arg1:INTEGER ; size : NATURAL) RETURN SIGNED IS
VARIABLE vector : SIGNED(0 TO size-1) := (OTHERS => '0');
VARIABLE tmp_int : INTEGER := arg1;
VARIABLE carry : STD_LOGIC := '1'; -- setup to add 1 if needed
VARIABLE carry2 : STD_LOGIC := '0';
BEGIN
FOR i IN size-1 DOWNTO 0 LOOP
IF tmp_int MOD 2 = 1 THEN
vector(i) := '1';
ELSE
vector(i) := '0';
END IF;
tmp_int := tmp_int / 2;
END LOOP;
IF arg1 < 0 THEN
FOR i IN size-1 DOWNTO 0 LOOP
carry2 := (NOT vector(i)) AND carry;
vector(i) := (NOT vector(i)) XOR carry;
carry := carry2;
END LOOP;
END IF;
RETURN vector;
END ;
-- sign/zero extend functions
--
FUNCTION zero_extend ( arg1 : STD_ULOGIC_VECTOR; size : NATURAL ) RETURN STD_ULOGIC_VECTOR
IS
VARIABLE answer : STD_ULOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length-1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : STD_LOGIC_VECTOR; size : NATURAL ) RETURN STD_LOGIC_VECTOR
IS
VARIABLE answer : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length-1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : STD_LOGIC; size : NATURAL ) RETURN STD_LOGIC_VECTOR
IS
VARIABLE answer : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
answer := (OTHERS => '0') ;
answer(0) := arg1;
RETURN(answer) ;
END ;
FUNCTION zero_extend ( arg1 : UNSIGNED; size : NATURAL ) RETURN UNSIGNED IS
VARIABLE answer : UNSIGNED(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => '0') ;
answer(arg1'length - 1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
FUNCTION sign_extend ( arg1 : SIGNED; size : NATURAL ) RETURN SIGNED IS
VARIABLE answer : SIGNED(size-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
ASSERT arg1'length <= size
REPORT "Vector is already larger then size."
SEVERITY WARNING ;
answer := (OTHERS => arg1(arg1'left)) ;
answer(arg1'length - 1 DOWNTO 0) := arg1;
RETURN(answer) ;
END ;
-- Some useful generic functions
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : STD_ULOGIC_VECTOR; i : INTEGER ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE qs : STD_ULOGIC_VECTOR (1 TO i);
VARIABLE qt : STD_ULOGIC_VECTOR (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : STD_LOGIC_VECTOR; i : INTEGER ) RETURN STD_LOGIC_VECTOR IS
VARIABLE qs : STD_LOGIC_VECTOR (1 TO i);
VARIABLE qt : STD_LOGIC_VECTOR (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--//// Zero Extend ////
--
-- Function zxt
--
FUNCTION zxt( q : UNSIGNED; i : INTEGER ) RETURN UNSIGNED IS
VARIABLE qs : UNSIGNED (1 TO i);
VARIABLE qt : UNSIGNED (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
--------------------------------------
-- Synthesizable addition Functions --
--------------------------------------
FUNCTION "+" ( arg1, arg2 : STD_LOGIC ) RETURN STD_LOGIC IS
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
BEGIN
RETURN xor_table( arg1, arg2 );
END "+";
function maximum (arg1, arg2: integer) return integer is
begin
if arg1 > arg2 then
return arg1;
else
return arg2;
end if;
end;
FUNCTION "+" (arg1, arg2 :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE carry : STD_ULOGIC := '0';
VARIABLE a,b,s1 : STD_ULOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2 :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE carry : STD_LOGIC := '0';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE res : UNSIGNED(1 TO ml);
VARIABLE carry : STD_LOGIC := '0';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := rt(i);
s1 := a + b;
res(i) := s1 + carry;
carry := (a AND b) OR (s1 AND carry);
END LOOP;
RETURN res;
END;
FUNCTION "+" (arg1, arg2:SIGNED) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a + b);
RETURN (answer);
END ;
-----------------------------------------
-- Synthesizable subtraction Functions --
-----------------------------------------
FUNCTION "-" ( arg1, arg2 : std_logic ) RETURN std_logic IS
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
BEGIN
RETURN xor_table( arg1, arg2 );
END "-";
FUNCTION "-" (arg1, arg2:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE borrow : STD_ULOGIC := '1';
VARIABLE a,b,s1 : STD_ULOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE res : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE borrow : STD_LOGIC := '1';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length);
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE res : UNSIGNED(1 TO ml);
VARIABLE borrow : STD_LOGIC := '1';
VARIABLE a,b,s1 : STD_LOGIC;
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'reverse_range LOOP
a := lt(i);
b := NOT rt(i);
s1 := a + b;
res(i) := s1 + borrow;
borrow := (a AND b) OR (s1 AND borrow);
END LOOP;
RETURN res;
END "-";
FUNCTION "-" (arg1, arg2:SIGNED) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED( a - b );
RETURN (answer);
END ;
-----------------------------------------
-- Unary subtract and add Functions --
-----------------------------------------
FUNCTION "+" (arg1:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:UNSIGNED) RETURN UNSIGNED IS
BEGIN
RETURN (arg1);
END;
FUNCTION "+" (arg1:SIGNED) RETURN SIGNED IS
BEGIN
RETURN (arg1);
END;
FUNCTION hasx( v : SIGNED ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION "-" (arg1:SIGNED) RETURN SIGNED IS
constant len : integer := arg1'length;
VARIABLE answer, tmp : SIGNED( len-1 downto 0 ) := (others=>'0');
VARIABLE index : integer := len;
BEGIN
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
IF hasx(arg1) THEN
answer := (OTHERS => 'X');
ELSE
tmp := arg1;
lp1 : FOR i IN answer'REVERSE_RANGE LOOP
IF (tmp(i) = '1' OR tmp(i) = 'H') THEN
index := i+1;
answer(i downto 0) := tmp(i downto 0);
exit;
END IF;
END LOOP lp1;
answer(len-1 downto index) := NOT tmp(len-1 downto index);
end if;
RETURN (answer);
END ;
--------------------------------------------
-- Synthesizable multiplication Functions --
--------------------------------------------
FUNCTION shift( v : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE v1 : STD_ULOGIC_VECTOR( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN STD_ULOGIC_VECTOR; b : OUT STD_ULOGIC_VECTOR) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR IS
VARIABLE v1 : STD_LOGIC_VECTOR( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN STD_LOGIC_VECTOR; b : OUT STD_LOGIC_VECTOR) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : SIGNED ) RETURN SIGNED IS
VARIABLE v1 : SIGNED( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN SIGNED; b : OUT SIGNED) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION shift( v : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE v1 : UNSIGNED( v'range );
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
PROCEDURE copy(a : IN UNSIGNED; b : OUT UNSIGNED) IS
VARIABLE bi : INTEGER := b'right;
BEGIN
FOR i IN a'reverse_range LOOP
b(bi) := a(i);
bi := bi - 1;
END LOOP;
END copy;
FUNCTION "*" (arg1, arg2:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE prod : STD_ULOGIC_VECTOR(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION "*" (arg1, arg2:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE prod : STD_LOGIC_VECTOR(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION "*" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : UNSIGNED(1 TO ml);
VARIABLE rt : UNSIGNED(1 TO ml);
VARIABLE prod : UNSIGNED(1 TO ml) := (OTHERS=>'0');
BEGIN
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
--//// Sign Extend ////
--
-- Function sxt
--
FUNCTION sxt( q : SIGNED; i : INTEGER ) RETURN SIGNED IS
VARIABLE qs : SIGNED (1 TO i);
VARIABLE qt : SIGNED (1 TO q'length);
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>q(q'left));
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
FUNCTION "*" (arg1, arg2:SIGNED) RETURN SIGNED IS
VARIABLE ml : INTEGER := arg1'length + arg2'length;
VARIABLE lt : SIGNED(1 TO ml);
VARIABLE rt : SIGNED(1 TO ml);
VARIABLE prod : SIGNED(1 TO ml) := (OTHERS=>'0');
BEGIN
assert arg1'length > 1 AND arg2'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := sxt( arg1, ml );
rt := sxt( arg2, ml );
FOR i IN rt'reverse_range LOOP
IF rt(i) = '1' THEN
prod := prod + lt;
END IF;
lt := shift(lt);
END LOOP;
RETURN prod;
END "*";
FUNCTION rshift( v : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR IS
VARIABLE v1 : STD_ULOGIC_VECTOR( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR IS
VARIABLE v1 : STD_LOGIC_VECTOR( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE v1 : UNSIGNED( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION hasx( v : UNSIGNED ) RETURN BOOLEAN IS
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION rshift( v : SIGNED ) RETURN SIGNED IS
VARIABLE v1 : SIGNED( v'range );
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION "/" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "/" (l, r :SIGNED) RETURN SIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : SIGNED(0 TO ml+1);
VARIABLE rt : SIGNED(0 TO ml+1);
VARIABLE quote : SIGNED(1 TO ml);
VARIABLE tmp : SIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : SIGNED(0 TO ml+1) := (OTHERS=>'0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN quote'range LOOP
quote(i) := 'X';
END LOOP;
ELSE
lt := sxt( l, ml+2 );
WHILE lt >= r LOOP
rt := sxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
END IF;
quote := tmp(2 TO ml+1);
RETURN quote;
END "/";
FUNCTION "MOD" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "MOD" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "MOD" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "MOD";
FUNCTION "REM" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_ULOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_ULOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_ULOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_ULOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "REM" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE rt : STD_LOGIC_VECTOR(0 TO ml+1);
VARIABLE quote : STD_LOGIC_VECTOR(1 TO ml);
VARIABLE tmp : STD_LOGIC_VECTOR(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : STD_LOGIC_VECTOR(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "REM" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml);
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml) := (OTHERS=>'0');
BEGIN
ASSERT NOT (r = "0")
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
IF hasx(l) OR hasx(r) THEN
FOR i IN lt'range LOOP
lt(i) := 'X';
END LOOP;
ELSE
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
END IF;
RETURN lt(2 TO ml+1);
END "REM";
FUNCTION "**" (l, r :STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
VARIABLE return_vector : STD_ULOGIC_VECTOR(l'range) := (OTHERS=>'0');
VARIABLE tmp : STD_ULOGIC_VECTOR(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
FUNCTION "**" (l, r :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE return_vector : STD_LOGIC_VECTOR(l'range) := (OTHERS=>'0');
VARIABLE tmp : STD_LOGIC_VECTOR(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
FUNCTION "**" (l, r :UNSIGNED) RETURN UNSIGNED IS
VARIABLE return_vector : UNSIGNED(l'range) := (OTHERS=>'0');
VARIABLE tmp : UNSIGNED(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := to_integer( r, 0 );
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
--
-- Absolute Value Functions
--
FUNCTION "abs" (arg1:SIGNED) RETURN SIGNED IS
constant len : integer := arg1'length;
VARIABLE answer, tmp : SIGNED( len-1 downto 0 ) := (others=>'0');
VARIABLE index : integer := len;
BEGIN
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
IF hasx(arg1) THEN
answer := (OTHERS => 'X');
ELSIF (arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L') THEN
answer := arg1;
ELSE
tmp := arg1;
lp1 : FOR i IN answer'REVERSE_RANGE LOOP
IF (tmp(i) = '1' OR tmp(i) = 'H') THEN
index := i+1;
answer(i downto 0) := tmp(i downto 0);
exit;
END IF;
END LOOP lp1;
answer(len-1 downto index) := NOT tmp(len-1 downto index);
end if;
RETURN (answer);
END ;
--
-- Shift Left (arithmetic) Functions
--
FUNCTION "sla" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sla" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
--
-- Shift Right (arithmetics) Functions
--
FUNCTION "sra" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "sra" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
--
-- Shift Left (logical) Functions
--
FUNCTION "sll" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others =>'0');
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others =>'0');
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others =>'0');
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
FUNCTION "sll" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others =>'0');
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(arg2+1 to len) & se(1 to arg2));
END IF;
END ;
--
-- Shift Right (logical) Functions
--
FUNCTION "srl" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_ulogic_vector(1 to len) := (others => '0');
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : std_logic_vector(1 to len) := (others => '0');
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => '0');
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
FUNCTION "srl" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => '0');
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (arg2 >= len) THEN
RETURN (se);
ELSIF (arg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (se(1 to arg2) & ans(1 to len-arg2));
END IF;
END ;
--
-- Rotate Left (Logical) Functions
--
FUNCTION "rol" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
FUNCTION "rol" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
END ;
--
-- Rotate Right (Logical) Functions
--
FUNCTION "ror" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_ULOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : STD_LOGIC_VECTOR(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : UNSIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
FUNCTION "ror" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : SIGNED(1 to len) := arg1;
BEGIN
IF (marg2 = 0) THEN
RETURN (arg1);
ELSE
RETURN (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
END ;
--
-- Equal functions.
--
CONSTANT eq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION eq ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN eq_table( l, r );
END;
FUNCTION eq ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (eq( lt, rt ));
END;
FUNCTION "=" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN FALSE;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION "=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (eq( lt, rt ));
END;
--
-- Not Equal function.
--
CONSTANT neq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION ne ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN neq_table( l, r );
END;
FUNCTION ne ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ne ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (ne( lt, rt ));
END;
FUNCTION "/=" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF ne( lt(i), rt(i) ) THEN
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION "/=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
RETURN (ne( lt, rt ));
END;
--
-- Less Than functions.
--
CONSTANT ltb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION lt ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
BEGIN
RETURN ltb_table( l, r );
END;
FUNCTION lt ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rtt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rtt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : UNSIGNED ( 1 TO ml );
VARIABLE rtt : UNSIGNED ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION lt ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE ltt, rtt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ltt := (OTHERS => l(l'left)) ;
ltt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rtt := (OTHERS => r(r'left)) ;
rtt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(ltt(ltt'left) = '1' AND rtt(rtt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(ltt(ltt'left) = '0' AND rtt(rtt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (lt( ltt, rtt ));
END IF ;
END;
FUNCTION "<" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE ltt : UNSIGNED ( 1 TO ml );
VARIABLE rtt : UNSIGNED ( 1 TO ml );
BEGIN
ltt := zxt( l, ml );
rtt := zxt( r, ml );
FOR i IN ltt'range LOOP
IF NOT eq( ltt(i), rtt(i) ) THEN
RETURN lt( ltt(i), rtt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION "<" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE ltt, rtt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
ltt := (OTHERS => l(l'left)) ;
ltt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rtt := (OTHERS => r(r'left)) ;
rtt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(ltt(ltt'left) = '1' AND rtt(rtt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(ltt(ltt'left) = '0' AND rtt(rtt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (lt( ltt, rtt ));
END IF ;
END;
--
-- Greater Than functions.
--
CONSTANT gtb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
FUNCTION gt ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN gtb_table( l, r );
END ;
FUNCTION gt ( l,r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_ULOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_ULOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : STD_LOGIC_VECTOR ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : STD_LOGIC_VECTOR ( 1 TO ml );
VARIABLE rt : STD_LOGIC_VECTOR ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION gt ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (gt( lt, rt ));
END IF ;
END;
FUNCTION ">" ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
RETURN gt( lt(i), rt(i) );
END IF;
END LOOP;
RETURN FALSE;
END;
FUNCTION ">" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (gt( lt, rt ));
END IF ;
END;
--
-- Less Than or Equal to functions.
--
CONSTANT leb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | X |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | W |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ) -- | D |
);
FUNCTION le ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN leb_table( l, r );
END ;
TYPE std_ulogic_fuzzy_state IS ('U', 'X', 'T', 'F', 'N');
TYPE std_ulogic_fuzzy_state_table IS ARRAY ( std_ulogic, std_ulogic ) OF std_ulogic_fuzzy_state;
CONSTANT le_fuzzy_table : std_ulogic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U' ), -- | U |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | X |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | 0 |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | Z |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | W |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | L |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | H |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ) -- | D |
);
FUNCTION le ( L,R : std_ulogic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_fuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
TYPE std_logic_fuzzy_state IS ('U', 'X', 'T', 'F', 'N');
TYPE std_logic_fuzzy_state_table IS ARRAY ( std_logic, std_logic ) OF std_logic_fuzzy_state;
CONSTANT le_lfuzzy_table : std_logic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U' ), -- | U |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | X |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | 0 |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | Z |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ), -- | W |
( 'N', 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N' ), -- | L |
( 'U', 'X', 'F', 'N', 'X', 'X', 'F', 'N', 'X' ), -- | H |
( 'U', 'X', 'X', 'N', 'X', 'X', 'X', 'N', 'X' ) -- | D |
);
FUNCTION le ( L,R : std_logic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION le ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION le (l, r:SIGNED) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (le( lt, rt ));
END IF ;
END;
FUNCTION "<=" ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := le_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION "<=" (l, r:SIGNED) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(TRUE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(FALSE) ;
ELSE
RETURN (le( lt, rt ));
END IF ;
END;
--
-- Greater Than or Equal to functions.
--
CONSTANT geb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 1 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | H |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ) -- | D |
);
FUNCTION ge ( l, r : std_logic ) RETURN BOOLEAN IS
BEGIN
RETURN geb_table( l, r );
END ;
CONSTANT ge_fuzzy_table : std_ulogic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U', 'U' ), -- | U |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | X |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | 0 |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | 1 |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | Z |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | W |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | L |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | H |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ) -- | D |
);
FUNCTION ge ( L,R : std_ulogic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_fuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
CONSTANT ge_lfuzzy_table : std_logic_fuzzy_state_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'N', 'U', 'U', 'U', 'N', 'U', 'U' ), -- | U |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | X |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | 0 |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | 1 |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | Z |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ), -- | W |
( 'U', 'X', 'N', 'F', 'X', 'X', 'N', 'F', 'X' ), -- | L |
( 'N', 'N', 'T', 'N', 'N', 'N', 'T', 'N', 'N' ), -- | H |
( 'U', 'X', 'N', 'X', 'X', 'X', 'N', 'X', 'X' ) -- | D |
);
FUNCTION ge ( L,R : std_logic_vector ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ge ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ge ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (ge( lt, rt ));
END IF ;
END;
FUNCTION ">=" ( L,R : UNSIGNED ) RETURN boolean IS
CONSTANT ml : integer := maximum( L'LENGTH, R'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : std_logic_fuzzy_state;
begin
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'RANGE LOOP
res := ge_lfuzzy_table( lt(i), rt(i) );
CASE res IS
WHEN 'U' => RETURN FALSE;
WHEN 'X' => RETURN FALSE;
WHEN 'T' => RETURN TRUE;
WHEN 'F' => RETURN FALSE;
WHEN OTHERS => null;
END CASE;
END LOOP;
RETURN TRUE;
end ;
FUNCTION ">=" ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
IF(lt(lt'left) = '1' AND rt(rt'left) = '0') THEN
RETURN(FALSE) ;
ELSIF(lt(lt'left) = '0' AND rt(rt'left) = '1') THEN
RETURN(TRUE) ;
ELSE
RETURN (ge( lt, rt ));
END IF ;
END;
-------------------------------------------------------------------------------
-- Logical Operations
-------------------------------------------------------------------------------
-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | D |
);
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | D |
);
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
-- truth table for "not" function
CONSTANT not_table: stdlogic_1D :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H D |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
FUNCTION "and" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := and_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "and";
FUNCTION "nand" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( and_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "nand";
FUNCTION "or" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := or_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "or";
FUNCTION "nor" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( or_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "nor";
FUNCTION "xor" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := xor_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "xor";
FUNCTION "not" ( arg1 : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE result : UNSIGNED ( arg1'RANGE ) := (Others => 'X');
begin
for i in result'range loop
result(i) := not_table( arg1(i) );
end loop;
return result;
end "not";
FUNCTION "and" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a and b);
RETURN (answer);
end "and";
FUNCTION "nand" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a nand b);
RETURN (answer);
end "nand";
FUNCTION "or" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a or b);
RETURN (answer);
end "or";
FUNCTION "nor" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a nor b);
RETURN (answer);
end "nor";
FUNCTION "xor" ( arg1, arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a xor b);
RETURN (answer);
end "xor";
FUNCTION "not" ( arg1 : SIGNED ) RETURN SIGNED IS
VARIABLE result : SIGNED ( arg1'RANGE ) := (Others => 'X');
begin
for i in result'range loop
result(i) := not_table( arg1(i) );
end loop;
return result;
end "not";
FUNCTION "xnor" ( arg1, arg2 : std_ulogic_vector ) RETURN std_ulogic_vector IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : std_ulogic_vector ( 1 to ml );
VARIABLE rt : std_ulogic_vector ( 1 to ml );
VARIABLE res : std_ulogic_vector ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : std_logic_vector ) RETURN std_logic_vector IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : std_logic_vector ( 1 to ml );
VARIABLE rt : std_logic_vector ( 1 to ml );
VARIABLE res : std_logic_vector ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a xnor b);
RETURN (answer);
end "xnor";
END ;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_fifo_v1_0_4;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout, follower_reg_mm2s : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal follower_full_mm2s, follower_empty_mm2s : std_logic := '0';
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0, --req for proper fifo operation
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- I_UPDT_DATA_FIFO : entity proc_common_srl_fifo_v5_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 33 ,
-- C_DEPTH => 24 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => cntrlstrm_fifo_wren ,
-- Data_In => cntrlstrm_fifo_din ,
-- FIFO_Read => cntrl_fifo_rden ,
-- Data_Out => cntrl_fifo_dout ,
-- FIFO_Empty => cntrl_fifo_empty ,
-- FIFO_Full => cntrlstrm_fifo_full,
-- Addr => open
-- );
cntrl_fifo_rden <= follower_empty_mm2s and (not cntrl_fifo_empty);
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (cntrl_tready = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (cntrl_fifo_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (cntrl_fifo_rden = '1') then
follower_reg_mm2s <= cntrl_fifo_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
-- cntrl_fifo_rden <= not cntrl_fifo_empty
-- and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= follower_full_mm2s --not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
-- CNTRL_SKID_BUF_I : entity axi_sg_v4_1_2.axi_sg_skid_buf
-- generic map(
-- C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
-- )
-- port map(
-- -- System Ports
-- ACLK => m_axi_sg_aclk ,
-- ARST => skid_rst ,
-- skid_stop => mm2s_stop_re ,
-- -- Slave Side (Stream Data Input)
-- S_VALID => cntrl_tvalid ,
-- S_READY => cntrl_tready ,
-- S_Data => cntrl_tdata ,
-- S_STRB => cntrl_tkeep ,
-- S_Last => cntrl_tlast ,
-- -- Master Side (Stream Data Output
-- M_VALID => m_axis_mm2s_cntrl_tvalid ,
-- M_READY => m_axis_mm2s_cntrl_tready ,
-- M_Data => m_axis_mm2s_cntrl_tdata ,
-- M_STRB => m_axis_mm2s_cntrl_tkeep ,
-- M_Last => m_axis_mm2s_cntrl_tlast
-- );
m_axis_mm2s_cntrl_tvalid <= cntrl_tvalid;
cntrl_tready <= m_axis_mm2s_cntrl_tready;
m_axis_mm2s_cntrl_tdata <= cntrl_tdata;
m_axis_mm2s_cntrl_tkeep <= cntrl_tkeep;
m_axis_mm2s_cntrl_tlast <= cntrl_tlast;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1_cdc_tig : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
-- ATTRIBUTE async_reg OF p_mm2s_stop_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF p_mm2s_stop_d2 : SIGNAL IS "true";
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_sg_v4_1_2.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
C_DEPTH => CNTRL_FIFO_DEPTH-1 ,
C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
-- C_DEPTH => 31 ,
-- C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
-- cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
-- or (xfer_in_progress and p_mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
IMP_SYNC_FLOP : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_mm2s_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_mm2s_stop_d1_cdc_tig <= '0';
-- p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1_cdc_tig <= mm2s_stop;
-- p_mm2s_stop_d1_cdc_tig <= mm2s_stop_reg;
-- p_mm2s_stop_d2 <= p_mm2s_stop_d1_cdc_tig;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
CNTRL_SKID_BUF_I : entity axi_sg_v4_1_2.axi_sg_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_fifo_v1_0_4;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout, follower_reg_mm2s : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal follower_full_mm2s, follower_empty_mm2s : std_logic := '0';
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0, --req for proper fifo operation
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- I_UPDT_DATA_FIFO : entity proc_common_srl_fifo_v5_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 33 ,
-- C_DEPTH => 24 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => cntrlstrm_fifo_wren ,
-- Data_In => cntrlstrm_fifo_din ,
-- FIFO_Read => cntrl_fifo_rden ,
-- Data_Out => cntrl_fifo_dout ,
-- FIFO_Empty => cntrl_fifo_empty ,
-- FIFO_Full => cntrlstrm_fifo_full,
-- Addr => open
-- );
cntrl_fifo_rden <= follower_empty_mm2s and (not cntrl_fifo_empty);
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (cntrl_tready = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (cntrl_fifo_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (cntrl_fifo_rden = '1') then
follower_reg_mm2s <= cntrl_fifo_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
-- cntrl_fifo_rden <= not cntrl_fifo_empty
-- and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= follower_full_mm2s --not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
-- CNTRL_SKID_BUF_I : entity axi_sg_v4_1_2.axi_sg_skid_buf
-- generic map(
-- C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
-- )
-- port map(
-- -- System Ports
-- ACLK => m_axi_sg_aclk ,
-- ARST => skid_rst ,
-- skid_stop => mm2s_stop_re ,
-- -- Slave Side (Stream Data Input)
-- S_VALID => cntrl_tvalid ,
-- S_READY => cntrl_tready ,
-- S_Data => cntrl_tdata ,
-- S_STRB => cntrl_tkeep ,
-- S_Last => cntrl_tlast ,
-- -- Master Side (Stream Data Output
-- M_VALID => m_axis_mm2s_cntrl_tvalid ,
-- M_READY => m_axis_mm2s_cntrl_tready ,
-- M_Data => m_axis_mm2s_cntrl_tdata ,
-- M_STRB => m_axis_mm2s_cntrl_tkeep ,
-- M_Last => m_axis_mm2s_cntrl_tlast
-- );
m_axis_mm2s_cntrl_tvalid <= cntrl_tvalid;
cntrl_tready <= m_axis_mm2s_cntrl_tready;
m_axis_mm2s_cntrl_tdata <= cntrl_tdata;
m_axis_mm2s_cntrl_tkeep <= cntrl_tkeep;
m_axis_mm2s_cntrl_tlast <= cntrl_tlast;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1_cdc_tig : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
-- ATTRIBUTE async_reg OF p_mm2s_stop_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF p_mm2s_stop_d2 : SIGNAL IS "true";
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_sg_v4_1_2.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
C_DEPTH => CNTRL_FIFO_DEPTH-1 ,
C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
-- C_DEPTH => 31 ,
-- C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
-- cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
-- or (xfer_in_progress and p_mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
IMP_SYNC_FLOP : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_mm2s_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_mm2s_stop_d1_cdc_tig <= '0';
-- p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1_cdc_tig <= mm2s_stop;
-- p_mm2s_stop_d1_cdc_tig <= mm2s_stop_reg;
-- p_mm2s_stop_d2 <= p_mm2s_stop_d1_cdc_tig;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
CNTRL_SKID_BUF_I : entity axi_sg_v4_1_2.axi_sg_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_fifo_v1_0_4;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout, follower_reg_mm2s : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal follower_full_mm2s, follower_empty_mm2s : std_logic := '0';
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0, --req for proper fifo operation
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- I_UPDT_DATA_FIFO : entity proc_common_srl_fifo_v5_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 33 ,
-- C_DEPTH => 24 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => cntrlstrm_fifo_wren ,
-- Data_In => cntrlstrm_fifo_din ,
-- FIFO_Read => cntrl_fifo_rden ,
-- Data_Out => cntrl_fifo_dout ,
-- FIFO_Empty => cntrl_fifo_empty ,
-- FIFO_Full => cntrlstrm_fifo_full,
-- Addr => open
-- );
cntrl_fifo_rden <= follower_empty_mm2s and (not cntrl_fifo_empty);
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (cntrl_tready = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (cntrl_fifo_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (cntrl_fifo_rden = '1') then
follower_reg_mm2s <= cntrl_fifo_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
-- cntrl_fifo_rden <= not cntrl_fifo_empty
-- and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= follower_full_mm2s --not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
-- CNTRL_SKID_BUF_I : entity axi_sg_v4_1_2.axi_sg_skid_buf
-- generic map(
-- C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
-- )
-- port map(
-- -- System Ports
-- ACLK => m_axi_sg_aclk ,
-- ARST => skid_rst ,
-- skid_stop => mm2s_stop_re ,
-- -- Slave Side (Stream Data Input)
-- S_VALID => cntrl_tvalid ,
-- S_READY => cntrl_tready ,
-- S_Data => cntrl_tdata ,
-- S_STRB => cntrl_tkeep ,
-- S_Last => cntrl_tlast ,
-- -- Master Side (Stream Data Output
-- M_VALID => m_axis_mm2s_cntrl_tvalid ,
-- M_READY => m_axis_mm2s_cntrl_tready ,
-- M_Data => m_axis_mm2s_cntrl_tdata ,
-- M_STRB => m_axis_mm2s_cntrl_tkeep ,
-- M_Last => m_axis_mm2s_cntrl_tlast
-- );
m_axis_mm2s_cntrl_tvalid <= cntrl_tvalid;
cntrl_tready <= m_axis_mm2s_cntrl_tready;
m_axis_mm2s_cntrl_tdata <= cntrl_tdata;
m_axis_mm2s_cntrl_tkeep <= cntrl_tkeep;
m_axis_mm2s_cntrl_tlast <= cntrl_tlast;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1_cdc_tig : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
-- ATTRIBUTE async_reg OF p_mm2s_stop_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF p_mm2s_stop_d2 : SIGNAL IS "true";
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_sg_v4_1_2.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
C_DEPTH => CNTRL_FIFO_DEPTH-1 ,
C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
-- C_DEPTH => 31 ,
-- C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
-- cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
-- or (xfer_in_progress and p_mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
IMP_SYNC_FLOP : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_mm2s_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_mm2s_stop_d1_cdc_tig <= '0';
-- p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1_cdc_tig <= mm2s_stop;
-- p_mm2s_stop_d1_cdc_tig <= mm2s_stop_reg;
-- p_mm2s_stop_d2 <= p_mm2s_stop_d1_cdc_tig;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
CNTRL_SKID_BUF_I : entity axi_sg_v4_1_2.axi_sg_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_fifo_v1_0_4;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout, follower_reg_mm2s : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal follower_full_mm2s, follower_empty_mm2s : std_logic := '0';
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0, --req for proper fifo operation
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- I_UPDT_DATA_FIFO : entity proc_common_srl_fifo_v5_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 33 ,
-- C_DEPTH => 24 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => cntrlstrm_fifo_wren ,
-- Data_In => cntrlstrm_fifo_din ,
-- FIFO_Read => cntrl_fifo_rden ,
-- Data_Out => cntrl_fifo_dout ,
-- FIFO_Empty => cntrl_fifo_empty ,
-- FIFO_Full => cntrlstrm_fifo_full,
-- Addr => open
-- );
cntrl_fifo_rden <= follower_empty_mm2s and (not cntrl_fifo_empty);
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (cntrl_tready = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (cntrl_fifo_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (cntrl_fifo_rden = '1') then
follower_reg_mm2s <= cntrl_fifo_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
-- cntrl_fifo_rden <= not cntrl_fifo_empty
-- and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= follower_full_mm2s --not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
-- CNTRL_SKID_BUF_I : entity axi_sg_v4_1_2.axi_sg_skid_buf
-- generic map(
-- C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
-- )
-- port map(
-- -- System Ports
-- ACLK => m_axi_sg_aclk ,
-- ARST => skid_rst ,
-- skid_stop => mm2s_stop_re ,
-- -- Slave Side (Stream Data Input)
-- S_VALID => cntrl_tvalid ,
-- S_READY => cntrl_tready ,
-- S_Data => cntrl_tdata ,
-- S_STRB => cntrl_tkeep ,
-- S_Last => cntrl_tlast ,
-- -- Master Side (Stream Data Output
-- M_VALID => m_axis_mm2s_cntrl_tvalid ,
-- M_READY => m_axis_mm2s_cntrl_tready ,
-- M_Data => m_axis_mm2s_cntrl_tdata ,
-- M_STRB => m_axis_mm2s_cntrl_tkeep ,
-- M_Last => m_axis_mm2s_cntrl_tlast
-- );
m_axis_mm2s_cntrl_tvalid <= cntrl_tvalid;
cntrl_tready <= m_axis_mm2s_cntrl_tready;
m_axis_mm2s_cntrl_tdata <= cntrl_tdata;
m_axis_mm2s_cntrl_tkeep <= cntrl_tkeep;
m_axis_mm2s_cntrl_tlast <= cntrl_tlast;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1_cdc_tig : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
-- ATTRIBUTE async_reg OF p_mm2s_stop_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF p_mm2s_stop_d2 : SIGNAL IS "true";
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_sg_v4_1_2.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
C_DEPTH => CNTRL_FIFO_DEPTH-1 ,
C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
-- C_DEPTH => 31 ,
-- C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
-- cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
-- or (xfer_in_progress and p_mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
IMP_SYNC_FLOP : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_mm2s_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_mm2s_stop_d1_cdc_tig <= '0';
-- p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1_cdc_tig <= mm2s_stop;
-- p_mm2s_stop_d1_cdc_tig <= mm2s_stop_reg;
-- p_mm2s_stop_d2 <= p_mm2s_stop_d1_cdc_tig;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
CNTRL_SKID_BUF_I : entity axi_sg_v4_1_2.axi_sg_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_fifo_v1_0_4;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout, follower_reg_mm2s : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal follower_full_mm2s, follower_empty_mm2s : std_logic := '0';
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0, --req for proper fifo operation
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- I_UPDT_DATA_FIFO : entity proc_common_srl_fifo_v5_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 33 ,
-- C_DEPTH => 24 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => cntrlstrm_fifo_wren ,
-- Data_In => cntrlstrm_fifo_din ,
-- FIFO_Read => cntrl_fifo_rden ,
-- Data_Out => cntrl_fifo_dout ,
-- FIFO_Empty => cntrl_fifo_empty ,
-- FIFO_Full => cntrlstrm_fifo_full,
-- Addr => open
-- );
cntrl_fifo_rden <= follower_empty_mm2s and (not cntrl_fifo_empty);
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (cntrl_tready = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (cntrl_fifo_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (cntrl_fifo_rden = '1') then
follower_reg_mm2s <= cntrl_fifo_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
-- cntrl_fifo_rden <= not cntrl_fifo_empty
-- and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= follower_full_mm2s --not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
-- CNTRL_SKID_BUF_I : entity axi_sg_v4_1_2.axi_sg_skid_buf
-- generic map(
-- C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
-- )
-- port map(
-- -- System Ports
-- ACLK => m_axi_sg_aclk ,
-- ARST => skid_rst ,
-- skid_stop => mm2s_stop_re ,
-- -- Slave Side (Stream Data Input)
-- S_VALID => cntrl_tvalid ,
-- S_READY => cntrl_tready ,
-- S_Data => cntrl_tdata ,
-- S_STRB => cntrl_tkeep ,
-- S_Last => cntrl_tlast ,
-- -- Master Side (Stream Data Output
-- M_VALID => m_axis_mm2s_cntrl_tvalid ,
-- M_READY => m_axis_mm2s_cntrl_tready ,
-- M_Data => m_axis_mm2s_cntrl_tdata ,
-- M_STRB => m_axis_mm2s_cntrl_tkeep ,
-- M_Last => m_axis_mm2s_cntrl_tlast
-- );
m_axis_mm2s_cntrl_tvalid <= cntrl_tvalid;
cntrl_tready <= m_axis_mm2s_cntrl_tready;
m_axis_mm2s_cntrl_tdata <= cntrl_tdata;
m_axis_mm2s_cntrl_tkeep <= cntrl_tkeep;
m_axis_mm2s_cntrl_tlast <= cntrl_tlast;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1_cdc_tig : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
-- ATTRIBUTE async_reg OF p_mm2s_stop_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF p_mm2s_stop_d2 : SIGNAL IS "true";
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_sg_v4_1_2.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
C_DEPTH => CNTRL_FIFO_DEPTH-1 ,
C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
-- C_DEPTH => 31 ,
-- C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
-- cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
-- or (xfer_in_progress and p_mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
IMP_SYNC_FLOP : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_mm2s_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_mm2s_stop_d1_cdc_tig <= '0';
-- p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1_cdc_tig <= mm2s_stop;
-- p_mm2s_stop_d1_cdc_tig <= mm2s_stop_reg;
-- p_mm2s_stop_d2 <= p_mm2s_stop_d1_cdc_tig;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
CNTRL_SKID_BUF_I : entity axi_sg_v4_1_2.axi_sg_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_fifo_v1_0_4;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout, follower_reg_mm2s : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal follower_full_mm2s, follower_empty_mm2s : std_logic := '0';
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0, --req for proper fifo operation
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- I_UPDT_DATA_FIFO : entity proc_common_srl_fifo_v5_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 33 ,
-- C_DEPTH => 24 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => cntrlstrm_fifo_wren ,
-- Data_In => cntrlstrm_fifo_din ,
-- FIFO_Read => cntrl_fifo_rden ,
-- Data_Out => cntrl_fifo_dout ,
-- FIFO_Empty => cntrl_fifo_empty ,
-- FIFO_Full => cntrlstrm_fifo_full,
-- Addr => open
-- );
cntrl_fifo_rden <= follower_empty_mm2s and (not cntrl_fifo_empty);
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (cntrl_tready = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (cntrl_fifo_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (cntrl_fifo_rden = '1') then
follower_reg_mm2s <= cntrl_fifo_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
-- cntrl_fifo_rden <= not cntrl_fifo_empty
-- and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= follower_full_mm2s --not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
-- CNTRL_SKID_BUF_I : entity axi_sg_v4_1_2.axi_sg_skid_buf
-- generic map(
-- C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
-- )
-- port map(
-- -- System Ports
-- ACLK => m_axi_sg_aclk ,
-- ARST => skid_rst ,
-- skid_stop => mm2s_stop_re ,
-- -- Slave Side (Stream Data Input)
-- S_VALID => cntrl_tvalid ,
-- S_READY => cntrl_tready ,
-- S_Data => cntrl_tdata ,
-- S_STRB => cntrl_tkeep ,
-- S_Last => cntrl_tlast ,
-- -- Master Side (Stream Data Output
-- M_VALID => m_axis_mm2s_cntrl_tvalid ,
-- M_READY => m_axis_mm2s_cntrl_tready ,
-- M_Data => m_axis_mm2s_cntrl_tdata ,
-- M_STRB => m_axis_mm2s_cntrl_tkeep ,
-- M_Last => m_axis_mm2s_cntrl_tlast
-- );
m_axis_mm2s_cntrl_tvalid <= cntrl_tvalid;
cntrl_tready <= m_axis_mm2s_cntrl_tready;
m_axis_mm2s_cntrl_tdata <= cntrl_tdata;
m_axis_mm2s_cntrl_tkeep <= cntrl_tkeep;
m_axis_mm2s_cntrl_tlast <= cntrl_tlast;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1_cdc_tig : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
-- ATTRIBUTE async_reg OF p_mm2s_stop_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF p_mm2s_stop_d2 : SIGNAL IS "true";
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_sg_v4_1_2.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
C_DEPTH => CNTRL_FIFO_DEPTH-1 ,
C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
-- C_DEPTH => 31 ,
-- C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
-- cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
-- or (xfer_in_progress and p_mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
IMP_SYNC_FLOP : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_mm2s_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_mm2s_stop_d1_cdc_tig <= '0';
-- p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1_cdc_tig <= mm2s_stop;
-- p_mm2s_stop_d1_cdc_tig <= mm2s_stop_reg;
-- p_mm2s_stop_d2 <= p_mm2s_stop_d1_cdc_tig;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
CNTRL_SKID_BUF_I : entity axi_sg_v4_1_2.axi_sg_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_fifo_v1_0_4;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout, follower_reg_mm2s : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal follower_full_mm2s, follower_empty_mm2s : std_logic := '0';
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0, --req for proper fifo operation
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- I_UPDT_DATA_FIFO : entity proc_common_srl_fifo_v5_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 33 ,
-- C_DEPTH => 24 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => cntrlstrm_fifo_wren ,
-- Data_In => cntrlstrm_fifo_din ,
-- FIFO_Read => cntrl_fifo_rden ,
-- Data_Out => cntrl_fifo_dout ,
-- FIFO_Empty => cntrl_fifo_empty ,
-- FIFO_Full => cntrlstrm_fifo_full,
-- Addr => open
-- );
cntrl_fifo_rden <= follower_empty_mm2s and (not cntrl_fifo_empty);
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (cntrl_tready = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (cntrl_fifo_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (cntrl_fifo_rden = '1') then
follower_reg_mm2s <= cntrl_fifo_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
-- cntrl_fifo_rden <= not cntrl_fifo_empty
-- and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= follower_full_mm2s --not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
-- CNTRL_SKID_BUF_I : entity axi_sg_v4_1_2.axi_sg_skid_buf
-- generic map(
-- C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
-- )
-- port map(
-- -- System Ports
-- ACLK => m_axi_sg_aclk ,
-- ARST => skid_rst ,
-- skid_stop => mm2s_stop_re ,
-- -- Slave Side (Stream Data Input)
-- S_VALID => cntrl_tvalid ,
-- S_READY => cntrl_tready ,
-- S_Data => cntrl_tdata ,
-- S_STRB => cntrl_tkeep ,
-- S_Last => cntrl_tlast ,
-- -- Master Side (Stream Data Output
-- M_VALID => m_axis_mm2s_cntrl_tvalid ,
-- M_READY => m_axis_mm2s_cntrl_tready ,
-- M_Data => m_axis_mm2s_cntrl_tdata ,
-- M_STRB => m_axis_mm2s_cntrl_tkeep ,
-- M_Last => m_axis_mm2s_cntrl_tlast
-- );
m_axis_mm2s_cntrl_tvalid <= cntrl_tvalid;
cntrl_tready <= m_axis_mm2s_cntrl_tready;
m_axis_mm2s_cntrl_tdata <= cntrl_tdata;
m_axis_mm2s_cntrl_tkeep <= cntrl_tkeep;
m_axis_mm2s_cntrl_tlast <= cntrl_tlast;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1_cdc_tig : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
-- ATTRIBUTE async_reg OF p_mm2s_stop_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF p_mm2s_stop_d2 : SIGNAL IS "true";
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_sg_v4_1_2.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
C_DEPTH => CNTRL_FIFO_DEPTH-1 ,
C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
-- C_DEPTH => 31 ,
-- C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
-- cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
-- or (xfer_in_progress and p_mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
IMP_SYNC_FLOP : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_mm2s_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_mm2s_stop_d1_cdc_tig <= '0';
-- p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1_cdc_tig <= mm2s_stop;
-- p_mm2s_stop_d1_cdc_tig <= mm2s_stop_reg;
-- p_mm2s_stop_d2 <= p_mm2s_stop_d1_cdc_tig;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
CNTRL_SKID_BUF_I : entity axi_sg_v4_1_2.axi_sg_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: e.kyriakakis:user:internoc_ni_axi_master:1.0
-- IP Revision: 18
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_internoc_ni_axi_master_1_0 IS
PORT (
if00_data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_in : IN STD_LOGIC;
if00_data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_out : OUT STD_LOGIC;
if00_send_done : IN STD_LOGIC;
if00_send_busy : IN STD_LOGIC;
m00_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_awvalid : OUT STD_LOGIC;
m00_axi_awready : IN STD_LOGIC;
m00_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m00_axi_wvalid : OUT STD_LOGIC;
m00_axi_wready : IN STD_LOGIC;
m00_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_bvalid : IN STD_LOGIC;
m00_axi_bready : OUT STD_LOGIC;
m00_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_arvalid : OUT STD_LOGIC;
m00_axi_arready : IN STD_LOGIC;
m00_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_rvalid : IN STD_LOGIC;
m00_axi_rready : OUT STD_LOGIC;
m00_axi_aclk : IN STD_LOGIC;
m00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_internoc_ni_axi_master_1_0;
ARCHITECTURE DemoInterconnect_internoc_ni_axi_master_1_0_arch OF DemoInterconnect_internoc_ni_axi_master_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_internoc_ni_axi_master_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT internoc_ni_axi_master_v1_0 IS
GENERIC (
C_IF00_DATA_WIDTH : INTEGER;
C_PACKET_WIDTH : INTEGER;
C_PACKET_DATA_WIDTH : INTEGER;
C_PACKET_CTRL_WIDTH : INTEGER;
C_PACKET_ADDR_WIDTH : INTEGER;
C_AXI_PACKET_ADDR_OFFSET : INTEGER;
C_M00_AXI_ADDR_WIDTH : INTEGER;
C_M00_SELF_ADDR : INTEGER;
C_TIMEOUT_PERIOD : INTEGER
);
PORT (
if00_data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_in : IN STD_LOGIC;
if00_data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_out : OUT STD_LOGIC;
if00_send_done : IN STD_LOGIC;
if00_send_busy : IN STD_LOGIC;
m00_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_awvalid : OUT STD_LOGIC;
m00_axi_awready : IN STD_LOGIC;
m00_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m00_axi_wvalid : OUT STD_LOGIC;
m00_axi_wready : IN STD_LOGIC;
m00_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_bvalid : IN STD_LOGIC;
m00_axi_bready : OUT STD_LOGIC;
m00_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_arvalid : OUT STD_LOGIC;
m00_axi_arready : IN STD_LOGIC;
m00_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_rvalid : IN STD_LOGIC;
m00_axi_rready : OUT STD_LOGIC;
m00_axi_aclk : IN STD_LOGIC;
m00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT internoc_ni_axi_master_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME M00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME m00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M00_AXI_RST RST, xilinx.com:signal:reset:1.0 m00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME M00_AXI_CLK, ASSOCIATED_BUSIF M00_AXI, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME m00_axi_aclk, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF M00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 m00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME M00_AXI, WIZ_DATA_WIDTH 32, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR";
BEGIN
U0 : internoc_ni_axi_master_v1_0
GENERIC MAP (
C_IF00_DATA_WIDTH => 8,
C_PACKET_WIDTH => 40,
C_PACKET_DATA_WIDTH => 32,
C_PACKET_CTRL_WIDTH => 3,
C_PACKET_ADDR_WIDTH => 5,
C_AXI_PACKET_ADDR_OFFSET => 16,
C_M00_AXI_ADDR_WIDTH => 32,
C_M00_SELF_ADDR => 16,
C_TIMEOUT_PERIOD => 16383
)
PORT MAP (
if00_data_in => if00_data_in,
if00_load_in => if00_load_in,
if00_data_out => if00_data_out,
if00_load_out => if00_load_out,
if00_send_done => if00_send_done,
if00_send_busy => if00_send_busy,
m00_axi_awaddr => m00_axi_awaddr,
m00_axi_awprot => m00_axi_awprot,
m00_axi_awvalid => m00_axi_awvalid,
m00_axi_awready => m00_axi_awready,
m00_axi_wdata => m00_axi_wdata,
m00_axi_wstrb => m00_axi_wstrb,
m00_axi_wvalid => m00_axi_wvalid,
m00_axi_wready => m00_axi_wready,
m00_axi_bresp => m00_axi_bresp,
m00_axi_bvalid => m00_axi_bvalid,
m00_axi_bready => m00_axi_bready,
m00_axi_araddr => m00_axi_araddr,
m00_axi_arprot => m00_axi_arprot,
m00_axi_arvalid => m00_axi_arvalid,
m00_axi_arready => m00_axi_arready,
m00_axi_rdata => m00_axi_rdata,
m00_axi_rresp => m00_axi_rresp,
m00_axi_rvalid => m00_axi_rvalid,
m00_axi_rready => m00_axi_rready,
m00_axi_aclk => m00_axi_aclk,
m00_axi_aresetn => m00_axi_aresetn
);
END DemoInterconnect_internoc_ni_axi_master_1_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: e.kyriakakis:user:internoc_ni_axi_master:1.0
-- IP Revision: 18
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_internoc_ni_axi_master_1_0 IS
PORT (
if00_data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_in : IN STD_LOGIC;
if00_data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_out : OUT STD_LOGIC;
if00_send_done : IN STD_LOGIC;
if00_send_busy : IN STD_LOGIC;
m00_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_awvalid : OUT STD_LOGIC;
m00_axi_awready : IN STD_LOGIC;
m00_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m00_axi_wvalid : OUT STD_LOGIC;
m00_axi_wready : IN STD_LOGIC;
m00_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_bvalid : IN STD_LOGIC;
m00_axi_bready : OUT STD_LOGIC;
m00_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_arvalid : OUT STD_LOGIC;
m00_axi_arready : IN STD_LOGIC;
m00_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_rvalid : IN STD_LOGIC;
m00_axi_rready : OUT STD_LOGIC;
m00_axi_aclk : IN STD_LOGIC;
m00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_internoc_ni_axi_master_1_0;
ARCHITECTURE DemoInterconnect_internoc_ni_axi_master_1_0_arch OF DemoInterconnect_internoc_ni_axi_master_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_internoc_ni_axi_master_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT internoc_ni_axi_master_v1_0 IS
GENERIC (
C_IF00_DATA_WIDTH : INTEGER;
C_PACKET_WIDTH : INTEGER;
C_PACKET_DATA_WIDTH : INTEGER;
C_PACKET_CTRL_WIDTH : INTEGER;
C_PACKET_ADDR_WIDTH : INTEGER;
C_AXI_PACKET_ADDR_OFFSET : INTEGER;
C_M00_AXI_ADDR_WIDTH : INTEGER;
C_M00_SELF_ADDR : INTEGER;
C_TIMEOUT_PERIOD : INTEGER
);
PORT (
if00_data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_in : IN STD_LOGIC;
if00_data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_out : OUT STD_LOGIC;
if00_send_done : IN STD_LOGIC;
if00_send_busy : IN STD_LOGIC;
m00_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_awvalid : OUT STD_LOGIC;
m00_axi_awready : IN STD_LOGIC;
m00_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m00_axi_wvalid : OUT STD_LOGIC;
m00_axi_wready : IN STD_LOGIC;
m00_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_bvalid : IN STD_LOGIC;
m00_axi_bready : OUT STD_LOGIC;
m00_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_arvalid : OUT STD_LOGIC;
m00_axi_arready : IN STD_LOGIC;
m00_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_rvalid : IN STD_LOGIC;
m00_axi_rready : OUT STD_LOGIC;
m00_axi_aclk : IN STD_LOGIC;
m00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT internoc_ni_axi_master_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME M00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME m00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M00_AXI_RST RST, xilinx.com:signal:reset:1.0 m00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME M00_AXI_CLK, ASSOCIATED_BUSIF M00_AXI, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME m00_axi_aclk, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF M00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 m00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME M00_AXI, WIZ_DATA_WIDTH 32, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR";
BEGIN
U0 : internoc_ni_axi_master_v1_0
GENERIC MAP (
C_IF00_DATA_WIDTH => 8,
C_PACKET_WIDTH => 40,
C_PACKET_DATA_WIDTH => 32,
C_PACKET_CTRL_WIDTH => 3,
C_PACKET_ADDR_WIDTH => 5,
C_AXI_PACKET_ADDR_OFFSET => 16,
C_M00_AXI_ADDR_WIDTH => 32,
C_M00_SELF_ADDR => 16,
C_TIMEOUT_PERIOD => 16383
)
PORT MAP (
if00_data_in => if00_data_in,
if00_load_in => if00_load_in,
if00_data_out => if00_data_out,
if00_load_out => if00_load_out,
if00_send_done => if00_send_done,
if00_send_busy => if00_send_busy,
m00_axi_awaddr => m00_axi_awaddr,
m00_axi_awprot => m00_axi_awprot,
m00_axi_awvalid => m00_axi_awvalid,
m00_axi_awready => m00_axi_awready,
m00_axi_wdata => m00_axi_wdata,
m00_axi_wstrb => m00_axi_wstrb,
m00_axi_wvalid => m00_axi_wvalid,
m00_axi_wready => m00_axi_wready,
m00_axi_bresp => m00_axi_bresp,
m00_axi_bvalid => m00_axi_bvalid,
m00_axi_bready => m00_axi_bready,
m00_axi_araddr => m00_axi_araddr,
m00_axi_arprot => m00_axi_arprot,
m00_axi_arvalid => m00_axi_arvalid,
m00_axi_arready => m00_axi_arready,
m00_axi_rdata => m00_axi_rdata,
m00_axi_rresp => m00_axi_rresp,
m00_axi_rvalid => m00_axi_rvalid,
m00_axi_rready => m00_axi_rready,
m00_axi_aclk => m00_axi_aclk,
m00_axi_aresetn => m00_axi_aresetn
);
END DemoInterconnect_internoc_ni_axi_master_1_0_arch;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity cse_jed is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end cse_jed;
architecture behaviour of cse_jed is
constant st0: std_logic_vector(3 downto 0) := "0100";
constant st1: std_logic_vector(3 downto 0) := "0110";
constant st9: std_logic_vector(3 downto 0) := "1110";
constant st6: std_logic_vector(3 downto 0) := "0101";
constant st8: std_logic_vector(3 downto 0) := "0001";
constant st2: std_logic_vector(3 downto 0) := "0011";
constant st5: std_logic_vector(3 downto 0) := "1100";
constant st3: std_logic_vector(3 downto 0) := "1101";
constant st4: std_logic_vector(3 downto 0) := "1111";
constant st7: std_logic_vector(3 downto 0) := "0111";
constant st10: std_logic_vector(3 downto 0) := "1001";
constant st11: std_logic_vector(3 downto 0) := "1010";
constant st12: std_logic_vector(3 downto 0) := "1011";
constant st13: std_logic_vector(3 downto 0) := "0000";
constant st14: std_logic_vector(3 downto 0) := "1000";
constant st15: std_logic_vector(3 downto 0) := "0010";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when st0 =>
if std_match(input, "1-000--") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "1-11---") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "1-1-1--") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st1; output <= "1100-10";
elsif std_match(input, "10011--") then next_state <= st9; output <= "0010001";
elsif std_match(input, "10001--") then next_state <= st6; output <= "0000-01";
elsif std_match(input, "10100--") then next_state <= st8; output <= "0000--0";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st1 =>
if std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st1; output <= "0100-00";
elsif std_match(input, "1000---") then next_state <= st2; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-10";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-10";
end if;
when st2 =>
if std_match(input, "10010--") then next_state <= st1; output <= "1100-00";
elsif std_match(input, "10011--") then next_state <= st5; output <= "0001000";
elsif std_match(input, "10000--") then next_state <= st2; output <= "0000-00";
elsif std_match(input, "10001--") then next_state <= st3; output <= "1000-00";
elsif std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0-----0") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0-----1") then next_state <= st0; output <= "0000-10";
elsif std_match(input, "-1----0") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "0000-10";
end if;
when st3 =>
if std_match(input, "10001--") then next_state <= st3; output <= "0000-00";
elsif std_match(input, "100-0--") then next_state <= st4; output <= "0000-00";
elsif std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-10";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-10";
end if;
when st4 =>
if std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st1; output <= "1100-00";
elsif std_match(input, "1000---") then next_state <= st4; output <= "0000-00";
elsif std_match(input, "10011--") then next_state <= st5; output <= "0001000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st5 =>
if std_match(input, "10-1---") then next_state <= st5; output <= "0000-00";
elsif std_match(input, "10-0---") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
end if;
when st6 =>
if std_match(input, "10--1--") then next_state <= st6; output <= "0000-00";
elsif std_match(input, "101----") then next_state <= st6; output <= "0000-00";
elsif std_match(input, "100-0--") then next_state <= st7; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st7 =>
if std_match(input, "100--0-") then next_state <= st7; output <= "0000-00";
elsif std_match(input, "101--0-") then next_state <= st6; output <= "0000-01";
elsif std_match(input, "10---1-") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st8 =>
if std_match(input, "10-00--") then next_state <= st8; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st9; output <= "0010101";
elsif std_match(input, "10-01--") then next_state <= st10; output <= "0000-10";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st9 =>
if std_match(input, "10-1---") then next_state <= st9; output <= "0000000";
elsif std_match(input, "10-0---") then next_state <= st7; output <= "0000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
end if;
when st10 =>
if std_match(input, "10-0---") then next_state <= st10; output <= "0000-00";
elsif std_match(input, "10-10--") then next_state <= st11; output <= "0000100";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st11 =>
if std_match(input, "10-10--") then next_state <= st11; output <= "0000000";
elsif std_match(input, "10-0---") then next_state <= st12; output <= "0000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st12 =>
if std_match(input, "10-0---") then next_state <= st12; output <= "0000000";
elsif std_match(input, "10-10--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st13 =>
if std_match(input, "10-10--") then next_state <= st13; output <= "0000000";
elsif std_match(input, "10-01--") then next_state <= st13; output <= "0000000";
elsif std_match(input, "10100--") then next_state <= st14; output <= "0000000";
elsif std_match(input, "10000--") then next_state <= st15; output <= "0000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
end if;
when st14 =>
if std_match(input, "--111--") then next_state <= st14; output <= "0000000";
elsif std_match(input, "--100--") then next_state <= st14; output <= "0000000";
elsif std_match(input, "--110--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "--101--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "--0----") then next_state <= st0; output <= "0001000";
end if;
when st15 =>
if std_match(input, "10000--") then next_state <= st15; output <= "0000000";
elsif std_match(input, "10010--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "10001--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "101----") then next_state <= st8; output <= "0001000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0001000";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0001000";
elsif std_match(input, "10011--") then next_state <= st0; output <= "0001000";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Enhanced simple dual-port memory.
--
-- Description:
-- ------------------------------------
-- Inferring / instantiating enhanced simple dual-port memory, with:
--
-- * dual clock, clock enable,
-- * 1 read/write port (1st port) plus 1 read port (2nd port).
--
-- The generalized behavior across Altera and Xilinx FPGAs since
-- Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:
--
-- * Same-Port Read-During Write:
-- At rising edge of "clk1", data "d1" written to port 1 (ce1 and we1 = '1')
-- is directly passed to the output "q1". This is also known as write-first
-- mode or read-through write behavior.
--
-- * Mixed-Port Read-During Write:
-- Here, the Altera M512/M4K TriMatrix memory (as found e.g. in Stratix
-- and Stratix II FPGAs) defines the minimum time after which the written data
-- at port 1 can be read-out at port 2 again. As stated in the Stratix
-- Handbook, Volume 2, page 2-13, data is actually written with the falling
-- (instead of the rising) edge of the clock into the memory array. The write
-- itself takes the write-cycle time which is less or equal to the minimum
-- clock-period time. After this, the data can be read-out at the other port.
-- Consequently, data "d1" written at the rising-edge of "clk1" at address
-- "a1" can be read-out at the 2nd port from the same address with the
-- 2nd rising-edge of "clk2" following the falling-edge of "clk1".
-- If the rising-edge of "clk2" coincides with the falling-edge of "clk1"
-- (e.g. same clock signal), then it is counted as the 1st rising-edge of
-- "clk2" in this timing.
--
-- WARNING: The simulated behavior on RT-level is not correct.
--
-- TODO: add timing diagram
-- TODO: implement correct behavior for RT-level simulation
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library STD;
use STD.TextIO.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
entity ocram_esdp is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk1 : in std_logic;
clk2 : in std_logic;
ce1 : in std_logic;
ce2 : in std_logic;
we1 : in std_logic;
a1 : in unsigned(A_BITS-1 downto 0);
a2 : in unsigned(A_BITS-1 downto 0);
d1 : in std_logic_vector(D_BITS-1 downto 0);
q1 : out std_logic_vector(D_BITS-1 downto 0);
q2 : out std_logic_vector(D_BITS-1 downto 0)
);
end ocram_esdp;
architecture rtl of ocram_esdp is
constant DEPTH : positive := 2**A_BITS;
begin
gInfer: if VENDOR = VENDOR_XILINX generate
-- RAM can be inferred correctly
-- XST Advanced HDL Synthesis generates extended simple dual-port
-- memory as expected.
-- RAM can be inferred correctly only for newer FPGAs!
subtype word_t is std_logic_vector(D_BITS - 1 downto 0);
type ram_t is array(0 to DEPTH - 1) of word_t;
begin
genLoadFile : if (str_length(FileName) /= 0) generate
-- Read a *.mem or *.hex file
impure function ocram_ReadMemFile(FileName : STRING) return ram_t is
file FileHandle : TEXT open READ_MODE is FileName;
variable CurrentLine : LINE;
variable TempWord : STD_LOGIC_VECTOR((div_ceil(word_t'length, 4) * 4) - 1 downto 0);
variable Result : ram_t := (others => (others => '0'));
begin
-- discard the first line of a mem file
if (str_toLower(FileName(FileName'length - 3 to FileName'length)) = ".mem") then
readline(FileHandle, CurrentLine);
end if;
for i in 0 to DEPTH - 1 loop
exit when endfile(FileHandle);
readline(FileHandle, CurrentLine);
hread(CurrentLine, TempWord);
Result(i) := resize(TempWord, word_t'length);
end loop;
return Result;
end function;
signal ram : ram_t := ocram_ReadMemFile(FILENAME);
signal a1_reg : unsigned(A_BITS-1 downto 0);
signal a2_reg : unsigned(A_BITS-1 downto 0);
begin
process (clk1)
begin
if rising_edge(clk1) then
if ce1 = '1' then
if we1 = '1' then
ram(to_integer(a1)) <= d1;
end if;
a1_reg <= a1;
end if;
end if;
end process;
q1 <= ram(to_integer(a1_reg)); -- gets new data
process (clk2)
begin -- process
if rising_edge(clk2) then
if ce2 = '1' then
a2_reg <= a2;
end if;
end if;
end process;
-- read data is unknown, when reading at write address
q2 <= ram(to_integer(a2_reg));
end generate;
genNoLoadFile : if (str_length(FileName) = 0) generate
signal ram : ram_t;
signal a1_reg : unsigned(A_BITS-1 downto 0);
signal a2_reg : unsigned(A_BITS-1 downto 0);
begin
process (clk1)
begin
if rising_edge(clk1) then
if ce1 = '1' then
if we1 = '1' then
ram(to_integer(a1)) <= d1;
end if;
a1_reg <= a1;
end if;
end if;
end process;
q1 <= ram(to_integer(a1_reg)); -- gets new data
process (clk2)
begin -- process
if rising_edge(clk2) then
if ce2 = '1' then
a2_reg <= a2;
end if;
end if;
end process;
-- read data is unknown, when reading at write address
q2 <= ram(to_integer(a2_reg));
end generate;
end generate gInfer;
gAltera: if VENDOR = VENDOR_ALTERA generate
component ocram_esdp_altera
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk1 : in std_logic;
clk2 : in std_logic;
ce1 : in std_logic;
ce2 : in std_logic;
we1 : in std_logic;
a1 : in unsigned(A_BITS-1 downto 0);
a2 : in unsigned(A_BITS-1 downto 0);
d1 : in std_logic_vector(D_BITS-1 downto 0);
q1 : out std_logic_vector(D_BITS-1 downto 0);
q2 : out std_logic_vector(D_BITS-1 downto 0)
);
end component;
begin
-- Direct instantiation of altsyncram (including component
-- declaration above) is not sufficient for ModelSim.
-- That requires also usage of altera_mf library.
i: ocram_esdp_altera
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS,
FILENAME => FILENAME
)
port map (
clk1 => clk1,
clk2 => clk2,
ce1 => ce1,
ce2 => ce2,
we1 => we1,
a1 => a1,
a2 => a2,
d1 => d1,
q1 => q1,
q2 => q2
);
end generate gAltera;
assert VENDOR = VENDOR_XILINX or VENDOR = VENDOR_ALTERA
report "Device not yet supported."
severity failure;
end rtl;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Enhanced simple dual-port memory.
--
-- Description:
-- ------------------------------------
-- Inferring / instantiating enhanced simple dual-port memory, with:
--
-- * dual clock, clock enable,
-- * 1 read/write port (1st port) plus 1 read port (2nd port).
--
-- The generalized behavior across Altera and Xilinx FPGAs since
-- Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:
--
-- * Same-Port Read-During Write:
-- At rising edge of "clk1", data "d1" written to port 1 (ce1 and we1 = '1')
-- is directly passed to the output "q1". This is also known as write-first
-- mode or read-through write behavior.
--
-- * Mixed-Port Read-During Write:
-- Here, the Altera M512/M4K TriMatrix memory (as found e.g. in Stratix
-- and Stratix II FPGAs) defines the minimum time after which the written data
-- at port 1 can be read-out at port 2 again. As stated in the Stratix
-- Handbook, Volume 2, page 2-13, data is actually written with the falling
-- (instead of the rising) edge of the clock into the memory array. The write
-- itself takes the write-cycle time which is less or equal to the minimum
-- clock-period time. After this, the data can be read-out at the other port.
-- Consequently, data "d1" written at the rising-edge of "clk1" at address
-- "a1" can be read-out at the 2nd port from the same address with the
-- 2nd rising-edge of "clk2" following the falling-edge of "clk1".
-- If the rising-edge of "clk2" coincides with the falling-edge of "clk1"
-- (e.g. same clock signal), then it is counted as the 1st rising-edge of
-- "clk2" in this timing.
--
-- WARNING: The simulated behavior on RT-level is not correct.
--
-- TODO: add timing diagram
-- TODO: implement correct behavior for RT-level simulation
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library STD;
use STD.TextIO.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
entity ocram_esdp is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk1 : in std_logic;
clk2 : in std_logic;
ce1 : in std_logic;
ce2 : in std_logic;
we1 : in std_logic;
a1 : in unsigned(A_BITS-1 downto 0);
a2 : in unsigned(A_BITS-1 downto 0);
d1 : in std_logic_vector(D_BITS-1 downto 0);
q1 : out std_logic_vector(D_BITS-1 downto 0);
q2 : out std_logic_vector(D_BITS-1 downto 0)
);
end ocram_esdp;
architecture rtl of ocram_esdp is
constant DEPTH : positive := 2**A_BITS;
begin
gInfer: if VENDOR = VENDOR_XILINX generate
-- RAM can be inferred correctly
-- XST Advanced HDL Synthesis generates extended simple dual-port
-- memory as expected.
-- RAM can be inferred correctly only for newer FPGAs!
subtype word_t is std_logic_vector(D_BITS - 1 downto 0);
type ram_t is array(0 to DEPTH - 1) of word_t;
begin
genLoadFile : if (str_length(FileName) /= 0) generate
-- Read a *.mem or *.hex file
impure function ocram_ReadMemFile(FileName : STRING) return ram_t is
file FileHandle : TEXT open READ_MODE is FileName;
variable CurrentLine : LINE;
variable TempWord : STD_LOGIC_VECTOR((div_ceil(word_t'length, 4) * 4) - 1 downto 0);
variable Result : ram_t := (others => (others => '0'));
begin
-- discard the first line of a mem file
if (str_toLower(FileName(FileName'length - 3 to FileName'length)) = ".mem") then
readline(FileHandle, CurrentLine);
end if;
for i in 0 to DEPTH - 1 loop
exit when endfile(FileHandle);
readline(FileHandle, CurrentLine);
hread(CurrentLine, TempWord);
Result(i) := resize(TempWord, word_t'length);
end loop;
return Result;
end function;
signal ram : ram_t := ocram_ReadMemFile(FILENAME);
signal a1_reg : unsigned(A_BITS-1 downto 0);
signal a2_reg : unsigned(A_BITS-1 downto 0);
begin
process (clk1)
begin
if rising_edge(clk1) then
if ce1 = '1' then
if we1 = '1' then
ram(to_integer(a1)) <= d1;
end if;
a1_reg <= a1;
end if;
end if;
end process;
q1 <= ram(to_integer(a1_reg)); -- gets new data
process (clk2)
begin -- process
if rising_edge(clk2) then
if ce2 = '1' then
a2_reg <= a2;
end if;
end if;
end process;
-- read data is unknown, when reading at write address
q2 <= ram(to_integer(a2_reg));
end generate;
genNoLoadFile : if (str_length(FileName) = 0) generate
signal ram : ram_t;
signal a1_reg : unsigned(A_BITS-1 downto 0);
signal a2_reg : unsigned(A_BITS-1 downto 0);
begin
process (clk1)
begin
if rising_edge(clk1) then
if ce1 = '1' then
if we1 = '1' then
ram(to_integer(a1)) <= d1;
end if;
a1_reg <= a1;
end if;
end if;
end process;
q1 <= ram(to_integer(a1_reg)); -- gets new data
process (clk2)
begin -- process
if rising_edge(clk2) then
if ce2 = '1' then
a2_reg <= a2;
end if;
end if;
end process;
-- read data is unknown, when reading at write address
q2 <= ram(to_integer(a2_reg));
end generate;
end generate gInfer;
gAltera: if VENDOR = VENDOR_ALTERA generate
component ocram_esdp_altera
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk1 : in std_logic;
clk2 : in std_logic;
ce1 : in std_logic;
ce2 : in std_logic;
we1 : in std_logic;
a1 : in unsigned(A_BITS-1 downto 0);
a2 : in unsigned(A_BITS-1 downto 0);
d1 : in std_logic_vector(D_BITS-1 downto 0);
q1 : out std_logic_vector(D_BITS-1 downto 0);
q2 : out std_logic_vector(D_BITS-1 downto 0)
);
end component;
begin
-- Direct instantiation of altsyncram (including component
-- declaration above) is not sufficient for ModelSim.
-- That requires also usage of altera_mf library.
i: ocram_esdp_altera
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS,
FILENAME => FILENAME
)
port map (
clk1 => clk1,
clk2 => clk2,
ce1 => ce1,
ce2 => ce2,
we1 => we1,
a1 => a1,
a2 => a2,
d1 => d1,
q1 => q1,
q2 => q2
);
end generate gAltera;
assert VENDOR = VENDOR_XILINX or VENDOR = VENDOR_ALTERA
report "Device not yet supported."
severity failure;
end rtl;
|
architecture a of e is
attribute foo : integer;
attribute foo of x : signal is 5;
attribute foo of x : component is 5;
attribute foo of x : label is 6;
attribute foo of x : type is 4;
begin
assert x'foo(5);
end architecture;
|
architecture a of e is
attribute foo : integer;
attribute foo of x : signal is 5;
attribute foo of x : component is 5;
attribute foo of x : label is 6;
attribute foo of x : type is 4;
begin
assert x'foo(5);
end architecture;
|
architecture a of e is
attribute foo : integer;
attribute foo of x : signal is 5;
attribute foo of x : component is 5;
attribute foo of x : label is 6;
attribute foo of x : type is 4;
begin
assert x'foo(5);
end architecture;
|
architecture a of e is
attribute foo : integer;
attribute foo of x : signal is 5;
attribute foo of x : component is 5;
attribute foo of x : label is 6;
attribute foo of x : type is 4;
begin
assert x'foo(5);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity fifo_control_unit is
port (
clkA : out std_logic;
clkB : out std_logic;
enA : out std_logic;
enB : out std_logic;
weA : out std_logic := '1';
--weB : out std_logic;
addrA : out std_logic_vector(11 downto 0);
addrB : out std_logic_vector(10 downto 0);
diA : out std_logic_vector(3 downto 0);
--diB : out std_logic_vector(7 downto 0);
--doA : out std_logic_vector(3 downto 0);
doB : in std_logic_vector(7 downto 0);
EOFenA : out std_logic;
EOFweA : out std_logic;
EOFenB : out std_logic;
addrEOFA : out std_logic_vector(13 downto 0);
addrEOFB : out std_logic_vector(12 downto 0);
diEOFA : out std_logic_vector(0 downto 0);
doEOFB : in std_logic_vector(1 downto 0);
empty : out std_logic := '1';
full : out std_logic := '0';
data_out : out std_logic_vector(7 downto 0);
EOF : out std_logic;
clk : in std_logic;
Rx_Clk : in std_logic;
Rx_DV : in std_logic;
Rx_D : in std_logic_vector(3 downto 0);
POP : in std_logic;
test : out std_logic_vector(7 downto 0)
);
end fifo_control_unit;
architecture behavioral of fifo_control_unit is
signal write_address_counter : std_logic_vector(11 downto 0) := "000000000000";
signal read_address_counter : std_logic_vector(10 downto 0) := (others=>'0');
signal empty_i : std_logic := '1';
signal full_i : std_logic := '0';
signal wea_i : std_logic;
-- signal first_received : std_logic := '0';
-- signal second_received : std_logic := '0';
signal doB_latched : std_logic_vector(7 downto 0) := (others=>'0');
signal EOF_latched : std_logic_vector(1 downto 0) := (others=>'0');
signal frame_started : std_logic := '0';
signal write_add_simple : std_logic := '1';
signal write_add_temp : std_logic_vector(11 downto 0) := (others=>'0');
signal read_add_simple : std_logic := '1';
signal read_add_temp : std_logic_vector(10 downto 0) := (others=>'0');
signal write_address_counter_minus_one : std_logic_vector(11 downto 0) := "100000000000";
signal write_address_counter_minus_one_temp : std_logic_vector(11 downto 0) := (others=>'0');
signal read_address_counter_minus_one : std_logic_vector(10 downto 0) := "10000000000";
signal read_address_counter_minus_one_temp : std_logic_vector(10 downto 0) := (others=>'0');
begin
-- test <= second & first;
--
-- PRZYPISANIA WYJÆ DO FRAME BUFFER'A
--
addrA <= write_address_counter;
addrB <= read_address_counter;
clkA <= Rx_Clk;
clkB <= clk;
enB <= POP;
enA <= Rx_DV;
diA <= Rx_D;
--data_out <= doB_latched;
data_out <= doB when read_add_simple = '0' else doB(3 downto 0) & doB(7 downto 4);
EOF <= doEOFB(0) or doEOFB(1);
--
-- PRZYPISANIA WYJÆ DO EOF BUFFER'A
--
addrEOFA <= "00" & write_address_counter_minus_one;
addrEOFB <= "00" & read_address_counter;
-- EOFenA <= '1';
-- EOFweA <= '1' when (Rx_DV = '0' and frame_started = '1') else '0';
-- EOFenB <= POP;
--
-- diEOFA <= "1";
EOFenA <= '1' when ((Rx_DV = '0' and frame_started = '1') or Rx_DV = '1') else '0';
EOFweA <= '1' when ((Rx_DV = '0' and frame_started = '1') or (wea_i = '1' and frame_started = '1')) else '0';
EOFenB <= POP;
diEOFA <= "1" when (Rx_DV = '0' and frame_started = '1') else "0";
--
-- FLAGA FRAME STARTED
--
-- ustawiana na 1 jak jest ramka, na 0 gdy nie ma
-- s³u¿y jako trigger do zapisania koñca ramki po opadniêciu Rx_DV
--
process(Rx_Clk)
begin
if rising_edge(Rx_Clk) then
if Rx_DV = '1' and frame_started = '0' then
frame_started <= '1';
elsif Rx_DV = '0'and frame_started = '1' then
frame_started <= '0';
end if;
end if;
end process;
--
-- USTAWIANIE WRITE ENABLE A
--
-- tutaj nastêpuje w³aciwe zabezpieczenie przed nadpisaniem starych danych w kolejce
--
process (Rx_Clk)
begin
if rising_edge(Rx_Clk) then
if (write_address_counter(11 downto 1) = 0 and read_address_counter = 0) or write_address_counter(11 downto 1) /= read_address_counter_minus_one then
weA <= '1';
wea_i <= '1';
else
weA <= '0';
wea_i <= '0';
end if;
end if;
end process;
--
-- LATCHOWANIE WYJÆ NA POP'IE
--
-- POP zwiêksza read counter + 1, a aktualnie wymagana wartoæ by³a wywietlana do tej pory, w zwi¹zku z tym
-- musimy j¹ zapisaæ, zanim zmieni siê na nastêpn¹
--
process (clk)
begin
if rising_edge(clk) then
if (POP = '1') then
if (read_add_simple = '1') then
doB_latched <= doB;
else
doB_latched <= doB(3 downto 0) & doB(7 downto 4);
end if;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (POP = '1') then
EOF_latched <= doEOFB;
end if;
end if;
end process;
--
-- USTAWIANIE FLAG EMPTY I FULL
--
process (Rx_Clk)
begin
if rising_edge(Rx_Clk) then
if write_address_counter(11 downto 1) = read_address_counter_minus_one then
full <= '1';
full_i <= '1';
else
full <= '0';
full_i <= '0';
end if;
end if;
end process;
-- process (clk)
-- begin
-- if rising_edge(clk) then
-- if read_address_counter = write_address_counter(11 downto 1) then
-- empty <= '1';
-- empty_i <= '1';
-- else
-- empty <= '0';
-- empty_i <= '0';
-- end if;
-- end if;
-- end process;
empty <= '1' when read_address_counter = write_address_counter(11 downto 1) else '0';
empty_i <= '1' when read_address_counter = write_address_counter(11 downto 1) else '0';
--
-- ZWIÊKSZANIE WRITE ADDRESS COUNTER'A W ZALE¯NOCI OD POPRZEDNIEJ WARTOCI
--
-- Licznik liczy w kodzie grey'a
-- simple zmieniana jest naprzemiennie i s³u¿y do rozró¿nienia jak policzyæ nastêpn¹ wartoæ
-- temp s³u¿y do xorowania z nim wartoci
-- zmiana nastêpuje przez odpowiednie dzia³anie
--
process (Rx_Clk)
begin
if rising_edge(Rx_Clk) then
if Rx_DV = '1' then
if (write_address_counter(11 downto 1) = 0 and read_address_counter = 0) or write_address_counter(11 downto 1) /= read_address_counter_minus_one then
write_add_simple <= not write_add_simple;
end if;
end if;
end if;
end process;
write_add_temp <= "100000000000" when (write_address_counter(10) = '1' and write_address_counter(9 downto 0) = "0000000000") or (write_address_counter = "100000000000") else
"010000000000" when write_address_counter(9) = '1' and write_address_counter(8 downto 0) = "000000000" else
"001000000000" when write_address_counter(8) = '1' and write_address_counter(7 downto 0) = "00000000" else
"000100000000" when write_address_counter(7) = '1' and write_address_counter(6 downto 0) = "0000000" else
"000010000000" when write_address_counter(6) = '1' and write_address_counter(5 downto 0) = "000000" else
"000001000000" when write_address_counter(5) = '1' and write_address_counter(4 downto 0) = "00000" else
"000000100000" when write_address_counter(4) = '1' and write_address_counter(3 downto 0) = "0000" else
"000000010000" when write_address_counter(3) = '1' and write_address_counter(2 downto 0) = "000" else
"000000001000" when write_address_counter(2) = '1' and write_address_counter(1 downto 0) = "00" else
"000000000100" when write_address_counter(1) = '1' and write_address_counter(0 downto 0) = "0" else
"000000000010" when write_address_counter(0) = '1' else
"000000000000";
process(Rx_Clk)
begin
if rising_edge(Rx_Clk) then
if Rx_DV = '1' then
if (write_address_counter(11 downto 1) = 0 and read_address_counter = 0) or write_address_counter(11 downto 1) /= read_address_counter_minus_one then
if write_add_simple = '1' then
write_address_counter <= write_address_counter xor "000000000001";
else
write_address_counter <= write_address_counter xor write_add_temp;
end if;
end if;
end if;
end if;
end process;
--
-- ZWIÊKSZANIE READ ADDRESS COUNTER'A W ZALE¯NOCI OD POPRZEDNIEJ WARTOCI
--
process (clk)
begin
if rising_edge(clk) then
if (POP = '1') then
if read_address_counter /= write_address_counter(11 downto 1) then
read_add_simple <= not read_add_simple;
end if;
end if;
end if;
end process;
read_add_temp <= "10000000000" when (read_address_counter(9) = '1' and read_address_counter(8 downto 0) = "000000000") or (read_address_counter = "10000000000") else
"01000000000" when read_address_counter(8) = '1' and read_address_counter(7 downto 0) = "00000000" else
"00100000000" when read_address_counter(7) = '1' and read_address_counter(6 downto 0) = "0000000" else
"00010000000" when read_address_counter(6) = '1' and read_address_counter(5 downto 0) = "000000" else
"00001000000" when read_address_counter(5) = '1' and read_address_counter(4 downto 0) = "00000" else
"00000100000" when read_address_counter(4) = '1' and read_address_counter(3 downto 0) = "0000" else
"00000010000" when read_address_counter(3) = '1' and read_address_counter(2 downto 0) = "000" else
"00000001000" when read_address_counter(2) = '1' and read_address_counter(1 downto 0) = "00" else
"00000000100" when read_address_counter(1) = '1' and read_address_counter(0 downto 0) = "0" else
"00000000010" when read_address_counter(0) = '1' else
"00000000000";
process(clk)
begin
if rising_edge(clk) then
if (POP = '1') then
if read_address_counter /= write_address_counter(11 downto 1) then
if read_add_simple = '1' then
read_address_counter <= read_address_counter xor "00000000001";
else
read_address_counter <= read_address_counter xor read_add_temp;
end if;
end if;
end if;
end if;
end process;
--
-- ZWIÊKSZANIE WRITE ADDRESS COUNTER'A MINUS ONE
--
-- minus one s³u¿y za adres do zapisania koñca ramki
--
write_address_counter_minus_one_temp <= "100000000000" when (write_address_counter_minus_one(10) = '1' and write_address_counter_minus_one(9 downto 0) = "0000000000") or (write_address_counter_minus_one = "100000000000") else
"010000000000" when write_address_counter_minus_one(9) = '1' and write_address_counter_minus_one(8 downto 0) = "000000000" else
"001000000000" when write_address_counter_minus_one(8) = '1' and write_address_counter_minus_one(7 downto 0) = "00000000" else
"000100000000" when write_address_counter_minus_one(7) = '1' and write_address_counter_minus_one(6 downto 0) = "0000000" else
"000010000000" when write_address_counter_minus_one(6) = '1' and write_address_counter_minus_one(5 downto 0) = "000000" else
"000001000000" when write_address_counter_minus_one(5) = '1' and write_address_counter_minus_one(4 downto 0) = "00000" else
"000000100000" when write_address_counter_minus_one(4) = '1' and write_address_counter_minus_one(3 downto 0) = "0000" else
"000000010000" when write_address_counter_minus_one(3) = '1' and write_address_counter_minus_one(2 downto 0) = "000" else
"000000001000" when write_address_counter_minus_one(2) = '1' and write_address_counter_minus_one(1 downto 0) = "00" else
"000000000100" when write_address_counter_minus_one(1) = '1' and write_address_counter_minus_one(0 downto 0) = "0" else
"000000000010" when write_address_counter_minus_one(0) = '1' else
"000000000000";
process(Rx_Clk)
begin
if rising_edge(Rx_Clk) then
if Rx_DV = '1' then
if (write_address_counter(11 downto 1) = 0 and read_address_counter = 0) or write_address_counter(11 downto 1) /= read_address_counter_minus_one then
if write_add_simple = '0' then
write_address_counter_minus_one <= write_address_counter_minus_one xor "000000000001";
else
write_address_counter_minus_one <= write_address_counter_minus_one xor write_address_counter_minus_one_temp;
end if;
end if;
end if;
end if;
end process;
--
-- ZWIÊKSZANIE READ ADDRESS COUNTER'A MINUS ONE
--
-- minus one s³u¿y do porównywania przy sterowaniu zapisywaniem i odczytywaniem
--
read_address_counter_minus_one_temp <= "10000000000" when (read_address_counter_minus_one(9) = '1' and read_address_counter_minus_one(8 downto 0) = "000000000") or (read_address_counter_minus_one = "10000000000") else
"01000000000" when read_address_counter_minus_one(8) = '1' and read_address_counter_minus_one(7 downto 0) = "00000000" else
"00100000000" when read_address_counter_minus_one(7) = '1' and read_address_counter_minus_one(6 downto 0) = "0000000" else
"00010000000" when read_address_counter_minus_one(6) = '1' and read_address_counter_minus_one(5 downto 0) = "000000" else
"00001000000" when read_address_counter_minus_one(5) = '1' and read_address_counter_minus_one(4 downto 0) = "00000" else
"00000100000" when read_address_counter_minus_one(4) = '1' and read_address_counter_minus_one(3 downto 0) = "0000" else
"00000010000" when read_address_counter_minus_one(3) = '1' and read_address_counter_minus_one(2 downto 0) = "000" else
"00000001000" when read_address_counter_minus_one(2) = '1' and read_address_counter_minus_one(1 downto 0) = "00" else
"00000000100" when read_address_counter_minus_one(1) = '1' and read_address_counter_minus_one(0 downto 0) = "0" else
"00000000010" when read_address_counter_minus_one(0) = '1' else
"00000000000";
process(clk)
begin
if rising_edge(clk) then
if (POP = '1') then
if read_address_counter /= write_address_counter(11 downto 1) then
if read_add_simple = '0' then
read_address_counter_minus_one <= read_address_counter_minus_one xor "00000000001";
else
read_address_counter_minus_one <= read_address_counter_minus_one xor read_address_counter_minus_one_temp;
end if;
end if;
end if;
end if;
end process;
end behavioral; |
---------------------------------------------------------------------------
--
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
---------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the DDS Compiler
-- LogiCORE module. The testbench has been generated by the Xilinx
-- CORE Generator software to accompany the netlist you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with the netlist created for your core.
--
-- See the DDS Compiler datasheet for further information about this core.
--
---------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated DDS Compiler core
-- named "sound_module".
--
-- There are two versions of your core that you can use in this testbench:
-- the XilinxCoreLib behavioral model or the generated netlist.
--
-- 1. XilinxCoreLib behavioral model
-- Compile sound_module.vhd into the work library. See your
-- simulator documentation for more information on how to do this.
--
-- 2. Generated netlist
-- Execute the following command in the directory containing your CORE
-- Generator output files, to create a VHDL netlist:
--
-- netgen -sim -ofmt vhdl sound_module.ngc sound_module_netlist.vhd
--
-- Compile sound_module_netlist.vhd into the work library. See your
-- simulator documentation for more information on how to do this.
--
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_sound_module is
end tb_sound_module;
architecture tb of tb_sound_module is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT input signals
-----------------------------------------------------------------------
-- General inputs
signal aclk : std_logic := '0'; -- the master clock
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Data master channel alias signals
signal m_axis_data_tdata_sine : std_logic_vector(15 downto 0) := (others => '0');
-- Alias signals for each separate TDM channel (these are 1 cycle delayed relative to the above alias signals)
signal m_axis_data_channel : integer := 0; -- indicates TDM channel number of data master channel outputs
signal m_axis_data_tdata_sine_c0 : std_logic_vector(15 downto 0) := (others => '0');
signal m_axis_data_tdata_sine_c1 : std_logic_vector(15 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.sound_module
port map (
aclk => aclk
,m_axis_data_tvalid => m_axis_data_tvalid
,m_axis_data_tdata => m_axis_data_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Run for long enough to produce 5 periods of outputs
wait for CLOCK_PERIOD * 10;
-- End of test
report "Not a real failure. Simulation finished successfully." severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the data master channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_sine <= m_axis_data_tdata(15 downto 0) when m_axis_data_tvalid = '1';
-- Data master channel alias signals for each TDM channel
-- Note that these are one cycle later than the overall data master channel signals
process (aclk)
begin
if rising_edge(aclk) then
if m_axis_data_tvalid = '1' then
if m_axis_data_channel = 1 then
m_axis_data_channel <= 0;
else
m_axis_data_channel <= m_axis_data_channel + 1;
end if;
if m_axis_data_channel = 0 then
m_axis_data_tdata_sine_c0 <= m_axis_data_tdata(15 downto 0);
elsif m_axis_data_channel = 1 then
m_axis_data_tdata_sine_c1 <= m_axis_data_tdata(15 downto 0);
end if;
end if;
end if;
end process;
end tb;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : CS8900A bus interface module
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: This module implements the bus-behavior of the CS8900A chip.
-- It is based on a dual ported memory, which can be read/written
-- from the cartridge port, as well as from the other CPU as I/O
-- device. This allows the software to emulate the functionality
-- of the link, while this hardware block only implements how the
-- chip behaves as seen from the cartrige port.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity cs8900a_bus
port (
clock : in std_logic;
reset : in std_logic;
bus_addr : in std_logic_vector(3 downto 0);
bus_write : in std_logic;
bus_read : in std_logic;
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
pp_addr : out unsigned(11 downto 0);
pp_write : out std_logic;
pp_read : out std_logic;
pp_tx_data : out std_logic; -- put
pp_rx_data : out std_logic; -- get
pp_wdata : out std_logic_vector(15 downto 0);
pp_rdata : in std_logic_vector(15 downto 0);
pp_new_rx_pkt : in std_logic );
end cs8900a_bus;
architecture gideon of cs8900a_bus is
-- The 8900A chip is accessed in WORDs, using alternately
-- even and odd bytes. Only PacketPage access in I/O mode
-- is supported.
constant c_rx_tx_data_0 : std_logic_vector(3 downto 1) := "000"; -- R/W
constant c_rx_tx_data_1 : std_logic_vector(3 downto 1) := "001"; -- R/W
constant c_tx_command : std_logic_vector(3 downto 1) := "010"; -- W
constant c_tx_length : std_logic_vector(3 downto 1) := "011"; -- W
constant c_isq : std_logic_vector(3 downto 1) := "100"; -- R
constant c_packet_page_pointer : std_logic_vector(3 downto 1) := "101"; -- R/W
constant c_packet_page_data_0 : std_logic_vector(3 downto 1) := "110"; -- R/W
constant c_packet_page_data_1 : std_logic_vector(3 downto 1) := "111"; -- R/W
constant c_lo_rx_tx_data_0 : std_logic_vector(3 downto 0) := "0000"; -- R/W
constant c_hi_rx_tx_data_0 : std_logic_vector(3 downto 0) := "0001"; -- R/W
constant c_lo_rx_tx_data_1 : std_logic_vector(3 downto 0) := "0010"; -- R/W
constant c_hi_rx_tx_data_1 : std_logic_vector(3 downto 0) := "0011"; -- R/W
constant c_lo_packet_page_pointer : std_logic_vector(3 downto 0) := "1010"; -- R/W
constant c_hi_packet_page_pointer : std_logic_vector(3 downto 0) := "1011"; -- R/W
constant c_lo_packet_page_data_0 : std_logic_vector(3 downto 0) := "1100"; -- R/W
constant c_hi_packet_page_data_0 : std_logic_vector(3 downto 0) := "1101"; -- R/W
constant c_lo_packet_page_data_1 : std_logic_vector(3 downto 0) := "1110"; -- R/W
constant c_hi_packet_page_data_1 : std_logic_vector(3 downto 0) := "1111"; -- R/W
signal packet_page_pointer : unsigned(11 downto 1);
signal packet_page_auto_inc : std_logic;
signal word_buffer : std_logic_vector(15 downto 0);
signal rx_count : integer range 0 to 2;
begin
pp_wdata <= word_buffer;
process(clock)
variable v_3bit_addr : std_logic_vector(3 downto 1);
begin
if rising_edge(clock) then
-- handle writes
pp_write <= '0';
pp_read <= '0';
pp_rx_data <= '0';
pp_tx_data <= '0';
pp_addr <= packet_page_pointer & '0';
v_3bit_addr := bus_addr(3 downto 1);
-- determine pp_addr for reads (default, will be overwritten by writes)
if bus_addr(3 downto 2)="00" then
case rx_count is
when 0 =>
pp_addr <= X"400";
when 1 =>
pp_addr <= X"402";
when others =>
pp_addr <= X"404";
end case;
if bus_read='1' and bus_addr(0)='1' then -- read from odd address
if rx_count /= 2 then
rx_count <= rx_count + 1;
pp_read <= '1';
else
pp_rx_data <= '1'; -- pop
end if;
end if;
end if;
if bus_write='1' then
if bus_addr(0)='0' then
word_buffer(7 downto 0) <= bus_wdata;
else
word_buffer(15 downto 8) <= bus_wdata;
case v_3bit_addr is
when c_rx_tx_data_0 | c_rx_tx_data_1 =>
pp_tx_data <= '1';
pp_write <= '1';
pp_addr <= X"A00";
when c_tx_command =>
pp_addr <= X"144";
pp_write <= '1';
when c_tx_length =>
pp_addr <= X"146";
pp_write <= '1';
when c_packet_page_pointer =>
packet_page_pointer <= unsigned(word_buffer(packet_page_pointer'range));
packet_page_auto_inc <= word_buffer(15);
when c_packet_page_data_0 | c_packet_page_data_1 =>
pp_write <= '1';
if packet_page_auto_inc='1' then
packet_page_pointer <= packet_page_pointer + 1;
end if;
when others =>
null;
end case;
end if;
end if;
if pp_new_tx_pkt='1' then
rx_count <= 0;
end if;
if reset='1' then
packet_page_pointer <= (others => '0');
packet_page_auto_inc <= '0';
end if;
end if;
end process;
-- determine output byte (combinatorial, since it's easy!)
with bus_addr select bus_rdata <=
pp_rdata(7 downto 0) when c_lo_rx_tx_data_0 | c_lo_rx_tx_data_1 | c_lo_packet_page_data_0 | c_lo_packet_page_data_1,
pp_rdata(15 downto 8) when c_hi_rx_tx_data_0 | c_hi_rx_tx_data_1 | c_hi_packet_page_data_0 | c_hi_packet_page_data_1,
std_logic_vector(packet_page_pointer(7 downto 1)) & '0' when c_lo_packet_page_pointer,
packet_page_auto_inc & "000" & std_logic_vector(packet_page_pointer(11 downto 8)) when c_hi_packet_page_pointer,
X"00" when others;
end;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : CS8900A bus interface module
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: This module implements the bus-behavior of the CS8900A chip.
-- It is based on a dual ported memory, which can be read/written
-- from the cartridge port, as well as from the other CPU as I/O
-- device. This allows the software to emulate the functionality
-- of the link, while this hardware block only implements how the
-- chip behaves as seen from the cartrige port.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity cs8900a_bus
port (
clock : in std_logic;
reset : in std_logic;
bus_addr : in std_logic_vector(3 downto 0);
bus_write : in std_logic;
bus_read : in std_logic;
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
pp_addr : out unsigned(11 downto 0);
pp_write : out std_logic;
pp_read : out std_logic;
pp_tx_data : out std_logic; -- put
pp_rx_data : out std_logic; -- get
pp_wdata : out std_logic_vector(15 downto 0);
pp_rdata : in std_logic_vector(15 downto 0);
pp_new_rx_pkt : in std_logic );
end cs8900a_bus;
architecture gideon of cs8900a_bus is
-- The 8900A chip is accessed in WORDs, using alternately
-- even and odd bytes. Only PacketPage access in I/O mode
-- is supported.
constant c_rx_tx_data_0 : std_logic_vector(3 downto 1) := "000"; -- R/W
constant c_rx_tx_data_1 : std_logic_vector(3 downto 1) := "001"; -- R/W
constant c_tx_command : std_logic_vector(3 downto 1) := "010"; -- W
constant c_tx_length : std_logic_vector(3 downto 1) := "011"; -- W
constant c_isq : std_logic_vector(3 downto 1) := "100"; -- R
constant c_packet_page_pointer : std_logic_vector(3 downto 1) := "101"; -- R/W
constant c_packet_page_data_0 : std_logic_vector(3 downto 1) := "110"; -- R/W
constant c_packet_page_data_1 : std_logic_vector(3 downto 1) := "111"; -- R/W
constant c_lo_rx_tx_data_0 : std_logic_vector(3 downto 0) := "0000"; -- R/W
constant c_hi_rx_tx_data_0 : std_logic_vector(3 downto 0) := "0001"; -- R/W
constant c_lo_rx_tx_data_1 : std_logic_vector(3 downto 0) := "0010"; -- R/W
constant c_hi_rx_tx_data_1 : std_logic_vector(3 downto 0) := "0011"; -- R/W
constant c_lo_packet_page_pointer : std_logic_vector(3 downto 0) := "1010"; -- R/W
constant c_hi_packet_page_pointer : std_logic_vector(3 downto 0) := "1011"; -- R/W
constant c_lo_packet_page_data_0 : std_logic_vector(3 downto 0) := "1100"; -- R/W
constant c_hi_packet_page_data_0 : std_logic_vector(3 downto 0) := "1101"; -- R/W
constant c_lo_packet_page_data_1 : std_logic_vector(3 downto 0) := "1110"; -- R/W
constant c_hi_packet_page_data_1 : std_logic_vector(3 downto 0) := "1111"; -- R/W
signal packet_page_pointer : unsigned(11 downto 1);
signal packet_page_auto_inc : std_logic;
signal word_buffer : std_logic_vector(15 downto 0);
signal rx_count : integer range 0 to 2;
begin
pp_wdata <= word_buffer;
process(clock)
variable v_3bit_addr : std_logic_vector(3 downto 1);
begin
if rising_edge(clock) then
-- handle writes
pp_write <= '0';
pp_read <= '0';
pp_rx_data <= '0';
pp_tx_data <= '0';
pp_addr <= packet_page_pointer & '0';
v_3bit_addr := bus_addr(3 downto 1);
-- determine pp_addr for reads (default, will be overwritten by writes)
if bus_addr(3 downto 2)="00" then
case rx_count is
when 0 =>
pp_addr <= X"400";
when 1 =>
pp_addr <= X"402";
when others =>
pp_addr <= X"404";
end case;
if bus_read='1' and bus_addr(0)='1' then -- read from odd address
if rx_count /= 2 then
rx_count <= rx_count + 1;
pp_read <= '1';
else
pp_rx_data <= '1'; -- pop
end if;
end if;
end if;
if bus_write='1' then
if bus_addr(0)='0' then
word_buffer(7 downto 0) <= bus_wdata;
else
word_buffer(15 downto 8) <= bus_wdata;
case v_3bit_addr is
when c_rx_tx_data_0 | c_rx_tx_data_1 =>
pp_tx_data <= '1';
pp_write <= '1';
pp_addr <= X"A00";
when c_tx_command =>
pp_addr <= X"144";
pp_write <= '1';
when c_tx_length =>
pp_addr <= X"146";
pp_write <= '1';
when c_packet_page_pointer =>
packet_page_pointer <= unsigned(word_buffer(packet_page_pointer'range));
packet_page_auto_inc <= word_buffer(15);
when c_packet_page_data_0 | c_packet_page_data_1 =>
pp_write <= '1';
if packet_page_auto_inc='1' then
packet_page_pointer <= packet_page_pointer + 1;
end if;
when others =>
null;
end case;
end if;
end if;
if pp_new_tx_pkt='1' then
rx_count <= 0;
end if;
if reset='1' then
packet_page_pointer <= (others => '0');
packet_page_auto_inc <= '0';
end if;
end if;
end process;
-- determine output byte (combinatorial, since it's easy!)
with bus_addr select bus_rdata <=
pp_rdata(7 downto 0) when c_lo_rx_tx_data_0 | c_lo_rx_tx_data_1 | c_lo_packet_page_data_0 | c_lo_packet_page_data_1,
pp_rdata(15 downto 8) when c_hi_rx_tx_data_0 | c_hi_rx_tx_data_1 | c_hi_packet_page_data_0 | c_hi_packet_page_data_1,
std_logic_vector(packet_page_pointer(7 downto 1)) & '0' when c_lo_packet_page_pointer,
packet_page_auto_inc & "000" & std_logic_vector(packet_page_pointer(11 downto 8)) when c_hi_packet_page_pointer,
X"00" when others;
end;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : CS8900A bus interface module
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: This module implements the bus-behavior of the CS8900A chip.
-- It is based on a dual ported memory, which can be read/written
-- from the cartridge port, as well as from the other CPU as I/O
-- device. This allows the software to emulate the functionality
-- of the link, while this hardware block only implements how the
-- chip behaves as seen from the cartrige port.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity cs8900a_bus
port (
clock : in std_logic;
reset : in std_logic;
bus_addr : in std_logic_vector(3 downto 0);
bus_write : in std_logic;
bus_read : in std_logic;
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
pp_addr : out unsigned(11 downto 0);
pp_write : out std_logic;
pp_read : out std_logic;
pp_tx_data : out std_logic; -- put
pp_rx_data : out std_logic; -- get
pp_wdata : out std_logic_vector(15 downto 0);
pp_rdata : in std_logic_vector(15 downto 0);
pp_new_rx_pkt : in std_logic );
end cs8900a_bus;
architecture gideon of cs8900a_bus is
-- The 8900A chip is accessed in WORDs, using alternately
-- even and odd bytes. Only PacketPage access in I/O mode
-- is supported.
constant c_rx_tx_data_0 : std_logic_vector(3 downto 1) := "000"; -- R/W
constant c_rx_tx_data_1 : std_logic_vector(3 downto 1) := "001"; -- R/W
constant c_tx_command : std_logic_vector(3 downto 1) := "010"; -- W
constant c_tx_length : std_logic_vector(3 downto 1) := "011"; -- W
constant c_isq : std_logic_vector(3 downto 1) := "100"; -- R
constant c_packet_page_pointer : std_logic_vector(3 downto 1) := "101"; -- R/W
constant c_packet_page_data_0 : std_logic_vector(3 downto 1) := "110"; -- R/W
constant c_packet_page_data_1 : std_logic_vector(3 downto 1) := "111"; -- R/W
constant c_lo_rx_tx_data_0 : std_logic_vector(3 downto 0) := "0000"; -- R/W
constant c_hi_rx_tx_data_0 : std_logic_vector(3 downto 0) := "0001"; -- R/W
constant c_lo_rx_tx_data_1 : std_logic_vector(3 downto 0) := "0010"; -- R/W
constant c_hi_rx_tx_data_1 : std_logic_vector(3 downto 0) := "0011"; -- R/W
constant c_lo_packet_page_pointer : std_logic_vector(3 downto 0) := "1010"; -- R/W
constant c_hi_packet_page_pointer : std_logic_vector(3 downto 0) := "1011"; -- R/W
constant c_lo_packet_page_data_0 : std_logic_vector(3 downto 0) := "1100"; -- R/W
constant c_hi_packet_page_data_0 : std_logic_vector(3 downto 0) := "1101"; -- R/W
constant c_lo_packet_page_data_1 : std_logic_vector(3 downto 0) := "1110"; -- R/W
constant c_hi_packet_page_data_1 : std_logic_vector(3 downto 0) := "1111"; -- R/W
signal packet_page_pointer : unsigned(11 downto 1);
signal packet_page_auto_inc : std_logic;
signal word_buffer : std_logic_vector(15 downto 0);
signal rx_count : integer range 0 to 2;
begin
pp_wdata <= word_buffer;
process(clock)
variable v_3bit_addr : std_logic_vector(3 downto 1);
begin
if rising_edge(clock) then
-- handle writes
pp_write <= '0';
pp_read <= '0';
pp_rx_data <= '0';
pp_tx_data <= '0';
pp_addr <= packet_page_pointer & '0';
v_3bit_addr := bus_addr(3 downto 1);
-- determine pp_addr for reads (default, will be overwritten by writes)
if bus_addr(3 downto 2)="00" then
case rx_count is
when 0 =>
pp_addr <= X"400";
when 1 =>
pp_addr <= X"402";
when others =>
pp_addr <= X"404";
end case;
if bus_read='1' and bus_addr(0)='1' then -- read from odd address
if rx_count /= 2 then
rx_count <= rx_count + 1;
pp_read <= '1';
else
pp_rx_data <= '1'; -- pop
end if;
end if;
end if;
if bus_write='1' then
if bus_addr(0)='0' then
word_buffer(7 downto 0) <= bus_wdata;
else
word_buffer(15 downto 8) <= bus_wdata;
case v_3bit_addr is
when c_rx_tx_data_0 | c_rx_tx_data_1 =>
pp_tx_data <= '1';
pp_write <= '1';
pp_addr <= X"A00";
when c_tx_command =>
pp_addr <= X"144";
pp_write <= '1';
when c_tx_length =>
pp_addr <= X"146";
pp_write <= '1';
when c_packet_page_pointer =>
packet_page_pointer <= unsigned(word_buffer(packet_page_pointer'range));
packet_page_auto_inc <= word_buffer(15);
when c_packet_page_data_0 | c_packet_page_data_1 =>
pp_write <= '1';
if packet_page_auto_inc='1' then
packet_page_pointer <= packet_page_pointer + 1;
end if;
when others =>
null;
end case;
end if;
end if;
if pp_new_tx_pkt='1' then
rx_count <= 0;
end if;
if reset='1' then
packet_page_pointer <= (others => '0');
packet_page_auto_inc <= '0';
end if;
end if;
end process;
-- determine output byte (combinatorial, since it's easy!)
with bus_addr select bus_rdata <=
pp_rdata(7 downto 0) when c_lo_rx_tx_data_0 | c_lo_rx_tx_data_1 | c_lo_packet_page_data_0 | c_lo_packet_page_data_1,
pp_rdata(15 downto 8) when c_hi_rx_tx_data_0 | c_hi_rx_tx_data_1 | c_hi_packet_page_data_0 | c_hi_packet_page_data_1,
std_logic_vector(packet_page_pointer(7 downto 1)) & '0' when c_lo_packet_page_pointer,
packet_page_auto_inc & "000" & std_logic_vector(packet_page_pointer(11 downto 8)) when c_hi_packet_page_pointer,
X"00" when others;
end;
|
---------------------------------------------------------------------------
-- Copyright 2012 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-10C.vhd
-- Creation Date:
-- Description:
-- 1050 Typewriter Console data latches and gating
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2012-04-07
-- Initial release
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
use work.FLL;
ENTITY n1050_DATA IS
port
(
-- Inputs
E_SW_SEL_BUS : IN E_SW_BUS_Type; -- 04CE1
USE_MANUAL_DECODER : IN STD_LOGIC; -- 03DA3
USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02BA3
USE_BASIC_CA_DECO : IN STD_LOGIC; -- 02AE6
GTD_CA_BITS : IN STD_LOGIC_VECTOR(0 to 3); -- 05CA2
XLATE_UC : IN STD_LOGIC; -- 09C
WR_LCH : IN STD_LOGIC; -- 09CD2 aka WRITE_LCH
RUN : IN STD_LOGIC; -- 09CE6
PROCEED_LCH : IN STD_LOGIC; -- 10BC3
-- TT4_POS_HOME_STT : IN STD_LOGIC; -- 10DD5
RD_OR_RD_INQ : IN STD_LOGIC; -- 09CC5
W_TIME, X_TIME, Y_TIME, Z_TIME : IN STD_LOGIC; -- 10AXX
Z_BUS : IN STD_LOGIC_VECTOR(0 to 8); -- 08BE3
CLOCK_1 : IN STD_LOGIC; -- 10AA5
PCH_1_CLUTCH : IN STD_LOGIC; -- 10DD5
GT_1050_BUS_OUT, GT_1050_TAGS_OUT : IN STD_LOGIC; -- 04CE6
n1050_OP_IN : IN STD_LOGIC; -- 10BC5
SET_SHIFT_LCH : IN STD_LOGIC; -- 09CD6
TA_REG_SET : IN STD_LOGIC; -- 10BB2
RST_ATTACH : IN STD_LOGIC; -- 10BC2
n1050_OPER : IN STD_LOGIC; -- 10DE4
READ_INQ : IN STD_LOGIC; -- 09CE6
RD_SHARE_REQ_LCH : IN STD_LOGIC; -- 09CC6
READ : IN STD_LOGIC; -- 09CE6
WRITE_MODE : IN STD_LOGIC; -- 09CFD2
RESTORE : IN STD_LOGIC; -- 10BD2
OUTPUT_SEL_AND_READY : IN STD_LOGIC; -- 10DD4
SHARE_REQ_RST : IN STD_LOGIC; -- 10BB6
n1050_RST_LCH : IN STD_LOGIC; -- 10BA3
RDR_1_CLUTCH : IN STD_LOGIC; -- 10DD5
UC_CHARACTER, LC_CHARACTER : IN STD_LOGIC; -- 09CD2
-- Z_BUS_0, Z_BUS_3 : IN STD_LOGIC; -- 06BDX
-- TT3_POS_1050_OPER : IN STD_LOGIC; -- 10DD4
TA_REG_POS_6_ATTN_RST : IN STD_LOGIC; -- 10BE3
PCH_BITS : IN STD_LOGIC_VECTOR(0 to 6);
-- CE controls
CE_GT_TA_OR_TE : IN STD_LOGIC;
CE_DATA_ENTER_GT : IN STD_LOGIC;
CE_TE_DECODE : IN STD_LOGIC;
CE_RUN_MODE : IN STD_LOGIC; -- 10DB3
n1050_CE_MODE : IN STD_LOGIC;
CE_BITS : IN STD_LOGIC_VECTOR(0 to 7); -- 10DA1
-- Outputs
A_REG_BUS : OUT STD_LOGIC_VECTOR(0 to 8); -- 07CA6
DATA_REG_BUS : OUT STD_LOGIC_VECTOR(0 to 7); -- 09C
TAGS_OUT : OUT STD_LOGIC_VECTOR(0 to 7); -- 10BB1 11AA2
NPL_BITS : OUT STD_LOGIC_VECTOR(0 to 7);
PTT_BITS : OUT STD_LOGIC_VECTOR(0 to 6); -- Output to printer ("RDR")
TE_LCH : OUT STD_LOGIC;
WR_SHARE_REQ : OUT STD_LOGIC; -- 10BD5
ALLOW_STROBE : OUT STD_LOGIC; -- 09CD4 09CE1
GT_WRITE_REG : OUT STD_LOGIC; -- 10DB4
FORCE_SHIFT_CHAR : OUT STD_LOGIC; -- 10DB4
FORCE_LC_SHIFT : OUT STD_LOGIC; -- 10DB4
SET_LOWER_CASE : OUT STD_LOGIC; -- 09CD4 09CB5
n1050_INTRV_REQ : OUT STD_LOGIC; -- 10BD4 04AA4
READY_SHARE : OUT STD_LOGIC; -- 10BD4 09CB4
TT5_POS_INTRV_REQ : OUT STD_LOGIC; -- 10DC4
-- Buses
TT_BUS: INOUT STD_LOGIC_VECTOR(0 to 7);
GTD_TT3: OUT STD_LOGIC;
DEBUG : INOUT DEBUG_BUS;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
P1,P2,P3,P4 : IN STD_LOGIC
);
END n1050_DATA;
ARCHITECTURE FMD OF n1050_DATA IS
type ConversionAtoE is array(0 to 255) of STD_LOGIC_VECTOR(0 to 7);
signal ASCII_TO_EBCDIC : ConversionAtoE :=
(
character'Pos(cr) => "00010101",
character'Pos(lf) => "00100101",
character'Pos(' ') => "01000000",
character'Pos('.') => "01001011",
character'Pos('<') => "01001100",
character'Pos('(') => "01001101",
character'Pos('+') => "01001110",
character'Pos('&') => "01010000",
character'Pos('$') => "01011011",
character'Pos(')') => "01011101",
character'Pos(';') => "01011110",
character'Pos('-') => "01100000",
character'Pos('/') => "01100001",
character'Pos(',') => "01101011",
character'Pos('%') => "01101100",
character'Pos('>') => "01101110",
character'Pos('?') => "01101111",
character'Pos(':') => "01111010",
character'Pos('#') => "01111011",
character'Pos('@') => "01111100",
character'Pos('0') => "11110000", character'Pos('1') => "11110001", character'Pos('2') => "11110010",
character'Pos('3') => "11110011", character'Pos('4') => "11110100",
character'Pos('5') => "11110101", character'Pos('6') => "11110110", character'Pos('7') => "11110111",
character'Pos('8') => "11111000", character'Pos('9') => "11111001",
character'Pos('A') => "11000001", character'Pos('B') => "11000010", character'Pos('C') => "11000011",
character'Pos('D') => "11000100", character'Pos('E') => "11000101", character'Pos('F') => "11000110",
character'Pos('G') => "11000111", character'Pos('H') => "11001000", character'Pos('I') => "11001001",
character'Pos('J') => "11010001", character'Pos('K') => "11010010", character'Pos('L') => "11010011",
character'Pos('M') => "11010100", character'Pos('N') => "11010101", character'Pos('O') => "11010110",
character'Pos('P') => "11010111", character'Pos('Q') => "11011000", character'Pos('R') => "11011001",
character'Pos('S') => "11100010", character'Pos('T') => "11100011", character'Pos('U') => "11100100",
character'Pos('V') => "11100101", character'Pos('W') => "11100110", character'Pos('X') => "11100111",
character'Pos('Y') => "11101000", character'Pos('Z') => "11101001",
character'Pos('a') => "10000001", character'Pos('b') => "10000010", character'Pos('c') => "10000011",
character'Pos('d') => "10000100", character'Pos('e') => "10000101", character'Pos('f') => "10000110",
character'Pos('g') => "10000111", character'Pos('h') => "10001000", character'Pos('i') => "10001001",
character'Pos('j') => "10010001", character'Pos('k') => "10010010", character'Pos('l') => "10010011",
character'Pos('m') => "10010100", character'Pos('n') => "10010101", character'Pos('o') => "10010110",
character'Pos('p') => "10010111", character'Pos('q') => "10011000", character'Pos('r') => "10011001",
character'Pos('s') => "10100010", character'Pos('t') => "10100011", character'Pos('u') => "10100100",
character'Pos('v') => "10100101", character'Pos('w') => "10100110", character'Pos('x') => "10100111",
character'Pos('y') => "10101000", character'Pos('z') => "10101001",
others => "01101111");
type ConversionEtoA is array(0 to 255) of character;
signal EBCDIC_TO_ASCII : ConversionEtoA :=
(
2#00010101# => cr,
2#00100101# => lf,
2#01000000# => ' ',
2#01001011# => '.',
2#01001100# => '<',
2#01001101# => '(',
2#01001110# => '+',
2#01001111# => '|',
2#01010000# => '&',
2#01011010# => '!',
2#01011011# => '$',
2#01011100# => '*',
2#01011101# => ')',
2#01011110# => ';',
2#01011111# => '~',
2#01100000# => '-',
2#01100001# => '/',
2#01101011# => ',',
2#01101100# => '%',
2#01101101# => '_',
2#01101110# => '>',
2#01101111# => '?',
2#01111010# => ':',
2#01111011# => '#',
2#01111100# => '@',
2#01111101# => ''',
2#01111110# => '=',
2#01111111# => '"',
2#11110000# => '0', 2#11110001# => '1', 2#11110010# => '2', 2#11110011# => '3', 2#11110100# => '4',
2#11110101# => '5', 2#11110110# => '6', 2#11110111# => '7', 2#11111000# => '8', 2#11111001# => '9',
2#11000001# => 'A', 2#11000010# => 'B', 2#11000011# => 'C', 2#11000100# => 'D', 2#11000101# => 'E',
2#11000110# => 'F', 2#11000111# => 'G', 2#11001000# => 'H', 2#11001001# => 'I',
2#11010001# => 'J', 2#11010010# => 'K', 2#11010011# => 'L', 2#11010100# => 'M', 2#11010101# => 'N',
2#11010110# => 'O', 2#11010111# => 'P', 2#11011000# => 'Q', 2#11011001# => 'R',
2#11100010# => 'S', 2#11100011# => 'T', 2#11100100# => 'U', 2#11100101# => 'V', 2#11100110# => 'W',
2#11100111# => 'X', 2#11101000# => 'Y', 2#11101001# => 'Z',
2#10000001# => 'a', 2#10000010# => 'b', 2#10000011# => 'c', 2#10000100# => 'd', 2#10000101# => 'e',
2#10000110# => 'f', 2#10000111# => 'g', 2#10001000# => 'h', 2#10001001# => 'i',
2#10010001# => 'j', 2#10010010# => 'k', 2#10010011# => 'l', 2#10010100# => 'm', 2#10010101# => 'n',
2#10010110# => 'o', 2#10010111# => 'p', 2#10011000# => 'q', 2#10011001# => 'r',
2#10100010# => 's', 2#10100011# => 't', 2#10100100# => 'u', 2#10100101# => 'v', 2#10100110# => 'w',
2#10100111# => 'x', 2#10101000# => 'y', 2#10101001# => 'z',
others => '?');
signal sGT_1050_BUS_OUT, sGT_1050_TAGS_OUT : STD_LOGIC;
signal sSET_LOWER_CASE : STD_LOGIC;
signal sTE_LCH : STD_LOGIC;
signal sSET_LOW_CASE : STD_LOGIC;
signal sDATA_REG : STD_LOGIC_VECTOR(0 to 7);
signal sNPL_BITS : STD_LOGIC_VECTOR(0 to 7);
signal GT_1050_BUS_TO_A, GT_1050_TAGS_TO_A : STD_LOGIC;
signal sTAGS_OUT : STD_LOGIC_VECTOR(0 to 7);
signal DATA_REG_LATCH : STD_LOGIC;
signal DATA_REG_IN : STD_LOGIC_VECTOR(0 to 7);
signal TI_P_BIT : STD_LOGIC;
signal sPTT_BITS : STD_LOGIC_VECTOR(0 to 6);
signal sGTD_TT3 : STD_LOGIC;
signal CE_TE_LCH_SET : STD_LOGIC;
signal TE_LCH_SET, TE_LCH_RESET : STD_LOGIC;
signal sGT_WRITE_REG : STD_LOGIC;
signal WR_SHARE_REQ_SET, WR_SHARE_REQ_RESET,sWR_SHARE_REQ : STD_LOGIC;
signal ALLOW_STROBE_SET, ALLOW_STROBE_RESET, sALLOW_STROBE : STD_LOGIC;
signal SHIFT_SET, SHIFT_RESET : STD_LOGIC;
signal sSHIFT : STD_LOGIC := '0';
signal INTRV_REQ_SET, INTRV_REQ_RESET, sINTRV_REQ : STD_LOGIC;
signal n1050_INTRV_REQ_RESET : STD_LOGIC;
signal NOT_OPER_RESET : STD_LOGIC;
signal NOT_OPER : STD_LOGIC := '0';
signal RDY_SHARE_SET, RDY_SHARE_RESET, sRDY_SHARE : STD_LOGIC;
signal CancelCode : STD_LOGIC;
signal NOT_n1050_OPER : STD_LOGIC;
BEGIN
-- Fig 5-10C
GT_1050_BUS_TO_A <= (E_SW_SEL_BUS.TI_SEL and USE_MANUAL_DECODER) or
(USE_ALT_CA_DECODER and not GTD_CA_BITS(0) and GTD_CA_BITS(1) and GTD_CA_BITS(2) and GTD_CA_BITS(3)); -- AB3C7 AA=1 CA=0111
GT_1050_TAGS_TO_A <= (E_SW_SEL_BUS.TT_SEL and USE_MANUAL_DECODER) or
(USE_BASIC_CA_DECO and not GTD_CA_BITS(0) and not GTD_CA_BITS(1) and not GTD_CA_BITS(2) and GTD_CA_BITS(3)); -- AA2C6 AA=0 CA=0001
A_REG_BUS <= not(((sNPL_BITS & TI_P_BIT) and (0 to 8=>GT_1050_BUS_TO_A)) or ((TT_BUS & '0') and (0 to 8=>GT_1050_TAGS_TO_A))); -- AC2E2 - Note: Inverted
DATA_REG_PH: PHV8 port map(D=>DATA_REG_IN,L=>DATA_REG_LATCH,Q=>sDATA_REG); -- AC3B2
DATA_REG_BUS <= sDATA_REG;
DATA_REG_LATCH <= (CE_DATA_ENTER_GT and CE_TE_DECODE) or (RD_OR_RD_INQ and W_TIME) or (T3 and sGT_1050_BUS_OUT) or not RUN; -- AC3P5
TAGS_OUT <= DATA_REG_IN; -- ?
sGT_1050_BUS_OUT <= GT_1050_BUS_OUT; -- AC2D6
sGT_1050_TAGS_OUT <= GT_1050_TAGS_OUT; -- AC2M4
DATA_REG_IN <= (Z_BUS(0 to 7) and (0 to 7=>(sGT_1050_BUS_OUT or sGT_1050_TAGS_OUT)))
or (CE_BITS and (0 to 7=>CE_GT_TA_OR_TE))
or (('0' & PCH_BITS) and (0 to 7=>(CLOCK_1 and PCH_1_CLUTCH))); -- AC2B4 AC2H6 AC2M6 AC2M2
sGTD_TT3 <= TT_BUS(3) and n1050_CE_MODE; -- AC2H5 AC2L4
GTD_TT3 <= sGTD_TT3;
TT_BUS(7) <= EVENPARITY(sDATA_REG(1 to 7)) and WR_LCH and RUN and not TT_BUS(0); -- AC2E4 AC2J2
-- CancelCode <= '1' when sDATA_REG(1 to 7)="1100000" else '0'; -- DATA_REG=X1100000
CancelCode <= '1' when sDATA_REG(1 to 7)="0010101" else '0'; -- DATA_REG (ASCII) = 15 = ^U
TT_BUS(0) <= CancelCode and PROCEED_LCH and TT_BUS(4); -- AL2F5 AC2D6
-- The following converts the card code CBA8421 on the DATA_REG bus to EBCDIC
-- C P P P P
-- B 0 0 1 1
-- A 0 1 0 1
-- =====================
-- 0 =40 @=7C -=60 &=50
-- 1 1=F1 /=61 j=91 a=81
-- 2 2=F2 s=A2 k=92 b=82
-- 3 3=F3 t=A3 l=93 c=83
-- 4 4=F4 u=A4 m=94 d=84
-- 5 5=F5 v=A5 n=95 e=85
-- 6 6=F6 w=A6 o=96 f=86
-- 7 7=F7 x=A7 p=97 g=87
-- 8 8=F8 y=A8 q=98 h=88
-- 9 9=F9 z=A9 r=99 i=89
-- A 0=FA CAN
-- B #=7B ,=6B $=5B .=4B
-- C
-- D CR
-- E UC EOB LC
-- F
-- For the purposes of this project, this will convert ASCII on CBA8421 into EBCDIC in MPL
-- sNPL_BITS(0) <= 0; -- AC3J2
-- sNPL_BITS(1) <= 0; -- AC3J2
-- sNPL_BITS(2) <= 0; -- AC3K2
-- sNPL_BITS(3) <= 0; -- AC3H2
-- sNPL_BITS(4) <= 0; -- AC3H2
-- sNPL_BITS(5) <= 0; -- AC3K2
-- sNPL_BITS(6) <= 0; -- AC3J2
-- sNPL_BITS(7) <= 0; -- AC3J2
sNPL_BITS <= ASCII_TO_EBCDIC(Conv_Integer(sDATA_REG));
-- sNPL_BITS <= STD_LOGIC_VECTOR(to_unsigned(Conv_Integer(sDATA_REG),8)); -- * * Temporary debug - no translation
NPL_BITS <= sNPL_BITS;
TI_P_BIT <= EVENPARITY(sNPL_BITS(0 to 7)); -- AC2G4
-- The following converts EBCDIC on the DATA_REG bus to card code CBA8421
-- For the purposes of this project, this will convert EBCDIC in DATA_REG into ASCII in PTT
-- sPTT_BIT_C <= EVEN_PARITY(...); -- C AC3G4
-- sPTT_BIT_B <= 0; -- AC3H2
-- sPTT_BIT_A <= 0; -- AC3K2
-- sPTT_BIT_8 <= 0; -- AC3G2
-- sPTT_BIT_4 <= 0; -- AC3G2
-- sPTT_BIT_2 <= 0; -- AC3G2
-- sPTT_BIT_1 <= 0; -- AC3G2
sPTT_BITS <= STD_LOGIC_VECTOR(to_unsigned(Character'Pos(EBCDIC_TO_ASCII(Conv_Integer(sDATA_REG))),7));
PTT_BITS <= sPTT_BITS;
CE_TE_LCH_SET <= (CE_DATA_ENTER_GT and CE_TE_DECODE) and n1050_OP_IN and CLOCK_1; -- AC2D7 AC2L6 ?? Ignore NOT in AC2M4
TE_LCH_SET <= CE_TE_LCH_SET or (CE_RUN_MODE and CE_TE_DECODE) or (sGT_1050_BUS_OUT and T4); -- AC2J7
sGT_WRITE_REG <= (Z_TIME and sALLOW_STROBE and not sSHIFT); -- AC2C6
GT_WRITE_REG <= sGT_WRITE_REG; -- AC2M4 AC2H6
TE_LCH_RESET <= sSET_LOWER_CASE or sGT_WRITE_REG;
TE_LCH_FL: entity FLL port map(S=>TE_LCH_SET,R=>TE_LCH_RESET,Q=>sTE_LCH); -- AC2B6
TE_LCH <= sTE_LCH;
WR_SHARE_REQ_SET <= not n1050_RST_LCH and W_TIME and WR_LCH and not sTE_LCH;
WR_SHARE_REQ_RESET <= RST_ATTACH or SHARE_REQ_RST;
WR_SHARE_REQ_FL: entity FLL port map(S=>WR_SHARE_REQ_SET,R=>WR_SHARE_REQ_RESET,Q=>sWR_SHARE_REQ); -- AC2K5 AC2D6
WR_SHARE_REQ <= sWR_SHARE_REQ;
ALLOW_STROBE_SET <= RDR_1_CLUTCH and Y_TIME and sTE_LCH;
ALLOW_STROBE_RESET <= sSET_LOWER_CASE or (Y_TIME and not RDR_1_CLUTCH) or X_TIME;
ALLOW_STROBE_FL: entity FLL port map(S=>ALLOW_STROBE_SET,R=>ALLOW_STROBE_RESET,Q=>sALLOW_STROBE); -- AC2B6
ALLOW_STROBE <= sALLOW_STROBE;
SHIFT_SET <= (n1050_CE_MODE and SET_SHIFT_LCH) or (SET_SHIFT_LCH and sTE_LCH and Y_TIME);
SHIFT_RESET <= X_TIME or sSET_LOWER_CASE;
SHIFT_FL: entity FLL port map(S=>SHIFT_SET,R=>SHIFT_RESET,Q=>sSHIFT); -- AC2B6
FORCE_SHIFT_CHAR <= (UC_CHARACTER and Z_TIME and sSHIFT) or (sSHIFT and Z_TIME and LC_CHARACTER); -- AC2C6
FORCE_LC_SHIFT <= (sSHIFT and Z_TIME and LC_CHARACTER); -- AC2D6 ?? not?
sSET_LOWER_CASE <= TA_REG_SET or RST_ATTACH; -- AC2C6 AC2D6
SET_LOWER_CASE <= sSET_LOWER_CASE;
INTRV_REQ_SET <= (not n1050_OPER and READ_INQ and not RD_SHARE_REQ_LCH)
or (not RD_SHARE_REQ_LCH and READ and (not TT_BUS(1) or not TT_BUS(3))) -- AC2G6 AC2H5
or ( WRITE_MODE
and not RESTORE
and not Z_TIME
and not TA_REG_SET
and (not TT_BUS(3) or not OUTPUT_SEL_AND_READY)
and (not CE_DATA_ENTER_GT or not n1050_CE_MODE)); -- AC2E5 AC2K7
INTRV_REQ_RESET <= SHARE_REQ_RST or RST_ATTACH; -- AC2H5 AC2H3
INTRV_REQ_FL: entity FLL port map(S=>INTRV_REQ_SET,R=>INTRV_REQ_RESET,Q=>sINTRV_REQ); -- AC2G6 AC2H3
TT5_POS_INTRV_REQ <= sINTRV_REQ;
n1050_INTRV_REQ_RESET <= n1050_CE_MODE or (Z_BUS(0) and GT_1050_TAGS_OUT) or (GT_1050_TAGS_OUT and Z_BUS(3)) or RST_ATTACH or sRDY_SHARE;
n1050_INTRV_REQ_FL: entity FLL port map(S=>sINTRV_REQ,R=>n1050_INTRV_REQ_RESET,Q=>n1050_INTRV_REQ); -- AC2K3 AC2H4
NOT_OPER_RESET <= RUN or sRDY_SHARE;
NOT_n1050_OPER <= not n1050_OPER;
NOT_OPER_FL: entity FLL port map(S=>NOT_n1050_OPER,R=>NOT_OPER_RESET,Q=>NOT_OPER); -- AC2G5 ?? Set input inverted
RDY_SHARE_SET <= not sINTRV_REQ and TT_BUS(3) and NOT_OPER; -- AC2J7
RDY_SHARE_RESET <= INTRV_REQ_RESET or RUN or TA_REG_POS_6_ATTN_RST;
RDY_SHARE_FL: entity FLL port map(S=>RDY_SHARE_SET,R=>RDY_SHARE_RESET,Q=>sRDY_SHARE); -- AC2F6 AC2E5
READY_SHARE <= sRDY_SHARE;
with DEBUG.Selection select
DEBUG.Probe <=
sDATA_REG(0) when 0,
sDATA_REG(1) when 1,
sDATA_REG(2) when 2,
sDATA_REG(3) when 3,
sDATA_REG(4) when 4,
sDATA_REG(5) when 5,
sDATA_REG(6) when 6,
sDATA_REG(7) when 7,
sNPL_BITS(0) when 8,
sNPL_BITS(1) when 9,
sNPL_BITS(2) when 10,
sNPL_BITS(3) when 11,
sNPL_BITS(4) when 12,
sNPL_BITS(5) when 13,
sNPL_BITS(6) when 14,
sNPL_BITS(7) when 15;
END FMD;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity contador_mod8 is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
contagem : out std_logic_vector(2 downto 0);
fim : out std_logic);
end contador_mod8;
architecture exemplo of contador_mod8 is
signal IQ: unsigned(2 downto 0);
begin
process (clock, conta, IQ, zera)
begin
if clock'event and clock = '1' then
if zera = '1' then
IQ <= (others => '0');
elsif conta = '1' then
IQ <= IQ + 1;
end if;
end if;
if IQ = 7 then
fim <= '1';
else
fim <= '0';
end if;
contagem <= std_logic_vector(IQ);
end process;
end exemplo;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2045.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02045ent IS
END c07s02b04x00p01n01i02045ent;
ARCHITECTURE c07s02b04x00p01n01i02045arch OF c07s02b04x00p01n01i02045ent IS
BEGIN
TESTING: PROCESS
type WORD is array(0 to 31) of BIT;
variable WORDV : WORD;
BEGIN
WORDV := WORDV - WORDV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02045 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02045arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2045.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02045ent IS
END c07s02b04x00p01n01i02045ent;
ARCHITECTURE c07s02b04x00p01n01i02045arch OF c07s02b04x00p01n01i02045ent IS
BEGIN
TESTING: PROCESS
type WORD is array(0 to 31) of BIT;
variable WORDV : WORD;
BEGIN
WORDV := WORDV - WORDV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02045 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02045arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2045.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02045ent IS
END c07s02b04x00p01n01i02045ent;
ARCHITECTURE c07s02b04x00p01n01i02045arch OF c07s02b04x00p01n01i02045ent IS
BEGIN
TESTING: PROCESS
type WORD is array(0 to 31) of BIT;
variable WORDV : WORD;
BEGIN
WORDV := WORDV - WORDV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02045 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02045arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.filter_shared_package.all;
entity filter_mac_mem_controller is
generic
(
BIQUADS : natural := B;
MAC_FILTER_CH : natural := MC; -- MAC operations per channel for Main filter operation
RMS_CH_EN : natural := RMS; -- Enable flag for RMS function. 0-disabled 1- enabled.
MEAN_CH_EN : natural := MEAN; -- Enable flag for MEAN function. 0-disabled 1- enabled.
CHANNELS : natural := C
);
port
(
cnt_delay_mac : in std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH+RMS_CH_EN+MEAN_CH_EN))))-1 downto 0);
cnt_delay_ch : in std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0);
cnt_acc_mac : in std_logic_vector(natural(ceil(log2(real(MAC_FILTER_CH+RMS_CH_EN+MEAN_CH_EN))))-1 downto 0);
cnt_acc_ch : in std_logic_vector(natural(ceil(log2(real(CHANNELS))))-1 downto 0);
valid_delay : in std_logic;
valid_acc : in std_logic;
zero_acc_misc : in std_logic;
acc_rdaddr : out ACC_ADD_T;
acc_rden : out std_logic;
acc_wraddr : out ACC_ADD_T;
acc_wren : out std_logic;
zero_acc : out std_logic
);
end filter_mac_mem_controller;
architecture behaviour of filter_mac_mem_controller is
constant MAC_BIQUAD : natural := MAC_FILTER_CH/BIQUADS;
signal filter_delay_s : std_logic_vector(natural(ceil(log2(real(MOD_ACC_PAGES))))-1 downto 0);
signal filter_acc_s : std_logic_vector(natural(ceil(log2(real(MOD_ACC_PAGES))))-1 downto 0);
signal zero_acc_filter_s : std_logic;
begin
-- read and write memory page
Read_Write_Page_RMS_MEAN : if RMS_CH_EN /= 0 and MEAN_CH_EN /= 0 generate
process(cnt_acc_mac,cnt_delay_mac)
variable tmp_cnt_acc_mac : unsigned(cnt_acc_mac'range);
variable tmp_cnt_delay_mac : unsigned(cnt_delay_mac'range);
variable tmp_filter_acc : std_logic_vector(filter_acc_s'range);
variable tmp_filter_delay : std_logic_vector(filter_delay_s'range);
begin
tmp_cnt_acc_mac := unsigned(cnt_acc_mac);
tmp_cnt_delay_mac := unsigned(cnt_delay_mac);
if tmp_cnt_acc_mac <= MAC_FILTER_CH - 1 then tmp_filter_acc := (others => '0');
elsif tmp_cnt_acc_mac = MAC_FILTER_CH then tmp_filter_acc := "01";
elsif tmp_cnt_acc_mac = MAC_FILTER_CH + 1 then tmp_filter_acc := "10";
else tmp_filter_acc := "--";
end if;
if tmp_cnt_delay_mac <= MAC_FILTER_CH - 1 then tmp_filter_delay := (others => '0');
elsif tmp_cnt_delay_mac = MAC_FILTER_CH then tmp_filter_delay := "01";
elsif tmp_cnt_delay_mac = MAC_FILTER_CH + 1 then tmp_filter_delay := "10";
else tmp_filter_delay := "--";
end if;
filter_acc_s <= tmp_filter_acc;
filter_delay_s <= tmp_filter_delay;
end process;
end generate;
Read_Write_Page_RMS_Or_MEAN: if ((RMS_CH_EN /= 0 and MEAN_CH_EN = 0) or (RMS_CH_EN = 0 and MEAN_CH_EN /= 0)) generate
process(cnt_acc_mac,cnt_delay_mac)
variable tmp_cnt_acc_mac : unsigned(cnt_acc_mac'range);
variable tmp_cnt_delay_mac : unsigned(cnt_delay_mac'range);
variable tmp_filter_acc : std_logic_vector(filter_acc_s'range);
variable tmp_filter_delay : std_logic_vector(filter_delay_s'range);
begin
tmp_cnt_acc_mac := unsigned(cnt_acc_mac);
tmp_cnt_delay_mac := unsigned(cnt_delay_mac);
if tmp_cnt_acc_mac <= MAC_FILTER_CH - 1 then tmp_filter_acc := (others => '0');
elsif tmp_cnt_acc_mac = MAC_FILTER_CH then tmp_filter_acc := "1"; -- RMS or MEAN
else tmp_filter_acc := "-";
end if;
if tmp_cnt_delay_mac <= MAC_FILTER_CH - 1 then tmp_filter_delay := (others => '0');
elsif tmp_cnt_delay_mac = MAC_FILTER_CH then tmp_filter_delay := "1"; -- RMS or MEAN
else tmp_filter_delay := "-";
end if;
filter_acc_s <= tmp_filter_acc;
filter_delay_s <= tmp_filter_delay;
end process;
end generate;
Read_Write_Page: if (RMS_CH_EN = 0 and MEAN_CH_EN = 0) generate
filter_acc_s <= (others => '0');
filter_delay_s <= (others => '0');
end generate;
-- read interface
acc_rdaddr <= std_logic_vector(resize(unsigned(filter_acc_s) * to_unsigned(CHANNELS,cnt_acc_ch'length), acc_wraddr'length) + unsigned(cnt_acc_ch)); -- p*C + c
acc_rden <= valid_acc;
-- write interface
acc_wraddr <= std_logic_vector(resize(unsigned(filter_delay_s) * to_unsigned(CHANNELS,cnt_delay_ch'length), acc_wraddr'length) + unsigned(cnt_delay_ch)); -- p*C + c
acc_wren <= valid_delay;
-- Zero the accumulator
Zero_Acc_Filter : process(cnt_delay_mac)
variable tmp_cnt_delay_mac : unsigned(cnt_delay_mac'range);
variable tmp_zero_acc_filter : std_logic;
begin
tmp_cnt_delay_mac := unsigned(cnt_delay_mac)+1;
tmp_zero_acc_filter := '0';
-- end of biquad 0,1,2,3,4...
if(((tmp_cnt_delay_mac) mod (MAC_BIQUAD) = 0) and tmp_cnt_delay_mac <= MAC_FILTER_CH) then
tmp_zero_acc_filter := '1';
end if;
zero_acc_filter_s <= tmp_zero_acc_filter;
end process Zero_Acc_Filter;
zero_acc <= zero_acc_filter_s or zero_acc_misc;
end behaviour;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity invalid is
port
(
i_ip0: in std_logic;
i_clock: in std_logic;
i_o: in std_logic;
i_o_reset: in std_logic;
i_o_b_reset: in std_logic;
i_i_reset: in std_logic;
o_ip0: out std_logic;
o_clock: out std_logic;
o_o: out std_logic;
o_i_reset: out std_logic;
o_o_reset: out std_logic;
o_o_b_reset: out std_logic;
b_ip0: inout std_logic;
b_clock: inout std_logic;
b_o: inout std_logic;
b_i_reset: inout std_logic;
b_o_reset: inout std_logic;
b_b_o_reset: inout std_logic
);
end;
architecture RTL of invalid is
begin
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/29/2015 11:08:18 AM
-- Design Name:
-- Module Name: dsp_32x32Mul_block - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNIMACRO;
use UNIMACRO.vcomponents.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity MulBB is
port (
CLK : in std_logic;
RST : in std_logic;
VALID_IN : in std_logic;
READY_IN : in std_logic;
LEFT : in std_logic_vector(31 downto 0);
RIGHT : in std_logic_vector(31 downto 0);
VALID_OUT : out std_logic;
READY_OUT : out std_logic;
MUL_OUT : out std_logic_vector(31 downto 0)
);
end MulBB;
architecture Behavioral of MulBB is
signal A_INPUT : std_logic_vector(41 downto 0) := (others => '0');
signal B_INPUT : std_logic_vector(34 downto 0) := (others => '0');
signal P_OUTPUT : std_logic_vector(75 downto 0) := (others => '0');
--
constant DELAY_MUL : positive := 7;
TYPE iBus_MUL is array(DELAY_MUL-1 downto 0) of std_logic;
signal ValidsRegBus_MUL : iBus_MUL := (others => '0');
--
COMPONENT logic_dff_block
Port (
D : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC
);
END COMPONENT;
--
-- BEGIN DSP48E1_inst_4
signal MULTISIGNOUT_DSP4 : std_logic := '0';
signal CARRYCASCOUT_DSP4 : std_logic := '0';
signal OVERFLOW_DSP4 : std_logic := '0';
signal PATTERNBDETECT_DSP4 : std_logic := '0';
signal PATTERNDETECT_DSP4 : std_logic := '0';
signal UNDERFLOW_DSP4 : std_logic := '0';
--
signal P_DSP4 : std_logic_vector(47 downto 0) := (others => '0');
--
signal ACIN_DSP4 : std_logic_vector(29 downto 0) := (others => '0');
signal BCIN_DSP4 : std_logic_vector(17 downto 0) := (others => '0');
signal CARRYCASCIN_DSP4 : std_logic := '0';
signal MULTISIGNIN_DSP4 : std_logic := '0';
signal PCIN_DSP4 : std_logic_vector(47 downto 0) := (others => '0');
signal PCOUT_DSP4 : std_logic_vector(47 downto 0) := (others => '0');
--
signal ALUMODE_DSP4 : std_logic_vector(3 downto 0) := (others => '0');
signal CARRYINSEL_DSP4 : std_logic_vector(2 downto 0) := (others => '0');
signal INMODE_DSP4 : std_logic_vector(4 downto 0) := (others => '0');
signal OPMODE_DSP4 : std_logic_vector(6 downto 0) := (others => '0');
--
signal A_DSP4 : std_logic_vector(29 downto 0) := (others => '0');
signal B_DSP4 : std_logic_vector(17 downto 0) := (others => '0');
signal C_DSP4 : std_logic_vector(47 downto 0) := (others => '0');
signal CARRYIN_DSP4 : std_logic := '0';
signal D_DSP4 : std_logic_vector(24 downto 0) := (others => '0');
-- END DSP48E1_inst_4
-- BEGIN DSP48E1_inst_3
signal MULTISIGNOUT_DSP3 : std_logic := '0';
signal CARRYCASCOUT_DSP3 : std_logic := '0';
signal OVERFLOW_DSP3 : std_logic := '0';
signal PATTERNBDETECT_DSP3 : std_logic := '0';
signal PATTERNDETECT_DSP3 : std_logic := '0';
signal UNDERFLOW_DSP3 : std_logic := '0';
--
signal P_DSP3 : std_logic_vector(47 downto 0) := (others => '0');
--
signal ACIN_DSP3 : std_logic_vector(29 downto 0) := (others => '0');
signal BCIN_DSP3 : std_logic_vector(17 downto 0) := (others => '0');
signal ACOUT_DSP3 : std_logic_vector(29 downto 0) := (others => '0');
signal BCOUT_DSP3 : std_logic_vector(17 downto 0) := (others => '0');
signal CARRYCASCIN_DSP3 : std_logic := '0';
signal MULTISIGNIN_DSP3 : std_logic := '0';
signal PCIN_DSP3 : std_logic_vector(47 downto 0) := (others => '0');
signal PCOUT_DSP3 : std_logic_vector(47 downto 0) := (others => '0');
--
signal ALUMODE_DSP3 : std_logic_vector(3 downto 0) := (others => '0');
signal CARRYINSEL_DSP3 : std_logic_vector(2 downto 0) := (others => '0');
signal INMODE_DSP3 : std_logic_vector(4 downto 0) := (others => '0');
signal OPMODE_DSP3 : std_logic_vector(6 downto 0) := (others => '0');
--
signal A_DSP3 : std_logic_vector(29 downto 0) := (others => '0');
signal B_DSP3 : std_logic_vector(17 downto 0) := (others => '0');
signal C_DSP3 : std_logic_vector(47 downto 0) := (others => '0');
signal CARRYIN_DSP3 : std_logic := '0';
signal D_DSP3 : std_logic_vector(24 downto 0) := (others => '0');
-- END DSP48E1_inst_3
-- BEGIN DSP48E1_inst_2
signal MULTISIGNOUT_DSP2 : std_logic := '0';
signal CARRYCASCOUT_DSP2 : std_logic := '0';
signal OVERFLOW_DSP2 : std_logic := '0';
signal PATTERNBDETECT_DSP2 : std_logic := '0';
signal PATTERNDETECT_DSP2 : std_logic := '0';
signal UNDERFLOW_DSP2 : std_logic := '0';
--
signal P_DSP2 : std_logic_vector(47 downto 0) := (others => '0');
--
signal ACIN_DSP2 : std_logic_vector(29 downto 0) := (others => '0');
signal BCIN_DSP2 : std_logic_vector(17 downto 0) := (others => '0');
signal ACOUT_DSP2 : std_logic_vector(29 downto 0) := (others => '0');
signal BCOUT_DSP2 : std_logic_vector(17 downto 0) := (others => '0');
signal CARRYCASCIN_DSP2 : std_logic := '0';
signal MULTISIGNIN_DSP2 : std_logic := '0';
signal PCIN_DSP2 : std_logic_vector(47 downto 0) := (others => '0');
signal PCOUT_DSP2 : std_logic_vector(47 downto 0) := (others => '0');
--
signal ALUMODE_DSP2 : std_logic_vector(3 downto 0) := (others => '0');
signal CARRYINSEL_DSP2 : std_logic_vector(2 downto 0) := (others => '0');
signal INMODE_DSP2 : std_logic_vector(4 downto 0) := (others => '0');
signal OPMODE_DSP2 : std_logic_vector(6 downto 0) := (others => '0');
--
signal A_DSP2 : std_logic_vector(29 downto 0) := (others => '0');
signal B_DSP2 : std_logic_vector(17 downto 0) := (others => '0');
signal C_DSP2 : std_logic_vector(47 downto 0) := (others => '0');
signal CARRYIN_DSP2 : std_logic := '0';
signal D_DSP2 : std_logic_vector(24 downto 0) := (others => '0');
-- END DSP48E1_inst_2
-- BEGIN DSP48E1_inst_1
signal MULTISIGNOUT_DSP1 : std_logic := '0';
signal CARRYCASCOUT_DSP1 : std_logic := '0';
signal OVERFLOW_DSP1 : std_logic := '0';
signal PATTERNBDETECT_DSP1 : std_logic := '0';
signal PATTERNDETECT_DSP1 : std_logic := '0';
signal UNDERFLOW_DSP1 : std_logic := '0';
--
signal P_DSP1 : std_logic_vector(47 downto 0) := (others => '0');
--
signal ACIN_DSP1 : std_logic_vector(29 downto 0) := (others => '0');
signal BCIN_DSP1 : std_logic_vector(17 downto 0) := (others => '0');
signal ACOUT_DSP1 : std_logic_vector(29 downto 0) := (others => '0');
signal BCOUT_DSP1 : std_logic_vector(17 downto 0) := (others => '0');
signal CARRYCASCIN_DSP1 : std_logic := '0';
signal MULTISIGNIN_DSP1 : std_logic := '0';
signal PCIN_DSP1 : std_logic_vector(47 downto 0) := (others => '0');
signal PCOUT_DSP1 : std_logic_vector(47 downto 0) := (others => '0');
--
signal ALUMODE_DSP1 : std_logic_vector(3 downto 0) := (others => '0');
signal CARRYINSEL_DSP1 : std_logic_vector(2 downto 0) := (others => '0');
signal INMODE_DSP1 : std_logic_vector(4 downto 0) := (others => '0');
signal OPMODE_DSP1 : std_logic_vector(6 downto 0) := (others => '0');
--
signal A_DSP1 : std_logic_vector(29 downto 0) := (others => '0');
signal B_DSP1 : std_logic_vector(17 downto 0) := (others => '0');
signal C_DSP1 : std_logic_vector(47 downto 0) := (others => '0');
signal CARRYIN_DSP1 : std_logic := '0';
signal D_DSP1 : std_logic_vector(24 downto 0) := (others => '0');
-- END DSP48E1_inst_1
COMPONENT dsp_sreg_block
Generic (
WIDTH : natural;
LENGTH : natural
);
Port (
D : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT dsp_dff_block
Generic (
Width : natural
);
Port (
D : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (WIDTH-1 downto 0)
);
END COMPONENT;
begin
-- DSP_4 OPMODE: 1010101 (shift PCIN | M | M)
-- ^
-- |
-- DSP_3 OPMODE: 0010101 (PCIN | M | M)
-- ^
-- |
-- DSP_2 OPMODE: 1010101 (shift PCIN | M | M)
-- ^
-- |
-- DSP_1 OPMODE: 0000101 (0 | M | M)
-- ############################################################################
DSP48E1_inst_4 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "CASCADE", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 1, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 1, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 1, -- Number of pipeline stages for C (0 or 1)
DREG => 1, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => CARRYCASCOUT_DSP4, -- 1-bit output: Cascade carry output
MULTSIGNOUT => MULTISIGNOUT_DSP4, -- 1-bit output: Multiplier sign cascade output
PCOUT => open, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => OVERFLOW_DSP4, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => PATTERNBDETECT_DSP4, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => PATTERNDETECT_DSP4, -- 1-bit output: Pattern detect output
UNDERFLOW => UNDERFLOW_DSP4, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => P_DSP4, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => ACIN_DSP4, -- 30-bit input: A cascade data input
BCIN => BCOUT_DSP3, -- 18-bit input: B cascade input
CARRYCASCIN => CARRYCASCIN_DSP4, -- 1-bit input: Cascade carry input
MULTSIGNIN => MULTISIGNIN_DSP4, -- 1-bit input: Multiplier sign input
PCIN => PCOUT_DSP3, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
ALUMODE => ALUMODE_DSP4, -- 4-bit input: ALU control input
CARRYINSEL => CARRYINSEL_DSP4, -- 3-bit input: Carry select input
CLK => CLK, -- 1-bit input: Clock input
INMODE => INMODE_DSP4, -- 5-bit input: INMODE control input
OPMODE => OPMODE_DSP4, -- 7-bit input: Operation mode input
-- Data: 30-bit (each) input: Data Ports
A => A_DSP4, -- 30-bit input: A data input
B => B_DSP4, -- 18-bit input: B data input
C => C_DSP4, -- 48-bit input: C data input
CARRYIN => CARRYIN_DSP4, -- 1-bit input: Carry input signal
D => D_DSP4, -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '1', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '1', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '1', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '1', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '1', -- 1-bit input: Clock enable input for DREG
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => RST, -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => RST, -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => RST, -- 1-bit input: Reset input for ALUMODEREG
RSTB => RST, -- 1-bit input: Reset input for BREG
RSTC => RST, -- 1-bit input: Reset input for CREG
RSTCTRL => RST, -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => RST, -- 1-bit input: Reset input for DREG and ADREG
RSTINMODE => RST, -- 1-bit input: Reset input for INMODEREG
RSTM => RST, -- 1-bit input: Reset input for MREG
RSTP => RST -- 1-bit input: Reset input for PREG
);
DSP48E1_inst_3 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 1, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 1, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 1, -- Number of pipeline stages for C (0 or 1)
DREG => 1, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => ACOUT_DSP3, -- 30-bit output: A port cascade output
BCOUT => BCOUT_DSP3, -- 18-bit output: B port cascade output
CARRYCASCOUT => CARRYCASCOUT_DSP3, -- 1-bit output: Cascade carry output
MULTSIGNOUT => MULTISIGNOUT_DSP3, -- 1-bit output: Multiplier sign cascade output
PCOUT => PCOUT_DSP3, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => OVERFLOW_DSP3, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => PATTERNBDETECT_DSP3, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => PATTERNDETECT_DSP3, -- 1-bit output: Pattern detect output
UNDERFLOW => UNDERFLOW_DSP3, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => P_DSP3, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => ACIN_DSP3, -- 30-bit input: A cascade data input
BCIN => BCIN_DSP3, -- 18-bit input: B cascade input
CARRYCASCIN => CARRYCASCIN_DSP3, -- 1-bit input: Cascade carry input
MULTSIGNIN => MULTISIGNIN_DSP3, -- 1-bit input: Multiplier sign input
PCIN => PCOUT_DSP2, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
ALUMODE => ALUMODE_DSP3, -- 4-bit input: ALU control input
CARRYINSEL => CARRYINSEL_DSP3, -- 3-bit input: Carry select input
CLK => CLK, -- 1-bit input: Clock input
INMODE => INMODE_DSP3, -- 5-bit input: INMODE control input
OPMODE => OPMODE_DSP3, -- 7-bit input: Operation mode input
-- Data: 30-bit (each) input: Data Ports
A => A_DSP3, -- 30-bit input: A data input
B => B_DSP3, -- 18-bit input: B data input
C => C_DSP3, -- 48-bit input: C data input
CARRYIN => CARRYIN_DSP3, -- 1-bit input: Carry input signal
D => D_DSP3, -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '1', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '1', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '1', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '1', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '1', -- 1-bit input: Clock enable input for DREG
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => RST, -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => RST, -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => RST, -- 1-bit input: Reset input for ALUMODEREG
RSTB => RST, -- 1-bit input: Reset input for BREG
RSTC => RST, -- 1-bit input: Reset input for CREG
RSTCTRL => RST, -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => RST, -- 1-bit input: Reset input for DREG and ADREG
RSTINMODE => RST, -- 1-bit input: Reset input for INMODEREG
RSTM => RST, -- 1-bit input: Reset input for MREG
RSTP => RST -- 1-bit input: Reset input for PREG
);
DSP48E1_inst_2 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "CASCADE", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 1, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 1, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 1, -- Number of pipeline stages for C (0 or 1)
DREG => 1, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => ACOUT_DSP2, -- 30-bit output: A port cascade output
BCOUT => BCOUT_DSP2, -- 18-bit output: B port cascade output
CARRYCASCOUT => CARRYCASCOUT_DSP2, -- 1-bit output: Cascade carry output
MULTSIGNOUT => MULTISIGNOUT_DSP2, -- 1-bit output: Multiplier sign cascade output
PCOUT => PCOUT_DSP2, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => OVERFLOW_DSP2, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => PATTERNBDETECT_DSP2, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => PATTERNDETECT_DSP2, -- 1-bit output: Pattern detect output
UNDERFLOW => UNDERFLOW_DSP2, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => P_DSP2, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => ACIN_DSP2, -- 30-bit input: A cascade data input
BCIN => BCOUT_DSP1, -- 18-bit input: B cascade input
CARRYCASCIN => CARRYCASCIN_DSP2, -- 1-bit input: Cascade carry input
MULTSIGNIN => MULTISIGNIN_DSP2, -- 1-bit input: Multiplier sign input
PCIN => PCOUT_DSP1, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
ALUMODE => ALUMODE_DSP2, -- 4-bit input: ALU control input
CARRYINSEL => CARRYINSEL_DSP2, -- 3-bit input: Carry select input
CLK => CLK, -- 1-bit input: Clock input
INMODE => INMODE_DSP2, -- 5-bit input: INMODE control input
OPMODE => OPMODE_DSP2, -- 7-bit input: Operation mode input
-- Data: 30-bit (each) input: Data Ports
A => A_DSP2, -- 30-bit input: A data input
B => B_DSP2, -- 18-bit input: B data input
C => C_DSP2, -- 48-bit input: C data input
CARRYIN => CARRYIN_DSP2, -- 1-bit input: Carry input signal
D => D_DSP2, -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '1', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '1', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '1', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '1', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '1', -- 1-bit input: Clock enable input for DREG
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => RST, -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => RST, -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => RST, -- 1-bit input: Reset input for ALUMODEREG
RSTB => RST, -- 1-bit input: Reset input for BREG
RSTC => RST, -- 1-bit input: Reset input for CREG
RSTCTRL => RST, -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => RST, -- 1-bit input: Reset input for DREG and ADREG
RSTINMODE => RST, -- 1-bit input: Reset input for INMODEREG
RSTM => RST, -- 1-bit input: Reset input for MREG
RSTP => RST -- 1-bit input: Reset input for PREG
);
DSP48E1_inst_1 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 1, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 1, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 1, -- Number of pipeline stages for C (0 or 1)
DREG => 1, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => ACOUT_DSP1, -- 30-bit output: A port cascade output
BCOUT => BCOUT_DSP1, -- 18-bit output: B port cascade output
CARRYCASCOUT => CARRYCASCOUT_DSP1, -- 1-bit output: Cascade carry output
MULTSIGNOUT => MULTISIGNOUT_DSP1, -- 1-bit output: Multiplier sign cascade output
PCOUT => PCOUT_DSP1, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => OVERFLOW_DSP1, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => PATTERNBDETECT_DSP1, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => PATTERNDETECT_DSP1, -- 1-bit output: Pattern detect output
UNDERFLOW => UNDERFLOW_DSP1, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => P_DSP1, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => ACIN_DSP1, -- 30-bit input: A cascade data input
BCIN => BCIN_DSP1, -- 18-bit input: B cascade input
CARRYCASCIN => CARRYCASCIN_DSP1, -- 1-bit input: Cascade carry input
MULTSIGNIN => MULTISIGNIN_DSP1, -- 1-bit input: Multiplier sign input
PCIN => PCIN_DSP1, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
ALUMODE => ALUMODE_DSP1, -- 4-bit input: ALU control input
CARRYINSEL => CARRYINSEL_DSP1, -- 3-bit input: Carry select input
CLK => CLK, -- 1-bit input: Clock input
INMODE => INMODE_DSP1, -- 5-bit input: INMODE control input
OPMODE => OPMODE_DSP1, -- 7-bit input: Operation mode input
-- Data: 30-bit (each) input: Data Ports
A => A_DSP1, -- 30-bit input: A data input
B => B_DSP1, -- 18-bit input: B data input
C => C_DSP1, -- 48-bit input: C data input
CARRYIN => CARRYIN_DSP1, -- 1-bit input: Carry input signal
D => D_DSP1, -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '1', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '1', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '1', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '1', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '1', -- 1-bit input: Clock enable input for DREG
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => RST, -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => RST, -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => RST, -- 1-bit input: Reset input for ALUMODEREG
RSTB => RST, -- 1-bit input: Reset input for BREG
RSTC => RST, -- 1-bit input: Reset input for CREG
RSTCTRL => RST, -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => RST, -- 1-bit input: Reset input for DREG and ADREG
RSTINMODE => RST, -- 1-bit input: Reset input for INMODEREG
RSTM => RST, -- 1-bit input: Reset input for MREG
RSTP => RST -- 1-bit input: Reset input for PREG
);
-- ############################################################################
ALUMODE_DSP4 <= "0000";
ALUMODE_DSP3 <= "0000";
ALUMODE_DSP2 <= "0000";
ALUMODE_DSP1 <= "0000";
OPMODE_DSP4 <= "1010101"; -- (shift PCIN | M | M)
OPMODE_DSP3 <= "0010101"; -- (PCIN | M | M)
OPMODE_DSP2 <= "1010101"; -- (shift PCIN | M | M)
OPMODE_DSP1 <= "0000101"; -- (0 | M | M)
-- ############################################################################
-- DSP INPUT REGISTERS
-------------------------------------------------------------------------------
IRegA_Dsp4: component dsp_sreg_block
generic map (
WIDTH => 25,
LENGTH => 3
)
port map (
D => A_INPUT(41 downto 17),
CLK => CLK,
RST => RST,
Q => A_DSP4(24 downto 0)
);
IRegA_Dsp3: component dsp_sreg_block
generic map (
WIDTH => 18,
LENGTH => 2
)
port map (
D => A_DSP1(17 downto 0),
CLK => CLK,
RST => RST,
Q => A_DSP3(17 downto 0)
);
IRegB_Dsp3: component dsp_sreg_block
generic map (
WIDTH => 18,
LENGTH => 2
)
port map (
D => B_INPUT(34 downto 17),
CLK => CLK,
RST => RST,
Q => B_DSP3(17 downto 0)
);
IRegA_Dsp2: component dsp_dff_block
generic map (
WIDTH => 25
)
port map (
D => A_INPUT(41 downto 17),
CLK => CLK,
RST => RST,
Q => A_DSP2(24 downto 0)
);
A_DSP1(17 downto 0) <= '0' & A_INPUT(16 downto 0);
B_DSP1(17 downto 0) <= '0' & B_INPUT(16 downto 0);
-------------------------------------------------------------------------------
-- DSP OUTPUT REGISTERS
-------------------------------------------------------------------------------
P_OUTPUT(75 downto 34) <= P_DSP4(41 downto 0);
ORegP_Dsp3: component dsp_dff_block
generic map (
WIDTH => 17
)
port map (
D => P_DSP3(16 downto 0),
CLK => CLK,
RST => RST,
Q => P_OUTPUT(33 downto 17)
);
ORegP_Dsp1: component dsp_sreg_block
generic map (
WIDTH => 17,
LENGTH => 3
)
port map (
D => P_DSP1(16 downto 0),
CLK => CLK,
RST => RST,
Q => P_OUTPUT(16 downto 0)
);
validReg_MUL_int: for i in 0 to DELAY_MUL generate
begin
validdffLeft_MUL: if i = 0 generate
begin
valid_dff: component logic_dff_block
port map (
D => VALID_IN,
CLK => CLK,
RST => RST,
Q => ValidsRegBus_MUL(i)
);
end generate validdffLeft_MUL;
--
dffOthers_MUL: if (i > 0 AND i < DELAY_MUL) generate
begin
valid_dff: component logic_dff_block
port map (
D => ValidsRegBus_MUL(i-1),
CLK => CLK,
RST => RST,
Q => ValidsRegBus_MUL(i)
);
end generate dffOthers_MUL;
--
dffRight_MUL: if i = DELAY_MUL generate
begin
valid_dff: component logic_dff_block
port map (
D => ValidsRegBus_MUL(i-1),
CLK => CLK,
RST => RST,
Q => VALID_OUT
);
end generate dffRight_MUL;
end generate validReg_MUL_int;
-- ############################################################################
calc_result : process(clk)
begin
if rising_edge(clk) then
A_INPUT <= (41 downto 32 => '0') & LEFT;
B_INPUT <= (34 downto 32 => '0') & RIGHT;
MUL_OUT <= P_OUTPUT(31 downto 0);
end if;
end process;
READY_OUT <= READY_IN;
end Behavioral;
|
-- file: clock_manager.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___200.000______0.000______50.0______210.548____196.077
-- CLK_OUT2____40.000______0.000______50.0______327.382____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________32____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock_manager is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_80 : out std_logic;
CLK_40 : out std_logic
);
end clock_manager;
architecture xilinx of clock_manager is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clock_manager,clk_wiz_v3_6,{component_name=clock_manager,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 4,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 20,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_80,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_40,
I => clkout1);
end xilinx;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
Entity hamming_decoder is
port
(hamming_in : in std_logic_vector(38 downto 0); --d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 --d26 d27 p0 p1 p2 p3 p4 p5 p6
dataout : out std_logic_vector(31 downto 0); --d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 --d26 d27
s_err_corr : out std_logic; --diagnostic outputs
d_err_det : out std_logic; --diagnostic outputs
no_error : out std_logic); --diagnostic outputs
end hamming_decoder;
architecture beh OF hamming_decoder is
Signal syndrome : std_logic_vector (6 downto 0);
begin
syndrome(0) <= hamming_in(0) xor hamming_in(1) xor hamming_in(3) xor hamming_in(4) xor hamming_in(6) xor
hamming_in(8) xor hamming_in(10) xor hamming_in(11) xor hamming_in(13) xor hamming_in(15) xor
hamming_in(17) xor hamming_in(19) xor hamming_in(21) xor hamming_in(23) xor hamming_in(25) xor hamming_in(26) xor hamming_in(28) xor hamming_in(30) xor hamming_in(32);
syndrome(1) <= hamming_in(0) xor hamming_in(2) xor hamming_in(3) xor hamming_in(5) xor hamming_in(6) xor
hamming_in(9) xor hamming_in(10) xor hamming_in(12) xor hamming_in(13) xor hamming_in(16) xor
hamming_in(17) xor hamming_in(20) xor hamming_in(21) xor hamming_in(24) xor hamming_in(25) xor hamming_in(27) xor hamming_in(28) xor hamming_in(31) xor hamming_in(33);
syndrome(2) <= XOR_REDUCE(hamming_in(3 downto 1)) xor XOR_REDUCE(hamming_in(10 downto 7)) xor XOR_REDUCE(hamming_in(17 downto 14)) xor
XOR_REDUCE(hamming_in(25 downto 22)) xor XOR_REDUCE(hamming_in(31 downto 29)) xor hamming_in(34);
syndrome(3) <= XOR_REDUCE(hamming_in(10 downto 4)) xor XOR_REDUCE(hamming_in(25 downto 18)) xor hamming_in(35);
syndrome(4) <= XOR_REDUCE(hamming_in(25 downto 11)) xor hamming_in(36);
syndrome(5) <= XOR_REDUCE(hamming_in(31 downto 26)) xor hamming_in(37);
syndrome(6) <= XOR_REDUCE(hamming_in(38 downto 0));
PROCESS(hamming_in, syndrome)
BEGIN
if syndrome(6) = '0' then
s_err_corr <= '0';
if (syndrome = "0000000") then -------no errors
no_error <= '1';
d_err_det <= '0';
dataout <= hamming_in(31 downto 0);
else -- (syndrome(5 downto 0) /= "000000")
no_error <= '0';
d_err_det <= '1';
dataout <= (others=> '0');
end if;
else -----------------------------------------------single bit error syndrome(6) = '1'
no_error <= '0';
d_err_det <= '0';
s_err_corr <= '1';
dataout <= hamming_in(31 downto 0); -- to cover all the bits
Case syndrome(5 downto 0) is
when "000000"|"000001"|"000010"|"000100"|"001000"|"010000"|"100000" => ------ this implies the error is only in parity bits, not data.
dataout <= hamming_in(31 downto 0);
when "000011" => dataout(0) <= not hamming_in(0);
when "000101" => dataout(1) <= not hamming_in(1);
when "000110" => dataout(2) <= not hamming_in(2);
when "000111" => dataout(3) <= not hamming_in(3);
when "001001" => dataout(4) <= not hamming_in(4);
when "001010" => dataout(5) <= not hamming_in(5);
when "001011" => dataout(6) <= not hamming_in(6);
when "001100" => dataout(7) <= not hamming_in(7);
when "001101" => dataout(8) <= not hamming_in(8);
when "001110" => dataout(9) <= not hamming_in(9);
when "001111" => dataout(10) <= not hamming_in(10);
when "010001" => dataout(11) <= not hamming_in(11);
when "010010" => dataout(12) <= not hamming_in(12);
when "010011" => dataout(13) <= not hamming_in(13);
when "010100" => dataout(14) <= not hamming_in(14);
when "010101" => dataout(15) <= not hamming_in(15);
when "010110" => dataout(16) <= not hamming_in(16);
when "010111" => dataout(17) <= not hamming_in(17);
when "011000" => dataout(18) <= not hamming_in(18);
when "011001" => dataout(19) <= not hamming_in(19);
when "011010" => dataout(20) <= not hamming_in(20);
when "011011" => dataout(21) <= not hamming_in(21);
when "011100" => dataout(22) <= not hamming_in(22);
when "011101" => dataout(23) <= not hamming_in(23);
when "011110" => dataout(24) <= not hamming_in(24);
when "011111" => dataout(25) <= not hamming_in(25);
when "100001" => dataout(26) <= not hamming_in(26);
when "100010" => dataout(27) <= not hamming_in(27);
when "100011" => dataout(28) <= not hamming_in(28);
when "100100" => dataout(29) <= not hamming_in(29);
when "100101" => dataout(30) <= not hamming_in(30);
when "100110" => dataout(31) <= not hamming_in(31);
when others=> dataout <= (others=> '0');
END Case;
END if;
END process;
END beh; |
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|
`protect begin_protected
`protect version = 1
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5680)
`protect data_block
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`protect end_protected
|
--
-- File Name: MessagePkg.vhd
-- Design Unit Name: MessagePkg
-- Revision: STANDARD VERSION, revision 2015.01
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for multi-line name/message to be associated with a data structure.
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Latest standard version available at:
-- http://www.SynthWorks.com/downloads
--
-- Revision History:
-- Date Version Description
-- 06/2010: 0.1 Initial revision
-- 07/2014: 2014.07 Moved specialization required by CoveragePkg to CoveragePkg
-- 07/2014: 2014.07a Removed initialized pointers which can lead to memory leaks.
-- 01/2015: 2015.01 Removed initialized parameter from Get
-- 04/2018: 2018.04 Minor updates to alert message
--
--
-- Copyright (c) 2010 - 2018 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use std.textio.all ;
package MessagePkg is
type MessagePType is protected
procedure Set (MessageIn : String) ;
impure function Get (ItemNumber : integer) return string ;
impure function GetCount return integer ;
impure function IsSet return boolean ;
procedure Clear ; -- clear message
procedure Deallocate ; -- clear message
end protected MessagePType ;
end package MessagePkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body MessagePkg is
-- Local Data Structure Types
type LineArrayType is array (natural range <>) of line ;
type LineArrayPtrType is access LineArrayType ;
type MessagePType is protected body
variable MessageCount : integer := 0 ;
constant INITIAL_ITEM_COUNT : integer := 16 ;
variable MaxMessageCount : integer := 0 ;
variable MessagePtr : LineArrayPtrType ;
------------------------------------------------------------
procedure Set (MessageIn : String) is
------------------------------------------------------------
variable NamePtr : line ;
variable OldMaxMessageCount : integer ;
variable OldMessagePtr : LineArrayPtrType ;
begin
MessageCount := MessageCount + 1 ;
if MessageCount > MaxMessageCount then
OldMaxMessageCount := MaxMessageCount ;
MaxMessageCount := MaxMessageCount + INITIAL_ITEM_COUNT ;
OldMessagePtr := MessagePtr ;
MessagePtr := new LineArrayType(1 to MaxMessageCount) ;
for i in 1 to OldMaxMessageCount loop
MessagePtr(i) := OldMessagePtr(i) ;
end loop ;
Deallocate( OldMessagePtr ) ;
end if ;
MessagePtr(MessageCount) := new string'(MessageIn) ;
end procedure Set ;
------------------------------------------------------------
impure function Get (ItemNumber : integer) return string is
------------------------------------------------------------
begin
if MessageCount > 0 then
if ItemNumber >= 1 and ItemNumber <= MessageCount then
return MessagePtr(ItemNumber).all ;
else
Alert(OSVVM_ALERTLOG_ID, "OSVVM.MessagePkg.Get input value out of range", FAILURE) ;
return "" ; -- error if this happens
end if ;
else
Alert(OSVVM_ALERTLOG_ID, "OSVVM.MessagePkg.Get message is not set", FAILURE) ;
return "" ; -- error if this happens
end if ;
end function Get ;
------------------------------------------------------------
impure function GetCount return integer is
------------------------------------------------------------
begin
return MessageCount ;
end function GetCount ;
------------------------------------------------------------
impure function IsSet return boolean is
------------------------------------------------------------
begin
return MessageCount > 0 ;
end function IsSet ;
------------------------------------------------------------
procedure Deallocate is -- clear message
------------------------------------------------------------
variable CurPtr : LineArrayPtrType ;
begin
for i in 1 to MessageCount loop
deallocate( MessagePtr(i) ) ;
end loop ;
MessageCount := 0 ;
MaxMessageCount := 0 ;
deallocate( MessagePtr ) ;
end procedure Deallocate ;
------------------------------------------------------------
procedure Clear is -- clear
------------------------------------------------------------
begin
Deallocate ;
end procedure Clear ;
end protected body MessagePType ;
end package body MessagePkg ; |
--
-- File Name: MessagePkg.vhd
-- Design Unit Name: MessagePkg
-- Revision: STANDARD VERSION, revision 2015.01
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for multi-line name/message to be associated with a data structure.
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Latest standard version available at:
-- http://www.SynthWorks.com/downloads
--
-- Revision History:
-- Date Version Description
-- 06/2010: 0.1 Initial revision
-- 07/2014: 2014.07 Moved specialization required by CoveragePkg to CoveragePkg
-- 07/2014: 2014.07a Removed initialized pointers which can lead to memory leaks.
-- 01/2015: 2015.01 Removed initialized parameter from Get
-- 04/2018: 2018.04 Minor updates to alert message
--
--
-- Copyright (c) 2010 - 2018 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use std.textio.all ;
package MessagePkg is
type MessagePType is protected
procedure Set (MessageIn : String) ;
impure function Get (ItemNumber : integer) return string ;
impure function GetCount return integer ;
impure function IsSet return boolean ;
procedure Clear ; -- clear message
procedure Deallocate ; -- clear message
end protected MessagePType ;
end package MessagePkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body MessagePkg is
-- Local Data Structure Types
type LineArrayType is array (natural range <>) of line ;
type LineArrayPtrType is access LineArrayType ;
type MessagePType is protected body
variable MessageCount : integer := 0 ;
constant INITIAL_ITEM_COUNT : integer := 16 ;
variable MaxMessageCount : integer := 0 ;
variable MessagePtr : LineArrayPtrType ;
------------------------------------------------------------
procedure Set (MessageIn : String) is
------------------------------------------------------------
variable NamePtr : line ;
variable OldMaxMessageCount : integer ;
variable OldMessagePtr : LineArrayPtrType ;
begin
MessageCount := MessageCount + 1 ;
if MessageCount > MaxMessageCount then
OldMaxMessageCount := MaxMessageCount ;
MaxMessageCount := MaxMessageCount + INITIAL_ITEM_COUNT ;
OldMessagePtr := MessagePtr ;
MessagePtr := new LineArrayType(1 to MaxMessageCount) ;
for i in 1 to OldMaxMessageCount loop
MessagePtr(i) := OldMessagePtr(i) ;
end loop ;
Deallocate( OldMessagePtr ) ;
end if ;
MessagePtr(MessageCount) := new string'(MessageIn) ;
end procedure Set ;
------------------------------------------------------------
impure function Get (ItemNumber : integer) return string is
------------------------------------------------------------
begin
if MessageCount > 0 then
if ItemNumber >= 1 and ItemNumber <= MessageCount then
return MessagePtr(ItemNumber).all ;
else
Alert(OSVVM_ALERTLOG_ID, "OSVVM.MessagePkg.Get input value out of range", FAILURE) ;
return "" ; -- error if this happens
end if ;
else
Alert(OSVVM_ALERTLOG_ID, "OSVVM.MessagePkg.Get message is not set", FAILURE) ;
return "" ; -- error if this happens
end if ;
end function Get ;
------------------------------------------------------------
impure function GetCount return integer is
------------------------------------------------------------
begin
return MessageCount ;
end function GetCount ;
------------------------------------------------------------
impure function IsSet return boolean is
------------------------------------------------------------
begin
return MessageCount > 0 ;
end function IsSet ;
------------------------------------------------------------
procedure Deallocate is -- clear message
------------------------------------------------------------
variable CurPtr : LineArrayPtrType ;
begin
for i in 1 to MessageCount loop
deallocate( MessagePtr(i) ) ;
end loop ;
MessageCount := 0 ;
MaxMessageCount := 0 ;
deallocate( MessagePtr ) ;
end procedure Deallocate ;
------------------------------------------------------------
procedure Clear is -- clear
------------------------------------------------------------
begin
Deallocate ;
end procedure Clear ;
end protected body MessagePType ;
end package body MessagePkg ; |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map(
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
a <= b;
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
a <= b;
end architecture ARCH;
|
----------------------------------------------------------------------------------
-- Author: Jonny Doin, jdoin@opencores.org
--
-- Create Date: 15:36:20 05/15/2011
-- Module Name: SPI_SLAVE - RTL
-- Project Name: SPI INTERFACE
-- Target Devices: Spartan-6
-- Tool versions: ISE 13.1
-- Description:
--
-- This block is the SPI slave interface, implemented in one single entity.
-- All internal core operations are synchronous to the external SPI clock, and follows the general SPI de-facto standard.
-- The parallel read/write interface is synchronous to a supplied system master clock, 'clk_i'.
-- Synchronization for the parallel ports is provided by input data request and write enable lines, and output data valid line.
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
-- clock domains.
--
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
-- It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), and lookahead prefetch
-- signaling ('PREFETCH').
--
-- PARALLEL WRITE INTERFACE
-- The parallel interface has a input port 'di_i' and an output port 'do_o'.
-- Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'.
-- When the core needs input data, a look ahead data request strobe , 'di_req_o' is pulsed 'PREFETCH' 'spi_sck_i'
-- cycles in advance to synchronize a user pipelined memory or fifo to present the next input data at 'di_i'
-- in time to have continuous clock at the spi bus, to allow back-to-back continuous load.
-- The data request strobe on 'di_req_o' is 2 'clk_i' clock cycles long.
-- The write to 'di_i' must occur at most one 'spi_sck_i' cycle before actual load to the core shift register, to avoid
-- race conditions at the register transfer.
-- The user circuit places data at the 'di_i' port and strobes the 'wren_i' line for one rising edge of 'clk_i'.
-- For a pipelined sync RAM, a PREFETCH of 3 cycles allows an address generator to present the new adress to the RAM in one
-- cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the interface one clock before transfer.
-- If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time.
-- The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last clock cycle,
-- if continuous transmission is intended.
-- When the interface is idle ('spi_ssel_i' is HIGH), the top bit of the latched 'di_i' port is presented at port 'spi_miso_o'.
--
-- PARALLEL WRITE PIPELINED SEQUENCE
-- =================================
-- __ __ __ __ __ __ __
-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- parallel interface clock
-- ___________
-- di_req_o ________/ \_____________________... -- 'di_req_o' asserted on rising edge of 'clk_i'
-- ______________ ___________________________...
-- di_i __old_data____X______new_data_____________... -- user circuit loads data on 'di_i' at next 'clk_i' rising edge
-- ________
-- wren_i __________________________/ \______... -- 'wren_i' enables latch on rising edge of 'clk_i'
--
--
-- PARALLEL READ INTERFACE
-- An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete
-- word is received, the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_sck_i'.
-- The signal 'do_valid_o' is strobed 3 'clk_i' clocks after, to directly drive a synchronous memory or fifo write enable.
-- 'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'clk_i'.
-- When the interface is idle, data at the 'do_o' port holds the last word received.
--
-- PARALLEL READ PIPELINED SEQUENCE
-- ================================
-- ______ ______ ______ ______
-- clk_spi_i ___/ bit1 \______/ bitN \______/bitN-1\______/bitN-2\__... -- spi base clock
-- __ __ __ __ __ __ __ __ __
-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- parallel interface clock
-- _________________ _____________________________________... -- 1) received data is transferred to 'do_buffer_reg'
-- do_o __old_data_______X__________new_data___________________... -- after last bit received, at next shift clock.
-- ____________
-- do_valid_o ________________________________/ \_________... -- 2) 'do_valid_o' strobed for 2 'clk_i' cycles
-- -- on the 3rd 'clk_i' rising edge.
--
--
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
--
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
--
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave
--
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
--
-- Copyright (C) 2011 Jonny Doin
-- -----------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.gnu.org/licenses/lgpl.txt
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2011/05/15 v0.10.0050 [JD] created the slave logic, with 2 clock domains, from SPI_MASTER module.
-- 2011/05/15 v0.15.0055 [JD] fixed logic for starting state when CPHA='1'.
-- 2011/05/17 v0.80.0049 [JD] added explicit clock synchronization circuitry across clock boundaries.
-- 2011/05/18 v0.95.0050 [JD] clock generation circuitry, with generators for all-rising-edge clock core.
-- 2011/06/05 v0.96.0053 [JD] changed async clear to sync resets.
-- 2011/06/07 v0.97.0065 [JD] added cross-clock buffers, fixed fsm async glitches.
-- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce
-- synthesis LUT overhead in Spartan-6 architecture.
-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
-- 2011/06/12 v0.97.0079 [JD] implemented wr_ack and di_req logic for state 0, and eliminated unnecessary registers reset.
-- 2011/06/17 v0.97.0079 [JD] implemented wr_ack and di_req logic for state 0, and eliminated unnecessary registers reset.
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
-- 2011/07/29 v2.00.0110 [JD] FIX: CPHA bugs:
-- - redesigned core clocking to address all CPOL and CPHA configurations.
-- - added CHANGE_EDGE to the FSM register transfer logic, to have MISO change at opposite
-- clock phases from SHIFT_EDGE.
-- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
-- 2011/08/01 v2.01.0115 [JD] Adjusted 'do_valid_o' pulse width to be 2 'clk_i', as in the master core.
-- Simulated in iSim with the master core for continuous transmission mode.
-- 2011/08/02 v2.02.0120 [JD] Added mux for MISO at reset state, to output di(N-1) at start. This fixed a bug in first bit.
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
-- 2011/08/04 v2.02.0121 [JD] Changed minor comment bugs in the combinatorial fsm logic.
-- 2011/08/08 v2.02.0122 [JD] FIX: continuous transfer mode bug. When wren_i is not strobed prior to state 1 (last bit), the
-- sequencer goes to state 0, and then to state 'N' again. This produces a wrong bit-shift for received
-- data. The fix consists in engaging continuous transfer regardless of the user strobing write enable, and
-- sequencing from state 1 to N as long as the master clock is present. If the user does not write new
-- data, the last data word is repeated.
-- 2011/08/08 v2.02.0123 [JD] ISSUE: continuous transfer mode bug, for ignored 'di_req' cycles. Instead of repeating the last data word,
-- the slave will send (others => '0') instead.
-- 2011/08/28 v2.02.0126 [JD] ISSUE: the miso_o MUX that preloads tx_bit when slave is desselected will glitch for CPHA='1'.
-- FIX: added a registered drive for the MUX select that will transfer the tx_reg only after the first tx_reg update.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
-- ====
--
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity spi_slave is
Generic (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 3); -- prefetch lookahead cycles
Port (
clk_i : in std_logic := 'X'; -- internal interface clock (clocks di/do registers)
spi_ssel_i : in std_logic := 'X'; -- spi bus slave select line
spi_sck_i : in std_logic := 'X'; -- spi bus sck clock (clocks the shift register core)
spi_mosi_i : in std_logic := 'X'; -- spi bus mosi input
spi_miso_o : out std_logic := 'X'; -- spi bus spi_miso_o output
di_req_o : out std_logic; -- preload lookahead data request line
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i)
wren_i : in std_logic := 'X'; -- user data write enable
wr_ack_o : out std_logic; -- write acknowledge
do_valid_o : out std_logic; -- do_o data valid strobe, valid during one clk_i rising edge.
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i)
--- debug ports: can be removed for the application circuit ---
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_next_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
end spi_slave;
--================================================================================================================
-- SYNTHESIS CONSIDERATIONS
-- ========================
-- There are several output ports that are used to simulate and verify the core operation.
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
-- circuitry.
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
-- synthesis tool will remove the receive logic from the generated circuitry.
-- Alternatively, you can remove these ports and related circuitry once the core is verified and
-- integrated to your circuit.
--================================================================================================================
architecture rtl of spi_slave is
-- constants to control FlipFlop synthesis
constant SHIFT_EDGE : std_logic := (CPOL xnor CPHA); -- MOSI data is captured and shifted at this SCK edge
constant CHANGE_EDGE : std_logic := (CPOL xor CPHA); -- MISO data is updated at this SCK edge
------------------------------------------------------------------------------------------
-- GLOBAL RESET:
-- all signals are initialized to zero at GSR (global set/reset) by giving explicit
-- initialization values at declaration. This is needed for all Xilinx FPGAs, and
-- especially for the Spartan-6 and newer CLB architectures, where a local reset can
-- reduce the usability of the slice registers, due to the need to share the control
-- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
-- By using GSR for the initialization, and reducing RESET local init to the really
-- essential, the model achieves better LUT/FF packing and CLB usability.
------------------------------------------------------------------------------------------
-- internal state signals for register and combinatorial stages
signal state_next : natural range N downto 0 := 0; -- state 0 is idle state
signal state_reg : natural range N downto 0 := 0; -- state 0 is idle state
-- shifter signals for register and combinatorial stages
signal sh_next : std_logic_vector (N-1 downto 0);
signal sh_reg : std_logic_vector (N-1 downto 0);
-- mosi and miso connections
signal rx_bit_next : std_logic; -- sample of MOSI input
signal tx_bit_next : std_logic;
signal tx_bit_reg : std_logic; -- drives MISO during sequential logic
signal preload_miso : std_logic; -- controls the MISO MUX
-- buffered di_i data signals for register and combinatorial stages
signal di_reg : std_logic_vector (N-1 downto 0);
-- internal wren_i stretcher for fsm combinatorial stage
signal wren : std_logic;
signal wr_ack_next : std_logic := '0';
signal wr_ack_reg : std_logic := '0';
-- buffered do_o data signals for register and combinatorial stages
signal do_buffer_next : std_logic_vector (N-1 downto 0);
signal do_buffer_reg : std_logic_vector (N-1 downto 0);
-- internal signal to flag transfer to do_buffer_reg
signal do_transfer_next : std_logic := '0';
signal do_transfer_reg : std_logic := '0';
-- internal input data request signal
signal di_req_next : std_logic := '0';
signal di_req_reg : std_logic := '0';
-- cross-clock do_valid_o logic
signal do_valid_next : std_logic := '0';
signal do_valid_A : std_logic := '0';
signal do_valid_B : std_logic := '0';
signal do_valid_C : std_logic := '0';
signal do_valid_D : std_logic := '0';
signal do_valid_o_reg : std_logic := '0';
-- cross-clock di_req_o logic
signal di_req_o_next : std_logic := '0';
signal di_req_o_A : std_logic := '0';
signal di_req_o_B : std_logic := '0';
signal di_req_o_C : std_logic := '0';
signal di_req_o_D : std_logic := '0';
signal di_req_o_reg : std_logic := '0';
begin
--=============================================================================================
-- GENERICS CONSTRAINTS CHECKING
--=============================================================================================
-- minimum word width is 8 bits
assert N >= 8
report "Generic parameter 'N' error: SPI shift register size needs to be 8 bits minimum"
severity FAILURE;
-- maximum prefetch lookahead check
assert PREFETCH <= N-5
report "Generic parameter 'PREFETCH' error: lookahead count out of range, needs to be N-5 maximum"
severity FAILURE;
--=============================================================================================
-- GENERATE BLOCKS
--=============================================================================================
--=============================================================================================
-- DATA INPUTS
--=============================================================================================
-- connect rx bit input
rx_bit_proc : rx_bit_next <= spi_mosi_i;
--=============================================================================================
-- CROSS-CLOCK PIPELINE TRANSFER LOGIC
--=============================================================================================
-- do_valid_o and di_req_o strobe output logic
-- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a
-- fixed-length delayed pulse for the output flags, at the parallel clock domain
out_transfer_proc : process ( clk_i, do_transfer_reg, di_req_reg,
do_valid_A, do_valid_B, do_valid_D,
di_req_o_A, di_req_o_B, di_req_o_D) is
begin
if clk_i'event and clk_i = '1' then -- clock at parallel port clock
-- do_transfer_reg -> do_valid_o_reg
do_valid_A <= do_transfer_reg; -- the input signal must be at least 2 clocks long
do_valid_B <= do_valid_A; -- feed it to a ripple chain of FFDs
do_valid_C <= do_valid_B;
do_valid_D <= do_valid_C;
do_valid_o_reg <= do_valid_next; -- registered output pulse
--------------------------------
-- di_req_reg -> di_req_o_reg
di_req_o_A <= di_req_reg; -- the input signal must be at least 2 clocks long
di_req_o_B <= di_req_o_A; -- feed it to a ripple chain of FFDs
di_req_o_C <= di_req_o_B;
di_req_o_D <= di_req_o_C;
di_req_o_reg <= di_req_o_next; -- registered output pulse
end if;
-- generate a 2-clocks pulse at the 3rd clock cycle
do_valid_next <= do_valid_A and do_valid_B and not do_valid_D;
di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D;
end process out_transfer_proc;
-- parallel load input registers: data register and write enable
in_transfer_proc: process (clk_i, wren_i, wr_ack_reg) is
begin
-- registered data input, input register with clock enable
if clk_i'event and clk_i = '1' then
if wren_i = '1' then
di_reg <= di_i; -- parallel data input buffer register
end if;
end if;
-- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset)
if clk_i'event and clk_i = '1' then
if wren_i = '1' then -- wren_i is the sync preset for wren
wren <= '1';
elsif wr_ack_reg = '1' then -- wr_ack is the sync reset for wren
wren <= '0';
end if;
end if;
end process in_transfer_proc;
--=============================================================================================
-- REGISTER TRANSFER PROCESSES
--=============================================================================================
-- fsm state and data registers change on spi SHIFT_EDGE
core_reg_proc : process (spi_sck_i, spi_ssel_i) is
begin
-- FFD registers clocked on SHIFT edge and cleared on idle (spi_ssel_i = 1)
-- state fsm register (fdr)
if spi_ssel_i = '1' then -- async clr
state_reg <= 0; -- state falls back to idle when slave not selected
elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on SHIFT edge, update state register
state_reg <= state_next; -- core fsm changes state with spi SHIFT clock
end if;
-- FFD registers clocked on SHIFT edge
-- rtl core registers (fd)
if spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on fsm state change, update all core registers
sh_reg <= sh_next; -- core shift register
do_buffer_reg <= do_buffer_next; -- registered data output
do_transfer_reg <= do_transfer_next; -- cross-clock transfer flag
di_req_reg <= di_req_next; -- input data request
wr_ack_reg <= wr_ack_next; -- wren ack for data load synchronization
end if;
-- FFD registers clocked on CHANGE edge and cleared on idle (spi_ssel_i = 1)
-- miso MUX preload control register (fdp)
if spi_ssel_i = '1' then -- async preset
preload_miso <= '1'; -- miso MUX sees top bit of parallel input when slave not selected
elsif spi_sck_i'event and spi_sck_i = CHANGE_EDGE then -- on CHANGE edge, change to tx_reg output
preload_miso <= spi_ssel_i; -- miso MUX sees tx_bit_reg when it is driven by SCK
end if;
-- FFD registers clocked on CHANGE edge
-- tx_bit register (fd)
if spi_sck_i'event and spi_sck_i = CHANGE_EDGE then
tx_bit_reg <= tx_bit_next; -- update MISO driver from the MSb
end if;
end process core_reg_proc;
--=============================================================================================
-- COMBINATORIAL LOGIC PROCESSES
--=============================================================================================
-- state and datapath combinatorial logic
core_combi_proc : process ( sh_reg, sh_next, state_reg, tx_bit_reg, rx_bit_next, do_buffer_reg,
do_transfer_reg, di_reg, di_req_reg, wren, wr_ack_reg) is
begin
-- all output signals are assigned to (avoid latches)
sh_next <= sh_reg; -- shift register
tx_bit_next <= tx_bit_reg; -- MISO driver
do_buffer_next <= do_buffer_reg; -- output data buffer
do_transfer_next <= do_transfer_reg; -- output data flag
wr_ack_next <= wr_ack_reg; -- write enable acknowledge
di_req_next <= di_req_reg; -- data input request
state_next <= state_reg; -- fsm control state
case state_reg is
when (N) => -- deassert 'di_rdy' and stretch do_valid
wr_ack_next <= '0'; -- acknowledge data in transfer
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
tx_bit_next <= sh_reg(N-1); -- output next MSbit
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N-1) downto (PREFETCH+3) => -- remove 'do_transfer' and shift bits
do_transfer_next <= '0'; -- reset 'do_valid' transfer signal
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
wr_ack_next <= '0'; -- remove data load ack for all but the load stages
tx_bit_next <= sh_reg(N-1); -- output next MSbit
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when (PREFETCH+2) downto 3 => -- raise prefetch 'di_req_o' signal
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
wr_ack_next <= '0'; -- remove data load ack for all but the load stages
tx_bit_next <= sh_reg(N-1); -- output next MSbit
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when 2 => -- transfer received data to do_buffer_reg on next cycle
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
wr_ack_next <= '0'; -- remove data load ack for all but the load stages
tx_bit_next <= sh_reg(N-1); -- output next MSbit
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
do_transfer_next <= '1'; -- signal transfer to do_buffer on next cycle
do_buffer_next <= sh_next; -- get next data directly into rx buffer
state_next <= state_reg - 1; -- update next state at each sck pulse
when 1 => -- transfer rx data to do_buffer and restart if new data is written
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
state_next <= N; -- next state is top bit of new data
if wren = '1' then -- load tx register if valid data present at di_reg
wr_ack_next <= '1'; -- acknowledge data in transfer
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data
else
wr_ack_next <= '0'; -- no data reload for continuous transfer mode
sh_next(N-1 downto 1) <= (others => '0'); -- clear transmit shift register
tx_bit_next <= '0'; -- send ZERO
end if;
when 0 => -- idle state: start and end of transmission
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data
wr_ack_next <= '1'; -- acknowledge data in transfer
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
do_transfer_next <= '0'; -- clear signal transfer to do_buffer
state_next <= N; -- next state is top bit of new data
when others =>
state_next <= 0; -- safe state
end case;
end process core_combi_proc;
--=============================================================================================
-- OUTPUT LOGIC PROCESSES
--=============================================================================================
-- data output processes
do_o_proc : do_o <= do_buffer_reg; -- do_o always available
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- copy registered wr_ack_o to output
-----------------------------------------------------------------------------------------------
-- MISO driver process: preload top bit of parallel data to MOSI at reset
-----------------------------------------------------------------------------------------------
-- this is a MUX that selects the combinatorial next tx bit at reset, and the registered tx bit
-- at sequential operation. The mux gives us a preload of the first bit, simplifying the shifter logic.
spi_miso_o_proc: process (preload_miso, tx_bit_reg, di_reg) is
begin
if preload_miso = '1' then
spi_miso_o <= di_reg(N-1); -- copy top bit of parallel data at reset
else
spi_miso_o <= tx_bit_reg; -- copy top bit of shifter at sequential operation
end if;
end process spi_miso_o_proc;
--=============================================================================================
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- these signals are useful for verification, and can be deleted after debug.
do_transfer_proc: do_transfer_o <= do_transfer_reg;
state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4)); -- export internal state to debug
rx_bit_next_proc: rx_bit_next_o <= rx_bit_next;
wren_o_proc: wren_o <= wren;
sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug
end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1459.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01459ent IS
END c08s07b00x00p04n01i01459ent;
ARCHITECTURE c08s07b00x00p04n01i01459arch OF c08s07b00x00p04n01i01459ent IS
begin
transmit: process
variable delay : integer := 1;
variable m : integer := 0;
variable n : integer := 0;
begin
if delay = 0 then
m := 1;
elsif delay = 4 then
n := 1;
end if;
assert NOT((m = 0) and (n = 0))
report "***PASSED TEST: c08s07b00x00p04n01i01459"
severity NOTE;
assert (m = 0) and (n = 0)
report "***FAILED TEST: c08s07b00x00p04n01i01459 - all conditions should be evaluated and yield FALSE"
severity ERROR;
wait;
end process transmit;
END c08s07b00x00p04n01i01459arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1459.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01459ent IS
END c08s07b00x00p04n01i01459ent;
ARCHITECTURE c08s07b00x00p04n01i01459arch OF c08s07b00x00p04n01i01459ent IS
begin
transmit: process
variable delay : integer := 1;
variable m : integer := 0;
variable n : integer := 0;
begin
if delay = 0 then
m := 1;
elsif delay = 4 then
n := 1;
end if;
assert NOT((m = 0) and (n = 0))
report "***PASSED TEST: c08s07b00x00p04n01i01459"
severity NOTE;
assert (m = 0) and (n = 0)
report "***FAILED TEST: c08s07b00x00p04n01i01459 - all conditions should be evaluated and yield FALSE"
severity ERROR;
wait;
end process transmit;
END c08s07b00x00p04n01i01459arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1459.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01459ent IS
END c08s07b00x00p04n01i01459ent;
ARCHITECTURE c08s07b00x00p04n01i01459arch OF c08s07b00x00p04n01i01459ent IS
begin
transmit: process
variable delay : integer := 1;
variable m : integer := 0;
variable n : integer := 0;
begin
if delay = 0 then
m := 1;
elsif delay = 4 then
n := 1;
end if;
assert NOT((m = 0) and (n = 0))
report "***PASSED TEST: c08s07b00x00p04n01i01459"
severity NOTE;
assert (m = 0) and (n = 0)
report "***FAILED TEST: c08s07b00x00p04n01i01459 - all conditions should be evaluated and yield FALSE"
severity ERROR;
wait;
end process transmit;
END c08s07b00x00p04n01i01459arch;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
use work.support_pkg.all;
--=================================================================================================
--=================================================================================================
package transaction_pkg is
--==========================================================================================
-- t_operation
-- - VVC and BFM operations
--==========================================================================================
type t_operation is (
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- VVC local
TRANSMIT,
RECEIVE,
EXPECT
);
-- Constants for the maximum sizes to use in this VVC.
-- You can create VVCs with smaller sizes than these constants, but not larger.
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
--==========================================================================================
--
-- Transaction info types, constants and global signal
--
--==========================================================================================
-- Transaction status
type t_transaction_status is (INACTIVE, IN_PROGRESS, FAILED, SUCCEEDED);
constant C_TRANSACTION_STATUS_DEFAULT : t_transaction_status := INACTIVE;
-- VVC Meta
type t_vvc_meta is record
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : integer;
end record;
constant C_VVC_META_DEFAULT : t_vvc_meta := (
msg => (others => ' '),
cmd_idx => -1
);
-- Base transaction
type t_base_transaction is record
operation : t_operation;
ethernet_frame : t_ethernet_frame;
vvc_meta : t_vvc_meta;
transaction_status : t_transaction_status;
end record;
constant C_BASE_TRANSACTION_SET_DEFAULT : t_base_transaction := (
operation => NO_OPERATION,
ethernet_frame => C_ETHERNET_FRAME_DEFAULT,
vvc_meta => C_VVC_META_DEFAULT,
transaction_status => C_TRANSACTION_STATUS_DEFAULT
);
-- Transaction group
type t_transaction_group is record
bt : t_base_transaction;
end record;
constant C_TRANSACTION_GROUP_DEFAULT : t_transaction_group := (
bt => C_BASE_TRANSACTION_SET_DEFAULT
);
subtype t_sub_channel is t_channel range RX to TX;
-- Global transaction info trigger signal
type t_ethernet_transaction_trigger_array is array (t_sub_channel range <>, natural range <>) of std_logic;
signal global_ethernet_vvc_transaction_trigger : t_ethernet_transaction_trigger_array(t_sub_channel'left to t_sub_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) :=
(others => (others => '0'));
-- Shared transaction info variable
type t_ethernet_transaction_group_array is array (t_sub_channel range <>, natural range <>) of t_transaction_group;
shared variable shared_ethernet_vvc_transaction_info : t_ethernet_transaction_group_array(t_sub_channel'left to t_sub_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) :=
(others => (others => C_TRANSACTION_GROUP_DEFAULT));
end package transaction_pkg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1284.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01284ent IS
port (X : in BIT; COUT : out BIT);
END c08s04b00x00p04n01i01284ent;
ARCHITECTURE c08s04b00x00p04n01i01284arch OF c08s04b00x00p04n01i01284ent IS
signal S1 : BIT;
BEGIN
TESTING: PROCESS
BEGIN
X <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01284 - A port whose mode is "IN" or "LINKAGE" can not be on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01284arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1284.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01284ent IS
port (X : in BIT; COUT : out BIT);
END c08s04b00x00p04n01i01284ent;
ARCHITECTURE c08s04b00x00p04n01i01284arch OF c08s04b00x00p04n01i01284ent IS
signal S1 : BIT;
BEGIN
TESTING: PROCESS
BEGIN
X <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01284 - A port whose mode is "IN" or "LINKAGE" can not be on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01284arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1284.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01284ent IS
port (X : in BIT; COUT : out BIT);
END c08s04b00x00p04n01i01284ent;
ARCHITECTURE c08s04b00x00p04n01i01284arch OF c08s04b00x00p04n01i01284ent IS
signal S1 : BIT;
BEGIN
TESTING: PROCESS
BEGIN
X <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01284 - A port whose mode is "IN" or "LINKAGE" can not be on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01284arch;
|
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_nexys4d_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-04 838 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
|
architecture RTL of ENTITY1 is
subtype read_size is integer range 0 to 9;
subtype write_size is integer range 0 to 9;
signal read : read_size;
signal write : write_size;
constant read_sz : read_size := 8;
constant write_sz : write_size := 1;
begin
end architecture RTL;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/31/2017 03:31:33 PM
-- Design Name:
-- Module Name: Debug_Controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
entity Debug_Controller is
port (clk,RST: in STD_LOGIC;
HALT: out STD_LOGIC;
REGGIE: in regfile_arr;
PC_IN: in doubleword;
UART_RXD: in STD_LOGIC;
UART_TXD : out STD_LOGIC);
end Debug_Controller;
architecture Behavioral of Debug_Controller is
component UART_RX_CTRL is
port (UART_RX: in STD_LOGIC;
CLK: in STD_LOGIC;
DATA: out STD_LOGIC_VECTOR (7 downto 0);
READ_DATA: out STD_LOGIC;
RESET_READ: in STD_LOGIC
);
end component;
component UART_TX_CTRL is
port( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end component;
-- Types
type CHAR_ARRAY is array (integer range<>) of std_logic_vector(7 downto 0);
type UART_STATE_TYPE is (IDLE, RECEIVE, UNPAUSE, DECODE, REGISTERS, PC, STEP, STEP_HI, STEP_LO, SEND_CHAR, REGFILE, SEND_CHAR_2, SEND_CHAR_3, SEND_CHAR_4, WAIT_CHAR, KEEP_WAITING_CHAR, LD_REGISTERS_STR, RESET_LO, RESET_HI);
type BOUNDS is array (integer range<>) of integer;
-- Constants
constant MAX_STR_LEN : integer := 750;
constant MAX_REGISTER_LEN : integer := 23;
constant RESET_CNTR_MAX : std_logic_vector(17 downto 0) := "110000110101000000";-- 100,000,000 * 0.002 = 200,000 = clk cycles per 2 ms
-- Signals
signal uart_curr_state, uart_next_state : UART_STATE_TYPE := idle;
signal uartRdy, uartSend ,uartTX: std_logic;
signal uartData: std_logic_vector(7 downto 0);
signal sendStr : CHAR_ARRAY(0 to (MAX_STR_LEN - 1)) := ( others => (others => '0'));
signal reset_cntr : std_logic_vector (17 downto 0) := (others=>'0');
-- String counters
signal reggie_counter : integer := 0;
signal reggie_str_counter : integer := 12;
signal reggie_counter_counter : integer := 0;
signal strEnd, strIndex: natural := 0;
signal strConcatCtr: integer := 0;
signal pc_str_counter: integer := 0;
signal pc_reg: doubleword := (others => '0');
-- CPU halt interface
signal halt_l : std_logic := '1';
-- UART RX and TX signals
signal uart_data_in: STD_LOGIC_VECTOR(7 DOWNTO 0);
signal data_available, reset_read: STD_LOGIC;
signal rx_str : CHAR_ARRAY(30 DOWNTO 0);
signal rx_str_ctr : integer := 0;
signal d_clk: std_logic := '0';
begin
DEBUG_UART_TX: UART_TX_CTRL port map(SEND => uartSend,
DATA => uartData,
CLK => CLK,
READY => uartRdy,
UART_TX => UART_TXD );
DEBUG_UART_RX: UART_RX_CTRL
port map(
UART_RX => UART_RXD,
CLK => CLK,
DATA => uart_data_in,
READ_DATA => data_available,
RESET_READ => reset_read
);
--State Machine transition
DEBUG_FSM: process(clk, rst) begin
if(rst = '1') then
uart_curr_state <= IDLE;
elsif(rising_edge(clk)) then
uart_curr_state <= uart_next_state;
end if;
end process;
HALT <= halt_l;
-- Generate the debug clock d_clk
D_CLK_GEN: process(clk) begin
if(rising_edge(clk)) then
if(halt_l = '0') then
d_clk <= d_clk xor '1';
end if;
end if;
end process;
DEBUG_FSM_TRANSITION: process(clk, rst) begin
if(rst = '1') then
strConcatCtr <= 0;
reggie_str_counter <= 0;
reset_read <= '1';
uart_next_state <= IDLE;
strIndex <= 0;
halt_l <= '1';
elsif(rising_edge(clk)) then
case uart_curr_state is
-- State IDLE: Nothing happening
when IDLE =>
reggie_counter_counter <= 0;
reggie_str_counter <= 0;
strConcatCtr <= 0;
strEnd <= 735;
uartSend <= '0';
strIndex <= 0;
reset_read <= '0';
reggie_counter <= 0;
pc_str_counter <= 0;
uart_next_state <= IDLE;
-- Default go to IDLE
if(data_available = '1' AND uartRdy = '1' ) then -- If we have data and not outputing anything
rx_str(0) <= uart_data_in; -- Save the data
uart_next_state <= DECODE;
end if;
-- State DECODE: Decode what function the user is accessing
when DECODE =>
if(rx_str(0) = X"72") then
uart_next_state <= REGFILE;
elsif(rx_str(0) = X"73") then
uart_next_state <= STEP;
elsif(rx_str(0) = X"75") then
uart_next_state <= UNPAUSE;
elsif(rx_str(0) = X"70") then
uart_next_state <= PC;
strEnd <= 23;
pc_reg <= PC_IN;
else
uart_next_state <= IDLE;
end if;
-- State REGFILE: Print out the entire register file
-- TODO: change this to make it less crappy
-- reggie_counter indicates how many registers should be printed
-- reggie_counter_counter is the length of the string printed per register
when REGFILE =>
uart_next_state <= REGFILE;
if( reggie_counter_counter = 23) then
reggie_counter <= reggie_counter + 1;
end if;
if(reggie_counter >= 31) then
uart_next_state <= REGISTERS;
else
reggie_str_counter <= reggie_str_counter + 1;
case reggie_str_counter is
when 0 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"72";
reggie_counter_counter <= 0;
when 1 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(std_logic_vector(to_unsigned(reggie_counter, 4)));
reggie_counter_counter <= 1;
when 2 => if(reggie_counter = 32) then
sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(X"2");
elsif(reggie_counter > 15) then
sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(X"1");
else
sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(X"0");
end if;
reggie_counter_counter <= 2;
when 3 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"78";
reggie_counter_counter <= 2;
when 4 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(63 downto 60));
reggie_counter_counter <= 3;
when 5 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(59 downto 56));
reggie_counter_counter <= 4;
when 6 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(55 downto 52));
reggie_counter_counter <= 5;
when 7 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(51 downto 48));
reggie_counter_counter <= 6;
when 8 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(47 downto 44));
reggie_counter_counter <= 7;
when 9 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(43 downto 40));
reggie_counter_counter <= 8;
when 10 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(39 downto 36));
reggie_counter_counter <= 9;
when 11 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(35 downto 32));
reggie_counter_counter <= 10;
when 12 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(31 downto 28));
reggie_counter_counter <= 11;
when 13 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(27 downto 24));
reggie_counter_counter <= 12;
when 14 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(23 downto 20));
reggie_counter_counter <= 13;
when 15 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(19 downto 16));
reggie_counter_counter <= 14;
when 16 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(15 downto 12));
reggie_counter_counter <= 15;
when 17 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(11 downto 8));
reggie_counter_counter <= 16;
when 18 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(7 downto 4));
reggie_counter_counter <= 17;
when 19 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(3 downto 0));
reggie_counter_counter <= 18;
when 20 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"20";
reggie_counter_counter <= 19;
when 21 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 20;
when 22 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 21;
when 23 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 22;
when 24 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 23;
reggie_str_counter <= 0;
when others => sendStr(24) <= X"20";
end case;
end if;
when PC =>
uart_next_state <= PC;
if(pc_str_counter > 21) then
uart_next_state <= SEND_CHAR;
else
pc_str_counter <= pc_str_counter + 1;
case pc_str_counter is
when 1 => sendStr(pc_str_counter) <= X"50";
when 2 => sendStr(pc_str_counter) <= X"43";
when 3 => sendStr(pc_str_counter) <= X"3A";
when 4 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(63 downto 60));
when 5 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(59 downto 56));
when 6 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(55 downto 52));
when 7 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(51 downto 48));
when 8 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(47 downto 44));
when 9 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(43 downto 40));
when 10 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(39 downto 36));
when 11 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(35 downto 32));
when 12 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(31 downto 28));
when 13 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(27 downto 24));
when 14 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(23 downto 20));
when 15 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(19 downto 16));
when 16 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(15 downto 12));
when 17 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(11 downto 8));
when 18 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(7 downto 4));
when 19 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(3 downto 0));
when 20 => sendStr(pc_str_counter) <= X"20";
when 21 => sendStr(pc_str_counter) <= X"0A";
when 22 => sendStr(pc_str_counter) <= X"0A";
when 23 => sendStr(pc_str_counter) <= X"0A";
when 24 => sendStr(pc_str_counter) <= X"0A";
when others => sendStr(24) <= X"20";
end case;
end if;
-- State STEP: Step one clock cycle
-- halt_l is 0, allows the CPU to continue for one clock cycle
when STEP =>
halt_l <= '0';
uart_next_state <= STEP_HI;
-- State STEP_HI: One step done
-- halt_l is 1, halts the processor
when STEP_HI =>
halt_l <= '1';
uart_next_state <= STEP_LO;
-- State STEP_LO: One step done
-- If the user wants to skip 2 clock cycles instead of one,
-- STEP_HI can set halt_l to 0 and STEP_LO can be set to 1
-- This can be
when STEP_LO =>
halt_l <= '1';
uart_next_state <= RESET_LO;
-- State REGISTERS: Once the strings are prepared, send the characters
when REGISTERS =>
uart_next_state <= SEND_CHAR;
-- State SEND_CHAR: Tell the UART controller to print things
when SEND_CHAR =>
strIndex <= strIndex + 1;
uartSend <= '1';
uartData <= sendStr(strIndex);
uart_next_state <= WAIT_CHAR;
-- State WAIT_CHAR: Checks if the entirety of the string
-- has been sent
when WAIT_CHAR =>
uart_next_state <= WAIT_CHAR;
if(strEnd <= strIndex) then
uart_next_state <= RESET_LO;
elsif(uartRdy = '1') then
uart_next_state <= SEND_CHAR;
end if;
-- State RESET_LO: Resets the RX_UART to flush whatever it
-- had as an input to prepare for the next function
when RESET_LO =>
reset_read <= '1';
uart_next_state <= RESET_HI;
-- State RESET_HI:
when RESET_HI =>
reset_read <= '0';
uart_next_state <= IDLE;
-- State UNPAUSE: Lifts the halt_l, allowing the CPU to run normally
when UNPAUSE =>
halt_l <= '0';
uart_next_state <= RESET_LO;
when OTHERS =>
uart_next_state <= IDLE;
end case;
end if;
end process;
end Behavioral;
|
-- *************************
-- Message Manager
-- (Prototype)
--
-- Written by Jason Agron
-- *************************
-- FIXMEs:
-- * Add in support for full-handshaking (user -> queue -> back to user)
-- * Change underlying queue structure to be faster (eliminate useless states)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity message_manager is
generic(
START_WITH_TOKEN : integer := 0;
QUEUE_ADDRESS_WIDTH : integer := 9;
DATA_WIDTH : integer := 32;
CHANNEL_ID_WIDTH : integer := 8;
SENDER_ID_WIDTH : integer := 8
);
port(
-- System-Level Control Ports
clk : in std_logic;
reset : in std_logic;
-- User Interface Ports
i_request : in std_logic;
i_user_opcode : in std_logic_vector(0 to 7);
i_user_data : in std_logic_vector(0 to DATA_WIDTH-1);
i_user_channel : in std_logic_vector(0 to CHANNEL_ID_WIDTH-1);
i_user_sender : in std_logic_vector(0 to SENDER_ID_WIDTH-1);
o_user_data : out std_logic_vector(0 to DATA_WIDTH-1);
o_user_channel : out std_logic_vector(0 to CHANNEL_ID_WIDTH-1);
o_user_sender : out std_logic_vector(0 to SENDER_ID_WIDTH-1);
o_busy : out std_logic;
o_send_ready : out std_logic;
o_recv_ready : out std_logic;
-- System Ports - Incoming Packet Interface
i_packet_data : in std_logic_vector(0 to DATA_WIDTH-1);
i_packet_channel : in std_logic_vector(0 to CHANNEL_ID_WIDTH-1);
i_packet_sender : in std_logic_vector(0 to SENDER_ID_WIDTH-1);
i_packet_valid : in std_logic;
-- System Ports -- Token Interface
i_token : in std_logic;
o_token : out std_logic;
-- System Ports - Outgoing Packet Interface
o_packet_data : out std_logic_vector(0 to DATA_WIDTH-1);
o_packet_channel : out std_logic_vector(0 to CHANNEL_ID_WIDTH-1);
o_packet_sender : out std_logic_vector(0 to SENDER_ID_WIDTH-1);
o_packet_valid : out std_logic
);
end entity message_manager;
architecture IMP of message_manager is
-- *****************************
-- Function Definitions
-- *****************************
-- Form a packet from it's components
function form_packet(
channel : std_logic_vector(0 to CHANNEL_ID_WIDTH - 1);
sender : std_logic_vector(0 to SENDER_ID_WIDTH - 1);
data : std_logic_vector(0 to DATA_WIDTH - 1)
) return std_logic_vector is
begin
return (channel & sender & data);
end function form_packet;
-- Extract data field from a formed packet
function get_packet_data(formed_packet : std_logic_vector(0 to CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH - 1)) return std_logic_vector is
begin
return formed_packet((CHANNEL_ID_WIDTH + SENDER_ID_WIDTH) to (CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH - 1));
end function get_packet_data;
-- Extract sender field from a formed packet
function get_packet_sender(formed_packet : std_logic_vector(0 to CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH - 1)) return std_logic_vector is
begin
return formed_packet((CHANNEL_ID_WIDTH) to (CHANNEL_ID_WIDTH + SENDER_ID_WIDTH - 1));
end function get_packet_sender;
-- Extract channel field from a formed packet
function get_packet_channel(formed_packet : std_logic_vector(0 to CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH - 1)) return std_logic_vector is
begin
return formed_packet(0 to (CHANNEL_ID_WIDTH - 1));
end function get_packet_channel;
-- *****************************
-- Component declaration for queue IP
-- *****************************
COMPONENT fast_queue
generic(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
PORT(
clk : in std_logic;
rst : in std_logic;
add_busy : out std_logic;
remove_busy : out std_logic;
add : in std_logic;
remove : in std_logic;
entryToAdd : in std_logic_vector(0 to DATA_BITS-1);
head : out std_logic_vector(0 to DATA_BITS-1);
headValid : out std_logic;
full : out std_logic;
empty : out std_logic
);
END COMPONENT;
-- **********************************
-- Constant Defintions
-- **********************************
-- Message Manager Opcodes
constant RESET_SEND_QUEUE : std_logic_vector(0 to 7) := x"01";
constant RESET_RECV_QUEUE : std_logic_vector(0 to 7) := x"02";
constant REGISTER_CHANNEL : std_logic_vector(0 to 7) := x"03";
constant SEND_PACKET : std_logic_vector(0 to 7) := x"04";
constant RECV_PACKET : std_logic_vector(0 to 7) := x"05";
constant REGISTER_SENDER : std_logic_vector(0 to 7) := x"06";
constant GET_QUEUE_STATUS : std_logic_vector(0 to 7) := x"07";
-- Pseudonyms for token values
constant NO_TOKEN : std_logic := '0';
constant HAS_TOKEN : std_logic := '1';
-- Pseudonyms for token counter values
constant COUNTER_OUT_OF_TIME : std_logic_vector(0 to QUEUE_ADDRESS_WIDTH -1) := (others => '0');
constant COUNTER_RESET_VALUE : std_logic_vector(0 to QUEUE_ADDRESS_WIDTH -1) := (others => '1');
-- **********************************
-- Internal registers and signals
-- **********************************
-- Registers to hold channel to listen for and sender ID
signal listen_channel, listen_channel_next : std_logic_vector(0 to CHANNEL_ID_WIDTH - 1);
signal sender_id, sender_id_next : std_logic_vector(0 to SENDER_ID_WIDTH - 1);
-- Registers used to detect incoming (valid) packets
signal i_packet_valid_d1, incoming_packet : std_logic;
-- Token register and token down counter
signal token_register : std_logic;
signal token_counter : std_logic_vector(0 to QUEUE_ADDRESS_WIDTH - 1); -- Decrementing token counter (limits the number of packets that can be sent at once)
-- Signals used to connect SEND QUEUE
signal send_queue_reset : std_logic;
signal send_queue_add : std_logic;
signal send_queue_add_busy, send_queue_remove_busy : std_logic;
signal send_queue_remove : std_logic;
signal send_queue_entry_to_add, send_queue_entry_to_add_next : std_logic_vector(0 to CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH - 1);
signal send_queue_head : std_logic_vector(0 to CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH - 1);
signal send_queue_head_valid : std_logic;
signal send_queue_full : std_logic;
signal send_queue_empty : std_logic;
-- Signals used to connect RECV QUEUE
signal recv_queue_reset : std_logic;
signal recv_queue_add : std_logic;
signal recv_queue_add_busy, recv_queue_remove_busy : std_logic;
signal recv_queue_remove : std_logic;
signal recv_queue_entry_to_add : std_logic_vector(0 to CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH - 1);
signal recv_queue_head : std_logic_vector(0 to CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH - 1);
signal recv_queue_head_valid : std_logic;
signal recv_queue_full : std_logic;
signal recv_queue_empty : std_logic;
-- Signals used to return data to user (b/c outputs are registered)
signal out_busy, out_busy_next : std_logic;
signal out_user_data, out_user_data_next : std_logic_vector(0 to DATA_WIDTH-1);
signal out_user_channel, out_user_channel_next : std_logic_vector(0 to CHANNEL_ID_WIDTH-1);
signal out_user_sender, out_user_sender_next : std_logic_vector(0 to SENDER_ID_WIDTH-1);
-- **************************
-- State definition for FSM
-- **************************
type state_type is (
IDLE,
RESET_MM,
CMD_RESET_SEND_QUEUE,
CMD_RESET_RECV_QUEUE,
CMD_REGISTER_CHANNEL,
CMD_REGISTER_SENDER,
CMD_SEND_PACKET,
CMD_RECV_PACKET,
CMD_GET_QUEUE_STATUS
);
signal current_state, next_state : state_type := IDLE;
begin
-- ********************************************************
-- Instantiations of receive (RECV) and send (SEND) queues
-- ********************************************************
SEND_QUEUE : fast_queue
generic map(
ADDRESS_BITS => QUEUE_ADDRESS_WIDTH,
DATA_BITS => (CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH)
)
port map(
clk => clk,
rst => send_queue_reset,
add_busy => send_queue_add_busy,
remove_busy => send_queue_remove_busy,
add => send_queue_add,
remove => send_queue_remove,
entryToAdd => send_queue_entry_to_add,
head => send_queue_head,
headValid => send_queue_head_valid,
full => send_queue_full,
empty => send_queue_empty
);
RECV_QUEUE : fast_queue
generic map(
ADDRESS_BITS => QUEUE_ADDRESS_WIDTH,
DATA_BITS => (CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH)
)
port map(
clk => clk,
rst => recv_queue_reset,
add_busy => recv_queue_add_busy,
remove_busy => recv_queue_remove_busy,
add => recv_queue_add,
remove => recv_queue_remove,
entryToAdd => recv_queue_entry_to_add,
head => recv_queue_head,
headValid => recv_queue_head_valid,
full => recv_queue_full,
empty => recv_queue_empty
);
-- ************************************************************
-- Set up status signals for user
-- ************************************************************
o_send_ready <= (not out_busy) and (not send_queue_full) and (not send_queue_add_busy);
o_recv_ready <= (not out_busy) and (recv_queue_head_valid);
o_user_data <= out_user_data;
o_user_channel <= out_user_channel;
o_user_sender <= out_user_sender;
o_busy <= out_busy;
-- ************************************************************
-- Process: USER_COMMAND_CONTROLLER
-- Purpose: FSM Controller for processing user-driven commands
-- ************************************************************
USER_COMMAND_CONTROLLER : process (clk) is
begin
if (clk'event and clk = '1') then
if (reset = '1') then
-- Reset all FSM variables
current_state <= RESET_MM;
listen_channel <= (others => '0');
send_queue_entry_to_add <= (others => '0');
out_user_data <= (others => '0');
out_user_channel <= (others => '0');
out_user_sender <= (others => '0');
out_busy <= '0';
sender_id <= (others => '0');
else
-- Transition all FSM variables
current_state <= next_state;
listen_channel <= listen_channel_next;
send_queue_entry_to_add <= send_queue_entry_to_add_next;
out_user_data <= out_user_data_next;
out_user_channel <= out_user_channel_next;
out_user_sender <= out_user_sender_next;
out_busy <= out_busy_next;
sender_id <= sender_id_next;
end if;
end if;
end process USER_COMMAND_CONTROLLER;
-- *****************************************************
-- Process: USER_COMMAND_CONTROLLER_LOGIC
-- Purpose: FSM Logic to processs user-driven commands
-- *****************************************************
USER_COMMAND_CONTROLLER_LOGIC : process (
current_state, listen_channel, send_queue_entry_to_add, i_request,
i_user_opcode, i_user_channel, i_user_sender, i_user_data, recv_queue_head,
sender_id, send_queue_empty, send_queue_full, send_queue_add_busy,
send_queue_remove_busy, recv_queue_empty, recv_queue_full, recv_queue_add_busy,
recv_queue_remove_busy, send_queue_head_valid, recv_queue_head_valid, out_user_data, out_user_channel, out_user_sender
) is
begin
-- Set default values for FSM signals
send_queue_add <= '0';
send_queue_reset <= '0';
send_queue_entry_to_add_next <= send_queue_entry_to_add;
recv_queue_reset <= '0';
recv_queue_remove <= '0';
--out_user_data_next <= (others => '0');
--out_user_channel_next <= (others => '0');
--out_user_sender_next <= (others => '0');
out_user_data_next <= out_user_data;
out_user_channel_next <= out_user_channel;
out_user_sender_next <= out_user_sender;
out_busy_next <= '0';
listen_channel_next <= listen_channel;
sender_id_next <= sender_id;
-- FSM Logic:
case (current_state) is
-- ************************
-- IDLE State
-- ************************
when IDLE =>
-- Check if a request is coming in and check the opcode...
if (i_request = '1') then
case (i_user_opcode) is
when RESET_SEND_QUEUE =>
send_queue_reset <= '1';
next_state <= CMD_RESET_SEND_QUEUE;
out_busy_next <= '1';
when RESET_RECV_QUEUE =>
recv_queue_reset <= '1';
next_state <= CMD_RESET_RECV_QUEUE;
out_busy_next <= '1';
when REGISTER_CHANNEL =>
listen_channel_next <= i_user_channel;
next_state <= CMD_REGISTER_CHANNEL;
out_busy_next <= '1';
when REGISTER_SENDER =>
sender_id_next <= i_user_sender;
next_state <= CMD_REGISTER_SENDER;
out_busy_next <= '1';
when SEND_PACKET =>
-- send_queue_entry_to_add_next <= form_packet(i_user_channel, sender_id, i_user_data); -- Use existing senderID register
send_queue_entry_to_add_next <= form_packet(i_user_channel, i_user_sender, i_user_data); -- Use fresh senderID coming from user
next_state <= CMD_SEND_PACKET;
out_busy_next <= '1';
when RECV_PACKET =>
out_user_data_next <= get_packet_data(recv_queue_head);
out_user_channel_next <= get_packet_channel(recv_queue_head);
out_user_sender_next <= get_packet_sender(recv_queue_head);
next_state <= CMD_RECV_PACKET;
out_busy_next <= '1';
when GET_QUEUE_STATUS =>
next_state <= CMD_GET_QUEUE_STATUS;
out_busy_next <= '1';
when others =>
next_state <= IDLE;
out_busy_next <= '1';
end case;
-- If no request is coming in then just stay in the IDLE state
else
next_state <= IDLE;
out_busy_next <= '0';
end if;
-- ************************
-- RESET SEND QUEUE
-- ************************
when CMD_RESET_SEND_QUEUE =>
send_queue_reset <= '1';
out_busy_next <= '1';
next_state <= IDLE;
-- ************************
-- RESET RECV QUEUE
-- ************************
when CMD_RESET_RECV_QUEUE =>
recv_queue_reset <= '1';
out_busy_next <= '1';
next_state <= IDLE;
-- ************************
-- REGISTER CHANNEL ID
-- ************************
when CMD_REGISTER_CHANNEL =>
out_busy_next <= '0';
next_state <= IDLE;
-- ************************
-- REGISTER SENDER ID
-- ************************
when CMD_REGISTER_SENDER =>
out_busy_next <= '0';
next_state <= IDLE;
-- ************************
-- SEND PACKET
-- ************************
when CMD_SEND_PACKET =>
send_queue_add <= '1';
out_busy_next <= '1';
next_state <= IDLE;
-- ************************
-- RECEIVE PACKET
-- ************************
when CMD_RECV_PACKET =>
out_user_data_next <= get_packet_data(recv_queue_head);
out_user_channel_next <= get_packet_channel(recv_queue_head);
out_user_sender_next <= get_packet_sender(recv_queue_head);
recv_queue_remove <= '1';
out_busy_next <= '1';
next_state <= IDLE;
-- ************************
-- GET QUEUE STATUS
-- ************************
when CMD_GET_QUEUE_STATUS =>
out_user_data_next <= x"00000" & "00" &
(send_queue_empty & send_queue_full & send_queue_add_busy & send_queue_remove_busy & send_queue_head_valid) &
(recv_queue_empty & recv_queue_full & recv_queue_add_busy & recv_queue_remove_busy & recv_queue_head_valid);
out_busy_next <= '0';
next_state <= IDLE;
-- ************************
-- RESET MESSAGE MANAGER
-- ************************
when RESET_MM =>
send_queue_reset <= '1';
recv_queue_reset <= '1';
out_busy_next <= '1';
next_state <= IDLE;
when others =>
-- Should never come here!!!!
next_state <= RESET_MM;
end case;
end process USER_COMMAND_CONTROLLER_LOGIC;
-- *****************************************************
-- Process: TOKEN_ANALYSIS
-- Purpose: To capture and process tokens as needed
-- *****************************************************
TOKEN_ANALYSIS : process (clk) is
begin
if (clk'event and clk = '1') then
-- Reset all token logic
if (reset = '1') then
-- Implement the initial token holder logic
if (START_WITH_TOKEN = 1) then
token_register <= HAS_TOKEN;
else
token_register <= NO_TOKEN;
end if;
-- Reset token counter and output token value
token_counter <= COUNTER_RESET_VALUE;
o_token <= NO_TOKEN;
else
-- If we have the token and it is time to give it up
if (token_register = HAS_TOKEN and token_counter = COUNTER_OUT_OF_TIME) then
-- Reset the counter
token_counter <= COUNTER_RESET_VALUE;
-- Give up the token
token_register <= NO_TOKEN;
-- Transfer the token down the line
o_token <= HAS_TOKEN;
-- If we have the token, but we don't need the token (nothing in the send queue)
elsif (token_register = HAS_TOKEN and send_queue_empty = '1') then
-- Keep the token counter at it's reset value
token_counter <= COUNTER_RESET_VALUE;
-- Give up the token
token_register <= NO_TOKEN;
-- Transfer the token down the line
o_token <= HAS_TOKEN;
-- If we have the token and it is not yet time to give it up
elsif (token_register = HAS_TOKEN) then
-- Decrement the token counter
token_counter <= token_counter - 1;
-- Keep the token
token_register <= HAS_TOKEN;
-- Don't pass the token down the line
o_token <= NO_TOKEN;
-- Otherwise
else
-- Keep the token counter at it's reset value
token_counter <= COUNTER_RESET_VALUE;
-- Keep monitoring for incoming tokens
token_register <= i_token;
-- Don't pass a token down the line
o_token <= NO_TOKEN;
end if;
end if;
end if;
end process TOKEN_ANALYSIS;
-- *****************************************************
-- Process: INCOMING_PACKET_DETECTOR
-- Purpose: Detects incoming valid incoming packets
-- *****************************************************
INCOMING_PACKET_DETECTOR : process (clk) is
begin
if (clk'event and clk = '1') then
if (reset = '1') then
i_packet_valid_d1 <= '0';
else
i_packet_valid_d1 <= i_packet_valid;
end if;
end if;
end process INCOMING_PACKET_DETECTOR;
incoming_packet <= i_packet_valid and (not i_packet_valid_d1); -- Detects positive edges
-- *****************************************************
-- Process: INCOMING_PACKET_CONTROLLER
-- Purpose: Incoming Packet Filtering
-- *****************************************************
INCOMING_PACKET_CONTROLLER : process (clk) is
begin
if (clk'event and clk = '1') then
-- If a valid packet is coming in and it matches the channel we are listening on, capture it
if (incoming_packet = '1' and i_packet_channel = listen_channel and i_packet_sender /= sender_id) then
recv_queue_add <= '1';
recv_queue_entry_to_add <= form_packet(i_packet_channel, i_packet_sender, i_packet_data);
else
recv_queue_add <= '0';
recv_queue_entry_to_add <= (others => '0');
end if;
end if;
end process INCOMING_PACKET_CONTROLLER;
-- *****************************************************
-- Process: OUTGOING_PACKET_CONTROLLER
-- Purpose: Outgoing Packet Filtering
-- *****************************************************
OUTGOING_PACKET_CONTROLLER : process (clk) is
begin
if (clk'event and clk = '1') then
-- If we don't have a token, then just forward packets from incoming port to outgoing port (unless the packet is one that we sent, packet has cycled)
if (token_register = NO_TOKEN and i_packet_sender /= sender_id) then
o_packet_data <= i_packet_data;
o_packet_channel <= i_packet_channel;
o_packet_sender <= i_packet_sender;
o_packet_valid <= i_packet_valid;
send_queue_remove <= '0';
-- If we do have a token and we have packets to send, then send them
elsif ((token_register = HAS_TOKEN) and (send_queue_head_valid = '1')) then
o_packet_data <= get_packet_data(send_queue_head);
o_packet_channel <= get_packet_channel(send_queue_head);
o_packet_sender <= get_packet_sender(send_queue_head);
o_packet_valid <= '1';
send_queue_remove <= '1';
-- Otherwise, drive valid line to low
else
o_packet_data <= (others => '0');
o_packet_channel <= (others => '0');
o_packet_sender <= (others => '0');
o_packet_valid <= '0';
send_queue_remove <= '0';
end if;
end if;
end process OUTGOING_PACKET_CONTROLLER;
end architecture IMP;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.std_logic_textio.all; -- I/O for logic types
library work;
use work.rv_components.all;
use work.utils.all;
use work.constants_pkg.all;
library STD;
use STD.textio.all; -- basic I/O
entity execute is
generic (
REGISTER_SIZE : positive range 32 to 32;
SIGN_EXTENSION_SIZE : positive;
INTERRUPT_VECTOR : std_logic_vector(31 downto 0);
BTB_ENTRIES : natural;
POWER_OPTIMIZED : boolean;
MULTIPLY_ENABLE : boolean;
DIVIDE_ENABLE : boolean;
SHIFTER_MAX_CYCLES : positive range 1 to 32;
ENABLE_EXCEPTIONS : boolean;
ENABLE_EXT_INTERRUPTS : boolean;
NUM_EXT_INTERRUPTS : positive range 1 to 32;
VCP_ENABLE : vcp_type;
FAMILY : string;
AUX_MEMORY_REGIONS : natural range 0 to 4;
AMR0_ADDR_BASE : std_logic_vector(31 downto 0);
AMR0_ADDR_LAST : std_logic_vector(31 downto 0);
AMR0_READ_ONLY : boolean;
UC_MEMORY_REGIONS : natural range 0 to 4;
UMR0_ADDR_BASE : std_logic_vector(31 downto 0);
UMR0_ADDR_LAST : std_logic_vector(31 downto 0);
UMR0_READ_ONLY : boolean;
HAS_ICACHE : boolean;
HAS_DCACHE : boolean
);
port (
clk : in std_logic;
reset : in std_logic;
global_interrupts : in std_logic_vector(NUM_EXT_INTERRUPTS-1 downto 0);
program_counter : in unsigned(REGISTER_SIZE-1 downto 0);
core_idle : in std_logic;
memory_interface_idle : in std_logic;
to_execute_valid : in std_logic;
to_execute_program_counter : in unsigned(REGISTER_SIZE-1 downto 0);
to_execute_predicted_pc : in unsigned(REGISTER_SIZE-1 downto 0);
to_execute_instruction : in std_logic_vector(INSTRUCTION_SIZE(VCP_ENABLE)-1 downto 0);
to_execute_next_instruction : in std_logic_vector(31 downto 0);
to_execute_next_valid : in std_logic;
to_execute_rs1_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
to_execute_rs2_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
to_execute_rs3_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
to_execute_sign_extension : in std_logic_vector(SIGN_EXTENSION_SIZE-1 downto 0);
from_execute_ready : buffer std_logic;
--quash_execute input isn't needed as mispredicts have already resolved
execute_idle : out std_logic;
--To PC correction
to_pc_correction_data : out unsigned(REGISTER_SIZE-1 downto 0);
to_pc_correction_source_pc : out unsigned(REGISTER_SIZE-1 downto 0);
to_pc_correction_valid : buffer std_logic;
to_pc_correction_predictable : out std_logic;
from_pc_correction_ready : in std_logic;
--To register file
to_rf_select : buffer std_logic_vector(REGISTER_NAME_SIZE-1 downto 0);
to_rf_data : buffer std_logic_vector(REGISTER_SIZE-1 downto 0);
to_rf_valid : buffer std_logic;
--Data ORCA-internal memory-mapped master
lsu_oimm_address : buffer std_logic_vector(REGISTER_SIZE-1 downto 0);
lsu_oimm_byteenable : out std_logic_vector((REGISTER_SIZE/8)-1 downto 0);
lsu_oimm_requestvalid : buffer std_logic;
lsu_oimm_readnotwrite : buffer std_logic;
lsu_oimm_writedata : out std_logic_vector(REGISTER_SIZE-1 downto 0);
lsu_oimm_readdata : in std_logic_vector(REGISTER_SIZE-1 downto 0);
lsu_oimm_readdatavalid : in std_logic;
lsu_oimm_waitrequest : in std_logic;
--ICache control (Invalidate/flush/writeback)
from_icache_control_ready : in std_logic;
to_icache_control_valid : buffer std_logic;
to_icache_control_command : out cache_control_command;
--DCache control (Invalidate/flush/writeback)
from_dcache_control_ready : in std_logic;
to_dcache_control_valid : buffer std_logic;
to_dcache_control_command : out cache_control_command;
--Cache control common signals
to_cache_control_base : out std_logic_vector(REGISTER_SIZE-1 downto 0);
to_cache_control_last : out std_logic_vector(REGISTER_SIZE-1 downto 0);
--Auxiliary/Uncached memory regions
amr_base_addrs : out std_logic_vector((imax(AUX_MEMORY_REGIONS, 1)*REGISTER_SIZE)-1 downto 0);
amr_last_addrs : out std_logic_vector((imax(AUX_MEMORY_REGIONS, 1)*REGISTER_SIZE)-1 downto 0);
umr_base_addrs : out std_logic_vector((imax(UC_MEMORY_REGIONS, 1)*REGISTER_SIZE)-1 downto 0);
umr_last_addrs : out std_logic_vector((imax(UC_MEMORY_REGIONS, 1)*REGISTER_SIZE)-1 downto 0);
pause_ifetch : out std_logic;
--Timer signals
timer_value : in std_logic_vector(63 downto 0);
timer_interrupt : in std_logic;
--Vector coprocessor port
vcp_data0 : out std_logic_vector(REGISTER_SIZE-1 downto 0);
vcp_data1 : out std_logic_vector(REGISTER_SIZE-1 downto 0);
vcp_data2 : out std_logic_vector(REGISTER_SIZE-1 downto 0);
vcp_instruction : out std_logic_vector(40 downto 0);
vcp_valid_instr : out std_logic;
vcp_ready : in std_logic;
vcp_illegal : in std_logic;
vcp_writeback_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
vcp_writeback_en : in std_logic;
vcp_alu_data1 : in std_logic_vector(REGISTER_SIZE-1 downto 0);
vcp_alu_data2 : in std_logic_vector(REGISTER_SIZE-1 downto 0);
vcp_alu_source_valid : in std_logic;
vcp_alu_result : out std_logic_vector(REGISTER_SIZE-1 downto 0);
vcp_alu_result_valid : out std_logic
);
end entity execute;
architecture behavioural of execute is
constant INSTRUCTION32 : std_logic_vector(31 downto 0) := (others => '-');
alias opcode : std_logic_vector(6 downto 0) is to_execute_instruction(INSTR_OPCODE'range);
alias rd_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
to_execute_instruction(REGISTER_RD'range);
alias rs1_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
to_execute_instruction(REGISTER_RS1'range);
alias rs2_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
to_execute_instruction(REGISTER_RS2'range);
alias rs3_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
to_execute_instruction(REGISTER_RD'range);
signal use_after_produce_stall : std_logic;
signal to_rf_select_writeable : std_logic;
signal rs1_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal rs2_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal rs3_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
alias next_rs1_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
to_execute_next_instruction(REGISTER_RS1'range);
alias next_rs2_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
to_execute_next_instruction(REGISTER_RS2'range);
alias next_rs3_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
to_execute_next_instruction(REGISTER_RD'range);
type fwd_mux_t is (ALU_FWD, NO_FWD);
signal rs1_mux : fwd_mux_t;
signal rs2_mux : fwd_mux_t;
signal rs3_mux : fwd_mux_t;
--Writeback data sources (VCP writes back through syscall)
signal alu_select : std_logic;
signal to_alu_valid : std_logic;
signal from_alu_ready : std_logic;
signal from_alu_illegal : std_logic;
signal from_alu_valid : std_logic;
signal from_alu_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal branch_select : std_logic;
signal to_branch_valid : std_logic;
--signal from_branch_ready : std_logic; --Branch unit always ready
signal from_branch_illegal : std_logic;
signal from_branch_valid : std_logic;
signal from_branch_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal lsu_select : std_logic;
signal to_lsu_valid : std_logic;
signal from_lsu_ready : std_logic;
signal from_lsu_illegal : std_logic;
signal from_lsu_misalign : std_logic;
signal from_lsu_valid : std_logic;
signal from_lsu_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal syscall_select : std_logic;
signal to_syscall_valid : std_logic;
signal from_syscall_ready : std_logic;
signal from_syscall_illegal : std_logic;
signal from_syscall_valid : std_logic;
signal from_syscall_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal vcp_select : std_logic;
signal to_vcp_valid : std_logic;
signal from_opcode_illegal : std_logic;
signal illegal_instruction : std_logic;
signal to_alu_rs1_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal to_alu_rs2_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal branch_to_pc_correction_valid : std_logic;
signal branch_to_pc_correction_data : unsigned(REGISTER_SIZE-1 downto 0);
signal writeback_stall_from_lsu : std_logic;
signal load_in_progress : std_logic;
signal lsu_idle : std_logic;
signal memory_idle : std_logic;
signal syscall_to_pc_correction_valid : std_logic;
signal syscall_to_pc_correction_data : unsigned(REGISTER_SIZE-1 downto 0);
signal from_writeback_ready : std_logic;
signal to_rf_mux : std_logic_vector(1 downto 0);
signal vcp_writeback_select : std_logic;
signal from_branch_misaligned : std_logic;
begin
--Decode instruction; could get pushed back to decode stage
process (opcode) is
begin
alu_select <= '0';
branch_select <= '0';
lsu_select <= '0';
syscall_select <= '0';
vcp_select <= '0';
from_opcode_illegal <= '0';
--Decode OPCODE to select submodule. All paths must decode to exactly one
--submodule.
--If ENABLE_EXCEPTIONS is false decode illegal instructions to ALU ops as
--the default way to handle.
case opcode is
when ALU_OP | ALUI_OP | LUI_OP | AUIPC_OP =>
alu_select <= '1';
when JAL_OP | JALR_OP | BRANCH_OP =>
branch_select <= '1';
when LOAD_OP | STORE_OP =>
lsu_select <= '1';
when SYSTEM_OP | MISC_MEM_OP =>
syscall_select <= '1';
when VCP32_OP =>
if VCP_ENABLE /= DISABLED then
vcp_select <= '1';
else
if ENABLE_EXCEPTIONS then
from_opcode_illegal <= '1';
else
alu_select <= '1';
end if;
end if;
when VCP64_OP =>
if VCP_ENABLE = SIXTY_FOUR_BIT then
vcp_select <= '1';
else
if ENABLE_EXCEPTIONS then
from_opcode_illegal <= '1';
else
alu_select <= '1';
end if;
end if;
when others =>
if ENABLE_EXCEPTIONS then
from_opcode_illegal <= '1';
else
alu_select <= '1';
end if;
end case;
end process;
--Currently only set valid/ready for execute when writeback is ready. This
--means that any instruction that completes in the execute cycle will be able to
--writeback without a stall; i.e. alu/branch/syscall instructions merely
--assert valid for once cycle and are done.
--Could be changed to have components hold their output if to_execute_ready
--was not true, which might slightly complicate logic but would allow some
--optimizations such as allowing a multicycle ALU op
--(multiply/shift/div/etc.) to start while waiting for a load to return.
to_alu_valid <= alu_select and to_execute_valid and from_writeback_ready;
to_branch_valid <= branch_select and to_execute_valid and from_writeback_ready;
to_lsu_valid <= lsu_select and to_execute_valid and from_writeback_ready;
to_syscall_valid <= syscall_select and to_execute_valid and from_writeback_ready;
to_vcp_valid <= vcp_select and to_execute_valid and from_writeback_ready;
from_execute_ready <= (not to_execute_valid) or (from_writeback_ready and
(((not lsu_select) or from_lsu_ready) and
((not alu_select) or from_alu_ready) and
((not syscall_select) or from_syscall_ready) and
((not vcp_select) or vcp_ready)));
illegal_instruction <= to_execute_valid and from_writeback_ready and (from_opcode_illegal or
(alu_select and from_alu_illegal) or
(branch_select and from_branch_illegal) or
(lsu_select and from_lsu_illegal) or
(syscall_select and from_syscall_illegal) or
(vcp_select and vcp_illegal));
-----------------------------------------------------------------------------
-- REGISTER FORWADING
-- Knowing the next instruction coming downt the pipeline, we can
-- generate the mux select bits for the next cycle.
-- there are several functional units that could generate a writeback. ALU,
-- JAL, Syscalls, load_store. the ALU forward directly to the next
-- instruction, The others stall the pipeline to wait for the registers to
-- propogate if the next instruction uses them.
--
-----------------------------------------------------------------------------
rs1_data <= from_alu_data when rs1_mux = ALU_FWD else
to_execute_rs1_data;
rs2_data <= from_alu_data when rs2_mux = ALU_FWD else
to_execute_rs2_data;
rs3_data <= from_alu_data when rs3_mux = ALU_FWD else
to_execute_rs3_data;
--No forward stall; system calls, loads, and branches aren't forwarded.
use_after_produce_stall <=
to_rf_select_writeable and (from_syscall_valid or load_in_progress or from_branch_valid) when
to_rf_select = rs1_select or to_rf_select = rs2_select or ((to_rf_select = rs3_select) and VCP_ENABLE /= DISABLED)
else '0';
--Calculate forwarding muxes for next instruction in advance in order to
--minimize execute cycle time.
process(clk)
begin
if rising_edge(clk) then
if from_writeback_ready = '1' then
rs1_mux <= NO_FWD;
rs2_mux <= NO_FWD;
rs3_mux <= NO_FWD;
end if;
if to_alu_valid = '1' and from_alu_ready = '1' then
if rd_select /= REGISTER_ZERO then
if rd_select = next_rs1_select then
rs1_mux <= ALU_FWD;
end if;
if rd_select = next_rs2_select then
rs2_mux <= ALU_FWD;
end if;
if rd_select = next_rs3_select then
rs3_mux <= ALU_FWD;
end if;
end if;
end if;
end if;
end process;
to_alu_rs1_data <= vcp_alu_data1 when vcp_select = '1' else
rs1_data;
to_alu_rs2_data <= vcp_alu_data2 when vcp_select = '1' else
rs2_data;
alu : arithmetic_unit
generic map (
REGISTER_SIZE => REGISTER_SIZE,
SIGN_EXTENSION_SIZE => SIGN_EXTENSION_SIZE,
POWER_OPTIMIZED => POWER_OPTIMIZED,
MULTIPLY_ENABLE => MULTIPLY_ENABLE,
DIVIDE_ENABLE => DIVIDE_ENABLE,
SHIFTER_MAX_CYCLES => SHIFTER_MAX_CYCLES,
ENABLE_EXCEPTIONS => ENABLE_EXCEPTIONS,
FAMILY => FAMILY
)
port map (
clk => clk,
to_alu_valid => to_alu_valid,
to_alu_rs1_data => to_alu_rs1_data,
to_alu_rs2_data => to_alu_rs2_data,
from_alu_ready => from_alu_ready,
from_alu_illegal => from_alu_illegal,
vcp_source_valid => vcp_alu_source_valid,
vcp_select => vcp_select,
from_execute_ready => from_execute_ready,
instruction => to_execute_instruction(INSTRUCTION32'range),
sign_extension => to_execute_sign_extension,
current_pc => to_execute_program_counter,
from_alu_data => from_alu_data,
from_alu_valid => from_alu_valid
);
branch : branch_unit
generic map (
REGISTER_SIZE => REGISTER_SIZE,
SIGN_EXTENSION_SIZE => SIGN_EXTENSION_SIZE,
BTB_ENTRIES => BTB_ENTRIES,
ENABLE_EXCEPTIONS => ENABLE_EXCEPTIONS
)
port map (
clk => clk,
reset => reset,
to_branch_valid => to_branch_valid,
from_branch_illegal => from_branch_illegal,
rs1_data => rs1_data,
rs2_data => rs2_data,
current_pc => to_execute_program_counter,
predicted_pc => to_execute_predicted_pc,
instruction => to_execute_instruction(INSTRUCTION32'range),
sign_extension => to_execute_sign_extension,
from_branch_valid => from_branch_valid,
from_branch_data => from_branch_data,
to_branch_ready => from_writeback_ready,
target_misaligned => from_branch_misaligned,
to_pc_correction_data => branch_to_pc_correction_data,
to_pc_correction_source_pc => to_pc_correction_source_pc,
to_pc_correction_valid => branch_to_pc_correction_valid,
from_pc_correction_ready => from_pc_correction_ready
);
ls_unit : load_store_unit
generic map (
REGISTER_SIZE => REGISTER_SIZE,
SIGN_EXTENSION_SIZE => SIGN_EXTENSION_SIZE,
ENABLE_EXCEPTIONS => ENABLE_EXCEPTIONS
)
port map (
clk => clk,
reset => reset,
lsu_idle => lsu_idle,
to_lsu_valid => to_lsu_valid,
from_lsu_illegal => from_lsu_illegal,
from_lsu_misalign => from_lsu_misalign,
rs1_data => rs1_data,
rs2_data => rs2_data,
instruction => to_execute_instruction(INSTRUCTION32'range),
sign_extension => to_execute_sign_extension,
load_in_progress => load_in_progress,
writeback_stall_from_lsu => writeback_stall_from_lsu,
lsu_ready => from_lsu_ready,
from_lsu_data => from_lsu_data,
from_lsu_valid => from_lsu_valid,
oimm_address => lsu_oimm_address,
oimm_byteenable => lsu_oimm_byteenable,
oimm_requestvalid => lsu_oimm_requestvalid,
oimm_readnotwrite => lsu_oimm_readnotwrite,
oimm_writedata => lsu_oimm_writedata,
oimm_readdata => lsu_oimm_readdata,
oimm_readdatavalid => lsu_oimm_readdatavalid,
oimm_waitrequest => lsu_oimm_waitrequest
);
memory_idle <= memory_interface_idle and lsu_idle;
syscall : sys_call
generic map (
REGISTER_SIZE => REGISTER_SIZE,
POWER_OPTIMIZED => POWER_OPTIMIZED,
INTERRUPT_VECTOR => INTERRUPT_VECTOR,
ENABLE_EXCEPTIONS => ENABLE_EXCEPTIONS,
ENABLE_EXT_INTERRUPTS => ENABLE_EXT_INTERRUPTS,
NUM_EXT_INTERRUPTS => NUM_EXT_INTERRUPTS,
VCP_ENABLE => VCP_ENABLE,
MULTIPLY_ENABLE => MULTIPLY_ENABLE,
AUX_MEMORY_REGIONS => AUX_MEMORY_REGIONS,
AMR0_ADDR_BASE => AMR0_ADDR_BASE,
AMR0_ADDR_LAST => AMR0_ADDR_LAST,
AMR0_READ_ONLY => AMR0_READ_ONLY,
UC_MEMORY_REGIONS => UC_MEMORY_REGIONS,
UMR0_ADDR_BASE => UMR0_ADDR_BASE,
UMR0_ADDR_LAST => UMR0_ADDR_LAST,
UMR0_READ_ONLY => UMR0_READ_ONLY,
HAS_ICACHE => HAS_ICACHE,
HAS_DCACHE => HAS_DCACHE
)
port map (
clk => clk,
reset => reset,
global_interrupts => global_interrupts,
core_idle => core_idle,
memory_idle => memory_idle,
program_counter => program_counter,
to_syscall_valid => to_syscall_valid,
from_syscall_illegal => from_syscall_illegal,
rs1_data => rs1_data,
rs2_data => rs2_data,
instruction => to_execute_instruction(INSTRUCTION32'range),
current_pc => to_execute_program_counter,
from_syscall_ready => from_syscall_ready,
from_branch_misaligned => from_branch_misaligned,
illegal_instruction => illegal_instruction,
from_lsu_addr_misalign => from_lsu_misalign,
from_lsu_address => lsu_oimm_address,
from_syscall_valid => from_syscall_valid,
from_syscall_data => from_syscall_data,
to_pc_correction_data => syscall_to_pc_correction_data,
to_pc_correction_valid => syscall_to_pc_correction_valid,
from_pc_correction_ready => from_pc_correction_ready,
from_icache_control_ready => from_icache_control_ready,
to_icache_control_valid => to_icache_control_valid,
to_icache_control_command => to_icache_control_command,
from_dcache_control_ready => from_dcache_control_ready,
to_dcache_control_valid => to_dcache_control_valid,
to_dcache_control_command => to_dcache_control_command,
to_cache_control_base => to_cache_control_base,
to_cache_control_last => to_cache_control_last,
amr_base_addrs => amr_base_addrs,
amr_last_addrs => amr_last_addrs,
umr_base_addrs => umr_base_addrs,
umr_last_addrs => umr_last_addrs,
pause_ifetch => pause_ifetch,
timer_value => timer_value,
timer_interrupt => timer_interrupt,
vcp_writeback_data => vcp_writeback_data,
vcp_writeback_en => vcp_writeback_en
);
vcp_port : vcp_handler
generic map (
REGISTER_SIZE => REGISTER_SIZE,
VCP_ENABLE => VCP_ENABLE
)
port map (
clk => clk,
reset => reset,
instruction => to_execute_instruction,
to_vcp_valid => to_vcp_valid,
vcp_select => vcp_select,
rs1_data => rs1_data,
rs2_data => rs2_data,
rs3_data => rs3_data,
vcp_data0 => vcp_data0,
vcp_data1 => vcp_data1,
vcp_data2 => vcp_data2,
vcp_instruction => vcp_instruction,
vcp_valid_instr => vcp_valid_instr,
vcp_writeback_select => vcp_writeback_select
);
vcp_alu_result_valid <= from_alu_valid;
vcp_alu_result <= from_alu_data;
------------------------------------------------------------------------------
-- PC correction (branch mispredict, interrupt, etc.)
------------------------------------------------------------------------------
to_pc_correction_data <= syscall_to_pc_correction_data when syscall_to_pc_correction_valid = '1' else
branch_to_pc_correction_data;
to_pc_correction_valid <= syscall_to_pc_correction_valid or branch_to_pc_correction_valid;
--Don't put syscalls in the BTB as they have side effects and must flush the
--pipeline anyway.
to_pc_correction_predictable <= not syscall_to_pc_correction_valid;
--Intuitively execute_idle is lsu_idle and alu_idle and branch_idle etc. for
--all the functional units. In practice the idle signal is only needed for
--interrupts, and it's fine to take an interrupt as long as the branch and
--syscall units have finished updating the PC and we're not waiting on a
--load. Even though for instance the ALU may have some internal state, since
--the execute unit is serialized it won't assert ready back to the decode
--unit until it has finished the instruction.
--Also note intuitively we'd want a writeback_idle signal as interrupts can
--be taken before writeback has occurred; however since there's no
--backpressure from writeback we can always guarantee that the writeback will
--occur before the interrupt handler decodes an instruction and reads a
--register.
execute_idle <= lsu_idle and (not to_pc_correction_valid);
------------------------------------------------------------------------------
-- Writeback
------------------------------------------------------------------------------
from_writeback_ready <= (not use_after_produce_stall) and (not writeback_stall_from_lsu);
process(clk)
begin
if rising_edge(clk) then
if from_writeback_ready = '1' then
to_rf_select <= rd_select;
if rd_select = REGISTER_ZERO then
to_rf_select_writeable <= '0';
else
to_rf_select_writeable <= '1';
end if;
end if;
end if;
end process;
to_rf_mux <= "00" when from_syscall_valid = '1' else
"01" when load_in_progress = '1' else
"10" when from_branch_valid = '1' else
"11";
with to_rf_mux select
to_rf_data <=
from_syscall_data when "00",
from_lsu_data when "01",
from_branch_data when "10",
from_alu_data when others;
to_rf_valid <= to_rf_select_writeable and (from_syscall_valid or
from_lsu_valid or
from_branch_valid or
(from_alu_valid and (not vcp_writeback_select)));
-------------------------------------------------------------------------------
-- Simulation assertions and debug
-------------------------------------------------------------------------------
--pragma translate_off
process(clk)
begin
if rising_edge(clk) then
if reset = '0' then
assert (bool_to_int(from_syscall_valid) +
bool_to_int(from_lsu_valid) +
bool_to_int(from_branch_valid) +
bool_to_int(from_alu_valid)) <= 1 report "Multiple Data Enables Asserted" severity failure;
end if;
end if;
end process;
my_print : process(clk)
variable my_line : line; -- type 'line' comes from textio
variable last_valid_pc : unsigned(REGISTER_SIZE-1 downto 0);
type register_list is array(0 to 31) of std_logic_vector(REGISTER_SIZE-1 downto 0);
variable shadow_registers : register_list := (others => (others => '0'));
constant DEBUG_WRITEBACK : boolean := false;
begin
if rising_edge(clk) then
if to_rf_valid = '1' and DEBUG_WRITEBACK then
write(my_line, string'("WRITEBACK: PC = "));
hwrite(my_line, std_logic_vector(last_valid_pc));
shadow_registers(to_integer(unsigned(to_rf_select))) := to_rf_data;
write(my_line, string'(" REGISTERS = {"));
for i in shadow_registers'range loop
hwrite(my_line, shadow_registers(i));
if i /= shadow_registers'right then
write(my_line, string'(","));
end if;
end loop; -- i
write(my_line, string'("}"));
writeline(output, my_line);
end if;
if to_execute_valid = '1' then
write(my_line, string'("executing pc = ")); -- formatting
hwrite(my_line, (std_logic_vector(to_execute_program_counter))); -- format type std_logic_vector as hex
write(my_line, string'(" instr = ")); -- formatting
if opcode = VCP64_OP then
hwrite(my_line, (to_execute_instruction)); -- format type std_logic_vector as hex
else
hwrite(my_line, (to_execute_instruction(31 downto 0))); -- format type std_logic_vector as hex
end if;
if from_execute_ready = '0' then
write(my_line, string'(" stalling")); -- formatting
else
last_valid_pc := to_execute_program_counter;
end if;
writeline(output, my_line); -- write to "output"
else
--write(my_line, string'("bubble")); -- formatting
--writeline(output, my_line); -- write to "output"
end if;
end if;
end process my_print;
--pragma translate_on
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.arith_dsp48e.all;
use work.utilities.all;
entity div_tb is
end div_tb;
architecture behavioral of div_tb is
constant C_DATAIN_WIDTH : integer := 32;
constant C_PRECISION : natural := 29; -- Quotient width = 32
constant c_ce_period : natural := 2;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal ce : std_logic := '0';
signal trg : std_logic := '0';
signal n : std_logic_vector(C_DATAIN_WIDTH-1 downto 0) := (others => '0');
signal d : std_logic_vector(C_DATAIN_WIDTH-1 downto 0) := (others => '0');
--Outputs
signal q : std_logic_vector(C_PRECISION downto 0);
signal r : std_logic_vector(C_DATAIN_WIDTH-1 downto 0) := (others => '0');
signal rdy : std_logic;
signal err : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant TAB : character := ht;
file test_out_data : text open write_mode is "output.dat";
begin
uut_div_fixedpoint : div_fixedpoint
generic map
(
G_DATAIN_WIDTH => C_DATAIN_WIDTH,
G_PRECISION => C_PRECISION
)
port map
(
clk_i => clk,
rst_i => rst,
ce_i => ce,
n_i => n,
d_i => d,
q_o => q,
r_o => r,
trg_i => trg,
rdy_o => rdy,
err_o => err
);
-- Clock process definitions
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
ce_gen : process(clk)
variable ce_count : natural := 0;
begin
if rising_edge(clk) then
ce_count := ce_count + 1;
if ce_count = c_ce_period then
ce <= '1';
ce_count := 0;
else
ce <= '0';
end if;
end if;
end process;
-- Stimulus process
stim_proc : process
variable outline : line;
variable i : integer;
begin
--rst <= '1';
--wait for clk_period*10.5*c_ce_period;
--rst <= '0';
--wait for clk_period*10*c_ce_period;
for i in 0 to 5740 loop
n <= std_logic_vector(to_signed((i*i)/2, C_DATAIN_WIDTH));
d <= std_logic_vector(to_signed(32947600, C_DATAIN_WIDTH));
wait for clk_period*1;
write(outline, to_integer(signed(n)));
write(outline, TAB);
write(outline, to_integer(signed(d)));
trg <= '1';
wait for clk_period*c_ce_period;
trg <= '0';
wait for clk_period*31*c_ce_period;
write(outline, TAB);
write(outline, to_integer(signed(q)));
write(outline, TAB);
write(outline, to_integer(signed(r)));
wait for clk_period*1*c_ce_period;
writeline(test_out_data, outline); -- write row to output file
end loop;
assert (false) report "Test finished." severity failure;
wait;
end process;
end;
|
-----------------------------------------------------------------------------------------
-- --
-- This file is part of the CAPH Compiler distribution --
-- http://caph.univ-bpclermont.fr --
-- --
-- Jocelyn SEROT --
-- Jocelyn.Serot@univ-bpclermont.fr --
-- --
-- Copyright 2011-2015 Jocelyn SEROT. All rights reserved. --
-- This file is distributed under the terms of the GNU Library General Public License --
-- with the special exception on linking described in file ../LICENSE. --
-- --
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
entity port_out is
generic ( filename: string := "result.in"; size: integer := 10 );
port ( empty : in std_logic;
din : in std_logic_vector(size-1 downto 0);
rd : out std_logic; -- read (pop) signal, active 1 on clk^
clk : in std_logic;
rst : in std_logic
);
end port_out;
architecture beh of port_out is
begin
process
file output_file: text;
variable file_line: line;
variable token: integer;
variable eof: boolean;
begin
rd <= '0';
eof := false;
file_open(output_file,filename,WRITE_MODE);
while not eof loop
wait until rising_edge(clk);
if ( empty = '0' ) then
write (file_line,to_bitvector(din));
writeline (output_file,file_line);
rd <= '1';
wait until rising_edge(clk);
rd <= '0';
end if;
end loop; -- TODO: set eof when run is completed ?
file_close(output_file);
wait;
end process;
end;
|
package fifo_pkg is
end PACKAGE;
package fifo_pkg is
end PACKAGE;
|
entity tb_var01a is
end tb_var01a;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_var01a is
signal clk : std_logic;
signal mask : std_logic_vector (1 downto 0);
signal val : std_logic_vector (7 downto 0);
signal res : std_logic_vector (7 downto 0);
begin
dut: entity work.var01a
port map (
clk => clk,
mask => mask,
val => val,
res => res);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
mask <= "11";
val <= x"12";
pulse;
assert res = x"12" report "res=" & to_hstring (res) severity failure;
mask <= "10";
val <= x"9a";
pulse;
assert res = x"92" severity failure;
mask <= "00";
val <= x"00";
pulse;
assert res = x"92" severity failure;
mask <= "01";
val <= x"de";
pulse;
assert res = x"9e" severity failure;
wait;
end process;
end behav;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "reg_file"
-------------------------------------------------------------------------------
-- Author : Calle <calle@Alukiste>
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
-------------------------------------------------------------------------------
entity reg_file_tb is
end reg_file_tb;
-------------------------------------------------------------------------------
architecture tb of reg_file_tb is
-- component generics
constant BASE_ADDRESS : integer range 0 to 16#7FFF# := 16#0010#;
constant REG_ADDR_BIT : natural := 1;
-- component ports
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type := (addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal reg_o : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
signal reg_i : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
-- clock
signal clk : std_logic := '1';
type comment_type is (idle, write, read);
signal comment : comment_type := idle;
begin -- tb
-- component instantiation
DUT : reg_file
generic map (
BASE_ADDRESS => BASE_ADDRESS,
REG_ADDR_BIT => REG_ADDR_BIT)
port map (
bus_o => bus_o,
bus_i => bus_i,
reg_o => reg_o,
reg_i => reg_i,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- Reset
reg_i <= (others => (others => '0'));
reg_i(0)(3 downto 0) <= "0001";
reg_i(1)(3 downto 0) <= "0010";
bus_i.addr <= (others => '0');
bus_i.data <= (others => '0');
bus_i.re <= '0';
bus_i.we <= '0';
wait until Clk = '1';
comment <= write;
writeWord(addr => 16#0010#, data => 16#0055#, bus_i => bus_i, clk => clk);
wait until Clk = '1';
wait until Clk = '1';
writeWord(addr => 16#0011#, data => 16#005f#, bus_i => bus_i, clk => clk);
wait until Clk = '1';
wait until Clk = '1';
-- read the registers
-- expected data is the input to the register_file reg_i(0) and reg_i(1)
comment <= read;
readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk);
readWord(addr => BASE_ADDRESS + 1, bus_i => bus_i, clk => clk);
-- do the same reads, but the DUT shouldn't react
-- bus data should be 0000
readWord(addr => BASE_ADDRESS + 2, bus_i => bus_i, clk => clk);
-- read from correct address again
readWord(addr => BASE_ADDRESS + 1, bus_i => bus_i, clk => clk);
wait for 1000 ns;
end process WaveGen_Proc;
end tb;
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "reg_file"
-------------------------------------------------------------------------------
-- Author : Calle <calle@Alukiste>
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
-------------------------------------------------------------------------------
entity reg_file_tb is
end reg_file_tb;
-------------------------------------------------------------------------------
architecture tb of reg_file_tb is
-- component generics
constant BASE_ADDRESS : integer range 0 to 16#7FFF# := 16#0010#;
constant REG_ADDR_BIT : natural := 1;
-- component ports
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type := (addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal reg_o : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
signal reg_i : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
-- clock
signal clk : std_logic := '1';
type comment_type is (idle, write, read);
signal comment : comment_type := idle;
begin -- tb
-- component instantiation
DUT : reg_file
generic map (
BASE_ADDRESS => BASE_ADDRESS,
REG_ADDR_BIT => REG_ADDR_BIT)
port map (
bus_o => bus_o,
bus_i => bus_i,
reg_o => reg_o,
reg_i => reg_i,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- Reset
reg_i <= (others => (others => '0'));
reg_i(0)(3 downto 0) <= "0001";
reg_i(1)(3 downto 0) <= "0010";
bus_i.addr <= (others => '0');
bus_i.data <= (others => '0');
bus_i.re <= '0';
bus_i.we <= '0';
wait until Clk = '1';
comment <= write;
writeWord(addr => 16#0010#, data => 16#0055#, bus_i => bus_i, clk => clk);
wait until Clk = '1';
wait until Clk = '1';
writeWord(addr => 16#0011#, data => 16#005f#, bus_i => bus_i, clk => clk);
wait until Clk = '1';
wait until Clk = '1';
-- read the registers
-- expected data is the input to the register_file reg_i(0) and reg_i(1)
comment <= read;
readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk);
readWord(addr => BASE_ADDRESS + 1, bus_i => bus_i, clk => clk);
-- do the same reads, but the DUT shouldn't react
-- bus data should be 0000
readWord(addr => BASE_ADDRESS + 2, bus_i => bus_i, clk => clk);
-- read from correct address again
readWord(addr => BASE_ADDRESS + 1, bus_i => bus_i, clk => clk);
wait for 1000 ns;
end process WaveGen_Proc;
end tb;
-------------------------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
entity prn32 is
generic(
n: integer:= 4;
seed: std_logic_vector:= X"12345678"
);
port(
clk: in std_logic;
pn_val: out std_logic_vector(n-1 downto 0)
);
end prn32;
architecture break_out of prn32 is
signal pn: std_logic_vector(31 downto 0):= seed;
begin
pn_val <= pn(n-1 downto 0);
random_gen: process(clk)
variable fb: std_logic;
variable fix: std_logic;
begin
if (clk'event and clk = '1') then
fix := '1';
for i in 30 downto 0 loop
fix := (not pn(i)) and fix;
end loop;
fb := pn(0) xor pn(1) xor pn(21) xor pn(31) xor fix;
pn <= pn(30 downto 0) & fb;
end if;
end process;
end break_out;
|
library ieee;
use ieee.std_logic_1164.all;
entity tristate_32 is
PORT(
my_in : in std_logic_vector(31 downto 0);
sel : in std_logic;
my_out : out std_logic_vector(31 downto 0)
);
end tristate_32;
architecture control of tristate_32 is
begin
my_out <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" when (sel = '0') else my_in;
end control; |
library ieee;
use ieee.std_logic_1164.all;
entity tristate_32 is
PORT(
my_in : in std_logic_vector(31 downto 0);
sel : in std_logic;
my_out : out std_logic_vector(31 downto 0)
);
end tristate_32;
architecture control of tristate_32 is
begin
my_out <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" when (sel = '0') else my_in;
end control; |
library ieee;
use ieee.std_logic_1164.all;
entity tristate_32 is
PORT(
my_in : in std_logic_vector(31 downto 0);
sel : in std_logic;
my_out : out std_logic_vector(31 downto 0)
);
end tristate_32;
architecture control of tristate_32 is
begin
my_out <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" when (sel = '0') else my_in;
end control; |
library ieee;
use ieee.std_logic_1164.all;
entity tristate_32 is
PORT(
my_in : in std_logic_vector(31 downto 0);
sel : in std_logic;
my_out : out std_logic_vector(31 downto 0)
);
end tristate_32;
architecture control of tristate_32 is
begin
my_out <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" when (sel = '0') else my_in;
end control; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity cnt01 is
port (
clock : in STD_LOGIC;
reset : in STD_LOGIC;
clear_count : in STD_LOGIC;
enable : in STD_LOGIC;
counter_out : out STD_LOGIC_VECTOR (9 downto 0)
);
end cnt01;
architecture behav of cnt01 is
signal s_count : unsigned(9 downto 0); -- := (others => '0');
begin
process(clock, reset)
begin
if reset = '1' then
s_count <= (others => '0');
elsif rising_edge(clock) then
if clear_count = '1' then
s_count <= (others => '0');
elsif enable = '1' then
s_count <= s_count + 1;
end if;
end if;
end process;
-- connect internal signal to output
counter_out <= std_logic_vector(s_count);
end behav;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.procedures.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity r6w2mem1k8 is
port(
clk : in std_logic;
clk2x : in std_logic;
addra : in std_logic_vector(9 downto 0);
ena : in std_logic;
doa : out t_data;
addrb : in std_logic_vector(9 downto 0);
enb : in std_logic;
dob : out t_data;
addrc : in std_logic_vector(9 downto 0);
enc : in std_logic;
doc : out t_data;
addrd : in std_logic_vector(9 downto 0);
en_d : in std_logic;
dod : out t_data;
addre : in std_logic_vector(9 downto 0);
ene : in std_logic;
doe : out t_data;
addrf : in std_logic_vector(9 downto 0);
enf : in std_logic;
dof : out t_data;
dig : in t_data;
addrg : in std_logic_vector(9 downto 0);
weg : in std_logic;
dih : in t_data;
addrh : in std_logic_vector(9 downto 0);
weh : in std_logic
);
end r6w2mem1k8;
architecture Structural of r6w2mem1k8 is
begin
p4mem1k8_0: entity work.p4mem1k8
port map(
clk => clk,
clk2x => clk2x,
dia => (others => '0'),
addra => addra,
ena => ena,
wea => '0',
doa => doa,
dib => dig,
addrb => addrg,
enb => weg,
web => weg,
dob => open,
dic => (others => '0'),
addrc => addrb,
enc => enb,
wec => '0',
doc => dob,
did => dih,
addrd => addrh,
en_d => weh,
wed => weh,
dod => open
);
p4mem1k8_1: entity work.p4mem1k8
port map(
clk => clk,
clk2x => clk2x,
dia => (others => '0'),
addra => addrc,
ena => enc,
wea => '0',
doa => doc,
dib => dig,
addrb => addrg,
enb => weg,
web => weg,
dob => open,
dic => (others => '0'),
addrc => addrd,
enc => en_d,
wec => '0',
doc => dod,
did => dih,
addrd => addrh,
en_d => weh,
wed => weh,
dod => open
);
p4mem1k8_2: entity work.p4mem1k8
port map(
clk => clk,
clk2x => clk2x,
dia => (others => '0'),
addra => addre,
ena => ene,
wea => '0',
doa => doe,
dib => dig,
addrb => addrg,
enb => weg,
web => weg,
dob => open,
dic => (others => '0'),
addrc => addrf,
enc => enf,
wec => '0',
doc => dof,
did => dih,
addrd => addrh,
en_d => weh,
wed => weh,
dod => open
);
end Structural;
|
--Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
--Date : Fri Sep 30 18:09:05 2016
--Host : graviton running 64-bit Debian GNU/Linux 7.10 (wheezy)
--Command : generate_target cpu.bd
--Design : cpu
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_ZVW4AE is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_ZVW4AE;
architecture STRUCTURE of m00_couplers_imp_ZVW4AE is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(8 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(8 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(8 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(8 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(8 downto 0) <= S_AXI_araddr(8 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(8 downto 0) <= S_AXI_awaddr(8 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_PQKNCJ is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m01_couplers_imp_PQKNCJ;
architecture STRUCTURE of m01_couplers_imp_PQKNCJ is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(8 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(8 downto 0);
M_AXI_arvalid <= m01_couplers_to_m01_couplers_ARVALID;
M_AXI_awaddr(8 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(8 downto 0);
M_AXI_awvalid <= m01_couplers_to_m01_couplers_AWVALID;
M_AXI_bready <= m01_couplers_to_m01_couplers_BREADY;
M_AXI_rready <= m01_couplers_to_m01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m01_couplers_to_m01_couplers_WVALID;
S_AXI_arready <= m01_couplers_to_m01_couplers_ARREADY;
S_AXI_awready <= m01_couplers_to_m01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m01_couplers_to_m01_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m01_couplers_to_m01_couplers_RVALID;
S_AXI_wready <= m01_couplers_to_m01_couplers_WREADY;
m01_couplers_to_m01_couplers_ARADDR(8 downto 0) <= S_AXI_araddr(8 downto 0);
m01_couplers_to_m01_couplers_ARREADY <= M_AXI_arready;
m01_couplers_to_m01_couplers_ARVALID <= S_AXI_arvalid;
m01_couplers_to_m01_couplers_AWADDR(8 downto 0) <= S_AXI_awaddr(8 downto 0);
m01_couplers_to_m01_couplers_AWREADY <= M_AXI_awready;
m01_couplers_to_m01_couplers_AWVALID <= S_AXI_awvalid;
m01_couplers_to_m01_couplers_BREADY <= S_AXI_bready;
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID <= M_AXI_bvalid;
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY <= S_AXI_rready;
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID <= M_AXI_rvalid;
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY <= M_AXI_wready;
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_1QFTZ3X is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m02_couplers_imp_1QFTZ3X;
architecture STRUCTURE of m02_couplers_imp_1QFTZ3X is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(10 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(10 downto 0);
M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID;
M_AXI_awaddr(10 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(10 downto 0);
M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID;
M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY;
M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID;
S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY;
S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID;
S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY;
m02_couplers_to_m02_couplers_ARADDR(10 downto 0) <= S_AXI_araddr(10 downto 0);
m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready;
m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid;
m02_couplers_to_m02_couplers_AWADDR(10 downto 0) <= S_AXI_awaddr(10 downto 0);
m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready;
m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid;
m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready;
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid;
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready;
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid;
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready;
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1AHKP6S is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1AHKP6S;
architecture STRUCTURE of s00_couplers_imp_1AHKP6S is
component cpu_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component cpu_auto_pc_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
signal NLW_auto_pc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_auto_pc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component cpu_auto_pc_1
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => NLW_auto_pc_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => NLW_auto_pc_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_B67PN0 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_B67PN0;
architecture STRUCTURE of s00_couplers_imp_B67PN0 is
component cpu_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component cpu_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component cpu_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity cpu_processing_system7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M01_AXI_arready : in STD_LOGIC;
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M01_AXI_awready : in STD_LOGIC;
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC;
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC;
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC;
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
M02_AXI_arready : in STD_LOGIC;
M02_AXI_arvalid : out STD_LOGIC;
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
M02_AXI_awready : in STD_LOGIC;
M02_AXI_awvalid : out STD_LOGIC;
M02_AXI_bready : out STD_LOGIC;
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC;
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC;
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC;
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC;
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end cpu_processing_system7_0_axi_periph_0;
architecture STRUCTURE of cpu_processing_system7_0_axi_periph_0 is
component cpu_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 )
);
end component cpu_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(8 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARADDR(8 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M00_AXI_awaddr(8 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWADDR(8 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(8 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARADDR(8 downto 0);
M01_AXI_arvalid <= m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
M01_AXI_awaddr(8 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWADDR(8 downto 0);
M01_AXI_awvalid <= m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
M01_AXI_bready <= m01_couplers_to_processing_system7_0_axi_periph_BREADY;
M01_AXI_rready <= m01_couplers_to_processing_system7_0_axi_periph_RREADY;
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid <= m01_couplers_to_processing_system7_0_axi_periph_WVALID;
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1(0) <= M02_ARESETN(0);
M02_AXI_araddr(10 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_ARADDR(10 downto 0);
M02_AXI_arvalid <= m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
M02_AXI_awaddr(10 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_AWADDR(10 downto 0);
M02_AXI_awvalid <= m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
M02_AXI_bready <= m02_couplers_to_processing_system7_0_axi_periph_BREADY;
M02_AXI_rready <= m02_couplers_to_processing_system7_0_axi_periph_RREADY;
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M02_AXI_wvalid <= m02_couplers_to_processing_system7_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY;
m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M00_AXI_wready(0);
m01_couplers_to_processing_system7_0_axi_periph_ARREADY <= M01_AXI_arready;
m01_couplers_to_processing_system7_0_axi_periph_AWREADY <= M01_AXI_awready;
m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_BVALID <= M01_AXI_bvalid;
m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RVALID <= M01_AXI_rvalid;
m01_couplers_to_processing_system7_0_axi_periph_WREADY <= M01_AXI_wready;
m02_couplers_to_processing_system7_0_axi_periph_ARREADY <= M02_AXI_arready;
m02_couplers_to_processing_system7_0_axi_periph_AWREADY <= M02_AXI_awready;
m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_BVALID <= M02_AXI_bvalid;
m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RVALID <= M02_AXI_rvalid;
m02_couplers_to_processing_system7_0_axi_periph_WREADY <= M02_AXI_wready;
processing_system7_0_axi_periph_ACLK_net <= ACLK;
processing_system7_0_axi_periph_ARESETN_net(0) <= ARESETN(0);
processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers: entity work.m00_couplers_imp_ZVW4AE
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(8 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARADDR(8 downto 0),
M_AXI_arready(0) => m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(8 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWADDR(8 downto 0),
M_AXI_awready(0) => m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m00_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m00_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m00_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(8 downto 0) => xbar_to_m00_couplers_ARADDR(8 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(8 downto 0) => xbar_to_m00_couplers_AWADDR(8 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_PQKNCJ
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(8 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARADDR(8 downto 0),
M_AXI_arready => m01_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m01_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(8 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWADDR(8 downto 0),
M_AXI_awready => m01_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m01_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m01_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m01_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m01_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m01_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m01_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m01_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(8 downto 0) => xbar_to_m01_couplers_ARADDR(40 downto 32),
S_AXI_arready => xbar_to_m01_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(8 downto 0) => xbar_to_m01_couplers_AWADDR(40 downto 32),
S_AXI_awready => xbar_to_m01_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready => xbar_to_m01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_1QFTZ3X
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN(0) => M02_ARESETN_1(0),
M_AXI_araddr(10 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_ARADDR(10 downto 0),
M_AXI_arready => m02_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m02_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(10 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_AWADDR(10 downto 0),
M_AXI_awready => m02_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m02_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m02_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m02_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m02_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m02_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m02_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m02_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(10 downto 0) => xbar_to_m02_couplers_ARADDR(74 downto 64),
S_AXI_arready => xbar_to_m02_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(10 downto 0) => xbar_to_m02_couplers_AWADDR(74 downto 64),
S_AXI_awready => xbar_to_m02_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready => xbar_to_m02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
);
s00_couplers: entity work.s00_couplers_imp_B67PN0
port map (
M_ACLK => processing_system7_0_axi_periph_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID
);
xbar: component cpu_xbar_0
port map (
aclk => processing_system7_0_axi_periph_ACLK_net,
aresetn => processing_system7_0_axi_periph_ARESETN_net(0),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(8 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(8 downto 0),
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(8 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(8 downto 0),
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity cpu_processing_system7_0_axi_periph_1_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end cpu_processing_system7_0_axi_periph_1_0;
architecture STRUCTURE of cpu_processing_system7_0_axi_periph_1_0 is
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_1_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_1_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_1_ARREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_ARVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_1_AWREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_AWVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_BREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_1_BVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_1_RREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_1_RVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_1_WREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_1_WVALID : STD_LOGIC;
begin
M00_AXI_araddr(31 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_1_ARADDR(31 downto 0);
M00_AXI_arvalid <= s00_couplers_to_processing_system7_0_axi_periph_1_ARVALID;
M00_AXI_awaddr(31 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_1_AWADDR(31 downto 0);
M00_AXI_awvalid <= s00_couplers_to_processing_system7_0_axi_periph_1_AWVALID;
M00_AXI_bready <= s00_couplers_to_processing_system7_0_axi_periph_1_BREADY;
M00_AXI_rready <= s00_couplers_to_processing_system7_0_axi_periph_1_RREADY;
M00_AXI_wdata(31 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_1_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_1_WSTRB(3 downto 0);
M00_AXI_wvalid <= s00_couplers_to_processing_system7_0_axi_periph_1_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_1_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_1_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_1_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_1_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_1_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_1_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_1_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_1_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_1_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_1_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_1_to_s00_couplers_WREADY;
processing_system7_0_axi_periph_1_ACLK_net <= M00_ACLK;
processing_system7_0_axi_periph_1_ARESETN_net(0) <= M00_ARESETN(0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_1_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_1_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_1_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_1_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_1_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_WVALID <= S00_AXI_wvalid;
s00_couplers_to_processing_system7_0_axi_periph_1_ARREADY <= M00_AXI_arready;
s00_couplers_to_processing_system7_0_axi_periph_1_AWREADY <= M00_AXI_awready;
s00_couplers_to_processing_system7_0_axi_periph_1_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
s00_couplers_to_processing_system7_0_axi_periph_1_BVALID <= M00_AXI_bvalid;
s00_couplers_to_processing_system7_0_axi_periph_1_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
s00_couplers_to_processing_system7_0_axi_periph_1_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
s00_couplers_to_processing_system7_0_axi_periph_1_RVALID <= M00_AXI_rvalid;
s00_couplers_to_processing_system7_0_axi_periph_1_WREADY <= M00_AXI_wready;
s00_couplers: entity work.s00_couplers_imp_1AHKP6S
port map (
M_ACLK => processing_system7_0_axi_periph_1_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_1_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_1_ARADDR(31 downto 0),
M_AXI_arready => s00_couplers_to_processing_system7_0_axi_periph_1_ARREADY,
M_AXI_arvalid => s00_couplers_to_processing_system7_0_axi_periph_1_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_1_AWADDR(31 downto 0),
M_AXI_awready => s00_couplers_to_processing_system7_0_axi_periph_1_AWREADY,
M_AXI_awvalid => s00_couplers_to_processing_system7_0_axi_periph_1_AWVALID,
M_AXI_bready => s00_couplers_to_processing_system7_0_axi_periph_1_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_1_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_processing_system7_0_axi_periph_1_BVALID,
M_AXI_rdata(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_1_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_processing_system7_0_axi_periph_1_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_1_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_processing_system7_0_axi_periph_1_RVALID,
M_AXI_wdata(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_1_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_processing_system7_0_axi_periph_1_WREADY,
M_AXI_wstrb(3 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_1_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_processing_system7_0_axi_periph_1_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_1_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_1_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_1_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_1_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_1_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_1_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_1_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_1_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_1_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_1_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_1_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_1_to_s00_couplers_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity cpu is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
EPC_INTF_addr : out STD_LOGIC_VECTOR ( 0 to 31 );
EPC_INTF_ads : out STD_LOGIC;
EPC_INTF_be : out STD_LOGIC_VECTOR ( 0 to 3 );
EPC_INTF_burst : out STD_LOGIC;
EPC_INTF_clk : in STD_LOGIC;
EPC_INTF_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
EPC_INTF_data_i : in STD_LOGIC_VECTOR ( 0 to 31 );
EPC_INTF_data_o : out STD_LOGIC_VECTOR ( 0 to 31 );
EPC_INTF_data_t : out STD_LOGIC_VECTOR ( 0 to 31 );
EPC_INTF_rd_n : out STD_LOGIC;
EPC_INTF_rdy : in STD_LOGIC_VECTOR ( 0 to 0 );
EPC_INTF_rnw : out STD_LOGIC;
EPC_INTF_rst : in STD_LOGIC;
EPC_INTF_wr_n : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
GPIO_tri_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
GPIO_tri_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
GPIO_tri_t : out STD_LOGIC_VECTOR ( 15 downto 0 );
IIC_0_scl_i : in STD_LOGIC;
IIC_0_scl_o : out STD_LOGIC;
IIC_0_scl_t : out STD_LOGIC;
IIC_0_sda_i : in STD_LOGIC;
IIC_0_sda_o : out STD_LOGIC;
IIC_0_sda_t : out STD_LOGIC;
IIC_1_scl_i : in STD_LOGIC;
IIC_1_scl_o : out STD_LOGIC;
IIC_1_scl_t : out STD_LOGIC;
IIC_1_sda_i : in STD_LOGIC;
IIC_1_sda_o : out STD_LOGIC;
IIC_1_sda_t : out STD_LOGIC;
IIC_scl_i : in STD_LOGIC;
IIC_scl_o : out STD_LOGIC;
IIC_scl_t : out STD_LOGIC;
IIC_sda_i : in STD_LOGIC;
IIC_sda_o : out STD_LOGIC;
IIC_sda_t : out STD_LOGIC;
Int0 : in STD_LOGIC_VECTOR ( 0 to 0 );
Int1 : in STD_LOGIC_VECTOR ( 0 to 0 );
Int2 : in STD_LOGIC_VECTOR ( 0 to 0 );
Int3 : in STD_LOGIC_VECTOR ( 0 to 0 );
OCXO_CLK100 : in STD_LOGIC;
OCXO_RESETN : out STD_LOGIC_VECTOR ( 0 to 0 );
UART_0_rxd : in STD_LOGIC;
UART_0_txd : out STD_LOGIC;
Vp_Vn_v_n : in STD_LOGIC;
Vp_Vn_v_p : in STD_LOGIC
);
end cpu;
architecture STRUCTURE of cpu is
component cpu_processing_system7_0_0 is
port (
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 5 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component cpu_processing_system7_0_0;
component cpu_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component cpu_axi_gpio_0_0;
component cpu_rst_processing_system7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component cpu_rst_processing_system7_0_100M_0;
component cpu_axi_iic_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
iic2intc_irpt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
sda_t : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
scl_t : out STD_LOGIC;
gpo : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component cpu_axi_iic_0_0;
component cpu_axi_epc_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
prh_clk : in STD_LOGIC;
prh_rst : in STD_LOGIC;
prh_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
prh_addr : out STD_LOGIC_VECTOR ( 0 to 31 );
prh_ads : out STD_LOGIC;
prh_be : out STD_LOGIC_VECTOR ( 0 to 3 );
prh_rnw : out STD_LOGIC;
prh_rd_n : out STD_LOGIC;
prh_wr_n : out STD_LOGIC;
prh_burst : out STD_LOGIC;
prh_rdy : in STD_LOGIC_VECTOR ( 0 to 0 );
prh_data_i : in STD_LOGIC_VECTOR ( 0 to 31 );
prh_data_o : out STD_LOGIC_VECTOR ( 0 to 31 );
prh_data_t : out STD_LOGIC_VECTOR ( 0 to 31 )
);
end component cpu_axi_epc_0_0;
component cpu_rst_M_AXI_GP1_ACLK_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component cpu_rst_M_AXI_GP1_ACLK_100M_0;
component cpu_xlconcat_0_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
In2 : in STD_LOGIC_VECTOR ( 0 to 0 );
In3 : in STD_LOGIC_VECTOR ( 0 to 0 );
In4 : in STD_LOGIC_VECTOR ( 0 to 0 );
In5 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
end component cpu_xlconcat_0_0;
component cpu_xadc_wiz_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
vp_in : in STD_LOGIC;
vn_in : in STD_LOGIC;
user_temp_alarm_out : out STD_LOGIC;
vccint_alarm_out : out STD_LOGIC;
vccaux_alarm_out : out STD_LOGIC;
vccpint_alarm_out : out STD_LOGIC;
vccpaux_alarm_out : out STD_LOGIC;
vccddro_alarm_out : out STD_LOGIC;
ot_out : out STD_LOGIC;
channel_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
eoc_out : out STD_LOGIC;
alarm_out : out STD_LOGIC;
eos_out : out STD_LOGIC;
busy_out : out STD_LOGIC
);
end component cpu_xadc_wiz_0_0;
signal GND_1 : STD_LOGIC;
signal In4_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal In5_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal Int0_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal Int1_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M_AXI_GP0_ACLK_1 : STD_LOGIC;
signal M_AXI_GP1_ACLK_1 : STD_LOGIC;
signal VCC_1 : STD_LOGIC;
signal Vp_Vn_1_V_N : STD_LOGIC;
signal Vp_Vn_1_V_P : STD_LOGIC;
signal axi_epc_0_EPC_INTF_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
signal axi_epc_0_EPC_INTF_ADS : STD_LOGIC;
signal axi_epc_0_EPC_INTF_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal axi_epc_0_EPC_INTF_BURST : STD_LOGIC;
signal axi_epc_0_EPC_INTF_CLK : STD_LOGIC;
signal axi_epc_0_EPC_INTF_CS_N : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_epc_0_EPC_INTF_DATA_I : STD_LOGIC_VECTOR ( 0 to 31 );
signal axi_epc_0_EPC_INTF_DATA_O : STD_LOGIC_VECTOR ( 0 to 31 );
signal axi_epc_0_EPC_INTF_DATA_T : STD_LOGIC_VECTOR ( 0 to 31 );
signal axi_epc_0_EPC_INTF_RDY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_epc_0_EPC_INTF_RD_N : STD_LOGIC;
signal axi_epc_0_EPC_INTF_RNW : STD_LOGIC;
signal axi_epc_0_EPC_INTF_RST : STD_LOGIC;
signal axi_epc_0_EPC_INTF_WR_N : STD_LOGIC;
signal axi_gpio_0_GPIO_TRI_I : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_gpio_0_GPIO_TRI_O : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_gpio_0_GPIO_TRI_T : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_iic_0_IIC_SCL_I : STD_LOGIC;
signal axi_iic_0_IIC_SCL_O : STD_LOGIC;
signal axi_iic_0_IIC_SCL_T : STD_LOGIC;
signal axi_iic_0_IIC_SDA_I : STD_LOGIC;
signal axi_iic_0_IIC_SDA_O : STD_LOGIC;
signal axi_iic_0_IIC_SDA_T : STD_LOGIC;
signal axi_iic_0_iic2intc_irpt : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_IIC_0_SCL_I : STD_LOGIC;
signal processing_system7_0_IIC_0_SCL_O : STD_LOGIC;
signal processing_system7_0_IIC_0_SCL_T : STD_LOGIC;
signal processing_system7_0_IIC_0_SDA_I : STD_LOGIC;
signal processing_system7_0_IIC_0_SDA_O : STD_LOGIC;
signal processing_system7_0_IIC_0_SDA_T : STD_LOGIC;
signal processing_system7_0_IIC_1_SCL_I : STD_LOGIC;
signal processing_system7_0_IIC_1_SCL_O : STD_LOGIC;
signal processing_system7_0_IIC_1_SCL_T : STD_LOGIC;
signal processing_system7_0_IIC_1_SDA_I : STD_LOGIC;
signal processing_system7_0_IIC_1_SDA_O : STD_LOGIC;
signal processing_system7_0_IIC_1_SDA_T : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP1_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP1_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP1_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP1_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP1_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP1_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP1_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP1_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP1_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP1_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP1_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP1_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP1_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP1_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP1_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP1_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP1_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP1_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP1_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP1_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP1_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP1_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP1_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP1_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP1_WVALID : STD_LOGIC;
signal processing_system7_0_UART_0_RxD : STD_LOGIC;
signal processing_system7_0_UART_0_TxD : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_1_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_1_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_1_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_1_M00_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_1_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_1_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_1_M00_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_WVALID : STD_LOGIC;
signal rst_M_AXI_GP1_ACLK_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal xadc_wiz_0_ip2intc_irpt : STD_LOGIC;
signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_axi_iic_0_gpo_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_M_AXI_GP1_ACLK_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_M_AXI_GP1_ACLK_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_M_AXI_GP1_ACLK_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xadc_wiz_0_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_busy_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_eoc_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_eos_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_ot_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_user_temp_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_vccaux_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_vccddro_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_vccint_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_vccpaux_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_vccpint_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_channel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
EPC_INTF_addr(0 to 31) <= axi_epc_0_EPC_INTF_ADDR(0 to 31);
EPC_INTF_ads <= axi_epc_0_EPC_INTF_ADS;
EPC_INTF_be(0 to 3) <= axi_epc_0_EPC_INTF_BE(0 to 3);
EPC_INTF_burst <= axi_epc_0_EPC_INTF_BURST;
EPC_INTF_cs_n(0) <= axi_epc_0_EPC_INTF_CS_N(0);
EPC_INTF_data_o(0 to 31) <= axi_epc_0_EPC_INTF_DATA_O(0 to 31);
EPC_INTF_data_t(0 to 31) <= axi_epc_0_EPC_INTF_DATA_T(0 to 31);
EPC_INTF_rd_n <= axi_epc_0_EPC_INTF_RD_N;
EPC_INTF_rnw <= axi_epc_0_EPC_INTF_RNW;
EPC_INTF_wr_n <= axi_epc_0_EPC_INTF_WR_N;
FCLK_CLK0 <= M_AXI_GP0_ACLK_1;
FCLK_RESET0_N <= processing_system7_0_FCLK_RESET0_N;
GPIO_tri_o(15 downto 0) <= axi_gpio_0_GPIO_TRI_O(15 downto 0);
GPIO_tri_t(15 downto 0) <= axi_gpio_0_GPIO_TRI_T(15 downto 0);
IIC_0_scl_o <= processing_system7_0_IIC_0_SCL_O;
IIC_0_scl_t <= processing_system7_0_IIC_0_SCL_T;
IIC_0_sda_o <= processing_system7_0_IIC_0_SDA_O;
IIC_0_sda_t <= processing_system7_0_IIC_0_SDA_T;
IIC_1_scl_o <= processing_system7_0_IIC_1_SCL_O;
IIC_1_scl_t <= processing_system7_0_IIC_1_SCL_T;
IIC_1_sda_o <= processing_system7_0_IIC_1_SDA_O;
IIC_1_sda_t <= processing_system7_0_IIC_1_SDA_T;
IIC_scl_o <= axi_iic_0_IIC_SCL_O;
IIC_scl_t <= axi_iic_0_IIC_SCL_T;
IIC_sda_o <= axi_iic_0_IIC_SDA_O;
IIC_sda_t <= axi_iic_0_IIC_SDA_T;
In4_1(0) <= Int2(0);
In5_1(0) <= Int3(0);
Int0_1(0) <= Int0(0);
Int1_1(0) <= Int1(0);
M_AXI_GP1_ACLK_1 <= OCXO_CLK100;
OCXO_RESETN(0) <= rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn(0);
UART_0_txd <= processing_system7_0_UART_0_TxD;
Vp_Vn_1_V_N <= Vp_Vn_v_n;
Vp_Vn_1_V_P <= Vp_Vn_v_p;
axi_epc_0_EPC_INTF_CLK <= EPC_INTF_clk;
axi_epc_0_EPC_INTF_DATA_I(0 to 31) <= EPC_INTF_data_i(0 to 31);
axi_epc_0_EPC_INTF_RDY(0) <= EPC_INTF_rdy(0);
axi_epc_0_EPC_INTF_RST <= EPC_INTF_rst;
axi_gpio_0_GPIO_TRI_I(15 downto 0) <= GPIO_tri_i(15 downto 0);
axi_iic_0_IIC_SCL_I <= IIC_scl_i;
axi_iic_0_IIC_SDA_I <= IIC_sda_i;
processing_system7_0_IIC_0_SCL_I <= IIC_0_scl_i;
processing_system7_0_IIC_0_SDA_I <= IIC_0_sda_i;
processing_system7_0_IIC_1_SCL_I <= IIC_1_scl_i;
processing_system7_0_IIC_1_SDA_I <= IIC_1_sda_i;
processing_system7_0_UART_0_RxD <= UART_0_rxd;
GND: unisim.vcomponents.GND
port map (
G => GND_1
);
VCC: unisim.vcomponents.VCC
port map (
P => VCC_1
);
axi_epc_0: component cpu_axi_epc_0_0
port map (
prh_addr(0 to 31) => axi_epc_0_EPC_INTF_ADDR(0 to 31),
prh_ads => axi_epc_0_EPC_INTF_ADS,
prh_be(0 to 3) => axi_epc_0_EPC_INTF_BE(0 to 3),
prh_burst => axi_epc_0_EPC_INTF_BURST,
prh_clk => axi_epc_0_EPC_INTF_CLK,
prh_cs_n(0) => axi_epc_0_EPC_INTF_CS_N(0),
prh_data_i(0 to 31) => axi_epc_0_EPC_INTF_DATA_I(0 to 31),
prh_data_o(0 to 31) => axi_epc_0_EPC_INTF_DATA_O(0 to 31),
prh_data_t(0 to 31) => axi_epc_0_EPC_INTF_DATA_T(0 to 31),
prh_rd_n => axi_epc_0_EPC_INTF_RD_N,
prh_rdy(0) => axi_epc_0_EPC_INTF_RDY(0),
prh_rnw => axi_epc_0_EPC_INTF_RNW,
prh_rst => axi_epc_0_EPC_INTF_RST,
prh_wr_n => axi_epc_0_EPC_INTF_WR_N,
s_axi_aclk => M_AXI_GP1_ACLK_1,
s_axi_araddr(31 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_ARADDR(31 downto 0),
s_axi_aresetn => rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn(0),
s_axi_arready => processing_system7_0_axi_periph_1_M00_AXI_ARREADY,
s_axi_arvalid => processing_system7_0_axi_periph_1_M00_AXI_ARVALID,
s_axi_awaddr(31 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_AWADDR(31 downto 0),
s_axi_awready => processing_system7_0_axi_periph_1_M00_AXI_AWREADY,
s_axi_awvalid => processing_system7_0_axi_periph_1_M00_AXI_AWVALID,
s_axi_bready => processing_system7_0_axi_periph_1_M00_AXI_BREADY,
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_1_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_RDATA(31 downto 0),
s_axi_rready => processing_system7_0_axi_periph_1_M00_AXI_RREADY,
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_1_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_WDATA(31 downto 0),
s_axi_wready => processing_system7_0_axi_periph_1_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_1_M00_AXI_WVALID
);
axi_gpio_0: component cpu_axi_gpio_0_0
port map (
gpio_io_i(15 downto 0) => axi_gpio_0_GPIO_TRI_I(15 downto 0),
gpio_io_o(15 downto 0) => axi_gpio_0_GPIO_TRI_O(15 downto 0),
gpio_io_t(15 downto 0) => axi_gpio_0_GPIO_TRI_T(15 downto 0),
s_axi_aclk => M_AXI_GP0_ACLK_1,
s_axi_araddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axi_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
s_axi_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
s_axi_awaddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(8 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
s_axi_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
s_axi_bready => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s_axi_rready => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s_axi_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID(0)
);
axi_iic_0: component cpu_axi_iic_0_0
port map (
gpo(0) => NLW_axi_iic_0_gpo_UNCONNECTED(0),
iic2intc_irpt => axi_iic_0_iic2intc_irpt,
s_axi_aclk => M_AXI_GP0_ACLK_1,
s_axi_araddr(8 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axi_arready => processing_system7_0_axi_periph_M01_AXI_ARREADY,
s_axi_arvalid => processing_system7_0_axi_periph_M01_AXI_ARVALID,
s_axi_awaddr(8 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(8 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M01_AXI_AWREADY,
s_axi_awvalid => processing_system7_0_axi_periph_M01_AXI_AWVALID,
s_axi_bready => processing_system7_0_axi_periph_M01_AXI_BREADY,
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M01_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_rready => processing_system7_0_axi_periph_M01_AXI_RREADY,
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M01_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_wready => processing_system7_0_axi_periph_M01_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M01_AXI_WVALID,
scl_i => axi_iic_0_IIC_SCL_I,
scl_o => axi_iic_0_IIC_SCL_O,
scl_t => axi_iic_0_IIC_SCL_T,
sda_i => axi_iic_0_IIC_SDA_I,
sda_o => axi_iic_0_IIC_SDA_O,
sda_t => axi_iic_0_IIC_SDA_T
);
processing_system7_0: component cpu_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
ENET0_PTP_DELAY_REQ_RX => NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_processing_system7_0_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_processing_system7_0_ENET0_SOF_TX_UNCONNECTED,
FCLK_CLK0 => M_AXI_GP0_ACLK_1,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
I2C0_SCL_I => processing_system7_0_IIC_0_SCL_I,
I2C0_SCL_O => processing_system7_0_IIC_0_SCL_O,
I2C0_SCL_T => processing_system7_0_IIC_0_SCL_T,
I2C0_SDA_I => processing_system7_0_IIC_0_SDA_I,
I2C0_SDA_O => processing_system7_0_IIC_0_SDA_O,
I2C0_SDA_T => processing_system7_0_IIC_0_SDA_T,
I2C1_SCL_I => processing_system7_0_IIC_1_SCL_I,
I2C1_SCL_O => processing_system7_0_IIC_1_SCL_O,
I2C1_SCL_T => processing_system7_0_IIC_1_SCL_T,
I2C1_SDA_I => processing_system7_0_IIC_1_SDA_I,
I2C1_SDA_O => processing_system7_0_IIC_1_SDA_O,
I2C1_SDA_T => processing_system7_0_IIC_1_SDA_T,
IRQ_F2P(5 downto 0) => xlconcat_0_dout(5 downto 0),
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK_1,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => M_AXI_GP1_ACLK_1,
M_AXI_GP1_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP1_ARADDR(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP1_ARBURST(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP1_ARCACHE(3 downto 0),
M_AXI_GP1_ARID(11 downto 0) => processing_system7_0_M_AXI_GP1_ARID(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP1_ARLEN(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP1_ARLOCK(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP1_ARPROT(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP1_ARQOS(3 downto 0),
M_AXI_GP1_ARREADY => processing_system7_0_M_AXI_GP1_ARREADY,
M_AXI_GP1_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP1_ARSIZE(2 downto 0),
M_AXI_GP1_ARVALID => processing_system7_0_M_AXI_GP1_ARVALID,
M_AXI_GP1_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP1_AWADDR(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP1_AWBURST(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP1_AWCACHE(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => processing_system7_0_M_AXI_GP1_AWID(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP1_AWLEN(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP1_AWLOCK(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP1_AWPROT(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP1_AWQOS(3 downto 0),
M_AXI_GP1_AWREADY => processing_system7_0_M_AXI_GP1_AWREADY,
M_AXI_GP1_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP1_AWSIZE(2 downto 0),
M_AXI_GP1_AWVALID => processing_system7_0_M_AXI_GP1_AWVALID,
M_AXI_GP1_BID(11 downto 0) => processing_system7_0_M_AXI_GP1_BID(11 downto 0),
M_AXI_GP1_BREADY => processing_system7_0_M_AXI_GP1_BREADY,
M_AXI_GP1_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP1_BRESP(1 downto 0),
M_AXI_GP1_BVALID => processing_system7_0_M_AXI_GP1_BVALID,
M_AXI_GP1_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP1_RDATA(31 downto 0),
M_AXI_GP1_RID(11 downto 0) => processing_system7_0_M_AXI_GP1_RID(11 downto 0),
M_AXI_GP1_RLAST => processing_system7_0_M_AXI_GP1_RLAST,
M_AXI_GP1_RREADY => processing_system7_0_M_AXI_GP1_RREADY,
M_AXI_GP1_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP1_RRESP(1 downto 0),
M_AXI_GP1_RVALID => processing_system7_0_M_AXI_GP1_RVALID,
M_AXI_GP1_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP1_WDATA(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => processing_system7_0_M_AXI_GP1_WID(11 downto 0),
M_AXI_GP1_WLAST => processing_system7_0_M_AXI_GP1_WLAST,
M_AXI_GP1_WREADY => processing_system7_0_M_AXI_GP1_WREADY,
M_AXI_GP1_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP1_WSTRB(3 downto 0),
M_AXI_GP1_WVALID => processing_system7_0_M_AXI_GP1_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
UART0_RX => processing_system7_0_UART_0_RxD,
UART0_TX => processing_system7_0_UART_0_TxD,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => GND_1,
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
processing_system7_0_axi_periph: entity work.cpu_processing_system7_0_axi_periph_0
port map (
ACLK => M_AXI_GP0_ACLK_1,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => M_AXI_GP0_ACLK_1,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(8 downto 0),
M00_AXI_arready(0) => processing_system7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid(0) => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
M00_AXI_awaddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(8 downto 0),
M00_AXI_awready(0) => processing_system7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid(0) => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
M00_AXI_bready(0) => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => processing_system7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready(0) => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => processing_system7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready(0) => processing_system7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid(0) => processing_system7_0_axi_periph_M00_AXI_WVALID(0),
M01_ACLK => M_AXI_GP0_ACLK_1,
M01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M01_AXI_araddr(8 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(8 downto 0),
M01_AXI_arready => processing_system7_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid => processing_system7_0_axi_periph_M01_AXI_ARVALID,
M01_AXI_awaddr(8 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(8 downto 0),
M01_AXI_awready => processing_system7_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid => processing_system7_0_axi_periph_M01_AXI_AWVALID,
M01_AXI_bready => processing_system7_0_axi_periph_M01_AXI_BREADY,
M01_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid => processing_system7_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready => processing_system7_0_axi_periph_M01_AXI_RREADY,
M01_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid => processing_system7_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready => processing_system7_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid => processing_system7_0_axi_periph_M01_AXI_WVALID,
M02_ACLK => M_AXI_GP0_ACLK_1,
M02_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M02_AXI_araddr(10 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(10 downto 0),
M02_AXI_arready => processing_system7_0_axi_periph_M02_AXI_ARREADY,
M02_AXI_arvalid => processing_system7_0_axi_periph_M02_AXI_ARVALID,
M02_AXI_awaddr(10 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(10 downto 0),
M02_AXI_awready => processing_system7_0_axi_periph_M02_AXI_AWREADY,
M02_AXI_awvalid => processing_system7_0_axi_periph_M02_AXI_AWVALID,
M02_AXI_bready => processing_system7_0_axi_periph_M02_AXI_BREADY,
M02_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid => processing_system7_0_axi_periph_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready => processing_system7_0_axi_periph_M02_AXI_RREADY,
M02_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid => processing_system7_0_axi_periph_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready => processing_system7_0_axi_periph_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid => processing_system7_0_axi_periph_M02_AXI_WVALID,
S00_ACLK => M_AXI_GP0_ACLK_1,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
processing_system7_0_axi_periph_1: entity work.cpu_processing_system7_0_axi_periph_1_0
port map (
ACLK => M_AXI_GP1_ACLK_1,
ARESETN(0) => rst_M_AXI_GP1_ACLK_100M_interconnect_aresetn(0),
M00_ACLK => M_AXI_GP1_ACLK_1,
M00_ARESETN(0) => rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arready => processing_system7_0_axi_periph_1_M00_AXI_ARREADY,
M00_AXI_arvalid => processing_system7_0_axi_periph_1_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awready => processing_system7_0_axi_periph_1_M00_AXI_AWREADY,
M00_AXI_awvalid => processing_system7_0_axi_periph_1_M00_AXI_AWVALID,
M00_AXI_bready => processing_system7_0_axi_periph_1_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => processing_system7_0_axi_periph_1_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => processing_system7_0_axi_periph_1_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => processing_system7_0_axi_periph_1_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => processing_system7_0_axi_periph_1_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => processing_system7_0_axi_periph_1_M00_AXI_WVALID,
S00_ACLK => M_AXI_GP1_ACLK_1,
S00_ARESETN(0) => rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP1_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP1_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP1_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP1_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP1_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP1_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP1_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP1_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP1_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP1_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP1_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP1_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP1_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP1_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP1_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP1_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP1_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP1_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP1_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP1_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP1_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP1_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP1_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP1_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP1_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP1_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP1_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP1_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP1_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP1_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP1_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP1_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP1_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP1_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP1_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP1_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP1_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP1_WVALID
);
rst_M_AXI_GP1_ACLK_100M: component cpu_rst_M_AXI_GP1_ACLK_100M_0
port map (
aux_reset_in => VCC_1,
bus_struct_reset(0) => NLW_rst_M_AXI_GP1_ACLK_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => VCC_1,
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_M_AXI_GP1_ACLK_100M_interconnect_aresetn(0),
mb_debug_sys_rst => GND_1,
mb_reset => NLW_rst_M_AXI_GP1_ACLK_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_M_AXI_GP1_ACLK_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => M_AXI_GP1_ACLK_1
);
rst_processing_system7_0_100M: component cpu_rst_processing_system7_0_100M_0
port map (
aux_reset_in => VCC_1,
bus_struct_reset(0) => NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => VCC_1,
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => GND_1,
mb_reset => NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => M_AXI_GP0_ACLK_1
);
xadc_wiz_0: component cpu_xadc_wiz_0_0
port map (
alarm_out => NLW_xadc_wiz_0_alarm_out_UNCONNECTED,
busy_out => NLW_xadc_wiz_0_busy_out_UNCONNECTED,
channel_out(4 downto 0) => NLW_xadc_wiz_0_channel_out_UNCONNECTED(4 downto 0),
eoc_out => NLW_xadc_wiz_0_eoc_out_UNCONNECTED,
eos_out => NLW_xadc_wiz_0_eos_out_UNCONNECTED,
ip2intc_irpt => xadc_wiz_0_ip2intc_irpt,
ot_out => NLW_xadc_wiz_0_ot_out_UNCONNECTED,
s_axi_aclk => M_AXI_GP0_ACLK_1,
s_axi_araddr(10 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(10 downto 0),
s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axi_arready => processing_system7_0_axi_periph_M02_AXI_ARREADY,
s_axi_arvalid => processing_system7_0_axi_periph_M02_AXI_ARVALID,
s_axi_awaddr(10 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(10 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M02_AXI_AWREADY,
s_axi_awvalid => processing_system7_0_axi_periph_M02_AXI_AWVALID,
s_axi_bready => processing_system7_0_axi_periph_M02_AXI_BREADY,
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M02_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
s_axi_rready => processing_system7_0_axi_periph_M02_AXI_RREADY,
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M02_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
s_axi_wready => processing_system7_0_axi_periph_M02_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M02_AXI_WVALID,
user_temp_alarm_out => NLW_xadc_wiz_0_user_temp_alarm_out_UNCONNECTED,
vccaux_alarm_out => NLW_xadc_wiz_0_vccaux_alarm_out_UNCONNECTED,
vccddro_alarm_out => NLW_xadc_wiz_0_vccddro_alarm_out_UNCONNECTED,
vccint_alarm_out => NLW_xadc_wiz_0_vccint_alarm_out_UNCONNECTED,
vccpaux_alarm_out => NLW_xadc_wiz_0_vccpaux_alarm_out_UNCONNECTED,
vccpint_alarm_out => NLW_xadc_wiz_0_vccpint_alarm_out_UNCONNECTED,
vn_in => Vp_Vn_1_V_N,
vp_in => Vp_Vn_1_V_P
);
xlconcat_0: component cpu_xlconcat_0_0
port map (
In0(0) => axi_iic_0_iic2intc_irpt,
In1(0) => xadc_wiz_0_ip2intc_irpt,
In2(0) => Int0_1(0),
In3(0) => Int1_1(0),
In4(0) => In4_1(0),
In5(0) => In5_1(0),
dout(5 downto 0) => xlconcat_0_dout(5 downto 0)
);
end STRUCTURE;
|
use work.p.all;
entity ent is
generic (
WIDTH : natural := 8
);
port (
test : in bit_vector(id(WIDTH)-1 downto 0)
);
end ent;
architecture a of ent is
begin
end a;
|
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_sha256
-- sha256.vhd is part of DS_sha256.
-- DS_sha256 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- DS_sha256 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all; -- std_logic
use ieee.numeric_std.all; -- to_integer()
entity sha256 is
port (
clk : in std_ulogic; -- clock
rstn : in std_ulogic; -- asynchronous active low reset
start : in std_ulogic;
M_i_j : in std_ulogic_vector(31 downto 0); -- 32-bit word of the i-th message block
M_j_memory_rcs_n : out std_ulogic; -- read chip select: when asserted low, memory can be read
M_j_memory_r_addr : out std_ulogic_vector(3 downto 0);
H_i_A,
H_i_B,
H_i_C,
H_i_D,
H_i_E,
H_i_F,
H_i_G,
H_i_H : out std_ulogic_vector(31 downto 0); -- resulting hash value H_(i)
done : out std_ulogic
);
end entity sha256;
architecture behav of sha256 is
-- datapath functions
function sigma0(
x: std_ulogic_vector
)
return std_ulogic_vector is
begin
return to_stdulogicvector((to_bitvector(x) ror 7) xor (to_bitvector(x) ror 18) xor (to_bitvector(x) srl 3));
end function sigma0;
function sigma1(
x: std_ulogic_vector
)
return std_ulogic_vector is
begin
return to_stdulogicvector((to_bitvector(x) ror 17) xor (to_bitvector(x) ror 19) xor (to_bitvector(x) srl 10));
end function sigma1;
function csigma0(
x: std_ulogic_vector
)
return std_ulogic_vector is
begin
return to_stdulogicvector((to_bitvector(x) ror 2) xor (to_bitvector(x) ror 13) xor (to_bitvector(x) ror 22));
end function csigma0;
function csigma1(
x: std_ulogic_vector
)
return std_ulogic_vector is
begin
return to_stdulogicvector((to_bitvector(x) ror 6) xor (to_bitvector(x) ror 11) xor (to_bitvector(x) ror 25));
end function csigma1;
function Maj(
x: std_ulogic_vector;
y: std_ulogic_vector;
z: std_ulogic_vector
)
return std_ulogic_vector is
begin
return (x and y) xor (x and z) xor (y and z);
end function Maj;
function Ch(
x: std_ulogic_vector;
y: std_ulogic_vector;
z: std_ulogic_vector
)
return std_ulogic_vector is
begin
return (x and y) xor ((not (x)) and z);
end function Ch;
function moduloAddition(
x: std_ulogic_vector;
y: std_ulogic_vector
)
return std_ulogic_vector is
variable tmp: std_ulogic_vector(x'length-1 downto 0) := std_ulogic_vector(unsigned(x) + unsigned(y));
begin
return tmp(31 downto 0);
end function moduloAddition;
-- NIST-defined Kj constant
type K_W_array_type is array(0 to 63) of std_ulogic_vector(31 downto 0);
constant K : K_W_array_type := (
x"428a2f98", x"71374491", x"b5c0fbcf", x"e9b5dba5", x"3956c25b", x"59f111f1", x"923f82a4", x"ab1c5ed5",
x"d807aa98", x"12835b01", x"243185be", x"550c7dc3", x"72be5d74", x"80deb1fe", x"9bdc06a7", x"c19bf174",
x"e49b69c1", x"efbe4786", x"0fc19dc6", x"240ca1cc", x"2de92c6f", x"4a7484aa", x"5cb0a9dc", x"76f988da",
x"983e5152", x"a831c66d", x"b00327c8", x"bf597fc7", x"c6e00bf3", x"d5a79147", x"06ca6351", x"14292967",
x"27b70a85", x"2e1b2138", x"4d2c6dfc", x"53380d13", x"650a7354", x"766a0abb", x"81c2c92e", x"92722c85",
x"a2bfe8a1", x"a81a664b", x"c24b8b70", x"c76c51a3", x"d192e819", x"d6990624", x"f40e3585", x"106aa070",
x"19a4c116", x"1e376c08", x"2748774c", x"34b0bcb5", x"391c0cb3", x"4ed8aa4a", x"5b9cca4f", x"682e6ff3",
x"748f82ee", x"78a5636f", x"84c87814", x"8cc70208", x"90befffa", x"a4506ceb", x"bef9a3f7", x"c67178f2"
);
-- initial hash value
type H_array_type is array(0 to 7) of std_ulogic_vector(31 downto 0);
constant H0 : H_array_type := (
x"6a09e667", x"bb67ae85", x"3c6ef372", x"a54ff53a",
x"510e527f", x"9b05688c", x"1f83d9ab", x"5be0cd19"
);
signal W : K_W_array_type;
signal counter : natural range 0 to 67;
signal j_expander, j_compressor, j_T : integer range -4 to 66;
signal T1, T2, A, B, C, D, E, F, G, H : std_ulogic_vector(31 downto 0);
begin
-- counter (control unit) process
process (clk, rstn)
begin
if rstn = '0' then
counter <= 0;
done <= '0';
elsif clk'event and clk = '1' then
done <= '0';
if ((start = '1' and counter = 0) or (counter > 0 and counter < 67)) then
counter <= counter + 1;
elsif (counter = 67) then
counter <= 0;
done <= '1';
end if;
end if;
end process;
-- expander process
process (clk, rstn)
variable j: integer range -2 to 65 := -2;
begin
j := counter - 2;
j_expander <= j;
if rstn = '0' then
W <= ((others => (others => '0')));
j := -2;
elsif clk'event and clk = '1' then
if (j >= 0 and j <= 15) then
W(j) <= M_i_j;
elsif (j > 15 and j < 64) then
W(j) <= moduloAddition(sigma1(W(j - 2)),
moduloAddition(W(j - 7),
moduloAddition(sigma0(W(j - 15)), W(j - 16)
)
)
);
end if;
end if;
end process;
-- compressor process
process (clk, rstn)
variable j: integer range -3 to 64 := -3;
begin
j := counter - 3;
j_compressor <= j;
if rstn = '0' or (start = '1' and counter = 0) then
A <= H0(0);
B <= H0(1);
C <= H0(2);
D <= H0(3);
E <= H0(4);
F <= H0(5);
G <= H0(6);
H <= H0(7);
j := -3;
elsif clk'event and clk = '1' then
if (j >= 0 and j < 64) then
-- compressor
H <= G;
G <= F;
F <= E;
E <= moduloAddition(D, T1);
D <= C;
C <= B;
B <= A;
A <= moduloAddition(T1, T2);
end if;
end if;
end process;
-- T1 and T2 computation for expander
process (clk, rstn)
variable j: integer range -3 to 64 := -3;
begin
j := counter - 3;
j_T <= j;
if rstn = '0' then
T1 <= (others => '0');
T2 <= (others => '0');
j := -3;
elsif clk'event and clk = '0' then
if (j >= 0 and j < 64) then
T1 <= moduloAddition(H,
moduloAddition(csigma1(E),
moduloAddition(Ch(E, F, G),
moduloAddition(K(j), W(j))
)
)
);
T2 <= moduloAddition(csigma0(A), Maj(A, B, C));
end if;
end if;
end process;
--output process
process (clk, rstn)
begin
if rstn = '0' then
H_i_A <= (others => '0');
H_i_B <= (others => '0');
H_i_C <= (others => '0');
H_i_D <= (others => '0');
H_i_E <= (others => '0');
H_i_F <= (others => '0');
H_i_G <= (others => '0');
H_i_H <= (others => '0');
elsif clk'event and clk = '0' then
if counter = 67 then
H_i_A <= moduloAddition(A, H0(0));
H_i_B <= moduloAddition(B, H0(1));
H_i_C <= moduloAddition(C, H0(2));
H_i_D <= moduloAddition(D, H0(3));
H_i_E <= moduloAddition(E, H0(4));
H_i_F <= moduloAddition(F, H0(5));
H_i_G <= moduloAddition(G, H0(6));
H_i_H <= moduloAddition(H, H0(7));
end if;
end if;
end process;
-- memory process
process (clk, rstn)
begin
if rstn = '0' then
M_j_memory_rcs_n <= '1';
M_j_memory_r_addr <= (others => 'Z');
elsif clk'event and clk = '1' then
if (start = '1' and counter = 0) or (counter > 0 and counter < 16) then
M_j_memory_rcs_n <= '0';
M_j_memory_r_addr <= std_ulogic_vector(to_unsigned(counter, 4));
else
M_j_memory_rcs_n <= '1';
M_j_memory_r_addr <= (others => 'Z');
end if;
end if;
end process;
end architecture behav; |
--!
--! \file first.vhd
--!
--! \author Ariane Keller
--! \date 29.07.2009
-- Demo file for the multibus. This file will be executed in slot 1.
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity first is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32;
C_NR_SLOTS : integer := 3
);
port (
-- user defined signals: use the signal names defined in the system.ucf file!
-- user defined signals only work if they are before the reconos signals!
-- Signals for the Multibus
ready_0 : out std_logic;
req_0 : out std_logic_vector(0 to 3 -1);
grant_0 : in std_logic_vector(0 to 3 - 1);
data_0 : out std_logic_vector(0 to 3 * 32 - 1);
sof_0 : out std_logic_vector(0 to C_NR_SLOTS - 1);
eof_0 : out std_logic_vector(0 to C_NR_SLOTS - 1);
src_rdy_0 : out std_logic_vector(0 to C_NR_SLOTS - 1);
dst_rdy_0 : in std_logic_vector(0 to C_NR_SLOTS - 1);
busdata_0 : in std_logic_vector(0 to 32 - 1);
bussof_0 : in std_logic;
buseof_0 : in std_logic;
bus_dst_rdy_0 : out std_logic;
bus_src_rdy_0 : in std_logic;
--- end user defined ports
-- normal reconOS signals
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- second ram
o_RAMAddr_x : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData_x : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData_x : in std_logic_vector(0 to C_BURST_DWIDTH-1); -- 32 bit
o_RAMWE_x : out std_logic;
o_RAMClk_x : out std_logic
);
end first;
architecture Behavioral of first is
-------------
-- constants
------------
constant C_MBOX_HANDLE_SW_HW : std_logic_vector(0 to 31) := X"00000000";
constant C_MBOX_HANDLE_HW_SW : std_logic_vector(0 to 31) := X"00000001";
-----------------
-- state machines
-----------------
type os_state is ( STATE_INIT,
STATE_SEND_ANSWER,
STATE_GET_COMMAND,
STATE_DECODE);
signal os_sync_state : os_state := STATE_INIT;
type s_state is ( S_STATE_INIT,
S_STATE_WAIT,
S_STATE_LOCK,
S_STATE_SEND_FIRST,
S_STATE_INTERM);
signal send_to_0_state : s_state;
signal send_to_0_state_next : s_state;
signal send_to_1_state : s_state;
signal send_to_1_state_next : s_state;
signal send_to_2_state : s_state;
signal send_to_2_state_next : s_state;
type r_state is ( R_STATE_INIT,
R_STATE_COUNT);
signal receive_state : r_state;
signal receive_state_next : r_state;
---------------------
-- Signal declaration
---------------------
-- bus signals (for communication between hw threats
signal to_0_data : std_logic_vector(0 to 32 - 1);
signal to_1_data : std_logic_vector(0 to 32 - 1);
signal to_2_data : std_logic_vector(0 to 32 - 1);
signal to_0_sof : std_logic;
signal to_1_sof : std_logic;
signal to_2_sof : std_logic;
signal to_1_eof : std_logic;
signal to_2_eof : std_logic;
signal to_0_eof : std_logic;
signal received_counter : natural;
signal received_counter_next: natural;
signal start_to_0 : std_logic;
signal s_0_counter : natural;
signal s_0_counter_next : natural;
signal start_to_1 : std_logic;
signal s_1_counter : natural;
signal s_1_counter_next : natural;
signal start_to_2 : std_logic;
signal s_2_counter : natural;
signal s_2_counter_next : natural;
--end signal declaration
begin
--default assignements
-- we don't need the memories
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWE <= '0';
o_RAMClk <= '0';
o_RAMAddr_x <= (others => '0');
o_RAMData_x <= (others => '0');
o_RAMWE_x <= '0';
o_RAMClk_x <= '0';
data_0 <= to_0_data & to_1_data & to_2_data;
ready_0 <= '0'; -- unused?
-----------------
-- State machines
-----------------
receiving : process(busdata_0, bussof_0, buseof_0, bus_src_rdy_0,
receive_state, received_counter)
begin
bus_dst_rdy_0 <= '1';
receive_state_next <= receive_state;
received_counter_next <= received_counter;
case receive_state is
when R_STATE_INIT =>
received_counter_next <= 0;
receive_state_next <= R_STATE_COUNT;
when R_STATE_COUNT =>
if bussof_0 = '1' then
received_counter_next <= received_counter + 1;
end if;
end case;
end process;
send_to_0 : process(start_to_0, send_to_0_state, s_0_counter, grant_0)
begin
src_rdy_0(0) <= '0';
to_0_data <= (others => '0');
sof_0(0) <= '0';
eof_0(0) <= '0';
req_0(0) <= '0';
send_to_0_state_next <= send_to_0_state;
s_0_counter_next <= s_0_counter;
case send_to_0_state is
when S_STATE_INIT =>
send_to_0_state_next <= S_STATE_WAIT;
s_0_counter_next <= 0;
when S_STATE_WAIT =>
if start_to_0 = '1' then
send_to_0_state_next <= S_STATE_LOCK;
end if;
when S_STATE_LOCK =>
req_0(0) <= '1';--req has to be high as long as we send packets.
if grant_0(0) = '0' then
send_to_0_state_next <= S_STATE_LOCK;
else
send_to_0_state_next <= S_STATE_SEND_FIRST;
end if;
when S_STATE_SEND_FIRST =>
src_rdy_0(0) <= '1';
sof_0(0) <= '1';
to_0_data <= (others => '1');
s_0_counter_next <= s_0_counter + 1;
send_to_0_state_next <= S_STATE_INTERM;
req_0(0) <= '1';
when S_STATE_INTERM =>
req_0(0) <= '1';
src_rdy_0(0) <= '1';
to_0_data <= (others => '0');
if s_0_counter = 15 then
s_0_counter_next <= 0;
send_to_0_state_next <= S_STATE_WAIT;
eof_0(0) <= '1';
else
s_0_counter_next <= s_0_counter + 1;
end if;
when others =>
send_to_0_state_next <= S_STATE_INIT;
end case;
end process;
send_to_1 : process(start_to_1, send_to_1_state, s_1_counter, grant_0)
begin
src_rdy_0(1) <= '0';
to_1_data <= (others => '0');
sof_0(1) <= '0';
eof_0(1) <= '0';
req_0(1) <= '0';
send_to_1_state_next <= send_to_1_state;
s_1_counter_next <= s_1_counter;
case send_to_1_state is
when S_STATE_INIT =>
send_to_1_state_next <= S_STATE_WAIT;
s_1_counter_next <= 0;
when S_STATE_WAIT =>
if start_to_1 = '1' then
send_to_1_state_next <= S_STATE_LOCK;
end if;
when S_STATE_LOCK =>
req_0(1) <= '1';
if grant_0(1) = '0' then
send_to_1_state_next <= S_STATE_LOCK;
else
send_to_1_state_next <= S_STATE_SEND_FIRST;
end if;
when S_STATE_SEND_FIRST =>
src_rdy_0(1) <= '1';
sof_0(1) <= '1';
to_1_data <= (others => '1');
s_1_counter_next <= s_1_counter + 1;
send_to_1_state_next <= S_STATE_INTERM;
req_0(1) <= '1';
when S_STATE_INTERM =>
req_0(1) <= '1';
src_rdy_0(1) <= '1';
to_1_data <= (others => '0');
if s_1_counter = 15 then
s_1_counter_next <= 0;
send_to_1_state_next <= S_STATE_WAIT;
eof_0(1) <= '1';
else
s_1_counter_next <= s_1_counter + 1;
end if;
when others =>
send_to_1_state_next <= S_STATE_INIT;
end case;
end process;
send_to_2 : process(start_to_2, send_to_2_state, s_2_counter, grant_0)
begin
src_rdy_0(2) <= '0';
to_2_data <= (others => '0');
sof_0(2) <= '0';
eof_0(2) <= '0';
req_0(2) <= '0';
send_to_2_state_next <= send_to_2_state;
s_2_counter_next <= s_2_counter;
case send_to_2_state is
when S_STATE_INIT =>
send_to_2_state_next <= S_STATE_WAIT;
s_2_counter_next <= 0;
when S_STATE_WAIT =>
if start_to_2 = '1' then
send_to_2_state_next <= S_STATE_LOCK;
end if;
when S_STATE_LOCK =>
req_0(2) <= '1';
if grant_0(2) = '0' then
send_to_2_state_next <= S_STATE_LOCK;
else
send_to_2_state_next <= S_STATE_SEND_FIRST;
end if;
when S_STATE_SEND_FIRST =>
src_rdy_0(2) <= '1';
sof_0(2) <= '1';
to_2_data <= (others => '1');
s_2_counter_next <= s_2_counter + 1;
send_to_2_state_next <= S_STATE_INTERM;
req_0(2) <= '1';
when S_STATE_INTERM =>
req_0(2) <= '1';
src_rdy_0(2) <= '1';
to_2_data <= (others => '0');
if s_2_counter = 15 then
s_2_counter_next <= 0;
send_to_2_state_next <= S_STATE_WAIT;
eof_0(2) <= '1';
else
s_2_counter_next <= s_2_counter + 1;
end if;
when others =>
send_to_2_state_next <= S_STATE_INIT;
end case;
end process;
-- memzing process
-- updates all the registers
proces_mem : process(clk, reset)
begin
if reset = '1' then
send_to_0_state <= S_STATE_INIT;
s_0_counter <= 0;
send_to_1_state <= S_STATE_INIT;
s_1_counter <= 0;
send_to_2_state <= S_STATE_INIT;
s_2_counter <= 0;
receive_state <= R_STATE_INIT;
received_counter <= 0;
elsif rising_edge(clk) then
send_to_0_state <= send_to_0_state_next;
s_0_counter <= s_0_counter_next;
send_to_1_state <= send_to_1_state_next;
s_1_counter <= s_1_counter_next;
send_to_2_state <= send_to_2_state_next;
s_2_counter <= s_2_counter_next;
receive_state <= receive_state_next;
received_counter <= received_counter_next;
end if;
end process;
-- OS synchronization state machine
-- this has to have this special format!
state_proc : process(clk, reset)
variable success : boolean;
variable done : boolean;
variable sw_command : std_logic_vector(0 to C_OSIF_DATA_WIDTH - 1);
begin
if reset = '1' then
reconos_reset_with_signature(o_osif, i_osif, X"ABCDEF01");
os_sync_state <= STATE_INIT;
start_to_0 <= '0';
start_to_1 <= '0';
start_to_2 <= '0';
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case os_sync_state is
when STATE_INIT =>
os_sync_state <= STATE_GET_COMMAND;
start_to_0 <= '0';
start_to_1 <= '0';
start_to_2 <= '0';
when STATE_SEND_ANSWER =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MBOX_HANDLE_HW_SW,
std_logic_vector(to_unsigned(received_counter,C_OSIF_DATA_WIDTH)));
if done then
os_sync_state <= STATE_GET_COMMAND;
end if;
when STATE_GET_COMMAND =>
reconos_mbox_get(done, success, o_osif, i_osif, C_MBOX_HANDLE_SW_HW, sw_command);
if done and success then
os_sync_state <= STATE_DECODE;
end if;
when STATE_DECODE =>
--default: command not known
os_sync_state <= STATE_GET_COMMAND;
-- element 0 indicates whether this thread should send to slot 0,
-- element 1 indicates whether this thread should send to slot 1,
-- element 6 indicates whether the receive counter from the bus interface
-- should be reported
if sw_command(6) = '1' then
os_sync_state <= STATE_SEND_ANSWER;
else
if sw_command(0) = '1' then
start_to_0 <= '1';
else
start_to_0 <= '0';
end if;
if sw_command(1) = '1' then
start_to_1 <= '1';
else
start_to_1 <= '0';
end if;
if sw_command(2) = '1' then
start_to_2 <= '1';
else
start_to_2 <= '0';
end if;
end if;
when others =>
os_sync_state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_b
--
-- Generated
-- by: wig
-- on: Tue Jun 27 05:23:07 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_MIXED ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-rtl-a.vhd,v 1.6 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: ent_b-rtl-a.vhd,v $
-- Revision 1.6 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_b
--
architecture rtl of ent_b is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_ba
-- No Generated Generics
-- Generated Generics for Entity ent_ba
-- End of Generated Generics for Entity ent_ba
-- No Generated Port
end component;
-- ---------
component ent_bb
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_ba
inst_ba: ent_ba
;
-- End of Generated Instance Port Map for inst_ba
-- Generated Instance Port Map for inst_bb
inst_bb: ent_bb
;
-- End of Generated Instance Port Map for inst_bb
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library verilog;
use verilog.vl_types.all;
entity LVDS_AD is
port(
rx_in : in vl_logic_vector(7 downto 0);
rx_inclock : in vl_logic;
rx_locked : out vl_logic;
rx_out : out vl_logic_vector(95 downto 0);
rx_outclock : out vl_logic
);
end LVDS_AD;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- used for address width calculation
use ieee.math_real.log2;
use ieee.math_real.ceil;
package aua_types is
constant ADDR_SIZE : natural := 16;
constant WORD_SIZE : natural := ADDR_SIZE;
subtype word_t is std_logic_vector(ADDR_SIZE-1 downto 0);
subtype pc_t is unsigned(ADDR_SIZE-1 downto 0);
subtype opcode_t is std_logic_vector(5 downto 0);
subtype reg_t is std_logic_vector(4 downto 0);
--
constant CLK_FREQ : natural := 70000000; -- main clock frequency
constant SRAM_RD_FREQ : natural := 50000000; -- ram clock when reading
constant SRAM_WR_FREQ : natural := 50000000; -- ram clock when writing
constant UART_RATE : natural := 115200; -- uart baud rate
constant RST_VECTOR : pc_t := x"8000";
constant RAM_ADDR_SIZE : natural := 14;
constant SC_SLAVE_CNT : natural := 4; -- count of simpcon slaves
constant SC_ADDR_SIZE : natural := ADDR_SIZE;
constant SC_DATA_SIZE : natural := 32;
constant SC_RDY_CNT_SIZE : natural := 2;
--
-- number of bits needed to address all slaves (2**SC_ADDR_BITS >= SLAVE_CNT)
constant SC_ADDR_BITS : integer := integer(ceil(log2(real(SC_SLAVE_CNT))));
--~ constant SC_ADDR_BITS : integer := integer(reqbits_for_choices(SC_SLAVE_CNT));
subtype sc_addr_t is std_logic_vector(SC_ADDR_SIZE-1 downto 0);
subtype sc_data_t is std_logic_vector(SC_DATA_SIZE-1 downto 0);
type sc_out_t is record
address : sc_addr_t;
wr_data : sc_data_t;
rd : std_logic;
wr : std_logic;
end record;
type sc_out_at is array (0 to SC_SLAVE_CNT-1) of sc_out_t;
subtype sc_rdy_cnt_t is unsigned(SC_RDY_CNT_SIZE-1 downto 0);
type sc_in_t is record
rd_data : sc_data_t;
rdy_cnt : sc_rdy_cnt_t;
end record;
type sc_in_at is array (0 to SC_SLAVE_CNT-1) of sc_in_t;
function max (L, R: real)
return real;
function bool2sl (arg : boolean)
return std_logic;
function sl2bool (arg : std_logic)
return boolean;
function reqbits_for_choices (choices : natural)
return positive;
function reqbitsZ_for_choices (choices : natural)
return natural;
end aua_types;
-- package body for aua on DE2
package body aua_types is
function max (L, R: real)
return real is begin
if L > R then
return L;
else
return R;
end if;
end function max;
function bool2sl (arg : boolean)
return std_logic is begin
if arg then
return '1';
else
return '0';
end if;
end function bool2sl;
function sl2bool (arg : std_logic)
return boolean is begin
if arg='1' then
return true;
else
return false;
end if;
end function sl2bool;
function reqbits_for_choices (choices : natural)
return positive is begin
if choices=1 then
return 1;
else
return positive(ceil(log2(real(choices))));
end if;
end function reqbits_for_choices;
function reqbitsZ_for_choices (choices : natural)
return natural is begin
return natural(ceil(log2(real(choices))));
end function reqbitsZ_for_choices;
end aua_types;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================================================================================================
-- Description: Implementation of a Non-Performing restoring divider with a configurable radix.
-- For detailed documentation see below.
--
-- Authors: Thomas B. Preusser
-- ============================================================================================================================================================
-- Copyright 2007-2014 Technische Universität Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library poc;
USE PoC.utils.ALL;
entity arith_div is
generic (
N : positive;-- := 32; -- Operand /Result Bit Widths
RAPOW : positive;-- := 1; -- Power of Radix used (2**RAPOW)
REGISTERED : boolean -- := false -- Output is registered
);
port (
-- Global Reset/Clock
clk : in std_logic;
rst : in std_logic;
-- Ready / Start
start : in std_logic;
rdy : out std_logic;
-- Arguments / Result (2's complement)
arg1, arg2 : in std_logic_vector(N-1 downto 0);
res : out std_logic_vector(N-1 downto 0)
);
end arith_div;
-------------------------------------------------------------------------------
-- Implementation of a Non-Performing Restoring Divider
--
-- Multi-Cycle division controlled by 'start' / 'rdy'. A new division can be
-- started, if 'rdy' = '1'. The result is available if 'rdy' is '1' again.
--
-- Note that the registered version is no slower than the unregistered one
-- as the conversion to a negative result is performed on-the-fly. It is,
-- however, somewhat more expensive as illustrated below.
--
-- Synthesis Costs of the differing feasible configurations:
--
-- Baseline values of Radix-2 unregistered configuration per 2009-12-08.
-- XST: Optimization Goal AREA
--
-- Radix 2 4 8
-- Registered
--
-- no 134 -2 -2 Flip Flops
-- 244 +95 +189 LUT4
--
-- yes +30 +26 +24 Flip Flops
-- +1 +97 +189 LUT4
--
--
-------------------------------------------------------------------------------
architecture div_npr of arith_div is
-- Constants
constant STEPS : positive := (N+RAPOW-1)/RAPOW; -- Number of Iteration Steps
-- State
signal Exec : std_logic; -- Operation is being executed
-- Argument/Result Registers
signal A : unsigned(N -1 downto 0); -- Dividend
signal B : unsigned(N+RAPOW*(STEPS-1)-1 downto 0); -- Divisor
signal S : std_logic; -- Quotient Sign
signal An : unsigned(N -1 downto 0); -- Next Residue Value
signal dn : unsigned(RAPOW-1 downto 0); -- Next Quotient Digit
-- Iteration Counter
signal Cnt : unsigned(1 to log2ceil(STEPS));
signal CntDD : unsigned(1 to log2ceil(STEPS)); -- Cnt - 1
signal CntEx0 : std_logic; -- Cnt = 0
begin -- div_npr
-- Registers
process(clk)
begin
if clk'event and clk = '1' then
-- Reset
if rst = '1' then
Exec <= '0';
-- Iteration Step
elsif Exec = '1' then
Cnt <= CntDD;
A <= An;
B <= (1 to RAPOW => '0') & B(B'LEFT downto RAPOW);
if CntEx0 = '1' then
Exec <= '0';
end if;
-- Operation Initialization
elsif start = '1' then
Exec <= '1';
if arg1(N-1) = '0' then
A <= unsigned(arg1);
else
A <= 0 - unsigned(arg1);
end if;
if arg2(N-1) = '0' then
B(B'LEFT downto (STEPS-1)*RAPOW) <= unsigned(arg2);
else
B(B'LEFT downto (STEPS-1)*RAPOW) <= 0 - unsigned(arg2);
end if;
B((STEPS-1)*RAPOW-1 downto 0) <= (others => '0');
S <= arg1(N-1) xor arg2(N-1);
Cnt <= to_unsigned(STEPS-1, log2ceil(STEPS));
end if;
end if;
end process;
rdy <= not Exec;
-- Counter Logic
CntDD <= Cnt - 1;
CntEx0 <= not Cnt(Cnt'LEFT) and CntDD(CntDD'LEFT);
-- Subtractor
blkSub: block
subtype tData is unsigned(N-1 downto 0);
subtype tDatx is unsigned(N downto 0);
type tDataArr is array (natural range<>) of tData;
type tDatxArr is array (natural range<>) of tDatx;
signal rng : std_logic_vector(RAPOW-1 downto 0); -- B beyond Range
signal di : tDatxArr(RAPOW-1 downto 0);
signal Ai : tDataArr(RAPOW downto 0);
begin
-- Calculate Ranges
rng(0) <= '1' when B(B'LEFT downto N) /= (B'LEFT downto N => '0') else '0';
lr: for i in 1 to RAPOW-1 generate
rng(i) <= rng(i-1) or B(N-i);
end generate lr;
-- Speculative Subtractions
Ai(RAPOW) <= A;
ls: for i in RAPOW-1 downto 0 generate
ieq0: if i = 0 generate
di(i) <= ('0' & Ai(i+1)) - ('0' & B(N-1 downto 0));
end generate ieq0;
ine0: if i /= 0 generate
di(i) <= ('0' & Ai(i+1)) - ('0' & B(N-i-1 downto 0) & (1 to i => '0'));
end generate ine0;
dn(i) <= not(rng(i) or di(i)(N));
Ai(i) <= di(i)(N-1 downto 0) when dn(i) = '1' else Ai(i+1);
end generate ls;
An <= Ai(0);
end block blkSub;
-- Quotient Composition
gNRG: if not REGISTERED generate
blkOut: block
signal Q : unsigned(N-1 downto 0); -- Quotient
begin
process(clk)
begin
if clk'event and clk = '1' then
if Exec = '1' then
Q <= Q(N-RAPOW-1 downto 0) & (dn xor (1 to RAPOW => S));
end if;
end if;
end process;
res <= std_logic_vector(Q + ("0" & S));
end block blkOut;
end generate gNRG;
gREG: if REGISTERED generate
blkOut: block
signal Q : unsigned(N -1 downto 0); -- Quotient
signal Qm1 : unsigned(N-RAPOW-1 downto 0); -- Quotient - 1
signal dnx : unsigned( RAPOW downto 0); -- (not dn) + 1
begin
dnx <= ('0' & not dn) + 1;
process(clk)
begin
if clk'event and clk = '1' then
if Exec = '1' then
if S = '0' then
Q <= Q(N-RAPOW-1 downto 0) & dn;
else
if dnx(RAPOW) = '1' then
Q(N-1 downto RAPOW) <= Q (N-RAPOW-1 downto 0);
else
Q(N-1 downto RAPOW) <= Qm1(N-RAPOW-1 downto 0);
end if;
Q(RAPOW-1 downto 0) <= dnx(RAPOW-1 downto 0);
Qm1 <= Qm1(N-2*RAPOW-1 downto 0) & not dn;
end if;
end if;
end if;
end process;
res <= std_logic_vector(Q);
end block blkOut;
end generate gREG;
end div_npr;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================================================================================================
-- Description: Implementation of a Non-Performing restoring divider with a configurable radix.
-- For detailed documentation see below.
--
-- Authors: Thomas B. Preusser
-- ============================================================================================================================================================
-- Copyright 2007-2014 Technische Universität Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library poc;
USE PoC.utils.ALL;
entity arith_div is
generic (
N : positive;-- := 32; -- Operand /Result Bit Widths
RAPOW : positive;-- := 1; -- Power of Radix used (2**RAPOW)
REGISTERED : boolean -- := false -- Output is registered
);
port (
-- Global Reset/Clock
clk : in std_logic;
rst : in std_logic;
-- Ready / Start
start : in std_logic;
rdy : out std_logic;
-- Arguments / Result (2's complement)
arg1, arg2 : in std_logic_vector(N-1 downto 0);
res : out std_logic_vector(N-1 downto 0)
);
end arith_div;
-------------------------------------------------------------------------------
-- Implementation of a Non-Performing Restoring Divider
--
-- Multi-Cycle division controlled by 'start' / 'rdy'. A new division can be
-- started, if 'rdy' = '1'. The result is available if 'rdy' is '1' again.
--
-- Note that the registered version is no slower than the unregistered one
-- as the conversion to a negative result is performed on-the-fly. It is,
-- however, somewhat more expensive as illustrated below.
--
-- Synthesis Costs of the differing feasible configurations:
--
-- Baseline values of Radix-2 unregistered configuration per 2009-12-08.
-- XST: Optimization Goal AREA
--
-- Radix 2 4 8
-- Registered
--
-- no 134 -2 -2 Flip Flops
-- 244 +95 +189 LUT4
--
-- yes +30 +26 +24 Flip Flops
-- +1 +97 +189 LUT4
--
--
-------------------------------------------------------------------------------
architecture div_npr of arith_div is
-- Constants
constant STEPS : positive := (N+RAPOW-1)/RAPOW; -- Number of Iteration Steps
-- State
signal Exec : std_logic; -- Operation is being executed
-- Argument/Result Registers
signal A : unsigned(N -1 downto 0); -- Dividend
signal B : unsigned(N+RAPOW*(STEPS-1)-1 downto 0); -- Divisor
signal S : std_logic; -- Quotient Sign
signal An : unsigned(N -1 downto 0); -- Next Residue Value
signal dn : unsigned(RAPOW-1 downto 0); -- Next Quotient Digit
-- Iteration Counter
signal Cnt : unsigned(1 to log2ceil(STEPS));
signal CntDD : unsigned(1 to log2ceil(STEPS)); -- Cnt - 1
signal CntEx0 : std_logic; -- Cnt = 0
begin -- div_npr
-- Registers
process(clk)
begin
if clk'event and clk = '1' then
-- Reset
if rst = '1' then
Exec <= '0';
-- Iteration Step
elsif Exec = '1' then
Cnt <= CntDD;
A <= An;
B <= (1 to RAPOW => '0') & B(B'LEFT downto RAPOW);
if CntEx0 = '1' then
Exec <= '0';
end if;
-- Operation Initialization
elsif start = '1' then
Exec <= '1';
if arg1(N-1) = '0' then
A <= unsigned(arg1);
else
A <= 0 - unsigned(arg1);
end if;
if arg2(N-1) = '0' then
B(B'LEFT downto (STEPS-1)*RAPOW) <= unsigned(arg2);
else
B(B'LEFT downto (STEPS-1)*RAPOW) <= 0 - unsigned(arg2);
end if;
B((STEPS-1)*RAPOW-1 downto 0) <= (others => '0');
S <= arg1(N-1) xor arg2(N-1);
Cnt <= to_unsigned(STEPS-1, log2ceil(STEPS));
end if;
end if;
end process;
rdy <= not Exec;
-- Counter Logic
CntDD <= Cnt - 1;
CntEx0 <= not Cnt(Cnt'LEFT) and CntDD(CntDD'LEFT);
-- Subtractor
blkSub: block
subtype tData is unsigned(N-1 downto 0);
subtype tDatx is unsigned(N downto 0);
type tDataArr is array (natural range<>) of tData;
type tDatxArr is array (natural range<>) of tDatx;
signal rng : std_logic_vector(RAPOW-1 downto 0); -- B beyond Range
signal di : tDatxArr(RAPOW-1 downto 0);
signal Ai : tDataArr(RAPOW downto 0);
begin
-- Calculate Ranges
rng(0) <= '1' when B(B'LEFT downto N) /= (B'LEFT downto N => '0') else '0';
lr: for i in 1 to RAPOW-1 generate
rng(i) <= rng(i-1) or B(N-i);
end generate lr;
-- Speculative Subtractions
Ai(RAPOW) <= A;
ls: for i in RAPOW-1 downto 0 generate
ieq0: if i = 0 generate
di(i) <= ('0' & Ai(i+1)) - ('0' & B(N-1 downto 0));
end generate ieq0;
ine0: if i /= 0 generate
di(i) <= ('0' & Ai(i+1)) - ('0' & B(N-i-1 downto 0) & (1 to i => '0'));
end generate ine0;
dn(i) <= not(rng(i) or di(i)(N));
Ai(i) <= di(i)(N-1 downto 0) when dn(i) = '1' else Ai(i+1);
end generate ls;
An <= Ai(0);
end block blkSub;
-- Quotient Composition
gNRG: if not REGISTERED generate
blkOut: block
signal Q : unsigned(N-1 downto 0); -- Quotient
begin
process(clk)
begin
if clk'event and clk = '1' then
if Exec = '1' then
Q <= Q(N-RAPOW-1 downto 0) & (dn xor (1 to RAPOW => S));
end if;
end if;
end process;
res <= std_logic_vector(Q + ("0" & S));
end block blkOut;
end generate gNRG;
gREG: if REGISTERED generate
blkOut: block
signal Q : unsigned(N -1 downto 0); -- Quotient
signal Qm1 : unsigned(N-RAPOW-1 downto 0); -- Quotient - 1
signal dnx : unsigned( RAPOW downto 0); -- (not dn) + 1
begin
dnx <= ('0' & not dn) + 1;
process(clk)
begin
if clk'event and clk = '1' then
if Exec = '1' then
if S = '0' then
Q <= Q(N-RAPOW-1 downto 0) & dn;
else
if dnx(RAPOW) = '1' then
Q(N-1 downto RAPOW) <= Q (N-RAPOW-1 downto 0);
else
Q(N-1 downto RAPOW) <= Qm1(N-RAPOW-1 downto 0);
end if;
Q(RAPOW-1 downto 0) <= dnx(RAPOW-1 downto 0);
Qm1 <= Qm1(N-2*RAPOW-1 downto 0) & not dn;
end if;
end if;
end if;
end process;
res <= std_logic_vector(Q);
end block blkOut;
end generate gREG;
end div_npr;
|
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