content stringlengths 1 1.04M ⌀ |
|---|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- FRECUENCIMETRO
-- Librerias necesarias
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
-- Definimos la entidad
ENTITY Frecuencimetro IS
PORT(
reloj : IN STD_LOGIC; -- Reloj interno de la placa
senialGenerador : IN STD_LOGIC; -- Senial introducida por el generador
... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity led_timer is
generic
(
on_time_exp : positive := 10
);
port
(
clk : in std_logic;
rst : in std_logic;
input : in std_logic;
led : out std_logic
);
end entity;
architecture rtl of led_timer is
signal cnt : std_logic_vector... |
-- +UEFSHDR----------------------------------------------------------------------
-- 2014 UEFS Universidade Estadual de Feira de Santana
-- TEC499-Sistemas Digitais
-- ------------------------------------------------------------------------------
-- TEAM: 01
-- ----------------------------------------------------------... |
-- $Id: tst_serlooplib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: tst_serlooplib
-- Description: Definitions ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY halfAdder IS
PORT (
in1 : IN std_logic;
in2 : IN std_logic;
res : OUT std_logic;
carry : OUT std_logic
);
END halfAdder;
ARCHITECTURE behavior OF halfAdder IS
BEGIN
res <= in1 XOR in2;
carry <= in1 AND in2;
END behavior;
|
------------------------------------------------------------------------------
-- Create/rivision Date: 7/13/2008, 7/15/2009, 6/28/2010
-- Design Name: Instruction Cache Emulator Unit
-- Module Name: inst_cache
-- Authors: Rahul P. Tekawade, Gandhi Puvvada
-- File: inst_cache_r2.vhd
-------------------... |
----------------------------------------------------------------------------------------------------
-- demuxer
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
----------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_lib.all;
entity timer is
port (
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
output : out std_logic_vector(26 downto 0)
);
end timer;
architecture arch of timer is
component pulser is
generic(
delay:inte... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- NEED RESULT: ARCH00009.P1_1: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.P1_2: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.P1_3: Resume after time on timeout clause expired passed
-- NEED RESULT: ARCH00009.P1_4: Resume after time on timeout clause ... |
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.iface.all;
use work.amba.all;
use work.mdctrom256.all;
package mdctlib is
constant TRIGBITS: integer := 14;
--constant rom_lenght: integer:=14;
constant cPI3_8 :std_logic_vector (31 downto 0) := "00000000000000000001100001111110";
constant cPI2_8 :std_logic_vector (... |
----------------------------------------------------------------------------------
-- Company: Laboratoire Leprince-Ringuet
-- Engineer:
--
-- Create Date: 12:09:35 10/14/2011
-- Design Name:
-- Module Name: crc32_8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Descriptio... |
-------------------------------------------------------------------------------
-- flash_2mx16_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_mch_emc_v3_01_a;
use xps_mch_emc... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "capture_ctrl" and "storage"
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : capture_ctrl+storage_tb.vhd
-- Created ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--!
--! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dac_serial is
port(
SPI_SCK: out std_logic; -- spi clock
DAC_CS: out std_logic; -- chip select
SPI_MOSI_1: out std_logic; -- Master output, slave (DAC) input
SPI_MOSI_2: out std_logic; -- Master output, slave (DAC) input
--SPI_M... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fir_types.all;
use work.fir_coeff_lib.all;
use std.textio.all;
entity fir_matlab is
end entity fir_matlab;
architecture sim of fir_matlab is
signal clk : std_logic := '0';
signal stb : std_logic := '0';
signal d : signed(26 downto 0);
s... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fir_types.all;
use work.fir_coeff_lib.all;
use std.textio.all;
entity fir_matlab is
end entity fir_matlab;
architecture sim of fir_matlab is
signal clk : std_logic := '0';
signal stb : std_logic := '0';
signal d : signed(26 downto 0);
s... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;
ENTITY windManager_tb IS
END windManager_tb;
ARCHITECTURE behavior OF windManager_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT windowsManager
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- This code is used to configure the Marvell 88e1111 and handle the MDIO pins (PHY_RESET, PHY_MDC and PHY_MDIO).
-- It can write and read the internals registers of the marvell.
-- Right now, the configuration used is the configuration by default and this entity only outputs an hardware reset when power up.
-- You ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2 is
e... |
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2 is
e... |
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2 is
e... |
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2 is
e... |
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2 is
e... |
-------------------------------------------------------------------------------
--! @file dpRamSplx-e.vhd
--
--! @brief Simplex Dual Port Ram Entity
--
--! @details This is the Simplex DPRAM entity.
--! The DPRAM has one write and one read port only.
--
---------------------------------------------------------... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fetch_mem is
port(
clk, rst : in std_logic;
read_addr : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(15 downto 0));
end fetch_mem;
architecture mixed of fetch_mem is
type mem_ty... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
package component_pack is
-- constant definitions
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100"... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
package component_pack is
-- constant definitions
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100"... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
package component_pack is
-- constant definitions
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100"... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/01/2014 10:27:20 AM
-- Design Name:
-- Module Name: mmc_crc7 - rtl
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Rev... |
-------------------------------------------------------------------------------
-- OpenMAC DMA FIFO
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributi... |
-------------------------------------------------------------------------------
-- OpenMAC DMA FIFO
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributi... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
entity interrupt_handler is
port (
data_in1, data_in2 : in std_logic_vector(7 downto 0);
raddr1, raddr2 : inout std_logic_vector(3 downto 0);
raddr_write : out std_logic_vector(3 downto 0);
reg_re, reg_w... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
entity dpram_sc is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first_a : boolean := false... |
LIBRARY IEEE;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
USE ieee.math_real.all;
--alu_ops_map = {
-- "+": "000",
-- "-": "001",
-- "*": "010",
-- "/": "011",
-- "!": "100",
-- "&": "101",
-- "^": "110",
-- "|": "111"
-- }
ENTITY ALU IS
GENERIC(
data_width... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:20:08 07/12/05
-- Design Name:
-- Module Name: combine_g_bar - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:41:32 02/12/2014
-- Design Name:
-- Module Name: full_adder_1_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:41:32 02/12/2014
-- Design Name:
-- Module Name: full_adder_1_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:22:12 02/06/2015
-- Design Name:
-- Module Name: addN - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:22:12 02/06/2015
-- Design Name:
-- Module Name: addN - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
-------------------------------------------------------------------------------
--
-- SNESpad controller core
--
-- $Id: snespad.vhd,v 1.2 2004/10/05 18:22:40 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised form... |
Library Ieee;
Use Ieee.Std_Logic_1164.all;
Entity Mips8B_DataPath is
Generic( N: Natural := 8;
RF_SIZE: Natural := 8;
SH_SIZE: Natural := 3;
RF_ADDR_SIZE: Natural := 3);
Port(clock: in Std_Logic;
-- Controle dos Registradores do Shift... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
-- test2 - clock divider controlled by quadrature decoder
-- Written in 2016 by <Ahmet Inan> <xdsopl@googlemail.com>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without an... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
entity Task2_ent_tb2 is
end entity Task2_ent_tb2;
architecture Task2_arch_tb2 of Task2_ent_tb2 is
constant delay_wr_in : Time := 5 ns;
const... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Copyright Institut Pascal Equipe Dream (19-10-2016)
-- Francois Berry, El Mehdi Abdali, Maxime Pelcat
-- This software is a computer program whose purpose is to manage dynamic
-- partial reconfiguration.
-- This software is governed b... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port (
MOSI_ext : out std_logic;
CSB_ext : out std_logic
);
end top;
architecture Behavioral of top is
signal CAPTURE: std_logic;
signal UPDATE:... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port (
MOSI_ext : out std_logic;
CSB_ext : out std_logic
);
end top;
architecture Behavioral of top is
signal CAPTURE: std_logic;
signal UPDATE:... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port (
MOSI_ext : out std_logic;
CSB_ext : out std_logic
);
end top;
architecture Behavioral of top is
signal CAPTURE: std_logic;
signal UPDATE:... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port (
MOSI_ext : out std_logic;
CSB_ext : out std_logic
);
end top;
architecture Behavioral of top is
signal CAPTURE: std_logic;
signal UPDATE:... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_b_e
--
-- Generated
-- by: wig
-- on: Wed Apr 5 12:50:28 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id:... |
ENTITY repro1_ent IS
port( S : inout string := "abcdef");
END repro1_ent;
ARCHITECTURE repro1_arch OF repro1_ent IS
constant C : string := "abcdef";
BEGIN
assert S = C;
END repro1_arch;
|
ENTITY repro1_ent IS
port( S : inout string := "abcdef");
END repro1_ent;
ARCHITECTURE repro1_arch OF repro1_ent IS
constant C : string := "abcdef";
BEGIN
assert S = C;
END repro1_arch;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- T... |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate FOR_LABEL;
IF_LABEL : if a = '1' generate
end generate IF_LABEL;
CASE_LABEL : case data generate
end generate CASE_LABEL;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate end generate FOR_LABEL;
IF_L... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.03.2014 15:08:57
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revi... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:39:03 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../io.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig ... |
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
lib... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY add_1bit_add_1bit_sch_tb IS
END add_1bit_add_1bit_sch_tb;
ARCHITECTURE behavioral OF add_1bit_add_1bit_sch_tb IS
COMPONENT add_1bit
PORT( Ak : IN STD_LOGIC;
Bk : IN STD_L... |
-------------------------------------------------------------------
-- System Generator version 11.1.00 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., an... |
-------------------------------------------------------------------
-- System Generator version 11.1.00 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., an... |
-------------------------------------------------------------------
-- System Generator version 11.1.00 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., an... |
entity issue110 is
end entity;
use std.textio.all;
architecture test of issue110 is
impure function write_func(x : integer) return integer is
variable l : line;
begin
write(l, x);
writeline(output, l);
return x;
end function;
procedure write_proc(x : integer) is
... |
entity issue110 is
end entity;
use std.textio.all;
architecture test of issue110 is
impure function write_func(x : integer) return integer is
variable l : line;
begin
write(l, x);
writeline(output, l);
return x;
end function;
procedure write_proc(x : integer) is
... |
entity issue110 is
end entity;
use std.textio.all;
architecture test of issue110 is
impure function write_func(x : integer) return integer is
variable l : line;
begin
write(l, x);
writeline(output, l);
return x;
end function;
procedure write_proc(x : integer) is
... |
entity issue110 is
end entity;
use std.textio.all;
architecture test of issue110 is
impure function write_func(x : integer) return integer is
variable l : line;
begin
write(l, x);
writeline(output, l);
return x;
end function;
procedure write_proc(x : integer) is
... |
entity issue110 is
end entity;
use std.textio.all;
architecture test of issue110 is
impure function write_func(x : integer) return integer is
variable l : line;
begin
write(l, x);
writeline(output, l);
return x;
end function;
procedure write_proc(x : integer) is
... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "reg_file_bram_double_buffered"
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "reg_file_bram_double_buffered"
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------... |
CONFIGURATION memory_stage_struct_config OF memory_stage IS
FOR struct
END FOR;
END memory_stage_struct_config; |
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