content stringlengths 1 1.04M ⌀ |
|---|
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY light IS
PORT ( x1, x2 : IN STD_LOGIC ;
f: OUT STD_LOGIC ) ;
END light ;
ARCHITECTURE LogicFunction OF light IS
signal tmp:std_logic :='0';
BEGIN
f <= (x1 AND NOT x2) OR (NOT x1 AND x2);
--process(x1)
--begin
--g<=x1;
--tmp<= x1 or x2;
--h<=tmp;
--end process;
... |
---------------------------------------------------------------
-- Title : Wishbone RAM for simulation
-- Project : -
---------------------------------------------------------------
-- File : iram32_sim.vhd
-- Author : michael.miehling@men.de
-- Organization : MEN Mikro Elektronik GmbH
--... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
----------------------------------------------------------------------------------
-- Company: WUT
-- Engineer: abyszuk
--
-- Create Date: 12:29:46 04/15/2008
-- Design Name:
-- Module Name: DDRs_Control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies: DDR c... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in s... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in s... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in s... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--
-- Authors: Francisco Paiva Knebel
-- Gabriel Alexandre Zillmer
--
-- Universidade Federal do Rio Grande do Sul
-- Instituto de Informática
-- Sistemas Digitais
-- Prof. Fernanda Lima Kastensmidt
--
-- Create Date: 17:04:14 05/14/2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 09/14/2014
--! Module Name: EPATH_FIFO_WRAP
--! Project Name: FELIX
----------------------------------------------------------------------------------
--... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 09/14/2014
--! Module Name: EPATH_FIFO_WRAP
--! Project Name: FELIX
----------------------------------------------------------------------------------
--... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 09/14/2014
--! Module Name: EPATH_FIFO_WRAP
--! Project Name: FELIX
----------------------------------------------------------------------------------
--... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company: NTU ATHENS - BNL
-- Engineer: Paris Moschovakos
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Paris Moschovakos
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free so... |
entity buf is
port ( a : in bit; y : out bit );
end entity;
architecture test of buf is
begin
y <= a after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity fanout_tree is
generic ( h : natural; d : positive );
port ( input : in bit; out... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00312
--
-- AUTHOR:
--
-- A. Wilm... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:30:59)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_nsga2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 30);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 31));... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 12:32:27 2017
-- Host : vldmr-PC running 64-bit Service ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 12:32:27 2017
-- Host : vldmr-PC running 64-bit Service ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity slot_timing is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
PHI2 : in std_logic;
BA : in std_logic;
serve_vic : in std_lo... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity slot_timing is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
PHI2 : in std_logic;
BA : in std_logic;
serve_vic : in std_lo... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity slot_timing is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
PHI2 : in std_logic;
BA : in std_logic;
serve_vic : in std_lo... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity slot_timing is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
PHI2 : in std_logic;
BA : in std_logic;
serve_vic : in std_lo... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:14:32 10/04/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/procesadordefinitivo/TBMUX32.vhd
-- Project Name: procesadordefinitivo
-- Target Device:
-- Tool ve... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:14:32 10/04/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/procesadordefinitivo/TBMUX32.vhd
-- Project Name: procesadordefinitivo
-- Target Device:
-- Tool ve... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:14:32 10/04/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/procesadordefinitivo/TBMUX32.vhd
-- Project Name: procesadordefinitivo
-- Target Device:
-- Tool ve... |
-- $Id: sys_tst_rlink_n3.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
library verilog;
use verilog.vl_types.all;
entity View_input_vlg_sample_tst is
port(
clk : in vl_logic;
reset : in vl_logic;
w : in vl_logic;
sampler_tx : out vl_logic
);
end View_input_vlg_sample_tst;
|
package pkg is
type nat_rec is record
a, b : natural;
end record;
type nat_arr is array (natural range <>) of natural;
end pkg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity tb_case02 is
end tb_case02;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_case02 is
signal s : std_logic_vector (4 downto 0);
signal o : std_logic;
begin
dut: entity work.case02
port map (s, o);
process
constant ov : std_logic_vector (0 to 31) :=... |
-------------------------------------------------------------------------------
--
-- File: CRC16_behavioral.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI CSI-2 Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c... |
entity fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic := '0'; -- Comment
sig2 : std_logic := '1'; -- Comment
sig3 : std_logic := 'Z' -- Comment
);
end entity fifo;
-- Failur... |
-------------------------------------------------------------------------------
-- baudrate - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xili... |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
--Date : Mon Mar 27 01:47:30 2017
--Host : andrewandrepowell2-desktop running 64-bit... |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Fri Sep 22 22:04:21 2017
-- Host : DarkCube running 64-bit major releas... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Technology specific dual-port RAM.
----------------------------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.14:52:11)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir2_spea2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13,... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
package pkg is
type protected_t is protected
end protected protected_t;
procedure proc(variable prot : inout protected_t; variable result : out boolean);
end package;
package body pkg is
type protected_t is protected body
end protected body protected_t;
procedure proc(variable prot : inout protected_t; v... |
package pkg is
type protected_t is protected
end protected protected_t;
procedure proc(variable prot : inout protected_t; variable result : out boolean);
end package;
package body pkg is
type protected_t is protected body
end protected body protected_t;
procedure proc(variable prot : inout protected_t; v... |
package pkg is
type protected_t is protected
end protected protected_t;
procedure proc(variable prot : inout protected_t; variable result : out boolean);
end package;
package body pkg is
type protected_t is protected body
end protected body protected_t;
procedure proc(variable prot : inout protected_t; v... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNPJ4Y7BVC is
generic ( ClockPhase : string := "1";
delay : positive := 1;
us... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNPJ4Y7BVC is
generic ( ClockPhase : string := "1";
delay : positive := 1;
us... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNPJ4Y7BVC is
generic ( ClockPhase : string := "1";
delay : positive := 1;
us... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNPJ4Y7BVC is
generic ( ClockPhase : string := "1";
delay : positive := 1;
us... |
-- This unit will simulate a DSP
-- It will read form a file
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use std.textio.all;
library simio;
use simio.SIMIO_PACKAGE.all;
entity dspemulator is
generic ( DSP_INC_FILE : string := "UNUSED" ;
ABUS_WIDTH : integer := 16;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.math_real.all;
library work;
use work.bus_pkg.all;
package depp_pkg is
subtype depp_address_type is std_logic_vector(7 downto 0);
subtype depp_data_type is std_logic_vector(7 downto 0);
constant depp2bus_write_mask_length_ceil... |
-------------------------------------------------------------------------------
-- axi_vdma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights... |
-------------------------------------------------------------------------------
-- axi_vdma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights... |
-------------------------------------------------------------------------------
-- axi_vdma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights... |
-------------------------------------------------------------------------------
-- axi_vdma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights... |
------------
-- pcore top level wrapper
-- generated at 2008-02-11 14:35:32.679588 by 'mkhwtask.py hwt_semaphore_wait 2 ../src/hwt_semaphore_wait.vhd'
------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.r... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_op is
generic (
NBITS_IN : natural := 1;
NBR_OF_CHROMA_IN : natural := 1;
NBR_OF_ROW_IN : natural := 1;
NBR_OF_COL_IN : natural := 1... |
--------------------------------------------------------------------------------
--
-- Title : ctrl_comp_pkg.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Up down counter
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_std.all;
entity Counter is
port (Clock, Reset, Enable, Load, UpDn: in Std_logic;
Data: in Std_logic_vector(7 downto 0);
Q: out Std_logic_vector(7 downto 0));
end;
architecture RTL of Counter is
signal C... |
-- Up down counter
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_std.all;
entity Counter is
port (Clock, Reset, Enable, Load, UpDn: in Std_logic;
Data: in Std_logic_vector(7 downto 0);
Q: out Std_logic_vector(7 downto 0));
end;
architecture RTL of Counter is
signal C... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity top is
Port (
sys_clk : in std_logic;
Led: out st... |
-- file: clk_32to25_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is... |
-- file: clk_32to25_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is... |
-- file: clk_32to25_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is... |
-- file: clk_32to25_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is... |
-- file: clk_32to25_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is... |
-- file: clk_32to25_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is... |
-- file: clk_32to25_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is... |
-- file: clk_32to25_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is... |
-- file: clk_32to25_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is... |
-- file: clk_32to25_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is... |
-- file: clk_32to25_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is... |
-- file: clk_32to25_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is... |
-- file: clk_32to25_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
entity foo is end;
architecture bar of foo is
type BIT is ('0', '1');
procedure prok is begin
case 0 is
-- expression
when 1 => null;
when not 3 => null;
-- discrete range
when 0 to 4 => wait;
when bit => wait;
-- element name
when asdf => null;
-- others
when others => null;
end ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
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