content stringlengths 1 1.04M ⌀ |
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-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:27 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
ARCHITECTURE rtl OF subunit0 IS
BEGIN
a_ready <= b_ready;
b_data <= a_data;
b_last <= a_last;
b_strb <= a_strb;
b_valid <= a_valid;
END ARCHITECTURE rtl; |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
entity real1 is
end entity;
architecture test of real1 is
begin
process is
variable r : real;
begin
assert r = real'left;
r := 1.0;
r := r + 1.4;
assert r > 2.0;
assert r < 3.0;
assert r >= real'low;
assert r <= real'high;
assert r /= 5.0... |
entity real1 is
end entity;
architecture test of real1 is
begin
process is
variable r : real;
begin
assert r = real'left;
r := 1.0;
r := r + 1.4;
assert r > 2.0;
assert r < 3.0;
assert r >= real'low;
assert r <= real'high;
assert r /= 5.0... |
entity real1 is
end entity;
architecture test of real1 is
begin
process is
variable r : real;
begin
assert r = real'left;
r := 1.0;
r := r + 1.4;
assert r > 2.0;
assert r < 3.0;
assert r >= real'low;
assert r <= real'high;
assert r /= 5.0... |
library ieee;
use ieee.std_logic_1164.all;
entity fluxo_de_dados_transmissao is
port(dado_serial : in std_logic;
enable_transmissao : in std_logic;
TD : out std_logic);
end fluxo_de_dados_transmissao;
architecture fluxo_de_dados_transmissao_Arch of fluxo_de_dados_transmissao is
begin
process (d... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:43:12 12/18/2013
-- Design Name:
-- Module Name: /home/nakayama/Desktop/583final/BO_Tests/Raster_Test.vhd
-- Project Name: BO_Tests
-- Target Device:
-- Tool versions:
-- Descript... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bug is
port(index : in integer range 0 to 1);
end bug;
architecture behav of bug is
type foobar is record
foo : std_logic;
bar : std_logic_vector(1 downto 0);
end record;
-- Changing the order works:
--ty... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity keyb_nov is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(1 downto 0)
);
end keyb_nov;
architecture behaviour of keyb_nov is
constant st0: std_logic_vector(4 downto 0) := "... |
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provid... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity adqsout is
port(
clk : in std_logic; -- clk90
dqs : in std_logic;
dqs_oe : in std_logic;
dqs_oct : in std_logic... |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity adqsout is
port(
clk : in std_logic; -- clk90
dqs : in std_logic;
dqs_oe : in std_logic;
dqs_oct : in std_logic... |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity adqsout is
port(
clk : in std_logic; -- clk90
dqs : in std_logic;
dqs_oe : in std_logic;
dqs_oct : in std_logic... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:22:35 11/21/2016
-- Design Name:
-- Module Name: PC_Adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 18:34:35 2017
-- Host : GILAMONSTER running 64-bit major rel... |
entity bitvec is
end entity;
architecture test of bitvec is
function get_bitvec(x, y : integer) return bit_vector is
variable r : bit_vector(x to y) := "00";
begin
return r;
end function;
begin
process is
variable b : bit_vector(3 downto 0);
variable n : integer;
... |
entity bitvec is
end entity;
architecture test of bitvec is
function get_bitvec(x, y : integer) return bit_vector is
variable r : bit_vector(x to y) := "00";
begin
return r;
end function;
begin
process is
variable b : bit_vector(3 downto 0);
variable n : integer;
... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
-------------------------------------------------------------------------------
-- axi_dma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserv... |
-------------------------------------------------------------------------------
-- axi_dma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserv... |
-------------------------------------------------------------------------------
-- axi_dma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserv... |
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Wishbone DMA Streaming Interface
---------------------------------------------------------------------------------------
-- File : xdma_interface_registers_pkg.vhd
-- Author ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your opti... |
--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your opti... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library machxo2;
use machxo2.components.all;
entity FiRoE is
generic (
IMP : string := "HDL",
TOGGLE : boolean := true
);
port (
FiRo_o : out std_logic;
Run_i : in std_logic
);
end entity FiRoE;
architecture ... |
library ieee;
use ieee.std_logic_1164.all;
entity stb_gen is
generic (
period_g : in positive);
port (
rst_i : in std_ulogic := '0';
clk_i : in std_ulogic;
sync_rst_i : in std_ulogic := '0';
stb_i : in std_ulogic := '1';
stb_o : out std_ulogic);
end;
architecture rtl of stb_gen is
signal stb : std_ulo... |
package body my_pkg is
procedure some_proc (
a : integer;
b : integer
) is
constant some_const : integer_vector :=
some_proc(
arg1, arg2, arg3, arg4,
arg5, arg6, arg7
) ;
variable a, b, c, d, e, f, g : integer;
constant some_const : integer_vector :=
... |
-- modified 2006-05-13 (Line 404)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_async_almost_full is
generic(
DEPTH : natural;
AWIDTH : natural;
DWIDTH : natural;
RAM_TYPE : string -- "BLOCK_RAM" or "DIS_RAM"
);
port(
reset : in std_logic;
... |
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and b... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:47 2017
-- Host : KLight-PC running 64-bit major relea... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RS232 is
Port ( clk : in STD_LOGIC;
-- Trasmisor --
Entrada_8bits : in STD_LOGIC_VECTOR (7 downto 0);
Activador_Envio_Mensaje : in STD_LOGIC;
Salida_1bit : out STD_LOGIC := '1';
-- Receptor --
Entrada_1bit : i... |
entity tb_subprg02 is
end tb_subprg02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_subprg02 is
signal a, na : std_logic_vector (3 downto 0);
signal n : natural range 0 to 1;
signal clk : std_logic;
begin
dut: entity work.subprg02
port map (a, n, clk, na);
process
procedure p... |
entity choice1 is
end entity;
architecture test of choice1 is
signal s : integer;
begin
p1: process is
variable x : integer;
begin
case s is
when 1 | 2 =>
x := 3;
when 3 | 4 | 5 =>
x := 4;
when integer'low to 0 =>
... |
-------------------------------------------------------------------------------
-- Bitmap VGA display with 640x480 pixel resolution
-------------------------------------------------------------------------------
-- V 1.1.2 (2015/11/29)
-- Bertrand Le Gal (bertrand.legal@enseirb-matmeca.fr)
-- Some little modification... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2011-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-----... |
-- ctl_bypass.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---
-- Shift register delay. It is usually used to delay
-- control signals when processing data path in
-- ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:47:07 10/06/2010
-- Design Name:
-- Module Name: RefreshDisplay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:47:07 10/06/2010
-- Design Name:
-- Module Name: RefreshDisplay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:47:07 10/06/2010
-- Design Name:
-- Module Name: RefreshDisplay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:47:07 10/06/2010
-- Design Name:
-- Module Name: RefreshDisplay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- ... |
-------------------------------------------------------------------------------
-- Company : HSLU
-- Engineer : Gai, Waj
--
-- Create Date: 19-May-11
-- Project : RT Video Lab 1: Exercise 2
-- Description: Testbench for 5-tap FIR filter with loadable coefficients
-----------------------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.types.all;
entity lt24 is
port
(
CLOCK_50 : in std_logic;
KEY : in std_logic_vector(1 downto 0);
GPIO_0 : inout std_logic_vector(33 downto 0);
LT24_LCD_ON : out std_logic;
LT24_CS_N : out std_logic;
LT24_RESET_N : out std_l... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
----------------------------------------------------------------------------------
-- Company: Grad School
-- Engineer: Andreas Schuh
--
-- Create Date: 20:14:04 02/07/2013
-- Design Name:
-- Module Name: Statemachine - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Descrip... |
library ieee;
use ieee.std_logic_1164.all;
entity xnor104 is
port (
a_i : in std_logic_vector (103 downto 0);
b_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity xnor104;
architecture rtl of xnor104 is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity xnor104 is
port (
a_i : in std_logic_vector (103 downto 0);
b_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity xnor104;
architecture rtl of xnor104 is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity xnor104 is
port (
a_i : in std_logic_vector (103 downto 0);
b_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity xnor104;
architecture rtl of xnor104 is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity xnor104 is
port (
a_i : in std_logic_vector (103 downto 0);
b_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity xnor104;
architecture rtl of xnor104 is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity solver_tb is
end solver_tb;
architecture behavioral of solver_tb is
component solver
port (
clk: in std_logic;
reset: in std_logic;
sat: out std_logic;
unsat: out std_logic
);
end component;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package approximationTable is
constant approximationVector : std_logic_vector(268-1 downto 0) := ('1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1'... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
---------------... |
-------------------------------------------------------------------------------------
-- FILE NAME : fmc150_stellar_cmd.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - fmc150_stellar_cmd
-- architecture - fmc150_stellar_cmd_syn
--
... |
-- VHDL de um contador de modulo 16
-- OBS: Para esse experimento so eh utilizada a contagem ate 11
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity contador_16_recepcao is
port(
clock : in std_logic;
enable : in std_logic;
zera : in std_l... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLMULT_SDNF1_3_block4.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- --------------------------... |
entity bounds37 is
end entity;
architecture test of bounds37 is
signal x : integer_vector(4 downto 0);
signal y : integer_vector(1 downto 0);
signal z : integer_vector(2 downto 0);
signal i0, i1 : integer;
begin
main: process is
begin
x <= (1, 2, 3, 4, 5);
wait for 1 ns;
... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: ClocksPLL.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- =========================================... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mips_soc is
port (
-- CLOCK
CPU_CLK : in std_logic; -- 32.5 Mhz
VGA_CLK : in std_logic; -- VGA_CLK 25Mhz
CPU_RESET : in std_logic;
-- VGA
VGA_R : OUT STD_LOGIC_VECTOR... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--Practica4 de Diseño Automatico de Sistemas
--Cronometro.
--Fichero Principal.
--Desarrollada por Héctor Gutiérrez Palancarejo.
library ieee;
use ieee.std_logic_1164.all;
entity cronometer is
port(
clk : in std_logic;
rst : in std_logic;
sel : in std_logic;
puesta_zero : in std_logic;
start_... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: RAM_multiple_access
-- Module Name: RAM_multiple_access
-- Project Name: Essen... |
--==============================================================================
-- File: d_mem.vhd
-- Author: Pietro Lorefice
--==============================================================================
-- Description:
-- Data memory for the processor. Synchronous dual-port interface with two
-- unidirectiona... |
library verilog;
use verilog.vl_types.all;
entity Control_unit_vlg_vec_tst is
end Control_unit_vlg_vec_tst;
|
iafRefCell- |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
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