content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
entity mwe is
end mwe;
architecture lulz of mwe is
type sig_t is array (0 to 1) of std_logic_vector(1 downto 0);
signal sigw : sig_t := (others => (others => '0'));
signal sigf : sig_t := (others => (others => '0'));
signal clk : std_logic := '0';
begin
clk <= not clk af... |
library ieee;
use ieee.std_logic_1164.all;
entity mwe is
end mwe;
architecture lulz of mwe is
type sig_t is array (0 to 1) of std_logic_vector(1 downto 0);
signal sigw : sig_t := (others => (others => '0'));
signal sigf : sig_t := (others => (others => '0'));
signal clk : std_logic := '0';
begin
clk <= not clk af... |
library ieee;
use ieee.std_logic_1164.all;
entity mwe is
end mwe;
architecture lulz of mwe is
type sig_t is array (0 to 1) of std_logic_vector(1 downto 0);
signal sigw : sig_t := (others => (others => '0'));
signal sigf : sig_t := (others => (others => '0'));
signal clk : std_logic := '0';
begin
clk <= not clk af... |
library ieee;
use ieee.std_logic_1164.all;
entity full_addr_1_bit is
port(
A: in std_logic;
B: in std_logic;
Cin: in std_logic; -- carry
S: out std_logic;
Cout: out std_logic -- carry out
);
end;
architecture full_addr_1_bit_beh of full_addr_1_bit is
begin
S <= A ... |
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessor_types.all;
entity packetprocessor_readnew is
port(w3 : in unsigned(10 downto 0);
w4 : in std_log... |
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessor_types.all;
entity packetprocessor_readnew is
port(w3 : in unsigned(10 downto 0);
w4 : in std_log... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:42:35 07/12/2010
-- Design Name:
-- Module Name: BMS_small - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
-------------------------------------------------------------------------------
--! @file AEAD_Arch.vhd
--! @brief Architecture of authenticated encryption unit.
--! Note: This file should not be modified by a user.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirik... |
-- Add_Frame_GN.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.25.10:37:27
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Add_Frame_GN is
port (
Avalon_ST_Sink_data : in std_logic_vector(23 downto 0) := (others => '0'); -- ... |
-- Add_Frame_GN.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.25.10:37:27
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Add_Frame_GN is
port (
Avalon_ST_Sink_data : in std_logic_vector(23 downto 0) := (others => '0'); -- ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Daniel Sánchez Huerta
--
-- Create Date: 19:04:59 12/18/2013
-- Design Name:
-- Module Name: VGA - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencie... |
library ieee;
use ieee.std_logic_1164.all;
entity programCounter is
port(clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0)
);
end programCounter;
architecture bhv of programCounter... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.BusMasters.all;
entity ADT7310P32S32_tb is
end ADT7310P32S32_tb;
architecture behavior of ADT7310P32S32_tb is
component ADT7310P32S32
port (
Reset_n_i : in std_logic;
Clk_i : in std_l... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | _... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Tue Jun 21 04:38:22 2016
-- Host : jalapeno running 64-bit unknown
-- C... |
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
architecture RTL of FIFO is
function func_1 (a : integer) return integer is
constant c : integer;
variable v : integer;
file f : something;
alias a is name;
begin
end function func1;
function func_1 (a : integer) return integer is
constant c : integer;
variable v : integer;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
package bus_pkg is
-- Busmaster
type busmaster_out_type is record
addr : std_logic_vector(14 downto 0);
data : std_logic_vector(15 downto 0);
re : std_logic;
we : std_logic;
end record;
type busmaster_in_type is record
data ... |
library ieee;
use ieee.std_logic_1164.all;
package bus_pkg is
-- Busmaster
type busmaster_out_type is record
addr : std_logic_vector(14 downto 0);
data : std_logic_vector(15 downto 0);
re : std_logic;
we : std_logic;
end record;
type busmaster_in_type is record
data ... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - ... |
package pack is
procedure proc (x : out integer);
end package;
package body pack is
procedure proc (x : out integer) is
begin
x := 5;
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue109 is
end entity;
use work.pac... |
package pack is
procedure proc (x : out integer);
end package;
package body pack is
procedure proc (x : out integer) is
begin
x := 5;
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue109 is
end entity;
use work.pac... |
package pack is
procedure proc (x : out integer);
end package;
package body pack is
procedure proc (x : out integer) is
begin
x := 5;
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue109 is
end entity;
use work.pac... |
package pack is
procedure proc (x : out integer);
end package;
package body pack is
procedure proc (x : out integer) is
begin
x := 5;
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue109 is
end entity;
use work.pac... |
package pack is
procedure proc (x : out integer);
end package;
package body pack is
procedure proc (x : out integer) is
begin
x := 5;
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue109 is
end entity;
use work.pac... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-------------------------------------------------------------------------------
-- Title : Ethernet Lane
-- Project : General Purpose Core
-------------------------------------------------------------------------------
-- File : EthRx.vhd
-- Author : Kurtis Nishimura
----------------------... |
--------------------------------------------------------------------------------
-- wpa2_compare.vhd
-- Calculates PRF with pairwise key expansion to compare against given MIC
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 13:39:51 11/14/2015
-- Design Name:
-- Module Name: IF_ID_REG - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependen... |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_ram_dq0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ==============... |
entity a is
end entity;
architecture b of a is
signal x, y : bit;
signal z : bit_vector(3 downto 0);
alias xa is x;
alias za : bit is z(2);
begin
-- wait for
process is
begin
wait for ps;
wait for 5 ns;
wait for 2 * 4 hr;
wait for 523; -- Not ... |
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF ... |
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: mblite_sdram
-- Date:2015-01-02
-- Author: Gideon
-- Description: mblite processor with sdram interface - test module
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: mblite_sdram
-- Date:2015-01-02
-- Author: Gideon
-- Description: mblite processor with sdram interface - test module
------------------------------------------------------... |
entity repro1 is
end repro1;
architecture behav of repro1 is
signal s1, s2 : bit;
component comp port (i : in bit; o : out bit);
end component;
begin
s1 <= '1';
c : comp port map (i => s1, o => s2);
end behav;
|
entity repro1 is
end repro1;
architecture behav of repro1 is
signal s1, s2 : bit;
component comp port (i : in bit; o : out bit);
end component;
begin
s1 <= '1';
c : comp port map (i => s1, o => s2);
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
entity block01 is
port (q : out std_logic;
d : std_logic;
clk : std_logic);
end block01;
architecture behav of block01 is
begin
b1 : block
begin
process (clk) is
begin
if rising_edge (clk) then
q <= d;
end if;
end process... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- Testbench for schedulectrl.vhd
--
-- Project :
-- File : tb_schedulectrl.vhd
-- Author : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003-10-17
-- L... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_ok_5_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: in... |
-- VHDL de um verificador de fim de jogo para o jogo da velha
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity verifica_fim is
port(
jogador_atual: in std_logic; -- jogador atual de acordo com a memoria do tabuleiro
jogadas_realizadas: i... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
entity no_messages is
generic (
DIVIDER : integer := 10
);
port (
reset : in std_logic;
clk_input : in std_logic;
clk_output : out std_logic
);
end no_messages;
architecture no_messages of no_messages is
begin
end no_messag... |
-----------------------------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : Package File Constants
-- Author : Jan Dürre
-- Last update : 21.05.2015
-- Description : -
--------------------------------------------------------------------------... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / ... |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / ... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sat May 27 21:33:31 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- megafunction wizard: %ALTFP_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_add_sub
-- ============================================================
-- File Name: add_flt_stratix5_latency.vhd
-- Megafunction Name(s):
-- altfp_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ===========... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY ComplexConditions IS
PORT(
clk : IN STD_LOGIC;
ctrlFifoLast : IN STD_LOGIC;
ctrlFifoVld : IN STD_LOGIC;
rst : IN STD_LOGIC;
s_idle : OUT STD_LOGIC;
sd0 : IN STD_LOGIC;
sd1 : IN STD_LOG... |
---------------------------------------------------------------------------
-- Package TEXTIO as defined in Chapter 14 of the IEEE Standard VHDL
-- Language Reference Manual (IEEE Std. 1076-1987), as modified
-- by the Issues Screening and Analysis Committee (ISAC), a subcommittee
-- of the VHDL Analysis and ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use WORK.alu_types.all;
-- Entity
entity P4ADDER is
generic(
N: integer:= NSUMG
);
port (
A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(N-1 downto 0);
Cin: in std_logic;
S: out std_logic_vec... |
entity e is
end entity;
architecture a of e is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type bad1 is protected
procedure foo (x : not_her... |
library ieee;
use ieee.std_logic_1164.all;
package track_pkg is
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant sdrom_array : t_byte_array := (
X"55", X"55", X"55", X"55", X"55", X"55", X"55", X"55", X"55", X"55", X"55", X"55", X"55", X"55", X"55", X"55",
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
port (
clk : in std_logic;
write : in std_logic;
addr : in std_logic_vector(1 downto 0);
data_write : in std_logic_vector(3 downto 0);
x0 : out std_logic_vector(3 downto 0);
x1 : out std_logic_vector(3 downto 0);
... |
------------------------------------------------------
-- Four Bit Up-Down Counter
-- File Name : counter_sig.vhd
-- Data Type : std_logic_vector
-- Reset : Asynchronous
-- Active : Low
------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_signed.A... |
-------------------------------------------------------------------------------
-- File Name : OutMux.vhd
--
-- Project : JPEG_ENC
--
-- Module : OutMux
--
-- Content : Output Multiplexer
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : OutMux.vhd
--
-- Project : JPEG_ENC
--
-- Module : OutMux
--
-- Content : Output Multiplexer
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
------------------------------------... |
-------------------------------------------------------------------------------
-- synch_bus_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library bfm_synch_v1_00_a;
use bfm_synch_v1_00... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY system IS
PORT(rst: IN std_logic; -- system reset, high active
clk: IN std_logic; -- system clock, 50 MHz, rising edge active
btn0: IN std_logic; -- push button, low active
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive ... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 12.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 12.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 12.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 12.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
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