content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--------------------------------------------------------------------------------
---
--- Ethernet MAC for Nexsys3 board
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
--- Revised by Amer Al-Canaan ... |
library verilog;
use verilog.vl_types.all;
entity usb_system_cpu_nios2_oci_debug is
port(
clk : in vl_logic;
dbrk_break : in vl_logic;
debugreq : in vl_logic;
hbreak_enabled : in vl_logic;
jdo : in vl_logic_vector(37 do... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std... |
-------------------------------------------------------------------------------
-- system_proc_sys_reset_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library proc_sys_reset_v3_00_a;
... |
-------------------------------------------------------------------------------
-- system_proc_sys_reset_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library proc_sys_reset_v3_00_a;
... |
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | _... |
architecture rtl of fifo is
type t_record is record
a : std_logic;
b : std_logic;
end record;
type t_record is record a : std_logic;
b : std_logic;
end record;
type t_record is record a : std_logic; b : std_logic; end record;
begin
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity ieee1 is
end entity;
architecture test of ieee1 is
begin
process is
variable a, b, c : std_logic_vector(3 downto 0);
variable d : std_logic_vector(5 downto 0);
begin
a := ( '0', '1', '0', '0' );
b := ( '1', '0', '1', '0' );
... |
library ieee;
use ieee.std_logic_1164.all;
entity ieee1 is
end entity;
architecture test of ieee1 is
begin
process is
variable a, b, c : std_logic_vector(3 downto 0);
variable d : std_logic_vector(5 downto 0);
begin
a := ( '0', '1', '0', '0' );
b := ( '1', '0', '1', '0' );
... |
library ieee;
use ieee.std_logic_1164.all;
entity ieee1 is
end entity;
architecture test of ieee1 is
begin
process is
variable a, b, c : std_logic_vector(3 downto 0);
variable d : std_logic_vector(5 downto 0);
begin
a := ( '0', '1', '0', '0' );
b := ( '1', '0', '1', '0' );
... |
library ieee;
use ieee.std_logic_1164.all;
entity ieee1 is
end entity;
architecture test of ieee1 is
begin
process is
variable a, b, c : std_logic_vector(3 downto 0);
variable d : std_logic_vector(5 downto 0);
begin
a := ( '0', '1', '0', '0' );
b := ( '1', '0', '1', '0' );
... |
library ieee;
use ieee.std_logic_1164.all;
entity ieee1 is
end entity;
architecture test of ieee1 is
begin
process is
variable a, b, c : std_logic_vector(3 downto 0);
variable d : std_logic_vector(5 downto 0);
begin
a := ( '0', '1', '0', '0' );
b := ( '1', '0', '1', '0' );
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vga_rgb888_pack is
port (
rgb888 : in std_logic_vector(23 downto 0);
data : out std_logic_vector(31 downto 0)
);
end vga_rgb888_pack;
architecture Behavioral of vga_rgb888_pack is
begin
data(23 downto 0) <= rgb888;
data(31 downto 24) <=... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity main is
end entity main;
architecture main of main is
type enum1 is ('A', 'B');
type enum2 is ('B', 'A');
procedure p1 (variable a: in enum1; variable b : in enum1) is
begin
report "p1 called";
end;
procedure p1 (variable a: in enum2; variable b : in enum2) is
... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Tue Mar 6 12:38:07 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -variant Ifelsif -nodelta -bak ../../macro.xls
--
--... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Find_Correct_Errors_N
-- Module Name: Controller_Find_Correct_Errors... |
----------------------------------------------------------------------------------
-- Company: Lake Union Bell
-- Engineer: Nick Burrows
--
-- Create Date: 20:48:18 09/22/2011
-- Design Name:
-- Module Name: WordRegister - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
--Part of Mano Basic Computer
--Behzad Mokhtari; MokhtariBehzad@Gmail.com
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--Memory
Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
use STD.textio.all;
Library manoBasic; use manoBasic.defines.al... |
-------------------------------------------------------------------------------
-- Copyright Institut Pascal Equipe Dream (19-10-2016)
-- Francois Berry, El Mehdi Abdali, Maxime Pelcat
-- This software is a computer program whose purpose is to manage dynamic
-- partial reconfiguration.
-- This software is gov... |
library IEEE;
use IEEE.std_logic_1164.all;
use work.NoCPackage.all;
entity topNoC is
end;
architecture topNoC of topNoC is
component inputmodule
port
(
clock : in std_logic;
reset : in std_logic;
incredit : in regNrot;
outtx : out regNrot;
outdata : out arrayNrot_r... |
-- Teste geral para a estrutura do Processador Mips8B
Library Ieee;
Use Ieee.Std_Logic_1164.all;
Use Ieee.Numeric_Std.all;
Entity test_processor is
End Entity test_processor;
Architecture test_general of test_processor is
Component Mips8B is
Port(Reset_n: In Std_Logic;
Clock: In Std_Logic;
... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "Instruction_Provider"
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : Instru... |
-- fsm.vhd: Finite State Machine
-- Author(s): David Mikus(xmikus15@stud.fit.vutbr.cz)
--
library ieee;
use ieee.std_logic_1164.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- -----------------------------------------------------------... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
library ieee;
use ieee.std_logic_1164.all;
entity tb_mixer is
end tb_mixer;
architecture behav of tb_mixer is
signal h, l, o : std_logic_vector (7 downto 0);
begin
dut : entity work.mixer
port map (h => h, l => l, o => o);
process
begin
h <= x"00";
l <= x"ab";
wait for 1 ns;
assert o = x"... |
library ieee;
use ieee.std_logic_1164.all;
entity tb_mixer is
end tb_mixer;
architecture behav of tb_mixer is
signal h, l, o : std_logic_vector (7 downto 0);
begin
dut : entity work.mixer
port map (h => h, l => l, o => o);
process
begin
h <= x"00";
l <= x"ab";
wait for 1 ns;
assert o = x"... |
---------------------------------------------------------------------------
-- Copyright 2015 - 2017 Systems Group, ETH Zurich
--
-- This hardware module is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_audio IS
END tb_audio;
ARCHITECTURE behavior OF tb_audio IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT topModule
PORT(
CLK : IN std_logic;
AUDIO1_RIGHT : OUT std_logic
);
END COMPONENT;
... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:19:36)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir1_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, ... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2012 Fredrik Ringhage, Gaisler Research
-- Modified by Jiri Gaisler, 2014-04-05
------------------------------------------------------------------------------
-- This file is a par... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2012 Fredrik Ringhage, Gaisler Research
-- Modified by Jiri Gaisler, 2014-04-05
------------------------------------------------------------------------------
-- This file is a par... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2012 Fredrik Ringhage, Gaisler Research
-- Modified by Jiri Gaisler, 2014-04-05
------------------------------------------------------------------------------
-- This file is a par... |
package ppkg is
procedure rep1 (msg : string := "failure");
procedure rep2;
procedure rep3;
end ppkg;
package body ppkg is
procedure rep1 (msg : string := "failure") is
begin
report msg;
end rep1;
procedure rep2 is
begin
rep1;
rep1;
end rep2;
procedure rep3 is
begin
rep1;
... |
package ppkg is
procedure rep1 (msg : string := "failure");
procedure rep2;
procedure rep3;
end ppkg;
package body ppkg is
procedure rep1 (msg : string := "failure") is
begin
report msg;
end rep1;
procedure rep2 is
begin
rep1;
rep1;
end rep2;
procedure rep3 is
begin
rep1;
... |
package ppkg is
procedure rep1 (msg : string := "failure");
procedure rep2;
procedure rep3;
end ppkg;
package body ppkg is
procedure rep1 (msg : string := "failure") is
begin
report msg;
end rep1;
procedure rep2 is
begin
rep1;
rep1;
end rep2;
procedure rep3 is
begin
rep1;
... |
package ppkg is
procedure rep1 (msg : string := "failure");
procedure rep2;
procedure rep3;
end ppkg;
package body ppkg is
procedure rep1 (msg : string := "failure") is
begin
report msg;
end rep1;
procedure rep2 is
begin
rep1;
rep1;
end rep2;
procedure rep3 is
begin
rep1;
... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
----
-- Original authors: Blake Johnson and Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
--
-- InternalTrig module
--
-- Produce trigger signal on a counter or from a command.
----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
entity Intern... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sounds is
port(
clk, not_reset: in std_logic;
enable: in std_logic;
period: in std_logic_vector(18 downto 0);
volume: in std_logic_vector(2 downto 0);
buzzer: out std_logic
);
end sounds;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sounds is
port(
clk, not_reset: in std_logic;
enable: in std_logic;
period: in std_logic_vector(18 downto 0);
volume: in std_logic_vector(2 downto 0);
buzzer: out std_logic
);
end sounds;
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:15:26 02/12/2014
-- Design Name:
-- Module Name: rca_4_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:54 2017
-- Host : KLight-PC running 64-bit major relea... |
context c1;
library ieee;
context c2;
context con1 is
library ieee;
context c3;
end context con1;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- revision history:
-- 06.08.2015 Patrick Appenheimer created
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
library WORK;
use WORK.cpu_pack.all;
entity tb_cpu_datapath is
end entity tb_cpu_datapath;
architecture behav_tb_cpu_datapath of tb_cpu_datapath is
-- -------- SIMULA... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivat... |
--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivat... |
-- NEED RESULT: ARCH00194.P2: Transaction occurred on signal asg with no time expression -- 0 ns assumed passed
-- NEED RESULT: ARCH00194.P1: Transaction occurred on signal asg with no time expression -- 0 ns assumed passed
-- NEED RESULT: P2: Inertial transactions entirely completed passed
-- NEED RESULT: P1: Ine... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
-- synthesis translate_on
-------------------------------------------------... |
-- NEED RESULT: ARCH00441: Allowable replacement of characters passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
--------------------------------------------------------------------... |
-- written by panooz
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use STD.TEXTIO.all;
library UNISIM;
use UNISIM.VComponents.all;
use IEEE.STD_LOGIC_TEXTIO.all;
entity tb is
end tb;
architecture testbench of tb is
signal simclk : std_logic := '0';
si... |
---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller ----
---- ATA/ATAPI-5 Controller (OCIDEC-2) ----
---- ... |
---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller ----
---- ATA/ATAPI-5 Controller (OCIDEC-2) ----
---- ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity View is
port (
DIN : in STD_LOGIC_VECTOR(15 downto 0);
Resetn, Clock, Run : in STD_LOGIC;
Done : out STD_LOGIC;
BusWires : buffer STD_LOGIC_VECTOR(15 downto 0)
);
end View;... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity View is
port (
DIN : in STD_LOGIC_VECTOR(15 downto 0);
Resetn, Clock, Run : in STD_LOGIC;
Done : out STD_LOGIC;
BusWires : buffer STD_LOGIC_VECTOR(15 downto 0)
);
end View;... |
-- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo AudioVideo_Config.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- ******************************... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
library ieee;
use ieee.std_logic_1164.all;
entity multiplier is
generic (
N : integer := 8
);
port (
clock : in std_logic;
load : std_logic;
A : in std_logic_vector(N-1 downto 0);
B : in std_logic_vector(N-1 downto 0);
result : out std_logic_vector(2*N-1 down... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
package cpu_pkg is
-- signed/unsigned extension
function unsiext1 (input : in STD_LOGIC_VECTOR( 7 downto 0))
return STD_LOGIC_VECTOR;
function unsiext2 (input ... |
-------------------------------------------------------------------------------
-- $Id: ip2bus_dmux_blk.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- ip2bus_dmux_blk.vhd - VHD design file
--------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: ip2bus_dmux_blk.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- ip2bus_dmux_blk.vhd - VHD design file
--------------------------------------------------... |
-- FT SDRAM controller
constant CFG_FTSDCTRL : integer := CONFIG_FTSDCTRL;
constant CFG_FTSDCTRL_INVCLK : integer := CONFIG_FTSDCTRL_INVCLK;
constant CFG_FTSDCTRL_EDAC : integer := CONFIG_FTSDCTRL_EDAC + CONFIG_FTSDCTRL_EDAC_RS*2;
constant CFG_FTSDCTRL_PAGE : integer := CONFIG_FTSDCTRL_PAGE + CONFIG_FT... |
-- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your opt... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
----------------------------------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Copyright (C) 2012-2021 Nick Gasson
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http:... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_... |
---------------------------------------------------------------------
-- Microbuffer
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- A small buffer with a FIFO-like interface, implemented
-- using registers.
---------------------------------------------------------------------
library i... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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