content stringlengths 1 1.04M ⌀ |
|---|
-- Twofish_ecb_decryption_monte_carlo_testbench_128bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at y... |
--------------------------------------------------------------------------------
-- FILE: CwGenerator
-- DESC: Generate Control Word
--
-- Author:
-- Create: 2015-05-30
-- Update: 2015-09-02
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_lo... |
library ieee;
use ieee.std_logic_1164.all;
entity trafficLight is
port ( clock : in std_logic;
Sa : in std_logic;
Sb : in std_logic;
Ga : out std_logic;
Ya : out std_logic;
Ra : out std_logic;
Gb : out std_logic;
Yb : out std_logic;
Rb : out std_logic);
end trafficLight;
architecture trafficLight_ar... |
----------------------------------------
-- INCR : IITB-RISC
-- Author : Sainath
-- Date : 18/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PCImmAdd is
port (
input1 : in std_logic_vector(15 downto 0); -- 16 std_logic input
input2 ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
entity t2 is
end t2;
architecture behav of t2 is
constant my_const : std_ulogic_vector := "01XWL";
constant my_str : string := "Hello";
begin
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity t2 is
end t2;
architecture behav of t2 is
constant my_const : std_ulogic_vector := "01XWL";
constant my_str : string := "Hello";
begin
end;
|
-- MMCM_BASE : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the body of the design code. The instance name
-- declaration : (MMCM_BASE_inst) and/or the port declarations after the
-- code : "=>" declaration m... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity code_det_tb is
end entity;
architecture code_det_tb of code_det_tb is
component code_det is
port (
clk : in std_logic;
I : in std_logic_vector (3 downto 0);
O : out std... |
--****************************************************************
-- Copyright 2013, Ryan Henderson
-- CMOS digital camera controller and frame capture device
--
-- comp_pckgs.vhd
--
-- Contains packages common and comp_pckgs. package common
-- defines some constants and functions used in the design.
-- comp_pckgs... |
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1... |
-------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
---------------------------------------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- NEED RESULT: ARCH00534: LEFT, RIGHT, HIGH, LOW attributes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
----------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Design Name : led_top
-- Create Date : 2015/12/31
-- Module Name :
-- Project Name :
-- Target Devices:
-- Tool Versions :
-- Description :
-- Revision :
-- Additional Comments:
--
---------------------------------... |
-- $Id: nexys2_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: nexys2_dummy - syn
-- Description: nexys... |
library verilog;
use verilog.vl_types.all;
entity reservation_free_entry_count is
port(
iINFO0 : in vl_logic;
iINFO1 : in vl_logic;
iINFO2 : in vl_logic;
iINFO3 : in vl_logic;
iINFO4 : in vl_logic;
iINFO... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY comparator IS
PORT ( INPUT : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- (3)=A, (2)=B, (1)=C, (0)=D
OUTPUT : OUT STD_LOGIC -- F0, F1, F2
);
END comparator;
ARCHITECTURE Behaviour OF comparator IS
BEGIN
OUTPUT <= (NOT INPUT(3) AND NOT INPUT(1)) OR (NOT INPUT(3) AND... |
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is
begin
a <= b;
end block;
-- Violations below
BLOCK_LABEL : block is
begin
a <= b;
end block;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity debouncer is
Port (
clock_i : in std_logic;
reset_i : in std_logic;
input_i : in std_logic;
output_o : out std_logic;
change_on_o : out std_logic;
change_off_o : out std_logic
);
end debouncer;
architecture ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20... |
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
entity ALUSrcMux is
port (
ALUSrc: in ctrl_t;
reg2data : in word_t;
-- Instruction 15-0 Address/Immediate
immediate : in word_t;
output : out word_t
);
end entity;
architecture behav... |
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com
--
-- This source file is free software: you ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_792 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_792;
architecture augh of cmp_792 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_792 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_792;
architecture augh of cmp_792 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
------------------------------------------------------------------------------
--
-- Miscellaneous Utility Functions
--
-- Author: Johann Glaser
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package Utils is
function WidthFromMax (x : p... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:35:58 06/03/2011
-- Design Name:
-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IPv4_TX_tb.vhd
-- Project Name: ip1
-- Target Device:
-- Tool versions:
--... |
-- Design:
-- Testbench for the Arithmetic Logic Unit of the Freon core.
-- Tests taken from: https://github.com/riscv/riscv-tests
--
-- Authors:
-- Pietro Lorefice <pietro.lorefice@gmail.com>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu_tb is
end entity; -- alu_tb
architecture tb ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
--
-- MIT License
--
-- Copyright (c) 2017 Mathias Helsen, Arne Vansteenkiste
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rig... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:02 03/28/2016
-- Design Name:
-- Module Name: ALU_Toplevel - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
library verilog;
use verilog.vl_types.all;
entity FABRICIF_HM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
apb32 : in vl_logic;
lastCycle : in vl_logic;
FPGAGOOD : in ... |
library verilog;
use verilog.vl_types.all;
entity FABRICIF_HM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
apb32 : in vl_logic;
lastCycle : in vl_logic;
FPGAGOOD : in ... |
library verilog;
use verilog.vl_types.all;
entity FABRICIF_HM is
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
ahbMode : in vl_logic;
apb32 : in vl_logic;
lastCycle : in vl_logic;
FPGAGOOD : in ... |
-------------------------------------------------------------------------------
-- Title : Testbench for SpW Node
-------------------------------------------------------------------------------
-- Author : Carl Treudler
-------------------------------------------------------------------------------
-- Descrip... |
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant0.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- =========================... |
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, after, enumerations, physical-types... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : VITAL
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Title : Components package
-- Project : Loa
-------------------------------------------------------------------------------
-- File :
-- Author : strongly-typed
-- Created : 2012-04-10
-- Platform :
-- Standard ... |
-------------------------------------------------------------------------------
-- Title : Components package
-- Project : Loa
-------------------------------------------------------------------------------
-- File :
-- Author : strongly-typed
-- Created : 2012-04-10
-- Platform :
-- Standard ... |
library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_multiplexer is
generic
(
width : integer := 4;
no_of_inputs : integer := 2;
select_size : integer := 1
);
port
(
input : in std_logic_vector(((width * no_of_inputs) - 1) downto 0);
mux_select : in std_logic_vector ((select_s... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
--... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity corwrapcontrol is
port(clk: in std_logic;
slave: in std_logic;
grant: in std_logic;
done_in: in std_logic;
rst: in std_logic;
done_out: out std_logic;
store: out std_logic;
en: out std_logic;
start: out std_logic;
r... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package cpu_pack is
type cycle is ( M1, M2, M3, M4, M5 );
type op_category is (
INTR,
HALT_WAIT,
-- 0X
HALT,
NOP,
JMP_i,
JMP_RRNZ_i... |
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package cpu_pack is
type cycle is ( M1, M2, M3, M4, M5 );
type op_category is (
INTR,
HALT_WAIT,
-- 0X
HALT,
NOP,
JMP_i,
JMP_RRNZ_i... |
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package cpu_pack is
type cycle is ( M1, M2, M3, M4, M5 );
type op_category is (
INTR,
HALT_WAIT,
-- 0X
HALT,
NOP,
JMP_i,
JMP_RRNZ_i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE test_ctrl_parameter_pkg IS
TYPE device_t IS (
DEVICE_NONAME,
DEVICE_TEST
);
-----------------------------------------------------------------------------
-- DDR SDRAM device definitions
---------------------------------------------... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE test_ctrl_parameter_pkg IS
TYPE device_t IS (
DEVICE_NONAME,
DEVICE_TEST
);
-----------------------------------------------------------------------------
-- DDR SDRAM device definitions
---------------------------------------------... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
----------... |
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 11:45:38 11/10/2015
-- Design Name:
-- Module Name: Equation_motor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Des... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Display_Controller is
Port (
-- User logic clock
CLK : in STD_LOGIC; -- 60 Mhz Clock
-- Display Outputs:
PIXEL : inout STD_LOGIC_VECTOR(8 downto 0) := "111100110";
HSYNC : inout STD_LOGIC := '0... |
package one is
type my_int is range 0 to 100;
function add_one(x : my_int) return my_int;
end package;
-------------------------------------------------------------------------------
use work.one.all;
package two is
subtype my_int2 is work.one.my_int range 10 to 50;
end package two;
-------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity Bresenhamer is
Port ( WriteEnable : out STD_LOGIC;
X : out STD_LOGIC_VECTOR (9 downto 0);
Y : out STD_LOGIC_VECTOR (8 downto 0);
X1 : in STD_LOGIC_VECTOR (9 downto 0);
Y1 : in STD_LO... |
entity gensub6 is
end entity;
architecture test of gensub6 is
procedure proc
generic (procedure preal(value : out real);
procedure pint(value : out integer))
(x : out integer; y : out real) is
begin
preal(y);
pint(x);
end procedure;
procedure get gener... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vga_cdma_control is
port (
clk : in std_logic;
active : in std_logic;
x_addr_r : in std_logic_vector(9 downto 0);
y_addr_r : in std_logic_vector(9 downto 0);
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in s... |
--
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:... |
---- Design Name: ccsds_tx_coder_differential
---- Version: 1.0.0
---- Description:
---- Word by word differential coder
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/18: initi... |
--!
--! Copyright (C) 2010 - 2013 Creonic GmbH
--!
--! @file: counter_tb.vhd
--! @brief: tb of counter
--! @author: Antonio Gutierrez
--! @date: 2014-05-23
--!
--!
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-----------------------------... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:08:04 2017
-- Host : EffulgentTome running 64-bit major r... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:49:58 01/01/2010
-- Design Name:
-- Module Name: C:/Users/georgecuris/Desktop/Back Up/FPGA/Projects/Current Projects/Systems/OZ-3/OZ3_TB.vhd
-- Project Name: OZ-3
-- Target De... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:49:58 01/01/2010
-- Design Name:
-- Module Name: C:/Users/georgecuris/Desktop/Back Up/FPGA/Projects/Current Projects/Systems/OZ-3/OZ3_TB.vhd
-- Project Name: OZ-3
-- Target De... |
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: PhSeROM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ==============================... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.BusMasters.all;
entity SlowADT7410_tb is
end SlowADT7410_tb;
architecture behavior of SlowADT7410_tb is
component SlowADT7410
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
... |
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <piat.jonathan@gmail.com>
--
-- Create Date: 15:31:55 03/22/2013
-- Design Name:
-- Module Name: smal_stack - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool ver... |
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <piat.jonathan@gmail.com>
--
-- Create Date: 15:31:55 03/22/2013
-- Design Name:
-- Module Name: smal_stack - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool ver... |
library IEEE;
use IEEE.std_logic_1164.all;
entity pfb_core_v5 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
pol1_in1: in std_logic_vector(15 downto 0);
sync: in std_logic;
pol1_out1: out std_logic_vector(35 downto 0);
sync_out: out std_logic
);
end pfb_core_v5;
architecture struc... |
------------------------------------------------------------------------------
-- Title : Top FMC516 design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-09-26
-- Platform : FPGA-generic
-----... |
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