content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
library work ;
use work.cordic_p.all ;
entity fsk_demodulator is
port (
clock : in std_logic ;
reset : in std_logic ;
in_real : in signed(15 downto 0) ;
in_imag : in sign... |
----------------------------------------------------------------------------------
-- Module Name: test_source_800_600_RGB_444_ch4 - Behavioral
--
-- Description: Generate a valid DisplayPort symbol stream for testing. In this
-- case 800x600 white screen.
--
-------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_axi_buffer_v1_0_SAXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI addr... |
----------------------------------------------------------------------------------
-- Company: Federal University of Santa Catarina
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision: ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_dynclk_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bu... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_dynclk_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bu... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_dynclk_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bu... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_dynclk_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bu... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_dynclk_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bu... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_dynclk_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bu... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_dynclk_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bu... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_dynclk_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bu... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_dynclk_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bu... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_dynclk_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bu... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_dynclk_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bu... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- generates pwm signal for motor
entity pwm_control is
generic(
-- clock 500KHz, 0.8ms-2.3ms for 0-180 degrees
--low_bound: integer := 400;
--high_bound: integer := 1300;
low_bound: ... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_LOGIC is
generic (N: integer := 8);
port (CLK, PUSH, POP, INIT: in std_logic;
ADD: out std_logic_vector(N-1 downto 0);
BUFF: buffer std_logic_vector(3 downto 0);
FULL, EMPTY, WE, NOPUSH, NOPOP: buffer st... |
-- Dmemory module (implements the data
-- memory for the MIPS computer)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY dmemory IS
PORT(
read_data : OUT STD_LOG... |
----------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2014 Brian K. Nemetz
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in... |
-------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
architecture test of test2 is
constant foo : bar := 32b"12345";
begin end;
|
-- NEED RESULT: ARCH00089.P1: Multi transport transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00089.P2: Multi transport transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00089.P3: Multi transport transactions occurred on signal asg with s... |
----------------------------------------------------------------------------------------------------------
-- Control Unit Hardwired: Purpose of this unit is to generate the correct CW and ALUOP depending on the
-- value of the OPCODE and FUNC field.
-- Three LUTs have been used: one for the Control Word, one for al... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:20 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $... |
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 15.11.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB ... |
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 15.11.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB ... |
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 15.11.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB ... |
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 15.11.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB ... |
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 15.11.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB ... |
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 15.11.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB ... |
architecture RTL of FIFO is
attribute mark_debug of wr_en : signal is "true";
attribute mark_debug of almost_empty : signal is "true";
attribute mark_debug of full : signal is "true";
begin
end architecture RTL;
|
library verilog;
use verilog.vl_types.all;
entity MUX8_1_32 is
port(
Sel : in vl_logic_vector(2 downto 0);
S0 : in vl_logic_vector(31 downto 0);
S1 : in vl_logic_vector(31 downto 0);
S2 : in vl_logic_vector(31 downto ... |
-- PCIEXP interface
constant CFG_PCIEXP : integer := CFG_PCIE;
constant CFG_PCIE_TYPE : integer := CFG_PCIETYPE;
constant CFG_PCIE_SIM_MAS : integer := CFG_PCIEMASTER;
constant CFG_PCIEXPVID : integer := 16#CONFIG_PCIEXP_VENDORID#;
constant CFG_PCIEXPDID : integer := 16#CONFIG_PCIEXP_DEVICEID#;
co... |
PACKAGE rteasy_functions IS
FUNCTION bool_signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN boolean;
FUNCTION signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_le (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
... |
PACKAGE rteasy_functions IS
FUNCTION bool_signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN boolean;
FUNCTION signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_le (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
... |
PACKAGE rteasy_functions IS
FUNCTION bool_signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN boolean;
FUNCTION signed_lt (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
FUNCTION signed_le (a, b : std_logic_vector; sign_index : natural)
RETURN std_logic_vector;
... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Thomas B. Preusser
-- Patr... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_187 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_187;
architecture augh of cmp_187 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_187 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_187;
architecture augh of cmp_187 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
--------------------------------------------------------------------------------
--
-- Title : cl_square.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Game... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity mdr is
port(
clock : in std_logic;
busC : in std_logic_vector(15 downto 0);
latch : in std_logic;
memo : in std_logic_vector(15 downto 0);
sel : in std_logic;... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity mdr is
port(
clock : in std_logic;
busC : in std_logic_vector(15 downto 0);
latch : in std_logic;
memo : in std_logic_vector(15 downto 0);
sel : in std_logic;... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity control is
port(
--inputs
clk: in std_logic;
rst: in std_logic;
current_pc: in unsigned(15 downto 0);
current_instruction: in unsigned(14 downto 0);
c_flag: in std_logic;
z_flag: in std_logic;
n_flag: in std_logic... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sherpa_rxtx is
port(
reset_in : in std_logic;
-- Clock interface --------------------------------------------------------------------------
usb_clk_in : in std_logic;
adc_clk_in : in std_logic;
dac_clk_in : in s... |
--==============================================================================
-- File: alu.vhd
-- Author: Pietro Lorefice
--==============================================================================
-- Description:
-- Arithmetic logic unit inside the processor. Asynchronous interface with
-- multiple outpu... |
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tma_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(5 downto 0)
);
end tma_rnd;
architecture behaviour of tma_rnd is
constant I0: std_logic_vector(4 downto 0) := "1110... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
package koc_signal_pack is
constant axi_resp_okay : std_logic_vector := "00";
component koc_signal is
generic (
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : in... |
--------------------------------------------------------------------------------
-- This code serial loads and pads message for SHA1 calculation
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Publi... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity core is
Port ( memRead : in STD_LOGIC_VECTOR (7 downto 0);
memWrite : out STD_LOGIC_VECTOR (7 downto 0);
memAddress : out STD_LOGIC_VECTOR (11 downto 0);
keyPad : in STD_LOG... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nic_v1_0_S00_AXI is
generic (
-- Users to add parameters here
USE_1K_NOT_4K_FIFO_DEPTH : boolean := true;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : in... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nic_v1_0_S00_AXI is
generic (
-- Users to add parameters here
USE_1K_NOT_4K_FIFO_DEPTH : boolean := true;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : in... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s1_rnd;
architecture behaviour of s1_rnd is
constant st0: std_logic_vector(4 downto 0) := "11101"... |
package pack is
generic ( n : integer ) ;
type t is (a, b, c);
end package ;
-------------------------------------------------------------------------------
package p5 is new work.pack generic map ( 5 );
entity genpack1 is
end entity;
use work.p5.all;
architecture test of genpack1 is
signal s : t;
begi... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.math_real.all;
PACKAGE FIR_constants IS
CONSTANT Nb : INTEGER := 9;
CONSTANT Ord: INTEGER := 8;
CONSTANT UO: INTEGER := 1;
CONSTANT Nbmult: INTEGER := 10;
CONSTANT Nbadder: INTEGER:= Nb; --NUM_BITS_MULT + integer(floor(log2(real(FIR_ORDER+1))));
CO... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:54:28 2017
-- Host : GILAMONSTER running 64-bit major rel... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:46:53 12/30/2015
-- Design Name:
-- Module Name: C:/Users/Kurtis/Desktop/mtcSvn/temp/LucaIRS3D_Ethernet_firmware/src/firmware-general/General/sim/EncodeDecode8b10b.vhd
-- Projec... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
--... |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: clockbuzzer1k.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================... |
-------------------------------------------------------------------------------
-- axi_sg_updt_sm
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights r... |
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <johannes@wltr.io>
--
-- Description:
-- Check for changes on one of the input channels.
--------------------------------------------------------------------------------
library ieee... |
-- $Id: sys_conf_sim.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either vers... |
library verilog;
use verilog.vl_types.all;
entity CONTROLLER is
port(
clock : in vl_logic;
\In\ : in vl_logic_vector(15 downto 0);
Zero : in vl_logic;
alu_cmd : out vl_logic_vector(3 downto 0);
rf_write_back_en: out vl... |
-- NEED RESULT: ARCH00329_Test_Bench: Component is declared but not instantiated passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
--------------------------------------------------... |
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_testbench is --test
generic ( -- test
n : integer := 8 -- test
); -- test
end top_testbench; -- test
architecture top_testbench_arch of top_testbench is
component top is
generic ... |
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_testbench is --test
generic ( -- test
n : integer := 8 -- test
); -- test
end top_testbench; -- test
architecture top_testbench_arch of top_testbench is
component top is
generic ... |
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_testbench is --test
generic ( -- test
n : integer := 8 -- test
); -- test
end top_testbench; -- test
architecture top_testbench_arch of top_testbench is
component top is
generic ... |
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_testbench is --test
generic ( -- test
n : integer := 8 -- test
); -- test
end top_testbench; -- test
architecture top_testbench_arch of top_testbench is
component top is
generic ... |
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