content stringlengths 1 1.04M ⌀ |
|---|
architecture RTL of ENT IS
begin
end RTL;
architecture RTL of ent is
begin
end rtl;
architecture RTL of Ent Is
begin
end Rtl;
architecture RTL of ENT is
begin
end;
architecture RTL of ENT is
begin
end architecture;
|
entity repro is
end repro;
entity buf is
port (i : bit; o : out bit);
end buf;
architecture behav of buf is
begin
o <= i;
end behav;
architecture behav of repro is
signal a, b : bit;
signal r : bit;
begin
dut: entity work.buf port map (i => a xor b, o => r);
process
begin
a <= '0';
b <= '1';
... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential ... |
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2009 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com
--
-- This source file is free software: you ... |
----------------------------------------------------------------------------------
-- Module Name: data_stream_test - Behavioral
--
-- Description: For sumulating the data stream, without the TX modules.
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from http... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cpuPipeline_tb is
end cpuPipeline_tb;
architecture cpuPipeline_tb_arch of cpuPipeline_tb is
component cpuPipeline is
port
(
clk : in std_logic;
reset : in std_logic;
four : INTEGER;
writeToRegisterFile : in std_logic;
writeToMemoryFile : in... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity top is
generic(
N: integer := 4;
M: integer := 8
);
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
COP : in std_logic;
d1 : in STD_LOGIC_VECTOR(2*N-1 downto 0);
d2 : in STD_LOGIC_VECTOR(N-1 downto 0);
r : out STD_LOGIC_VECTOR(2*N-... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Title : Global Project Package
-- Project : ASP-SoC
-------------------------------------------------------------------------------
-- Description: Global definitons
---------------------------------------------------------------... |
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_unsigned.all;
use IEEE.Std_Logic_arith.all;
entity Cont_desc is
port ( CLK1, rst, en: in std_logic;
S: out std_logic_vector(9 downto 0)
);
end Cont_desc;
architecture Cont_desc_estr of Cont_desc is
signal cont: std_logic_vector(9 downto 0):="111110... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Cursor
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx IS... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Cursor
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx IS... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Cursor
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx IS... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Cursor
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx IS... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
--This is an autogenerated file
--Do not modify it by hand
--Generated at 2017-12-08T14:25:09+13:00
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package enforcement_types_AlphabetEnforcer is
type enforced_signals_AlphabetEnforcer is record
--put the enforced signals in here
A : std_logic;
... |
entity test is
constant a : b :=
foo.bar;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity audio_to_AXI_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI add... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity audio_to_AXI_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI add... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_7_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_7_e-... |
--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://gith... |
--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://gith... |
library verilog;
use verilog.vl_types.all;
entity PLL is
port(
inclk0 : in vl_logic;
c0 : out vl_logic;
c1 : out vl_logic;
locked : out vl_logic
);
end PLL;
|
entity bitstr1 is
end entity;
architecture test of bitstr1 is
begin
main: process is
begin
-- Examples from LRM
assert B"1111_1111_1111" = string'("111111111111");
assert X"FFF" = string'(b"1111_1111_1111");
assert O"777" = string'(b"111_111_111");
assert X"777" = strin... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Sat Sep 23 13:25:26 2017
-- Host : DarkCube running 64-bit major re... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_test1
-- Date:2015-01-27
-- Author: Gideon
-- Description: Testcase 2 for USB host
-- This testcase initializes a repeated IN transfer in Circular Mem Buffer mode
-----... |
library verilog;
use verilog.vl_types.all;
entity usb_system_cpu_nios2_oci_dtrace is
port(
clk : in vl_logic;
cpu_d_address : in vl_logic_vector(28 downto 0);
cpu_d_read : in vl_logic;
cpu_d_readdata : in vl_logic_vector(31 downto 0);
cpu_d... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected und... |
-- MDSynth Sound Chip
--
-- Copyright (c) 2012, Meldora Inc.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-- following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice, t... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
-- Keep Comment
G_GEN_1 => 3,
-- Keep Comment
G_GEN_2 => 4,
-- Keep Comment
G_GEN_3 => 5
-- Keep Comment
)
port map (
-- Keep Comment
PORT_1 => w_port_1,
-- Keep Comment
... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-... |
entity test is
generic (
a, b : integer;
c : natural);
begin
assert (a = b) and ((b /= c) or not (a = c))
report "a /= b" severity failure;
end entity;
architecture a of test is
begin
end architecture;
|
entity test is
generic (
a, b : integer;
c : natural);
begin
assert (a = b) and ((b /= c) or not (a = c))
report "a /= b" severity failure;
end entity;
architecture a of test is
begin
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 21:41:11 09/24/2009
-- Design Name:
-- Module Name: SequenceDetectorEx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: ... |
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
begin
proc_name (0, '1', x"00", sig1);
proc_name (0, '1', x"00", sig1);
end archit... |
--------------------------------------------------------------------------------------------------
-- Multirate FIR Filter
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
-------------------------------------------------... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library verilog;
use verilog.vl_types.all;
entity execute_sys_reg is
port(
iCMD : in vl_logic_vector(4 downto 0);
iSOURCE0 : in vl_logic_vector(31 downto 0);
iSOURCE1 : in vl_logic_vector(31 downto 0);
oOUT : out vl_logic_vector(31 d... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful... |
package pkg_6502_opcodes is
type t_opcode_array is array(0 to 255) of string(1 to 13);
constant opcode_array : t_opcode_array := (
"BRK ", "ORA ($nn,X) ", "HLT* ", "ASO*($nn,X) ",
"NOP*$nn ", "ORA $nn ", "ASL $nn ", "ASO*$nn ",
"PHP ", "ORA # ... |
--**********************************************************************
-- Copyright 2012 by XESS Corp <http://www.xess.com>.
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3... |
library verilog;
use verilog.vl_types.all;
entity finalproject_clocks_stdsync_sv6 is
port(
clk : in vl_logic;
din : in vl_logic;
dout : out vl_logic;
reset_n : in vl_logic
);
end finalproject_clocks_stdsync_sv6;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:19:41 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... |
entity bounds29 is
end entity;
architecture test of bounds29 is
subtype my_real is real range 0.0 to 10.0;
constant MATH_PI : REAL := 3.14159_26535_89793_23846;
subtype PRINCIPAL_VALUE is REAL range -MATH_PI to MATH_PI;
begin
main: process is
variable p1, p2 : principal_value;
... |
-------------------------------------------------------------------------------
--
-- The Program Status Word (PSW).
-- Implements the PSW with its special bits.
--
-- $Id: psw.vhd,v 1.8 2005-06-11 10:08:43 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redis... |
library verilog;
use verilog.vl_types.all;
entity Mux_4 is
port(
clk : in vl_logic;
res : in vl_logic;
en : in vl_logic;
big_alu_result : in vl_logic_vector(27 downto 0);
fra_result : in vl_logic_vector(27 downto ... |
-- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or info... |
library ieee;
use ieee.std_logic_1164.all;
entity ps2_interface is
port(clk : in std_logic;
rst : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
new_data_ack : in std_logic;
data : out std_logic_vector(7 downto 0);
new_data : out std_logic
);
end ps2_interface;
architecture... |
------------------------------------------------------------------------------
-- Title : Wishbone Position Calculation Core
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-07-02
-- Platform... |
entity hello is
end hello;
architecture behav of hello is
begin
assert false report "Hello world" severity note;with behav;
|
--
-- Test application for spwstream.
--
-- This entity implements one spwstream instance with SpaceWire signals
-- routed to external ports. The SpaceWire port is assumed to be looped back
-- to itself externally, either directly (tx pins wired to rx pins) or
-- through a remote SpaceWire device which is programm... |
--
-- Test application for spwstream.
--
-- This entity implements one spwstream instance with SpaceWire signals
-- routed to external ports. The SpaceWire port is assumed to be looped back
-- to itself externally, either directly (tx pins wired to rx pins) or
-- through a remote SpaceWire device which is programm... |
----------------------------------------------------------------------------------
-- --
-- ------------------- --
-- | | ... |
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the... |
library ieee;
use ieee.std_logic_1164.all;
entity repro is
port (clk : std_logic;
rst : std_logic;
o : out std_logic);
end repro;
architecture behav of repro is
signal v : natural range 0 to 3;
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
v <= 0;
... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
entity tb_dff02 is
end tb_dff02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff02 is
signal clk : std_logic;
signal rstn : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff02
port map (
q => dout,
d => din,
clk => clk,
... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:01:24 12/15/2014
-- Design Name:
-- Module Name: /media/media/Dropbox/Dropbox/befunge_processor/befunge_stack_tb.vhd
-- Project Name: befunge_processor
-- Target Device:
-- Tool ... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
-- Btrace 448
-- Ray Generator
--
-- Bradley Boccuzzi
-- 2016
-- !Remove from project
library ieee;
library ieee_proposed;
use ieee.std_logic_1164.all;
use ieee_proposed.fixed_pkg.all;
use ieee.std_logic_unsigned.all;
use work.btrace_pack.all;
entity raygenn is
generic(int, fraction: integer := 16);
port(clk, rst: ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- (Up to) 256 bytes of ROM
entity RomFD00 is
port (
A : in std_logic_vector(7 downto 0);
D : out std_logic_vector(7 downto 0)
);
end;
architecture Behavioural of RomFD00 is
begin
process(A)
begin
case A is
... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:31:57)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir1_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, ... |
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
L_RD_EN : linkage std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
WR_EN : in std_logic;
DATA : out std_logic_vector(31 downto 0);
RD_EN ... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
-- Date : Mon Nov 03 20:58:05 2014
-- Host : ECE-411-6 running 64-bit Service Pack... |
library ieee;
use ieee.std_logic_1164.all;
entity a is
port (
iClk : in std_ulogic);
end entity a;
|
library ieee;
use ieee.std_logic_1164.all;
entity a is
port (
iClk : in std_ulogic);
end entity a;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
lpm_compare1_inst : lpm_compare1 PORT MAP (
dataa => dataa_sig,
datab => datab_sig,
AleB => AleB_sig
);
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:17:04)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
EN... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ALU is
generic(
n: natural := 32
);
port(
a, b: in std_logic_vector(n-1 downto 0);
Oper: in std_logic_vector(3 downto 0);
Result: buffer std_logic_vector(n-1 downto 0);
Zero, CarryOut, Overflow: buffer std_logic
);
... |
-------------------------------------------------------------------------------
-- uartlite_rx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xi... |
-------------------------------------------------------------------------------
-- uartlite_rx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xi... |
-------------------------------------------------------------------------------
-- uartlite_rx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xi... |
-------------------------------------------------------------------------------
-- uartlite_rx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xi... |
-------------------------------------------------------------------------------
-- uartlite_rx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xi... |
-------------------------------------------------------------------------------
-- uartlite_rx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xi... |
architecture RTL of FIFO is
function func1 return integer is
begin
end;
pure function func1 return integer is
begin
end;
impure function func1 return integer is
begin
end;
function func1 (a : integer) return integer is
begin
end;
pure function func1 (a : integer) return integer is
begi... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
------------------------------------------------------------------------------/
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------/
-- ____ ____
-- / /\/ /
-- /___/ \ /... |
-- $Id: sys_w11a_c7.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_c7 - syn
-- Description: w11a tes... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.