content stringlengths 1 1.04M ⌀ |
|---|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
-- Copyright (C) Clifton Labs. All rights reserved.
-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. CLIFTON... |
-- Copyright (C) Clifton Labs. All rights reserved.
-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. CLIFTON... |
-- Copyright (C) Clifton Labs. All rights reserved.
-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. CLIFTON... |
-------------------------------------------------------------------------------
--! @file irqGenRtl.vhd
--
--! @brief irq generator with sync latch feature
--
--! @details The irq generator is similar to a ordinary interrupt controller,
--! however, it is extended with a "sync-latch" feature. This enables to
--! thrott... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.68... |
--------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : bootstrap.vhd
-- /___/ ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Fri May 9 13:48:22 2014
-- Host : macbook running 64-bit Arch Linux
-- ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : out std_logic;
B : out std_logic;
C : in std_logic;
clock : in std_logic;
enable2 : in std_logic;
enable : in std_logic);
end ... |
-- How do I subtract two std_logic_vectors signed
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity alu is
Port ( in1 : in std_logic_vector(15 downto 0);
in2 : in std_logic_vector(15 downto 0);
clk : in STD_LOGIC; -- Just in case, this design is async
r... |
entity array11 is
end entity;
architecture test of array11 is
type rec is record
x : integer_vector;
end record;
type rec_vec is array (natural range <>) of rec;
function sum_all (r : rec_vec) return integer is
variable result : integer := 0;
begin
for i in r'range loop
... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz<
--
-- Description: Generate clocking for sending TMDS data use the OSERDES2
--
-- REMEMBER TO CHECK CLKIN_PERIOD ON PLL_BASE
-- For pixel rates between 25Mhz and 50MHz use the following PLL... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz<
--
-- Description: Generate clocking for sending TMDS data use the OSERDES2
--
-- REMEMBER TO CHECK CLKIN_PERIOD ON PLL_BASE
-- For pixel rates between 25Mhz and 50MHz use the following PLL... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fsm IS
PORT(
clk, reset, run : IN STD_LOGIC;
IR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
R0, R1, R2, R3, R4, R5, R6, R7, Aset, Gset, IRset, done : OUT STD_LOGIC;
multSel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := "ZZZZ";
aluSel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := "... |
-----------------------------------------------------------------------------
-- MUX_branch
-- This MUX is feed with the following inputs:
-- - PCSrc: control signal coming from the MEM stage that eventually
-- tells whether a branch is taken or not.
-- - PC_4: is the current value of the program counter incre... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Fri Sep 22 23:00:38 2017
-- Host : DarkCube running 64-bit major re... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
entity tb_pragma01_syn is
end tb_pragma01_syn;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_pragma01_syn is
signal is_sim : std_logic;
begin
dut: entity work.pragma01
port map (is_sim);
process
begin
wait for 1 ns;
assert is_sim = '0' severity failure;
wait;
end proce... |
-- Inter-Prediction Interpolator Filter
-- see ITU Std. 8.4.2.2.1 and 8.4.2.2.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity inter_core is
generic(
x_len : integer := 4;
y_len : integer := 4;
sample_size : int... |
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF ... |
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF ... |
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF ... |
package axil_generic_pkg is
generic(
ADDR_WIDTH : natural
);
type mosi_t is record
valid : bit;
addr : bit_vector(ADDR_WIDTH-1 downto 0);
end record;
type miso_t is record
ready : bit;
end record;
|
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
Library UNIMACRO;
use UNIMACRO.vcomponents.all;
entity memory is
generic(address_width : natural := 16);
port(clk : in std_logic;
... |
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
Library UNIMACRO;
use UNIMACRO.vcomponents.all;
entity memory is
generic(address_width : natural := 16);
port(clk : in std_logic;
... |
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
Library UNIMACRO;
use UNIMACRO.vcomponents.all;
entity memory is
generic(address_width : natural := 16);
port(clk : in std_logic;
... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 15:16:45 11/14/2015
-- Design Name:
-- Module Name: InstDecoder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Depen... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library IEEE;
use IEEE.std_logic_1164.all;
package pkg2 is
component com1 is
--
end component com1;
component com3 is
--
end component com3;
end package pkg2;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:32:46 06/20/2014
-- Design Name:
-- Module Name: channel_sel - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04.03.2016 11:22:26
-- Design Name:
-- Module Name: rem_testbench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
architecture RTL of FIFO is
begin
process
begin
for_label : for index in 4 to 23 loop
end loop for_label;
FOR_LABEL : for index in 4 to 23 loop
end loop for_label;
For_label : for index in 4 to 23 loop
end loop for_label;
end process;
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 00:02:34 2017
-- Host : Juice-Laptop running 64-bit majo... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 00:02:34 2017
-- Host : Juice-Laptop running 64-bit majo... |
----------------------------------------------------------------------------------
--! Company: Weizmann Institute of Science
--! Engineer: juna
--!
--! Create Date: 18/12/2014
--! Module Name: pulse_pdxx_pwxx
----------------------------------------------------------------------------------
--! Use s... |
--------------------------------------------------------------------------------
-- Copyright (C) 2017 Kevin Bloom <kdb5pct.edu>
--
-- This program is free software: you can redistribute it and/or modify it under
-- the terms of the Lesser GNU General Public License as published by the Free
-- Software Foundation, eit... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux5x1 is
generic (N : integer := 16);
port (B : in std_logic_vector(N-1 downto 0);
C : in std_logic_vector(N-1 downto 0);
D: in std_logic_vector(N-1 downto 0);
E : in std_logic_vector(N-1 downto 0);
sel : in std_logic_vector(2 downto 0... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
----------------------------------------------------------------------------------
-- Company: TU Vienna
-- Engineer: Georg Blemenschitz
--
-- Create Date: 09:33:07 01/29/2010
-- Design Name: SPI
-- Module Name: tb_SPIControl
-- Description: VHDL Test Bench for module: SPIControl
--
-- Revision:
-- Revision 0.01... |
--*****************************************************************************
-- @Copyright 2010 by guyoubao, All rights reserved.
-- Module name : Pulse control
-- Call by :
-- Description :
-- IC : EP3C16F484C6
-- Version : A ... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Thu Aug 25 17:36:10 2016
-- Host : fpgaserv running 64-bit Ubuntu 14.04... |
--
-- Title TaggedSorter
--
-- Note: has 2 (1 * 2) queue capacities
-- basic block of tagged sorter
-- C-C Wang's style implementation
--
-- Author: Insop Song
-- Begin Date : 2007 04 23
-- Ver : 0.3b
-- Ver : 0.3c
--
-- Revision History
-- -------------------------------------------... |
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessordf_types.all;
entity packetprocessordf_topentity is
port(input_0_0 : in std_logic_vector(28 downto 0);
input_0_1 ... |
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessordf_types.all;
entity packetprocessordf_topentity is
port(input_0_0 : in std_logic_vector(28 downto 0);
input_0_1 ... |
library ieee;
use ieee.std_logic_1164.all;
entity repro3 is
end;
architecture behav of repro3 is
type t_axilite_write_address_channel is record
--DUT inputs
awaddr : std_logic_vector;
awvalid : std_logic;
end record;
type t_axilite_write_data_channel is record
--DUT inputs
wdata : std_lo... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity clock_conv is
port
(
IN_50MHz : in std_logic;
-- Output ports
OUT_0_1Hz : out std_logic;
OUT_1Hz : out std_logic;
OUT_10Hz : out std_logic
);
end clock_conv;
architecture clock_convimpl of clock_conv is
signal count_a: integer range ... |
------------------------------------------------------------------------------
-- dma_if.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
... |
-- library foo
package pack is
component comp is
port ( p : in bit );
end component;
end package;
-- library bar
library foo;
entity e is
end entity;
architecture a of e is
begin
u: component foo.pack.comp -- OK
port map ( '1' );
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity qualified_expr is
port (
X : in std_logic_vector(7 downto 0);
CIn : in std_logic;
Y : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of qualified_expr is
begin
-- anal... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity qualified_expr is
port (
X : in std_logic_vector(7 downto 0);
CIn : in std_logic;
Y : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of qualified_expr is
begin
-- anal... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package c1541_pkg is
constant c_drvreg_power : unsigned(3 downto 0) := X"0";
constant c_drvreg_reset : unsigned(3 downto 0) := X"1";
constant c_drvreg_address : unsigned(3 downto 0) := X"2";
constant c_drvreg_senso... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package c1541_pkg is
constant c_drvreg_power : unsigned(3 downto 0) := X"0";
constant c_drvreg_reset : unsigned(3 downto 0) := X"1";
constant c_drvreg_address : unsigned(3 downto 0) := X"2";
constant c_drvreg_senso... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package c1541_pkg is
constant c_drvreg_power : unsigned(3 downto 0) := X"0";
constant c_drvreg_reset : unsigned(3 downto 0) := X"1";
constant c_drvreg_address : unsigned(3 downto 0) := X"2";
constant c_drvreg_senso... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package c1541_pkg is
constant c_drvreg_power : unsigned(3 downto 0) := X"0";
constant c_drvreg_reset : unsigned(3 downto 0) := X"1";
constant c_drvreg_address : unsigned(3 downto 0) := X"2";
constant c_drvreg_senso... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-------------------------------------------------------
--! @author Andrew Powell
--! @date January 28, 2017
--! @brief Contains the entity and architecture of the
--! Interrupt Controller's Slave AXI4-Lite Write
--! Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_5bit is
Port (
SEL: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (4 downto 0);
B: in STD_LOGIC_VECTOR (4 downto 0);
OUTPUT: out STD_LOGIC_VECTOR (4 downto 0)
);
end mux_5bit;
architecture Behavioral of mux_5bit is
begin
OUTPUT <= A when (SEL = '0'... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--This should pass
context c1 is
end context c1;
context c1 is
end context;
--This should fail
context c1 is
end;
context c1 is
end
;
-- Split declaration across lines
context
c1
is
end
context
;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity WhackAMole is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
SWITCHES : in STD_LOGIC_VECTOR (7 downto 0);
DISP_EN : out STD_LOGIC_VECTOR (3 downto 0);
LEDS : out STD_LOGIC_VECTOR (7 downto 0);
... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:46:24 2017
-- Host : Juice-Laptop running 64-bit majo... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:46:24 2017
-- Host : Juice-Laptop running 64-bit majo... |
-- PS2 wrapper, peripheral for MARK-II
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: v.mlejnecky@seznam.cz
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ps2 is
generic(
... |
----------------------------------------------------------------------------------
-- Company: University of Cyprus, Department of Computer Science
-- Engineer: Dr. Petros Panayi
--
-- Create Date: 13:17:29 03/23/2007
-- Design Name:
-- Module Name: InstructionsROM - Behavioral
-- Project Name:
-- Target D... |
library ieee;
use ieee.std_logic_1164.ALL;
entity IR is
port (
x: in std_logic_vector(31 downto 0);
clk, IRWrite: in std_logic;
y: out std_logic_vector(31 downto 0)
);
end IR;
architecture Structural of IR is
signal temp: std_logic_vector(31 downto 0) := X"00000000";
begin
y <= temp;
process(clk... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s27_nov is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(0 downto 0)
);
end s27_nov;
architecture behaviour of s27_nov is
constant s000: std_logic_vector(2 downto 0) := "01... |
-------------------------------------------------------------------------------
-- Title : Multiply
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : Unit Multiply multiplies L and R channel with a factor
---------------------------... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use s... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--FSM de controle de estados do jogo
entity FSM_control is port(
CLK, RESET, END_BONUS, END_TIME, ENTER, TARGET: in std_logic;
SEL_DISP: out std_logic_vector(1 downto 0);
STATESS: out std_logic_vector(4 downto 0);
SEL_LED, SET_ROLL, EN_TIM... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ee_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
--... |
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity reg_mux is
--generic declarations
port (
a, b, c, d: in std_logic_vector(3 downto 0);
sel: in std_logic_vector(1 downto 0) ;
clk: in std_logic;
x, y: out std_logic_vector(3 downto 0));
end entity... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Jun 05 11:21:36 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--
-- Copyright (C) 2011, 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 11:54:14 10/26/2009
-- Design Name:
-- Module Name: OZ3 - Behavioral
-- Project Name: OZ-3
-- Target Devices: Xilinx XC3S500E-4FG320
-- Tool versions:
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 11:54:14 10/26/2009
-- Design Name:
-- Module Name: OZ3 - Behavioral
-- Project Name: OZ-3
-- Target Devices: Xilinx XC3S500E-4FG320
-- Tool versions:
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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