content stringlengths 1 1.04M ⌀ |
|---|
-------------------------------------------------------------------------------
-- axi_datamover_pcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc.... |
-------------------------------------------------------------------------------
-- axi_datamover_pcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc.... |
-------------------------------------------------------------------------------
-- axi_datamover_pcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc.... |
-------------------------------------------------------------------------------
-- axi_datamover_pcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc.... |
-------------------------------------------------------------------------------
-- axi_datamover_pcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc.... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_shadow_ok_3_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_in_tb is
end entity;
architecture structure of fifo_in_tb is
component fifo_in is
port (
CLOCK : in std_logic;
RESET : in std_logic;
DIN : in std_logic_vector(31 downto 0);
VIN : in std_logic;
RIN : out std_... |
-- test.vhd
entity test is
port (
clk : in bit;
rst : in bit;
val_o : out bit_vector(15 downto 0)
);
end entity test;
architecture rtl of test is
begin -- architecture rtl
end architecture rtl;
-- test_tb.vhd
entity test_tb is
end entity test_tb;
architecture tb of test_tb is
-- component po... |
-- test.vhd
entity test is
port (
clk : in bit;
rst : in bit;
val_o : out bit_vector(15 downto 0)
);
end entity test;
architecture rtl of test is
begin -- architecture rtl
end architecture rtl;
-- test_tb.vhd
entity test_tb is
end entity test_tb;
architecture tb of test_tb is
-- component po... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =========================================================================================================================================================... |
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Me... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity tb_repro_slv is
end tb_repro_slv;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_repro_slv is
signal clk : std_logic;
signal a : std_logic_vector(7 downto 0);
signal b : std_logic_vector(7 downto 0);
begin
dut: entity work.repro_slv
port map (
clk => clk, a => a, b => b);... |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate FOR_LABEL;
IF_LABEL : if a = '1' generate
end generate IF_LABEL;
CASE_LABEL : case data generate
end generate CASE_LABEL;
-- Violations below
FOR_LABEL :for i in 0 to 7 generate
end generate FOR_LABEL;
IF... |
entity ent is
end entity;
architecture a of ent is
procedure set(x : integer; value : integer := 0) is
begin
end procedure;
procedure set(x : integer; y : integer; value : integer := 0) is
begin
end procedure;
procedure set(x : integer; y : integer; z : integer; value : integer := 0) is
begin
end p... |
entity ent is
end entity;
architecture a of ent is
procedure set(x : integer; value : integer := 0) is
begin
end procedure;
procedure set(x : integer; y : integer; value : integer := 0) is
begin
end procedure;
procedure set(x : integer; y : integer; z : integer; value : integer := 0) is
begin
end p... |
entity ent is
end entity;
architecture a of ent is
procedure set(x : integer; value : integer := 0) is
begin
end procedure;
procedure set(x : integer; y : integer; value : integer := 0) is
begin
end procedure;
procedure set(x : integer; y : integer; z : integer; value : integer := 0) is
begin
end p... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:16:23 04/28/2017
-- Design Name:
-- Module Name: button_debounce - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
--... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.snes_lib.all;
entity tasty_snes is
port (
clk_i : in std_logic;
rst_i : in std_logic;
snes_js_btn_i : in snes_js_btn_r;
snes_js_bus_i : in snes_js_bus_i_r;
snes_js_bus_o : out s... |
architecture rtl of fifo is
begin
process begin
report "Something" &
"Something Else" &
"Yet another thing"
severity WARNING;
end process;
end architecture rtl;
|
-- $Id: pdp11_ounit.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either versi... |
-- $Id: pdp11_ounit.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either versi... |
package protected_type_pkg is
type protected_t is protected
procedure proc;
end protected;
end package;
package body protected_type_pkg is
type protected_t is protected body
procedure proc is
begin
end;
end protected body;
end package body;
-----------------------------------------------------... |
package protected_type_pkg is
type protected_t is protected
procedure proc;
end protected;
end package;
package body protected_type_pkg is
type protected_t is protected body
procedure proc is
begin
end;
end protected body;
end package body;
-----------------------------------------------------... |
package protected_type_pkg is
type protected_t is protected
procedure proc;
end protected;
end package;
package body protected_type_pkg is
type protected_t is protected body
procedure proc is
begin
end;
end protected body;
end package body;
-----------------------------------------------------... |
package protected_type_pkg is
type protected_t is protected
procedure proc;
end protected;
end package;
package body protected_type_pkg is
type protected_t is protected body
procedure proc is
begin
end;
end protected body;
end package body;
-----------------------------------------------------... |
package protected_type_pkg is
type protected_t is protected
procedure proc;
end protected;
end package;
package body protected_type_pkg is
type protected_t is protected body
procedure proc is
begin
end;
end protected body;
end package body;
-----------------------------------------------------... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:33:34 11/21/2012
-- Design Name:
-- Module Name: MemoriaDeInstrucciones - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
-- NEED RESULT: ARCH00423: Basic character set passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
... |
--------------------------------------------
-- Project: YARR
-- Author: Timon Heim (timon.heim@cern.ch)
-- Description: Top module for YARR on SPEC
-- Dependencies: -
--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
librar... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
architecture RTL of FIFO is
begin
IF_LABEL : if a = '1' generate
elsif a = '0' generate
end generate;
-- Violations below
IF_LABEL : if a = '1' generate
elsif a = '0' generate
end generate;
IF_LABEL : if a = '1' generate
elsif a = '0' generate
end generate;
end;
|
--Copyright 2014 by Emmanuel D. Bello <emabello42@gmail.com>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms o... |
-------------------------------------------------------------------------------
-- axi_uartlite - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] X... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
--This should pass
context con1 is
END context con1;
--These should fail
context con1 is
END context con1;
context co1 is
END context con1;
|
------------------------------------------------------------------------------
--
-- File: Ps2Interface.vhd
-- Author: Sergiu Arpadi
-- Original Project: AXI PS2
-- Date: 10 October 2017
--
-------------------------------------------------------------------------------
--Copyright (c) 2017 Digilent
--
--Permission is ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: tuk
--
-- Create Date: 18:57:52 11/21/2013
-- Design Name:
-- Module Name: CPU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
-... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
entity addr_deco is
generic (N: integer := 3);
port (
address: in natural range 0 to 2**N-1;
ena: in bit;
word_line: out bit_vector(2**N-1 downto 0));
end entity addr_deco;
-----------... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
entity assign8 is
end entity;
architecture test of assign8 is
function get_ints(count : natural) return integer_vector is
variable result : integer_vector(1 to count);
begin
for i in 1 to count loop
result(i) := i;
end loop;
return result;
end function;
pro... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library verilog;
use verilog.vl_types.all;
entity Add is
port(
a : in vl_logic_vector(7 downto 0);
b : in vl_logic_vector(7 downto 0);
\out\ : out vl_logic_vector(7 downto 0)
);
end Add;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY lift_tb IS
END lift_tb;
RCHITECTURE behavior OF lift_tb IS
-- Component Declaration for the Unit Under Test (UUT)
-- fix this component for your design
COMPONENT lift
PORT(
clk : IN std_logic;
sensors : IN ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006-2009 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006-2009 ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity my_video_filter_mul_mul_16ns_16ns_32_1_DSP48_0 is
port (
a: in std_logic_vector(16 - 1 downto 0);
b: in std_logic_vector(16 - 1 downto 0);
p: out std_logic_vector(32 - 1 downto 0));
end entity;
architecture behav of my_video_fil... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity my_video_filter_mul_mul_16ns_16ns_32_1_DSP48_0 is
port (
a: in std_logic_vector(16 - 1 downto 0);
b: in std_logic_vector(16 - 1 downto 0);
p: out std_logic_vector(32 - 1 downto 0));
end entity;
architecture behav of my_video_fil... |
------------------------------------------------------------------------------
-- Title : Wishbone Ethernet MAC Wrapper
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2012-11-12
-- Platform : FPGA-g... |
--!
--! Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:17:48 11/24/2015
-- Design Name:
-- Module Name: D:/ProySisDigAva/Levi/P34_RWM_Definition/RWM_TB.vhd
-- Project Name: P34_RWM_Definition
-- Target Device:
-- Tool versions:
-- Des... |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32) -- Comment
;
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
GENERIC(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32); -... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
library verilog;
use verilog.vl_types.all;
entity Monitor_sv_unit is
end Monitor_sv_unit;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library verilog;
use verilog.vl_types.all;
entity nfa_get_finals is
generic(
ap_const_logic_1: vl_logic := Hi1;
ap_const_logic_0: vl_logic := Hi0;
ap_ST_pp0_stg0_fsm_0: vl_logic_vector(0 to 1) := (Hi1, Hi0);
ap_ST_pp0_stg1_fsm_1: vl_logic_vector(0 to 1) := (Hi0, Hi0);
ap_ST_p... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 -... |
-------------------------------------------------------------------------------
-- Copyright 2014 Paulino Ruiz de Clavijo Vázquez <paulino@dte.us.es>
-- This file is part of the Digilentinc-peripherals project.
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in com... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 20:15:05 2017
-- Host : GILAMONSTER running 64-bit major rel... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbara_hot is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(1 downto 0)
);
end bbara_hot;
architecture behaviour of bbara_hot is
constant st0: std_logic_vector(9 downto 0) :... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
ENTITY test_spi_accell IS
END test_spi_accell;
ARCHITECTURE behavior OF test_spi_accell IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT spi_accel
PORT(
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
package config is
constant width : integer;
end package;
-------------------------------------------------------------------------------
use work.config.all;
package types is
type rec is record
x : bit_vector(1 to width); -- OK
end record;
end package;
---------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : ByteStuffer.vhd
--
-- Project : JPEG_ENC
--
-- Module : ByteStuffer
--
-- Content : ByteStuffer
--
-- Description : ByteStuffer core
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------... |
-------------------------------------------------------------------------------
-- File Name : ByteStuffer.vhd
--
-- Project : JPEG_ENC
--
-- Module : ByteStuffer
--
-- Content : ByteStuffer
--
-- Description : ByteStuffer core
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------... |
-------------------------------------------------------------------------------
-- File Name : ByteStuffer.vhd
--
-- Project : JPEG_ENC
--
-- Module : ByteStuffer
--
-- Content : ByteStuffer
--
-- Description : ByteStuffer core
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------... |
-------------------------------------------------------------------------------
-- File Name : ByteStuffer.vhd
--
-- Project : JPEG_ENC
--
-- Module : ByteStuffer
--
-- Content : ByteStuffer
--
-- Description : ByteStuffer core
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------... |
-------------------------------------------------------------------------------
-- File Name : ByteStuffer.vhd
--
-- Project : JPEG_ENC
--
-- Module : ByteStuffer
--
-- Content : ByteStuffer
--
-- Description : ByteStuffer core
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------... |
-- $Id: nexys2_fusp_cuff_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: nexys2_fusp_cuff_dummy - syn
-- Descr... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Create Date: 14:09:12 09/15/2013
-- Module Name: SDRAM_Controller - Behavioral
-- Description: Simple SDRAM controller for a Micron 48LC16M16A2-7E
-- o... |
------------------------------------------------------------------------------
-- Title : Top DSP design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-09-01
-- Platform : FPGA-generic
--------... |
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
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