content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity dm_cache is
port (
clock : in std_logic;
reset : in std_logic;
client_req : in t_mem_req;
client_resp : out t_mem_resp;
mem_req : out t_m... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity dm_cache is
port (
clock : in std_logic;
reset : in std_logic;
client_req : in t_mem_req;
client_resp : out t_mem_resp;
mem_req : out t_m... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity dm_cache is
port (
clock : in std_logic;
reset : in std_logic;
client_req : in t_mem_req;
client_resp : out t_mem_resp;
mem_req : out t_m... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity dm_cache is
port (
clock : in std_logic;
reset : in std_logic;
client_req : in t_mem_req;
client_resp : out t_mem_resp;
mem_req : out t_m... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity dm_cache is
port (
clock : in std_logic;
reset : in std_logic;
client_req : in t_mem_req;
client_resp : out t_mem_resp;
mem_req : out t_m... |
entity tb_ret01 is
end tb_ret01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ret01 is
signal d : std_logic_vector (7 downto 0);
signal r : integer;
begin
dut: entity work.ret01
port map (d, r);
process
begin
d <= x"01";
wait for 1 ns;
assert r = 1 severity failure;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_350 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_350;
architecture augh of add_350 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_350 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_350;
architecture augh of add_350 is
signal carry_inA : std_l... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004-2008 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyr... |
-------------------------------------------------------------------------------
-- Copyright 2014 Paulino Ruiz de Clavijo Vázquez <paulino@dte.us.es>
-- This file is part of the Digilentinc-peripherals project.
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in... |
-- **********************************
-- * Circuito de sincronización VGA *
-- **********************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_sinc is
port(
clk: in std_logic; -- Reloj de 50 MHz
rst: in std_logic;
px_tick, video_on : out std_logic;... |
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity left_shift is
generic (
SHIFT_BITS : positive := 1;
WORD_WIDTH : positive := 8;
NUM_WORDS : positive := 2);
port (
clk : in std_logic;
rst : in std_logic;
en ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- NEED RESULT: ARCH00247: Test of operator overloading passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
---------------------------------------------------------------------------... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/Complex3Multiply_block5.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -----------------------------------... |
--
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_605 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_605;
architecture augh of mul_605 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_605 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_605;
architecture augh of mul_605 is
signal tmp_res : signed(... |
-- $Id: tb_serport_autobaud.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_serport_autobaud - sim
-- Descript... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "ConfigRegister"
-- Project :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.std... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity GENERIC_WHEN is
generic( FOO : std_logic_vector(1 downto 0) );
port( IN1 : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(1 downto 0) );
end GENERIC_WHEN;
architectu... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity GENERIC_WHEN is
generic( FOO : std_logic_vector(1 downto 0) );
port( IN1 : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(1 downto 0) );
end GENERIC_WHEN;
architectu... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity GENERIC_WHEN is
generic( FOO : std_logic_vector(1 downto 0) );
port( IN1 : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(1 downto 0) );
end GENERIC_WHEN;
architectu... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.flat_memory_model.all;
use work.iec_bus_bfm_pkg.all;
entity harness_1541 is
end harness_1541;
architecture structural of harness_1541 is
signal sram_a : std... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.flat_memory_model.all;
use work.iec_bus_bfm_pkg.all;
entity harness_1541 is
end harness_1541;
architecture structural of harness_1541 is
signal sram_a : std... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.flat_memory_model.all;
use work.iec_bus_bfm_pkg.all;
entity harness_1541 is
end harness_1541;
architecture structural of harness_1541 is
signal sram_a : std... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.flat_memory_model.all;
use work.iec_bus_bfm_pkg.all;
entity harness_1541 is
end harness_1541;
architecture structural of harness_1541 is
signal sram_a : std... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.flat_memory_model.all;
use work.iec_bus_bfm_pkg.all;
entity harness_1541 is
end harness_1541;
architecture structural of harness_1541 is
signal sram_a : std... |
---------------------------------------------------------------------------------------------------
--
-- Title : Two End Point Example for Ring Bus
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
----------------------------------------------------------------------------... |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: adder1bit_comb.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the te... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
clk : std_logic;
req : std_logic;
val : std_logic;
ack : out std_logic);
end ent;
architecture behav of ent is
signal cnt : natural range 0 to 5;
begin
process (clk)
begin
if rising_edge(clk) then
if cnt < 5 then
cnt... |
---------------------------------------------------------------------------
--
-- Title: Hardware Thread Interface
-- Version 3: Subinterfaces for memory, function call, and control
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- The NEO430 Processor Project, by Stephan Nolting
-- Auto-generated memory init file (for BOOTLOADER)
library ieee;
use ieee.std_logic_1164.all;
package neo430_bootloader_image is
type bootloader_init_image_t is array (0 to 65535) of std_ulogic_vector(15 downto 0);
constant bootloader_init_image : bootloader_i... |
-------------------------------------------------------------------------------
-- Title : Generic Multiplier
-- Project :
-------------------------------------------------------------------------------
-- File : generic_multiplier.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created ... |
-- -------------------------------------------------------------
--
-- Generated Configuration for __COMMON__
--
-- Generated
-- by: wig
-- on: Wed Dec 14 12:20:57 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: w... |
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity onehot_tb is
end onehot_tb;
architecture TB_ARCHITECTURE of onehot_tb is
-- Component declaration of the tested unit
component onehot
port(
CLK : in STD_LOGIC;
... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_217 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_217;
architecture augh of sub_217 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_217 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_217;
architecture augh of sub_217 is
signal carry_inA : std_l... |
library verilog;
use verilog.vl_types.all;
entity reservation_alu2_entry is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREMOVE_VALID : in vl_logic;
iREGISTER_VALID : in vl_logic;
oINFO_REGIST_LOCK: out vl_logic;
iREGISTER_... |
library ieee_proposed;
use ieee_proposed.standard_additions.all;
package TestVectors is
--Generated in Julia with
-- freqs = [linspace(0,0.49,1024); linspace(0.49,0,1024)]
-- phases = cumsum(2pi*freqs)
-- chirp = sin(phases)
-- writecsv("chirp.dat", reshape(chirp, 16, 128)')
--Then add leading zeros to numbers
cons... |
-------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of TERASIC DE2i-150 development board PCIe-MN design part
--
--! @details This is the toplevel of the Nios MN FPGA Pcp design for the
--! Terasic DE2i-150 development Board.
--
-----------------... |
-- $Id: $
-- File name: tb_usbInterceptor.vhd
-- Created: 4/18/2012
-- Author: John Wyant
-- Lab Section: 337-02
-- Version: 1.0 Initial Test Bench
library ieee;
--library gold_lib; --UNCOMMENT if you're using a GOLD model
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use gold_lib.all; -... |
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Use Work.RC5_Pkg.all;
Entity rc5_rnd_key Is
Port
(
clr : in std_logic;
clk : in std_logic;
key_vld : in std_logic;
key_in : in Std_logic_vector (127 downto 0);
skey : out rom;
key_rdy : out std_logic
);
End rc5_rnd_key;
Archi... |
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Use Work.RC5_Pkg.all;
Entity rc5_rnd_key Is
Port
(
clr : in std_logic;
clk : in std_logic;
key_vld : in std_logic;
key_in : in Std_logic_vector (127 downto 0);
skey : out rom;
key_rdy : out std_logic
);
End rc5_rnd_key;
Archi... |
--*****************************************************************************
--* Copyright (c) 2012 by Michael Fischer. All rights reserved.
--*
--* Redistribution and use in source and binary forms, with or without
--* modification, are permitted provided that the following conditions
--* are met:
--*
--* ... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Sun Oct 4 22:06:59 2015
-- Host : cascade.andrew.cmu.edu running 64-bi... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: uint_to_ieee754_fp - Structural
-- Description: Converts an unsigned integer into IEEE-754 floating point notation
-----------------------------------------------... |
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: uint_to_ieee754_fp - Structural
-- Description: Converts an unsigned integer into IEEE-754 floating point notation
-----------------------------------------------... |
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: uint_to_ieee754_fp - Structural
-- Description: Converts an unsigned integer into IEEE-754 floating point notation
-----------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_420 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_420;
architecture augh of add_420 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_420 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_420;
architecture augh of add_420 is
signal carry_inA : std_l... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patric... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patric... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Bin7SegDecoder is
port(enable : in std_logic;
binInput : in std_logic_vector(3 downto 0);
decOut_n : out std_logic_vector(6 downto 0));
end Bin7SegDecoder;
architecture RTL of Bin7SegDecoder is
signal s_decOut_n : std_logic_vector(6 downto 0);
begin
with... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Bin7SegDecoder is
port(enable : in std_logic;
binInput : in std_logic_vector(3 downto 0);
decOut_n : out std_logic_vector(6 downto 0));
end Bin7SegDecoder;
architecture RTL of Bin7SegDecoder is
signal s_decOut_n : std_logic_vector(6 downto 0);
begin
with... |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: lpm_counter1.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- =============================... |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: lpm_counter1.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- =============================... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos (rodrigo4zevedo@gmail.com)
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity fa is
Port ( a : in std... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.textio.all;
entity instructionMemory is
Port (
address : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
outInstruction : out STD_LOGIC_VECTOR (31 downto 0));
end instructionMemory;
architectu... |
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
entity ovl_one_hot is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : pos... |
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY i8080tests IS
END i8080tests;
ARCHITECTURE behavior OF i8080tests IS
-- Component Declaration for the Unit Under Test... |
--************************************************************************************************
-- Component declarations for AVR core (Bus Masters)
-- Version 0.3
-- Designed by Ruslan Lepetenok
-- Modified 04.08.2005
--******************************************************************************************... |
--************************************************************************************************
-- Component declarations for AVR core (Bus Masters)
-- Version 0.3
-- Designed by Ruslan Lepetenok
-- Modified 04.08.2005
--******************************************************************************************... |
--************************************************************************************************
-- Component declarations for AVR core (Bus Masters)
-- Version 0.3
-- Designed by Ruslan Lepetenok
-- Modified 04.08.2005
--******************************************************************************************... |
--************************************************************************************************
-- Component declarations for AVR core (Bus Masters)
-- Version 0.3
-- Designed by Ruslan Lepetenok
-- Modified 04.08.2005
--******************************************************************************************... |
library verilog;
use verilog.vl_types.all;
entity Addsub_vlg_check_tst is
port(
result : in vl_logic_vector(15 downto 0);
sampler_rx : in vl_logic
);
end Addsub_vlg_check_tst;
|
entity protected4 is
end entity;
architecture test of protected4 is
type p is protected
procedure init(path : string);
end protected;
type p is protected body
type ft is file of integer;
file f : ft;
procedure init(path : string) is
begin
file_open(f, ... |
entity protected4 is
end entity;
architecture test of protected4 is
type p is protected
procedure init(path : string);
end protected;
type p is protected body
type ft is file of integer;
file f : ft;
procedure init(path : string) is
begin
file_open(f, ... |
-------------------------------------------------------------------------------
-- $Id: pf_adder_bit.vhd,v 1.1 2003/03/15 01:05:26 ostlerf Exp $
-------------------------------------------------------------------------------
-- pf_adder_bit.vhd - entity/architecture pair
------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_adder_bit.vhd,v 1.1 2003/03/15 01:05:26 ostlerf Exp $
-------------------------------------------------------------------------------
-- pf_adder_bit.vhd - entity/architecture pair
------------------------------------------------... |
-------------------------------------------------------------------------------
-- plb_bus_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_00_a;
use plb_v46_v1_00_a.all... |
-------------------------------------------------------------------------------
-- plb_bus_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_00_a;
use plb_v46_v1_00_a.all... |
architecture RTL of FIFO is
begin
-- Demonstrates Use Case #1: Replicating Logic
-- Stores just the most significant byte in a new signal
LABEL1: for i in 0 to 7 generate
end generate LABEL1;
-- Test nesting
LABEL2A: for i in 0 to 7 generate
LABEL2B: for i in 0 to 7 generate
LABEL2C: fo... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.