content stringlengths 1 1.04M ⌀ |
|---|
-- NEED RESULT: ARCH00376.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00376: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00376: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Wed Nov 01 12:03:22 2017
-- Host : vldmr-PC running 64-bit Service ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity A is
port(x: in std_ulogic_vector(4 downto 0));
end entity;
architecture test of A is
begin
end architecture;
entity B is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of B is
functi... |
----------------------------------------------------------------------------
---- Create Date: 00:12:45 10/23/2010
---- Design Name: pic
---- Project Name: PIC
---- Description:
---- A Programmable Interrupt Controller which can handle upto 8 ----
---- level triggered interrupts.The operating modes available are ... |
architecture RTL of FIFO is
begin
blk_block_label : block is begin end block blk_block_label;
block_label : block is begin end block block_label;
end architecture RTL;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
entity tb_exit02 is
end tb_exit02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_exit02 is
signal v : std_logic_vector(3 downto 0);
signal r : integer;
begin
dut: entity work.exit02
port map (val => v, res => r);
process
begin
v <= "0001";
wait for 1 ns;
assert r = 0 s... |
--!
--! @file: exercise7_9.vhd
--! @brief: frequency divider with variable
--! @author: Antonio Gutierrez
--! @date: 2013-10-29
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity freq_divider is
generic (M: ... |
-- file: clk_wiz_v3_6.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This discl... |
entity loop2 is
end;
architecture behav of loop2 is
begin
process
variable i : natural := 0;
begin
report "hello";
loop
exit when i = 10;
wait for 1 ns;
report "hello2";
i := i + 1;
end loop;
report "SUCCESS";
wait;
end process;
end behav;
|
entity loop2 is
end;
architecture behav of loop2 is
begin
process
variable i : natural := 0;
begin
report "hello";
loop
exit when i = 10;
wait for 1 ns;
report "hello2";
i := i + 1;
end loop;
report "SUCCESS";
wait;
end process;
end behav;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.math_real.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity SystemTest is
end SystemTest;
architecture Behavioral of SystemTest is
signal clk_main : std_logic := '0';
signal clk_cpu : std_... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- A parameterized, inferable, true dual-port, dual-clock block RAM in VHDL.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bram_tdp is
generic (
DATA : integer := 72;
ADDR : integer := 10
);
port (
-- Port A
a_clk : in std_logic;
a_wr : in std_lo... |
entity e is end entity;
library ieee;
architecture h of e is
constant L :positive := integer(ieee.math_real.ceil(9.9));
signal s :bit_vector(31 downto 0);
alias a :bit_vector(L-1 downto 2) is s(L-1 downto 2);
signal b :bit_vector(L-1 downto 2);
begin
a <= b;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:34:39 06/13/2016
-- Design Name:
-- Module Name: VDFF - Automat
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
--... |
--------------------------------------------------------------------------------
-- Title : FIFO for DMA
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_dma_fifo.vhd
-- Author : michael.miehling@men.de
-- Organization :... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:16:14)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_nsga2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
E... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:36:53 11/26/2015
-- Design Name:
-- Module Name: C:/Users/lwilkinson/Documents/Xilinx/IBM2030GIT/Testbench_panel_Switches.vhd
-- Project Name: IBM2030
-- Target Device:
-- Tool vers... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-------------------------------------------------------------------------------
-- axi_epc.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Engineer: Lefteris Kyriakakis
--
-- Create Date: 06/28/2017
-- Design Name: Serial-In-Parallel-Out Shift Register
-- Module Name: P2S Serializer - behave
-- Target Devices: Any
----------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.num... |
-- Engineer: Lefteris Kyriakakis
--
-- Create Date: 06/28/2017
-- Design Name: Serial-In-Parallel-Out Shift Register
-- Module Name: P2S Serializer - behave
-- Target Devices: Any
----------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.num... |
-- Engineer: Lefteris Kyriakakis
--
-- Create Date: 06/28/2017
-- Design Name: Serial-In-Parallel-Out Shift Register
-- Module Name: P2S Serializer - behave
-- Target Devices: Any
----------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.num... |
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... |
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... |
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_never is
constant assert_name : string := "OVL_NEVER";
constant path ... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
-- Date : Thu Jul 24 13:45:06 2014
-- Host : CE-2013-124 running 64-bit Service Pa... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity funcif is
end entity;
architecture test of funcif is
function foo(x : integer) return integer is
begin
if x > 5 then
return 1;
else
return 0;
end if;
end function;
begin
end architecture;
|
entity funcif is
end entity;
architecture test of funcif is
function foo(x : integer) return integer is
begin
if x > 5 then
return 1;
else
return 0;
end if;
end function;
begin
end architecture;
|
entity funcif is
end entity;
architecture test of funcif is
function foo(x : integer) return integer is
begin
if x > 5 then
return 1;
else
return 0;
end if;
end function;
begin
end architecture;
|
entity funcif is
end entity;
architecture test of funcif is
function foo(x : integer) return integer is
begin
if x > 5 then
return 1;
else
return 0;
end if;
end function;
begin
end architecture;
|
entity funcif is
end entity;
architecture test of funcif is
function foo(x : integer) return integer is
begin
if x > 5 then
return 1;
else
return 0;
end if;
end function;
begin
end architecture;
|
entity bounds13 is
end entity;
architecture test of bounds13 is
begin
process is
type myint is range 1 to 3;
begin
assert myint'value(" 3 ") = 3;
assert myint'value("4") = 1; -- Error
wait;
end process;
end architecture;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: clk_gen.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ===========================================... |
-------------------------------------------------------------------------------
-- $Id: opb_bram_if_cntlr.vhd,v 1.10 2003/06/27 14:20:34 anitas Exp $
-------------------------------------------------------------------------------
-- opb_bram_if_cntlr.vhd - entity/architecture pair
-------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:59:04 11/22/2015
-- Design Name:
-- Module Name: State_Reg_Ultrasonic - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confi... |
library ieee;
use ieee.std_logic_1164.all;
use work.util.all;
entity axi_stream_wrapper is
generic(k: key_enum);
port(ACLK: in std_logic; -- positive edge clock
ARESETN: in std_logic; -- active-low synchronous reset
S_AXIS_TREADY: out std_logic;
S_AXIS_TDATA: in std_logic_vector(31 d... |
-- File: pck_myhdl_081.vhd
-- Generated by MyHDL 0.8.1
-- Date: Sun Jun 14 22:11:56 2015
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_081 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std... |
-------------------------------------------------------------------------------------
-- FILE NAME : ads62p49_ctrl.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - ads62p49_ctrl
-- architecture - ads62p49_ctrl_syn
--
-- LANGUAGE :... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
use std.env.stop;
entity test2 is
generic (
SIM : boolean := false
);
port (
val : in std_ulogic
);
end entity test2;
architecture behaviour of test2 is
begin
process_0: process(all)
begin
if not SIM or val = '1' then
... |
------------------------------------------------------------------------------
-- INFORMATION: http://www.GNSS-sensor.com
-- PROPERTY: GNSS Sensor Ltd
-- E-MAIL: chief@gnss-sensor.com
-- DESCRIPTION: Clock domain transition modules description
------------------------------------------------------------... |
------------------------------------------------------------------------------
-- INFORMATION: http://www.GNSS-sensor.com
-- PROPERTY: GNSS Sensor Ltd
-- E-MAIL: chief@gnss-sensor.com
-- DESCRIPTION: Clock domain transition modules description
------------------------------------------------------------... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity e is end entity;
architecture a of e is
signal x : integer;
begin
bad syntax;
x <= 2; x <= 1 + 2; -- Recovery
some more bad syntax;
x <= 2; x <= 1 + 2; -- Recovery
process
begin
end; -- Missing "process"
x <... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
use Std.Textio.all;
library IEEE;
use ieee.std_logic_1164.ALL;
entity test_latch is end;
architecture test_latch of test_latch is
component c_Latch
generic (width : INTEGER := 4);
port (input : in std_logic_vector((width - 1) downto 0);
Enable:in std_logic; Clear :in std_logic; clock : in std_logic;
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
entity casioTone is
port (
-- Entradas
ps2Clk: in std_logic;
ps2Data: in std_logic;
clk: in std_logic;
rst: in std_logic;
-- Salidas
altavoz: out std_logic
);
end casioTone;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- NEED RESULT: ARCH00405.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00405.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00405.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH... |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ==================================... |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ==================================... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare4.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- =============================... |
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : x7seg_.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
--... |
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEE... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usub23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity usub23;
architecture rtl of usub23 is
begin
c_o <= a_i - b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usub23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity usub23;
architecture rtl of usub23 is
begin
c_o <= a_i - b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usub23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity usub23;
architecture rtl of usub23 is
begin
c_o <= a_i - b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usub23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity usub23;
architecture rtl of usub23 is
begin
c_o <= a_i - b_i;
end architecture rtl;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer ... |
entity registrador is port
( clk : in bit;
rst : in bit;
set : in bit;
d : in bit_vector(2 downto 0);
q : out bit_vector(2 downto 0));
end registrador;
architecture hardware of registrador is begin
process(clk)
begin
if(clk 'event and clk = '1') then
if(rst = '1') then q <= "000";
... |
entity test is
type t is range 0 to 10 units
foo;
bar = 2 foo;
baz = bar;
end units;
end;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity cpu_en... |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
signal a : std_logic;
begin
end;
end generate;
IF_LABEL : if a = '1' generate
signal a : std_logic;
begin
end;
end generate;
CASE_LABEL : case data generate
when a = b =>
signal a : std_logic;
b... |
library ieee;
use ieee.std_logic_1164.all;
entity moving_average_filter is
Port ( sin : in std_logic_vector (10 downto 0);
clk : in std_logic;
sout : out std_logic_vector (10 downto 0);
rst : in std_logic);
end moving_average_filter;
architecture behavioral of moving_average... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
use Ieee.std_logic_unsigned.all;
entity FaceAndRowToAddr is
Port (
Texture : in STD_LOGIC_VECTOR (3 downto 0);
Row : in STD_LOGIC_VECTOR (5 downto 0);
AddressOut : out STD_LOGIC_VECTOR (... |
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