content stringlengths 1 1.04M ⌀ |
|---|
--------------------------------------------------------------------------------
-- MMU_in_IRAM
-- Main role of this unit is to perform the address translation. It maps the
-- logic address generated(which is word-aligned) to the memory, which is not
-- word-aligned. Basically it shift right the input address by tw... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code mu... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_b_e
--
-- Generated
-- by: wig
-- on: Mon Mar 5 07:51:26 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../case.xls
--
-- !!! Do not edit this file! Autogenerated by ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity car_core is
port(
main_clk, reset, seq_reset, i2s_ws: in std_logic;
--
lvds_io: inout std_logic;
--
i2s_sclk: out std_logic;
i2s_dspk: in std_logic;
i2s_dmic: out std_logic;
--
spi_sck: in std_logic;
spi_mosi: in std_logic... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-... |
--!
--! @file: flipflop.vhd
--! @brief:
--! @author: Antonio Gutierrez
--! @date: 2013-11-26
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
--------------------------------------
entity flipflop is
--generic d... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 18:34:36 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 X... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 X... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 X... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 X... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 X... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNP7P5YZV2 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNP7P5YZV2 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNP7P5YZV2 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... |
--Practica5 de Diseño Automatico de Sistemas
--Piano Electronico.
--Fichero Principal.
--Desarrollada por Héctor Gutiérrez Palancarejo.
library ieee;
use ieee.std_logic_1164.all;
entity piano is
port(
clk : in std_logic;
rst : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
sound : o... |
library ieee;
use ieee.std_logic_1164.all;
-- 15-bit 4:2 counter
entity counter42 is
port ( a : in STD_LOGIC_VECTOR (14 downto 0);
b : in STD_LOGIC_VECTOR (14 downto 0);
c : in STD_LOGIC_VECTOR (14 downto 0);
d : in STD_LOGIC_VECTOR (14 downto 0);
s : out STD_LOGIC... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity bin2bcd_6bit is
Port ( binIN : in STD_LOGIC_VECTOR (5 downto 0);
ones : out STD_LOGIC_VECTOR (3 downto 0);
tens : out STD_LOGIC_VECTOR (3 downto 0)
);
end bin2bcd_6bit;
architecture Behavioral of bin2bc... |
------------------------------------------------------------------------------
-- radio_controller.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMIN... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:15:13 09/17/2014
-- Design Name:
-- Module Name: /home/gsanchez/Apps/TP_01/TB_C74F85_12B.vhd
-- Project Name: TP_01
-- Target Device:
-- Tool versions:
-- Description:
--
-- V... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- *******************************************************************
--
-- Owner: Xilinx Inc.
-- File: txmit.vhd
--
-- Purpose: UART transmit description. Interprets
-- processor read/write parallel bus cycles
-- and converts to output serial data.
--
-- Created: VHDL code generated by Visual HDL 8-15... |
-- *******************************************************************
--
-- Owner: Xilinx Inc.
-- File: txmit.vhd
--
-- Purpose: UART transmit description. Interprets
-- processor read/write parallel bus cycles
-- and converts to output serial data.
--
-- Created: VHDL code generated by Visual HDL 8-15... |
-- *******************************************************************
--
-- Owner: Xilinx Inc.
-- File: txmit.vhd
--
-- Purpose: UART transmit description. Interprets
-- processor read/write parallel bus cycles
-- and converts to output serial data.
--
-- Created: VHDL code generated by Visual HDL 8-15... |
-- *******************************************************************
--
-- Owner: Xilinx Inc.
-- File: txmit.vhd
--
-- Purpose: UART transmit description. Interprets
-- processor read/write parallel bus cycles
-- and converts to output serial data.
--
-- Created: VHDL code generated by Visual HDL 8-15... |
library verilog;
use verilog.vl_types.all;
entity mist1032sa_uart_transmitter_double_flipflop is
generic(
N : integer := 1
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREQ_DATA : in vl_logic_vector;
oOUT_DATA ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Justin Nguyen
--
-- Create Date: 11:24:03 09/18/2017
-- Design Name:
-- Module Name: Mux4x1
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This is a generic 4x1 10 bit mux with... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/11/2017 10:26:23 AM
-- Design Name:
-- Module Name: app_package - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
architecture RTL of FIFO is
begin
a <= b and c or d xor e nand f nor g xor h xnor i;
a <= (b) and (c) or (d) xor (e) nand (f) nor (g) xor (h) xnor (i);
-- Violations
a <= b and c or d xor e nand f nor g xor h xnor i;
a <= (b) and (c) or (d) xor (e) nand (f) nor (g) xor (h) xnor (i);
--... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; --for using std_logic
USE IEEE.STD_LOGIC_UNSIGNED.ALL; --for addition of std_logic
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY PING IS
PORT( CLK,CLR : IN STD_LOGIC;
SERVE1, SERVE2 : IN STD_LOGIC; --Players
... |
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Generic asynchronous FIFO wrapper
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: generic_async_fifo (generic_async... |
-------------------------------------------------------------------------------
-- axi_datamover_rddata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_rddata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_rddata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
--
-- Title :TaggedSorter32
--
-- Note : has 64 (32 * 2) queue capacities
-- Author: Insop Song
-- Begin Date : 2007 05 01
-- Ver : 0.1
--
-- Revision History
-- ---------------------------------------------------------------
-- Date Author Comments
-- 2007 05 01 Insop Song
... |
-- $RCSfile: mult_gen_v11_2_comp.vhd,v $ $Revision: 1.5 $ $Date: 2011/03/08 17:19:19 $
--------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package cart_slot_pkg is
constant c_cart_c64_mode : unsigned(3 downto 0) := X"0";
constant c_cart_c64_stop : unsigned(3 downto 0) := X"1";
constant c_cart_c64_stop_mode : unsigned(3 downto 0) := X"2";
cons... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -----------------------------------------------------------------
-- FIFO with a FrameLink interface
-- -----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.math_pack.all;
entity FRAME_FI... |
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <johannes@wltr.io>
--
-- Description:
-- Triplicate data on write and perform majority voting on read.
--------------------------------------------------------------------------------
libra... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--
-- File Name : RandomPkg.vhd
-- Design Unit Name : RandomPkg
-- Revision : STANDARD VERSION
--
-- Maintainer : Jim Lewis email : jim@synthworks.com
-- Contributor(s) :
-- Jim Lewis email: jim@synthworks.com
-- Lars Asplund email: lars.anders.asplund@gmail.com - Ra... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity saa5050_rom_dual_port is
generic (
ADDR_WIDTH : integer := 12;
DATA_WIDTH : integer := 8
);
port(
clock : in std_logic;
addressA : in std_logic_vector(ADDR_WIDTH-... |
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- /... |
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- /... |
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- /... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "InputSwitchingMatrix"
-- Project :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ie... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library std;
entity mt9_config_i2c is
port(
reset_n : in std_logic;
mt9_extclk : in std_logic;
mt9_sclk : in std_logic;
mt9_sclkdouble : in std_logic;
mt9_extclk_o : out std_logic;
... |
----------------------------------------------------------------------------------
-- Company: The University of York
-- Engineer: Christopher Crispin-Bailey
--
-- Create Date: 19:57:29 04/09/2014
-- Design Name:
-- Module Name: mem - Behavioral
-- Project Name: Bit Serial Processors
-- Target Devices:
-... |
----------------------------------------------------------------------------------
-- Company: The University of York
-- Engineer: Christopher Crispin-Bailey
--
-- Create Date: 19:57:29 04/09/2014
-- Design Name:
-- Module Name: mem - Behavioral
-- Project Name: Bit Serial Processors
-- Target Devices:
-... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xil... |
------------------------------------------------------------------------------
-- Title : Inverter of one Channel Pair
------------------------------------------------------------------------------
-- Author : José Alvim Berkenbrock
-- Company : CNPEM LNLS-DAC-DIG
-- Platform : FPGA-generic
--------------... |
entity tb_dff05 is
end tb_dff05;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff05 is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
signal en : std_logic;
begin
dut: entity work.dff05
por... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd : in std_logic_vector(0 to 63);
thrd2intrfc : out std_logic_vecto... |
-- file: obstacles/generate_random.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Random number module.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.numeric_std.all ;
entity g... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library verilog;
use verilog.vl_types.all;
entity NumberAnDisplay_vlg_sample_tst is
port(
V : in vl_logic_vector(3 downto 0);
sampler_tx : out vl_logic
);
end NumberAnDisplay_vlg_sample_tst;
|
-- UART Transmitter with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- Special version made 2nd November 2005 in which the data_present signal
-- was brough out as well as the half and full status signals.
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 14... |
-- UART Transmitter with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- Special version made 2nd November 2005 in which the data_present signal
-- was brough out as well as the half and full status signals.
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 14... |
-- UART Transmitter with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- Special version made 2nd November 2005 in which the data_present signal
-- was brough out as well as the half and full status signals.
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 14... |
-- UART Transmitter with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- Special version made 2nd November 2005 in which the data_present signal
-- was brough out as well as the half and full status signals.
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 14... |
-- UART Transmitter with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- Special version made 2nd November 2005 in which the data_present signal
-- was brough out as well as the half and full status signals.
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 14... |
-- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mariangela is
port (
din : in std_logic_vector(15 downto 0);
start, clk : in std_logic;
dout : out std_logic_vector(15 downto 0);
fine : out s... |
-- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mariangela is
port (
din : in std_logic_vector(15 downto 0);
start, clk : in std_logic;
dout : out std_logic_vector(15 downto 0);
fine : out s... |
----------------------------------------------------------------------------------
--
-- Copyright (C) 2014 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free ... |
architecture RTL of ENTITY_NAME is
function func1 return integer is
begin
hpp := '1' when (pf_vlan2x_tci(3 downto 0) >= x"A" and pf_vlan2x_tci(3 downto 0) <= x"F") else '0';
hpp := '1' when a >= b and x <= y else '0';
other_target <= '0' when x <= y;
end function;
begin
process
begin
SEL... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_AB_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this fil... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:01:43 11/21/2015
-- Design Name:
-- Module Name: Line_Detection - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Main module of line Detect... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:01:43 11/21/2015
-- Design Name:
-- Module Name: Line_Detection - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Main module of line Detect... |
library ieee;
use ieee.std_logic_1164.all;
entity test4 is
port (led: out std_logic_vector (7 downto 0);
rst : std_logic;
clk : std_logic);
end test4;
architecture synth of test4 is
signal int : std_logic_vector(1 downto 0);
begin
-- led(7) <= '0';
-- led(6) <= '1';
-- led(5) <= '0';
-- led(3 ... |
----------------------------------------------------------------------------------
-- ------------------- --
-- | | --
-- RST ---------| RST | ... |
library verilog;
use verilog.vl_types.all;
entity altera_merlin_slave_agent is
generic(
PKT_BEGIN_BURST : integer := 81;
PKT_DATA_H : integer := 31;
PKT_DATA_L : integer := 0;
PKT_SYMBOL_W : integer := 8;
PKT_BYTEEN_H : integer := 71;
PKT_BYTEEN_L :... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.txt_util.all;
use IEEE.numeric_std.ALL;
use IEEE.math_real.ALL;
entity spi_tb is
generic (
clock_period : time;
randVal : natural
);
port (
clk : in STD_LOGIC;
done : out boolean;
success : out boolean
);
end sp... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 17:33:00 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- file : test_lfsr4.vhdl
-- Copyright (C) 2010 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
--... |
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT <component name>
PORT(
<port1> : IN std_logic;
... |
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT <component name>
PORT(
<port1> : IN std_logic;
... |
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT <component name>
PORT(
<port1> : IN std_logic;
... |
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT <component name>
PORT(
<port1> : IN std_logic;
... |
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT <component name>
PORT(
<port1> : IN std_logic;
... |
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT <component name>
PORT(
<port1> : IN std_logic;
... |
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT <component name>
PORT(
<port1> : IN std_logic;
... |
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT <component name>
PORT(
<port1> : IN std_logic;
... |
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