content stringlengths 1 1.04M ⌀ |
|---|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNVJUPFOX3 is
generic ( ClockPhase : string := "1";
delay : positive := 1;
us... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNVJUPFOX3 is
generic ( ClockPhase : string := "1";
delay : positive := 1;
us... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
entity b is
end entity;
architecture a of b is
type my_int is range 0 to 100;
signal x : my_int := 2;
type resistance is range 0 to 10000000
units
ohm;
kohm = 1000 ohm;
Mohm = 1000 kohm;
end units;
signal r : resistance := 100 ohm;
subtype big_r... |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Entity : openMAC_Ethernet
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitte... |
-------------------------------------------------------------------------------
-- Entity : openMAC_Ethernet
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitte... |
-------------------------------------------------------------------------------
-- Entity : openMAC_Ethernet
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitte... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_10_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FtoI2 is
port (
clk : in std_logic;
f : in std_logic_vector(31 downto 0);
i : out std_logic_vector(31 downto 0));
end FtoI2;
architecture dataflow_pipeline of FtoI2 is
signal x_len_pre : std_logic_vector(8 dow... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:55:21 07/10/2015
-- Design Name:
-- Module Name: dff - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
... |
-------------------------------------------------------------------------------
--! @file phyMgmt-rtl-ea.vhd
--
--! @brief OpenMAC phy management module
--
--! @details This is the openMAC phy management module to configure the connected
--! phys via SMI (= serial management interface).
-----------------------... |
-- Component instantiation and port mapping.\n
<<instance_name>>: <<COMPONENT_NAME>> port map(<<port1>>=><<portX>>, <<port2>>=><<portY>>);
|
-- Component instantiation and port mapping.\n
<<instance_name>>: <<COMPONENT_NAME>> port map(<<port1>>=><<portX>>, <<port2>>=><<portY>>);
|
-- Component instantiation and port mapping.\n
<<instance_name>>: <<COMPONENT_NAME>> port map(<<port1>>=><<portX>>, <<port2>>=><<portY>>);
|
-- Component instantiation and port mapping.\n
<<instance_name>>: <<COMPONENT_NAME>> port map(<<port1>>=><<portX>>, <<port2>>=><<portY>>);
|
-- Component instantiation and port mapping.\n
<<instance_name>>: <<COMPONENT_NAME>> port map(<<port1>>=><<portX>>, <<port2>>=><<portY>>);
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Package: VHDL package for comp... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Package: VHDL package for comp... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity generic_register is
generic (
DATA_WIDTH : natural := 32
);
port (
clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(DATA_W... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity generic_register is
generic (
DATA_WIDTH : natural := 32
);
port (
clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(DATA_W... |
library ieee;
use ieee.std_logic_1164.all;
entity testcase3 is
generic (
edge : std_logic := '1'
);
port (
clk : in std_logic;
D : in std_logic;
Q : out std_logic
);
end testcase3;
architecture behavior of testcase3 is
begin
tc3: p... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Bitmap VGA display with 640x480 pixel resolution
-------------------------------------------------------------------------------
-- V 1.1.2 (2015/11/29)
-- Bertrand Le Gal (bertrand.legal@enseirb-matmeca.fr)
-- Some little modification... |
architecture RTL of FIFO is
begin
process
variable var1 : integer;
begin
end process;
process (a, b)
variable var1 : integer;
begin
end process;
process is
variable var1 : integer;
begin
end process;
-- Violations below
process
variable var1 : integer;
begin
end process... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
port(
clk : in std_logic;
rd_en : in std_logic;
rd_addr : in std_logic_vector(15 downto 0);
rd_data : out std_logic_vector(63 downto 0);
wr_en : in std_logic;
wr_sel : in std_logic_vector(7 downto 0);
wr_addr... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Keyboard is
port (Reset : in STD_LOGIC;
Clock : in STD_LOGIC;
PS2Clock : inout STD_LOGIC;
PS2Data : inout STD_LOGIC;
CodeReady : out STD_LOGIC;
ScanCode : out STD_LOGIC_VECT... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
use work.OV76X0Pack.all;
entity ConvFilter is
generic (
DataW : positive;
CompDataW : positive;
Res : positive
);
port (
Clk : in bit1;
RstN ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_LV is
generic (
DATA_WIDTH: integer := 11
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_lo... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ae
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!... |
package pkg is
procedure iterate (
input : in bit_vector);
end pkg;
package body pkg is
procedure iterate (
input : in bit_vector) is
variable j : integer := input'range'left;
begin -- iterate
for i in input'range loop
assert i = j report "TEST FAILED" severity failure;
j := j + 1;
... |
package pkg is
procedure iterate (
input : in bit_vector);
end pkg;
package body pkg is
procedure iterate (
input : in bit_vector) is
variable j : integer := input'range'left;
begin -- iterate
for i in input'range loop
assert i = j report "TEST FAILED" severity failure;
j := j + 1;
... |
package pkg is
procedure iterate (
input : in bit_vector);
end pkg;
package body pkg is
procedure iterate (
input : in bit_vector) is
variable j : integer := input'range'left;
begin -- iterate
for i in input'range loop
assert i = j report "TEST FAILED" severity failure;
j := j + 1;
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-----
-----
-- CHAR ROM COMO LO TENÍA EN EL TP2, USAR LO Q SIRVA
-----
-----
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity Char_ROM is
generic(
N: integer:= 6;
M: integer:= 3;
W: integer:= 8
);
port(
char_address: in std_logic_vector(5 downto 0);
font_row, font_col: in std_... |
library ieee;
use ieee.std_logic_1164.all;
entity issue is
port (foo : in std_logic_vector (3 downto 0);
bar : out std_logic_vector (7 downto 0));
end issue;
architecture beh of issue is
begin
bar <= ('0' & foo, others=>'0');
end architecture beh;
|
-- #################################################################################################
-- # << NEO430 - Address Generator Unit >> #
-- # ********************************************************************************************* #
-- # Address comp... |
-- >> Simulation model <<
-- On-chip memory with Wishbone interface.
--
-- 32-bit wide data port. Accesses are allowed only to bytes,
-- half-words (at half-word boundaries) and full words.
-- Word-addressing is used (address 3 is bytes 12-15, etc.)
--
-- Initializes itself from a .hex file.
--
-- Luz micro-c... |
-- >> Simulation model <<
-- On-chip memory with Wishbone interface.
--
-- 32-bit wide data port. Accesses are allowed only to bytes,
-- half-words (at half-word boundaries) and full words.
-- Word-addressing is used (address 3 is bytes 12-15, etc.)
--
-- Initializes itself from a .hex file.
--
-- Luz micro-c... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
-- NEED RESULT: ARCH00634.P1: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00634.P2: Multi transport transactions occurred on signal asg with aggregate of simple names on LHS passed
-- NEED RESULT: ARCH00634.P3: Multi transport transactions occur... |
architecture RTL of ENT is
begin
end architecture RTL;
architecture RTL of ENT is
begin
end RTL;
architecture RTL of ENT is
begin
end architecture RTL;
architecture RTL of ENT is
begin
end
architecture RTL;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_b
--
-- Generated
-- by: wig
-- on: Fri Jun 9 05:15:53 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../highlow.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wi... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.zpu_top_pkg.all;
use work.wishbone_pkg.all;
use work.zpupkg.all;
use work.zpu_config.all;
------------------------------------------------------------------------
-- Top level ZPU + wishbone componenent to use in a veri... |
-- GRCAN 2.0 interface
constant CFG_GRCAN : integer := CONFIG_GRCAN_ENABLE;
constant CFG_GRCAN_NUM : integer := CONFIG_GRCAN_NUM;
constant CFG_GRCANIO : integer := 16#CONFIG_GRCANIO#;
constant CFG_GRCANIRQ : integer := CONFIG_GRCANIRQ;
|
-- GRCAN 2.0 interface
constant CFG_GRCAN : integer := CONFIG_GRCAN_ENABLE;
constant CFG_GRCAN_NUM : integer := CONFIG_GRCAN_NUM;
constant CFG_GRCANIO : integer := 16#CONFIG_GRCANIO#;
constant CFG_GRCANIRQ : integer := CONFIG_GRCANIRQ;
|
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/29 11:38:22 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: phase_align_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.2 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulst... |
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/29 11:38:22 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: phase_align_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.2 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulst... |
------------------------------------------------------------------------------
-- superip.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE C... |
library ieee;
use ieee.std_logic_1164.all;
entity issue is
generic (type t_type);
end issue;
architecture beh of issue is
begin
end architecture beh;
|
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as publis... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2014 Brian K. Nemetz
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/15/2015 03:17:32 PM
-- Design Name:
-- Module Name: rotateWord - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
-- CTRL_BIT_REGISTER
-- Einlesen der einzelnen Werte für bestimmte Bits, Berechung der Parität und Ausgabe als Byte
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 08.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 24.04.2013 (Erweiterungen für Testumgebung)
-- Umstellung auf: rising_edge(CLK)... |
-- CTRL_BIT_REGISTER
-- Einlesen der einzelnen Werte für bestimmte Bits, Berechung der Parität und Ausgabe als Byte
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 08.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 24.04.2013 (Erweiterungen für Testumgebung)
-- Umstellung auf: rising_edge(CLK)... |
-- $Id: tb_s3board_fusp.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either v... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
package elab16_pack is
type int8 is array (7 downto 0) of integer;
type int8_vector is array (integer range <>) of int8;
end package;
-------------------------------------------------------------------------------
use work.elab16_pack.all;
entity sub is
generic (
val : integer );
port (
... |
package elab16_pack is
type int8 is array (7 downto 0) of integer;
type int8_vector is array (integer range <>) of int8;
end package;
-------------------------------------------------------------------------------
use work.elab16_pack.all;
entity sub is
generic (
val : integer );
port (
... |
package elab16_pack is
type int8 is array (7 downto 0) of integer;
type int8_vector is array (integer range <>) of int8;
end package;
-------------------------------------------------------------------------------
use work.elab16_pack.all;
entity sub is
generic (
val : integer );
port (
... |
package elab16_pack is
type int8 is array (7 downto 0) of integer;
type int8_vector is array (integer range <>) of int8;
end package;
-------------------------------------------------------------------------------
use work.elab16_pack.all;
entity sub is
generic (
val : integer );
port (
... |
package elab16_pack is
type int8 is array (7 downto 0) of integer;
type int8_vector is array (integer range <>) of int8;
end package;
-------------------------------------------------------------------------------
use work.elab16_pack.all;
entity sub is
generic (
val : integer );
port (
... |
library IEEE;
use ieee.std_logic_1164.all;
entity two_to_one_mux_1_bit is
port(
a, b : in std_logic;
sel : in std_logic;
output : out std_logic
);
end entity two_to_one_mux_1_bit;
architecture behav of two_to_one_mux_1_bit is
begin
--output <= (a and (not sel)) or (b and sel);
output <= a when (sel = '0... |
-- --------------------------------------------------------------------
--
-- Title : std_logic_textio
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Adapted by IEEE P1164 Working Group from
-- : ... |
--
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your... |
-- 3-D Ram Inference Example ( Simple Dual port)
-- Compile this file in VHDL2008 mode
-- File:rams_sdp_3d.vhd
library ieee;
use ieee.std_logic_1164.all;
package mypack is
type myarray_t is array(integer range<>) of std_logic_vector;
type mem_t is array(integer range<>) of myarray_t;
end package;
library ieee;
u... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:04:38 02/13/2016
-- Design Name:
-- Module Name: nibble2sevenseg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependen... |
----------------------------------------------------------------------------------
-- Company: MIT
-- Engineer: Andreas Schuh
-- Top level design
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_198 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_198;
architecture augh of mul_198 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_198 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_198;
architecture augh of mul_198 is
signal tmp_res : signed(... |
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity AlrTest is
Port (KEY, SW: IN std_logic_vector ( 17 downto 0);
CLOCK_50: IN std_logic;
LEDG: OUT std_logic_vector (3 downto 0);
LEDR: OUT std_logic_vector (17 downto 0);
HEX0, HEX1, HEX2: OUT std_logic_vector(6 downto 0));
end AlrT... |
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.1 (lin64) Build 1215546 Mon Apr 27 19:07:21 MDT 2015
--Date : Thu May 12 11:41:56 2016
--Host : fx6 running 64-bit openSUSE Leap 42.1 (x8... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--
-- File Increment: TbNames.vhd
-- Design Unit Increment: TbNames
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Purpose
-- Test Names
--
-- Developed for:
-- ... |
--
-- File Increment: TbNames.vhd
-- Design Unit Increment: TbNames
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Purpose
-- Test Names
--
-- Developed for:
-- ... |
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