content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity kirkman_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(11 downto 0);
output: out std_logic_vector(5 downto 0)
);
end kirkman_rnd;
architecture behaviour of kirkman_rnd is
constant rst0: std_logic_vector(3 dow... |
-- file: pll_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity spi_comm is
port(
CLK : in std_logic;
RESET : in std_logic;
SPI_CS_A : in std_logic;
SPI_CS_D : in std_logic;
SPI_SCK : in std_logic;
SPI_DI : in std_logic;
SPI_DO : out std_logic;
ADDR_O :... |
-- $Id: tb_tst_rlink_arty.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_rlink_arty
-- Description: Config... |
-------------------------------------------------------------------------------
-- $Id: pf_counter_bit.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_bit.vhd - entity/architecture pair
------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_193 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_193;
architecture augh of mul_193 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_193 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_193;
architecture augh of mul_193 is
signal tmp_res : signed(... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:18:55 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major... |
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Softw... |
package pack is
type pt is protected
procedure not_called;
end protected;
function add2(x : integer) return integer;
end package;
package body pack is
type pt is protected body
procedure not_called is
begin
end procedure;
end protected body;
shared variable ... |
entity tb_thingy is
end tb_thingy;
architecture tb of tb_thingy is
component thingy is
generic (
a_a : integer
);
port (
x%x : in bit; -- <==
y_y : out bit
);
end component;
signal stimuli : bit;
signal response : bit;
begin
dut : thingy
generic map (
a_a => 42
)
port map (
x_x => stimuli... |
entity tb_thingy is
end tb_thingy;
architecture tb of tb_thingy is
component thingy is
generic (
a_a : integer
);
port (
x%x : in bit; -- <==
y_y : out bit
);
end component;
signal stimuli : bit;
signal response : bit;
begin
dut : thingy
generic map (
a_a => 42
)
port map (
x_x => stimuli... |
-- $Id$
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This p... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_303 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_303;
architecture augh of sub_303 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_303 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_303;
architecture augh of sub_303 is
signal carry_inA : std_l... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_6_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 08:31:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Auth... |
-----------------------------------------------------------------------------
-- LEON Demonstration design
-- Copyright (C) 2004 - 2015 Cobham Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gais... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.68... |
----------------------------------------------------------------------------------
-- Company: TU Vienna
-- Engineer: Georg Blemenschitz
--
-- Create Date: 17:41:00 12/02/2009
-- Design Name: FIFO
-- Module Name: FIFOBinaryCounter - rtl
-- Description: Binary counter for FIFO
--
-- Revision:
-- Revision 0.01... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
u_inst1 : INST1
port map (
PORT_1 => w_port... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:07:27 11/13/2013
-- Design Name:
-- Module Name: Y:/cg3207-proj/decoder_test.vhd
-- Project Name: Lab3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VH... |
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | _... |
constant"
|
constant"
|
constant"
|
constant"
|
constant"
|
constant"
|
constant"
|
constant"
|
constant"
|
constant"
|
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_SYNC12 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic_vector(11 downto 0);
Q : out vl_logic_vector(11 downto 0)
);
end F2DSS_ACE_MIS... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_SYNC12 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic_vector(11 downto 0);
Q : out vl_logic_vector(11 downto 0)
);
end F2DSS_ACE_MIS... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_SYNC12 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic_vector(11 downto 0);
Q : out vl_logic_vector(11 downto 0)
);
end F2DSS_ACE_MIS... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and ... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pr_axis is
generic (
DATAWIDTH : integer := 64
);
port (
s_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
s_axis_data_tkeep : in std_logic_vector(DA... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity audio_dac_8bit is
Port ( clk : in STD_LOGIC;
data : in signed (8 downto 0);
pulseStream : out STD_LOGIC);
end audio_dac_8bit;
architecture Behavioral of audio_dac_8bit is
signal sum : unsigned (9 downto 0) := to_... |
-----------------------------------------------------------------------------
-- LEON Demonstration design test bench
-- Copyright (C) 2004 - 2015 Cobham Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 200... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY opULA IS
PORT (
ULAop :in std_logic_vector(1 downto 0);
funct :in std_logic_vector(5 downto 0);
oper :out std_logic_vector(3 downto 0)
);
END opULA;
ARCHITECTURE rtl OF opULA IS
BEG... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains... |
------------------------------------------------------------------------
-- mouse_controller.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zolt�n
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Softwa... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity deadtime_gen is
generic
(
-- Number of bits in the counter
DT_N : positive;
-- Amount of deadtime
DT_VAL : natural
);
port
(
clk : in std_l... |
-- *********************************************************************
-- Copyright 2008, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_a_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig... |
--
-- Definition of a single port ROM for KCPSM3 program defined by programm.psm
--
-- Generated by KCPSM3 Assembler 07Jun2016-12:01:25.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define ... |
-------------------------------------------------------------------------------
--! @file phyMgmt-rtl-ea.vhd
--
--! @brief OpenMAC phy management module
--
--! @details This is the openMAC phy management module to configure the connected
--! phys via SMI (= serial management interface).
-----------------------... |
-- Some comment
entity FIFO is
end entity;
library ieee;
entity FIFO is
end entity;
library ieee;
-- First Comment
-- Second Comment
-- Third Comment
entity fifo is end entity;
library ieee;
-- First Comment
-- Second Comment
-- Third Comment
entity fifo is end entity;
entity fifo is end entity;
|
---------------------------------------------------------------------------
-- Company : Automaticaly generated by POD
-- Author(s) :
--
-- Creation Date : 2009-06-08
-- File : Top_testoutput_tb.vhd
--
-- Abstract :
-- insert a description here
--
------------------------------------------------------... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 02:34:38 2019
-- Host : varun-laptop running 64-bit Serv... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sseg_mux is
port(
clk, reset: in std_logic;
in0, in1, in2, in3: in std_logic_vector(7 downto 0);
en: out std_logic_vector(3 downto 0);
sseg: out std_logic_vector(7 downto 0)
);
end sseg_mux;
arch... |
----------------------------------------------------------------------------------
-- Module Name: transceiver_test - Behavioral
--
-- Description: A partial implementation allowing simulation of the main stream
-- components without the compications of the AUX channel. Not made
-- to be... |
architecture rtl of fifo is
begin
process begin
report "hello" severity FAILURE;
report "hello"
severity FAILURE;
end process;
end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Albert Fazakas
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--source code automatically generated.
--Aaron Mills
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity puf_sram is
port(
rst: in std_logic;
clk: in std_logic;
en: in std_logic;
Q1: out std_logic;
Q2: out std_logic
);
end puf_sram;
architecture Behavioral of puf_sra... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.float_pkg.all;
use work.tbu_text_out_pkg.all;
package tbu_assert_pkg is
constant REAL_DELTA_MAX: real := 0.001;
constant FLOAT_DELTA_MAX: real := 0.001;
procedure assert_that(msg: string; expr: boolean);
proce... |
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/16/2016 06:00:47 AM
-- Design Name:
-- Module Name: spi_tb1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
... |
----------------------------------------------------------------------
-- brdLexSwx (A3PE/A3P PQ208 Eval Board)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- board/kit dependency : LEDs & SW polarity
--
----------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_341 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_341;
architecture augh of mul_341 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_341 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_341;
architecture augh of mul_341 is
signal tmp_res : signed(... |
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- testbench - behavior
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
-----------------------------------------------------------------... |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
use work.component_pack.all;
entity router_SW_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
gene... |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
use work.component_pack.all;
entity router_SW_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
gene... |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
use work.component_pack.all;
entity router_SW_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
gene... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
--! @file syncTog-rtl-ea.vhd
--
--! @brief Synchronizer with toggling signal
--
--! @details This is a synchronizer that transfers an incoming signal to the
--! target clock domain with toggling signal levels.
---------------------... |
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