content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
entity counter_div_trig is
generic
( OFFSET : integer
; BIT_WIDTH : integer
);
port
( clk : in std_logic
; tr : in std_logic
; counter_out : out std_logic_vector((BIT_WIDTH - 1... |
package my_package is
type slv_1_t is array (natural range <>) of bit_vector;
function addslvreg_f(arg0 : slv_1_t; arg1 : bit_vector) return slv_1_t;
end package my_package;
package body my_package is
function addslvreg_f(arg0 : slv_1_t; arg1 : bit_vector) return slv_1_t is
variable cb_v : bit_vect... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Fri Sep 22 16:52:26 2017
-- Host : vldmr-PC running 64-bit Service ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Fri Sep 22 16:52:26 2017
-- Host : vldmr-PC running 64-bit Service ... |
entity tb_dff09 is
end tb_dff09;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff09 is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic_vector (3 downto 0);
signal dout : std_logic_vector (3 downto 0);
begin
dut: entity work.dff09
port map (
q => dout,
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: Whypcore.vhd
-- // Date: 12/9/2004
-- // Description: WHYP Core
-- // Class: CSE 378
-- ===================================================... |
--------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <ccl@xunit.de>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redis... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity Regs_Grou... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:18:54 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fsm IS
PORT(
run : IN std_logic;
reset : IN std_logic;
clk : IN std_logic;
IR : IN std_logic_vector(9 DOWNTO 0);
done : OUT std_logic;
multSel : OUT std_logic_vector(3 DOWNTO 0);
R0 : OUT std_logic;
R1 : OUT std_logic;
R2 : OUT std_logic;
... |
-------------------------------------------------------------------------------
--
-- The testbench for t8048.
--
-- $Id: tb_t8048-c.vhd,v 1.3 2006-06-22 00:21:28 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
----------------------------------------------------... |
-- NEED RESULT: ARCH00696: Expressions, signal and variable names allowed as actual designator in association list passed
-- NEED RESULT: ARCH00696_1: Actual designator may be 'open' passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics,... |
-------------------------------------------------------------------------------
-- Title : Testbench for design HDLC Enc/Dec
-------------------------------------------------------------------------------
-- Author : Carl Treudler (cjt@users.sourceforge.net)
-- Standard : VHDL'93/02
-------------------------... |
-------------------------------------------------------------------------------
-- Title : Testbench for design HDLC Enc/Dec
-------------------------------------------------------------------------------
-- Author : Carl Treudler (cjt@users.sourceforge.net)
-- Standard : VHDL'93/02
-------------------------... |
---------------------------------------------------------------------------
-- This VHDL file was developed by Altera Corporation. It may be
-- freely copied and/or distributed at no cost. Any persons using this
-- file for any purpose do so at their own risk, and are responsible for
-- the results of such use. Alte... |
library ieee;
use ieee.std_logic_1164.all;
entity testcase is
generic (
init_bit : std_logic := '1'
);
end testcase;
architecture rtl of testcase is
-- assigning generic to std_logic works OK
signal test_assign : std_logic := init_bit;
-- assigning generic to part of std_logic_vector brea... |
entity dut is
port(
a : in string(1 to 1)
);
end entity dut;
architecture a of dut is
component dut_internal
port(
a : in string;
b : in string
);
end component dut_internal;
signal b : string(1 to 1);
begin
inst : dut_internal
port map (
a => a
-- b => b
);
end architecture a;
|
--
-- UART interrupt control
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- History: 1.0 - Initial version
-- 1.1 - Automatic flow control
--
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- Licens... |
--
-- UART interrupt control
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- History: 1.0 - Initial version
-- 1.1 - Automatic flow control
--
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- Licens... |
--
-- UART interrupt control
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- History: 1.0 - Initial version
-- 1.1 - Automatic flow control
--
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- Licens... |
--
-- UART interrupt control
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- History: 1.0 - Initial version
-- 1.1 - Automatic flow control
--
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- Licens... |
--
-- UART interrupt control
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- History: 1.0 - Initial version
-- 1.1 - Automatic flow control
--
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- Licens... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY MultBcd_5x5Dig IS
PORT (
EntradaA : IN unsigned (19 DOWNTO 0); -- Entrada1 com 5 digitos BCD
EntradaB : IN unsigned (19 DOWNTO 0); -- Entrada2 com 5 digitos BCD
SaidaZ : OUT unsigned (39 DOWNTO 0) -- Saída com 10 digitos BCD
);
END... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY MultBcd_5x5Dig IS
PORT (
EntradaA : IN unsigned (19 DOWNTO 0); -- Entrada1 com 5 digitos BCD
EntradaB : IN unsigned (19 DOWNTO 0); -- Entrada2 com 5 digitos BCD
SaidaZ : OUT unsigned (39 DOWNTO 0) -- Saída com 10 digitos BCD
);
END... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
--... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03/05/2015 03:03:28 PM
-- Design Name:
-- Module Name: sd_spi_pkg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
----------------------------------------
-- Memory Module : IITB-RISC
-- Author : Titto Thomas
-- Date : 18/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Memory is
port (
clock : in std_logic; -- clock
write :... |
package fifo_pkg is
end package fifo_pkg;
package fifo is
end package fifo;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
entity GENERIC_STANDARD_TYPES is
generic ( lowb : integer := ... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity repro1 is
end entity;
architecture a of repro1 is
begin
process
type LongInteger is range -2**47 to 2**47-1;
variable v : LongInteger;
variable s : string (1 to 4);
begin
v := 12345678901;
report "v = " & LongInteger'image(v) severity note;
s := "1245";
assert LongInteger'Value (... |
entity repro1 is
end entity;
architecture a of repro1 is
begin
process
type LongInteger is range -2**47 to 2**47-1;
variable v : LongInteger;
variable s : string (1 to 4);
begin
v := 12345678901;
report "v = " & LongInteger'image(v) severity note;
s := "1245";
assert LongInteger'Value (... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity struct_out is
generic (
N_INST : boolean := true;
S_INST : boolean := true;
E_INST : boolean := true;
W_INST : boolean := true
);
port (
CLOCK : in std_logic;
RESET : in std_logic;
-- local
L_DIN : in std_logic_vector(... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity struct_out is
generic (
N_INST : boolean := true;
S_INST : boolean := true;
E_INST : boolean := true;
W_INST : boolean := true
);
port (
CLOCK : in std_logic;
RESET : in std_logic;
-- local
L_DIN : in std_logic_vector(... |
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
entity cpu_tb is
generic (FIRMWARE : string);
end entity cpu_tb;
architecture behav of cpu_tb is
component cpu is
port (clk : in std_logic;
rst : in std_logic;
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:16:59 11/21/2013
-- Design Name:
-- Module Name: IF_ID - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Rewritten on basis from Matthieu Cattin,
-- # taken from the gn4124-core on ohwr.org
-- ####################################
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use IEEE.STD_L... |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Rewritten on basis from Matthieu Cattin,
-- # taken from the gn4124-core on ohwr.org
-- ####################################
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use IEEE.STD_L... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OMUXT is
Port ( Crs2 : in STD_LOGIC_VECTOR (31 downto 0);
SEUimm: in STD_LOGIC_VECTOR (31 downto 0);
i : in STD_LOGIC;
oper2 : out STD_LOGIC_VECTOR (31 downto 0));
end OMUXT;
architecture Behavioral of OMUXT is
begin
process(... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OMUXT is
Port ( Crs2 : in STD_LOGIC_VECTOR (31 downto 0);
SEUimm: in STD_LOGIC_VECTOR (31 downto 0);
i : in STD_LOGIC;
oper2 : out STD_LOGIC_VECTOR (31 downto 0));
end OMUXT;
architecture Behavioral of OMUXT is
begin
process(... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OMUXT is
Port ( Crs2 : in STD_LOGIC_VECTOR (31 downto 0);
SEUimm: in STD_LOGIC_VECTOR (31 downto 0);
i : in STD_LOGIC;
oper2 : out STD_LOGIC_VECTOR (31 downto 0));
end OMUXT;
architecture Behavioral of OMUXT is
begin
process(... |
configuration conf of ent is
use work.foo;
attribute x of y : signal is 5;
for arch
for all : comp
use entity work.foo(x);
end for;
end for;
end configuration;
|
configuration conf of ent is
use work.foo;
attribute x of y : signal is 5;
for arch
for all : comp
use entity work.foo(x);
end for;
end for;
end configuration;
|
configuration conf of ent is
use work.foo;
attribute x of y : signal is 5;
for arch
for all : comp
use entity work.foo(x);
end for;
end for;
end configuration;
|
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
... |
--------------------------------------------------------------------------
--
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use... |
-----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : Infra-red Receiver for NEC TX Format
-- Author : Jan Dürre
-- Last update : 12.08.2014
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.a... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library verilog;
use verilog.vl_types.all;
entity PC is
port(
PC_in : in vl_logic_vector(31 downto 0);
PC_out : out vl_logic_vector(31 downto 0);
Clk : in vl_logic;
PC_write_en : in vl_logic
);
end PC;
|
entity test is
package a is new b generic map(c => ((bar baz)) foo);
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.05.2016 21:14:53
-- Design Name:
-- Module Name: tb_main_design_icmp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencie... |
-- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.cpu_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity clkdiv is
Port (
CLK : in STD_LOGIC;
-- CPU interface
CLK50MHz : out STD_LOGIC := '0';
CLK25MHz ... |
entity test is
subtype t is foo(0 to 2)(bar);
end;
|
entity repro is
end repro;
architecture behav of repro is
signal v : natural;
constant c : integer := 5;
begin
v <= natural (c)'a;
end behav;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Entity: Sorting network: bitonic s... |
------------------------------------------------------------------------------------------------------------------------
-- Comment
------------------------------------------------------------------------------------------------------------------------
--+--------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- drp_arbiter.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port ( clk : in std_logic;
reset : in std_logic;
pause : in std_logic;
count_out : out std_logic_vector(3 downto 0));
end counter;
architecture Behavioral of counter is
signal temp_count : std... |
-------------------------------------------------------------------------------
-- ADC LTC2351 module
--
-- Operates the LTC2351 in free running mode and connects it to
-- the internal parallel bus of the beacon board.
-- Provides a 'done' signal to the bus which can be used as an interrupt
-- source
--
-- Connects t... |
-------------------------------------------------------------------------------
-- ADC LTC2351 module
--
-- Operates the LTC2351 in free running mode and connects it to
-- the internal parallel bus of the beacon board.
-- Provides a 'done' signal to the bus which can be used as an interrupt
-- source
--
-- Connects t... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE STD.textio.all;
ENTITY tb_FIR_filter IS
GENERIC(
N: integer := 8;
Nb: integer := 9;
N_sample: integer := 1000
);
END ENTITY;
ARCHITECTURE test OF tb_FIR_filter IS
TYPE vector_test IS ARRAY (N_sample-1 DOWNTO 0) OF INTEGER;
... |
entity repro is
end;
architecture behav of repro is
subtype byte is bit_vector (7 downto 0);
type byte_array is array (1 to 10, boolean, 'a' to 'c') of byte;
signal s : byte_array;
begin
process
begin
wait;
end process;
end behav;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
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