content stringlengths 1 1.04M ⌀ |
|---|
package fifo_pkg is
end fifo_pkg;
package fifo_pkg is
end fifo_pkg;
package fifo_pkg is
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This fil... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- NEED RESULT: ARCH00472: Entity designator in an attribute spec may be a simple name or an operator symbol passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
----------------------... |
-------------------------------------------------------------------------------
-- Title : Fine Delay FMC SPEC (Simple PCI-Express FMC Carrier) top level
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File : spec_top_std.... |
entity entity_attr is
constant MIN_DELAY : NATURAL := 42;
attribute DELAY : NATURAL;
attribute DELAY of entity_attr : entity is MIN_DELAY;
end entity;
architecture foo of entity_attr is
begin
end architecture;
entity issue197 is
end entity;
architecture foe of issue197 is
constant fumble: natural := wor... |
entity entity_attr is
constant MIN_DELAY : NATURAL := 42;
attribute DELAY : NATURAL;
attribute DELAY of entity_attr : entity is MIN_DELAY;
end entity;
architecture foo of entity_attr is
begin
end architecture;
entity issue197 is
end entity;
architecture foe of issue197 is
constant fumble: natural := wor... |
entity entity_attr is
constant MIN_DELAY : NATURAL := 42;
attribute DELAY : NATURAL;
attribute DELAY of entity_attr : entity is MIN_DELAY;
end entity;
architecture foo of entity_attr is
begin
end architecture;
entity issue197 is
end entity;
architecture foe of issue197 is
constant fumble: natural := wor... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package utils is
function imax (
constant M : integer;
constant N : integer
)
return integer;
function imin (
constant M : integer;
constant N : integer
)
return integer;
function log2(
constant N : intege... |
-------------------------------------------------------------------------------
--! @file subMatrix.vhd
--! @brief AES substitute matrix function
--! @project VLSI Book - AES-128 Example
--! @author Michael Muehlberghuber (mbgh@iis.ee.ethz.ch)
--! @company Integrated Systems Laboratory, ETH Zurich
... |
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: gl_dff5.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- =================================================... |
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: gl_dff5.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- =================================================... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
----------------------------------------------------------------------------------
-- Author: Marcin Osowski
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.types.all;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------|
-- Author : Miguel Morales-Sandoval Copyrights (R) |
-- Project : " Reconfigurable ECC" |
-- Organization : INAOE, Computer Science Department |
-- Date : Originally created March,... |
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This progr... |
-- **************************************************************************
-- READ FLOW
-- **************************************************************************
-- Ce composant est connecte a un com_flow_fifo en entree et a un processing (FV/LV/Data) en sortie
--
-- 16/10/2014 - creation
----------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:01:51 11/08/2015
-- Design Name:
-- Module Name: shift_register_n_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
---------------------------------------------------------------------------------
-- Engineer: Klimann Wendelin
--
-- Create Date: 08:36:20 11/Okt/2013
-- Design Name: i2s_out
--
-- Description:
--
-- This module provides a bridge between an I2S serial device (audio ADC, S/PDIF
-- Decoded data) and a para... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- $Id: sys_conf_ba4_msim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf_ba4_msim
-- Description: Defini... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
----------------------------------------------------------------------------------
-- Organizacao e Arquitetura de Computadores
-- Professor: Marcelo Grandi Mandelli
-- Responsaveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimaraes
----------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Organizacao e Arquitetura de Computadores
-- Professor: Marcelo Grandi Mandelli
-- Responsaveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimaraes
----------------------------------------------------------------... |
-------------------------------------------------------------------------------------
-- FILE NAME : tb_sip_capture_x4.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : Jan 21, 2015
-----------------------------------------... |
--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
-- pragma translate_off
librar... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
architecture RTL of FIFO is
begin
process
begin
loop end loop;
loop end loop END_LOOP_LABEL;
-- Violations below
loop end loop
;
loop end loop END_LOOP_LABEL
;
end process;
end;
|
-- The FLI doesn't appear to support an entrypoint defined from the
-- command line parameters or using a pre-defined symbol in a library
-- (unlike VPI or VHPI). Therefore an entrypoint has to come from
-- the VHDL side. Because we require access to the FLI at elaboration
-- to register the start of sim callback, we... |
-- The FLI doesn't appear to support an entrypoint defined from the
-- command line parameters or using a pre-defined symbol in a library
-- (unlike VPI or VHPI). Therefore an entrypoint has to come from
-- the VHDL side. Because we require access to the FLI at elaboration
-- to register the start of sim callback, we... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:32:17 02/15/2017
-- Design Name:
-- Module Name: Detectordepulso - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
--... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY floprgeneric IS
GENERIC (N: INTEGER:=32);
PORT (d: IN std_logic_vector(N-1 DOWNTO 0);
clk, reset: IN std_logic;
q: OUT std_logic_vector(N-1 DOWNTO 0));
END floprgeneric;
ARCHITECTURE flopr_est OF floprgeneric IS
BEGIN
PROCESS(clk, reset... |
library verilog;
use verilog.vl_types.all;
entity EmitOneCH is
port(
Transmit_CLK : in vl_logic;
RX_Gate : in vl_logic;
EmitDelay : in vl_logic_vector(7 downto 0);
Emit_Width : in vl_logic_vector(5 downto 0);
TXP : out vl_l... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:37:51 10/29/2011
-- Design Name:
-- Module Name: procesoJugador - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- ... |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : if a = '1' generate
end generate;
CASE_LABEL : case data generate
end generate;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
END generate;
IF_LABEL : if a = '1' generate
END gen... |
-------------------------------------------------------------------------------
-- Entrée
-- clk, reset : la clock et le reset
-- T : un tick ('1' ou '0')
-- E : un entier entre 0 et 7, controllant la vitesse du tick 'S'
--
-- Sortie
-- S : un tick plus ou moins lent en fonction de 'E',
-- généré à partir de 'T'
-... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
package test_pkg is
shared variable shared_var : boolean := false;
procedure log(
va1 : boolean := shared_var
);
end package;
package body test_pkg is
procedure log( va1 : boolean := shared_var ) is
begin
report "va1 is " & boolean'image(va1);
end procedure;
end package body... |
-------------------------------------------------------------------------------
--
-- T411 system toplevel.
--
-- $Id: t411.vhd,v 1.2 2008-08-23 11:19:20 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use... |
-- NEED RESULT: ARCH00419.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00419: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00419: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00419: One i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------------------------
-- Filter Bank Implementation
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
-------------------------------------------... |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' t... |
----------------------------------------------------------------------------------
-- Company: Trenz Electronic GmbH
-- Engineer: Antti Lukats
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revisi... |
-- NEED RESULT: ARCH00136.P1: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136.P2: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00136.P3: Multi inertial transactions occurred on signal asg with simple n... |
-------------------------------------------------------------------------------
-- Title : Slave checker
-- Project :
-------------------------------------------------------------------------------
-- File : slave_checker.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-... |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: memData.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ==================... |
entity lfsr16 is
generic (
WIDTH : positive := 16;
TAP : natural := 3 );
port (
clk : in bit;
reset : in bit; -- Asynchronous
en : in bit;
value : out bit_vector(15 downto 0) );
end entity;
architecture rtl of lfsr16 is
signal state_r : bit_vector(WI... |
entity lfsr16 is
generic (
WIDTH : positive := 16;
TAP : natural := 3 );
port (
clk : in bit;
reset : in bit; -- Asynchronous
en : in bit;
value : out bit_vector(15 downto 0) );
end entity;
architecture rtl of lfsr16 is
signal state_r : bit_vector(WI... |
entity lfsr16 is
generic (
WIDTH : positive := 16;
TAP : natural := 3 );
port (
clk : in bit;
reset : in bit; -- Asynchronous
en : in bit;
value : out bit_vector(15 downto 0) );
end entity;
architecture rtl of lfsr16 is
signal state_r : bit_vector(WI... |
entity lfsr16 is
generic (
WIDTH : positive := 16;
TAP : natural := 3 );
port (
clk : in bit;
reset : in bit; -- Asynchronous
en : in bit;
value : out bit_vector(15 downto 0) );
end entity;
architecture rtl of lfsr16 is
signal state_r : bit_vector(WI... |
entity lfsr16 is
generic (
WIDTH : positive := 16;
TAP : natural := 3 );
port (
clk : in bit;
reset : in bit; -- Asynchronous
en : in bit;
value : out bit_vector(15 downto 0) );
end entity;
architecture rtl of lfsr16 is
signal state_r : bit_vector(WI... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_1_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 08:31:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Auth... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:45:35 05/22/2013
-- Design Name:
-- Module Name: JKS - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 2019, Fabio Belavenuto (belavenuto@gmail.com)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions ... |
-- $Id: tb_tst_sram_n2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_sram_n2
-- Description: Configuratio... |
library ieee;
use ieee.std_logic_1164.all;
use work.basic_types_pkg.all;
use work.input_types_pkg.all;
use work.graphics_types_pkg.all;
use work.text_mode_pkg.all;
use work.sprites_pkg.all;
use work.game_state_pkg.all;
use work.resource_handles_pkg.all;
use work.resource_handles_helper_pkg.all;
use work.resou... |
-------------------------------------------------------------------------------------
-- FILE NAME : .vhd
-- AUTHOR : Luis F. Munoz
-- COMPANY : 4DSP
-- UNITS : Entity - toplevel_template
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : May 21, 2014
--------------------... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:05:02 07/30/2015
-- Design Name:
-- Module Name: C:/Users/rccoder/ALU/CPU/CPU_tb.vhd
-- Project Name: CPU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test B... |
--------------------------------------------------------------------------
-- Shift
--------------------------------------------------------------------------
-- 0,01,000 SLL (Shift Left logical)
-- 0,01,010 SRL (Shift Right logical)
-- 0,01,011 SRA (Shift Right arithmetic)
---------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity maxOnesCounter is
port(
x : in std_logic;
clock : in std_logic;
maxOnes : out std_logic_vector(7 downto 0) := (others => '0')
);
end maxOnesCounter;
architecture behavioural of maxOnesCounter is
begin
clock_process: proc... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity regbank_3p is
generic (
ADDRESS_BITS: integer := 4;
ZEROSIZE: integer := 4
);
port (
clk: in std_logic;
rb1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb1_en: in std... |
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute it and/or modify
-- it... |
--
-- Author: Pawel Szostek (pawel.szostek@cern.ch)
-- Date: 27.07.2011
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity dummy is
port (o1: out std_logic_vector(8 downto 1); -- intentionally messed indices
i1: in std_logic_vector(0 to 7) ... |
--
-- Author: Pawel Szostek (pawel.szostek@cern.ch)
-- Date: 27.07.2011
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity dummy is
port (o1: out std_logic_vector(8 downto 1); -- intentionally messed indices
i1: in std_logic_vector(0 to 7) ... |
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- * Redistributions i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library IEEE;
use ieee.std_logic_1164.all;
entity alu is
port( --Inputs
a, b, less, ainvert , binvert, carryin : in std_logic;
ALUOp : in std_logic_vector(1 downto 0);
--Outputs
carryout, result, set, overflow: out std_logic
);
end entity alu;
architecture behav of alu is
signal amuxoutput, bmuxoutput, and... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_215 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_215;
architecture augh of mul_215 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_215 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_215;
architecture augh of mul_215 is
signal tmp_res : signed(... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
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