content stringlengths 1 1.04M ⌀ |
|---|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/18/2013 11:21:31 PM
-- Design Name:
-- Module Name: ten_gig_eth - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
--------------------------------------------------------------------------------
---- ----
---- This file is part of the yaVGA project ----
---- http://www.opencores.org/?do=project&who=yavga -... |
-- NEED RESULT: ARCH00258: Matching end name not necessary on architecture body passed
-- NEED RESULT: ARCH00258: Matching end name permitted on architecture body passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:34:05 06/17/2015
-- Design Name:
-- Module Name: PH - slt
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revis... |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:12:40 12/10/2009
-- Design Name:
-- Module Name: E:/FPGA/Projects/Current Projects/Systems/OZ-3/MEMIO_TB.vhd
-- Project Name: OZ-3
-- Target Device:
-- Tool versions:
--... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:12:40 12/10/2009
-- Design Name:
-- Module Name: E:/FPGA/Projects/Current Projects/Systems/OZ-3/MEMIO_TB.vhd
-- Project Name: OZ-3
-- Target Device:
-- Tool versions:
--... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
use work.utils_pak.all;
entity controller_tb is end;
architecture controller_tb_arc of controller_tb is
signal clk: std_logic := '0';
signal reset_n: std_logic;
sig... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
use work.utils_pak.all;
entity controller_tb is end;
architecture controller_tb_arc of controller_tb is
signal clk: std_logic := '0';
signal reset_n: std_logic;
sig... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll1 is
port
(-- Clock in ports
CLKIN_IN : in std_logic;
-- Clock out ports
CLK0_OUT : out std_logic;
... |
library verilog;
use verilog.vl_types.all;
entity finalproject_jtag_uart is
port(
av_address : in vl_logic;
av_chipselect : in vl_logic;
av_read_n : in vl_logic;
av_write_n : in vl_logic;
av_writedata : in vl_logic_vector(31 downto 0);... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.Display_Management_pkg.all;
entity Tools_Memory is --===========================================================================
generic(
enable_debug : boolean := true;
resolution : string := "1920x1080@60Hz"
)... |
-- Inter-Prediction Interpolator Filter
-- see ITU Std. 8.4.2.2.1 and 8.4.2.2.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity half_pixel_interpolator_fir is
port(
x0 : in std_logic_vector(7 downto 0);
x1 : in std_logic_v... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- File: calc_next_age.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Dec 16 22:44:22 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity calc_next_age is
port (
age_out: out std_logic;
live_count: in unsigned(3 downto 0)... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:33:00 09/05/2016
-- Design Name:
-- Module Name: C:/daten/development/fpga/lxp32proj/lxp32_soc/tb_soc.vhd
-- Project Name: lxp32_01
-- Target Device:
-- Tool versions:
-- Descript... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _ ... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gais... |
library IEEE;
use IEEE.Std_Logic_1164.all;
entity fsm is
port (dif: in std_logic_vector(1 downto 0);
clock, init, fire, reset: in std_logic;
memaddr: in std_logic_vector(1 downto 0);
linha: in std_logic_vector(13 downto 0);
displaycont: out std_logic_vector(7 downto 0);
displayaddr: out std_logic_vector(1 d... |
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--Module Title: Gen_Latch_High
--Module Description:
-- This module is a generic data latch. When the enable signal is high, a register
-- changes to the value placed on the input. When the enable signal... |
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--Module Title: Gen_Latch_High
--Module Description:
-- This module is a generic data latch. When the enable signal is high, a register
-- changes to the value placed on the input. When the enable signal... |
-----------------------------------------------------------------------------
-- Package: fse_v2
-- File: romprn_tech.vhd
-- Author: Sergey Khabarov - sergeykhbr@gmail.com
-- Description: Technology specific Bootable ROM
------------------------------------------------------------------------------
lib... |
-----------------------------------------------------------------------------
-- Package: fse_v2
-- File: romprn_tech.vhd
-- Author: Sergey Khabarov - sergeykhbr@gmail.com
-- Description: Technology specific Bootable ROM
------------------------------------------------------------------------------
lib... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb1_pkg.all;
use work.tl_vector_pkg.all;
use work.tl_string_util_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity tb_ulpi_host is
end ;
architecture tb of tb_ulpi_host is
signal clock : std_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb1_pkg.all;
use work.tl_vector_pkg.all;
use work.tl_string_util_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity tb_ulpi_host is
end ;
architecture tb of tb_ulpi_host is
signal clock : std_... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--------------------------------------------------------------------------------
-- File Name: PRBS_ANY.vhd
-- Version: 1.1
-- Date: 06-2015
--------------------------------------------------------------------------------
--
-- Company: Xilinx, Inc.
-- Contributor: Daniele Riccardi, Paolo Nov... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity reset_ctrl is
port(
I_clk: in std_logic;
I_reset: in std_logic; -- input for "active high" reset signal
I_reset_inv: in std_logic; -- input for "active low" reset signal
O_reset: out std_logic -- reset output, "active high"
);
en... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 09:04:41 2017
-- Host : Shaun running 64-bit major relea... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 09:04:41 2017
-- Host : Shaun running 64-bit major relea... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 09:04:41 2017
-- Host : Shaun running 64-bit major relea... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity tb_ram4 is
end tb_ram4;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ram4 is
signal rdat : std_logic_vector(1 downto 0);
signal raddr : std_logic_vector(1 downto 0);
signal init : std_logic_vector(7 downto 0);
signal rst : std_logic;
signal clk : std_logic;
begin
dut: entity ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity watchdogDevice_v1_0 is
generic (
-- Users to add parameters here
base_clk : INTEGER := 125000000;
unique_id : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
-- User parameters ends
-- Do not modify the parameters beyo... |
--
-- A simulation model of VIC20 hardware
-- Copyright (c) MikeJ - March 2003
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use packagefa4bit00.all;
entity topfa4bit00 is
port(
C00: in std_logic ;
A00: in std_logic ;
B00: in std_logic ;
S00: out std_logic ;
C01: out std_logic );
end;
architecture topfa4bit0 o... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
library WORK;
package globals is
-- CONFIGURATION CONSTANTS
constant C_INCLUDE_DECODING_LOGIC : boolean := true; -- Allow both enc and decryption
constant C_CTRL_SIGNAL_SIZE : integer :=... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
library WORK;
package globals is
-- CONFIGURATION CONSTANTS
constant C_INCLUDE_DECODING_LOGIC : boolean := true; -- Allow both enc and decryption
constant C_CTRL_SIGNAL_SIZE : integer :=... |
--Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated do... |
-------------------------------------------------------------------------------
--
-- GCpad controller core
--
-- $Id: gcpad_tx.vhd,v 1.2 2004-10-08 20:51:59 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and ... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "Memory_access"
-- Project :
-------------------------------------------------------------------------------
-- File : Memory_access_tb.vhd
-- Author : Simon Desfarges
-- Company :
-- C... |
-------------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2014, Digilent RO. All rights reserved
--
----------------------------------------------... |
----------------------------------------------------------------------
-- myChpOsc (for RTG4)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Instantiate 50 MHz OnChip RC Oscillator
--
-- !!Watch Out!! Think twice where the OnChip Oscillator can be used.
-- The... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEE... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLROM_3_12.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------... |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- ... |
architecture RTL of FIFO is
shared variable shar_var1 : integer;
begin
process
variable var1 : integer;
begin
end process;
end architecture RTL;
-- Violations below
architecture RTL of FIFO is
shared variable shar_var1 :integer;
shared variable shar_var1 : integer;
begin
process
variab... |
-------------------------------------------------------------------------------
-- $Id: or_gate.vhd,v 1.1.4.1 2009/10/06 21:09:10 gburch Exp $
-------------------------------------------------------------------------------
-- or_gate.vhd - entity/architecture pair
-------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: or_gate.vhd,v 1.1.4.1 2009/10/06 21:09:10 gburch Exp $
-------------------------------------------------------------------------------
-- or_gate.vhd - entity/architecture pair
-------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: or_gate.vhd,v 1.1.4.1 2009/10/06 21:09:10 gburch Exp $
-------------------------------------------------------------------------------
-- or_gate.vhd - entity/architecture pair
-------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: or_gate.vhd,v 1.1.4.1 2009/10/06 21:09:10 gburch Exp $
-------------------------------------------------------------------------------
-- or_gate.vhd - entity/architecture pair
-------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: or_gate.vhd,v 1.1.4.1 2009/10/06 21:09:10 gburch Exp $
-------------------------------------------------------------------------------
-- or_gate.vhd - entity/architecture pair
-------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: or_gate.vhd,v 1.1.4.1 2009/10/06 21:09:10 gburch Exp $
-------------------------------------------------------------------------------
-- or_gate.vhd - entity/architecture pair
-------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: or_gate.vhd,v 1.1.4.1 2009/10/06 21:09:10 gburch Exp $
-------------------------------------------------------------------------------
-- or_gate.vhd - entity/architecture pair
-------------------------------------------------------... |
-- Automatically generated: write_netlist -wraprm_lec -vhdl -module extadc-wrapreconfmodule-lec.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ExtADC is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
Sen... |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... |
architecture RTL of FIFO is
begin
process
begin
end process;
-- Violations below
PROCESS
begin
end process;
end architecture RTL;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.14:51:52)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir2_hype_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_signed.all;
use IEEE.STD_logic_arith.all;
entity operational_unit is
generic(
N: integer := 4;
M: integer := 8
);
port(
clk,rst : in STD_LOGIC;
y : in STD_LOGIC_VECTOR(25 downto 1);
COP : in std_logic;
d1 : in STD_LOGIC_VECTOR(... |
library ieee;
use ieee.std_logic_1164.all;
entity ShiftReg is
generic (N: integer:= 3);
port(
Din, CE, CLK, CLR: in std_logic;
Dout: out std_logic_vector(N-1 downto 0)
);
end ShiftReg;
architecture Beh of ShiftReg is
signal outS: std_logic_vector(N-1 downto 0);
begin
process(CLR, CLK)
begin ... |
entity test is
end test;
library ieee;
use ieee.std_logic_1164.all;
package foo is
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U ... |
entity test is
end test;
library ieee;
use ieee.std_logic_1164.all;
package foo is
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U ... |
entity test is
end test;
library ieee;
use ieee.std_logic_1164.all;
package foo is
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U ... |
-------------------------------------------------------------------------------
-- Title : Clock Enable synchronizer for data/valid signals
-- Project :
-------------------------------------------------------------------------------
-- File : ce_synch.vhd
-- Author : Lucas Russo <lerwys@gmail.com>
--... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
---------------------------------------------------------------------------------------------------
--
-- Title : Testbench for Two End Point Example for Ring Bus
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
--------------------------------------------------------------... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_5_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_5_e-... |
-- -------------------------------------------------------------
--
-- Entity Declaration for bsr
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: bsr... |
-------------------------------------------------------------------------------
-- Author: Aragonés Orellana, Silvia
-- García Garcia, Ruy
-- Project Name: PIC
-- Design Name: ram.vhd
-- Module Name: spr.vhd
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEE... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY dec_keyboard IS
PORT( hex_bus : IN STD_LOGIC_VECTOR(7 downto 0);
scan_rd : IN STD_LOGIC;
clk : IN STD_LOGIC;
bin_digit : OUT STD_LOGIC_VECTOR(7 downto 0);
int ... |
-------------------------------------------------------------------------
---- ----
---- Company: University of Bonn ----
---- Engineer: Daniel Hahne & John Bieling ----
---- ... |
-- A testbench has no ports.
entity adder_tb is
end adder_tb;
architecture behav of adder_tb is
-- Declaration of the component that will be instantiated.
component adder
port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
end component;
-- Specifies which entity is bound with the component... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:50:47 11/13/2015
-- Design Name:
-- Module Name: C:/Users/nledwith/Desktop/Exp8/Exp8_actual/Wrap_test.vhd
-- Project Name: Exp8_actual
-- Target Device:
-- Tool versions: ... |
entity access8 is
end entity;
architecture test of access8 is
type int_vector is array (natural range <>) of integer;
type rec is record
f : int_vector(1 to 1000);
end record;
type big_array is array (natural range <>) of rec;
type p_big_array is access big_array;
signal n : integer :... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Keyboard Controller
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Keyboard Controller
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Keyboard Controller
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Keyboard Controller
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Keyboard Controller
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E... |
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