content stringlengths 1 1.04M ⌀ |
|---|
-- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ********************************************************************... |
-- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ********************************************************************... |
-- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ********************************************************************... |
-- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ********************************************************************... |
-- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ********************************************************************... |
-- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ********************************************************************... |
-- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ********************************************************************... |
-- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ********************************************************************... |
-- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ********************************************************************... |
-- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ********************************************************************... |
-- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ********************************************************************... |
-- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ********************************************************************... |
-- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ********************************************************************... |
-- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ********************************************************************... |
entity test is
subtype t is foo (0 to 2)(open)(bar'baz);
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
library ieee;
use ieee.std_logic_1164.all;
library std;
use std.env.all;
entity cover_report1 is
end entity cover_report1;
architecture test of cover_report1 is
signal s_a : std_logic;
signal s_b : std_logic;
signal s_c : std_logic;
signal s_clk : std_logic := '0';
begin
s_clk <= not(s_cl... |
library ieee;
use ieee.std_logic_1164.all;
library std;
use std.env.all;
entity cover_report1 is
end entity cover_report1;
architecture test of cover_report1 is
signal s_a : std_logic;
signal s_b : std_logic;
signal s_c : std_logic;
signal s_clk : std_logic := '0';
begin
s_clk <= not(s_cl... |
-------------------------------------------------------------------------------
--
-- Module : decode_8b10b_wrapper.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder
--
-- Description : Top-level core wrapper file
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER ... |
-------------------------------------------------------------------------------
--
-- Module : decode_8b10b_wrapper.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder
--
-- Description : Top-level core wrapper file
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:53:08 04/04/2013
-- Design Name:
-- Module Name: MUX2x1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision... |
entity concat5 is
end entity;
architecture test of concat5 is
function count_as(x : string) return integer is
variable r : integer := 0;
begin
for i in 1 to x'length loop
if x(i) = 'a' then
r := r + 1;
end if;
end loop;
return r;
end ... |
entity concat5 is
end entity;
architecture test of concat5 is
function count_as(x : string) return integer is
variable r : integer := 0;
begin
for i in 1 to x'length loop
if x(i) = 'a' then
r := r + 1;
end if;
end loop;
return r;
end ... |
entity concat5 is
end entity;
architecture test of concat5 is
function count_as(x : string) return integer is
variable r : integer := 0;
begin
for i in 1 to x'length loop
if x(i) = 'a' then
r := r + 1;
end if;
end loop;
return r;
end ... |
entity concat5 is
end entity;
architecture test of concat5 is
function count_as(x : string) return integer is
variable r : integer := 0;
begin
for i in 1 to x'length loop
if x(i) = 'a' then
r := r + 1;
end if;
end loop;
return r;
end ... |
entity concat5 is
end entity;
architecture test of concat5 is
function count_as(x : string) return integer is
variable r : integer := 0;
begin
for i in 1 to x'length loop
if x(i) = 'a' then
r := r + 1;
end if;
end loop;
return r;
end ... |
-- -------------------------------------------------------------
--
-- Entity Declaration for __COMMON__
--
-- Generated
-- by: wig
-- on: Mon Mar 22 12:42:23 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../io.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ... |
--
-- This file is part of top_wireworld
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either versio... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/07/30 20:12:36
-- Nombre del módulo: siete_segmentos_completo - Behavioral
-- Descripción:
-- Se encarga de unir el decodifi... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/07/30 20:12:36
-- Nombre del módulo: siete_segmentos_completo - Behavioral
-- Descripción:
-- Se encarga de unir el decodifi... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/07/30 20:12:36
-- Nombre del módulo: siete_segmentos_completo - Behavioral
-- Descripción:
-- Se encarga de unir el decodifi... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VCo... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_332 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_332;
architecture augh of sub_332 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_332 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_332;
architecture augh of sub_332 is
signal carry_inA : std_l... |
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2009 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com
--
-- This source file is free software: you ... |
entity sub is
port (
i : in bit_vector(7 downto 0);
o : out bit_vector(7 downto 0) );
end entity;
architecture test of sub is
begin
o <= not i after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity elab14 is
end entity;
archite... |
entity sub is
port (
i : in bit_vector(7 downto 0);
o : out bit_vector(7 downto 0) );
end entity;
architecture test of sub is
begin
o <= not i after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity elab14 is
end entity;
archite... |
entity sub is
port (
i : in bit_vector(7 downto 0);
o : out bit_vector(7 downto 0) );
end entity;
architecture test of sub is
begin
o <= not i after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity elab14 is
end entity;
archite... |
entity sub is
port (
i : in bit_vector(7 downto 0);
o : out bit_vector(7 downto 0) );
end entity;
architecture test of sub is
begin
o <= not i after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity elab14 is
end entity;
archite... |
entity sub is
port (
i : in bit_vector(7 downto 0);
o : out bit_vector(7 downto 0) );
end entity;
architecture test of sub is
begin
o <= not i after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity elab14 is
end entity;
archite... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE rc5_pkg IS
type rc5_rom_26 is array (0 to 25) of std_logic_vector(31 downto 0);
type rc5_rom_4 is array (0 to 3) of std_logic_vector(31 downto 0);
type rc5_key_StateType is (ST_IDLE, -- In this state RC5 key expansion is ready for input
ST_KEY_I... |
`entity fum is
`end entity;
`
`architecture bul of fum is
` begin
` end architecture;
```
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 17:45:06 07/30/2009
-- Design Name:
-- Module Name: Sys_SecondTimer - Structural
-- Project Name: Second Timer
-- Target Devices:
-- Tool versions:
-- Descripti... |
entity foo is end;
architecture bar of foo is
type TIME is range -1E18 to 1E18 units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units;
type DISTANCE is range 0 to 1E16 units
Å;
nm = 10 Å;
um = 1000 nm;
mm = 1000 um;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_capture_GN5SAAB6UA is
generic ( XFILE : string... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_capture_GN5SAAB6UA is
generic ( XFILE : string... |
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com
--
-- This source file is free software: you ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: TODO
--
-- Description:... |
-- Automatically generated: write_netlist -wraprm_vhdl2008 -vhdl -module adt7310-wrapreconfmodule-vhdl2008.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ADT7310 is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_lo... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- Data width: 32
-- Parity: False
------------------------------------------------------------
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- Data width: 32
-- Parity: False
------------------------------------------------------------
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- Data width: 32
-- Parity: False
------------------------------------------------------------
... |
entity test is
package a is new b generic map(c => foo(bar (open)(open)(baz (quz'xxx))));
end;
|
-- $Id: sys_conf_sim.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MulticycleControl is
port(
Opcode: in std_logic_vector(5 downto 0);
clk: in std_logic;
RegDst, RegWrite, ALUSrcA, IRWrite, MemtoReg, MemWrite, MemRead, IorD, PCWrite, PCWriteCond: out std_logic;
ALUSrcB, ALUOp, PCSource: out ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------------
-- FILE NAME : data_align.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : AUG 21, 2014
------------------------------------------------... |
--!
--! @file: exercise5_14.vhd
--! @brief: Recommended Unsigned Adder/Substracter
--! @author: Antonio Gutierrez
--! @date: 2013-10-23
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity unsigned_adder_substracte... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- control module
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY control IS
PORT(
Opcode : IN STD_LOGIC_VECTOR( 5 DOWNTO 0 );
Function_opcode : IN STD_LOGIC_VECTOR( 5 DOWNTO 0 );
RegDst : OUT STD_LOGIC;
RegWrite : OUT STD_LOGIC;
... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DTAR is port(
D : in std_logic;
C : in std_logic;
CLR : in std_logic;
Q : out std_logic
);
end DTAR;
architecture behavior of DTAR is
signal S : std_logic;
begin
Main : process (CLR, D, C, S)
begin
if CLR = '1' then
S <= '0';
elsif rising_edge... |
library ieee;
use ieee.std_logic_1164.all;
use work.mixer_pkg.sample_array;
entity mixer is
generic(
sample_bits: positive
);
port(
i_samples: in sample_array(0 to 127)(sample_bits-1 downto 0)
);
end mixer;
architecture behavioural of mixer is
begin
end behavioural;
|
-------------------------------------------------------------------------------
--
-- $Id$
--
-- jmem_core - a generic interface module for accessing on-chip and off-chip
-- memory and peripherals
--
-- For host software support visit
-- http://urjtag.org/
--
-- This program is free software; you can redi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:06:07 05/29/2014
-- Design Name:
-- Module Name: FSM2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision: ... |
-----------------------------------------------------------------------------------------------------------
--
-- SINGLE PRECISION FP NUMBERS COMPARATOR
--
-- Created by Claudio Brunelli, 2004
--
--------------------------------------------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02/14/2017 03:15:15 PM
-- Design Name:
-- Module Name: filter_lib - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity first is
Port(
led : out std_logic_vector(3 downto 0);
btn : in std_logic_vector(3 downto 0)
);
end first;
architecture Behavioralfirst of first is
begin
led <= btn;
end Behavioralfirst;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.custom_pkg.all;
entity controller is
port ( clk : in std_logic;
rst : in std_logic;
wea : in std_logic_vector(0 downto 0);
dina_image : in std_logic_vector(7 downto 0);
dina_weights : in std_logic_vector(23 downto 0);
addra_ima... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for BPM Swap Channels Interface Registers
---------------------------------------------------------------------------------------
-- File : wb_bpm_swap_regs.vhd
-- Author : a... |
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for BPM Swap Channels Interface Registers
---------------------------------------------------------------------------------------
-- File : wb_bpm_swap_regs.vhd
-- Author : a... |
-- TestBench Template
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
use virtual_button_lib.uart_constants.all;
use virtual_button_lib.uart_functions.all;
use virtual_button_lib.button_pkg.all;
... |
library ieee;
use ieee.math_real.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package Constants is
---------------------------FUNCTIONS---------------------------
function AddressBits(constant n : in integer) return integer;
function MaxValueBits(constant n : in integer) return integer;
function R... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
----------... |
-------------------------------------------------------------------------------
-- Title : Partial delta/sigma core testbench
-- Project :
-------------------------------------------------------------------------------
-- File : part_delta_sigma_tb.vhd
-- Author : Vitor Finotti Ferreira <finotti@fino... |
architecture RTL of FIFO is
begin
process
begin
label : for index in 4 to 23 loop
end loop;
label_loop : for index in 4 to 23 loop
end loop;
end process;
end;
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License... |
library ieee;
use ieee.std_logic_1164.all;
package work6 is
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic);
end component;
component TimeBase is
port(
CLOCK : in std_logic; -- input clock of 20... |
library ieee;
use ieee.std_logic_1164.all;
package work6 is
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic);
end component;
component TimeBase is
port(
CLOCK : in std_logic; -- input clock of 20... |
library ieee;
use ieee.std_logic_1164.all;
package work6 is
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic);
end component;
component TimeBase is
port(
CLOCK : in std_logic; -- input clock of 20... |
library ieee;
use ieee.std_logic_1164.all;
package work6 is
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic);
end component;
component TimeBase is
port(
CLOCK : in std_logic; -- input clock of 20... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
entity PACKETIZER_LV is
generic (
DATA_WIDTH: integer := 11;
current_address : integer := 0;
SHMU_address : intege... |
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