content stringlengths 1 1.04M ⌀ |
|---|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/Complex3Multiply.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.utils.all;
use work.constants_pkg.all;
package rv_components is
component orca is
generic (
REGISTER_SIZE : positive range 32 to 32 := 32;
RESET_VECTOR : std_logic_vector(31 downto 0) := X"00000000... |
-------------------------------------------------------------------------------
-- xps_intc - entity / architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This... |
architecture RTL of FIFO is
procedure PARITY
(signal X : in std_logic_vector;
signal Y : out std_logic);
procedure Proc_1 (constant In1: in Integer; variable O1: out Integer);
procedure Proc_2 (signal Sig: inout Bit);
procedure sum2num(signal a: in signed(3 downto 0);
signal b:... |
--------------------------------------------------------------------------------
--
-- Title : ctrl_game_block.vhd
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Ma... |
-------------------------------------------------------------------------------
-- Title : Synchronous FIFO
-------------------------------------------------------------------------------
-- Author : Carl Treudler (cjt@users.sourceforge.net)
-- Standard : VHDL'93/02
------------------------------------------... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:39:36 2017
-- Host : DarkCube running 64-bit major releas... |
-- The arithmetic-logic unit (ALU)
--
-- Luz micro-controller implementation
-- Eli Bendersky (C) 2008-2010
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
use work.utils_pak.all;
-- The 'op' input tells the ALU which operation to perform
-- in ... |
-- The arithmetic-logic unit (ALU)
--
-- Luz micro-controller implementation
-- Eli Bendersky (C) 2008-2010
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
use work.utils_pak.all;
-- The 'op' input tells the ALU which operation to perform
-- in ... |
---------------------------------------------------------------------
-- Barrel shifter
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Performs logical (unsigned) and arithmetic (signed) shifts
-- in both directions. Pipeline latency: 1 cycle.
-------------------------------------------... |
----------------------------------------------------------------------------------
-- Company: University of Genoa
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 11:06:29 07/26/2011
-- Design Name:
-- Module Name: newCaoticGen - Behavioral
-- Project Name:
-- Target Devices:
... |
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http... |
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http... |
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http... |
entity assign1 is
end;
use work.pkg.all;
architecture behav of assign1 is
begin
process
variable v : rec_4;
begin
v.a := 5;
assert v.a = 5 severity failure;
v.s := "Good";
assert v.a = 5 severity failure;
assert v.s = "Good" severity failure;
assert false report "ok" severity note;
... |
entity assign1 is
end;
use work.pkg.all;
architecture behav of assign1 is
begin
process
variable v : rec_4;
begin
v.a := 5;
assert v.a = 5 severity failure;
v.s := "Good";
assert v.a = 5 severity failure;
assert v.s = "Good" severity failure;
assert false report "ok" severity note;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 18/03/2015
--! Module Name: EPROC_OUT4
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use ... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 18/03/2015
--! Module Name: EPROC_OUT4
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use ... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 18/03/2015
--! Module Name: EPROC_OUT4
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use ... |
-- NEED RESULT: ARCH00653: The predefined attributes of an interface object (port) of mode 'out' for an entity may be read failed
-- NEED RESULT: ARCH00653.Proc1: The predefined attributes of an interface object (signal parameter) of mode 'out' for a subp may be read failed
-- NEED RESULT: ARCH00653.Proc2: The predef... |
-- TriggerInLogic.vhd
--
-- Deserializes triggers and passes them to the User Logic through a FIFO based interface.
-- The FIFO allows the trigger receive logic and the User Logic clock to have independent clocks.
--
-- REVISIONS
--
-- 3/6/2014 CRJ
-- Created
--
-- 7/31/2014 CRJ
-- Modified to allow use of I/O buf... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity parity_analyser_tb is
end parity_analyser_tb;
architecture behavior of parity_analyser_tb is
component PARITY_ANALYSER
port(A : in std_logic_vector(3 downto 0);
S : out std_logic);
... |
library verilog;
use verilog.vl_types.all;
entity SSD1306_VHDLImplementation_vlg_check_tst is
port(
CD : in vl_logic;
CLKO : in vl_logic;
CS : in vl_logic;
DO : in vl_logic;
RSTO : in vl_logic;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.UartPkg.all;
entity Chip_Power_tb is
generic (
SPISelect : integer := 1; -- 0: CPU, 1: CHLL
ImpulseGen : integer := 0 -- 0: no, 1: connect Inputs_i(7) to a signal with pulses for wa... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 242/130/136/1
library work;
use work.io_bus_pkg.all;
entity audio_select is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 242/130/136/1
library work;
use work.io_bus_pkg.all;
entity audio_select is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 242/130/136/1
library work;
use work.io_bus_pkg.all;
entity audio_select is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 242/130/136/1
library work;
use work.io_bus_pkg.all;
entity audio_select is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Module:
--
-- Authors: Thomas B. Preusser
--
-- Description: UAR... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Module:
--
-- Authors: Thomas B. Preusser
--
-- Description: UAR... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Module:
--
-- Authors: Thomas B. Preusser
--
-- Description: UAR... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF1_3_block6.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ---------------------------------... |
entity e is
end entity;
architecture test of e is
alias my_int is integer; -- OK
signal x : my_int; -- OK
subtype s is my_int range 1 to 5; -- OK
alias my_bad : integer is integer; -- Error
alias ax is x; -- OK
signal y : ax; ... |
entity e is
end entity;
architecture test of e is
alias my_int is integer; -- OK
signal x : my_int; -- OK
subtype s is my_int range 1 to 5; -- OK
alias my_bad : integer is integer; -- Error
alias ax is x; -- OK
signal y : ax; ... |
entity e is
end entity;
architecture test of e is
alias my_int is integer; -- OK
signal x : my_int; -- OK
subtype s is my_int range 1 to 5; -- OK
alias my_bad : integer is integer; -- Error
alias ax is x; -- OK
signal y : ax; ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
entity user_logic_hwtul is
generic(
G_INPUT_WIDTH : integer := 32;
G_DIVISOR_WIDTH : integer := 4;
divisor : std_logic_vector(0 to 3) := "101... |
--------------------------------------------------------------------------------
-- FILE: ControlUnit
-- DESC: Control unit of DLX
--
-- Author:
-- Create: 2015-06-01
-- Update: 2015-10-03
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logi... |
-- file: Clock.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a li... |
-- megafunction wizard: %DDR2 SDRAM Controller with UniPHY v13.1%
-- GENERATION: XML
-- ddr2ctrl.vhd
-- Generated using ACDS version 13.1 162 at 2013.12.06.15:39:20
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ddr2ctrl is
port (
pll_ref_clk : in std_logic ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_i2c_master_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_... |
Library ieee;
use ieee.std_logic_1164.all;
entity OneBitAdder is
port(
A, B, CIN: IN std_logic;
S, COUT: OUT std_logic
);
end OneBitAdder;
architecture impl of OneBitAdder is
begin
S <= A xor B xor CIN;
COUT <= (A and B) or (A and CIN) or (B and CIN);
end impl;
|
-- Simple IRQ Manager
-- Based on the original design by:
--
-- Fabrice Mousset (fabrice.mousset@laposte.net)
-- Project : Wishbone Interruption Manager (ARMadeus wishbone example)
-- See: http://www.armadeus.com/wiki/index.php?title=A_simple_design_with_Wishbone_bus
library ieee;
use ieee.std_logic_1164.a... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
use work.procedures.all;
entity tb_filter is
end tb_filter;
architecture behav of tb_filter is
signal rst : std_logic := '1';
signal clk :... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versi... |
-------------------------------------------------------------------------------
--
-- The Port 1 unit.
-- Implements the Port 1 logic.
--
-- $Id: p1-c.vhd,v 1.2 2005-06-11 10:08:43 arniml Exp $
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t4... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains con... |
----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2017 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in comp... |
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2016 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! @brief Simple UART module.
--! The foll... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_shadow_k1_k4_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
--... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:59:46 02/10/2016
-- Design Name:
-- Module Name: /home/csmajs/masfo001/lab4/tb.vhd
-- Project Name: lab4
-- Target Device:
-- Tool versions:
-- Description:
--
-- ... |
library verilog;
use verilog.vl_types.all;
entity dft_testbench is
end dft_testbench;
|
library verilog;
use verilog.vl_types.all;
entity dft_testbench is
end dft_testbench;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbonepkg.all;
entity sinkdev is
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type
);
end entity sinkdev;
architecture behave of sinkdev is
signal ack,err: std_l... |
--------- Test bench -----------------
library ieee;
use ieee.std_logic_1164.all;
library work;
entity testbench is
end entity;
architecture behaviorial of testbench is
component memory256x8 is
port (
ck : in std_logic;
we : in std_logic;
address : in std_logic_vector(7 downto 0);
dat... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s27_jed is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(0 downto 0)
);
end s27_jed;
architecture behaviour of s27_jed is
constant s000: std_logic_vector(2 downto 0) := "11... |
-- -------------------------------------------------------------
--
-- Generated Configuration for __COMMON__
--
-- Generated
-- by: lutscher
-- on: Tue Jun 23 10:43:20 2009
-- cmd: /home/lutscher/work/MIX/mix_1.pl a_clk.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author$
-- $Id$
-- $Date$
--... |
library IEEE;
use IEEE.std_logic_1164.all;
entity nor_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity nor_gate;
architecture rtl of nor_gate is
begin
c_o <= a_i nor b_i;
end architecture rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity nor_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity nor_gate;
architecture rtl of nor_gate is
begin
c_o <= a_i nor b_i;
end architecture rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity nor_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity nor_gate;
architecture rtl of nor_gate is
begin
c_o <= a_i nor b_i;
end architecture rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity nor_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity nor_gate;
architecture rtl of nor_gate is
begin
c_o <= a_i nor b_i;
end architecture rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User i... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User i... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User i... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User i... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User i... |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use ieee.math_complex.all ;
architecture qpsk_tx of bladerf is
begin
end architecture ; -- arch
|
architecture RTL of FIFO is
begin
IF_LABEL : if a = '1' GENERATE
elsif b = '1' GENERATE
else GENERATE
end generate;
-- Violations below
IF_LABEL : if a = '1' GENERATE
elsif b = '1' GENERATE
else GENERATE
end generate;
end;
|
-------------------------------------------------------------------------------
-- system_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_stub is
port (
fpga_0_USB_UART_R... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:41:35 11/23/2013
-- Design Name:
-- Module Name: Special_Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:41:35 11/23/2013
-- Design Name:
-- Module Name: Special_Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 20:17:03 2017
-- Host : GILAMONSTER running 64-bit major rel... |
package pack is
type rec is record
x : integer;
end record;
type pt is protected
impure function next_id return integer;
end protected;
impure function get_rec return rec;
function get_id (r : rec) return integer;
end package;
package body pack is
type pt is protected ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ethernet_mac;
use ethernet_mac.ethernet_types.all;
use ethernet_mac.framing_common.all;
entity chips_mac_adaptor is
port(
-- Common clock for MAC and chips
clock_i : in std_ulogic;
reset_i : in std_ulogic;
-- MAC FI... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:40:41 11/01/2009
-- Design Name:
-- Module Name: module_with_fifo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--------------------------------------------------------------------------------
--
-- FileName: i2c_master.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF A... |
--------------------------------------------------------------------------------
--
-- FileName: i2c_master.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF A... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_277 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_277;
architecture augh of add_277 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_277 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_277;
architecture augh of add_277 is
signal carry_inA : std_l... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.op... |
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