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-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:55:15 2017
-- Host : GILAMONSTER running 64-bit major rel... |
library ieee;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
--use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use work.math_real.all;
library lpm;
use lpm.lpm_components.all;
entity test_module is
Generic( WIDTH_IN : integer := 8
);
Port( N : in integer; --Number
Exp : in real; --Exp... |
-- jtagtestrw.vhd
-- Generated using ACDS version 16.1 200
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity jtagtestrw is
port (
tdi : out std_logic; -- jtag.tdi
tdo : in std_logic := '0'; ... |
-- jtagtestrw.vhd
-- Generated using ACDS version 16.1 200
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity jtagtestrw is
port (
tdi : out std_logic; -- jtag.tdi
tdo : in std_logic := '0'; ... |
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- This file contains a testbench for RioPcsUart.
--
-- To Do:
-- -
--
-- Aut... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.ROCACHE_PKG.all;
-- Instruction memory for DLX
-- Memory filled by a process which reads from a file
-- file name is "test.asm.mem"
entity ROMEM is
generic (
file_path : -- string(1 t... |
------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet. Pu... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dilate_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_r... |
architecture a of e is
alias foo is bar;
alias blah : integer is boo;
alias funci is func [integer, boolean return boolean];
alias proci is proc [integer];
alias proce is proc [];
alias funce is func [return integer];
begin
end architecture;
|
architecture a of e is
alias foo is bar;
alias blah : integer is boo;
alias funci is func [integer, boolean return boolean];
alias proci is proc [integer];
alias proce is proc [];
alias funce is func [return integer];
begin
end architecture;
|
architecture a of e is
alias foo is bar;
alias blah : integer is boo;
alias funci is func [integer, boolean return boolean];
alias proci is proc [integer];
alias proce is proc [];
alias funce is func [return integer];
begin
end architecture;
|
architecture a of e is
alias foo is bar;
alias blah : integer is boo;
alias funci is func [integer, boolean return boolean];
alias proci is proc [integer];
alias proce is proc [];
alias funce is func [return integer];
begin
end architecture;
|
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
END procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
var... |
----------------------------------------------------------------------
-- OscXtlCnt
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Blink 8 LEDs using external Xtal Clock.
-- Use External Xtal, adjust its signal to some MHz and
-- add a bunch of registers for th... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--This should pass
context con1 is
end context con1;
context con2 is
end context;
--This should fail
context con3 is
end;
context con4 is
end
;
-- Split declaration across lines
context
con5
is
end
context
;
|
-- Hi Emacs, this is -*- mode: vhdl -*-
----------------------------------------------------------------------------------
-- Unidirectional PS2 Interface (device -> host)
-- For connect mouse/keyboard
--
-- The PS/2 mouse and keyboard implement a bidirectional synchronous serial
-- protocol. The bus is "idle" when b... |
-------------------------------------------------------------------------------
-- Title : Synchronous FIFO
-------------------------------------------------------------------------------
-- Author : Carl Treudler (cjt@users.sourceforge.net)
-- Standard : VHDL'93/02
------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Synchronous FIFO
-------------------------------------------------------------------------------
-- Author : Carl Treudler (cjt@users.sourceforge.net)
-- Standard : VHDL'93/02
------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RegA is
port(
x: in std_logic_vector(31 downto 0);
clk: in std_logic;
y: out std_logic_vector(31 downto 0)
);
end RegA;
architecture Structural of RegA is
signal temp: std_logic_vector(31 downto 0) := X"00000000";
begin
y ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- system_microblaze_0_d_bram_ctrl_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntl... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity alu is
port (
clk: in std_logic;
rst: in std_logic;
a: in unsigned(31 downto 0);
b: in unsigned(31 downto 0);
o: out unsigned(31 downto 0);
y: out unsigned(31 downto 0);
op: i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity topo is
port ( SW : in std_logic_vector (17 downto 0);
HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7: out std_logic_vector(6 downto 0);
LEDR : out std_logic_vector (17 downto 0);
LEDG : out std... |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: debug_ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity alu is
port(
func : in std_logic_vector(3 downto 0);
busA : in std_logic_vector(15 downto 0);
busB : in std_logic_vector(15 downto 0);
inZ : in std_logic;
inS : in std_logic;
... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity alu is
port(
func : in std_logic_vector(3 downto 0);
busA : in std_logic_vector(15 downto 0);
busB : in std_logic_vector(15 downto 0);
inZ : in std_logic;
inS : in std_logic;
... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity DIVIDER_32b_4x_fast is
generic(SIZE: INTEGER := 32);
port(
reset : in STD_LOGIC;
start : in STD_LOGIC;
clk : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR((SIZE - 1) downto... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 17:57:15 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bi... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 17:57:15 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bi... |
library ieee;
use ieee.std_logic_1164.all;
entity sub is
port (
clk : out std_logic;
cnt : inout integer := 0);
end entity;
architecture test of sub is
signal clk_i : bit := '0';
signal clk_std : std_logic;
begin
clk_i <= not clk_i after 1 ns;
clk_std <= to_stdulogic(clk_i);
... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
use work.all;
use work.util.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
USE IEEE.math_real.ALL;
use work.testbench_mm_master_pkg.all;
entity stream_to_avalon_tb is
end entity;
architecture sim of stream_to_avalon_tb is
signal stream_valid : std_logic ;
... |
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <johannes@wltr.io>
--
-- Description:
-- Send data to MAX5541 DAC.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
-------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
-------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
-------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
-------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
-------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
--! @file alteraOpenmacTop-rtl-ea.vhd
--
--! @brief OpenMAC toplevel for Altera
--
--! @details This is the openMAC toplevel for Altera platform.
-------------------------------------------------------------------------------
--
-- (c) B... |
architecture rtl of fifo is
begin
x <= a AND b OR c NAND d NOR e XOR f XNOR g;
x <= a AND b OR c NAND d NOR e XOR f XNOR g;
end architecture;
|
------------------------------------------------------------------------------------------------------------------------
-- Model Title: Hall sensor
-- Entity Name: hall_sensor
-- Author: <vladimir.kolchuzhin@ieee.org>
-- Created:
-- Last update: 2020/07/08 Schaeftlarn
--
---------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity idctbuff is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra2_data : out std_logic_vector(31 downto 0);
ra2_addr : in std_logic_vector(8 downt... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity idctbuff is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra2_data : out std_logic_vector(31 downto 0);
ra2_addr : in std_logic_vector(8 downt... |
--
-- Taken from rtl/commonlib/types_util.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Pac... |
--
-- Taken from rtl/commonlib/types_util.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Pac... |
--
-- Taken from rtl/commonlib/types_util.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Pac... |
--
-- Taken from rtl/commonlib/types_util.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Pac... |
--
-- Taken from rtl/commonlib/types_util.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Pac... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_6502_defs.all;
use work.pkg_6502_decode.all;
use work.pkg_6502_opcodes.all;
use work.file_io_pkg.all;
library std;
use std.textio.all;
entity tb_decode is
end tb_decode;
architecture tb of tb_decode is
... |
library ieee;
use ieee.std_logic_1164.all;
entity conv01 is
port (i : std_logic_vector (19 downto 0);
o : out std_logic_vector (31 downto 0));
end conv01;
architecture behav of conv01 is
begin
process (i)
variable v : std_logic_vector (31 downto 0);
begin
v := (i'left downto 0 => i, others => '0... |
entity FIFO is
END entity;
entity FIFO is
END entity;
entity FIFO is
END entity;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic ( widthB : natural := 4;
widthA : natural := 4);
po... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic ( widthB : natural := 4;
widthA : natural := 4);
po... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic ( widthB : natural := 4;
widthA : natural := 4);
po... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic ( widthB : natural := 4;
widthA : natural := 4);
po... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic ( widthB : natural := 4;
widthA : natural := 4);
po... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic ( widthB : natural := 4;
widthA : natural := 4);
po... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic ( widthB : natural := 4;
widthA : natural := 4);
po... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic ( widthB : natural := 4;
widthA : natural := 4);
po... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz<
--
-- Module Name: adau1761_configuraiton_data - Behavioral
-- Description: A script for the I3C2, which sends out I2c transactions to configure
-- the ADAU1761 codec.
--
--... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz<
--
-- Module Name: adau1761_configuraiton_data - Behavioral
-- Description: A script for the I3C2, which sends out I2c transactions to configure
-- the ADAU1761 codec.
--
--... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_861 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_861;
architecture augh of cmp_861 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_861 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_861;
architecture augh of cmp_861 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
-- implementation of the HDB1 encoder.
entity hdb1_enc is
port (
clr_bar,
clk : in bit; -- clock input.
e : in bit; -- input.
s0, s1 : out bit -- output.
);
end hdb1_enc;
architecture behaviour of hdb1_enc is
signal q0, q1, q2 : bit; -- 3 flipflops for 6 states.
beg... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_2_block.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -----------------------------------... |
-- A dual-port 2KiB RAM described as recommended by Xilinx
-- (C) Copyright 2011 Christopher D. Kilgour
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License,... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
entity repro5 is
end repro5;
architecture behav of repro5 is
type my_rec is record
a : bit;
w : bit_vector (1 to 2);
end record;
procedure check (signal v : my_rec) is
begin
assert v.a = '0' and v.w = "01";
end check;
procedure pack (signal a : bit; signal w : bit_vector) is
begin
check... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ab
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:20 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:03:00 05/17/2016
-- Design Name:
-- Module Name: pUe11 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
-- $Id: tb_nx_cram_memctl.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 26.08.2016 16:22:30
-- Design Name:
-- Module Name: control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- ... |
-- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Red... |
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Red... |
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