content stringlengths 1 1.04M ⌀ |
|---|
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Red... |
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Red... |
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Red... |
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Red... |
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Red... |
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Red... |
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Red... |
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Red... |
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Red... |
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Red... |
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Red... |
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Red... |
-------------------------------------------------------------------------------
-- Title :
-------------------------------------------------------------------------------
-- File : UtilityPkg.vhd
-- Author : Kurtis Nishimura
------------------------------------------------------------------------------... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
package body fifo_pkg is
end package body fifo_pkg;
package body fifo is
end package body fifo;
|
--/*******************************************************************************
-- *
-- *
-- * File:
-- * counter.vhd
-- *
-- *
-- * Module:
-- * precise_timestamp
-- *
-- * Author:
-- * Mario Ruiz
-- *
-- *
-- * Copyright (C) 2015 - Mario Ruiz and HPCN-UAM High Performance Computing and Net... |
library ieee;
use ieee.std_logic_1164.all;
entity reg_file_tb is
end entity reg_file_tb;
architecture tb of reg_file_tb is
constant T : time := 20 ns;
constant B : integer := 16;
constant R : integer := 4;
signal clk, rst, we_l : std_logic;
signal w_data, r_data_1, r_data_2 : std_logic_vector(B-1 downto 0);
s... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... |
-------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
... |
-- Btrace 448
-- Up/down counter
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
generic(n: integer := 5);
port(clk, reset: in std_logic;
ld, up, down: in std_logic;
d: in std_logic_vector(n-1 downto 0);
q: out std_logic_vect... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mash is
generic (
g_order : positive := 2;
g_width : positive := 16 );
port (
clock : in std_logic;
enable : in std_logic := '1';
reset : in std_logic;
dac_in : in uns... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mash is
generic (
g_order : positive := 2;
g_width : positive := 16 );
port (
clock : in std_logic;
enable : in std_logic := '1';
reset : in std_logic;
dac_in : in uns... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mash is
generic (
g_order : positive := 2;
g_width : positive := 16 );
port (
clock : in std_logic;
enable : in std_logic := '1';
reset : in std_logic;
dac_in : in uns... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mash is
generic (
g_order : positive := 2;
g_width : positive := 16 );
port (
clock : in std_logic;
enable : in std_logic := '1';
reset : in std_logic;
dac_in : in uns... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mash is
generic (
g_order : positive := 2;
g_width : positive := 16 );
port (
clock : in std_logic;
enable : in std_logic := '1';
reset : in std_logic;
dac_in : in uns... |
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemen... |
library ieee;
use ieee.std_logic_1164.all;
entity output07 is
port (clk : std_logic;
i : std_logic;
o : out std_logic_vector (1 downto 0) := "10");
end output07;
architecture behav of output07 is
begin
process (clk)
begin
if rising_edge(clk) then
o (0) <= i;
o (1) <= not i;
e... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rounder is
generic(
TOTAL_BITS:natural := 23;
EXP_BITS: natural := 6
);
port (
exponent_addition_cout: in std_logic;
man_in: in std_logic_vector(TOTAL_BITS - EXP_BITS downto 0);
exp_in: in std_logic_vector(EXP_BITS - 1 downto 0)... |
-------------------------------------------------------------------------------
-- Title : Wishbone Debugger SDB descriptor
-- Project : FMC DEL 1ns 4cha-stand-alone application (fmc-delay-1ns-4cha-sa)
-------------------------------------------------------------------------------
-- File : synthesis_desc... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- $Id: rb_sres_or_3.vhd 343 2010-12-05 21:24:38Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either vers... |
-- $Id: rb_sres_or_3.vhd 343 2010-12-05 21:24:38Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either vers... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
end entity ent;
architecture arch of ent is
signal test: natural;
constant e : natural := 3;
begin
LL: case e generate
when 0 =>
when 1 to 4 =>
test <= 1;
when l5: 5 | 7=>
test <= 2;
when others =>
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
end entity ent;
architecture arch of ent is
signal test: natural;
constant e : natural := 3;
begin
LL: case e generate
when 0 =>
when 1 to 4 =>
test <= 1;
when l5: 5 | 7=>
test <= 2;
when others =>
... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Fri Jul 8 09:16:27 2016
-- Host : jalapeno running 64-bit unknown
-- C... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library ieee;
use ieee.std_logic_1164.all;
entity MulticycleCPU is
port(
clk: in std_logic;
CarryOut, Overflow: out std_logic
);
end MulticycleCPU;
architecture Behavioral of MulticycleCPU is
component PCMulticycle is
port(
clk, d: in std_logic;
AddressIn: in std_logic_vector(31 downto 0... |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity aclkout is
port(
clk : in std_logic;
ddr_clk : out std_logic;
ddr_clkn: out std_logic
);
end;
architecture rtl of aclkout is
com... |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity aclkout is
port(
clk : in std_logic;
ddr_clk : out std_logic;
ddr_clkn: out std_logic
);
end;
architecture rtl of aclkout is
com... |
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity aclkout is
port(
clk : in std_logic;
ddr_clk : out std_logic;
ddr_clkn: out std_logic
);
end;
architecture rtl of aclkout is
com... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_APB3_PPE_IF is
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
TDM_CNT : in vl_logic_vector(2 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_APB3_PPE_IF is
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
TDM_CNT : in vl_logic_vector(2 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_APB3_PPE_IF is
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
TDM_CNT : in vl_logic_vector(2 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
... |
entity bot is
generic ( N : integer );
end entity;
architecture test of bot is
constant k : integer := N;
signal x, y : natural;
begin
p1: process (y) is
begin
x <= y + 5;
end process;
p2: process is
begin
assert << constant ^.^.g(N).uut.k : integer >> = N;
<< ... |
-- ApsCmdConstants.vhd
--
-- This provides menmonic definitions for the command word fields
--
--
-- REVISIONS
--
-- 7/9/2013 CRJ
-- Created
--
-- 8/13/2013 CRJ
-- Initial release
--
-- END REVISIONS
--
library ieee;
use ieee.std_logic_1164.all;
package ApsCmdConstants is
-- Constants used in the command pa... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your opt... |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful... |
library verilog;
use verilog.vl_types.all;
entity MUX4_1_IControl is
port(
Sel : in vl_logic_vector(1 downto 0);
S0 : in vl_logic_vector(31 downto 0);
S1 : in vl_logic_vector(31 downto 0);
S2 : in vl_logic_vector(31 d... |
--------------------------------------------------------------------------------------
-- The configuration settings choose by the user are read here. If a modification is
-- detected, a configuration is started with the new values.
-- This bloc generates the triggers to acquire data at the sample rate define by use... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity CoPro6502papilio is
generic (
UseT65Core : boolean := false;
UseJensCore : boolean := false;
UseAlanDCore : boolean := true
);
port (
-- GOP Signals
fas... |
context c1 is
library ieee;
end context c1;
-- try multiline
context c1
is
library ieee;
end context c1;
context
c1
is library ieee;
end context
c1
;
context
c1
is
library ieee;
end
;
context
c1
is
library ieee;
end --comment
context
;
-- Try single line
context c1 is library ieee; use ieee.std_logic_... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
--???21EDA??
--?????:A-C8V4
--www.21eda.com
--??LED???LED??????0??????1???
--????????21EDA????????
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY LEDA is ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
... |
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
... |
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
... |
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PIT IS
PORT(
clk : in std_logic;
rst : in std_logic;
bus_dq : inout std_logic_vector(15 downto 0);
bus_rw : in std_logic;
bus_req : in std_logic;
bus_addr : in ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
package pack1 is
type ma_t is array(1 downto 0) of bit_vector(1 downto 0);
end pack1;
use work.pack1.all;
entity arraysub is
generic(par1: bit_vector(3 downto 0) := "1111");
end entity;
architecture test of arraysub is
signal s1, s2: ma_t;
begin
s1(1)<=par1(1 downto 0);
s1(0)<=par1(3 downto 2);
... |
package pack1 is
type ma_t is array(1 downto 0) of bit_vector(1 downto 0);
end pack1;
use work.pack1.all;
entity arraysub is
generic(par1: bit_vector(3 downto 0) := "1111");
end entity;
architecture test of arraysub is
signal s1, s2: ma_t;
begin
s1(1)<=par1(1 downto 0);
s1(0)<=par1(3 downto 2);
... |
package pack1 is
type ma_t is array(1 downto 0) of bit_vector(1 downto 0);
end pack1;
use work.pack1.all;
entity arraysub is
generic(par1: bit_vector(3 downto 0) := "1111");
end entity;
architecture test of arraysub is
signal s1, s2: ma_t;
begin
s1(1)<=par1(1 downto 0);
s1(0)<=par1(3 downto 2);
... |
package pack1 is
type ma_t is array(1 downto 0) of bit_vector(1 downto 0);
end pack1;
use work.pack1.all;
entity arraysub is
generic(par1: bit_vector(3 downto 0) := "1111");
end entity;
architecture test of arraysub is
signal s1, s2: ma_t;
begin
s1(1)<=par1(1 downto 0);
s1(0)<=par1(3 downto 2);
... |
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 28.11.2013 13:51:50
-- Design Name:
-- Module Name: aeg1500_tb - Behavioral
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Version... |
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 28.11.2013 13:51:50
-- Design Name:
-- Module Name: aeg1500_tb - Behavioral
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Version... |
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