content stringlengths 1 1.04M ⌀ |
|---|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:28:39 03/31/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/ProjLab1/TopLevel_tb.vhd
-- Project Name: ProjLab1
-- Target Device:
-- Tool ver... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:28:39 03/31/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/ProjLab1/TopLevel_tb.vhd
-- Project Name: ProjLab1
-- Target Device:
-- Tool ver... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:28:39 03/31/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/ProjLab1/TopLevel_tb.vhd
-- Project Name: ProjLab1
-- Target Device:
-- Tool ver... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:28:39 03/31/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/ProjLab1/TopLevel_tb.vhd
-- Project Name: ProjLab1
-- Target Device:
-- Tool ver... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- test_sync.vhd
entity TEST_SYNC is
generic (
BITS : integer := 1
);
port (
I : in bit_vector(BITS-1 downto 0);
O : out bit_vector(BITS-1 downto 0)
);
end TEST_SYNC;
architecture MODEL of TEST_SYNC is
begin
O <= I;
end MODEL;
-- test_ng.vhd
entity TEST_NG is
ge... |
-- test_sync.vhd
entity TEST_SYNC is
generic (
BITS : integer := 1
);
port (
I : in bit_vector(BITS-1 downto 0);
O : out bit_vector(BITS-1 downto 0)
);
end TEST_SYNC;
architecture MODEL of TEST_SYNC is
begin
O <= I;
end MODEL;
-- test_ng.vhd
entity TEST_NG is
ge... |
architecture structure of Uart is
-- component declaration
component RxModule
generic (
MaxDataWidth : integer range 2 to 64;
MaxSpeedDividerWidth : integer;
RxFifoAdressWidth : integer range 2 to 10;
Oversampling : integer range 2 to ... |
----------------------------------------------------------------------------------
--
-- Lab session #4: screenFormat
--
-- Send the screen elements to the VGA controller
--
-- Authors:
-- David Estévez Fernández
-- Sergio Vilches Expósito
--
------------------------------------------------------------------... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--This VHDL code is part of the OZ-3, a 32-bit processor
--
--Module Title: ALU
--Module Description:
-- The Arithmetic and Logic Unit of the OZ-3. It handles two 32-bit
-- inputs and performs one of t... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package slot_bus_pkg is
type t_slot_req is record
bus_address : unsigned(15 downto 0); -- for async reads and direct bus writes
bus_rwn : std_logic; -- for async reads and writes
bus_write... |
--Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
--Date : Wed Oct 18 15:14:15 2017
--Host : TacitMonolith running 64-bit Ubuntu 16.04... |
entity UC is
port(
an_input: in bit_vector;
an_output: out bit_vector
);
end entity;
architecture test of UC is
begin
an_output <= an_input;
end architecture;
-------------------------------------------------------------------------------
entity bounds10 is
end entity;
architecture t... |
entity UC is
port(
an_input: in bit_vector;
an_output: out bit_vector
);
end entity;
architecture test of UC is
begin
an_output <= an_input;
end architecture;
-------------------------------------------------------------------------------
entity bounds10 is
end entity;
architecture t... |
entity UC is
port(
an_input: in bit_vector;
an_output: out bit_vector
);
end entity;
architecture test of UC is
begin
an_output <= an_input;
end architecture;
-------------------------------------------------------------------------------
entity bounds10 is
end entity;
architecture t... |
entity UC is
port(
an_input: in bit_vector;
an_output: out bit_vector
);
end entity;
architecture test of UC is
begin
an_output <= an_input;
end architecture;
-------------------------------------------------------------------------------
entity bounds10 is
end entity;
architecture t... |
entity UC is
port(
an_input: in bit_vector;
an_output: out bit_vector
);
end entity;
architecture test of UC is
begin
an_output <= an_input;
end architecture;
-------------------------------------------------------------------------------
entity bounds10 is
end entity;
architecture t... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ALU_tb IS
END ALU_tb;
ARCHITECTURE behavior OF ALU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
CRS1 : IN std_logic_vector(31 downto 0);
CRS2mux : IN std_logic_vector(31 downto 0);
... |
entity guard3 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of guard3 is
signal s : std_logic bus := 'H';
begin
p1: process is
begin
assert s = 'H';
s <= '0';
wait for 1 ns;
assert s = '0';
s <= null after 5 ns;
wait for 1 ns;
... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Jun 05 01:41:24 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- Hello world program
use std.textio.all; -- Imports the standard textio package.
-- Defines a design entity, without any ports.
entity hello_world is
end hello_world;
architecture behaviour of hello_world is
begin
process
variable l : line;
begin
write (l, String'("Hello world!"));
writeline (outp... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory is
generic (
WIDTH : integer );
port (
clk : in std_logic;
addr : in unsigned(7 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory is
generic (
WIDTH : integer );
port (
clk : in std_logic;
addr : in unsigned(7 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory is
generic (
WIDTH : integer );
port (
clk : in std_logic;
addr : in unsigned(7 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory is
generic (
WIDTH : integer );
port (
clk : in std_logic;
addr : in unsigned(7 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory is
generic (
WIDTH : integer );
port (
clk : in std_logic;
addr : in unsigned(7 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);... |
Library IEEE;
use IEEE.std_logic_1164.all;
entity x25_13x is
Port (
A302,A301,A300,A299,A298,A269,A268,A267,A266,A265,A236,A235,A234,A233,A232,A203,A202,A201,A200,A199,A166,A167,A168,A169,A170: in std_logic;
A74: buffer std_logic
);
end x25_13x;
architecture x25_13x_behav of x25_13x is
signal a1a,a2a,a3a,a4a,a5a,a... |
-- Copyright (C) 1991-2012 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07:57:25 09/18/2015
-- Design Name:
-- Module Name: mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Mux 4 to 1
--
-- Dependencies:
--
-... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- $Id: sys_conf2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity tb_mcu is
end tb_mcu;
architecture TB of tb_mcu is
signal rst : std_logic;
signal clk : std_logic := '0';
signal Switch : std_logic_vector(3 downto 0);
signal LED : ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:40:23 12/18/2014
-- Design Name:
-- Module Name: /home/jpiat/development/FPGA/logi-family/logi-hard/test_bench/cam_deser_4_to_pixels_tb.vhd
-- Project Name: cam_deser
-- Target Device... |
entity vhpi1 is
port (
x : in natural;
y : out natural );
end entity;
architecture test of vhpi1 is
signal v : bit_vector(3 downto 0) := "0011";
signal b : bit;
begin
p1: process (x) is
begin
report "x=" & integer'image(x);
y <= x + 1 after 1 ns;
end process;
... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : P R E D I C T I O N
--
--
-- The particles are loaded into the local RAM by the Framework... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilin... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilin... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilin... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilin... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilin... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilin... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilin... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilin... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
package ann_types is
type ann_mode is ( idle, run, learn );
end package ann_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.float_types.all;
USE work.sram_types.all;
USE work.ann_types.all;
PACKAGE ann_components IS
COMPONENT ann IS
GENERIC (
N_I : INTEGE... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--##############################################################################
-- light8080 : Intel 8080 binary compatible core
--##############################################################################
-- v1.4 (01 dec 2016) Moved to GitHub, uC extracted to separate package.
-- v1.3 (12 feb 2012) Fix: Gen... |
-------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- T... |
-------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- T... |
-------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- T... |
--------------------------------------------------------
-- Sender component for comport
-- Trigger on by send_start pulse, otherwise stays
-- idle. Currently send 8-bit data at once. The data
-- must be available during the sending.
-- States
-- STATE_IDLE
-- send_start(pulse) -> STATE_START_BIT
-- ... |
-------------------------------------------------------------------------------
-- Company : HSLU
-- Engineer : Gai, Waj
--
-- Create Date: 28-Mar-11, 21-Mar-14
-- Project : RT Video Lab 1: Exercise 1
-- Description: 5-tap FIR filter in transposed form
----------------------------------------------... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity fmc116_ltc2... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:29:47 2017
-- Host : DarkCube running 64-bit major re... |
-- Errors in context
use work.nothere.all; -- Error
package p is
constant k : mytype := myfunc; -- Error (suppressed)
end package;
package body p is
constant y : mytype := myfunc; -- Error (suppressed)
end package body;
|
package issue444 is
type rec is record
x : integer;
end record;
type rec_array is array (natural range <>) of rec;
procedure proc (x : in integer);
end package;
package body issue444 is
procedure proc (x : in integer) is
-- This uses a temporary var to initialise the array...
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may ... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Controller IS
PORT (
opcode : IN std_logic_vector(5 DOWNTO 0); -- instruction 31-26
regDst : OUT std_logic;
jump : OUT std_logic;
branch : OUT std_logic;
memRead : OUT std_logic;
memToRegister : OUT std_logic;
ALUop ... |
architecture rtl of fifo is
begin
procedure_call_label : postponed wr_en(a, b);
postponed wr_en(a, b);
wr_en(a, b);
process_label : process
begin
procedure_call_label : wr_en(a, b);
wr_en(a, b);
end process;
-- Violations below
procedure_call_label : postponed wr_en(a, b);
proce... |
library ieee;
use ieee.std_logic_1164.all;
entity foo is
port (
addr : in integer;
nibble0 : out std_logic_vector(3 downto 0);
nibble1 : out std_logic_vector(3 downto 0)
);
end foo;
architecture foo of foo is
type data_array_t is array (3 downto 0) of std_logic_vector(7 downto 0);
signal data_buf... |
--==========================================================================================================================
-- FILE NAME : issue_unit.vhd
-- DESCRIPTION : issue unit helps to issue one instruction at a time even when multiple instructions are ready to be issued.
-- the priority depends o... |
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.std_logic_textio.all;
package tbfuncs is
function Vector2String(constant V : in std_logic_vector) return string;
function Vector2String(constant V : in std_logic) return string;
impure function CheckStdLogic (
constant Value : in ... |
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.std_logic_textio.all;
package tbfuncs is
function Vector2String(constant V : in std_logic_vector) return string;
function Vector2String(constant V : in std_logic) return string;
impure function CheckStdLogic (
constant Value : in ... |
library IEEE;
use IEEE.std_logic_1164.all;
entity spi2apb is
port (
-- SPI
signal MISO : in std_logic;
signal MOSI : out std_logic;
signal SCLK : out std_logic;
signal SS_n : out std_logic;
-- APB
signal apb_select : in std_logic;
signal clk : in std_logi... |
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
end fifo_pkg;
|
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
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