content stringlengths 1 1.04M ⌀ |
|---|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
package randgen_package is
-- Declare constants
-- Number of bits used for internal register of the chaotic map
constant N_BIT : integer := 16;
-- Number of bits to skip in the output sequence
constant SKIP : integer := 3;
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity btn_ledbar is
Port (
btn : in STD_LOGIC;
reset : in STD_LOGIC;
ledA : out STD_LOGIC_VECTOR (7 downto 0)
);
end btn_ledbar;
architecture Behavioral of btn_ledbar is
-- Signals
signal amount: integer range 0 to 80;
begin
p1: process (b... |
----------------------------------------------------------------------------------
-- Responsáveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimarães
-- Ultima mod.: 03/jun/2017
-- Nome do Módulo: Registrador
-- Descrição: Registrador com largura de palavra parametrizável
-- e com habili... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_152 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_152;
architecture augh of cmp_152 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_152 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_152;
architecture augh of cmp_152 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
----------------------------------------
-- 32 BIT ALU --
-- PORT MAPPING --
-- A: 32 bit input value --
-- B: 32 bit input value --
-- CIN: 1 bit input carry --
-- FUN: 4 bit input function selector --
-- 0 - ZERO ... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--##############################################################################
-- light8080 : Intel 8080 binary compatible core
--##############################################################################
-- v1.3 (12 FEB 2012) Fix: General solution to AND, OR, XOR clearing CY,ACY.
-- v1.2 (08 jul 2010) Fix:... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:53:59 09/16/2014
-- Design Name:
-- Module Name: C:/temp/teeest/tb_big_little_endian.vhd
-- Project Name: teeest
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--This file describes a mux2_1
--Mario Barbareschi
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2_1 is
Port ( SEL : in STD_LOGIC;
A : in STD_LOGIC;
B : in STD_LOGIC;
X : out STD_LOGIC
);
end mux2_1;
architecture dataflow of mux2_1 is
begin
-- X <= A when ... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity for_loop is
port(
a : in std_logic_vector(7 downto 0);
Count : out std_logic_vector(2 downto 0)
);
end for_loop;
architecture behavior of for_loop is
begin
process(a)
variable Count_Aux : std_logic_vector(2 downto 0);
be... |
-------------------------------------------------------------------------------
--
-- The Program Memory control unit.
-- All operations related to the Program Memory are managed here.
--
-- $Id: pmem_ctrl-c.vhd,v 1.2 2005-06-11 10:08:43 arniml Exp $
--
-- All rights reserved
--
----------------------------------------... |
----------------------------------------------------------------------------------
-- Create Date: 16:41:34 03/11/2016
-- Design Name: Pipeline Control
-- Team: Team 5
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01... |
----------------------------------------------------------------------------------
-- Create Date: 16:41:34 03/11/2016
-- Design Name: Pipeline Control
-- Team: Team 5
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
entity flip_flop_7474 is
Port ( j: in bit);
begin
assert j'stable (6 ns);
end flip_flop_7474;
|
------------------------------------------------------------------------------
-- Testbench for the alu_or function of the zunit
--
-- Project :
-- File : tb_tstor.vhd
-- Author : Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.Types.all;
entity SramController is
generic (
AddrW : positive;
DataW : positive
);
port (
Clk : in bit1;
Rst_N : in bit1;
-- Internal interface
Addr : in word(Ad... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:49:36 09/11/2011
-- Design Name:
-- Module Name: concatenador - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencie... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_4_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:50:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author:... |
--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
-- pragma translate_off
library... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo is
generic (
FIFO_WIDTH : positive := 10;
DATA_WIDTH : positive := 32
);
port (
-- clock and reset
CLOCK : in std_logic;
RESET : in std_logic;
-- fifo input interface
DAT_I : in std_logic_vector(D... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo is
generic (
FIFO_WIDTH : positive := 10;
DATA_WIDTH : positive := 32
);
port (
-- clock and reset
CLOCK : in std_logic;
RESET : in std_logic;
-- fifo input interface
DAT_I : in std_logic_vector(D... |
-------------------------------------------------------------------------------
-- $Id: axi_emc.vhd
-------------------------------------------------------------------------------
-- axi_emc.vhd - Entity and architecture
-------------------------------------------------------------------------------
-------------------... |
-------------------------------------------------------------------------------
-- $Id: axi_emc.vhd
-------------------------------------------------------------------------------
-- axi_emc.vhd - Entity and architecture
-------------------------------------------------------------------------------
-------------------... |
-------------------------------------------------------------------------------
-- $Id: axi_emc.vhd
-------------------------------------------------------------------------------
-- axi_emc.vhd - Entity and architecture
-------------------------------------------------------------------------------
-------------------... |
-------------------------------------------------------------------------------
-- $Id: axi_emc.vhd
-------------------------------------------------------------------------------
-- axi_emc.vhd - Entity and architecture
-------------------------------------------------------------------------------
-------------------... |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity train11_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end train11_hot;
architecture behaviour of train11_hot is
constant st0: std_logic_vector(10 down... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev580 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
me... |
library ieee;
use ieee.std_logic_1164.all;
entity aggr03 is
port (a : std_logic_vector (7 downto 0);
b : out std_logic_vector (7 downto 0));
end aggr03;
architecture rtl of aggr03 is
signal r : std_logic_vector (7 downto 0);
begin
b <= r or a;
r <= (7 downto 2 => '0', others => '1');
end rtl;
|
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is dis... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is dis... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is dis... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is dis... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is dis... |
--- Projekt: INP 1 - Maticovy displej
--- Autor: Frantisek Kolacek (xkolac12@stud.fit.vutbr.cz)
--- Datum: 28. 10. 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- Definice rozhrani pro praci s maticovym displejem
entity ledc8x8 is
port (... |
-----------------------------------------------------------------------------
-- Definition of a single port ROM for RATASM defined by prog_rom.psm
--
-- Generated by RATASM Assembler
--
-- Standard IEEE libraries
--
-----------------------------------------------------------------------------
--------------... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
-------------------------------------
-- Hex display controller --
-- PORT MAPPING --
-- Value : 4 bit input value --
-------------------------------------
-- OUT : 7 bit output value --
-------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY he... |
architecture RTL of ENT is
begin
end RTL;
architecture RTL of ENT is
begin
end RTL;
architecture RTL of ENT is
begin
end;
architecture RTL of ENT is
begin
end ;
architecture RTL of ENT is
begin
end
;
architecture RTL of ENT is
begin
end--Comment
;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
entity Task1_ent_tb2 is
end entity Task1_ent_tb2;
architecture Task1_arch_tb2 of Task1_ent_tb2 is
constant delay_wr_in : Time := 5 ns;
consta... |
-- ALUNOS:
-- Bruno Luiz da Silva
-- Gustavo Fernades
--
--
-- TÍTULO:
-- Consumo instantâneo de combustível
--
--
-- RESUMO:
-- Calculará o consumo instantâneo de combustível de um carro
--
--
-- ENTRADAS/SAÍDAS (I/O):
-- (I) SW: oito chaves, cada uma de um bit, onde serão inseridos os dados (multiplicando, multiplica... |
library ieee;
use ieee.UPF.all;
entity test is
end entity;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.CONSTANTS.all;
use work.CONFIG_MANDELBROT.all;
use IEEE.NUMERIC_STD.ALL;
entity FSM is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
b_done : in STD_LOGIC_VECTOR (7 downto 0);
stop : in std_logic;
doneVGA : in std_logic;
start : out STD_LOGIC;
start... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tbfuncs.all;
entity ByteRegister_tb is
end ByteRegister_tb;
architecture behavior of ByteRegister_tb is
component ByteRegister
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
D_i : in std_logic_vector(7 downt... |
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provid... |
--------------------------------------------------------------------------------
-- Title : Module for interrupt generation, synchronized to clk
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : interrupt_core.vhd
-- Author : Susanne ... |
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisim_VPKG.vhd,v 1.19 2010/12/08 18:25:32 fphillip Exp $
----------------------------------------------------------------
--
-- Created by the Synopsys Library Compiler v3.4b
-- FILENAME : unisim_VPKG.vhd
-- FILE CONTENTS: VITAL Table, he... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity maw is
generic (
-- window width is 2^depth
depth : integer;
input_bit_width : integer
);
port (
clk_i , rst_i : in std_logic;
value_i : in unsigned ( input_bit_width-1 downto 0 );
-- the oup... |
------------------------------------------------------------------------------
--
-- File: DPTI_to_AXI_S_converter.vhd
-- Author: Sergiu Arpadi
-- Original Project: AXI DPTI
-- Date: 8 June 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent In... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:06:03 10/20/11
-- Design Name:
-- Module Name: Binary Counter. 8 bits. Reset asinc. Clock enable.
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- D... |
library verilog;
use verilog.vl_types.all;
entity Bcd2digitAdder_vlg_check_tst is
port(
finalCarry : in vl_logic;
result : in vl_logic_vector(7 downto 0);
sampler_rx : in vl_logic
);
end Bcd2digitAdder_vlg_check_tst;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-- use ieee.numeric_std.all;
-- use ieee.std_logic_unsigned.all;
entity issue352 is
end entity;
architecture arch of issue352 is
signal FixRealKCM_F400_uid2_Rtemp : std_logic_vector(4 downto 0) := "11111";
signal R :std_logic_vector(5 ... |
architecture rtl of fifo is
begin
process begin
loop end LOOP;
LOOP END LOOP;
end process;
end;
|
library verilog;
use verilog.vl_types.all;
entity AddrDecM3 is
port(
addr : in vl_logic_vector(31 downto 0);
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
COM_MASTERENABLE: in vl_logic;
addrDec : out vl_logic_vector(8 downto 0)
);
end AddrDec... |
library verilog;
use verilog.vl_types.all;
entity AddrDecM3 is
port(
addr : in vl_logic_vector(31 downto 0);
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
COM_MASTERENABLE: in vl_logic;
addrDec : out vl_logic_vector(8 downto 0)
);
end AddrDec... |
library verilog;
use verilog.vl_types.all;
entity AddrDecM3 is
port(
addr : in vl_logic_vector(31 downto 0);
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
COM_MASTERENABLE: in vl_logic;
addrDec : out vl_logic_vector(8 downto 0)
);
end AddrDec... |
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : io_ctrl_.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 18:24:55 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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