content stringlengths 1 1.04M ⌀ |
|---|
-- Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:15:11
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER is
port (
height : out std_logic_vector(15 downto 0); ... |
-- Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:15:11
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER is
port (
height : out std_logic_vector(15 downto 0); ... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF1_3_block3.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ---------------------------------... |
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:39:47 01/18/2015
-- Design Name:
-- Module Name: C:/Users/Angel LM/Desktop/Frecuencimetroo 6.0/Frecuencimentro/PrePresentacion_TB.vhd
-- Project Name: Frecuencimentro
-- Targe... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:39:47 01/18/2015
-- Design Name:
-- Module Name: C:/Users/Angel LM/Desktop/Frecuencimetroo 6.0/Frecuencimentro/PrePresentacion_TB.vhd
-- Project Name: Frecuencimentro
-- Targe... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PIPO4 is
Port ( Rin: in STD_LOGIC_VECTOR (3 downto 0);
CLK,Preset,Clear: in STD_LOGIC;
Rout : out STD_LOGIC_VECTOR (3 downto 0));
end PIPO4;
architecture PIPO4_arch of PIPO4 is
component DFF_PC
port(D,CLK,Preset,Clear: in STD_LOGIC; Q,Qnot: o... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 08 17:42:47 2017
-- Host : GILAMONSTER running 64-bit major rel... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:40:32 02/20/2017
-- Design Name:
-- Module Name: C:/ANDREStemp/LabElecDig/Detector_De_Pulso/Detectordepulso_TB.vhd
-- Project Name: Detector_De_Pulso
-- Target Device:
-- Tool versi... |
library IEEE;
use IEEE.std_logic_1164.all;
package tube_comp_pack is
component tube port (
h_addr : in std_logic_vector(2 downto 0);
h_cs_b : in std_logic;
h_data_in : in std_logic_vector(7 downto 0);
h_data_out : out std_logic_vector(7 downto 0);
h_phi2 : in std_logic;
h_rdn... |
library IEEE;
use IEEE.std_logic_1164.all;
package tube_comp_pack is
component tube port (
h_addr : in std_logic_vector(2 downto 0);
h_cs_b : in std_logic;
h_data_in : in std_logic_vector(7 downto 0);
h_data_out : out std_logic_vector(7 downto 0);
h_phi2 : in std_logic;
h_rdn... |
library IEEE;
use IEEE.std_logic_1164.all;
package tube_comp_pack is
component tube port (
h_addr : in std_logic_vector(2 downto 0);
h_cs_b : in std_logic;
h_data_in : in std_logic_vector(7 downto 0);
h_data_out : out std_logic_vector(7 downto 0);
h_phi2 : in std_logic;
h_rdn... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2019 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.synt... |
-- megafunction wizard: %ALTDDIO_OUT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTDDIO_OUT
-- ============================================================
-- File Name: altddio_out1.vhd
-- Megafunction Name(s):
-- ALTDDIO_OUT
--
-- Simulation Library Files(s):
-- altera_mf
-- =======================... |
-- megafunction wizard: %ALTDDIO_OUT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTDDIO_OUT
-- ============================================================
-- File Name: altddio_out1.vhd
-- Megafunction Name(s):
-- ALTDDIO_OUT
--
-- Simulation Library Files(s):
-- altera_mf
-- =======================... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:25:25 10/17/2014
-- Design Name:
-- Module Name: roulette - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/13 08:21:52
-- Nombre del módulo: clk4Hz - Behavioral
-- Comentarios adicionales:
-- Implementación de forma exacta, a c... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/13 08:21:52
-- Nombre del módulo: clk4Hz - Behavioral
-- Comentarios adicionales:
-- Implementación de forma exacta, a c... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Divisor is
Port ( clk : in STD_LOGIC;
newC : out STD_LOGIC);
end Divisor;
architecture Behavioral of Divisor is
--signal aux: integer range 0 to 433; --115200 (433, 217)
--signal aux: integer range 0 to 2603; --192... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TripleWordVoter is
port(
clk : in ST... |
------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx BRAM ----
---- ----
----... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mod10 is
Port ( outp : out std_logic_vector(3 downto 0);
dir : in std_logic;
carry: out std_logic;
clr : in std_logic;
clk : in std_logic);
end mod10;
architectur... |
-------------------------------------------------------------------------------
--
-- T410/411 ROM.
--
-- $Id: t410_rom-struct-a.vhd,v 1.1 2006-06-05 22:44:29 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms... |
architecture RTL of FIFO is
constant c_width : integer := 16;
constant c_depth : integer := 512;
constant c_word :integer := 1024;
begin
end architecture RTL;
|
architecture RTL of FIFO is
function func_1 (a : integer) return integer;
function func_2 (b : integer) return integer;
begin
OUT1 <= func_1;
PROC1 : process () is
begin
sig1 <= func_1;
sig2 <= func_1(a) or func_2(b);
sig3 <= func_1 or func_2;
end process;
end architecture RTL;
|
------------------------------------------------------------------------------
--
-- File: Ps2InterfaceWrapper.vhd
-- Author: Sergiu Arpadi
-- Original Project: AXI PS2
-- Date: 10 October 2017
--
-------------------------------------------------------------------------------
--Copyright (c) 2017 Digilent
--
--Permiss... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_134 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_134;
architecture augh of add_134 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_134 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_134;
architecture augh of add_134 is
signal carry_inA : std_l... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
entity driver14 is
end entity;
architecture test of driver14 is
type rec is record
x, y : natural;
end record;
type rec_array is array (natural range <>) of rec;
function resolved (x : rec_array) return rec is
begin
return x(0); -- Returns pointer to its argume... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CNT_V is
Generic(clk_divisor: natural);
Port(clk : in std_logic;
reset : in std_logic;
q_o : out std_logic);
end CNT_V;
architecture behv of CNT_V is
--components
--constants
--signals
signal q: std_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CNT_V is
Generic(clk_divisor: natural);
Port(clk : in std_logic;
reset : in std_logic;
q_o : out std_logic);
end CNT_V;
architecture behv of CNT_V is
--components
--constants
--signals
signal q: std_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CNT_V is
Generic(clk_divisor: natural);
Port(clk : in std_logic;
reset : in std_logic;
q_o : out std_logic);
end CNT_V;
architecture behv of CNT_V is
--components
--constants
--signals
signal q: std_... |
-------------------------------------------------------------------------------
--
-- T410 system toplevel.
--
-- $Id: t410-c.vhd,v 1.1 2006-06-11 22:18:28 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, w... |
------------------------------------------------------------------------------
-- Title : Wishbone BPM SWAP flat interface
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
--------------... |
-----------------------------------------------------------------------------------------------------------
--
-- DENORMALS HANDLER
--
-- Created by Claudio Brunelli, 2004
--
-----------------------------------------------------------------------------------------------------------
--Copy... |
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the follow... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) status control register
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permi... |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) status control register
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permi... |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) status control register
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permi... |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) status control register
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permi... |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) status control register
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permi... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity tb_aggr03 is
end tb_aggr03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_aggr03 is
signal a, b : std_logic_vector(7 downto 0);
begin
dut: entity work.aggr03
port map (a, b);
process
begin
a <= x"ff";
wait for 1 ns;
assert b = x"ff" severity failure;
a <= x"e... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14.09.2016 21:11:45
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
--
-- Description: Entirely combinational, and all operations a... |
-------------------------------------------------------------------------------
-- axi_sg_updt_q_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All righ... |
-------------------------------------------------------------------------------
-- axi_sg_updt_q_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All righ... |
-------------------------------------------------------------------------------
-- axi_sg_updt_q_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All righ... |
-------------------------------------------------------------------------------
-- axi_sg_updt_q_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All righ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 00:02:33 2017
-- Host : Juice-Laptop running 64-bit majo... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 00:02:33 2017
-- Host : Juice-Laptop running 64-bit majo... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
Library ieee;
Use ieee.std_logic_1164.all;
Entity REG is
Generic ( n : integer := 16);
port(
Clock,Reset: in std_logic;
d : in std_logic_vector(n-1 downto 0);
R1_Out, R2_Out : out std_logic_vector(15 downto 0);
w_en : in std_logic ;--write enable
Rout,R1,R2 : in std_logic_vector(2 downto 0);--
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiply_add_GNKLXFKAO3 is
generic ( family : string := "Cyclone V";
direction : strin... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiply_add_GNKLXFKAO3 is
generic ( family : string := "Cyclone V";
direction : strin... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiply_add_GNKLXFKAO3 is
generic ( family : string := "Cyclone V";
direction : strin... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiply_add_GNKLXFKAO3 is
generic ( family : string := "Cyclone V";
direction : strin... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiply_add_GNKLXFKAO3 is
generic ( family : string := "Cyclone V";
direction : strin... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiply_add_GNKLXFKAO3 is
generic ( family : string := "Cyclone V";
direction : strin... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiply_add_GNKLXFKAO3 is
generic ( family : string := "Cyclone V";
direction : strin... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiply_add_GNKLXFKAO3 is
generic ( family : string := "Cyclone V";
direction : strin... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 08-02-2016
-- Module Name: halfaddr.vhd
--------------------------------------------------------------------------------
use IEEE;
library IEEE.std_logic_1164... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
-- Date : Mon Mar 24 13:58:19 2014
-- Host : macbook running 64-bit Arc... |
-- Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
-- Date : Mon Mar 24 13:58:19 2014
-- Host : macbook running 64-bit Arc... |
-- Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
-- Date : Mon Mar 24 13:58:19 2014
-- Host : macbook running 64-bit Arc... |
-- Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
-- Date : Mon Mar 24 13:58:19 2014
-- Host : macbook running 64-bit Arc... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 18/03/2015
--! Module Name: EPROC_OUT8
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use ... |
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