content stringlengths 1 1.04M ⌀ |
|---|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------------------------------
-- light8080_tb_pkg.vhdl -- Support package for Light8080 TBs.
--
-- Contains procedures and functions used to dump CPU traces, etc.
--
-- Please see the LICENSE file in the project root for license matters.
-------------------------------... |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: COUNTER_TIMEOUT.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ==========================... |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: COUNTER_TIMEOUT.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ==========================... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- $Id: tb_w11a_br_arty.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_w11a_br_arty
-- Description: Configurat... |
library verilog;
use verilog.vl_types.all;
entity endian_controller is
port(
iSRC_MASK : in vl_logic_vector(3 downto 0);
iSRC_DATA : in vl_logic_vector(31 downto 0);
oDEST_MASK : out vl_logic_vector(3 downto 0);
oDEST_DATA : out vl_logic_vector(31 ... |
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute it and/or modify
-- it... |
entity repro2 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Test case architecture
architecture func of repro2 is
signal s : std_logic := 'Z';
procedure write (signal s : inout std_logic) is
begin
null;
end write;
begin
b: block
port (s1 : out std_logic := ... |
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_core.vhd,v 1.1 2005/02/18 15:30:21 wirthlin Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- ... |
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_core.vhd,v 1.1 2005/02/18 15:30:21 wirthlin Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- ... |
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_core.vhd,v 1.1 2005/02/18 15:30:21 wirthlin Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- ... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "checksum"
-- Project :
-------------------------------------------------------------------------------
-- File : checksum_tb.vhd
-- Author : <sheac@DRESDEN>
-- Company :
-- Cr... |
-- fft_helpers.vhd
--
-- Created on: 13 Jul 2017
-- Author: Fabian Meyer
--
-- This package provides a complex datatype and associated helper functions
-- for easier computation of a FFT. Operations are implemented using fixed
-- point arithmetic.
--
-- This code is mostly based on the sample provided by vapin, but... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.Numeric_std.all;
entity reg_x is
port(
clk : in std_logic;
rst_n : in std_logic;
sel : in std_logic;
w_enable : in std_logic;
r_enable : in std_logic;
d_in : in std_logic_vector(31 downto 0);
d_out : out std_logic_vector(31 downto 0)... |
--------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core ... |
--------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core ... |
------------------------------------------------------------------------------
-- uart_cntrl.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHER... |
----------------------------------------------------
------------------CODE FOR upCOUNTER------------------
----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MOD16UP is
port(CLK: in std_logic;
reset: in std_logic;
Q... |
-- $Id: tb_tst_rlink_n4.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_rlink_n4
-- Description: Config... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:47:36 11/21/2016
-- Design Name:
-- Module Name: shiftRegister8Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
--CODE
-------------------------------------------------------------------------------------------------
-- Author: Mickael Carl
-- Date: 2015-04-02
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--C... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;
entity FrameBuffer is
Port ( inX : in STD_LOGIC_VECTOR (9 downto 0);
inY : in STD_LOGIC_VECTOR (8 downto 0);
outX : in STD_LOGIC_VECTOR (9 downto 0);
outY : in ST... |
library ieee;
use ieee.std_logic_1164.all;
use work.common.all;
use work.id_pkg.all;
entity instruction_decoder is
port (d : in id_in;
q : out id_out); -- decoded data
end entity instruction_decoder;
architecture behavioral of instruction_decoder is
-----------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use work.common.all;
use work.id_pkg.all;
entity instruction_decoder is
port (d : in id_in;
q : out id_out); -- decoded data
end entity instruction_decoder;
architecture behavioral of instruction_decoder is
-----------------------------------... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This fil... |
library verilog;
use verilog.vl_types.all;
entity Game_vlg_sample_tst is
port(
Clk : in vl_logic;
Rb : in vl_logic;
Reset : in vl_logic;
sampler_tx : out vl_logic
);
end Game_vlg_sample_tst;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_with_checkers_top is
port (
-- flow control
credit_in_N, credit_in_E, ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_with_checkers_top is
port (
-- flow control
credit_in_N, credit_in_E, ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_with_checkers_top is
port (
-- flow control
credit_in_N, credit_in_E, ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
-- Con celda y sin maquina de estados
--------------------------------------------------------
-- x^131 + x^8 + x^3 + x^2 + 1
entity serial_multipl... |
-- 32-bit testing circuit
-- this circuit performs comparisons between one or two operands (greater than, less than, equal, zero)
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity tester_32_bit is
port (
-- input... |
-------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 04
-- Project :
-------------------------------------------------------------------------------
-- File : multi_port_adder.vhd
-- Author : Tuomas Huuki, Jonas Nikula
-- Company : TUT
-- C... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:29:02 11/11/2015
-- Design Name:
-- Module Name: control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY cpu_core_testbranch_tb IS
END cpu_core_testbranch_tb;
ARCHITECTURE behavior OF cpu_core_testbranch_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cpu_core
GENERIC( instruction_file : string);
P... |
-- Single clock - Dual port block RAM
-- Heavily inspired from
-- http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity block_ram is
generic(
DATA_WIDTH: integer := 8;
ADDR_WIDTH: integer := 10
);
po... |
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use work.custom_pkg.all;
ENTITY prediction_tb IS
END prediction_tb;
ARCHITECTURE behavior OF prediction_tb IS
-- Component Declaration
COMPONENT prediction
port
(clk : in std_logic;
... |
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_Std.all;
entity bit_AddDiv1 is
port
(
denominator : out std_logic_vector(15 downto 0) := "0000000000110100";
out_bus : out std_logic_vector(15 downto 0);
in_Bus : in std_logic_vector(... |
-- Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
--... |
--This should pass
context c1 is
end context c1;
--This should fail
context c1 is
end context c1;
context c1 is
end context c1;
context c1 is
end context c1;
--This should pass
context c1 is
end context c1;
-- Split declaration across lines
context
c1
is
end
context
c1
;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:29:49 2017
-- Host : DarkCube running 64-bit major releas... |
-------------------------------------------------------------------------------
-- axi_datamover_cmd_status.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_cmd_status.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_cmd_status.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_cmd_status.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
----------------------------------------------------------------------
-- brdConst_pkg (for Fusion Advanced Dev Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Package to declare board specific constants.
--
-- LEDs & PushButton SW polarity XOR constants
-- ... |
-------------------------------------------------------------------------------
-- $Id: ipif_pkg.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- IPIF Common Library Package
----------------------------------------------------------------... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
-- Title : Motor control for BLDC and DC motors
-- Project : Loa
-------------------------------------------------------------------------------
-- File : motor_control_pkg.vhd
-- Author : Fabian Greif <fabian.greif@rwth-... |
-------------------------------------------------------------------------------
-- Title : Motor control for BLDC and DC motors
-- Project : Loa
-------------------------------------------------------------------------------
-- File : motor_control_pkg.vhd
-- Author : Fabian Greif <fabian.greif@rwth-... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/20/2017 02:26:29 PM
-- Design Name:
-- Module Name: m_clk_sync - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/20/2017 02:26:29 PM
-- Design Name:
-- Module Name: m_clk_sync - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
add_i : add
generic map (
WIDTH => WIDTH,
HEIGHT => HEIGHT
)
port map (
clk => clk,
in => in,
output => output
);
|
entity test is begin end;
|
entity test is begin end;
|
-- --------------------------------------------------------------------
--
-- Copyright 2002 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE [Draft] Standard 1076.3
-- reduce_pkg
-- This source file may not be copied, sold, or included
-- with software that is sold without wr... |
-------------------------------------------------------------------------------
-- UART
-- Implements a universal asynchronous receiver transmitter
-------------------------------------------------------------------------------
-- clock
-- Input clock, must match frequency value given on clock_frequency
-- ge... |
-- A2601 Main Core
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any later vers... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity NIB2_7SEG_SRC is
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity NIB2_7SEG_SRC is
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity NIB2_7SEG_SRC is
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity NIB2_7SEG_SRC is
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity NIB2_7SEG_SRC is
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity NIB2_7SEG_SRC is
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_nmsuppression is
generic (
ROW_WIDTH : integer := 5
);
port (
clk : in std_logic;
enable : in std_logic;
active : in std_logic;
x_addr_in : in std_logic_vector(9 downto 0);
y_addr... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_nmsuppression is
generic (
ROW_WIDTH : integer := 5
);
port (
clk : in std_logic;
enable : in std_logic;
active : in std_logic;
x_addr_in : in std_logic_vector(9 downto 0);
y_addr... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_nmsuppression is
generic (
ROW_WIDTH : integer := 5
);
port (
clk : in std_logic;
enable : in std_logic;
active : in std_logic;
x_addr_in : in std_logic_vector(9 downto 0);
y_addr... |
library verilog;
use verilog.vl_types.all;
entity stratixii_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
enable_dpa_mode : string := "OFF";
data_align_rollover: vl_notype;
lose_lock_on_one_change: string := "OFF";
reset... |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential... |
-- NEED RESULT: ARCH00047.P1: Implicit array subtype conversion occurs for simple names passed
-- NEED RESULT: ARCH00047.P2: Implicit array subtype conversion occurs for simple names passed
-- NEED RESULT: ARCH00047.P3: Implicit array subtype conversion occurs for simple names passed
-- NEED RESULT: ARCH00047.P4: Im... |
-- Copyright (c) 2009 Frank Buss (fb@frank-buss.de)
-- See license.txt for license
--
-- Simple RS232 receiver with generic, baudrate and 8N1 mode.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE work.all;
entity rs232_receiver is
generic(
-- clock frequency, in hz
SYSTEM_SPEED,
-- ... |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
... |
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_b
--
-- Generated
-- by: wig
-- on: Thu Oct 13 08:24:14 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../intra.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll1.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ==================================... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Testbench for ParallelPolyphase
-- Initial version: Colm Ryan (cryan@bbn.com)
-- Create Date: 05/05/2015
-- Dependencies:
--
--
----------------------------------------------------------------------------------
library IEEE;
use I... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
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