content stringlengths 1 1.04M ⌀ |
|---|
-- NEED RESULT: ARCH00315: Process with Sens List and End Label passed
-- NEED RESULT: ARCH00315: Process has no process declarative items in itsdeclarative part passed
-- NEED RESULT: ARCH00315: Process with Sens List and No End Label passed
-- NEED RESULT: ARCH00315: Process has no process declarative items in its... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
architecture RTL of FIFO is
alias ident : std_logic_vector(3 downto 0) is write_enable [name1, name2 return integer];
alias ident : std_logic_vector(3 downto 0) is write_enable [name1, name2];
alias ident : std_logic_vector(3 downto 0) is write_enable [return integer];
alias ident : std_logic_vector(3 ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity extractor is
port (
ext_in:in std_logic_vector(47 downto 0 );
ext_out:out std_logic_vector(22 downto 0 )
);
end extractor ;
architecture behaviour of extractor is
begin
process (ext_in)
begin
if (ext_in(... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versi... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Vers... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
entity sub1 is
end entity;
architecture a of sub1 is
begin
end architecture;
-------------------------------------------------------------------------------
entity sub2 is
end entity;
architecture a of sub2 is
begin
end architecture;
-------------------------------------------------------------------------------
... |
----------------------------------------------------------------------------------------------
--
-- Generated by X-HDL Verilog Translator - Version 4.0.0 Apr. 30, 2006
-- Wed Jun 17 2009 01:00:48
--
-- Input file : /home/samsonn/SandBox_LBranch_11.2/env/Databases/ip/src2/L/mig_v3_2/data/dlib/virtex6/ddr3_sdr... |
-------------------------------------------------------------------------------
-- TESTBENCH_standalone.vhd
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_standalone.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-----------------------... |
-------------------------------------------------------------------------------
-- TESTBENCH_standalone.vhd
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_standalone.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-----------------------... |
-------------------------------------------------------------------------------
-- TESTBENCH_standalone.vhd
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_standalone.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-----------------------... |
library verilog;
use verilog.vl_types.all;
entity dps is
port(
iCLOCK : in vl_logic;
iDPS_BASE_CLOCK : in vl_logic;
inRESET : in vl_logic;
iDPS_IRQ_CONFIG_TABLE_REQ: in vl_logic;
iDPS_IRQ_CONFIG_TABLE_ENTRY: in vl_logic_vector(1 downto 0);... |
A15 - LED_1
A14 - LED_2
A13 - LED_3
A12 - LED_4
E17 - LED_5
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
entity ent is
port (
i : in bit;
i2 : bit;
o : out bit
);
end ent;
architecture a of ent is
begin
o <= i or i2;
end;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_a
--
-- Generated
-- by: wig
-- on: Thu Feb 10 18:56:39 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -nodelta ../../typecast.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
termi... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - ... |
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 09:01:29 10/06/2015
-- Design Name:
-- Module Name: Counter_0_to_19 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Des... |
-- SKIP because sb $v0, $gp; sb $v1, $gp doesn't read $v0's value back
-- This is the top level MIPS architecture
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.txt_utils.all;
entity mips_vga_tb is
end;
architecture struct of mips_vga_tb is
component regFile is
port (
... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 -... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library src;
use src.depp_pkg.all;
use src.bus_pkg.all;
package depp_tb_pkg is
type depp_slave_state_type is record
address : bus_address_type;
writeData : bus_data_type;
readData : bus_data_type;
... |
-- test1 - leds showing state of ring counter controlled by quadrature decoder
-- Written in 2016 by <Ahmet Inan> <xdsopl@googlemail.com>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is d... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: dsp_block - Behavioral
-- Description: Where you can put your own processing of the audio stream
---------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: dsp_block - Behavioral
-- Description: Where you can put your own processing of the audio stream
---------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: dsp_block - Behavioral
-- Description: Where you can put your own processing of the audio stream
---------------------------------------------------------------... |
architecture rtl of fifo is
begin
process begin
report "Something" &
"Something Else" &
"Yet another thing"
severity WARNING;
end process;
end architecture rtl;
|
--!
--! @file: example9_2.vhd
--! @brief: function in package
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
library work;
use work.my_package.all;
--------------------------------------
entity organiz... |
-- Generic accumulator
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;
LIBRARY work;
ENTITY Generic_accumulator IS
GENERIC (N : integer := 8);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DIN... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY HeadFieldExtractor IS
PORT(
din_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
din_last : IN STD_LOGIC;
din_ready : OUT STD_LOGIC;
din_valid : IN STD_LOGIC;
dout_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAM_7.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ====================... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.numeric_bit.all;
entity xnor_gate is
port (
a_i : in bit; -- inputs
b_i : in bit;
c_o : out bit -- output
);
end entity xnor_gate;
architecture rtl of xnor_gate is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library IEEE;
use IEEE.numeric_bit.all;
entity xnor_gate is
port (
a_i : in bit; -- inputs
b_i : in bit;
c_o : out bit -- output
);
end entity xnor_gate;
architecture rtl of xnor_gate is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library IEEE;
use IEEE.numeric_bit.all;
entity xnor_gate is
port (
a_i : in bit; -- inputs
b_i : in bit;
c_o : out bit -- output
);
end entity xnor_gate;
architecture rtl of xnor_gate is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library IEEE;
use IEEE.numeric_bit.all;
entity xnor_gate is
port (
a_i : in bit; -- inputs
b_i : in bit;
c_o : out bit -- output
);
end entity xnor_gate;
architecture rtl of xnor_gate is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RAM_64K is
port (
clk : in std_logic;
we_uP : in std_logic;
ce : in std_logic;
addr_uP : in std_logic_vector (15 downto 0);
D_uP : in std_logic_vector (7 downto 0);
... |
--Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2017.4.1 (win64) Build 2117270 Tue Jan 30 15:32:00 MST 2018
--Date : Wed Apr 4 00:27:52 2018
--Host : varun-laptop running 64-bit Service Pac... |
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
lib... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
library work;
use work.tl_string_util_pkg.all;
library std;
use std.textio.all;
entity mblite_simu is
end entity;
architecture test of mblite_simu is
... |
----------------------------------------------------------------------------------------------
-- This file is part of mblite_ip.
--
-- mblite_ip is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either versio... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.3 (lin64) Build 1034051 Fri Oct 3 16:31:15 MDT 2014
-- Date : Sun Oct 25 15:42:23 2015
-- Host : arthas-ubuntu running 64-bit Ubuntu ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32 -- Comment
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
GENERIC(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32) -... |
------------------------------------------------------------------------
-- CPE 133 VHDL File: sseg_dec.vhd
-- Description: Special seven segment display driver;
--
-- two special inputs:
--
-- VALID: if valid = 0, four dashes will be display
-- if valid = 1, decimal number appears on display
--
-- ... |
----------------------------------------------------------------------------------
-- Thibault Bailly
--
-- create date: 07-03-2017
-- design name:
-- module name: arch_generic_One_Detect_Edge
-- description: Generic
--
-- dependencies:
--
-- revision: Initial release
--
-- additional comments:
--
--
--
-- parame... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use s... |
architecture rtl of fifo is
begin
process is begin
exit;
exit;
exit_label : exit;
exit_label : exit;
end process;
end architecture rtl;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
package pvz_objects is
constant N: integer := 5;
constant M: integer := 9;
type plant is record
plant_type: std_logic_vector(1 downto 0); -- 00: peashooter; 01: wallnut; 10: sunflower
hp: std_logic_vector(3 downto 0); -- 植物血量
pea: integer r... |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien ... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity somador is port(
x,y : in std_logic_vector(15 downto 0);
result : out std_logic_vector(15 downto 0)
);
end somador;
architecture hardware of somador is begin
result <= x + y;
end hardware;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, eithe... |
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, eithe... |
--------------------------------------------------------------------------------
-- Company: <Mehatronika>
-- Author: <Aleksandr Gudilko>
-- Email: gudilkoalex@gmail.com
--
-- File: Decoder_1hot_3-to-8.vhd
-- File history:
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
-- ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien ... |
--------------------------------------------------------------------------------
-- Entity: amd_flash
-- Date:2018-08-12
-- Author: gideon
--
-- Description: Emulation of AMD flash, in this case 29F040 (512K)
-- This is a behavioral model of a Flash chip. It does not store the actual data
-- The 'allow_write' si... |
--*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual prope... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity scf_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(26 downto 0);
output: out std_logic_vector(55 downto 0)
);
end scf_rnd;
architecture behaviour of scf_rnd is
constant state1: std_logic_vector(6 downto 0) :=... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.Font.all;
entity top is
Port (
vgaRed : out std_logic_vector (3 downto 0);
vgaGreen : out std_logic_vector (3 downto 0);
vgaBlue : out... |
--==============================================================================
-- File: data_path.vhd
-- Author: Pietro Lorefice
--==============================================================================
-- Description:
-- Datapath portion of the FSMD processor architecture. It's the core of the
-- processo... |
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