content stringlengths 1 1.04M ⌀ |
|---|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual pr... |
-- debugreg.vhd
-- very simple readable and adressable 64 bit (2x 32 bit)
-- purpose: debug output
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity debugreg is
port (
clk : in std_logic;
rst_n : in std_logic;
bus_addr : in std_logic_vector(2 downto 0);
bus_da... |
-- debugreg.vhd
-- very simple readable and adressable 64 bit (2x 32 bit)
-- purpose: debug output
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity debugreg is
port (
clk : in std_logic;
rst_n : in std_logic;
bus_addr : in std_logic_vector(2 downto 0);
bus_da... |
-- debugreg.vhd
-- very simple readable and adressable 64 bit (2x 32 bit)
-- purpose: debug output
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity debugreg is
port (
clk : in std_logic;
rst_n : in std_logic;
bus_addr : in std_logic_vector(2 downto 0);
bus_da... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 09:04:41 2017
-- Host : Shaun running 64-bit major release ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 09:04:41 2017
-- Host : Shaun running 64-bit major release ... |
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT sdramcontroller
PORT(
clk : IN std_logic;
addr : IN std_logic_vector(15 downto 0);
cmd : IN std_logic_vector(1 downto 0);
d... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For TDP
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
package pack3 is
type int_vector is array (natural range <>) of integer;
type rec is record
x : integer;
y : integer;
a : int_vector(1 to 3);
z : integer;
end record;
constant r : rec;
end package;
package body pack3 is
constant r : rec := (1, 2, (3, 4, 5), 6);
end... |
library verilog;
use verilog.vl_types.all;
entity magnitude is
port(
clk : in vl_logic;
Y0 : in vl_logic_vector(11 downto 0);
Y1 : in vl_logic_vector(11 downto 0);
Y2 : in vl_logic_vector(11 downto 0);
Y3 ... |
library verilog;
use verilog.vl_types.all;
entity magnitude is
port(
clk : in vl_logic;
Y0 : in vl_logic_vector(11 downto 0);
Y1 : in vl_logic_vector(11 downto 0);
Y2 : in vl_logic_vector(11 downto 0);
Y3 ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:15:05 12/09/2014
-- Design Name:
-- Module Name: Bus_Breakout_4S4B - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:21:09 02/26/2014
-- Design Name:
-- Module Name: Z:/Source/Effects/EffectEcho_tb.vhd
-- Project Name: Soundbox_ISE
-- Target Device:
-- Tool versions:
-- Description:
--
-- VH... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
entity SINGLE_SRL is
generic (SRL_WIDTH : integer := 24);
port (
clk : in std_logic;
inp : in std_logic;
outp : out std_logic);
end SINGLE_SRL;
architecture beh of SINGLE_SRL is
signal shift_reg : std_logic_vector (SRL_WIDTH-1 downto 0);
b... |
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: divider_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
------------------------------------------------... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk512_jed is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk512_jed;
architecture behaviour of dk512_jed is
constant state_1: std_logic_vector(3 downto ... |
entity issue70 is
end;
architecture test of issue70 is
procedure my_write(value : in bit_vector) is
variable s: bit_vector(1 to value'length);
variable m: bit_vector(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := m(i);
end loop;
w... |
entity issue70 is
end;
architecture test of issue70 is
procedure my_write(value : in bit_vector) is
variable s: bit_vector(1 to value'length);
variable m: bit_vector(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := m(i);
end loop;
w... |
entity issue70 is
end;
architecture test of issue70 is
procedure my_write(value : in bit_vector) is
variable s: bit_vector(1 to value'length);
variable m: bit_vector(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := m(i);
end loop;
w... |
entity issue70 is
end;
architecture test of issue70 is
procedure my_write(value : in bit_vector) is
variable s: bit_vector(1 to value'length);
variable m: bit_vector(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := m(i);
end loop;
w... |
entity issue70 is
end;
architecture test of issue70 is
procedure my_write(value : in bit_vector) is
variable s: bit_vector(1 to value'length);
variable m: bit_vector(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := m(i);
end loop;
w... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
----------------------------------------------------------------------------------------------------
-- serial_multiplier.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Projec... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.types.all;
use work.common.all;
use work.interfaces.all;
entity cpu is
port(clk : in std_logic;
reset : in std_logic);
end entity;
architecture rtl of cpu is
component alu is
port( ... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
term... |
-------------------------------------------------------------------------------
-- $Id: gen_srlfifo.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
-------------------------------------------------------------------------------
-- srl_fifo.vhd - Entity and architecture
--
-- (c) Copyright [2003] - [2010] Xilinx, Inc. All... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
----------------------------------------------------------------------------------
-- Testbench for Audiointerface for Zedboard
--
-- Stefan Scholl, DC9ST
-- Microelectronic Systems Design Research Group
-- TU Kaiserslautern
-- 2014
----------------------------------------------------------------------------------
-- T... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
term... |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity VectorRegister is
generic (
wordLength : natural := 8
);
port (
input : in std_logic_vector(wordLength-1 downto 0);
output : out std_logic_vector(wordLength-1 downto 0);
clk : in std_logic;
reset : in std_logic
) ;
end enti... |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity VectorRegister is
generic (
wordLength : natural := 8
);
port (
input : in std_logic_vector(wordLength-1 downto 0);
output : out std_logic_vector(wordLength-1 downto 0);
clk : in std_logic;
reset : in std_logic
) ;
end enti... |
-------------------------------------------------------------------------------
-- $Id: priority_register_logic.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- OPB Arbiter - Priority Register Logic
----------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: priority_register_logic.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- OPB Arbiter - Priority Register Logic
----------------------------------------... |
-- tb_Gray_Binarization.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.12.15:50:58
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_Gray_Binarization is
end entity tb_Gray_Binarization;
architecture rtl of tb_Gray_Binarization is
component Gray_Binarization_GN is
port (
... |
-- tb_Gray_Binarization.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.12.15:50:58
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_Gray_Binarization is
end entity tb_Gray_Binarization;
architecture rtl of tb_Gray_Binarization is
component Gray_Binarization_GN is
port (
... |
--************************************************************************
--
-- Copyright (C) August Schwerdfeger
-- September 30, 2015
--
--************************************************************************
-- This program is free software: you can redistribute it and/or modify--
-- it under the terms of the ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package idram_utils is
function log2(
N : integer)
return integer;
function log2_f(
N : integer)
return integer;
function conditional (
a : boolean;
if_true : in integer;
if_false : in integer)
return... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_b_e
--
-- Generated
-- by: wig
-- on: Mon Oct 10 12:25:03 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $... |
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemen... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Sun Oct 4 21:52:20 2015
-- Host : cascade.andrew.cmu.edu running 64-bi... |
architecture RTL of FIFO is
begin
process
variable var1 : integer := 0; -- Comment 1
file file1 : load_file_file open read_mode is load_file_name; -- Comment 2
constant con1 : std_logic := '1'; -- Comment 3
begin
end process... |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity ClockDecimator is
generic (
wordLength : natural := 8;
divider : natural := 2
);
port (
input : in std_logic_vector(wordLength-1 downto 0);
output : out std_logic_vector(wordLength-1 downto 0);
reset : in std_logic;
clk : ... |
-- wasca.vhd
-- Generated using ACDS version 14.1 186 at 2015.05.28.08:37:08
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_toplevel is
port (
clk_clk : in std_logic := '0'; -- clk.... |
-- wasca.vhd
-- Generated using ACDS version 14.1 186 at 2015.05.28.08:37:08
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_toplevel is
port (
clk_clk : in std_logic := '0'; -- clk.... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_FG_Solving_Key_Equation_4
-- Module Name: Controller_FG_Solving_Key_... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, eithe... |
entity guard2 is
end entity;
architecture test of guard2 is
type int_vec is array (natural range <>) of integer;
function resolved (x : int_vec) return integer is
begin
return x'length;
end function;
subtype rint is resolved integer;
signal vbus : rint bus;
signal vreg : rint re... |
entity e is
end entity e;
architecture test of e is
begin
test : process is
type frequency is range -2147483647 to 2147483647 units KHz;
MHz = 1000 KHz;
GHz = 1000 MHz;
end units;
begin
assert frequency'image(2 MHz) = "2000 khz"; -- this should work, but GHDL produces an err... |
entity e is
end entity e;
architecture test of e is
begin
test : process is
type frequency is range -2147483647 to 2147483647 units KHz;
MHz = 1000 KHz;
GHz = 1000 MHz;
end units;
begin
assert frequency'image(2 MHz) = "2000 khz"; -- this should work, but GHDL produces an err... |
entity e is
end entity e;
architecture test of e is
begin
test : process is
type frequency is range -2147483647 to 2147483647 units KHz;
MHz = 1000 KHz;
GHz = 1000 MHz;
end units;
begin
assert frequency'image(2 MHz) = "2000 khz"; -- this should work, but GHDL produces an err... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:06 10/20/2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity psr is
Port(
clk : in std_logic;
reset : in std_logic;
nzvc : in std_logic_vector(3 downto 0);... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:13:08 09/03/2013
-- Design Name:
-- Module Name: clock_divider - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- R... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.MATH_REAL.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : L I K E L I H O O D
--
--
-- One observation and the reference da... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-- file: design_1_clk_wiz_1_0.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclai... |
-- file: design_1_clk_wiz_1_0.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclai... |
library verilog;
use verilog.vl_types.all;
entity WB_STAGE is
port(
pipeline_reg_in : in vl_logic_vector(36 downto 0);
Reg_write_en : out vl_logic;
Reg_write_dest : out vl_logic_vector(2 downto 0);
Reg_write_data : out vl_logic_vector(15 downto 0)
);
end WB_STAG... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:09:52 02/06/2016
-- Design Name:
-- Module Name: rs232 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
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