content stringlengths 1 1.04M ⌀ |
|---|
--
--
-- register at offset 0 is timebase. read- and writeable
-- reguster at offset 1 is control register. not yet used.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_v2_00_a;
--use proc_common_v2_00_a.proc_common_pkg.all;
--use proc_common_v2_00_a.ipif_pkg.all;
--libr... |
--
--
-- register at offset 0 is timebase. read- and writeable
-- reguster at offset 1 is control register. not yet used.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_v2_00_a;
--use proc_common_v2_00_a.proc_common_pkg.all;
--use proc_common_v2_00_a.ipif_pkg.all;
--libr... |
library verilog;
use verilog.vl_types.all;
entity DSSAB is
generic(
DAC_RESOLUTION : integer := 0
);
port(
DIGEN0 : in vl_logic;
DIGEN1 : in vl_logic;
DIGEN2 : in vl_logic;
DIGEN3 : in vl_logic;
DIGEN4 ... |
library verilog;
use verilog.vl_types.all;
entity DSSAB is
generic(
DAC_RESOLUTION : integer := 0
);
port(
DIGEN0 : in vl_logic;
DIGEN1 : in vl_logic;
DIGEN2 : in vl_logic;
DIGEN3 : in vl_logic;
DIGEN4 ... |
library verilog;
use verilog.vl_types.all;
entity DSSAB is
generic(
DAC_RESOLUTION : integer := 0
);
port(
DIGEN0 : in vl_logic;
DIGEN1 : in vl_logic;
DIGEN2 : in vl_logic;
DIGEN3 : in vl_logic;
DIGEN4 ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/15/2015 03:27:35 PM
-- Design Name:
-- Module Name: invShiftRows - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/15/2015 03:27:35 PM
-- Design Name:
-- Module Name: invShiftRows - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2013 Tobias Gubener --
-- ... |
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2013 Tobias Gubener --
-- ... |
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Entity Display Is
Port (
counting_i: In std_logic_vector (23 downto 0);
blink_i: In std_logic;
out0_o: Out std_logic_vector (6 downto 0);
out1_o: Out std_logic_vector (3 downto 0);
out2_o: Out std_logic_vector (3 downto 0);
out3_o... |
-------------------------------------------------------------------------------
-- Title : Components package (generated by Emacs VHDL Mode 3.33.6)
-- Project : Loa
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Components package (generated by Emacs VHDL Mode 3.33.6)
-- Project : Loa
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of ... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_368 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_368;
architecture augh of mul_368 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_368 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_368;
architecture augh of mul_368 is
signal tmp_res : signed(... |
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Softw... |
-- modem_transmissao.vhd
--
-- componente que modela a transmissao de dados do modem
-- => usar para os testes de simulacao do projeto final
--
-- ATENCAO:
-- mudar comentarios nas linhas 90 ou 91 para selecionar contagem de atraso do CTS (sintese vs simulacao)
--
-- Labdig (3o quadrimestre de 2017)
library ... |
architecture RTL of FIFO is begin end architecture RTL;
architecture RTL of FIFO is begin end architecture RTL;
architecture RTL of FIFO is begin end architecture RTL;
-- This should fail
architecture RTL of FIFO is
signal a : std_logic;
begin
a <= b after 1 ns;
end architecture RTL;
-- This should not fail
arch... |
architecture RTL of FIFO is begin end architecture RTL;
architecture RTL of FIFO is begin end architecture RTL;
architecture RTL of FIFO is begin end architecture RTL;
-- This should fail
architecture RTL of FIFO is
signal a : std_logic;
begin
a <= b after 1 ns;
end architecture RTL;
-- This should not fail
arch... |
architecture RTL of FIFO is begin end architecture RTL;
architecture RTL of FIFO is begin end architecture RTL;
architecture RTL of FIFO is begin end architecture RTL;
-- This should fail
architecture RTL of FIFO is
signal a : std_logic;
begin
a <= b after 1 ns;
end architecture RTL;
-- This should not fail
arch... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Dec 25 17:16:48 2016
-- Host : KLight-PC running 64-bit major relea... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mode_decoder is
generic(
N: integer:= 6;
M: integer:= 3;
W: integer:= 8
);
port(
clk: in std_logic := '0';
char_in: in std_logic_vector(7 downto 0) := (others => '0');
RxRdy: in std_logic := '0';
mode: out std_logic_vector(1... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:49:41 01/18/2015
-- Design Name:
-- Module Name: C:/Users/Angel LM/Documents/Frecuencimetroo/Frecuencimentro/SalidaPrePresentacion_TB.vhd
-- Project Name: Frecuencimentro
-- T... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:49:41 01/18/2015
-- Design Name:
-- Module Name: C:/Users/Angel LM/Documents/Frecuencimetroo/Frecuencimentro/SalidaPrePresentacion_TB.vhd
-- Project Name: Frecuencimentro
-- T... |
-----------------------------------------
-- Autores: Vinicius Cerutti e Yuri Bittencourt
-- Disciplina: Organização e arquitetura de Computadores II
-- T1 - Comunicação Serial Periférico-Processador
-- Parte da lógica de cola que tem como objetivo de mapear os
-- endereços do periferico junto com os da mémoria
-----... |
-- Vhdl test bench created from schematic C:\Users\fafik\Dropbox\infa\git\ethernet\ethernet4b\ethernetRX.sch - Sat Aug 30 21:36:03 2014
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends th... |
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- ... |
------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 23:40:00 02/26/2015
-- Design Name: red_diamond_top
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- T... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:27:00 12/18/2014
-- Design Name:
-- Module Name: ultrasonic - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
library ieee;
use ieee. std_logic_1164.all;
entity sync_RS is
PORT(S: in std_logic;
R: in std_logic;
CLOCK: in std_logic;
CLR: in std_logic;
PRESET: in std_logic;
Q: out std_logic;
QN: out std_logic);
end sync_RS;
Architecture Arch_sync_RS of sync_RS is
begin
FF: process (CLOCK, CLR, PRESET)
variable x: ... |
----------------------------------------------------------------------------------
--
-- Copyright (C) 2014 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free ... |
-- NEED RESULT: ARCH00488: String and bit string literals allowed at place of one dimensional character type passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
----------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
package AlertLogPkg is
subtype AlertLogIDType is integer ;
type AlertLogIDVectorType is array (integer range <>) of AlertLogIDType ;
type AlertType is (FAILURE, ERROR, WARNING) ; -- NEVER
subtype AlertIndexType is AlertType range FAILURE to WARNING ;
type AlertCountType ... |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity sync_fifo is
generic (
DEPTH : positive := 32 ;
WIDTH : positive := 16 ;
READ_AHEAD : boolean := true
) ;
port (
areset : in std_logic ;
clock : in ... |
-------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
entity shiftMux is
port (
Shift: in ctrl_t;
reg1data : in word_t;
shamt : in word_t; -- Instruction 0-6 Zero-extended
output : out word_t
);
end entity;
architecture behav of shiftMux is... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_574 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_574;
architecture augh of sub_574 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_574 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_574;
architecture augh of sub_574 is
signal carry_inA : std_l... |
entity atod is
end atod;
architecture behav of atod is
type real_array is array (natural range <>) of real;
constant csts : real_array :=
(1.0,
0.0,
-- Corner cases from
-- http://www.exploringbinary.com/
-- decimal-to-realing-point-needs-arbitrary-precision/
7.8459735791271921e6... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s510_hot is
port(
clock: in std_logic;
input: in std_logic_vector(18 downto 0);
output: out std_logic_vector(6 downto 0)
);
end s510_hot;
architecture behaviour of s510_hot is
constant s000000: std_logic_vector(46 downto 0... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- A Generic timer with a 40 bit natural number as input.
--
-- entity name: g23_generic_timer
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; ca.desalaberry@mail.mcgill.ca,
-- Graham Ludwinski; graham.ludwinski@mail.mcgill.ca
--
-- Date: 27/02/20... |
-- A Generic timer with a 40 bit natural number as input.
--
-- entity name: g23_generic_timer
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; ca.desalaberry@mail.mcgill.ca,
-- Graham Ludwinski; graham.ludwinski@mail.mcgill.ca
--
-- Date: 27/02/20... |
-- A Generic timer with a 40 bit natural number as input.
--
-- entity name: g23_generic_timer
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; ca.desalaberry@mail.mcgill.ca,
-- Graham Ludwinski; graham.ludwinski@mail.mcgill.ca
--
-- Date: 27/02/20... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk15_jed is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(4 downto 0)
);
end dk15_jed;
architecture behaviour of dk15_jed is
constant state1: std_logic_vector(1 downto 0) :... |
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the ... |
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:39:23 08/26/2016
-- Design Name:
-- Module Name: C:/Users/Yoshio/git/ecorun/ecorun_fi_hardware/fi_timer/FiTimer/TestPulseTimer.vhd
-- Project Name: FiTimer
-- Target Device:
-- Tool... |
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- filtering_algorithm_wrapper - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
---------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
entity generic_counter_tb is
end;
architecture generic_counter_tb_func of generic_counter_tb is
signal rst_in: std_logic:='1';
signal ena_in: std_logic:='0';
signal clk_in: std_logic:='0';
signal n_out: std_logic_vector(3 downto 0);
signal c_out: std_logic:='... |
entity case10 is
end entity;
architecture test of case10 is
type my_enum is (a, b, c);
signal e : my_enum;
signal i : natural;
begin
update: process (i) is
begin
case i is
when my_enum'pos(a) => e <= a;
when my_enum'pos(b) => e <= b;
when my_enum'pos(c)... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_165 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_165;
architecture augh of add_165 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_165 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_165;
architecture augh of add_165 is
signal carry_inA : std_l... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:19:44 04/12/2016
-- Design Name:
-- Module Name: /home/tj/Desktop/UMD_RISC-16G5/ProjectLab2/HardwareTestPart2/Lab04/Shado_Reg_tb.vhd
-- Project Name: Lab04
-- Target Device:
-- Tool... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:19:44 04/12/2016
-- Design Name:
-- Module Name: /home/tj/Desktop/UMD_RISC-16G5/ProjectLab2/HardwareTestPart2/Lab04/Shado_Reg_tb.vhd
-- Project Name: Lab04
-- Target Device:
-- Tool... |
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_core.vhd,v 1.1 2005/02/17 20:29:34 crh Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filen... |
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_core.vhd,v 1.1 2005/02/17 20:29:34 crh Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filen... |
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_core.vhd,v 1.1 2005/02/17 20:29:34 crh Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filen... |
-- safe_path for SinDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE SinDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END SinDPStratixVf400_safe_path;
PACKAGE body SinDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
-- safe_path for SinDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE SinDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END SinDPStratixVf400_safe_path;
PACKAGE body SinDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
-- safe_path for SinDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE SinDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END SinDPStratixVf400_safe_path;
PACKAGE body SinDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
-- safe_path for SinDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE SinDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END SinDPStratixVf400_safe_path;
PACKAGE body SinDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
-- safe_path for SinDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE SinDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END SinDPStratixVf400_safe_path;
PACKAGE body SinDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
-- safe_path for SinDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE SinDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END SinDPStratixVf400_safe_path;
PACKAGE body SinDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
-- safe_path for SinDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE SinDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END SinDPStratixVf400_safe_path;
PACKAGE body SinDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
-- safe_path for SinDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE SinDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END SinDPStratixVf400_safe_path;
PACKAGE body SinDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
-- safe_path for SinDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE SinDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END SinDPStratixVf400_safe_path;
PACKAGE body SinDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
-- safe_path for SinDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE SinDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END SinDPStratixVf400_safe_path;
PACKAGE body SinDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN... |
--////////////////////// IIR_Biquad_II /////////////////////////////////--
-- ***********************************************************************
-- FileName: IIR_Biquad_II.vhd
-- FPGA: Xilinx Spartan 6
-- IDE: Xilinx ISE 13.1
--
-- HDL IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND... |
--////////////////////// IIR_Biquad_II /////////////////////////////////--
-- ***********************************************************************
-- FileName: IIR_Biquad_II.vhd
-- FPGA: Xilinx Spartan 6
-- IDE: Xilinx ISE 13.1
--
-- HDL IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND... |
--////////////////////// IIR_Biquad_II /////////////////////////////////--
-- ***********************************************************************
-- FileName: IIR_Biquad_II.vhd
-- FPGA: Xilinx Spartan 6
-- IDE: Xilinx ISE 13.1
--
-- HDL IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND... |
--////////////////////// IIR_Biquad_II /////////////////////////////////--
-- ***********************************************************************
-- FileName: IIR_Biquad_II.vhd
-- FPGA: Xilinx Spartan 6
-- IDE: Xilinx ISE 13.1
--
-- HDL IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND... |
-------------------------------------------------------------------------------
-- Title : Data bus muxer
-- Project : Cache implementations
-------------------------------------------------------------------------------
-- File : data_t_mux.vhd
-- Author : Robert Jarzmik <robert.jarzmik@free.fr>
-- ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
entity command_interface is
port (
clock : in std_logic;
reset : in std_logic;
-- C64 side interface
slot_req : i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
entity command_interface is
port (
clock : in std_logic;
reset : in std_logic;
-- C64 side interface
slot_req : i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
entity command_interface is
port (
clock : in std_logic;
reset : in std_logic;
-- C64 side interface
slot_req : i... |
-- file: clk_32to960_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to960_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to960_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to960_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to960_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to960_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to960_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to960_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to960_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to960_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to960_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.