content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity v_split1 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end v... |
-------------------------------------------------------------------------------
--
-- File: EEPROM_8b.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digil... |
-------------------------------------------------------------------------------
--
-- File: EEPROM_8b.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digil... |
-------------------------------------------------------------------------------
--
-- File: EEPROM_8b.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digil... |
-------------------------------------------------------------------------------
--
-- File: EEPROM_8b.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digil... |
-------------------------------------------------------------------------------
--
-- File: EEPROM_8b.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digil... |
-------------------------------------------------------------------------------
--
-- File: EEPROM_8b.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digil... |
-------------------------------------------------------------------------------
--
-- File: EEPROM_8b.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digil... |
-------------------------------------------------------------------------------
--
-- File: EEPROM_8b.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digil... |
-------------------------------------------------------------------------------
--
-- File: EEPROM_8b.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digil... |
-------------------------------------------------------------------------------
--
-- File: EEPROM_8b.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digil... |
-------------------------------------------------------------------------------
--
-- File: EEPROM_8b.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digil... |
-------------------------------------------------------------------------------
--
-- File: EEPROM_8b.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digil... |
-------------------------------------------------------------------------------
--
-- File: EEPROM_8b.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digil... |
-------------------------------------------------------------------------------
--
-- File: EEPROM_8b.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digil... |
-------------------------------------------------------------------------------
--
-- File: EEPROM_8b.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digil... |
----------------------------------------------------------------------
-- File Downloaded from http://www.nandland.com
----------------------------------------------------------------------
-- This file contains the UART Transmitter. This transmitter is able
-- to transmit 8 bits of serial data, one start bit, one sto... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and ... |
-- NEED RESULT: ARCH00359.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00359: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00359: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport ... |
-----------------------------------------------------------------------------
-- LEON3 Zedboard Demonstration design
-- Copyright (C) 2012 Fredrik Ringhage, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyrigh... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
--**********************************************************************************************
-- JTAG TAP controller SM
-- Version 0.2
-- Modified 14.06.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IE... |
--**********************************************************************************************
-- JTAG TAP controller SM
-- Version 0.2
-- Modified 14.06.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IE... |
--**********************************************************************************************
-- JTAG TAP controller SM
-- Version 0.2
-- Modified 14.06.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IE... |
--**********************************************************************************************
-- JTAG TAP controller SM
-- Version 0.2
-- Modified 14.06.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IE... |
package body dosomething is
procedure dosomething_c_hello (
constant r : in dosomething_t);
attribute foreign of dosomething_c_hello : procedure is "VHPIDIRECT dosomething_c_hello";
procedure dosomething_c_hello (
constant r : in dosomething_t) is
begin
assert false se... |
package body dosomething is
procedure dosomething_c_hello (
constant r : in dosomething_t);
attribute foreign of dosomething_c_hello : procedure is "VHPIDIRECT dosomething_c_hello";
procedure dosomething_c_hello (
constant r : in dosomething_t) is
begin
assert false se... |
library ieee;
use ieee.std_logic_1164.all;
entity rejestr is
generic
(
);
port
(
reset: in std_logic;
data: inout std_logic_vector(7 downto 0);
ag: out std_logic_vector(7 downto 0);
ctrl: in std_logic_vector(7 downto 0)
);
end rejestr;
architecture bhv of rejestr is
signal value: std_logic_vector(7 d... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the entity and architecture of the
--! the base crossbar component of the Plasma-SoC's
--! AXI Crossbar.
-------------------------------------------------------
library ieee;
use ieee.std_lo... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07:23:48 01/07/2014
-- Design Name:
-- Module Name: C:/Users/hamster/Projects/FPGA/adau1761_test/tb_adau1761_test.vhd
-- Project Name: adau1761_test
-- Target Device:
-- Tool ... |
-- megafunction wizard: %ALTERA_FP_FUNCTIONS v17.0%
-- GENERATION: XML
-- fp_mul.vhd
-- Generated using ACDS version 17.0 595
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fp_mul is
port (
clk : in std_logic := '0'; -- clk.clk
areset : in std... |
package simple is
procedure test_add2;
procedure test_fact;
procedure test_sum;
procedure test_int_image;
procedure test_sqrt;
end package;
package body simple is
function add2 (n : integer) return integer is
begin
return n + 2;
end function;
procedure test_add2 is
... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versi... |
library IEEE;
use IEEE.std_logic_1164.all;
-- Test bench for Sigasi Tutorial Project.
entity testbench is
end entity testbench;
architecture STR of testbench is
signal data_out : std_logic_vector(7 downto 0);
signal data_in : std_logic_vector(7 downto 0);
signal valid : std_logic;
signal start : std_logic;... |
library IEEE;
use IEEE.std_logic_1164.all;
-- Test bench for Sigasi Tutorial Project.
entity testbench is
end entity testbench;
architecture STR of testbench is
signal data_out : std_logic_vector(7 downto 0);
signal data_in : std_logic_vector(7 downto 0);
signal valid : std_logic;
signal start : std_logic;... |
-- ============================================================
-- File Name: binding.vhd
-- ============================================================
-- ************************************************************
-- THIS IS A AUTO-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 2.0 BUILD. GENERATED ON 2016-1... |
----------------------------------------------------------------------------------
-- Устройство: имитатор клавиатуры. Принимает скан код от клиента,
-- преобразовует его в сигналы ps/2 и передает в пользовательский код.
-- Код: 0x06
----------------------------------------------------------------------------------
li... |
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... |
----- LIBRARIES -----
LIBRARY ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity shift_div is
port ( SW : in std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(4 downto 0)
);
end shift_div;
architecture shift of shift_div is
begin
--process(SW)
-- begin
-- if(SW(5) = '1')then -... |
-- $Id: ibdr_lp11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2009-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version... |
component limbus is
port (
clk_100_clk : in std_logic := 'X'; -- clk
reset_100_reset_n : in std_logic := 'X'; -- reset_n
tristate_conduit_bridge_s... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-----------------------------------------------------------------------------------------------------------
--
-- INTERNAL RESULTS PACKING (AND ROUNDING) LOGIC
--
-- Created by Claudio Brunelli, 2004
--
-----------------------------------------------------------------... |
----------------------------------------------------------------------
--- Processor
----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
entity processor is
port (
rst : in std_logic;
ck : in std_l... |
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of PORTLIST_i_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 18:36:53 2007
-- cmd: /home/wig/work/MIX/mix_0.pl -report portlist ../../portlist.xls
--
-- !!! Do not edit this file! Autogenerated by MIX ... |
library verilog;
use verilog.vl_types.all;
entity dps_irq is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iDPS_IRQ_CONFIG_TABLE_REQ: in vl_logic;
iDPS_IRQ_CONFIG_TABLE_ENTRY: in vl_logic_vector(1 downto 0);
iDPS_IRQ_CONFIG_TABLE_FLAG_MAS... |
library verilog;
use verilog.vl_types.all;
entity Input_Display_vlg_check_tst is
port(
adder1_hex_display: in vl_logic_vector(15 downto 0);
adder2_hex_display: in vl_logic_vector(15 downto 0);
sum : in vl_logic_vector(23 downto 0);
sampler_rx : in vl_... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Mar 28 02:08:39 2017
-- Host : DESKTOP-B1QME94 running 64-bit major... |
entity simple is
end;
architecture behav of simple is
begin
process
begin
report "hello";
assert false report "SUCESS";
end process;
end behav;
|
entity simple is
end;
architecture behav of simple is
begin
process
begin
report "hello";
assert false report "SUCESS";
end process;
end behav;
|
----------------------------------------------------------------------------------
--This is the main state machine of the serdes FPGA
--it generates the appropriate command
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.nume... |
architecture RTL of FIFO is
begin
process
begin
a <= b;
end process;
-- Violations below
process
begin
a <= b;
end process;
end architecture RTL;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity t is
end t1;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:18:15 10/30/2014
-- Design Name:
-- Module Name: /home/stephen/projects/hardware/hdmilight/fpga/test_configRam.vhd
-- Project Name: hdmilight
-- Target Device:
-- Tool versions:
-... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:53:14 05/24/2014
-- Design Name:
-- Module Name: /media/DATA42/Dropbox/EmbeddedRetina/embeddedretina_ise/tb_DescriptorMaker.vhd
-- Project Name: EmbeddedRetina_ISE
-- Target Device: ... |
-------------------------------------------------------------------------------
-- File Name : HostBFM.vhd
--
-- Project : JPEG_ENC
--
-- Module : HostBFM
--
-- Content : Host BFM (Xilinx OPB v2.1)
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
--------------------------... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/Complex3Multiply_block10.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -----------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity buffered_spi is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
avalon_read : in STD_LOGIC;
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity buffered_spi is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
avalon_read : in STD_LOGIC;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.VITAL_Primitives.all;
use work.DE2_CONSTANTS.all;
entity DE2Component is
port (
KEY : in std_logic_vector (3 downto 0); --Buttons
SW : in std_logic_vector (7 downto 0); -- Switches
CLOCK_50 : in std_logic; -- 50 MHz Cl... |
----------------------------------------------------------------------------------
-- Author: Osowski Marcin
-- Create Date: 16:19:05 05/24/2011
--
-- Description: This entity delays given signal of width signal_width by n clock cycles.
-------------------------------------------------------------------------------... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_7_e
--
-- Generated
-- by: wig
-- on: Wed Nov 30 06:48:17 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------------------------------------
entity Gate_NAND is
Port
(
A : in STD_LOGIC;
B : in STD_LOGIC;
Z : out STD_LOGIC
);
end Gate_NAND;
-------------------------------------------------------... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Thu Jun 29 16:41:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VH... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
----------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
----------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
----------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
----------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
----------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
----------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
----------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
----------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
----------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
----------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
----------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
----------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
----------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
----------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
----------------------------------------------... |
-- Version: v11.4 SP1 11.4.1.17
library ieee;
use ieee.std_logic_1164.all;
library igloo;
use igloo.all;
entity vga_controller is
port( vga_controller_0_row_0 : out std_logic_vector(9 downto 1);
vga_controller_0_column_0 : out std_logic_vector(9 downto 0);
h_sync_c : o... |
-------------------------------------------------------------------------------
-- bfm_monitor_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_monitor_bfm_v1_00_a;
use plb_mon... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -------------------------------------------------------------
--
-- Generated Configuration for vgca
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id... |
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