content stringlengths 1 1.04M ⌀ |
|---|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:17:10 11/17/2013
-- Design Name:
-- Module Name: C:/Users/etingi01/Mips32_948282/My_Or_tb_948282.vhd
-- Project Name: Mips32_948282
-- Target Device:
-- Tool versions:
-- Descript... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Write port
in_stb : in std_logic;
in_ack : out std_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Write port
in_stb : in std_logic;
in_ack : out std_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Write port
in_stb : in std_logic;
in_ack : out std_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Write port
in_stb : in std_logic;
in_ack : out std_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Write port
in_stb : in std_logic;
in_ack : out std_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Write port
in_stb : in std_logic;
in_ack : out std_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Write port
in_stb : in std_logic;
in_ack : out std_... |
--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your opti... |
--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your opti... |
--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your opti... |
--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your opti... |
--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your opti... |
library ieee;
use ieee.std_logic_1164.all;
entity JK_FF is
PORT ( K: in std_logic;
J: in std_logic;
CLK: in std_logic;
CLR: in std_logic;
PRE: in std_logic;
QN: out std_logic;
Q: out std_logic);
end JK_FF... |
library verilog;
use verilog.vl_types.all;
entity priority_encoder_16 is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iRESTART : in vl_logic;
iSOURCE_VALID0 : in vl_logic;
iSOURCE_VALID1 : in vl_logic;
iSOURCE_VALID2... |
-- $Id: sys_tst_snhumanio_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_snhumanio_n4d - syn
-- Desc... |
library ieee;
use ieee.std_logic_1164.all;
entity c_or is
generic
(
width : integer := 1
);
port
(
input1 : std_logic_vector((width - 1) downto 0);
input2 : std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_or;
architecture behavior of c_or is
begin
P0... |
library ieee;
use ieee.std_logic_1164.all;
entity c_or is
generic
(
width : integer := 1
);
port
(
input1 : std_logic_vector((width - 1) downto 0);
input2 : std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_or;
architecture behavior of c_or is
begin
P0... |
-- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE transistor_test OF top_entity IS
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net3 : electrical;
terminal unnamed_net2 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- A... |
-- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE transistor_test OF top_entity IS
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net3 : electrical;
terminal unnamed_net2 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- A... |
-- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE transistor_test OF top_entity IS
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net3 : electrical;
terminal unnamed_net2 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- A... |
-- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE transistor_test OF top_entity IS
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net3 : electrical;
terminal unnamed_net2 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- A... |
-- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE transistor_test OF top_entity IS
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net3 : electrical;
terminal unnamed_net2 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- A... |
-- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE transistor_test OF top_entity IS
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net3 : electrical;
terminal unnamed_net2 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- A... |
-- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE transistor_test OF top_entity IS
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net3 : electrical;
terminal unnamed_net2 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- A... |
-- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE transistor_test OF top_entity IS
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net3 : electrical;
terminal unnamed_net2 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- A... |
-- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE transistor_test OF top_entity IS
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net3 : electrical;
terminal unnamed_net2 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- A... |
-- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE transistor_test OF top_entity IS
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net3 : electrical;
terminal unnamed_net2 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- A... |
-- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE transistor_test OF top_entity IS
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net3 : electrical;
terminal unnamed_net2 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- A... |
-- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE transistor_test OF top_entity IS
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net3 : electrical;
terminal unnamed_net2 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- A... |
-- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE transistor_test OF top_entity IS
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net3 : electrical;
terminal unnamed_net2 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- A... |
LIBRARY IEEE;
USE IEEE.std_logic_1164ALL;
ENTITY mux IS
PORT (i0, i1, i2, i3, a, b : IN std_logic;
PORT (q : OUT std_logic);
END mux;
ARCHITECTURE better OF mux IS
BEGIN
PROCESS ( i0, i1, i2, i3, a, b )
VARIABLE muxval : INTEGER;
BEGIN
muxval := 0;
IF (a = ‘1’) THEN
muxval := muxval + 1;
END IF;
IF ... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_FDET is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic;
FALL : out vl_logic
);
end F2DSS_ACE_MISC_FDET;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_FDET is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic;
FALL : out vl_logic
);
end F2DSS_ACE_MISC_FDET;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_FDET is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic;
FALL : out vl_logic
);
end F2DSS_ACE_MISC_FDET;
|
entity Controller is
port(
Rb,Reset, Eq,D7,D711,D2312,CLK:in bit;
State_debug:out integer range 0 to 3;
Sp,Roll,Win,Lose,Clear:out bit:='0');
end entity Controller;
architecture Behavior of Controller is
signal State,NextState:integer range 0 to 3:=0;
begin
State_debug<=State;
process(Rb,Reset,State)
begin
i... |
--##############################################################################
-- de1_demo.vhdl -- ION CPU demo on Terasic DE-1 Cyclone-II starter board.
--##############################################################################
-- This module is little more than a wrapper around the application entity.
-------... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity iq_decim is
generic (
DATA_SIZE : integer := 16;
AXI_SIZE : integer := 32
);
port (
clk : in std_logic;
rst : in std_logic;
start_acq : in std_logic;
decim_in : in std_logic_vector(AXI_SIZE-1 downto 0);
data_en : in std_logic... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package constants is
constant XLEN: integer := 32;
constant XLEN_ZERO: std_logic_vector(XLEN-1 downto 0) := X"00000000";
constant XLEN_ONE: std_logic_vector(XLEN-1 downto 0) := X"00000001";
constant RESET_VECTOR: std_logic_vector(XLEN-1 downto 0) := X"00000000";
constant ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Michael Jones
--
-- Create Date: 09:47:04 05/23/2013
-- Design Name:
-- Module Name: nes_ctl_3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Michael Jones
--
-- Create Date: 09:47:04 05/23/2013
-- Design Name:
-- Module Name: nes_ctl_3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_pipelined_adder_GN4HTUTWRG is
generic ( width : natural := 0;
pipeline : integer := 0)... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_pipelined_adder_GN4HTUTWRG is
generic ( width : natural := 0;
pipeline : integer := 0)... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_pipelined_adder_GN4HTUTWRG is
generic ( width : natural := 0;
pipeline : integer := 0)... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity ent is
end ent;
architecture a of ent is
signal s : string(1 to 3);
begin
s <= "abc";
process(all)
begin
case s is
when "abc" =>
when others =>
end case;
end process;
end a;
|
--
-- Copyright (c) ARMadeus Project 2009
--
-- simulation component for SN74HC594
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later... |
----------------------------------------------------------------------------------
-- Company: LBNL
-- Engineer: Yuan Mei
--
-- Create Date: 03/25/2014 07:22:25 PM
-- Design Name:
-- Module Name: sdram_buffer_fifo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Interface ... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use i... |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Entity: rom
-- Author: Waj
-- Date : 11-May-13, 26-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Program memory for simple von-Neumann MCU with registerd read da... |
---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- ... |
entity FIFO is
port (
I_WR_EN : inout std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : inout std_logic;
I_DATA : in std_logic_vector(31 downto 0);... |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... |
----------------------------------------------------------------------------------
-- Company: Universidad Complutense de Madrid
-- Engineer: TOC & TC
--
-- Create Date:
-- Design Name: Practica 2
-- Module Name: tb_muneca - beh
-- Project Name: Practica 2
-- Target Devices: Spartan-3 ... |
-- revision history:
-- 05.08.2015 Patrick Appenheimer created
-- 05.08.2015 Patrick Appenheimer testcase added
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
library WORK;
use WORK.cpu_pack.all;
entity tb_alu is
end entity tb_alu;
architecture behav_tb_alu of tb_alu is
... |
library ieee;
use ieee.std_logic_1164.all;
entity testbench is
end testbench;
architecture testbench_arch of testbench is
component testbench_recursive_stack
end component;
component testbench_pw_string
end component;
component testbench_vowels
end component;
begin
stack : testbench_recurs... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:46:39 2017
-- Host : WK117 running 64-bit major release ... |
-------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of Nios CN hostif gpio design
--
--! @details This is the toplevel of the Nios CN hostif gpio design for the
--! INK DE2-115 Evaluation Board.
--
------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_80 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_80;
architecture BEHAVIO... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
-- In this test, we declare a component in the "gates" package
-- and show that it can be referenced within the package namespace.
library ieee;
use ieee.numeric_bit.all;
package gates is
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit);
end component fa1;
end p... |
-- In this test, we declare a component in the "gates" package
-- and show that it can be referenced within the package namespace.
library ieee;
use ieee.numeric_bit.all;
package gates is
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit);
end component fa1;
end p... |
-- In this test, we declare a component in the "gates" package
-- and show that it can be referenced within the package namespace.
library ieee;
use ieee.numeric_bit.all;
package gates is
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit);
end component fa1;
end p... |
-- In this test, we declare a component in the "gates" package
-- and show that it can be referenced within the package namespace.
library ieee;
use ieee.numeric_bit.all;
package gates is
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit);
end component fa1;
end p... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Button Controller
-- Project Name: Button Controller
-- Target Devices: Spartan-3E
-- ... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017
-- Date : Fri Jun 23 10:02:11 2017
-- Host : dshwdev running 64-bit Ubuntu 16.04.... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... |
--*****************************************************************************
--* Copyright (c) 2012 by Michael Fischer. All rights reserved.
--*
--* Redistribution and use in source and binary forms, with or without
--* modification, are permitted provided that the following conditions
--* are met:
--*
--* ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/TWDLROM_3_16.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ---------------------------------... |
-------------------------------------------------------------------------------
-- axi_datamover_mm2s_dre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-- File name: aes_textio.vhd
-- Created: 2009-04-06
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: AES textio package
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
library work;
use work.numeric_std_textio... |
-- NEED RESULT: ARCH00118.P1: Multi transport transactions occurred on signal asg with indexed name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00118: One transport transaction occurred on signal asg with indexed name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00118: Old transacti... |
-------------------------------------------------------------------------------
--
-- Title : No Title
-- Design : POWERLINK
-- Author : ATSALZ137
-- Company : Bernecker + Rainer
--
-------------------------------------------------------------------------------
--
-- File : C:\mairt\... |
-------------------------------------------------------------------------------
--
-- Title : No Title
-- Design : POWERLINK
-- Author : ATSALZ137
-- Company : Bernecker + Rainer
--
-------------------------------------------------------------------------------
--
-- File : C:\mairt\... |
-------------------------------------------------------------------------------
--
-- Title : No Title
-- Design : POWERLINK
-- Author : ATSALZ137
-- Company : Bernecker + Rainer
--
-------------------------------------------------------------------------------
--
-- File : C:\mairt\... |
-------------------------------------------------------------------------------
--
-- Title : No Title
-- Design : POWERLINK
-- Author : ATSALZ137
-- Company : Bernecker + Rainer
--
-------------------------------------------------------------------------------
--
-- File : C:\mairt\... |
-------------------------------------------------------------------------------
--
-- Title : No Title
-- Design : POWERLINK
-- Author : ATSALZ137
-- Company : Bernecker + Rainer
--
-------------------------------------------------------------------------------
--
-- File : C:\mairt\... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity v_split1 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end v... |
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