content stringlengths 1 1.04M ⌀ |
|---|
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 09:01:36 11/24/2015
-- Design Name:
-- Module Name: RWM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vgaram is
Port (CLK : in STD_LOGIC;
-- sequencer port:
SeqReadEnable : in STD_LOGIC;
SeqAddr : in STD_LOGIC_VECTOR (10 downto 0);
SeqDataOut ... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of pad_pads_e
--
-- Generated
-- by: wig
-- on: Wed Jul 5 07:04:19 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author:... |
-- Generated by PERL program wishbone.pl. Do not edit this file.
--
-- For defines see wishbone.defines
--
-- Generated Sun Oct 18 18:30:29 2015
--
-- Wishbone masters:
-- mips_wbm
--
-- Wishbone slaves:
-- ram_wbs
-- baseadr 0x00000000 - size 0x00000400
-- wbs
-- baseadr 0x00000400 - size 0x00000400
----... |
-- Generated by PERL program wishbone.pl. Do not edit this file.
--
-- For defines see wishbone.defines
--
-- Generated Sun Oct 18 18:30:29 2015
--
-- Wishbone masters:
-- mips_wbm
--
-- Wishbone slaves:
-- ram_wbs
-- baseadr 0x00000000 - size 0x00000400
-- wbs
-- baseadr 0x00000400 - size 0x00000400
----... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library verilog;
use verilog.vl_types.all;
entity MEM_WB_Seg is
port(
Clk : in vl_logic;
stall : in vl_logic;
flush : in vl_logic;
MemData : in vl_logic_vector(31 downto 0);
WBData : in vl_logic_vector(31 do... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:27:35 03/11/2014
-- Design Name:
-- Module Name: nowyRXTX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:23:15 10/19/2014
-- Design Name:
-- Module Name: MIPS_sign_extender_and_shifter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
... |
-------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 ... |
-------------------------------------------------------------------------------
-- Slave Attachment - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
--!
--! @mainpage RISC-V System-on-Chip VHDL IP library
--!
--! @par Overview
--! The IP Library is an integrated set of reusable IP cores, designed for
--! system-on-chip (SOC) development. The IP cores are centered around a
--! common on-chip AMBA AXI system bus, and use a coherent method for
--! simulation and ... |
--!
--! @mainpage RISC-V System-on-Chip VHDL IP library
--!
--! @par Overview
--! The IP Library is an integrated set of reusable IP cores, designed for
--! system-on-chip (SOC) development. The IP cores are centered around a
--! common on-chip AMBA AXI system bus, and use a coherent method for
--! simulation and ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use STD.textio.all; --defines line, output
package txt_utils is
function to_string (value : STD_ULOGIC) return STRING;
function to_string (value : STD_ULOGIC_VECTOR) return STRING;
function to_string (value : STD_LOGIC_VECTOR) return STRI... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEE... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library verilog;
use verilog.vl_types.all;
entity e_s is
port(
clk : in vl_logic;
reset : in vl_logic;
sec : in vl_logic;
rwe1 : in vl_logic;
rwe2 : in vl_logic;
rwe3 : in vl_lo... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity input_split0 is
port (
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0);
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(4 downto 0);
ra2_data : ... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity input_split0 is
port (
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0);
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(4 downto 0);
ra2_data : ... |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity checkEnd is
port( try0 : in std_logic_vector(3 downto 0);
try1 : in std_logic_vector(3 downto 0);
cert : in std_logic_vector(3 downto 0);
erra : in std_logic_vector(3 downto 0);... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 01/02/2018 02:03:32 PM
-- Module Name: tb_ALU - Behavioral
-- Description:
--
-- Additional Comments:
--
-----------------------------------------------------------------------------... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--
-- File Name: VendorCovApiPkg.vhd
-- Design Unit Name: VendorCovApiPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
--
-- Based on work done in package VendorCovApiPkg_Aldec.vhd by:
-- ...
--
--
-- Package Defines
-- A set of foreign... |
--
-- File Name: VendorCovApiPkg.vhd
-- Design Unit Name: VendorCovApiPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
--
-- Based on work done in package VendorCovApiPkg_Aldec.vhd by:
-- ...
--
--
-- Package Defines
-- A set of foreign... |
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEE... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity receive is
generic (
NDBits : natural := 8
);
port (
clk : in std_logic;
rst : in std_logic;
Rx : in std_logic;
Dout : out std_logic_vector(NDBits-1 downto 0);
RxErr : out std_log... |
-- -------------------------------------------------------------
--
-- Generated Configuration for a_clk
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id... |
entity cond2 is
end entity;
architecture test of cond2 is
signal x, y : integer;
begin
process is
begin
x <= 5;
y <= 2;
wait for 1 ns;
if x = 5 then
if y = 2 then
report "y = 2";
if x = 4 then
report "x = 4" se... |
entity cond2 is
end entity;
architecture test of cond2 is
signal x, y : integer;
begin
process is
begin
x <= 5;
y <= 2;
wait for 1 ns;
if x = 5 then
if y = 2 then
report "y = 2";
if x = 4 then
report "x = 4" se... |
entity cond2 is
end entity;
architecture test of cond2 is
signal x, y : integer;
begin
process is
begin
x <= 5;
y <= 2;
wait for 1 ns;
if x = 5 then
if y = 2 then
report "y = 2";
if x = 4 then
report "x = 4" se... |
entity cond2 is
end entity;
architecture test of cond2 is
signal x, y : integer;
begin
process is
begin
x <= 5;
y <= 2;
wait for 1 ns;
if x = 5 then
if y = 2 then
report "y = 2";
if x = 4 then
report "x = 4" se... |
entity cond2 is
end entity;
architecture test of cond2 is
signal x, y : integer;
begin
process is
begin
x <= 5;
y <= 2;
wait for 1 ns;
if x = 5 then
if y = 2 then
report "y = 2";
if x = 4 then
report "x = 4" se... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
term... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex7_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex7_hot;
architecture behaviour of ex7_hot is
constant s1: std_logic_vector(9 downto 0) := "1000... |
-------------------------------------------------------------------------------
-- Title : VHDL model of the ADT7310 SPI Temperature Sensor
-- Project :
-------------------------------------------------------------------------------
-- File : adt7310.vhd
-- Author : Johann Glaser
-- Company :
-- ... |
-------------------------------------------------------------------------------
-- Title : VHDL model of the ADT7310 SPI Temperature Sensor
-- Project :
-------------------------------------------------------------------------------
-- File : adt7310.vhd
-- Author : Johann Glaser
-- Company :
-- ... |
-------------------------------------------------------------------------------
-- Title : VHDL model of the ADT7310 SPI Temperature Sensor
-- Project :
-------------------------------------------------------------------------------
-- File : adt7310.vhd
-- Author : Johann Glaser
-- Company :
-- ... |
-------------------------------------------------------------------------------
-- Title : VHDL model of the ADT7310 SPI Temperature Sensor
-- Project :
-------------------------------------------------------------------------------
-- File : adt7310.vhd
-- Author : Johann Glaser
-- Company :
-- ... |
-------------------------------------------------------------------------------
-- Title : VHDL model of the ADT7310 SPI Temperature Sensor
-- Project :
-------------------------------------------------------------------------------
-- File : adt7310.vhd
-- Author : Johann Glaser
-- Company :
-- ... |
-------------------------------------------------------------------------------
-- Title : VHDL model of the ADT7310 SPI Temperature Sensor
-- Project :
-------------------------------------------------------------------------------
-- File : adt7310.vhd
-- Author : Johann Glaser
-- Company :
-- ... |
-------------------------------------------------------------------------------
-- Title : VHDL model of the ADT7310 SPI Temperature Sensor
-- Project :
-------------------------------------------------------------------------------
-- File : adt7310.vhd
-- Author : Johann Glaser
-- Company :
-- ... |
-------------------------------------------------------------------------------
-- Title : VHDL model of the ADT7310 SPI Temperature Sensor
-- Project :
-------------------------------------------------------------------------------
-- File : adt7310.vhd
-- Author : Johann Glaser
-- Company :
-- ... |
-------------------------------------------------------------------------------
-- Title : VHDL model of the ADT7310 SPI Temperature Sensor
-- Project :
-------------------------------------------------------------------------------
-- File : adt7310.vhd
-- Author : Johann Glaser
-- Company :
-- ... |
-------------------------------------------------------------------------------
-- Title : VHDL model of the ADT7310 SPI Temperature Sensor
-- Project :
-------------------------------------------------------------------------------
-- File : adt7310.vhd
-- Author : Johann Glaser
-- Company :
-- ... |
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
end package body FIFO_PKG;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential ... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use i... |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
... |
library verilog;
use verilog.vl_types.all;
entity cnt is
port(
clock : in vl_logic;
ex1 : in vl_logic;
ex2 : in vl_logic;
ex3 : in vl_logic;
ex4 : in vl_logic;
read1 : in vl_lo... |
library verilog;
use verilog.vl_types.all;
entity cnt is
port(
clock : in vl_logic;
ex1 : in vl_logic;
ex2 : in vl_logic;
ex3 : in vl_logic;
ex4 : in vl_logic;
read1 : in vl_lo... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- int_sulv.vhdl
-- créé sam. janv. 29 12:11:00 CET 2011 par whygee@f-cpu.org
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package int_sulv is
subtype int_1 is unsigned( 0 downto 0);
subtype int_2 is unsigned( 1 downto 0);
subtype int_3 is unsigned( 2 downto 0);
subtype int_4 is ... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_a_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:18:10 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aua_types.all;
entity id is
port (
clk : in std_logic;
reset : in std_logic;
-- pipeline register inputs
opcode_in : in opcode_t;
dest_in : in reg_t;
pc_in : in pc_t;
pcnxt_in : in pc_t;
rega_in : in reg_t;
regb_i... |
-------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, %TPL_YEAR% All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used and/or copied only with the written permissio... |
-------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, %TPL_YEAR% All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used and/or copied only with the written permissio... |
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
cp_ok : out std_logic;
cp_en : in std_logic;
cp_rest : in std_logic;
cp_din : in std_logic_vector(63 downto 0);
cp_dout : out std_logic_vector(63 downto 0);
stdout_... |
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
cp_ok : out std_logic;
cp_en : in std_logic;
cp_rest : in std_logic;
cp_din : in std_logic_vector(63 downto 0);
cp_dout : out std_logic_vector(63 downto 0);
stdout_... |
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