content stringlengths 1 1.04M ⌀ |
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-- $Id: tb_rlink_tba.vhd 1203 2019-08-19 21:41:03Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_rlink_tba - sim
-- Description: Test ... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_eb_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity la is
Port(
xtalClock : in std_logic;
Led : out std_logic_vector(7 downto 0);
sw : in std_logic_vector(7 downto 0);
btn : in std_logic_vector(3 downto ... |
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
architecture RTL of ENT is
begin
end architecture RTL;
architecture RTL of ENT is
begin
end RTL;
architecture RTL of ENT is
begin
end;
architecture RTL of ENT is
begin
end ;
architecture RTL of ENT is
begin
end
;
architecture RTL of ENT is
begin
end--Comment
;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Jeffrey Magina and Jon Leidhold
--
-- Create Date: SPRING 2015
-- Module Name: Flip Flop
-- Project Name: ALUwithINPUT
-- Target Devices: Spartan-... |
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: RickWare
--
-- Create Date: 11:42:22 11/04/2015
-- Design Name:
-- Module Name: Ultrasonic - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-... |
-- This source file was created for J-PET project in WFAIS (Jagiellonian University in Cracow)
-- License for distribution outside WFAIS UJ and J-PET project is GPL v 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use std.textio.all;
use ieee.std_logic_textio.all;
entity packet_simulation is
Port (
clock :... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Helper procedures for handling writing raw ethernet frames
---
-- Original author: Colm Ryan
-- Copyright 2015,2016 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package ethernet_frame_pkg is
type byte_array is array(natural range <>) of std_logic_vector(7 downto 0... |
-------------------------------------------------------------------------------
--
-- File: rgb2dvi.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 30 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilen... |
-------------------------------------------------------------------------------
--
-- File: rgb2dvi.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 30 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilen... |
-------------------------------------------------------------------------------
--
-- File: rgb2dvi.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 30 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilen... |
-------------------------------------------------------------------------------
--
-- File: rgb2dvi.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 30 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilen... |
-------------------------------------------------------------------------------
--
-- File: rgb2dvi.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 30 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilen... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
---SI=[MDR,GR,ADDRESS]
entity busA is
port(
clock: in std_logic;
MDR : in std_logic_vector(15 downto 0);
GR : in std_logic_vector(15 downto 0);
ADDR : in std_logic_vector( 7 downto 0);
SI : in s... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
---SI=[MDR,GR,ADDRESS]
entity busA is
port(
clock: in std_logic;
MDR : in std_logic_vector(15 downto 0);
GR : in std_logic_vector(15 downto 0);
ADDR : in std_logic_vector( 7 downto 0);
SI : in s... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
entity dff11 is
port (q : out std_logic_vector(7 downto 0);
d : std_logic_vector(7 downto 0);
clk : std_logic);
end dff11;
architecture behav of dff11 is
begin
process
begin
wait until rising_edge (clk);
q <= d;
end process;
end behav;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 23:08:49 07/29/2009
-- Design Name:
-- Module Name: Comp_Counter - Behavioral
-- Project Name: Binary Counter
-- Target Devices:
-- Tool versions:
-- Descriptio... |
entity case4 is
end;
architecture behav of case4 is
subtype bv4 is bit_vector (1 to 4);
type vec2 is array (natural range <>) of bv4;
constant vects : vec2 := (x"0", x"3", x"9", x"4", x"a");
procedure print (msg : string; t : time) is
begin
report msg;
wait for t;
end print;
begin
process
begi... |
entity case4 is
end;
architecture behav of case4 is
subtype bv4 is bit_vector (1 to 4);
type vec2 is array (natural range <>) of bv4;
constant vects : vec2 := (x"0", x"3", x"9", x"4", x"a");
procedure print (msg : string; t : time) is
begin
report msg;
wait for t;
end print;
begin
process
begi... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.all;
entity sdram is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000"
);
port(
--bus interface
clk: in std_logic;
res: in std_logic;
address: in std_logic_... |
--------------------------------------------------------------------------------
--
-- Shift register (SRL) based synchronous FIFO
--
-- Signals:
-- clk : clock
-- rst : synchronous reset (active high)
-- din : data input
-- wr_en : write enable
-- full : FIFO full flag
-- dout : data output... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Sun Jun 18 18:41:12 2017
-- Host : DESKTOP-GKPSR1F running 64-bit major... |
-------------------------------------------------------------------------------
-- TDC sample preparation test bench
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this softw... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s820_hot is
port(
clock: in std_logic;
input: in std_logic_vector(17 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s820_hot;
architecture behaviour of s820_hot is
constant s00000: std_logic_vector(24 downto 0... |
-------------------------------------------------------------------------------
-- system_top.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_top is
port (
processing_system7_... |
-------------------------------------------------------------------------------
-- system_top.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_top is
port (
processing_system7_... |
-------------------------------------------------------------------------------
-- system_top.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_top is
port (
processing_system7_... |
library verilog;
use verilog.vl_types.all;
entity usb_system_cpu_ociram_sp_ram_module is
generic(
lpm_file : string := "UNUSED"
);
port(
address : in vl_logic_vector(7 downto 0);
byteenable : in vl_logic_vector(3 downto 0);
clock : in ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:33:34 11/21/2012
-- Design Name:
-- Module Name: MemoriaDeInstrucciones - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:... |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 8;
constant AMPL_WIDTH : integer := 8;
type lut_type is array... |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 8;
constant AMPL_WIDTH : integer := 8;
type lut_type is array... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- file: clk_gen.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a ... |
-- file: clk_gen.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a ... |
-------------------------------------------------------
-- Author: Hugues CREUSY
--February 2004
-- VHDL model
-- project: M25P32 50 MHz,
-- release: 1.0
-----------------------------------------------------
-- Unit : Package mem_util_pkg
-----------------------------------------------------
-------------------------... |
library verilog;
use verilog.vl_types.all;
entity MSS_SYSREG is
generic(
DEBUG : integer := 1;
INITFILE : string := ""
);
port(
EM_CONFIG0 : out vl_logic_vector(31 downto 0);
EM_CONFIG1 : out vl_logic_vector(31 downto 0);
COM_ESRAMFWR... |
library verilog;
use verilog.vl_types.all;
entity MSS_SYSREG is
generic(
DEBUG : integer := 1;
INITFILE : string := ""
);
port(
EM_CONFIG0 : out vl_logic_vector(31 downto 0);
EM_CONFIG1 : out vl_logic_vector(31 downto 0);
COM_ESRAMFWR... |
library verilog;
use verilog.vl_types.all;
entity MSS_SYSREG is
generic(
DEBUG : integer := 1;
INITFILE : string := ""
);
port(
EM_CONFIG0 : out vl_logic_vector(31 downto 0);
EM_CONFIG1 : out vl_logic_vector(31 downto 0);
COM_ESRAMFWR... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- tb_Binarization.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:26:08
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_Binarization is
end entity tb_Binarization;
architecture rtl of tb_Binarization is
component Binarization_GN is
port (
Clock ... |
-- tb_Binarization.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:26:08
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_Binarization is
end entity tb_Binarization;
architecture rtl of tb_Binarization is
component Binarization_GN is
port (
Clock ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY lights IS
PORT (
SW : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CLOCK_50 : IN STD_LOGIC;
LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
DRAM_CLK, DRAM_CKE : OUT STD_LOGIC;
DRAM_ADDR :... |
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