content stringlengths 1 1.04M ⌀ |
|---|
--
-- ADC for ZPUINO
--
--
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- ... |
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: EPROC_FIFO_DRIVER
--! Project Name: FELIX
----------------------------------------------------------------------------------
... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
entity tb is
end tb;
architecture sim of tb is
-- Extra tests for 'image and 'value on enumeration types (other than boolean)
-- Type with less than 256 values
type e8 is (one, two, three, four);
-- Type with more than 256 values
type e32 is (T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
T20, T21... |
entity tb is
end tb;
architecture sim of tb is
-- Extra tests for 'image and 'value on enumeration types (other than boolean)
-- Type with less than 256 values
type e8 is (one, two, three, four);
-- Type with more than 256 values
type e32 is (T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
T20, T21... |
entity tb is
end tb;
architecture sim of tb is
-- Extra tests for 'image and 'value on enumeration types (other than boolean)
-- Type with less than 256 values
type e8 is (one, two, three, four);
-- Type with more than 256 values
type e32 is (T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
T20, T21... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity ALU is
port (
clk : in std_logic;
code : in std_logic_vector(3 downto 0);
tagD : in tag_t;
valA : in value_t;
valB : in value_t;
emitTag : out tag_t := (others => '0');
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pack0 is
procedure inc(signal val:inout std_logic_vector);
procedure inc(signal val:inout unsigned);
procedure inc(signal val:inout signed);
procedure inc(signal val:inout integer);
procedure dec(signal val:inout std_logic_vector);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pack0 is
procedure inc(signal val:inout std_logic_vector);
procedure inc(signal val:inout unsigned);
procedure inc(signal val:inout signed);
procedure inc(signal val:inout integer);
procedure dec(signal val:inout std_logic_vector);... |
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity nbit_XtoY_mux is
generic(
bitPerInput: integer:=2;
numInputs: integer:=4
);
port(
enable: in std_logic;
input:in std_logic_vector(bitPerInput*numInputs-1 downto 0);
output:out std_logic_vector(... |
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Softw... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
ENTITY test_fetch_register IS
END test_fetch_register;
ARCHITECTURE behavior OF test_fetch_register IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fetch_register
PORT(
mem_addr : IN ... |
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:53:00 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
entity debounce is
generic(
delay:integer := 50000
);
port(
clk: in std_logic;
input: in std_logic;
output: out std_logic
);
end debounce;
architecture Behavio... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Types.all;
use work.Consts.all;
use work.Funcs.all;
entity tbDataPath is
end tbDataPath;
architecture tb_data_path_arch of tbDataPath is
constant ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
constant DATA_SIZE : integer := C_SYS_DATA_SIZE;
co... |
library verilog;
use verilog.vl_types.all;
entity finalproject_mm_interconnect_0_router_002 is
port(
clk : in vl_logic;
reset : in vl_logic;
sink_valid : in vl_logic;
sink_data : in vl_logic_vector(104 downto 0);
sink_startofpa... |
library verilog;
use verilog.vl_types.all;
entity arm_n_cntr is
port(
clk : in vl_logic;
reset : in vl_logic;
cout : out vl_logic;
modulus : in vl_logic_vector(31 downto 0)
);
end arm_n_cntr;
|
-------------------------------------------------------------------------------
-- Entity: cpu_ctrl
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Control unit without instruction pipelining for the RISC-CPU of the
-- von-Neuman MCU.
-------------------... |
-------------------------------------------------------------------------------
-- Entity: cpu_ctrl
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Control unit without instruction pipelining for the RISC-CPU of the
-- von-Neuman MCU.
-------------------... |
-----------------------------------------------------------------------
-- Design : Counter VHDL top module, SPEC (Simple PCIe Carrier)
-- Author : Javier D. Garcia-Lasheras
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.... |
-----------------------------------------------------------------------
-- Design : Counter VHDL top module, SPEC (Simple PCIe Carrier)
-- Author : Javier D. Garcia-Lasheras
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_8_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:50:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author:... |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Ha... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Title : MIPS Processor
-- Project :
-------------------------------------------------------------------------------
-- File : MIPS_CPU.vhd
-- Author : Robert Jarzmik <robert.jarzmik@free.fr>
-- Company :
-- Create... |
-- Company: Team 5
-- Engineer:
-- -Timothy Doucette Jr
-- -Robert Mushrall III
-- -Christopher Parks
--
-- Create Date: 14:26:47 03/31/2016
-- Design Name:
-- Module Name: Instruction_Memory_TL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
------------------------------------------------------------------
-- Processador Intel 8086 arquiteturado em pipeline e simplificado
------------------------------------------------------------------
-- Desenvolvedores: Jimmy Pinto Stelzer, Bruno Goulart e Bruno Paes
-- Baseado no exemplo de implementação do MIPS dos ... |
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Potential Ventures Ltd
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistribu... |
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Potential Ventures Ltd
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistribu... |
-- NEED RESULT: ARCH00345.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: A... |
--------------------------------------------------------------------------------
--
-- AM2901 Benchmark -- mem test vectors
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Verification Info... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_314 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_314;
architecture augh of add_314 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_314 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_314;
architecture augh of add_314 is
signal carry_inA : std_l... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.procedures.all;
entity simple_alu is
port(
clk : in std_logic;
a : in t_data;
b : in t_data;
op : in std_logic_vector(2 downto 0);
c :... |
-- $Id: tb_tst_serloop.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop - sim
-- Description: Ge... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library ieee;
use ieee.std_logic_1164.all;
use work.memory_types.all;
entity test_vga_rom is
end test_vga_rom;
architecture behavioural of test_vga_rom is
component VGA_ROM is
generic (
contents: vga_memory
);
port (
clock : in std_logic;
enable : in std_logic;
address : in nat... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SPI_MasterTB is
end entity; --SPI_MasterTB
architecture tb of SPI_MasterTB is
constant G_CLOCK_FREQUENCY : integer := 100E6;
constant G_CLOCK_DIVIDER : integer := 100;
constant G_SPI_TRANSACT... |
library ieee;
use ieee.std_logic_1164.all;
use work.utils_pkg.all;
entity event_hold_stage_tb is
end event_hold_stage_tb;
architecture tb of event_hold_stage_tb is
signal dout : std_logic := '0';
signal din : std_logic := '0';
signal period : std_logic := '0';
signal clk : std_logic := '0';
be... |
library ieee;
use ieee.std_logic_1164.all;
use work.utils_pkg.all;
entity event_hold_stage_tb is
end event_hold_stage_tb;
architecture tb of event_hold_stage_tb is
signal dout : std_logic := '0';
signal din : std_logic := '0';
signal period : std_logic := '0';
signal clk : std_logic := '0';
be... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 28-03-2016
-- Module Name: p9.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Solving_Key_Equation_1
-- Module Name: Solving_Key_Equation_1
-- Project Name: ... |
-- library foo
package pack is
end package;
entity sub2 is
end entity;
architecture a of sub2 is
begin
end architecture;
use work.pack.all;
entity sub1 is
end entity;
architecture a of sub1 is
component sub2 is
end component;
begin
sub_i: component sub2;
end architecture;
-- library bar
library foo;... |
-- library foo
package pack is
end package;
entity sub2 is
end entity;
architecture a of sub2 is
begin
end architecture;
use work.pack.all;
entity sub1 is
end entity;
architecture a of sub1 is
component sub2 is
end component;
begin
sub_i: component sub2;
end architecture;
-- library bar
library foo;... |
-- library foo
package pack is
end package;
entity sub2 is
end entity;
architecture a of sub2 is
begin
end architecture;
use work.pack.all;
entity sub1 is
end entity;
architecture a of sub1 is
component sub2 is
end component;
begin
sub_i: component sub2;
end architecture;
-- library bar
library foo;... |
-- library foo
package pack is
end package;
entity sub2 is
end entity;
architecture a of sub2 is
begin
end architecture;
use work.pack.all;
entity sub1 is
end entity;
architecture a of sub1 is
component sub2 is
end component;
begin
sub_i: component sub2;
end architecture;
-- library bar
library foo;... |
-- library foo
package pack is
end package;
entity sub2 is
end entity;
architecture a of sub2 is
begin
end architecture;
use work.pack.all;
entity sub1 is
end entity;
architecture a of sub1 is
component sub2 is
end component;
begin
sub_i: component sub2;
end architecture;
-- library bar
library foo;... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity not00 is
port(
clkn: in std_logic ;
codopn: in std_logic_vector ( 3 downto 0 );
inFlagn: in std_logic;
portAn: in std_logic_vector ( 7 downto 0 );
outn: out std_logic_vector ( 7 downto 0 ... |
-------------------------------------------------------------------------------
--
-- SNESpad controller core
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- $Id: snespad_comp-pack.vhd,v 1.1 2004-10-05 18:20:14 arniml Exp $
--
------------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:30:45 03/28/2014
-- Design Name:
-- Module Name: sccpu_cpu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:35 05/08/2012
-- Design Name:
-- Module Name: instmemory - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Re... |
--
-- GPIOs on s6micro
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
entity Top is
port (
dips_i : in std_logic_vector(3 downto 0);
pbs_i : in std_logic;
leds_o : out s... |
--
-- GPIOs on s6micro
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
entity Top is
port (
dips_i : in std_logic_vector(3 downto 0);
pbs_i : in std_logic;
leds_o : out s... |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_propos... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.types_pkg.all;
package robot_layer_2_pkg is
constant MOTOR_COUNT : natural := 6;
constant QEI_COUNT : natural := 4+1;
component robot_layer_2 is
generic (
CLK_FREQUENCY_HZ : positive;
... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:16:35 10/31/2006
-- Design Name: fast_queue
-- Module Name: C:/fast_queueProject/src/fast_queue_tb.vhd
-- Project Name: myProj
-- Target Device:
-- Tool versions:
-- Description: ... |
library ieee;
use ieee.std_logic_1164.all;
entity sub is
port ( x : inout std_logic );
end entity;
architecture test of sub is
begin
p1: process is
begin
x <= '1';
wait for 1 ns;
x <= '0';
wait for 0 ns;
assert x'active;
assert not x'event;
assert x... |
entity tb_asgn05 is
end tb_asgn05;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_asgn05 is
signal s0 : std_logic;
signal s1 : std_logic;
signal r : std_logic_vector (5 downto 0);
begin
dut: entity work.asgn05
port map (s0 => s0, s1 => s1, r => r);
process
begin
s0 <= '0';
... |
entity call6a is
end;
architecture behav of call6a is
procedure check (s : string) is
begin
wait for 1 ns;
assert s (2) = 'a';
end;
begin
process
variable c : character := 'a';
begin
check ("bac");
wait for 2 ns;
check ((1 => 'e', 2 => c, 3 => 'c'));
report "SUCCESS";
wait;
... |
entity call6a is
end;
architecture behav of call6a is
procedure check (s : string) is
begin
wait for 1 ns;
assert s (2) = 'a';
end;
begin
process
variable c : character := 'a';
begin
check ("bac");
wait for 2 ns;
check ((1 => 'e', 2 => c, 3 => 'c'));
report "SUCCESS";
wait;
... |
-------------------------------------------------------------------------------
--! @file convRmiiToMii-rtl-ea.vhd
--
--! @brief RMII-to-MII converter
--
--! @details This is an RMII-to-MII converter to convert MII phy traces to RMII.
--! Example: MII PHY <--> RMII-to-MII converter <--> RMII MAC
--------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue is
port (sub_uns : out unsigned (8-1 downto 0);
sub_sgn : out signed (8-1 downto 0));
end issue;
architecture beh of issue is
begin
sub_uns <= unsigned'(b"0000_0000") - 1; -- works
sub_sgn <= signed'(b"0000_000... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_3_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:50:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author:... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity globalmodereg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
reset: in STD_LOGIC;
loadglobalmode: in STD_LOGIC;
readglobalmode: in STD_LOGIC;
ctrena: out STD_LOGIC;
pwmena: out STD_... |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fast_slave is
port(
clk_proc : in std_logic;
reset_n : in std_logic;
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o :... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
use Std.Textio.all;
LIBRARY ieee;
use ieee.std_logic_1164.ALL;
LIBRARY WORK;
use WORK.ALL;
entity test_Signal is end;
architecture test_Signal of test_Signal is
component C_Signal
generic (width : INTEGER := 4);
port (Input : in std_logic_Vector((width - 1) downto 0);
Store, Update, Clear, clock : i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
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