content stringlengths 1 1.04M ⌀ |
|---|
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_... |
-------------------------------------------------------------------------------
--
-- Title : addr_decoder
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\PLK_MN\plk_mn\src\lib\addr_decoder.vhd
-- Generated : We... |
-------------------------------------------------------------------------------
--
-- Title : addr_decoder
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\PLK_MN\plk_mn\src\lib\addr_decoder.vhd
-- Generated : We... |
-------------------------------------------------------------------------------
--
-- Title : addr_decoder
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\PLK_MN\plk_mn\src\lib\addr_decoder.vhd
-- Generated : We... |
-------------------------------------------------------------------------------
--
-- Title : addr_decoder
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\PLK_MN\plk_mn\src\lib\addr_decoder.vhd
-- Generated : We... |
-------------------------------------------------------------------------------
--
-- Title : addr_decoder
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\PLK_MN\plk_mn\src\lib\addr_decoder.vhd
-- Generated : We... |
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provid... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
package fifo_pkg is
end package fifo_pkg;
package fifo_pkg is
end package fifo_pkg;
|
----------------------------------------------------------------------------------
-- Company: University of Genoa
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 11:06:29 07/26/2011
-- Design Name:
-- Module Name: newCaoticGen - Behavioral
-- Project Name:
-- Target Devices:
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful... |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
-- Violation below
entity FIFO is
generic (
W_WIDTH : integer := 256;
DEPTH : integer := 32
);
end entity FIFO;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity And2 is
generic (delay: DELAY_LENGTH)
-- DELAY_LENGTH is a subtype: time range 0 fs to highest_time in the system
port (x, y: in BIT; z: out BIT);
end entity And2;
architecture arch2 of And2 is
begin
z <= x and y after delay;
end architecture arch2;
-- When gate is used in a netlist, a value is... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
configuration b_config of b is
for b_archi2
--
end for;
end configuration b_config;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
ENTITY test_bcd_display IS
END test_bcd_display;
ARCHITECTURE behavior OF test_bcd_display IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bcd_display
PORT(
... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ea_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNXAOKDYKC is
port(
input : in std_logic_vector(0 downto 0);
output : out std_logi... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNXAOKDYKC is
port(
input : in std_logic_vector(0 downto 0);
output : out std_logi... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNXAOKDYKC is
port(
input : in std_logic_vector(0 downto 0);
output : out std_logi... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNXAOKDYKC is
port(
input : in std_logic_vector(0 downto 0);
output : out std_logi... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under th... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under th... |
-- NEED RESULT: ARCH00295: Bit short circuiting results passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
---------------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:10:00 02/25/2015
-- Design Name:
-- Module Name: esram - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY sumadorTest IS
END sumadorTest;
ARCHITECTURE behavior OF sumadorTest IS
COMPONENT Prueba
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
op : IN std_logic;
s : OUT std_logic_vector(... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY sumadorTest IS
END sumadorTest;
ARCHITECTURE behavior OF sumadorTest IS
COMPONENT Prueba
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
op : IN std_logic;
s : OUT std_logic_vector(... |
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 200... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.03.2014 15:08:57
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revi... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:45:01 2017
-- Host : Juice-Laptop running 64-bit major re... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:45:01 2017
-- Host : Juice-Laptop running 64-bit major re... |
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
package SortListGenericPkg is
generic (
type ElementType;
type ArrayofElementType;
function array_length(A : ArrayofElementType) return natural;
function element_get(A : ArrayofElementType; index : natural) return ElementType
);
function inside (constant E : ElementType; constant A : in ArrayofEl... |
package SortListGenericPkg is
generic (
type ElementType;
type ArrayofElementType;
function array_length(A : ArrayofElementType) return natural;
function element_get(A : ArrayofElementType; index : natural) return ElementType
);
function inside (constant E : ElementType; constant A : in ArrayofEl... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_846 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_846;
architecture augh of cmp_846 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_846 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_846;
architecture augh of cmp_846 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
--
-- @file PS2_Driver.vhd
-- @date December, 2013
-- @author G. Roggemans <g.roggemans@grog.be>
-- @copyright Copyright (c) GROG [https://grog.be] 2013, All Rights Reserved
--
-- This application is free software: you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License ... |
-------------------------------------------------------------------------------
-- axi_datamover_indet_btt.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- Entity: cpu
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Top-level of CPU for simple von-Neumann MCU.
-----------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Entity: cpu
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Top-level of CPU for simple von-Neumann MCU.
-----------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Entity: cpu
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Top-level of CPU for simple von-Neumann MCU.
-----------------------------------------------------------------... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:07:51 2017
-- Host : EffulgentTome running 64-bit maj... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vga_lib.all;
entity vga_sync_gen_tb is
end vga_sync_gen_tb;
architecture bhv of vga_sync_gen_tb is
signal clk50Mhz : std_logic := '0';
signal clk25Mhz : std_logic;
signal rst : std_logic;
signal Hcount,Vcount : std_logic_vector(COUNT_WID... |
----------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2014 Brian K. Nemetz
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.Std_Logic_1164.all;
--Multiplexador 4x1 30bits
entity mux4x1_30 is
port (MAP1, MAP2, MAP3, MAP4: in std_logic_vector(29 downto 0);
REG: out std_logic_vector(29 downto 0);
SW: in std_logic_vector(1 downto 0)
);
end mux4x1_30;
--Definicao Arquitetura
architecture circuito of mux4x1_30 is
be... |
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Jakub Cabal
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, cop... |
-- Module Name: InputGate - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
entity
test6
is
port --port
( --(
a
: --;;;
in
std_logic_vector
(
width
-
1
downto
0
);
b : in std_logic;
c : out std_logic
)
;
end
test6;
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_218 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_218;
architecture augh of cmp_218 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_218 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_218;
architecture augh of cmp_218 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
architecture RTL of FIFO is
begin
process
variable var1 : integer;
begin
end process;
process (a, b)
variable var1 : integer;
begin
end process;
process is
variable var1 : integer;
begin
end process;
-- Violations below
process
variable var1 : integer;
begin
end process... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief FPGA Virtex6 specific constants definition.
------------------------------------------------------... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief FPGA Virtex6 specific constants definition.
------------------------------------------------------... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package misc_pkg is
type array_of_natural is array(natural range <>) of natural;
function zeros(count : natural; width : natural) return std_logic_vector;
function zeros(count : natural) return std_logic_vector;
end package;
package body misc_p... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:38:12 03/08/2017
-- Design Name:
-- Module Name: vga_init - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
ARCHITECTURE RTL OF FIFO IS
BEGIN
END ARCHITECTURE RTL;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
termina... |
-- Taken from a comment https://github.com/universal-ctags/ctags/issues/2678
-- submitted by @pidgeon777
library ieee;
use ieee.std_logic_1164.all;
entity ENTITY_TOP is
generic (
GEN : integer := 0
);
port (
INP : in std_logic
);
end entity;
architecture arch of ENTITY_TOP is
signal sig : std_logic ... |
-- Taken from a comment https://github.com/universal-ctags/ctags/issues/2678
-- submitted by @pidgeon777
library ieee;
use ieee.std_logic_1164.all;
entity ENTITY_TOP is
generic (
GEN : integer := 0
);
port (
INP : in std_logic
);
end entity;
architecture arch of ENTITY_TOP is
signal sig : std_logic ... |
-- Taken from a comment https://github.com/universal-ctags/ctags/issues/2678
-- submitted by @pidgeon777
library ieee;
use ieee.std_logic_1164.all;
entity ENTITY_TOP is
generic (
GEN : integer := 0
);
port (
INP : in std_logic
);
end entity;
architecture arch of ENTITY_TOP is
signal sig : std_logic ... |
-- Taken from a comment https://github.com/universal-ctags/ctags/issues/2678
-- submitted by @pidgeon777
library ieee;
use ieee.std_logic_1164.all;
entity ENTITY_TOP is
generic (
GEN : integer := 0
);
port (
INP : in std_logic
);
end entity;
architecture arch of ENTITY_TOP is
signal sig : std_logic ... |
-- Taken from a comment https://github.com/universal-ctags/ctags/issues/2678
-- submitted by @pidgeon777
library ieee;
use ieee.std_logic_1164.all;
entity ENTITY_TOP is
generic (
GEN : integer := 0
);
port (
INP : in std_logic
);
end entity;
architecture arch of ENTITY_TOP is
signal sig : std_logic ... |
-- Taken from a comment https://github.com/universal-ctags/ctags/issues/2678
-- submitted by @pidgeon777
library ieee;
use ieee.std_logic_1164.all;
entity ENTITY_TOP is
generic (
GEN : integer := 0
);
port (
INP : in std_logic
);
end entity;
architecture arch of ENTITY_TOP is
signal sig : std_logic ... |
-- Taken from a comment https://github.com/universal-ctags/ctags/issues/2678
-- submitted by @pidgeon777
library ieee;
use ieee.std_logic_1164.all;
entity ENTITY_TOP is
generic (
GEN : integer := 0
);
port (
INP : in std_logic
);
end entity;
architecture arch of ENTITY_TOP is
signal sig : std_logic ... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_2_e
--
-- Generated
-- by: wig
-- on: Wed Nov 30 06:48:17 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\lms\lms_pcore_addr_decoder.vhd
-- Created: 2015-06-19 16:39:46
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
-- -------------------------------------------------------------
-- ------------------------------------... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\lms\lms_pcore_addr_decoder.vhd
-- Created: 2015-06-19 16:39:46
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
-- -------------------------------------------------------------
-- ------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:09:07 11/20/2016
-- Design Name:
-- Module Name: twosComp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP lookup... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\lms\lms_pcore_axi_lite_module.vhd
-- Created: 2015-06-19 16:39:46
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
-- -------------------------------------------------------------
-- ---------------------------------... |
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