content stringlengths 1 1.04M ⌀ |
|---|
--
-- Audio mixer
--
-- Copyright 2011 TRSi
--
-- Version: 0.1
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
--... |
--
-- Audio mixer
--
-- Copyright 2011 TRSi
--
-- Version: 0.1
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
--... |
--
-- Audio mixer
--
-- Copyright 2011 TRSi
--
-- Version: 0.1
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
--... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1... |
-------------------------------------------------------------------------------
--
-- The testbench for t8039.
--
-- $Id: tb_t8039.vhd,v 1.5 2008-04-28 22:13:33 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised fo... |
--!
--! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
library ieee;
use ieee.std_logic_1164.all;
entity ent2 is
port (
clk : in std_logic;
o : out std_logic
);
end;
architecture a of ent2 is
procedure inv(signal s : inout std_logic) is
begin
s <= not s;
end procedure;
signal test : std_logic := '0';
begin
process(clk)
... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for ddrv4_struct
--
-- Generated by wig
-- on Wed Jan 29 16:39:40 2003
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author$
-- $Id$
-- $Date$
-- $Log$
--
-- Based on Mix Arch... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
package pkg is
function func (s : string) return natural;
function func2 (s : natural) return natural;
function func3(x : integer) return integer;
end package;
package body pkg is
function func(s : string) return natural is
function inner_func return natural is
begin
return s'length;
end;
b... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.std_logic_1164.ALL;
entity A is
port (
clk : in std_logic;
input : in std_logic;
output : out std_logic
);
end entity A;
architecture RTL of A is
begin
not_proc : process (clk)
variable not_input : std_logic := '0';
begin
if rising_edge(clk... |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use ieee.std_logic_unsigned.all;
entity clk_enabler is
GENERIC (
CONSTANT cnt_max : integer := 99999999);
port(
clock: in std_logic;
reset: in std_logic;
clk_en: out std_logic
);
end clk_e... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:28:59 2017
-- Host : EffulgentTome running 64-bit major r... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor cor... |
-- **********************************************************************************
-- Project : MiniBlaze
-- Author : Benjamin Lemoine
-- Module : peripheral_7_segements
-- Date : 07/25/2016
--
-- Description :
--
-- -----------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_top is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
aclk : in std_logic; -- interface clock
arst_n : in std_logic; -- interface reset
... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version... |
-- freq_controller.vhd
--
-- Created on: 12 May 2017
-- Author: Fabian Meyer
--
-- Component that allows to set blinking frequency from user input (buttons).
-- Uses sync_buffer component to debounce buttons signals. Button signals
-- are sampled with ~732Hz (24MHz / 2**15).
library ieee;
use ieee.std_logic_1164.a... |
package vunit4 is
type rec;
type int_ptr is access integer;
impure function get_rec(n : natural) return rec;
end package;
package body vunit4 is
type rec is record
x : int_ptr;
end record;
type int_ptr_vec is array (natural range <>) of int_ptr;
shared variable v : int_ptr_vec(... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
library ieee;
use ieee.std_logic_1164.all;
entity asgn03 is
port (s0 : std_logic;
s1 : std_logic;
r : out std_logic_vector (2 downto 0));
end asgn03;
architecture behav of asgn03 is
begin
process (s0, s1) is
begin
r <= "000";
if s0 = '1' then
r (1) <= '1';
if s1 = '1' then
... |
-- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your opt... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.BusMasters.all;
entity ADT7310P32LS16L_tb is
end ADT7310P32LS16L_tb;
architecture behavior of ADT7310P32LS16L_tb is
component ADT7310P32LS16L
port (
Reset_n_i : in std_logic;
Clk_i : ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ROM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ==================================... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_A_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file... |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This ... |
-- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: mux2g.vhd
-- // Date: 12/9/2004
-- // Description: 8 channel, n bit mux
-- // Class: CSE 378
-- ===========================================... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.internoc_pack.all;
entity internoc_ni_axi_master_v1_0_M00_AXI is
generic (
-- Users to add parameters here
C_IF00_DATA_WIDTH : integer := 8;
C_PACKET_WIDTH : integer := 40;
C_PACKET_ADDR_WIDTH : integer := 5... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.internoc_pack.all;
entity internoc_ni_axi_master_v1_0_M00_AXI is
generic (
-- Users to add parameters here
C_IF00_DATA_WIDTH : integer := 8;
C_PACKET_WIDTH : integer := 40;
C_PACKET_ADDR_WIDTH : integer := 5... |
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_aa
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:27 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_MIXED -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!... |
-- The MIT License (MIT)
--
-- Copyright (c) 2016 Jakub Cabal <xcabal05@stud.feec.vutbr.cz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limita... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/Complex3Multiply_block2.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ------------------------------------... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual simple output buffer.
----------------------------------------------------------------------------
library i... |
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : Z80CpuMon.vhd
-- /__... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief System Top level modules and interconnect declarations.
----------------------------------------... |
entity var2 is
end;
use work.pkg.all;
architecture behav of var2 is
begin
process
variable v1, v2 : rec_4;
begin
v2 := v1;
wait;
end process;
end behav;
|
entity var2 is
end;
use work.pkg.all;
architecture behav of var2 is
begin
process
variable v1, v2 : rec_4;
begin
v2 := v1;
wait;
end process;
end behav;
|
entity FIFO is
end entity;
architecture rtl of fifo is
begin
end architecture;
entity FIFO is
end entity;
architecture rtl of fifo is begin end architecture;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
entity PipeReg is
generic ( BITS : natural := 32);
port(
data : in std_logic_vector(BITS-1 downto 0);
enable : in std_logic; -- load/enable.
clr : in std_logic; -- async. clear.
clk : in std_logic; -- clock.
output : out std_l... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
------------------------------------------------------------------------------
-- Context scheduler
--
-- Project :
-- URL : $URL: $
-- Author : Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Last changed: $Id: $
------------------------... |
-- File name: pcie_top.vhd
-- Created: 2009-04-13
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: PCIe top level
use work.pcie.all;
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pcie_top is
port... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon May 26 11:13:41 2014
-- Host : macbook running 64-bit Arch Linux
-- ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-------------------------------------------------------------------------------
-- Entity: rom
-- Author: Waj
-- Date : 11-May-13, 26-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Program memory for simple von-Neumann MCU with registerd read da... |
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
------------------------------------------------------------------... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.tce_util.all;
entity ffaccel_input_mux_12 is
generic (
BUSW_0 : integer := 32;
BUSW_1 : integer := 32;
BUSW_2 : integer := 32;
BUSW_3 : integer := 32;
BUSW_4 : integer := 32;
BUSW_5 : integer := 32;
BUSW_6 ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.tce_util.all;
entity ffaccel_input_mux_12 is
generic (
BUSW_0 : integer := 32;
BUSW_1 : integer := 32;
BUSW_2 : integer := 32;
BUSW_3 : integer := 32;
BUSW_4 : integer := 32;
BUSW_5 : integer := 32;
BUSW_6 ... |
-------------------------------------------------------------------------------
-- axi_bram_ctrl_top.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary informatio... |
library ieee;
use ieee.std_logic_1164.all;
package general is
component clock_counter is
generic
(
f: integer := 50000000
);
port
(
clock_i: in std_logic;
clock_o: out std_logic
);
end component;
component random_gen is
generic(
N : ... |
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'image(1) = "1" report "TEST FAILED image 1" severity FAILURE;
report "TEST PASSED image 1" severity NOTE;
assert small'image(2) = "2" report "TEST FAILED image 2" severit... |
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'image(1) = "1" report "TEST FAILED image 1" severity FAILURE;
report "TEST PASSED image 1" severity NOTE;
assert small'image(2) = "2" report "TEST FAILED image 2" severit... |
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'image(1) = "1" report "TEST FAILED image 1" severity FAILURE;
report "TEST PASSED image 1" severity NOTE;
assert small'image(2) = "2" report "TEST FAILED image 2" severit... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_STICKYFLAG32 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
SET : in vl_logic_vector(31 downto 0);
CLR : in vl_logic_vector(31 downto 0);
FLAG ... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_STICKYFLAG32 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
SET : in vl_logic_vector(31 downto 0);
CLR : in vl_logic_vector(31 downto 0);
FLAG ... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_STICKYFLAG32 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
SET : in vl_logic_vector(31 downto 0);
CLR : in vl_logic_vector(31 downto 0);
FLAG ... |
--------------------------------------------------------------------------------
-- Title : 16z091-01 module
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : rx_ctrl.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfel... |
-------------------------------------------------------------------------------
-- $Id: t400_por-c.vhd,v 1.2 2006-05-07 01:49:16 arniml Exp $
-------------------------------------------------------------------------------
configuration t400_por_rtl_c0 of t400_por is
for cyclone
end for;
end t400_por_rtl_c0;
--... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:19:46)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir1_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
te... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY VOLTAGE_SOURCE IS
GENERIC ( amplitude : REAL := 2.0;
offset : REAL := 1.2;
width : REAL := 0.002;
period : REAL := 0.005;
k : REAL := 100.0 );
PORT ( ... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY VOLTAGE_SOURCE IS
GENERIC ( amplitude : REAL := 2.0;
offset : REAL := 1.2;
width : REAL := 0.002;
period : REAL := 0.005;
k : REAL := 100.0 );
PORT ( ... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY VOLTAGE_SOURCE IS
GENERIC ( amplitude : REAL := 2.0;
offset : REAL := 1.2;
width : REAL := 0.002;
period : REAL := 0.005;
k : REAL := 100.0 );
PORT ( ... |
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