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LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY VOLTAGE_SOURCE IS GENERIC ( amplitude : REAL := 2.0; offset : REAL := 1.2; width : REAL := 0.002; period : REAL := 0.005; k : REAL := 100.0 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY VOLTAGE_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY VOLTAGE_SOURCE IS GENERIC ( amplitude : REAL := 2.0; offset : REAL := 1.2; width : REAL := 0.002; period : REAL := 0.005; k : REAL := 100.0 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY VOLTAGE_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY VOLTAGE_SOURCE IS GENERIC ( amplitude : REAL := 2.0; offset : REAL := 1.2; width : REAL := 0.002; period : REAL := 0.005; k : REAL := 100.0 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY VOLTAGE_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY VOLTAGE_SOURCE IS GENERIC ( amplitude : REAL := 2.0; offset : REAL := 1.2; width : REAL := 0.002; period : REAL := 0.005; k : REAL := 100.0 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY VOLTAGE_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY VOLTAGE_SOURCE IS GENERIC ( amplitude : REAL := 2.0; offset : REAL := 1.2; width : REAL := 0.002; period : REAL := 0.005; k : REAL := 100.0 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY VOLTAGE_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY VOLTAGE_SOURCE IS GENERIC ( amplitude : REAL := 2.0; offset : REAL := 1.2; width : REAL := 0.002; period : REAL := 0.005; k : REAL := 100.0 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY VOLTAGE_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY VOLTAGE_SOURCE IS GENERIC ( amplitude : REAL := 2.0; offset : REAL := 1.2; width : REAL := 0.002; period : REAL := 0.005; k : REAL := 100.0 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY VOLTAGE_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY VOLTAGE_SOURCE IS GENERIC ( amplitude : REAL := 2.0; offset : REAL := 1.2; width : REAL := 0.002; period : REAL := 0.005; k : REAL := 100.0 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY VOLTAGE_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY VOLTAGE_SOURCE IS GENERIC ( amplitude : REAL := 2.0; offset : REAL := 1.2; width : REAL := 0.002; period : REAL := 0.005; k : REAL := 100.0 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY VOLTAGE_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY VOLTAGE_SOURCE IS GENERIC ( amplitude : REAL := 2.0; offset : REAL := 1.2; width : REAL := 0.002; period : REAL := 0.005; k : REAL := 100.0 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY VOLTAGE_SOURCE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity debounce is port ( clk : in std_logic; signal_in : in std_logic; signal_out : out std_logic ); end debounce; architecture Behavioral of debounce is signal c : unsigned(23 downto 0); begin process(clk) begin if rising_edge(clk) then if signal_in = '1' then if c = x"FFFFFF" then signal_out <= '1'; else signal_out <= '0'; end if; c <= c + 1; else c <= (others => '0'); signal_out <= '0'; end if; end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity debounce is port ( clk : in std_logic; signal_in : in std_logic; signal_out : out std_logic ); end debounce; architecture Behavioral of debounce is signal c : unsigned(23 downto 0); begin process(clk) begin if rising_edge(clk) then if signal_in = '1' then if c = x"FFFFFF" then signal_out <= '1'; else signal_out <= '0'; end if; c <= c + 1; else c <= (others => '0'); signal_out <= '0'; end if; end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity debounce is port ( clk : in std_logic; signal_in : in std_logic; signal_out : out std_logic ); end debounce; architecture Behavioral of debounce is signal c : unsigned(23 downto 0); begin process(clk) begin if rising_edge(clk) then if signal_in = '1' then if c = x"FFFFFF" then signal_out <= '1'; else signal_out <= '0'; end if; c <= c + 1; else c <= (others => '0'); signal_out <= '0'; end if; end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity debounce is port ( clk : in std_logic; signal_in : in std_logic; signal_out : out std_logic ); end debounce; architecture Behavioral of debounce is signal c : unsigned(23 downto 0); begin process(clk) begin if rising_edge(clk) then if signal_in = '1' then if c = x"FFFFFF" then signal_out <= '1'; else signal_out <= '0'; end if; c <= c + 1; else c <= (others => '0'); signal_out <= '0'; end if; end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity debounce is port ( clk : in std_logic; signal_in : in std_logic; signal_out : out std_logic ); end debounce; architecture Behavioral of debounce is signal c : unsigned(23 downto 0); begin process(clk) begin if rising_edge(clk) then if signal_in = '1' then if c = x"FFFFFF" then signal_out <= '1'; else signal_out <= '0'; end if; c <= c + 1; else c <= (others => '0'); signal_out <= '0'; end if; end if; end process; end Behavioral;
architecture rtl of fifo is begin process begin my_signal <= '1' when input = "00" else my_signal2 or my_sig3 when input = "01" else my_sig4 and my_sig5 when input = "10" else '0'; my_signal <= '1' when input = "0000" else my_signal2 or my_sig3 when input = "0100" and input = "1100" else my_sig4 when input = "0010" else '0'; my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else '0' when input(3 downto 0) = "0010" else 'Z'; my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else '0' when input(3 downto 0) = "0010" else 'Z'; my_signal <= '1' when a = "0000" and func1(345) or b = "1000" and func2(567) and c = "00" else sig1 when a = "1000" and func2(560) and b = "0010" else '0'; my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else my_signal when input(3 downto 0) = "0010" else 'Z'; -- Testing no code after assignment my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else my_signal when input(3 downto 0) = "0010" else 'Z'; my_signal <= (others => '0') when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else my_signal when input(3 downto 0) = "0010" else 'Z'; end process; end architecture rtl;
------------------------------------------------------------------------------- -- bfm_monitor_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library plbv46_monitor_bfm_v1_00_a; use plbv46_monitor_bfm_v1_00_a.all; entity bfm_monitor_wrapper is port ( PLB_CLK : in std_logic; PLB_RESET : in std_logic; SYNCH_OUT : out std_logic_vector(0 to 31); SYNCH_IN : in std_logic_vector(0 to 31); M_request : in std_logic_vector(0 to 1); M_priority : in std_logic_vector(0 to 3); M_buslock : in std_logic_vector(0 to 1); M_RNW : in std_logic_vector(0 to 1); M_BE : in std_logic_vector(0 to 31); M_msize : in std_logic_vector(0 to 3); M_size : in std_logic_vector(0 to 7); M_type : in std_logic_vector(0 to 5); M_TAttribute : in std_logic_vector(0 to 31); M_lockErr : in std_logic_vector(0 to 1); M_abort : in std_logic_vector(0 to 1); M_UABus : in std_logic_vector(0 to 63); M_ABus : in std_logic_vector(0 to 63); M_wrDBus : in std_logic_vector(0 to 255); M_wrBurst : in std_logic_vector(0 to 1); M_rdBurst : in std_logic_vector(0 to 1); PLB_MAddrAck : in std_logic_vector(0 to 1); PLB_MRearbitrate : in std_logic_vector(0 to 1); PLB_MTimeout : in std_logic_vector(0 to 1); PLB_MBusy : in std_logic_vector(0 to 1); PLB_MRdErr : in std_logic_vector(0 to 1); PLB_MWrErr : in std_logic_vector(0 to 1); PLB_MIRQ : in std_logic_vector(0 to 1); PLB_MWrDAck : in std_logic_vector(0 to 1); PLB_MRdDBus : in std_logic_vector(0 to 255); PLB_MRdWdAddr : in std_logic_vector(0 to 7); PLB_MRdDAck : in std_logic_vector(0 to 1); PLB_MRdBTerm : in std_logic_vector(0 to 1); PLB_MWrBTerm : in std_logic_vector(0 to 1); PLB_Mssize : in std_logic_vector(0 to 3); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic_vector(0 to 0); PLB_wrPrim : in std_logic_vector(0 to 0); PLB_MasterID : in std_logic_vector(0 to 0); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 15); PLB_msize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_TAttribute : in std_logic_vector(0 to 15); PLB_lockErr : in std_logic; PLB_UABus : in std_logic_vector(0 to 31); PLB_ABus : in std_logic_vector(0 to 31); PLB_wrDBus : in std_logic_vector(0 to 127); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_rdpendReq : in std_logic; PLB_wrpendReq : in std_logic; PLB_rdpendPri : in std_logic_vector(0 to 1); PLB_wrpendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); Sl_addrAck : in std_logic_vector(0 to 0); Sl_wait : in std_logic_vector(0 to 0); Sl_rearbitrate : in std_logic_vector(0 to 0); Sl_wrDAck : in std_logic_vector(0 to 0); Sl_wrComp : in std_logic_vector(0 to 0); Sl_wrBTerm : in std_logic_vector(0 to 0); Sl_rdDBus : in std_logic_vector(0 to 127); Sl_rdWdAddr : in std_logic_vector(0 to 3); Sl_rdDAck : in std_logic_vector(0 to 0); Sl_rdComp : in std_logic_vector(0 to 0); Sl_rdBTerm : in std_logic_vector(0 to 0); Sl_MBusy : in std_logic_vector(0 to 1); Sl_MRdErr : in std_logic_vector(0 to 1); Sl_MWrErr : in std_logic_vector(0 to 1); Sl_MIRQ : in std_logic_vector(0 to 1); Sl_ssize : in std_logic_vector(0 to 1); PLB_SaddrAck : in std_logic; PLB_Swait : in std_logic; PLB_Srearbitrate : in std_logic; PLB_SwrDAck : in std_logic; PLB_SwrComp : in std_logic; PLB_SwrBTerm : in std_logic; PLB_SrdDBus : in std_logic_vector(0 to 127); PLB_SrdWdAddr : in std_logic_vector(0 to 3); PLB_SrdDAck : in std_logic; PLB_SrdComp : in std_logic; PLB_SrdBTerm : in std_logic; PLB_SMBusy : in std_logic_vector(0 to 1); PLB_SMRdErr : in std_logic_vector(0 to 1); PLB_SMWrErr : in std_logic_vector(0 to 1); PLB_SMIRQ : in std_logic_vector(0 to 1); PLB_Sssize : in std_logic_vector(0 to 1) ); end bfm_monitor_wrapper; architecture STRUCTURE of bfm_monitor_wrapper is component plbv46_monitor_bfm is generic ( PLB_MONITOR_NUM : std_logic_vector(0 to 3); PLB_SLAVE0_ADDR_LO_0 : std_logic_vector(0 to 31); PLB_SLAVE0_ADDR_HI_0 : std_logic_vector(0 to 31); PLB_SLAVE1_ADDR_LO_0 : std_logic_vector(0 to 31); PLB_SLAVE1_ADDR_HI_0 : std_logic_vector(0 to 31); PLB_SLAVE2_ADDR_LO_0 : std_logic_vector(0 to 31); PLB_SLAVE2_ADDR_HI_0 : std_logic_vector(0 to 31); PLB_SLAVE3_ADDR_LO_0 : std_logic_vector(0 to 31); PLB_SLAVE3_ADDR_HI_0 : std_logic_vector(0 to 31); PLB_SLAVE4_ADDR_LO_0 : std_logic_vector(0 to 31); PLB_SLAVE4_ADDR_HI_0 : std_logic_vector(0 to 31); PLB_SLAVE5_ADDR_LO_0 : std_logic_vector(0 to 31); PLB_SLAVE5_ADDR_HI_0 : std_logic_vector(0 to 31); PLB_SLAVE6_ADDR_LO_0 : std_logic_vector(0 to 31); PLB_SLAVE6_ADDR_HI_0 : std_logic_vector(0 to 31); PLB_SLAVE7_ADDR_LO_0 : std_logic_vector(0 to 31); PLB_SLAVE7_ADDR_HI_0 : std_logic_vector(0 to 31); PLB_SLAVE0_ADDR_LO_1 : std_logic_vector(0 to 31); PLB_SLAVE0_ADDR_HI_1 : std_logic_vector(0 to 31); PLB_SLAVE1_ADDR_LO_1 : std_logic_vector(0 to 31); PLB_SLAVE1_ADDR_HI_1 : std_logic_vector(0 to 31); PLB_SLAVE2_ADDR_LO_1 : std_logic_vector(0 to 31); PLB_SLAVE2_ADDR_HI_1 : std_logic_vector(0 to 31); PLB_SLAVE3_ADDR_LO_1 : std_logic_vector(0 to 31); PLB_SLAVE3_ADDR_HI_1 : std_logic_vector(0 to 31); PLB_SLAVE4_ADDR_LO_1 : std_logic_vector(0 to 31); PLB_SLAVE4_ADDR_HI_1 : std_logic_vector(0 to 31); PLB_SLAVE5_ADDR_LO_1 : std_logic_vector(0 to 31); PLB_SLAVE5_ADDR_HI_1 : std_logic_vector(0 to 31); PLB_SLAVE6_ADDR_LO_1 : std_logic_vector(0 to 31); PLB_SLAVE6_ADDR_HI_1 : std_logic_vector(0 to 31); PLB_SLAVE7_ADDR_LO_1 : std_logic_vector(0 to 31); PLB_SLAVE7_ADDR_HI_1 : std_logic_vector(0 to 31); C_MON_PLB_AWIDTH : integer; C_MON_PLB_DWIDTH : integer; C_MON_PLB_NUM_MASTERS : integer; C_MON_PLB_NUM_SLAVES : integer; C_MON_PLB_MID_WIDTH : integer ); port ( PLB_CLK : in std_logic; PLB_RESET : in std_logic; SYNCH_OUT : out std_logic_vector(0 to 31); SYNCH_IN : in std_logic_vector(0 to 31); M_request : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); M_priority : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1)); M_buslock : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); M_RNW : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); M_BE : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_DWIDTH/8)-1)); M_msize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1)); M_size : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_MASTERS)-1)); M_type : in std_logic_vector(0 to ((3*C_MON_PLB_NUM_MASTERS)-1)); M_TAttribute : in std_logic_vector(0 to 16*C_MON_PLB_NUM_MASTERS-1); M_lockErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); M_abort : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); M_UABus : in std_logic_vector(0 to ((C_MON_PLB_AWIDTH*C_MON_PLB_NUM_MASTERS)-1)); M_ABus : in std_logic_vector(0 to ((C_MON_PLB_AWIDTH*C_MON_PLB_NUM_MASTERS)-1)); M_wrDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_MASTERS)-1)); M_wrBurst : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); M_rdBurst : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); PLB_MAddrAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); PLB_MRearbitrate : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); PLB_MTimeout : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); PLB_MBusy : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); PLB_MRdErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); PLB_MWrErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); PLB_MIRQ : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); PLB_MWrDAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); PLB_MRdDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_MASTERS)-1)); PLB_MRdWdAddr : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_MASTERS)-1)); PLB_MRdDAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); PLB_MRdBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); PLB_MWrBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); PLB_Mssize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1)); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1); PLB_wrPrim : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1); PLB_MasterID : in std_logic_vector(0 to C_MON_PLB_MID_WIDTH-1); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH/8)-1)); PLB_msize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_TAttribute : in std_logic_vector(0 to 15); PLB_lockErr : in std_logic; PLB_UABus : in std_logic_vector(0 to 31); PLB_ABus : in std_logic_vector(0 to 31); PLB_wrDBus : in std_logic_vector(0 to (C_MON_PLB_DWIDTH-1)); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_rdpendReq : in std_logic; PLB_wrpendReq : in std_logic; PLB_rdpendPri : in std_logic_vector(0 to 1); PLB_wrpendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); Sl_addrAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1); Sl_wait : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1); Sl_rearbitrate : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1); Sl_wrDAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1); Sl_wrComp : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1); Sl_wrBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1); Sl_rdDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_SLAVES)-1)); Sl_rdWdAddr : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_SLAVES)-1)); Sl_rdDAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1); Sl_rdComp : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1); Sl_rdBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1); Sl_MBusy : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1)); Sl_MRdErr : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1)); Sl_MWrErr : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1)); Sl_MIRQ : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1)); Sl_ssize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_SLAVES)-1)); PLB_SaddrAck : in std_logic; PLB_Swait : in std_logic; PLB_Srearbitrate : in std_logic; PLB_SwrDAck : in std_logic; PLB_SwrComp : in std_logic; PLB_SwrBTerm : in std_logic; PLB_SrdDBus : in std_logic_vector(0 to C_MON_PLB_DWIDTH-1); PLB_SrdWdAddr : in std_logic_vector(0 to 3); PLB_SrdDAck : in std_logic; PLB_SrdComp : in std_logic; PLB_SrdBTerm : in std_logic; PLB_SMBusy : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); PLB_SMRdErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); PLB_SMWrErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); PLB_SMIRQ : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1); PLB_Sssize : in std_logic_vector(0 to 1) ); end component; begin bfm_monitor : plbv46_monitor_bfm generic map ( PLB_MONITOR_NUM => B"0000", PLB_SLAVE0_ADDR_LO_0 => X"00000000", PLB_SLAVE0_ADDR_HI_0 => X"00000000", PLB_SLAVE1_ADDR_LO_0 => X"00000000", PLB_SLAVE1_ADDR_HI_0 => X"00000000", PLB_SLAVE2_ADDR_LO_0 => X"00000000", PLB_SLAVE2_ADDR_HI_0 => X"00000000", PLB_SLAVE3_ADDR_LO_0 => X"00000000", PLB_SLAVE3_ADDR_HI_0 => X"00000000", PLB_SLAVE4_ADDR_LO_0 => X"00000000", PLB_SLAVE4_ADDR_HI_0 => X"00000000", PLB_SLAVE5_ADDR_LO_0 => X"00000000", PLB_SLAVE5_ADDR_HI_0 => X"00000000", PLB_SLAVE6_ADDR_LO_0 => X"00000000", PLB_SLAVE6_ADDR_HI_0 => X"00000000", PLB_SLAVE7_ADDR_LO_0 => X"00000000", PLB_SLAVE7_ADDR_HI_0 => X"00000000", PLB_SLAVE0_ADDR_LO_1 => X"00000000", PLB_SLAVE0_ADDR_HI_1 => X"00000000", PLB_SLAVE1_ADDR_LO_1 => X"00000000", PLB_SLAVE1_ADDR_HI_1 => X"00000000", PLB_SLAVE2_ADDR_LO_1 => X"00000000", PLB_SLAVE2_ADDR_HI_1 => X"00000000", PLB_SLAVE3_ADDR_LO_1 => X"00000000", PLB_SLAVE3_ADDR_HI_1 => X"00000000", PLB_SLAVE4_ADDR_LO_1 => X"00000000", PLB_SLAVE4_ADDR_HI_1 => X"00000000", PLB_SLAVE5_ADDR_LO_1 => X"00000000", PLB_SLAVE5_ADDR_HI_1 => X"00000000", PLB_SLAVE6_ADDR_LO_1 => X"00000000", PLB_SLAVE6_ADDR_HI_1 => X"00000000", PLB_SLAVE7_ADDR_LO_1 => X"00000000", PLB_SLAVE7_ADDR_HI_1 => X"00000000", C_MON_PLB_AWIDTH => 32, C_MON_PLB_DWIDTH => 128, C_MON_PLB_NUM_MASTERS => 2, C_MON_PLB_NUM_SLAVES => 1, C_MON_PLB_MID_WIDTH => 1 ) port map ( PLB_CLK => PLB_CLK, PLB_RESET => PLB_RESET, SYNCH_OUT => SYNCH_OUT, SYNCH_IN => SYNCH_IN, M_request => M_request, M_priority => M_priority, M_buslock => M_buslock, M_RNW => M_RNW, M_BE => M_BE, M_msize => M_msize, M_size => M_size, M_type => M_type, M_TAttribute => M_TAttribute, M_lockErr => M_lockErr, M_abort => M_abort, M_UABus => M_UABus, M_ABus => M_ABus, M_wrDBus => M_wrDBus, M_wrBurst => M_wrBurst, M_rdBurst => M_rdBurst, PLB_MAddrAck => PLB_MAddrAck, PLB_MRearbitrate => PLB_MRearbitrate, PLB_MTimeout => PLB_MTimeout, PLB_MBusy => PLB_MBusy, PLB_MRdErr => PLB_MRdErr, PLB_MWrErr => PLB_MWrErr, PLB_MIRQ => PLB_MIRQ, PLB_MWrDAck => PLB_MWrDAck, PLB_MRdDBus => PLB_MRdDBus, PLB_MRdWdAddr => PLB_MRdWdAddr, PLB_MRdDAck => PLB_MRdDAck, PLB_MRdBTerm => PLB_MRdBTerm, PLB_MWrBTerm => PLB_MWrBTerm, PLB_Mssize => PLB_Mssize, PLB_PAValid => PLB_PAValid, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_MasterID => PLB_MasterID, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_msize => PLB_msize, PLB_size => PLB_size, PLB_type => PLB_type, PLB_TAttribute => PLB_TAttribute, PLB_lockErr => PLB_lockErr, PLB_UABus => PLB_UABus, PLB_ABus => PLB_ABus, PLB_wrDBus => PLB_wrDBus, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_rdpendReq => PLB_rdpendReq, PLB_wrpendReq => PLB_wrpendReq, PLB_rdpendPri => PLB_rdpendPri, PLB_wrpendPri => PLB_wrpendPri, PLB_reqPri => PLB_reqPri, Sl_addrAck => Sl_addrAck, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_wrBTerm => Sl_wrBTerm, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_rdBTerm => Sl_rdBTerm, Sl_MBusy => Sl_MBusy, Sl_MRdErr => Sl_MRdErr, Sl_MWrErr => Sl_MWrErr, Sl_MIRQ => Sl_MIRQ, Sl_ssize => Sl_ssize, PLB_SaddrAck => PLB_SaddrAck, PLB_Swait => PLB_Swait, PLB_Srearbitrate => PLB_Srearbitrate, PLB_SwrDAck => PLB_SwrDAck, PLB_SwrComp => PLB_SwrComp, PLB_SwrBTerm => PLB_SwrBTerm, PLB_SrdDBus => PLB_SrdDBus, PLB_SrdWdAddr => PLB_SrdWdAddr, PLB_SrdDAck => PLB_SrdDAck, PLB_SrdComp => PLB_SrdComp, PLB_SrdBTerm => PLB_SrdBTerm, PLB_SMBusy => PLB_SMBusy, PLB_SMRdErr => PLB_SMRdErr, PLB_SMWrErr => PLB_SMWrErr, PLB_SMIRQ => PLB_SMIRQ, PLB_Sssize => PLB_Sssize ); end architecture STRUCTURE;
-- -*- vhdl -*- ------------------------------------------------------------------------------- -- Copyright (c) 2012, The CARPE Project, All rights reserved. -- -- See the AUTHORS file for individual contributors. -- -- -- -- Copyright and related rights are licensed under the Solderpad -- -- Hardware License, Version 0.51 (the "License"); you may not use this -- -- file except in compliance with the License. You may obtain a copy of -- -- the License at http://solderpad.org/licenses/SHL-0.51. -- -- -- -- Unless required by applicable law or agreed to in writing, software, -- -- hardware and materials distributed under this License is distributed -- -- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -- -- either express or implied. See the License for the specific language -- -- governing permissions and limitations under the License. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library sys; use sys.sys_pkg.all; use work.cpu_mmu_inst_pkg.all; use work.cpu_l1mem_inst_pass_pkg.all; entity cpu_l1mem_inst_pass is port ( clk : in std_ulogic; rstn : in std_ulogic; cpu_mmu_inst_ctrl_in : out cpu_mmu_inst_ctrl_in_type; cpu_mmu_inst_dp_in : out cpu_mmu_inst_dp_in_type; cpu_mmu_inst_ctrl_out : in cpu_mmu_inst_ctrl_out_type; cpu_mmu_inst_dp_out : in cpu_mmu_inst_dp_out_type; cpu_l1mem_inst_pass_ctrl_in : in cpu_l1mem_inst_pass_ctrl_in_type; cpu_l1mem_inst_pass_dp_in : in cpu_l1mem_inst_pass_dp_in_type; cpu_l1mem_inst_pass_ctrl_out : out cpu_l1mem_inst_pass_ctrl_out_type; cpu_l1mem_inst_pass_dp_out : out cpu_l1mem_inst_pass_dp_out_type; sys_master_ctrl_out : out sys_master_ctrl_out_type; sys_master_dp_out : out sys_master_dp_out_type; sys_slave_ctrl_out : in sys_slave_ctrl_out_type; sys_slave_dp_out : in sys_slave_dp_out_type ); end;
library verilog; use verilog.vl_types.all; entity Roll_Sum_vlg_vec_tst is end Roll_Sum_vlg_vec_tst;
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015 --Date : Sun May 08 18:17:54 2016 --Host : Win10Desktop running 64-bit major release (build 9200) --Command : generate_target triangle_intersect.bd --Design : triangle_intersect --Purpose : IP block netlist ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity m00_couplers_imp_YCVYZF is port ( M_ACLK : in STD_LOGIC; M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_arid : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_arready : in STD_LOGIC; M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_arvalid : out STD_LOGIC; M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_awid : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_awready : in STD_LOGIC; M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_awvalid : out STD_LOGIC; M_AXI_bid : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_bready : out STD_LOGIC; M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_bvalid : in STD_LOGIC; M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); M_AXI_rid : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_rlast : in STD_LOGIC; M_AXI_rready : out STD_LOGIC; M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_rvalid : in STD_LOGIC; M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); M_AXI_wid : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_wlast : out STD_LOGIC; M_AXI_wready : in STD_LOGIC; M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); M_AXI_wvalid : out STD_LOGIC; S_ACLK : in STD_LOGIC; S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arid : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arready : out STD_LOGIC; S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arvalid : in STD_LOGIC; S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awid : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awready : out STD_LOGIC; S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awvalid : in STD_LOGIC; S_AXI_bid : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_bready : in STD_LOGIC; S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_bvalid : out STD_LOGIC; S_AXI_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_rid : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_rlast : out STD_LOGIC; S_AXI_rready : in STD_LOGIC; S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_rvalid : out STD_LOGIC; S_AXI_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_wlast : in STD_LOGIC; S_AXI_wready : out STD_LOGIC; S_AXI_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_wvalid : in STD_LOGIC ); end m00_couplers_imp_YCVYZF; architecture STRUCTURE of m00_couplers_imp_YCVYZF is component triangle_intersect_auto_pc_1 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awid : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wid : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_wlast : out STD_LOGIC; m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bid : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arid : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rid : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); end component triangle_intersect_auto_pc_1; signal S_ACLK_1 : STD_LOGIC; signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_pc_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_pc_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_m00_couplers_ARREADY : STD_LOGIC; signal auto_pc_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_pc_to_m00_couplers_ARVALID : STD_LOGIC; signal auto_pc_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_pc_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_pc_to_m00_couplers_AWREADY : STD_LOGIC; signal auto_pc_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_pc_to_m00_couplers_AWVALID : STD_LOGIC; signal auto_pc_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m00_couplers_BREADY : STD_LOGIC; signal auto_pc_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m00_couplers_BVALID : STD_LOGIC; signal auto_pc_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal auto_pc_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m00_couplers_RLAST : STD_LOGIC; signal auto_pc_to_m00_couplers_RREADY : STD_LOGIC; signal auto_pc_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m00_couplers_RVALID : STD_LOGIC; signal auto_pc_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal auto_pc_to_m00_couplers_WID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_m00_couplers_WLAST : STD_LOGIC; signal auto_pc_to_m00_couplers_WREADY : STD_LOGIC; signal auto_pc_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); signal auto_pc_to_m00_couplers_WVALID : STD_LOGIC; signal m00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal m00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_auto_pc_ARREADY : STD_LOGIC; signal m00_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_auto_pc_ARVALID : STD_LOGIC; signal m00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal m00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_auto_pc_AWREADY : STD_LOGIC; signal m00_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_auto_pc_AWVALID : STD_LOGIC; signal m00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_auto_pc_BREADY : STD_LOGIC; signal m00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_auto_pc_BVALID : STD_LOGIC; signal m00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal m00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_auto_pc_RLAST : STD_LOGIC; signal m00_couplers_to_auto_pc_RREADY : STD_LOGIC; signal m00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_auto_pc_RVALID : STD_LOGIC; signal m00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal m00_couplers_to_auto_pc_WLAST : STD_LOGIC; signal m00_couplers_to_auto_pc_WREADY : STD_LOGIC; signal m00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m00_couplers_to_auto_pc_WVALID : STD_LOGIC; begin M_AXI_araddr(31 downto 0) <= auto_pc_to_m00_couplers_ARADDR(31 downto 0); M_AXI_arburst(1 downto 0) <= auto_pc_to_m00_couplers_ARBURST(1 downto 0); M_AXI_arcache(3 downto 0) <= auto_pc_to_m00_couplers_ARCACHE(3 downto 0); M_AXI_arid(1 downto 0) <= auto_pc_to_m00_couplers_ARID(1 downto 0); M_AXI_arlen(3 downto 0) <= auto_pc_to_m00_couplers_ARLEN(3 downto 0); M_AXI_arlock(1 downto 0) <= auto_pc_to_m00_couplers_ARLOCK(1 downto 0); M_AXI_arprot(2 downto 0) <= auto_pc_to_m00_couplers_ARPROT(2 downto 0); M_AXI_arqos(3 downto 0) <= auto_pc_to_m00_couplers_ARQOS(3 downto 0); M_AXI_arsize(2 downto 0) <= auto_pc_to_m00_couplers_ARSIZE(2 downto 0); M_AXI_arvalid <= auto_pc_to_m00_couplers_ARVALID; M_AXI_awaddr(31 downto 0) <= auto_pc_to_m00_couplers_AWADDR(31 downto 0); M_AXI_awburst(1 downto 0) <= auto_pc_to_m00_couplers_AWBURST(1 downto 0); M_AXI_awcache(3 downto 0) <= auto_pc_to_m00_couplers_AWCACHE(3 downto 0); M_AXI_awid(1 downto 0) <= auto_pc_to_m00_couplers_AWID(1 downto 0); M_AXI_awlen(3 downto 0) <= auto_pc_to_m00_couplers_AWLEN(3 downto 0); M_AXI_awlock(1 downto 0) <= auto_pc_to_m00_couplers_AWLOCK(1 downto 0); M_AXI_awprot(2 downto 0) <= auto_pc_to_m00_couplers_AWPROT(2 downto 0); M_AXI_awqos(3 downto 0) <= auto_pc_to_m00_couplers_AWQOS(3 downto 0); M_AXI_awsize(2 downto 0) <= auto_pc_to_m00_couplers_AWSIZE(2 downto 0); M_AXI_awvalid <= auto_pc_to_m00_couplers_AWVALID; M_AXI_bready <= auto_pc_to_m00_couplers_BREADY; M_AXI_rready <= auto_pc_to_m00_couplers_RREADY; M_AXI_wdata(63 downto 0) <= auto_pc_to_m00_couplers_WDATA(63 downto 0); M_AXI_wid(1 downto 0) <= auto_pc_to_m00_couplers_WID(1 downto 0); M_AXI_wlast <= auto_pc_to_m00_couplers_WLAST; M_AXI_wstrb(7 downto 0) <= auto_pc_to_m00_couplers_WSTRB(7 downto 0); M_AXI_wvalid <= auto_pc_to_m00_couplers_WVALID; S_ACLK_1 <= S_ACLK; S_ARESETN_1(0) <= S_ARESETN(0); S_AXI_arready <= m00_couplers_to_auto_pc_ARREADY; S_AXI_awready <= m00_couplers_to_auto_pc_AWREADY; S_AXI_bid(1 downto 0) <= m00_couplers_to_auto_pc_BID(1 downto 0); S_AXI_bresp(1 downto 0) <= m00_couplers_to_auto_pc_BRESP(1 downto 0); S_AXI_bvalid <= m00_couplers_to_auto_pc_BVALID; S_AXI_rdata(63 downto 0) <= m00_couplers_to_auto_pc_RDATA(63 downto 0); S_AXI_rid(1 downto 0) <= m00_couplers_to_auto_pc_RID(1 downto 0); S_AXI_rlast <= m00_couplers_to_auto_pc_RLAST; S_AXI_rresp(1 downto 0) <= m00_couplers_to_auto_pc_RRESP(1 downto 0); S_AXI_rvalid <= m00_couplers_to_auto_pc_RVALID; S_AXI_wready <= m00_couplers_to_auto_pc_WREADY; auto_pc_to_m00_couplers_ARREADY <= M_AXI_arready; auto_pc_to_m00_couplers_AWREADY <= M_AXI_awready; auto_pc_to_m00_couplers_BID(1 downto 0) <= M_AXI_bid(1 downto 0); auto_pc_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); auto_pc_to_m00_couplers_BVALID <= M_AXI_bvalid; auto_pc_to_m00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0); auto_pc_to_m00_couplers_RID(1 downto 0) <= M_AXI_rid(1 downto 0); auto_pc_to_m00_couplers_RLAST <= M_AXI_rlast; auto_pc_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); auto_pc_to_m00_couplers_RVALID <= M_AXI_rvalid; auto_pc_to_m00_couplers_WREADY <= M_AXI_wready; m00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); m00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); m00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); m00_couplers_to_auto_pc_ARID(1 downto 0) <= S_AXI_arid(1 downto 0); m00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0); m00_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0); m00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); m00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0); m00_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0); m00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); m00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid; m00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); m00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); m00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); m00_couplers_to_auto_pc_AWID(1 downto 0) <= S_AXI_awid(1 downto 0); m00_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0); m00_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0); m00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); m00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0); m00_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0); m00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); m00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid; m00_couplers_to_auto_pc_BREADY <= S_AXI_bready; m00_couplers_to_auto_pc_RREADY <= S_AXI_rready; m00_couplers_to_auto_pc_WDATA(63 downto 0) <= S_AXI_wdata(63 downto 0); m00_couplers_to_auto_pc_WLAST <= S_AXI_wlast; m00_couplers_to_auto_pc_WSTRB(7 downto 0) <= S_AXI_wstrb(7 downto 0); m00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid; auto_pc: component triangle_intersect_auto_pc_1 port map ( aclk => S_ACLK_1, aresetn => S_ARESETN_1(0), m_axi_araddr(31 downto 0) => auto_pc_to_m00_couplers_ARADDR(31 downto 0), m_axi_arburst(1 downto 0) => auto_pc_to_m00_couplers_ARBURST(1 downto 0), m_axi_arcache(3 downto 0) => auto_pc_to_m00_couplers_ARCACHE(3 downto 0), m_axi_arid(1 downto 0) => auto_pc_to_m00_couplers_ARID(1 downto 0), m_axi_arlen(3 downto 0) => auto_pc_to_m00_couplers_ARLEN(3 downto 0), m_axi_arlock(1 downto 0) => auto_pc_to_m00_couplers_ARLOCK(1 downto 0), m_axi_arprot(2 downto 0) => auto_pc_to_m00_couplers_ARPROT(2 downto 0), m_axi_arqos(3 downto 0) => auto_pc_to_m00_couplers_ARQOS(3 downto 0), m_axi_arready => auto_pc_to_m00_couplers_ARREADY, m_axi_arsize(2 downto 0) => auto_pc_to_m00_couplers_ARSIZE(2 downto 0), m_axi_arvalid => auto_pc_to_m00_couplers_ARVALID, m_axi_awaddr(31 downto 0) => auto_pc_to_m00_couplers_AWADDR(31 downto 0), m_axi_awburst(1 downto 0) => auto_pc_to_m00_couplers_AWBURST(1 downto 0), m_axi_awcache(3 downto 0) => auto_pc_to_m00_couplers_AWCACHE(3 downto 0), m_axi_awid(1 downto 0) => auto_pc_to_m00_couplers_AWID(1 downto 0), m_axi_awlen(3 downto 0) => auto_pc_to_m00_couplers_AWLEN(3 downto 0), m_axi_awlock(1 downto 0) => auto_pc_to_m00_couplers_AWLOCK(1 downto 0), m_axi_awprot(2 downto 0) => auto_pc_to_m00_couplers_AWPROT(2 downto 0), m_axi_awqos(3 downto 0) => auto_pc_to_m00_couplers_AWQOS(3 downto 0), m_axi_awready => auto_pc_to_m00_couplers_AWREADY, m_axi_awsize(2 downto 0) => auto_pc_to_m00_couplers_AWSIZE(2 downto 0), m_axi_awvalid => auto_pc_to_m00_couplers_AWVALID, m_axi_bid(1 downto 0) => auto_pc_to_m00_couplers_BID(1 downto 0), m_axi_bready => auto_pc_to_m00_couplers_BREADY, m_axi_bresp(1 downto 0) => auto_pc_to_m00_couplers_BRESP(1 downto 0), m_axi_bvalid => auto_pc_to_m00_couplers_BVALID, m_axi_rdata(63 downto 0) => auto_pc_to_m00_couplers_RDATA(63 downto 0), m_axi_rid(1 downto 0) => auto_pc_to_m00_couplers_RID(1 downto 0), m_axi_rlast => auto_pc_to_m00_couplers_RLAST, m_axi_rready => auto_pc_to_m00_couplers_RREADY, m_axi_rresp(1 downto 0) => auto_pc_to_m00_couplers_RRESP(1 downto 0), m_axi_rvalid => auto_pc_to_m00_couplers_RVALID, m_axi_wdata(63 downto 0) => auto_pc_to_m00_couplers_WDATA(63 downto 0), m_axi_wid(1 downto 0) => auto_pc_to_m00_couplers_WID(1 downto 0), m_axi_wlast => auto_pc_to_m00_couplers_WLAST, m_axi_wready => auto_pc_to_m00_couplers_WREADY, m_axi_wstrb(7 downto 0) => auto_pc_to_m00_couplers_WSTRB(7 downto 0), m_axi_wvalid => auto_pc_to_m00_couplers_WVALID, s_axi_araddr(31 downto 0) => m00_couplers_to_auto_pc_ARADDR(31 downto 0), s_axi_arburst(1 downto 0) => m00_couplers_to_auto_pc_ARBURST(1 downto 0), s_axi_arcache(3 downto 0) => m00_couplers_to_auto_pc_ARCACHE(3 downto 0), s_axi_arid(1 downto 0) => m00_couplers_to_auto_pc_ARID(1 downto 0), s_axi_arlen(7 downto 0) => m00_couplers_to_auto_pc_ARLEN(7 downto 0), s_axi_arlock(0) => m00_couplers_to_auto_pc_ARLOCK(0), s_axi_arprot(2 downto 0) => m00_couplers_to_auto_pc_ARPROT(2 downto 0), s_axi_arqos(3 downto 0) => m00_couplers_to_auto_pc_ARQOS(3 downto 0), s_axi_arready => m00_couplers_to_auto_pc_ARREADY, s_axi_arregion(3 downto 0) => m00_couplers_to_auto_pc_ARREGION(3 downto 0), s_axi_arsize(2 downto 0) => m00_couplers_to_auto_pc_ARSIZE(2 downto 0), s_axi_arvalid => m00_couplers_to_auto_pc_ARVALID, s_axi_awaddr(31 downto 0) => m00_couplers_to_auto_pc_AWADDR(31 downto 0), s_axi_awburst(1 downto 0) => m00_couplers_to_auto_pc_AWBURST(1 downto 0), s_axi_awcache(3 downto 0) => m00_couplers_to_auto_pc_AWCACHE(3 downto 0), s_axi_awid(1 downto 0) => m00_couplers_to_auto_pc_AWID(1 downto 0), s_axi_awlen(7 downto 0) => m00_couplers_to_auto_pc_AWLEN(7 downto 0), s_axi_awlock(0) => m00_couplers_to_auto_pc_AWLOCK(0), s_axi_awprot(2 downto 0) => m00_couplers_to_auto_pc_AWPROT(2 downto 0), s_axi_awqos(3 downto 0) => m00_couplers_to_auto_pc_AWQOS(3 downto 0), s_axi_awready => m00_couplers_to_auto_pc_AWREADY, s_axi_awregion(3 downto 0) => m00_couplers_to_auto_pc_AWREGION(3 downto 0), s_axi_awsize(2 downto 0) => m00_couplers_to_auto_pc_AWSIZE(2 downto 0), s_axi_awvalid => m00_couplers_to_auto_pc_AWVALID, s_axi_bid(1 downto 0) => m00_couplers_to_auto_pc_BID(1 downto 0), s_axi_bready => m00_couplers_to_auto_pc_BREADY, s_axi_bresp(1 downto 0) => m00_couplers_to_auto_pc_BRESP(1 downto 0), s_axi_bvalid => m00_couplers_to_auto_pc_BVALID, s_axi_rdata(63 downto 0) => m00_couplers_to_auto_pc_RDATA(63 downto 0), s_axi_rid(1 downto 0) => m00_couplers_to_auto_pc_RID(1 downto 0), s_axi_rlast => m00_couplers_to_auto_pc_RLAST, s_axi_rready => m00_couplers_to_auto_pc_RREADY, s_axi_rresp(1 downto 0) => m00_couplers_to_auto_pc_RRESP(1 downto 0), s_axi_rvalid => m00_couplers_to_auto_pc_RVALID, s_axi_wdata(63 downto 0) => m00_couplers_to_auto_pc_WDATA(63 downto 0), s_axi_wlast => m00_couplers_to_auto_pc_WLAST, s_axi_wready => m00_couplers_to_auto_pc_WREADY, s_axi_wstrb(7 downto 0) => m00_couplers_to_auto_pc_WSTRB(7 downto 0), s_axi_wvalid => m00_couplers_to_auto_pc_WVALID ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity s00_couplers_imp_18SS9VV is port ( M_ACLK : in STD_LOGIC; M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_araddr : out STD_LOGIC_VECTOR ( 9 downto 0 ); M_AXI_arready : in STD_LOGIC; M_AXI_arvalid : out STD_LOGIC; M_AXI_awaddr : out STD_LOGIC_VECTOR ( 9 downto 0 ); M_AXI_awready : in STD_LOGIC; M_AXI_awvalid : out STD_LOGIC; M_AXI_bready : out STD_LOGIC; M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_bvalid : in STD_LOGIC; M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_rready : out STD_LOGIC; M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_rvalid : in STD_LOGIC; M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_wready : in STD_LOGIC; M_AXI_wvalid : out STD_LOGIC; S_ACLK : in STD_LOGIC; S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arready : out STD_LOGIC; S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arvalid : in STD_LOGIC; S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awready : out STD_LOGIC; S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awvalid : in STD_LOGIC; S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_bready : in STD_LOGIC; S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_bvalid : out STD_LOGIC; S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_rlast : out STD_LOGIC; S_AXI_rready : in STD_LOGIC; S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_rvalid : out STD_LOGIC; S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S_AXI_wlast : in STD_LOGIC; S_AXI_wready : out STD_LOGIC; S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_wvalid : in STD_LOGIC ); end s00_couplers_imp_18SS9VV; architecture STRUCTURE of s00_couplers_imp_18SS9VV is component triangle_intersect_auto_pc_0 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); end component triangle_intersect_auto_pc_0; signal S_ACLK_1 : STD_LOGIC; signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC; signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC; signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC; signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC; signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC; signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC; signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC; signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC; signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC; signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC; signal NLW_auto_pc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_auto_pc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_auto_pc_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); begin M_AXI_araddr(9 downto 0) <= auto_pc_to_s00_couplers_ARADDR(9 downto 0); M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID; M_AXI_awaddr(9 downto 0) <= auto_pc_to_s00_couplers_AWADDR(9 downto 0); M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID; M_AXI_bready <= auto_pc_to_s00_couplers_BREADY; M_AXI_rready <= auto_pc_to_s00_couplers_RREADY; M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0); M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID; S_ACLK_1 <= S_ACLK; S_ARESETN_1(0) <= S_ARESETN(0); S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY; S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY; S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0); S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0); S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID; S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0); S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0); S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST; S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0); S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID; S_AXI_wready <= s00_couplers_to_auto_pc_WREADY; auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready; auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready; auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid; auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid; auto_pc_to_s00_couplers_WREADY <= M_AXI_wready; s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0); s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0); s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0); s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0); s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid; s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0); s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0); s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0); s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0); s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid; s00_couplers_to_auto_pc_BREADY <= S_AXI_bready; s00_couplers_to_auto_pc_RREADY <= S_AXI_rready; s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0); s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast; s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid; auto_pc: component triangle_intersect_auto_pc_0 port map ( aclk => S_ACLK_1, aresetn => S_ARESETN_1(0), m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0), m_axi_arprot(2 downto 0) => NLW_auto_pc_m_axi_arprot_UNCONNECTED(2 downto 0), m_axi_arready => auto_pc_to_s00_couplers_ARREADY, m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID, m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0), m_axi_awprot(2 downto 0) => NLW_auto_pc_m_axi_awprot_UNCONNECTED(2 downto 0), m_axi_awready => auto_pc_to_s00_couplers_AWREADY, m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID, m_axi_bready => auto_pc_to_s00_couplers_BREADY, m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0), m_axi_bvalid => auto_pc_to_s00_couplers_BVALID, m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0), m_axi_rready => auto_pc_to_s00_couplers_RREADY, m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0), m_axi_rvalid => auto_pc_to_s00_couplers_RVALID, m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0), m_axi_wready => auto_pc_to_s00_couplers_WREADY, m_axi_wstrb(3 downto 0) => NLW_auto_pc_m_axi_wstrb_UNCONNECTED(3 downto 0), m_axi_wvalid => auto_pc_to_s00_couplers_WVALID, s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0), s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0), s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0), s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0), s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0), s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0), s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0), s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0), s_axi_arready => s00_couplers_to_auto_pc_ARREADY, s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0), s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID, s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0), s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0), s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0), s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0), s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0), s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0), s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0), s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0), s_axi_awready => s00_couplers_to_auto_pc_AWREADY, s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0), s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID, s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0), s_axi_bready => s00_couplers_to_auto_pc_BREADY, s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0), s_axi_bvalid => s00_couplers_to_auto_pc_BVALID, s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0), s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0), s_axi_rlast => s00_couplers_to_auto_pc_RLAST, s_axi_rready => s00_couplers_to_auto_pc_RREADY, s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0), s_axi_rvalid => s00_couplers_to_auto_pc_RVALID, s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0), s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0), s_axi_wlast => s00_couplers_to_auto_pc_WLAST, s_axi_wready => s00_couplers_to_auto_pc_WREADY, s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0), s_axi_wvalid => s00_couplers_to_auto_pc_WVALID ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity s00_couplers_imp_1FME12G is port ( M_ACLK : in STD_LOGIC; M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_arready : in STD_LOGIC; M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_arvalid : out STD_LOGIC; M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); M_AXI_rlast : in STD_LOGIC; M_AXI_rready : out STD_LOGIC; M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_rvalid : in STD_LOGIC; S_ACLK : in STD_LOGIC; S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arready : out STD_LOGIC; S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arvalid : in STD_LOGIC; S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_rlast : out STD_LOGIC; S_AXI_rready : in STD_LOGIC; S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_rvalid : out STD_LOGIC ); end s00_couplers_imp_1FME12G; architecture STRUCTURE of s00_couplers_imp_1FME12G is component triangle_intersect_auto_us_0 is port ( s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); end component triangle_intersect_auto_us_0; signal GND_1 : STD_LOGIC; signal S_ACLK_1 : STD_LOGIC; signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_us_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_us_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_us_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_us_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal auto_us_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_us_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_us_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_us_to_s00_couplers_ARREADY : STD_LOGIC; signal auto_us_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_us_to_s00_couplers_ARVALID : STD_LOGIC; signal auto_us_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal auto_us_to_s00_couplers_RLAST : STD_LOGIC; signal auto_us_to_s00_couplers_RREADY : STD_LOGIC; signal auto_us_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_us_to_s00_couplers_RVALID : STD_LOGIC; signal s00_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s00_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_us_ARREADY : STD_LOGIC; signal s00_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_auto_us_ARVALID : STD_LOGIC; signal s00_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_auto_us_RLAST : STD_LOGIC; signal s00_couplers_to_auto_us_RREADY : STD_LOGIC; signal s00_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_auto_us_RVALID : STD_LOGIC; signal NLW_auto_us_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); begin M_AXI_araddr(31 downto 0) <= auto_us_to_s00_couplers_ARADDR(31 downto 0); M_AXI_arburst(1 downto 0) <= auto_us_to_s00_couplers_ARBURST(1 downto 0); M_AXI_arcache(3 downto 0) <= auto_us_to_s00_couplers_ARCACHE(3 downto 0); M_AXI_arlen(7 downto 0) <= auto_us_to_s00_couplers_ARLEN(7 downto 0); M_AXI_arlock(0) <= auto_us_to_s00_couplers_ARLOCK(0); M_AXI_arprot(2 downto 0) <= auto_us_to_s00_couplers_ARPROT(2 downto 0); M_AXI_arqos(3 downto 0) <= auto_us_to_s00_couplers_ARQOS(3 downto 0); M_AXI_arsize(2 downto 0) <= auto_us_to_s00_couplers_ARSIZE(2 downto 0); M_AXI_arvalid <= auto_us_to_s00_couplers_ARVALID; M_AXI_rready <= auto_us_to_s00_couplers_RREADY; S_ACLK_1 <= S_ACLK; S_ARESETN_1(0) <= S_ARESETN(0); S_AXI_arready <= s00_couplers_to_auto_us_ARREADY; S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_us_RDATA(31 downto 0); S_AXI_rlast <= s00_couplers_to_auto_us_RLAST; S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_us_RRESP(1 downto 0); S_AXI_rvalid <= s00_couplers_to_auto_us_RVALID; auto_us_to_s00_couplers_ARREADY <= M_AXI_arready; auto_us_to_s00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0); auto_us_to_s00_couplers_RLAST <= M_AXI_rlast; auto_us_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); auto_us_to_s00_couplers_RVALID <= M_AXI_rvalid; s00_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); s00_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); s00_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); s00_couplers_to_auto_us_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0); s00_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); s00_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); s00_couplers_to_auto_us_ARVALID <= S_AXI_arvalid; s00_couplers_to_auto_us_RREADY <= S_AXI_rready; GND: unisim.vcomponents.GND port map ( G => GND_1 ); auto_us: component triangle_intersect_auto_us_0 port map ( m_axi_araddr(31 downto 0) => auto_us_to_s00_couplers_ARADDR(31 downto 0), m_axi_arburst(1 downto 0) => auto_us_to_s00_couplers_ARBURST(1 downto 0), m_axi_arcache(3 downto 0) => auto_us_to_s00_couplers_ARCACHE(3 downto 0), m_axi_arlen(7 downto 0) => auto_us_to_s00_couplers_ARLEN(7 downto 0), m_axi_arlock(0) => auto_us_to_s00_couplers_ARLOCK(0), m_axi_arprot(2 downto 0) => auto_us_to_s00_couplers_ARPROT(2 downto 0), m_axi_arqos(3 downto 0) => auto_us_to_s00_couplers_ARQOS(3 downto 0), m_axi_arready => auto_us_to_s00_couplers_ARREADY, m_axi_arregion(3 downto 0) => NLW_auto_us_m_axi_arregion_UNCONNECTED(3 downto 0), m_axi_arsize(2 downto 0) => auto_us_to_s00_couplers_ARSIZE(2 downto 0), m_axi_arvalid => auto_us_to_s00_couplers_ARVALID, m_axi_rdata(63 downto 0) => auto_us_to_s00_couplers_RDATA(63 downto 0), m_axi_rlast => auto_us_to_s00_couplers_RLAST, m_axi_rready => auto_us_to_s00_couplers_RREADY, m_axi_rresp(1 downto 0) => auto_us_to_s00_couplers_RRESP(1 downto 0), m_axi_rvalid => auto_us_to_s00_couplers_RVALID, s_axi_aclk => S_ACLK_1, s_axi_araddr(31 downto 0) => s00_couplers_to_auto_us_ARADDR(31 downto 0), s_axi_arburst(1 downto 0) => s00_couplers_to_auto_us_ARBURST(1 downto 0), s_axi_arcache(3 downto 0) => s00_couplers_to_auto_us_ARCACHE(3 downto 0), s_axi_aresetn => S_ARESETN_1(0), s_axi_arlen(7 downto 0) => s00_couplers_to_auto_us_ARLEN(7 downto 0), s_axi_arlock(0) => GND_1, s_axi_arprot(2 downto 0) => s00_couplers_to_auto_us_ARPROT(2 downto 0), s_axi_arqos(3) => GND_1, s_axi_arqos(2) => GND_1, s_axi_arqos(1) => GND_1, s_axi_arqos(0) => GND_1, s_axi_arready => s00_couplers_to_auto_us_ARREADY, s_axi_arregion(3) => GND_1, s_axi_arregion(2) => GND_1, s_axi_arregion(1) => GND_1, s_axi_arregion(0) => GND_1, s_axi_arsize(2 downto 0) => s00_couplers_to_auto_us_ARSIZE(2 downto 0), s_axi_arvalid => s00_couplers_to_auto_us_ARVALID, s_axi_rdata(31 downto 0) => s00_couplers_to_auto_us_RDATA(31 downto 0), s_axi_rlast => s00_couplers_to_auto_us_RLAST, s_axi_rready => s00_couplers_to_auto_us_RREADY, s_axi_rresp(1 downto 0) => s00_couplers_to_auto_us_RRESP(1 downto 0), s_axi_rvalid => s00_couplers_to_auto_us_RVALID ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity s01_couplers_imp_1G34NP1 is port ( M_ACLK : in STD_LOGIC; M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_awready : in STD_LOGIC; M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_awvalid : out STD_LOGIC; M_AXI_bready : out STD_LOGIC; M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_bvalid : in STD_LOGIC; M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); M_AXI_wlast : out STD_LOGIC; M_AXI_wready : in STD_LOGIC; M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); M_AXI_wvalid : out STD_LOGIC; S_ACLK : in STD_LOGIC; S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awready : out STD_LOGIC; S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awvalid : in STD_LOGIC; S_AXI_bready : in STD_LOGIC; S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_bvalid : out STD_LOGIC; S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_wlast : in STD_LOGIC; S_AXI_wready : out STD_LOGIC; S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_wvalid : in STD_LOGIC ); end s01_couplers_imp_1G34NP1; architecture STRUCTURE of s01_couplers_imp_1G34NP1 is component triangle_intersect_auto_us_1 is port ( s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_wlast : out STD_LOGIC; m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC ); end component triangle_intersect_auto_us_1; signal GND_1 : STD_LOGIC; signal S_ACLK_1 : STD_LOGIC; signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_us_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_us_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_us_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_us_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal auto_us_to_s01_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_us_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_us_to_s01_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_us_to_s01_couplers_AWREADY : STD_LOGIC; signal auto_us_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_us_to_s01_couplers_AWVALID : STD_LOGIC; signal auto_us_to_s01_couplers_BREADY : STD_LOGIC; signal auto_us_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_us_to_s01_couplers_BVALID : STD_LOGIC; signal auto_us_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal auto_us_to_s01_couplers_WLAST : STD_LOGIC; signal auto_us_to_s01_couplers_WREADY : STD_LOGIC; signal auto_us_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); signal auto_us_to_s01_couplers_WVALID : STD_LOGIC; signal s01_couplers_to_auto_us_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s01_couplers_to_auto_us_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s01_couplers_to_auto_us_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s01_couplers_to_auto_us_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s01_couplers_to_auto_us_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s01_couplers_to_auto_us_AWREADY : STD_LOGIC; signal s01_couplers_to_auto_us_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s01_couplers_to_auto_us_AWVALID : STD_LOGIC; signal s01_couplers_to_auto_us_BREADY : STD_LOGIC; signal s01_couplers_to_auto_us_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s01_couplers_to_auto_us_BVALID : STD_LOGIC; signal s01_couplers_to_auto_us_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s01_couplers_to_auto_us_WLAST : STD_LOGIC; signal s01_couplers_to_auto_us_WREADY : STD_LOGIC; signal s01_couplers_to_auto_us_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s01_couplers_to_auto_us_WVALID : STD_LOGIC; signal NLW_auto_us_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); begin M_AXI_awaddr(31 downto 0) <= auto_us_to_s01_couplers_AWADDR(31 downto 0); M_AXI_awburst(1 downto 0) <= auto_us_to_s01_couplers_AWBURST(1 downto 0); M_AXI_awcache(3 downto 0) <= auto_us_to_s01_couplers_AWCACHE(3 downto 0); M_AXI_awlen(7 downto 0) <= auto_us_to_s01_couplers_AWLEN(7 downto 0); M_AXI_awlock(0) <= auto_us_to_s01_couplers_AWLOCK(0); M_AXI_awprot(2 downto 0) <= auto_us_to_s01_couplers_AWPROT(2 downto 0); M_AXI_awqos(3 downto 0) <= auto_us_to_s01_couplers_AWQOS(3 downto 0); M_AXI_awsize(2 downto 0) <= auto_us_to_s01_couplers_AWSIZE(2 downto 0); M_AXI_awvalid <= auto_us_to_s01_couplers_AWVALID; M_AXI_bready <= auto_us_to_s01_couplers_BREADY; M_AXI_wdata(63 downto 0) <= auto_us_to_s01_couplers_WDATA(63 downto 0); M_AXI_wlast <= auto_us_to_s01_couplers_WLAST; M_AXI_wstrb(7 downto 0) <= auto_us_to_s01_couplers_WSTRB(7 downto 0); M_AXI_wvalid <= auto_us_to_s01_couplers_WVALID; S_ACLK_1 <= S_ACLK; S_ARESETN_1(0) <= S_ARESETN(0); S_AXI_awready <= s01_couplers_to_auto_us_AWREADY; S_AXI_bresp(1 downto 0) <= s01_couplers_to_auto_us_BRESP(1 downto 0); S_AXI_bvalid <= s01_couplers_to_auto_us_BVALID; S_AXI_wready <= s01_couplers_to_auto_us_WREADY; auto_us_to_s01_couplers_AWREADY <= M_AXI_awready; auto_us_to_s01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); auto_us_to_s01_couplers_BVALID <= M_AXI_bvalid; auto_us_to_s01_couplers_WREADY <= M_AXI_wready; s01_couplers_to_auto_us_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); s01_couplers_to_auto_us_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); s01_couplers_to_auto_us_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); s01_couplers_to_auto_us_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0); s01_couplers_to_auto_us_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); s01_couplers_to_auto_us_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); s01_couplers_to_auto_us_AWVALID <= S_AXI_awvalid; s01_couplers_to_auto_us_BREADY <= S_AXI_bready; s01_couplers_to_auto_us_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); s01_couplers_to_auto_us_WLAST <= S_AXI_wlast; s01_couplers_to_auto_us_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); s01_couplers_to_auto_us_WVALID <= S_AXI_wvalid; GND: unisim.vcomponents.GND port map ( G => GND_1 ); auto_us: component triangle_intersect_auto_us_1 port map ( m_axi_awaddr(31 downto 0) => auto_us_to_s01_couplers_AWADDR(31 downto 0), m_axi_awburst(1 downto 0) => auto_us_to_s01_couplers_AWBURST(1 downto 0), m_axi_awcache(3 downto 0) => auto_us_to_s01_couplers_AWCACHE(3 downto 0), m_axi_awlen(7 downto 0) => auto_us_to_s01_couplers_AWLEN(7 downto 0), m_axi_awlock(0) => auto_us_to_s01_couplers_AWLOCK(0), m_axi_awprot(2 downto 0) => auto_us_to_s01_couplers_AWPROT(2 downto 0), m_axi_awqos(3 downto 0) => auto_us_to_s01_couplers_AWQOS(3 downto 0), m_axi_awready => auto_us_to_s01_couplers_AWREADY, m_axi_awregion(3 downto 0) => NLW_auto_us_m_axi_awregion_UNCONNECTED(3 downto 0), m_axi_awsize(2 downto 0) => auto_us_to_s01_couplers_AWSIZE(2 downto 0), m_axi_awvalid => auto_us_to_s01_couplers_AWVALID, m_axi_bready => auto_us_to_s01_couplers_BREADY, m_axi_bresp(1 downto 0) => auto_us_to_s01_couplers_BRESP(1 downto 0), m_axi_bvalid => auto_us_to_s01_couplers_BVALID, m_axi_wdata(63 downto 0) => auto_us_to_s01_couplers_WDATA(63 downto 0), m_axi_wlast => auto_us_to_s01_couplers_WLAST, m_axi_wready => auto_us_to_s01_couplers_WREADY, m_axi_wstrb(7 downto 0) => auto_us_to_s01_couplers_WSTRB(7 downto 0), m_axi_wvalid => auto_us_to_s01_couplers_WVALID, s_axi_aclk => S_ACLK_1, s_axi_aresetn => S_ARESETN_1(0), s_axi_awaddr(31 downto 0) => s01_couplers_to_auto_us_AWADDR(31 downto 0), s_axi_awburst(1 downto 0) => s01_couplers_to_auto_us_AWBURST(1 downto 0), s_axi_awcache(3 downto 0) => s01_couplers_to_auto_us_AWCACHE(3 downto 0), s_axi_awlen(7 downto 0) => s01_couplers_to_auto_us_AWLEN(7 downto 0), s_axi_awlock(0) => GND_1, s_axi_awprot(2 downto 0) => s01_couplers_to_auto_us_AWPROT(2 downto 0), s_axi_awqos(3) => GND_1, s_axi_awqos(2) => GND_1, s_axi_awqos(1) => GND_1, s_axi_awqos(0) => GND_1, s_axi_awready => s01_couplers_to_auto_us_AWREADY, s_axi_awregion(3) => GND_1, s_axi_awregion(2) => GND_1, s_axi_awregion(1) => GND_1, s_axi_awregion(0) => GND_1, s_axi_awsize(2 downto 0) => s01_couplers_to_auto_us_AWSIZE(2 downto 0), s_axi_awvalid => s01_couplers_to_auto_us_AWVALID, s_axi_bready => s01_couplers_to_auto_us_BREADY, s_axi_bresp(1 downto 0) => s01_couplers_to_auto_us_BRESP(1 downto 0), s_axi_bvalid => s01_couplers_to_auto_us_BVALID, s_axi_wdata(31 downto 0) => s01_couplers_to_auto_us_WDATA(31 downto 0), s_axi_wlast => s01_couplers_to_auto_us_WLAST, s_axi_wready => s01_couplers_to_auto_us_WREADY, s_axi_wstrb(3 downto 0) => s01_couplers_to_auto_us_WSTRB(3 downto 0), s_axi_wvalid => s01_couplers_to_auto_us_WVALID ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity s02_couplers_imp_1FFYAJ6 is port ( M_ACLK : in STD_LOGIC; M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_arready : in STD_LOGIC; M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_arvalid : out STD_LOGIC; M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_awready : in STD_LOGIC; M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_awvalid : out STD_LOGIC; M_AXI_bready : out STD_LOGIC; M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_bvalid : in STD_LOGIC; M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); M_AXI_rlast : in STD_LOGIC; M_AXI_rready : out STD_LOGIC; M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_rvalid : in STD_LOGIC; M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); M_AXI_wlast : out STD_LOGIC; M_AXI_wready : in STD_LOGIC; M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); M_AXI_wvalid : out STD_LOGIC; S_ACLK : in STD_LOGIC; S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arready : out STD_LOGIC; S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_arvalid : in STD_LOGIC; S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awready : out STD_LOGIC; S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_awvalid : in STD_LOGIC; S_AXI_bready : in STD_LOGIC; S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_bvalid : out STD_LOGIC; S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_rlast : out STD_LOGIC; S_AXI_rready : in STD_LOGIC; S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_rvalid : out STD_LOGIC; S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_wlast : in STD_LOGIC; S_AXI_wready : out STD_LOGIC; S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_wvalid : in STD_LOGIC ); end s02_couplers_imp_1FFYAJ6; architecture STRUCTURE of s02_couplers_imp_1FFYAJ6 is component triangle_intersect_auto_us_2 is port ( s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_wlast : out STD_LOGIC; m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); end component triangle_intersect_auto_us_2; signal GND_1 : STD_LOGIC; signal S_ACLK_1 : STD_LOGIC; signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_us_to_s02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_us_to_s02_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_us_to_s02_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_us_to_s02_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal auto_us_to_s02_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_us_to_s02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_us_to_s02_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_us_to_s02_couplers_ARREADY : STD_LOGIC; signal auto_us_to_s02_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_us_to_s02_couplers_ARVALID : STD_LOGIC; signal auto_us_to_s02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal auto_us_to_s02_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_us_to_s02_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_us_to_s02_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal auto_us_to_s02_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal auto_us_to_s02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_us_to_s02_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal auto_us_to_s02_couplers_AWREADY : STD_LOGIC; signal auto_us_to_s02_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal auto_us_to_s02_couplers_AWVALID : STD_LOGIC; signal auto_us_to_s02_couplers_BREADY : STD_LOGIC; signal auto_us_to_s02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_us_to_s02_couplers_BVALID : STD_LOGIC; signal auto_us_to_s02_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal auto_us_to_s02_couplers_RLAST : STD_LOGIC; signal auto_us_to_s02_couplers_RREADY : STD_LOGIC; signal auto_us_to_s02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal auto_us_to_s02_couplers_RVALID : STD_LOGIC; signal auto_us_to_s02_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal auto_us_to_s02_couplers_WLAST : STD_LOGIC; signal auto_us_to_s02_couplers_WREADY : STD_LOGIC; signal auto_us_to_s02_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); signal auto_us_to_s02_couplers_WVALID : STD_LOGIC; signal s02_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s02_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s02_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s02_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s02_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s02_couplers_to_auto_us_ARREADY : STD_LOGIC; signal s02_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s02_couplers_to_auto_us_ARVALID : STD_LOGIC; signal s02_couplers_to_auto_us_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s02_couplers_to_auto_us_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s02_couplers_to_auto_us_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s02_couplers_to_auto_us_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s02_couplers_to_auto_us_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s02_couplers_to_auto_us_AWREADY : STD_LOGIC; signal s02_couplers_to_auto_us_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s02_couplers_to_auto_us_AWVALID : STD_LOGIC; signal s02_couplers_to_auto_us_BREADY : STD_LOGIC; signal s02_couplers_to_auto_us_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s02_couplers_to_auto_us_BVALID : STD_LOGIC; signal s02_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s02_couplers_to_auto_us_RLAST : STD_LOGIC; signal s02_couplers_to_auto_us_RREADY : STD_LOGIC; signal s02_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s02_couplers_to_auto_us_RVALID : STD_LOGIC; signal s02_couplers_to_auto_us_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s02_couplers_to_auto_us_WLAST : STD_LOGIC; signal s02_couplers_to_auto_us_WREADY : STD_LOGIC; signal s02_couplers_to_auto_us_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s02_couplers_to_auto_us_WVALID : STD_LOGIC; signal NLW_auto_us_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_auto_us_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); begin M_AXI_araddr(31 downto 0) <= auto_us_to_s02_couplers_ARADDR(31 downto 0); M_AXI_arburst(1 downto 0) <= auto_us_to_s02_couplers_ARBURST(1 downto 0); M_AXI_arcache(3 downto 0) <= auto_us_to_s02_couplers_ARCACHE(3 downto 0); M_AXI_arlen(7 downto 0) <= auto_us_to_s02_couplers_ARLEN(7 downto 0); M_AXI_arlock(0) <= auto_us_to_s02_couplers_ARLOCK(0); M_AXI_arprot(2 downto 0) <= auto_us_to_s02_couplers_ARPROT(2 downto 0); M_AXI_arqos(3 downto 0) <= auto_us_to_s02_couplers_ARQOS(3 downto 0); M_AXI_arsize(2 downto 0) <= auto_us_to_s02_couplers_ARSIZE(2 downto 0); M_AXI_arvalid <= auto_us_to_s02_couplers_ARVALID; M_AXI_awaddr(31 downto 0) <= auto_us_to_s02_couplers_AWADDR(31 downto 0); M_AXI_awburst(1 downto 0) <= auto_us_to_s02_couplers_AWBURST(1 downto 0); M_AXI_awcache(3 downto 0) <= auto_us_to_s02_couplers_AWCACHE(3 downto 0); M_AXI_awlen(7 downto 0) <= auto_us_to_s02_couplers_AWLEN(7 downto 0); M_AXI_awlock(0) <= auto_us_to_s02_couplers_AWLOCK(0); M_AXI_awprot(2 downto 0) <= auto_us_to_s02_couplers_AWPROT(2 downto 0); M_AXI_awqos(3 downto 0) <= auto_us_to_s02_couplers_AWQOS(3 downto 0); M_AXI_awsize(2 downto 0) <= auto_us_to_s02_couplers_AWSIZE(2 downto 0); M_AXI_awvalid <= auto_us_to_s02_couplers_AWVALID; M_AXI_bready <= auto_us_to_s02_couplers_BREADY; M_AXI_rready <= auto_us_to_s02_couplers_RREADY; M_AXI_wdata(63 downto 0) <= auto_us_to_s02_couplers_WDATA(63 downto 0); M_AXI_wlast <= auto_us_to_s02_couplers_WLAST; M_AXI_wstrb(7 downto 0) <= auto_us_to_s02_couplers_WSTRB(7 downto 0); M_AXI_wvalid <= auto_us_to_s02_couplers_WVALID; S_ACLK_1 <= S_ACLK; S_ARESETN_1(0) <= S_ARESETN(0); S_AXI_arready <= s02_couplers_to_auto_us_ARREADY; S_AXI_awready <= s02_couplers_to_auto_us_AWREADY; S_AXI_bresp(1 downto 0) <= s02_couplers_to_auto_us_BRESP(1 downto 0); S_AXI_bvalid <= s02_couplers_to_auto_us_BVALID; S_AXI_rdata(31 downto 0) <= s02_couplers_to_auto_us_RDATA(31 downto 0); S_AXI_rlast <= s02_couplers_to_auto_us_RLAST; S_AXI_rresp(1 downto 0) <= s02_couplers_to_auto_us_RRESP(1 downto 0); S_AXI_rvalid <= s02_couplers_to_auto_us_RVALID; S_AXI_wready <= s02_couplers_to_auto_us_WREADY; auto_us_to_s02_couplers_ARREADY <= M_AXI_arready; auto_us_to_s02_couplers_AWREADY <= M_AXI_awready; auto_us_to_s02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); auto_us_to_s02_couplers_BVALID <= M_AXI_bvalid; auto_us_to_s02_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0); auto_us_to_s02_couplers_RLAST <= M_AXI_rlast; auto_us_to_s02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); auto_us_to_s02_couplers_RVALID <= M_AXI_rvalid; auto_us_to_s02_couplers_WREADY <= M_AXI_wready; s02_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); s02_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); s02_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); s02_couplers_to_auto_us_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0); s02_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); s02_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); s02_couplers_to_auto_us_ARVALID <= S_AXI_arvalid; s02_couplers_to_auto_us_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); s02_couplers_to_auto_us_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); s02_couplers_to_auto_us_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); s02_couplers_to_auto_us_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0); s02_couplers_to_auto_us_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); s02_couplers_to_auto_us_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); s02_couplers_to_auto_us_AWVALID <= S_AXI_awvalid; s02_couplers_to_auto_us_BREADY <= S_AXI_bready; s02_couplers_to_auto_us_RREADY <= S_AXI_rready; s02_couplers_to_auto_us_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); s02_couplers_to_auto_us_WLAST <= S_AXI_wlast; s02_couplers_to_auto_us_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); s02_couplers_to_auto_us_WVALID <= S_AXI_wvalid; GND: unisim.vcomponents.GND port map ( G => GND_1 ); auto_us: component triangle_intersect_auto_us_2 port map ( m_axi_araddr(31 downto 0) => auto_us_to_s02_couplers_ARADDR(31 downto 0), m_axi_arburst(1 downto 0) => auto_us_to_s02_couplers_ARBURST(1 downto 0), m_axi_arcache(3 downto 0) => auto_us_to_s02_couplers_ARCACHE(3 downto 0), m_axi_arlen(7 downto 0) => auto_us_to_s02_couplers_ARLEN(7 downto 0), m_axi_arlock(0) => auto_us_to_s02_couplers_ARLOCK(0), m_axi_arprot(2 downto 0) => auto_us_to_s02_couplers_ARPROT(2 downto 0), m_axi_arqos(3 downto 0) => auto_us_to_s02_couplers_ARQOS(3 downto 0), m_axi_arready => auto_us_to_s02_couplers_ARREADY, m_axi_arregion(3 downto 0) => NLW_auto_us_m_axi_arregion_UNCONNECTED(3 downto 0), m_axi_arsize(2 downto 0) => auto_us_to_s02_couplers_ARSIZE(2 downto 0), m_axi_arvalid => auto_us_to_s02_couplers_ARVALID, m_axi_awaddr(31 downto 0) => auto_us_to_s02_couplers_AWADDR(31 downto 0), m_axi_awburst(1 downto 0) => auto_us_to_s02_couplers_AWBURST(1 downto 0), m_axi_awcache(3 downto 0) => auto_us_to_s02_couplers_AWCACHE(3 downto 0), m_axi_awlen(7 downto 0) => auto_us_to_s02_couplers_AWLEN(7 downto 0), m_axi_awlock(0) => auto_us_to_s02_couplers_AWLOCK(0), m_axi_awprot(2 downto 0) => auto_us_to_s02_couplers_AWPROT(2 downto 0), m_axi_awqos(3 downto 0) => auto_us_to_s02_couplers_AWQOS(3 downto 0), m_axi_awready => auto_us_to_s02_couplers_AWREADY, m_axi_awregion(3 downto 0) => NLW_auto_us_m_axi_awregion_UNCONNECTED(3 downto 0), m_axi_awsize(2 downto 0) => auto_us_to_s02_couplers_AWSIZE(2 downto 0), m_axi_awvalid => auto_us_to_s02_couplers_AWVALID, m_axi_bready => auto_us_to_s02_couplers_BREADY, m_axi_bresp(1 downto 0) => auto_us_to_s02_couplers_BRESP(1 downto 0), m_axi_bvalid => auto_us_to_s02_couplers_BVALID, m_axi_rdata(63 downto 0) => auto_us_to_s02_couplers_RDATA(63 downto 0), m_axi_rlast => auto_us_to_s02_couplers_RLAST, m_axi_rready => auto_us_to_s02_couplers_RREADY, m_axi_rresp(1 downto 0) => auto_us_to_s02_couplers_RRESP(1 downto 0), m_axi_rvalid => auto_us_to_s02_couplers_RVALID, m_axi_wdata(63 downto 0) => auto_us_to_s02_couplers_WDATA(63 downto 0), m_axi_wlast => auto_us_to_s02_couplers_WLAST, m_axi_wready => auto_us_to_s02_couplers_WREADY, m_axi_wstrb(7 downto 0) => auto_us_to_s02_couplers_WSTRB(7 downto 0), m_axi_wvalid => auto_us_to_s02_couplers_WVALID, s_axi_aclk => S_ACLK_1, s_axi_araddr(31 downto 0) => s02_couplers_to_auto_us_ARADDR(31 downto 0), s_axi_arburst(1 downto 0) => s02_couplers_to_auto_us_ARBURST(1 downto 0), s_axi_arcache(3 downto 0) => s02_couplers_to_auto_us_ARCACHE(3 downto 0), s_axi_aresetn => S_ARESETN_1(0), s_axi_arlen(7 downto 0) => s02_couplers_to_auto_us_ARLEN(7 downto 0), s_axi_arlock(0) => GND_1, s_axi_arprot(2 downto 0) => s02_couplers_to_auto_us_ARPROT(2 downto 0), s_axi_arqos(3) => GND_1, s_axi_arqos(2) => GND_1, s_axi_arqos(1) => GND_1, s_axi_arqos(0) => GND_1, s_axi_arready => s02_couplers_to_auto_us_ARREADY, s_axi_arregion(3) => GND_1, s_axi_arregion(2) => GND_1, s_axi_arregion(1) => GND_1, s_axi_arregion(0) => GND_1, s_axi_arsize(2 downto 0) => s02_couplers_to_auto_us_ARSIZE(2 downto 0), s_axi_arvalid => s02_couplers_to_auto_us_ARVALID, s_axi_awaddr(31 downto 0) => s02_couplers_to_auto_us_AWADDR(31 downto 0), s_axi_awburst(1 downto 0) => s02_couplers_to_auto_us_AWBURST(1 downto 0), s_axi_awcache(3 downto 0) => s02_couplers_to_auto_us_AWCACHE(3 downto 0), s_axi_awlen(7 downto 0) => s02_couplers_to_auto_us_AWLEN(7 downto 0), s_axi_awlock(0) => GND_1, s_axi_awprot(2 downto 0) => s02_couplers_to_auto_us_AWPROT(2 downto 0), s_axi_awqos(3) => GND_1, s_axi_awqos(2) => GND_1, s_axi_awqos(1) => GND_1, s_axi_awqos(0) => GND_1, s_axi_awready => s02_couplers_to_auto_us_AWREADY, s_axi_awregion(3) => GND_1, s_axi_awregion(2) => GND_1, s_axi_awregion(1) => GND_1, s_axi_awregion(0) => GND_1, s_axi_awsize(2 downto 0) => s02_couplers_to_auto_us_AWSIZE(2 downto 0), s_axi_awvalid => s02_couplers_to_auto_us_AWVALID, s_axi_bready => s02_couplers_to_auto_us_BREADY, s_axi_bresp(1 downto 0) => s02_couplers_to_auto_us_BRESP(1 downto 0), s_axi_bvalid => s02_couplers_to_auto_us_BVALID, s_axi_rdata(31 downto 0) => s02_couplers_to_auto_us_RDATA(31 downto 0), s_axi_rlast => s02_couplers_to_auto_us_RLAST, s_axi_rready => s02_couplers_to_auto_us_RREADY, s_axi_rresp(1 downto 0) => s02_couplers_to_auto_us_RRESP(1 downto 0), s_axi_rvalid => s02_couplers_to_auto_us_RVALID, s_axi_wdata(31 downto 0) => s02_couplers_to_auto_us_WDATA(31 downto 0), s_axi_wlast => s02_couplers_to_auto_us_WLAST, s_axi_wready => s02_couplers_to_auto_us_WREADY, s_axi_wstrb(3 downto 0) => s02_couplers_to_auto_us_WSTRB(3 downto 0), s_axi_wvalid => s02_couplers_to_auto_us_WVALID ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity triangle_intersect_axi_mem_intercon_0 is port ( ACLK : in STD_LOGIC; ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M00_ACLK : in STD_LOGIC; M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M00_AXI_arid : out STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); M00_AXI_arready : in STD_LOGIC; M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M00_AXI_arvalid : out STD_LOGIC; M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); M00_AXI_awid : out STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); M00_AXI_awready : in STD_LOGIC; M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M00_AXI_awvalid : out STD_LOGIC; M00_AXI_bid : in STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_bready : out STD_LOGIC; M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_bvalid : in STD_LOGIC; M00_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); M00_AXI_rid : in STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_rlast : in STD_LOGIC; M00_AXI_rready : out STD_LOGIC; M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_rvalid : in STD_LOGIC; M00_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); M00_AXI_wid : out STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_wlast : out STD_LOGIC; M00_AXI_wready : in STD_LOGIC; M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); M00_AXI_wvalid : out STD_LOGIC; S00_ACLK : in STD_LOGIC; S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_arready : out STD_LOGIC; S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_arvalid : in STD_LOGIC; S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_rlast : out STD_LOGIC; S00_AXI_rready : in STD_LOGIC; S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_rvalid : out STD_LOGIC; S01_ACLK : in STD_LOGIC; S01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S01_AXI_awready : out STD_LOGIC; S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S01_AXI_awvalid : in STD_LOGIC; S01_AXI_bready : in STD_LOGIC; S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S01_AXI_bvalid : out STD_LOGIC; S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S01_AXI_wlast : in STD_LOGIC; S01_AXI_wready : out STD_LOGIC; S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S01_AXI_wvalid : in STD_LOGIC; S02_ACLK : in STD_LOGIC; S02_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S02_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S02_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S02_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S02_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S02_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S02_AXI_arready : out STD_LOGIC; S02_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S02_AXI_arvalid : in STD_LOGIC; S02_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S02_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S02_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S02_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); S02_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S02_AXI_awready : out STD_LOGIC; S02_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S02_AXI_awvalid : in STD_LOGIC; S02_AXI_bready : in STD_LOGIC; S02_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S02_AXI_bvalid : out STD_LOGIC; S02_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S02_AXI_rlast : out STD_LOGIC; S02_AXI_rready : in STD_LOGIC; S02_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S02_AXI_rvalid : out STD_LOGIC; S02_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S02_AXI_wlast : in STD_LOGIC; S02_AXI_wready : out STD_LOGIC; S02_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S02_AXI_wvalid : in STD_LOGIC ); end triangle_intersect_axi_mem_intercon_0; architecture STRUCTURE of triangle_intersect_axi_mem_intercon_0 is component triangle_intersect_xbar_0 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 95 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 23 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 8 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 8 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awvalid : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awready : out STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 191 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 23 downto 0 ); s_axi_wlast : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_wvalid : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_wready : out STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_bvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_bready : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 95 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 23 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 8 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 8 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arvalid : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arready : out STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 191 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_rlast : out STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_rvalid : out STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_rready : in STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awid : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_bid : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arid : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rid : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 ) ); end component triangle_intersect_xbar_0; signal GND_1 : STD_LOGIC; signal M00_ACLK_1 : STD_LOGIC; signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal S00_ACLK_1 : STD_LOGIC; signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal S01_ACLK_1 : STD_LOGIC; signal S01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal S02_ACLK_1 : STD_LOGIC; signal S02_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal VCC_1 : STD_LOGIC; signal axi_mem_intercon_ACLK_net : STD_LOGIC; signal axi_mem_intercon_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 ); signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC; signal axi_mem_intercon_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axi_mem_intercon_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_to_s01_couplers_AWREADY : STD_LOGIC; signal axi_mem_intercon_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_to_s01_couplers_AWVALID : STD_LOGIC; signal axi_mem_intercon_to_s01_couplers_BREADY : STD_LOGIC; signal axi_mem_intercon_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_to_s01_couplers_BVALID : STD_LOGIC; signal axi_mem_intercon_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_to_s01_couplers_WLAST : STD_LOGIC; signal axi_mem_intercon_to_s01_couplers_WREADY : STD_LOGIC; signal axi_mem_intercon_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_to_s01_couplers_WVALID : STD_LOGIC; signal axi_mem_intercon_to_s02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_to_s02_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_to_s02_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_to_s02_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axi_mem_intercon_to_s02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_to_s02_couplers_ARREADY : STD_LOGIC; signal axi_mem_intercon_to_s02_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_to_s02_couplers_ARVALID : STD_LOGIC; signal axi_mem_intercon_to_s02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_to_s02_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_to_s02_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_to_s02_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axi_mem_intercon_to_s02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_to_s02_couplers_AWREADY : STD_LOGIC; signal axi_mem_intercon_to_s02_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_to_s02_couplers_AWVALID : STD_LOGIC; signal axi_mem_intercon_to_s02_couplers_BREADY : STD_LOGIC; signal axi_mem_intercon_to_s02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_to_s02_couplers_BVALID : STD_LOGIC; signal axi_mem_intercon_to_s02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_to_s02_couplers_RLAST : STD_LOGIC; signal axi_mem_intercon_to_s02_couplers_RREADY : STD_LOGIC; signal axi_mem_intercon_to_s02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_to_s02_couplers_RVALID : STD_LOGIC; signal axi_mem_intercon_to_s02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_to_s02_couplers_WLAST : STD_LOGIC; signal axi_mem_intercon_to_s02_couplers_WREADY : STD_LOGIC; signal axi_mem_intercon_to_s02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_to_s02_couplers_WVALID : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_axi_mem_intercon_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal m00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_axi_mem_intercon_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal m00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal m00_couplers_to_axi_mem_intercon_WID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC; signal m00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); signal m00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC; signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s00_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 ); signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_couplers_to_xbar_ARVALID : STD_LOGIC; signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 ); signal s00_couplers_to_xbar_RREADY : STD_LOGIC; signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 ); signal s01_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s01_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s01_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s01_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s01_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal s01_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s01_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s01_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 1 to 1 ); signal s01_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s01_couplers_to_xbar_AWVALID : STD_LOGIC; signal s01_couplers_to_xbar_BREADY : STD_LOGIC; signal s01_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 3 downto 2 ); signal s01_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 1 to 1 ); signal s01_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal s01_couplers_to_xbar_WLAST : STD_LOGIC; signal s01_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 1 to 1 ); signal s01_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s01_couplers_to_xbar_WVALID : STD_LOGIC; signal s02_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s02_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s02_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s02_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s02_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal s02_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s02_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s02_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 2 to 2 ); signal s02_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s02_couplers_to_xbar_ARVALID : STD_LOGIC; signal s02_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s02_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s02_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s02_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s02_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal s02_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s02_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s02_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 2 to 2 ); signal s02_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s02_couplers_to_xbar_AWVALID : STD_LOGIC; signal s02_couplers_to_xbar_BREADY : STD_LOGIC; signal s02_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 5 downto 4 ); signal s02_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 2 to 2 ); signal s02_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 191 downto 128 ); signal s02_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 2 to 2 ); signal s02_couplers_to_xbar_RREADY : STD_LOGIC; signal s02_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 5 downto 4 ); signal s02_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 2 to 2 ); signal s02_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal s02_couplers_to_xbar_WLAST : STD_LOGIC; signal s02_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 2 to 2 ); signal s02_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s02_couplers_to_xbar_WVALID : STD_LOGIC; signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal xbar_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal xbar_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal xbar_to_m00_couplers_ARREADY : STD_LOGIC; signal xbar_to_m00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal xbar_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal xbar_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal xbar_to_m00_couplers_AWREADY : STD_LOGIC; signal xbar_to_m00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m00_couplers_BVALID : STD_LOGIC; signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal xbar_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m00_couplers_RLAST : STD_LOGIC; signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal xbar_to_m00_couplers_RVALID : STD_LOGIC; signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m00_couplers_WREADY : STD_LOGIC; signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_xbar_s_axi_arready_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_xbar_s_axi_awready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_xbar_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_xbar_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_xbar_s_axi_bvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_xbar_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 64 ); signal NLW_xbar_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_xbar_s_axi_rlast_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_xbar_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); signal NLW_xbar_s_axi_rvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_xbar_s_axi_wready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); begin M00_ACLK_1 <= M00_ACLK; M00_ARESETN_1(0) <= M00_ARESETN(0); M00_AXI_araddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0); M00_AXI_arburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0); M00_AXI_arcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0); M00_AXI_arid(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARID(1 downto 0); M00_AXI_arlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0); M00_AXI_arlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0); M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0); M00_AXI_arqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0); M00_AXI_arsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0); M00_AXI_arvalid <= m00_couplers_to_axi_mem_intercon_ARVALID; M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0); M00_AXI_awburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0); M00_AXI_awcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0); M00_AXI_awid(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWID(1 downto 0); M00_AXI_awlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0); M00_AXI_awlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0); M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0); M00_AXI_awqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0); M00_AXI_awsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0); M00_AXI_awvalid <= m00_couplers_to_axi_mem_intercon_AWVALID; M00_AXI_bready <= m00_couplers_to_axi_mem_intercon_BREADY; M00_AXI_rready <= m00_couplers_to_axi_mem_intercon_RREADY; M00_AXI_wdata(63 downto 0) <= m00_couplers_to_axi_mem_intercon_WDATA(63 downto 0); M00_AXI_wid(1 downto 0) <= m00_couplers_to_axi_mem_intercon_WID(1 downto 0); M00_AXI_wlast <= m00_couplers_to_axi_mem_intercon_WLAST; M00_AXI_wstrb(7 downto 0) <= m00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0); M00_AXI_wvalid <= m00_couplers_to_axi_mem_intercon_WVALID; S00_ACLK_1 <= S00_ACLK; S00_ARESETN_1(0) <= S00_ARESETN(0); S00_AXI_arready <= axi_mem_intercon_to_s00_couplers_ARREADY; S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0); S00_AXI_rlast <= axi_mem_intercon_to_s00_couplers_RLAST; S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0); S00_AXI_rvalid <= axi_mem_intercon_to_s00_couplers_RVALID; S01_ACLK_1 <= S01_ACLK; S01_ARESETN_1(0) <= S01_ARESETN(0); S01_AXI_awready <= axi_mem_intercon_to_s01_couplers_AWREADY; S01_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0); S01_AXI_bvalid <= axi_mem_intercon_to_s01_couplers_BVALID; S01_AXI_wready <= axi_mem_intercon_to_s01_couplers_WREADY; S02_ACLK_1 <= S02_ACLK; S02_ARESETN_1(0) <= S02_ARESETN(0); S02_AXI_arready <= axi_mem_intercon_to_s02_couplers_ARREADY; S02_AXI_awready <= axi_mem_intercon_to_s02_couplers_AWREADY; S02_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s02_couplers_BRESP(1 downto 0); S02_AXI_bvalid <= axi_mem_intercon_to_s02_couplers_BVALID; S02_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s02_couplers_RDATA(31 downto 0); S02_AXI_rlast <= axi_mem_intercon_to_s02_couplers_RLAST; S02_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s02_couplers_RRESP(1 downto 0); S02_AXI_rvalid <= axi_mem_intercon_to_s02_couplers_RVALID; S02_AXI_wready <= axi_mem_intercon_to_s02_couplers_WREADY; axi_mem_intercon_ACLK_net <= ACLK; axi_mem_intercon_ARESETN_net(0) <= ARESETN(0); axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0); axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0); axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0); axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0); axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0); axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0); axi_mem_intercon_to_s00_couplers_ARVALID <= S00_AXI_arvalid; axi_mem_intercon_to_s00_couplers_RREADY <= S00_AXI_rready; axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0) <= S01_AXI_awaddr(31 downto 0); axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0) <= S01_AXI_awburst(1 downto 0); axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0) <= S01_AXI_awcache(3 downto 0); axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0) <= S01_AXI_awlen(7 downto 0); axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0) <= S01_AXI_awprot(2 downto 0); axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0) <= S01_AXI_awsize(2 downto 0); axi_mem_intercon_to_s01_couplers_AWVALID <= S01_AXI_awvalid; axi_mem_intercon_to_s01_couplers_BREADY <= S01_AXI_bready; axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0) <= S01_AXI_wdata(31 downto 0); axi_mem_intercon_to_s01_couplers_WLAST <= S01_AXI_wlast; axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0) <= S01_AXI_wstrb(3 downto 0); axi_mem_intercon_to_s01_couplers_WVALID <= S01_AXI_wvalid; axi_mem_intercon_to_s02_couplers_ARADDR(31 downto 0) <= S02_AXI_araddr(31 downto 0); axi_mem_intercon_to_s02_couplers_ARBURST(1 downto 0) <= S02_AXI_arburst(1 downto 0); axi_mem_intercon_to_s02_couplers_ARCACHE(3 downto 0) <= S02_AXI_arcache(3 downto 0); axi_mem_intercon_to_s02_couplers_ARLEN(7 downto 0) <= S02_AXI_arlen(7 downto 0); axi_mem_intercon_to_s02_couplers_ARPROT(2 downto 0) <= S02_AXI_arprot(2 downto 0); axi_mem_intercon_to_s02_couplers_ARSIZE(2 downto 0) <= S02_AXI_arsize(2 downto 0); axi_mem_intercon_to_s02_couplers_ARVALID <= S02_AXI_arvalid; axi_mem_intercon_to_s02_couplers_AWADDR(31 downto 0) <= S02_AXI_awaddr(31 downto 0); axi_mem_intercon_to_s02_couplers_AWBURST(1 downto 0) <= S02_AXI_awburst(1 downto 0); axi_mem_intercon_to_s02_couplers_AWCACHE(3 downto 0) <= S02_AXI_awcache(3 downto 0); axi_mem_intercon_to_s02_couplers_AWLEN(7 downto 0) <= S02_AXI_awlen(7 downto 0); axi_mem_intercon_to_s02_couplers_AWPROT(2 downto 0) <= S02_AXI_awprot(2 downto 0); axi_mem_intercon_to_s02_couplers_AWSIZE(2 downto 0) <= S02_AXI_awsize(2 downto 0); axi_mem_intercon_to_s02_couplers_AWVALID <= S02_AXI_awvalid; axi_mem_intercon_to_s02_couplers_BREADY <= S02_AXI_bready; axi_mem_intercon_to_s02_couplers_RREADY <= S02_AXI_rready; axi_mem_intercon_to_s02_couplers_WDATA(31 downto 0) <= S02_AXI_wdata(31 downto 0); axi_mem_intercon_to_s02_couplers_WLAST <= S02_AXI_wlast; axi_mem_intercon_to_s02_couplers_WSTRB(3 downto 0) <= S02_AXI_wstrb(3 downto 0); axi_mem_intercon_to_s02_couplers_WVALID <= S02_AXI_wvalid; m00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready; m00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready; m00_couplers_to_axi_mem_intercon_BID(1 downto 0) <= M00_AXI_bid(1 downto 0); m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0); m00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid; m00_couplers_to_axi_mem_intercon_RDATA(63 downto 0) <= M00_AXI_rdata(63 downto 0); m00_couplers_to_axi_mem_intercon_RID(1 downto 0) <= M00_AXI_rid(1 downto 0); m00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast; m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0); m00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid; m00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready; GND: unisim.vcomponents.GND port map ( G => GND_1 ); VCC: unisim.vcomponents.VCC port map ( P => VCC_1 ); m00_couplers: entity work.m00_couplers_imp_YCVYZF port map ( M_ACLK => M00_ACLK_1, M_ARESETN(0) => M00_ARESETN_1(0), M_AXI_araddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0), M_AXI_arburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0), M_AXI_arcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0), M_AXI_arid(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARID(1 downto 0), M_AXI_arlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0), M_AXI_arlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0), M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0), M_AXI_arqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0), M_AXI_arready => m00_couplers_to_axi_mem_intercon_ARREADY, M_AXI_arsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0), M_AXI_arvalid => m00_couplers_to_axi_mem_intercon_ARVALID, M_AXI_awaddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0), M_AXI_awburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0), M_AXI_awcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0), M_AXI_awid(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWID(1 downto 0), M_AXI_awlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0), M_AXI_awlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0), M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0), M_AXI_awqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0), M_AXI_awready => m00_couplers_to_axi_mem_intercon_AWREADY, M_AXI_awsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0), M_AXI_awvalid => m00_couplers_to_axi_mem_intercon_AWVALID, M_AXI_bid(1 downto 0) => m00_couplers_to_axi_mem_intercon_BID(1 downto 0), M_AXI_bready => m00_couplers_to_axi_mem_intercon_BREADY, M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0), M_AXI_bvalid => m00_couplers_to_axi_mem_intercon_BVALID, M_AXI_rdata(63 downto 0) => m00_couplers_to_axi_mem_intercon_RDATA(63 downto 0), M_AXI_rid(1 downto 0) => m00_couplers_to_axi_mem_intercon_RID(1 downto 0), M_AXI_rlast => m00_couplers_to_axi_mem_intercon_RLAST, M_AXI_rready => m00_couplers_to_axi_mem_intercon_RREADY, M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0), M_AXI_rvalid => m00_couplers_to_axi_mem_intercon_RVALID, M_AXI_wdata(63 downto 0) => m00_couplers_to_axi_mem_intercon_WDATA(63 downto 0), M_AXI_wid(1 downto 0) => m00_couplers_to_axi_mem_intercon_WID(1 downto 0), M_AXI_wlast => m00_couplers_to_axi_mem_intercon_WLAST, M_AXI_wready => m00_couplers_to_axi_mem_intercon_WREADY, M_AXI_wstrb(7 downto 0) => m00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0), M_AXI_wvalid => m00_couplers_to_axi_mem_intercon_WVALID, S_ACLK => axi_mem_intercon_ACLK_net, S_ARESETN(0) => axi_mem_intercon_ARESETN_net(0), S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0), S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0), S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0), S_AXI_arid(1 downto 0) => xbar_to_m00_couplers_ARID(1 downto 0), S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0), S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0), S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0), S_AXI_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0), S_AXI_arready => xbar_to_m00_couplers_ARREADY, S_AXI_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0), S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0), S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0), S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0), S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0), S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0), S_AXI_awid(1 downto 0) => xbar_to_m00_couplers_AWID(1 downto 0), S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0), S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0), S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0), S_AXI_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0), S_AXI_awready => xbar_to_m00_couplers_AWREADY, S_AXI_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0), S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0), S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0), S_AXI_bid(1 downto 0) => xbar_to_m00_couplers_BID(1 downto 0), S_AXI_bready => xbar_to_m00_couplers_BREADY(0), S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0), S_AXI_bvalid => xbar_to_m00_couplers_BVALID, S_AXI_rdata(63 downto 0) => xbar_to_m00_couplers_RDATA(63 downto 0), S_AXI_rid(1 downto 0) => xbar_to_m00_couplers_RID(1 downto 0), S_AXI_rlast => xbar_to_m00_couplers_RLAST, S_AXI_rready => xbar_to_m00_couplers_RREADY(0), S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0), S_AXI_rvalid => xbar_to_m00_couplers_RVALID, S_AXI_wdata(63 downto 0) => xbar_to_m00_couplers_WDATA(63 downto 0), S_AXI_wlast => xbar_to_m00_couplers_WLAST(0), S_AXI_wready => xbar_to_m00_couplers_WREADY, S_AXI_wstrb(7 downto 0) => xbar_to_m00_couplers_WSTRB(7 downto 0), S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0) ); s00_couplers: entity work.s00_couplers_imp_1FME12G port map ( M_ACLK => axi_mem_intercon_ACLK_net, M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0), M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0), M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0), M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0), M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0), M_AXI_arlock(0) => s00_couplers_to_xbar_ARLOCK(0), M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0), M_AXI_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0), M_AXI_arready => s00_couplers_to_xbar_ARREADY(0), M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0), M_AXI_arvalid => s00_couplers_to_xbar_ARVALID, M_AXI_rdata(63 downto 0) => s00_couplers_to_xbar_RDATA(63 downto 0), M_AXI_rlast => s00_couplers_to_xbar_RLAST(0), M_AXI_rready => s00_couplers_to_xbar_RREADY, M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0), M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0), S_ACLK => S00_ACLK_1, S_ARESETN(0) => S00_ARESETN_1(0), S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0), S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0), S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0), S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0), S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0), S_AXI_arready => axi_mem_intercon_to_s00_couplers_ARREADY, S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0), S_AXI_arvalid => axi_mem_intercon_to_s00_couplers_ARVALID, S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0), S_AXI_rlast => axi_mem_intercon_to_s00_couplers_RLAST, S_AXI_rready => axi_mem_intercon_to_s00_couplers_RREADY, S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0), S_AXI_rvalid => axi_mem_intercon_to_s00_couplers_RVALID ); s01_couplers: entity work.s01_couplers_imp_1G34NP1 port map ( M_ACLK => axi_mem_intercon_ACLK_net, M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0), M_AXI_awaddr(31 downto 0) => s01_couplers_to_xbar_AWADDR(31 downto 0), M_AXI_awburst(1 downto 0) => s01_couplers_to_xbar_AWBURST(1 downto 0), M_AXI_awcache(3 downto 0) => s01_couplers_to_xbar_AWCACHE(3 downto 0), M_AXI_awlen(7 downto 0) => s01_couplers_to_xbar_AWLEN(7 downto 0), M_AXI_awlock(0) => s01_couplers_to_xbar_AWLOCK(0), M_AXI_awprot(2 downto 0) => s01_couplers_to_xbar_AWPROT(2 downto 0), M_AXI_awqos(3 downto 0) => s01_couplers_to_xbar_AWQOS(3 downto 0), M_AXI_awready => s01_couplers_to_xbar_AWREADY(1), M_AXI_awsize(2 downto 0) => s01_couplers_to_xbar_AWSIZE(2 downto 0), M_AXI_awvalid => s01_couplers_to_xbar_AWVALID, M_AXI_bready => s01_couplers_to_xbar_BREADY, M_AXI_bresp(1 downto 0) => s01_couplers_to_xbar_BRESP(3 downto 2), M_AXI_bvalid => s01_couplers_to_xbar_BVALID(1), M_AXI_wdata(63 downto 0) => s01_couplers_to_xbar_WDATA(63 downto 0), M_AXI_wlast => s01_couplers_to_xbar_WLAST, M_AXI_wready => s01_couplers_to_xbar_WREADY(1), M_AXI_wstrb(7 downto 0) => s01_couplers_to_xbar_WSTRB(7 downto 0), M_AXI_wvalid => s01_couplers_to_xbar_WVALID, S_ACLK => S01_ACLK_1, S_ARESETN(0) => S01_ARESETN_1(0), S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0), S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0), S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0), S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0), S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0), S_AXI_awready => axi_mem_intercon_to_s01_couplers_AWREADY, S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0), S_AXI_awvalid => axi_mem_intercon_to_s01_couplers_AWVALID, S_AXI_bready => axi_mem_intercon_to_s01_couplers_BREADY, S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0), S_AXI_bvalid => axi_mem_intercon_to_s01_couplers_BVALID, S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0), S_AXI_wlast => axi_mem_intercon_to_s01_couplers_WLAST, S_AXI_wready => axi_mem_intercon_to_s01_couplers_WREADY, S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0), S_AXI_wvalid => axi_mem_intercon_to_s01_couplers_WVALID ); s02_couplers: entity work.s02_couplers_imp_1FFYAJ6 port map ( M_ACLK => axi_mem_intercon_ACLK_net, M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0), M_AXI_araddr(31 downto 0) => s02_couplers_to_xbar_ARADDR(31 downto 0), M_AXI_arburst(1 downto 0) => s02_couplers_to_xbar_ARBURST(1 downto 0), M_AXI_arcache(3 downto 0) => s02_couplers_to_xbar_ARCACHE(3 downto 0), M_AXI_arlen(7 downto 0) => s02_couplers_to_xbar_ARLEN(7 downto 0), M_AXI_arlock(0) => s02_couplers_to_xbar_ARLOCK(0), M_AXI_arprot(2 downto 0) => s02_couplers_to_xbar_ARPROT(2 downto 0), M_AXI_arqos(3 downto 0) => s02_couplers_to_xbar_ARQOS(3 downto 0), M_AXI_arready => s02_couplers_to_xbar_ARREADY(2), M_AXI_arsize(2 downto 0) => s02_couplers_to_xbar_ARSIZE(2 downto 0), M_AXI_arvalid => s02_couplers_to_xbar_ARVALID, M_AXI_awaddr(31 downto 0) => s02_couplers_to_xbar_AWADDR(31 downto 0), M_AXI_awburst(1 downto 0) => s02_couplers_to_xbar_AWBURST(1 downto 0), M_AXI_awcache(3 downto 0) => s02_couplers_to_xbar_AWCACHE(3 downto 0), M_AXI_awlen(7 downto 0) => s02_couplers_to_xbar_AWLEN(7 downto 0), M_AXI_awlock(0) => s02_couplers_to_xbar_AWLOCK(0), M_AXI_awprot(2 downto 0) => s02_couplers_to_xbar_AWPROT(2 downto 0), M_AXI_awqos(3 downto 0) => s02_couplers_to_xbar_AWQOS(3 downto 0), M_AXI_awready => s02_couplers_to_xbar_AWREADY(2), M_AXI_awsize(2 downto 0) => s02_couplers_to_xbar_AWSIZE(2 downto 0), M_AXI_awvalid => s02_couplers_to_xbar_AWVALID, M_AXI_bready => s02_couplers_to_xbar_BREADY, M_AXI_bresp(1 downto 0) => s02_couplers_to_xbar_BRESP(5 downto 4), M_AXI_bvalid => s02_couplers_to_xbar_BVALID(2), M_AXI_rdata(63 downto 0) => s02_couplers_to_xbar_RDATA(191 downto 128), M_AXI_rlast => s02_couplers_to_xbar_RLAST(2), M_AXI_rready => s02_couplers_to_xbar_RREADY, M_AXI_rresp(1 downto 0) => s02_couplers_to_xbar_RRESP(5 downto 4), M_AXI_rvalid => s02_couplers_to_xbar_RVALID(2), M_AXI_wdata(63 downto 0) => s02_couplers_to_xbar_WDATA(63 downto 0), M_AXI_wlast => s02_couplers_to_xbar_WLAST, M_AXI_wready => s02_couplers_to_xbar_WREADY(2), M_AXI_wstrb(7 downto 0) => s02_couplers_to_xbar_WSTRB(7 downto 0), M_AXI_wvalid => s02_couplers_to_xbar_WVALID, S_ACLK => S02_ACLK_1, S_ARESETN(0) => S02_ARESETN_1(0), S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s02_couplers_ARADDR(31 downto 0), S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s02_couplers_ARBURST(1 downto 0), S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s02_couplers_ARCACHE(3 downto 0), S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s02_couplers_ARLEN(7 downto 0), S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s02_couplers_ARPROT(2 downto 0), S_AXI_arready => axi_mem_intercon_to_s02_couplers_ARREADY, S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s02_couplers_ARSIZE(2 downto 0), S_AXI_arvalid => axi_mem_intercon_to_s02_couplers_ARVALID, S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s02_couplers_AWADDR(31 downto 0), S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s02_couplers_AWBURST(1 downto 0), S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s02_couplers_AWCACHE(3 downto 0), S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s02_couplers_AWLEN(7 downto 0), S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s02_couplers_AWPROT(2 downto 0), S_AXI_awready => axi_mem_intercon_to_s02_couplers_AWREADY, S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s02_couplers_AWSIZE(2 downto 0), S_AXI_awvalid => axi_mem_intercon_to_s02_couplers_AWVALID, S_AXI_bready => axi_mem_intercon_to_s02_couplers_BREADY, S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s02_couplers_BRESP(1 downto 0), S_AXI_bvalid => axi_mem_intercon_to_s02_couplers_BVALID, S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s02_couplers_RDATA(31 downto 0), S_AXI_rlast => axi_mem_intercon_to_s02_couplers_RLAST, S_AXI_rready => axi_mem_intercon_to_s02_couplers_RREADY, S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s02_couplers_RRESP(1 downto 0), S_AXI_rvalid => axi_mem_intercon_to_s02_couplers_RVALID, S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s02_couplers_WDATA(31 downto 0), S_AXI_wlast => axi_mem_intercon_to_s02_couplers_WLAST, S_AXI_wready => axi_mem_intercon_to_s02_couplers_WREADY, S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s02_couplers_WSTRB(3 downto 0), S_AXI_wvalid => axi_mem_intercon_to_s02_couplers_WVALID ); xbar: component triangle_intersect_xbar_0 port map ( aclk => axi_mem_intercon_ACLK_net, aresetn => axi_mem_intercon_ARESETN_net(0), m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0), m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0), m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0), m_axi_arid(1 downto 0) => xbar_to_m00_couplers_ARID(1 downto 0), m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0), m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0), m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0), m_axi_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0), m_axi_arready(0) => xbar_to_m00_couplers_ARREADY, m_axi_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0), m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0), m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0), m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0), m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0), m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0), m_axi_awid(1 downto 0) => xbar_to_m00_couplers_AWID(1 downto 0), m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0), m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0), m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0), m_axi_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0), m_axi_awready(0) => xbar_to_m00_couplers_AWREADY, m_axi_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0), m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0), m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0), m_axi_bid(1 downto 0) => xbar_to_m00_couplers_BID(1 downto 0), m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0), m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0), m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID, m_axi_rdata(63 downto 0) => xbar_to_m00_couplers_RDATA(63 downto 0), m_axi_rid(1 downto 0) => xbar_to_m00_couplers_RID(1 downto 0), m_axi_rlast(0) => xbar_to_m00_couplers_RLAST, m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0), m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0), m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID, m_axi_wdata(63 downto 0) => xbar_to_m00_couplers_WDATA(63 downto 0), m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0), m_axi_wready(0) => xbar_to_m00_couplers_WREADY, m_axi_wstrb(7 downto 0) => xbar_to_m00_couplers_WSTRB(7 downto 0), m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0), s_axi_araddr(95 downto 64) => s02_couplers_to_xbar_ARADDR(31 downto 0), s_axi_araddr(63) => GND_1, s_axi_araddr(62) => GND_1, s_axi_araddr(61) => GND_1, s_axi_araddr(60) => GND_1, s_axi_araddr(59) => GND_1, s_axi_araddr(58) => GND_1, s_axi_araddr(57) => GND_1, s_axi_araddr(56) => GND_1, s_axi_araddr(55) => GND_1, s_axi_araddr(54) => GND_1, s_axi_araddr(53) => GND_1, s_axi_araddr(52) => GND_1, s_axi_araddr(51) => GND_1, s_axi_araddr(50) => GND_1, s_axi_araddr(49) => GND_1, s_axi_araddr(48) => GND_1, s_axi_araddr(47) => GND_1, s_axi_araddr(46) => GND_1, s_axi_araddr(45) => GND_1, s_axi_araddr(44) => GND_1, s_axi_araddr(43) => GND_1, s_axi_araddr(42) => GND_1, s_axi_araddr(41) => GND_1, s_axi_araddr(40) => GND_1, s_axi_araddr(39) => GND_1, s_axi_araddr(38) => GND_1, s_axi_araddr(37) => GND_1, s_axi_araddr(36) => GND_1, s_axi_araddr(35) => GND_1, s_axi_araddr(34) => GND_1, s_axi_araddr(33) => GND_1, s_axi_araddr(32) => GND_1, s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0), s_axi_arburst(5 downto 4) => s02_couplers_to_xbar_ARBURST(1 downto 0), s_axi_arburst(3) => GND_1, s_axi_arburst(2) => GND_1, s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0), s_axi_arcache(11 downto 8) => s02_couplers_to_xbar_ARCACHE(3 downto 0), s_axi_arcache(7) => GND_1, s_axi_arcache(6) => GND_1, s_axi_arcache(5) => GND_1, s_axi_arcache(4) => GND_1, s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0), s_axi_arid(5) => GND_1, s_axi_arid(4) => GND_1, s_axi_arid(3) => GND_1, s_axi_arid(2) => GND_1, s_axi_arid(1) => GND_1, s_axi_arid(0) => GND_1, s_axi_arlen(23 downto 16) => s02_couplers_to_xbar_ARLEN(7 downto 0), s_axi_arlen(15) => GND_1, s_axi_arlen(14) => GND_1, s_axi_arlen(13) => GND_1, s_axi_arlen(12) => GND_1, s_axi_arlen(11) => GND_1, s_axi_arlen(10) => GND_1, s_axi_arlen(9) => GND_1, s_axi_arlen(8) => GND_1, s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0), s_axi_arlock(2) => s02_couplers_to_xbar_ARLOCK(0), s_axi_arlock(1) => GND_1, s_axi_arlock(0) => s00_couplers_to_xbar_ARLOCK(0), s_axi_arprot(8 downto 6) => s02_couplers_to_xbar_ARPROT(2 downto 0), s_axi_arprot(5) => GND_1, s_axi_arprot(4) => GND_1, s_axi_arprot(3) => GND_1, s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0), s_axi_arqos(11 downto 8) => s02_couplers_to_xbar_ARQOS(3 downto 0), s_axi_arqos(7) => GND_1, s_axi_arqos(6) => GND_1, s_axi_arqos(5) => GND_1, s_axi_arqos(4) => GND_1, s_axi_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0), s_axi_arready(2) => s02_couplers_to_xbar_ARREADY(2), s_axi_arready(1) => NLW_xbar_s_axi_arready_UNCONNECTED(1), s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0), s_axi_arsize(8 downto 6) => s02_couplers_to_xbar_ARSIZE(2 downto 0), s_axi_arsize(5) => GND_1, s_axi_arsize(4) => GND_1, s_axi_arsize(3) => GND_1, s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0), s_axi_arvalid(2) => s02_couplers_to_xbar_ARVALID, s_axi_arvalid(1) => GND_1, s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID, s_axi_awaddr(95 downto 64) => s02_couplers_to_xbar_AWADDR(31 downto 0), s_axi_awaddr(63 downto 32) => s01_couplers_to_xbar_AWADDR(31 downto 0), s_axi_awaddr(31) => GND_1, s_axi_awaddr(30) => GND_1, s_axi_awaddr(29) => GND_1, s_axi_awaddr(28) => GND_1, s_axi_awaddr(27) => GND_1, s_axi_awaddr(26) => GND_1, s_axi_awaddr(25) => GND_1, s_axi_awaddr(24) => GND_1, s_axi_awaddr(23) => GND_1, s_axi_awaddr(22) => GND_1, s_axi_awaddr(21) => GND_1, s_axi_awaddr(20) => GND_1, s_axi_awaddr(19) => GND_1, s_axi_awaddr(18) => GND_1, s_axi_awaddr(17) => GND_1, s_axi_awaddr(16) => GND_1, s_axi_awaddr(15) => GND_1, s_axi_awaddr(14) => GND_1, s_axi_awaddr(13) => GND_1, s_axi_awaddr(12) => GND_1, s_axi_awaddr(11) => GND_1, s_axi_awaddr(10) => GND_1, s_axi_awaddr(9) => GND_1, s_axi_awaddr(8) => GND_1, s_axi_awaddr(7) => GND_1, s_axi_awaddr(6) => GND_1, s_axi_awaddr(5) => GND_1, s_axi_awaddr(4) => GND_1, s_axi_awaddr(3) => GND_1, s_axi_awaddr(2) => GND_1, s_axi_awaddr(1) => GND_1, s_axi_awaddr(0) => GND_1, s_axi_awburst(5 downto 4) => s02_couplers_to_xbar_AWBURST(1 downto 0), s_axi_awburst(3 downto 2) => s01_couplers_to_xbar_AWBURST(1 downto 0), s_axi_awburst(1) => GND_1, s_axi_awburst(0) => GND_1, s_axi_awcache(11 downto 8) => s02_couplers_to_xbar_AWCACHE(3 downto 0), s_axi_awcache(7 downto 4) => s01_couplers_to_xbar_AWCACHE(3 downto 0), s_axi_awcache(3) => GND_1, s_axi_awcache(2) => GND_1, s_axi_awcache(1) => GND_1, s_axi_awcache(0) => GND_1, s_axi_awid(5) => GND_1, s_axi_awid(4) => GND_1, s_axi_awid(3) => GND_1, s_axi_awid(2) => GND_1, s_axi_awid(1) => GND_1, s_axi_awid(0) => GND_1, s_axi_awlen(23 downto 16) => s02_couplers_to_xbar_AWLEN(7 downto 0), s_axi_awlen(15 downto 8) => s01_couplers_to_xbar_AWLEN(7 downto 0), s_axi_awlen(7) => GND_1, s_axi_awlen(6) => GND_1, s_axi_awlen(5) => GND_1, s_axi_awlen(4) => GND_1, s_axi_awlen(3) => GND_1, s_axi_awlen(2) => GND_1, s_axi_awlen(1) => GND_1, s_axi_awlen(0) => GND_1, s_axi_awlock(2) => s02_couplers_to_xbar_AWLOCK(0), s_axi_awlock(1) => s01_couplers_to_xbar_AWLOCK(0), s_axi_awlock(0) => GND_1, s_axi_awprot(8 downto 6) => s02_couplers_to_xbar_AWPROT(2 downto 0), s_axi_awprot(5 downto 3) => s01_couplers_to_xbar_AWPROT(2 downto 0), s_axi_awprot(2) => GND_1, s_axi_awprot(1) => GND_1, s_axi_awprot(0) => GND_1, s_axi_awqos(11 downto 8) => s02_couplers_to_xbar_AWQOS(3 downto 0), s_axi_awqos(7 downto 4) => s01_couplers_to_xbar_AWQOS(3 downto 0), s_axi_awqos(3) => GND_1, s_axi_awqos(2) => GND_1, s_axi_awqos(1) => GND_1, s_axi_awqos(0) => GND_1, s_axi_awready(2) => s02_couplers_to_xbar_AWREADY(2), s_axi_awready(1) => s01_couplers_to_xbar_AWREADY(1), s_axi_awready(0) => NLW_xbar_s_axi_awready_UNCONNECTED(0), s_axi_awsize(8 downto 6) => s02_couplers_to_xbar_AWSIZE(2 downto 0), s_axi_awsize(5 downto 3) => s01_couplers_to_xbar_AWSIZE(2 downto 0), s_axi_awsize(2) => GND_1, s_axi_awsize(1) => GND_1, s_axi_awsize(0) => GND_1, s_axi_awvalid(2) => s02_couplers_to_xbar_AWVALID, s_axi_awvalid(1) => s01_couplers_to_xbar_AWVALID, s_axi_awvalid(0) => GND_1, s_axi_bid(5 downto 0) => NLW_xbar_s_axi_bid_UNCONNECTED(5 downto 0), s_axi_bready(2) => s02_couplers_to_xbar_BREADY, s_axi_bready(1) => s01_couplers_to_xbar_BREADY, s_axi_bready(0) => GND_1, s_axi_bresp(5 downto 4) => s02_couplers_to_xbar_BRESP(5 downto 4), s_axi_bresp(3 downto 2) => s01_couplers_to_xbar_BRESP(3 downto 2), s_axi_bresp(1 downto 0) => NLW_xbar_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid(2) => s02_couplers_to_xbar_BVALID(2), s_axi_bvalid(1) => s01_couplers_to_xbar_BVALID(1), s_axi_bvalid(0) => NLW_xbar_s_axi_bvalid_UNCONNECTED(0), s_axi_rdata(191 downto 128) => s02_couplers_to_xbar_RDATA(191 downto 128), s_axi_rdata(127 downto 64) => NLW_xbar_s_axi_rdata_UNCONNECTED(127 downto 64), s_axi_rdata(63 downto 0) => s00_couplers_to_xbar_RDATA(63 downto 0), s_axi_rid(5 downto 0) => NLW_xbar_s_axi_rid_UNCONNECTED(5 downto 0), s_axi_rlast(2) => s02_couplers_to_xbar_RLAST(2), s_axi_rlast(1) => NLW_xbar_s_axi_rlast_UNCONNECTED(1), s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0), s_axi_rready(2) => s02_couplers_to_xbar_RREADY, s_axi_rready(1) => GND_1, s_axi_rready(0) => s00_couplers_to_xbar_RREADY, s_axi_rresp(5 downto 4) => s02_couplers_to_xbar_RRESP(5 downto 4), s_axi_rresp(3 downto 2) => NLW_xbar_s_axi_rresp_UNCONNECTED(3 downto 2), s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0), s_axi_rvalid(2) => s02_couplers_to_xbar_RVALID(2), s_axi_rvalid(1) => NLW_xbar_s_axi_rvalid_UNCONNECTED(1), s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0), s_axi_wdata(191 downto 128) => s02_couplers_to_xbar_WDATA(63 downto 0), s_axi_wdata(127 downto 64) => s01_couplers_to_xbar_WDATA(63 downto 0), s_axi_wdata(63) => GND_1, s_axi_wdata(62) => GND_1, s_axi_wdata(61) => GND_1, s_axi_wdata(60) => GND_1, s_axi_wdata(59) => GND_1, s_axi_wdata(58) => GND_1, s_axi_wdata(57) => GND_1, s_axi_wdata(56) => GND_1, s_axi_wdata(55) => GND_1, s_axi_wdata(54) => GND_1, s_axi_wdata(53) => GND_1, s_axi_wdata(52) => GND_1, s_axi_wdata(51) => GND_1, s_axi_wdata(50) => GND_1, s_axi_wdata(49) => GND_1, s_axi_wdata(48) => GND_1, s_axi_wdata(47) => GND_1, s_axi_wdata(46) => GND_1, s_axi_wdata(45) => GND_1, s_axi_wdata(44) => GND_1, s_axi_wdata(43) => GND_1, s_axi_wdata(42) => GND_1, s_axi_wdata(41) => GND_1, s_axi_wdata(40) => GND_1, s_axi_wdata(39) => GND_1, s_axi_wdata(38) => GND_1, s_axi_wdata(37) => GND_1, s_axi_wdata(36) => GND_1, s_axi_wdata(35) => GND_1, s_axi_wdata(34) => GND_1, s_axi_wdata(33) => GND_1, s_axi_wdata(32) => GND_1, s_axi_wdata(31) => GND_1, s_axi_wdata(30) => GND_1, s_axi_wdata(29) => GND_1, s_axi_wdata(28) => GND_1, s_axi_wdata(27) => GND_1, s_axi_wdata(26) => GND_1, s_axi_wdata(25) => GND_1, s_axi_wdata(24) => GND_1, s_axi_wdata(23) => GND_1, s_axi_wdata(22) => GND_1, s_axi_wdata(21) => GND_1, s_axi_wdata(20) => GND_1, s_axi_wdata(19) => GND_1, s_axi_wdata(18) => GND_1, s_axi_wdata(17) => GND_1, s_axi_wdata(16) => GND_1, s_axi_wdata(15) => GND_1, s_axi_wdata(14) => GND_1, s_axi_wdata(13) => GND_1, s_axi_wdata(12) => GND_1, s_axi_wdata(11) => GND_1, s_axi_wdata(10) => GND_1, s_axi_wdata(9) => GND_1, s_axi_wdata(8) => GND_1, s_axi_wdata(7) => GND_1, s_axi_wdata(6) => GND_1, s_axi_wdata(5) => GND_1, s_axi_wdata(4) => GND_1, s_axi_wdata(3) => GND_1, s_axi_wdata(2) => GND_1, s_axi_wdata(1) => GND_1, s_axi_wdata(0) => GND_1, s_axi_wlast(2) => s02_couplers_to_xbar_WLAST, s_axi_wlast(1) => s01_couplers_to_xbar_WLAST, s_axi_wlast(0) => VCC_1, s_axi_wready(2) => s02_couplers_to_xbar_WREADY(2), s_axi_wready(1) => s01_couplers_to_xbar_WREADY(1), s_axi_wready(0) => NLW_xbar_s_axi_wready_UNCONNECTED(0), s_axi_wstrb(23 downto 16) => s02_couplers_to_xbar_WSTRB(7 downto 0), s_axi_wstrb(15 downto 8) => s01_couplers_to_xbar_WSTRB(7 downto 0), s_axi_wstrb(7) => VCC_1, s_axi_wstrb(6) => VCC_1, s_axi_wstrb(5) => VCC_1, s_axi_wstrb(4) => VCC_1, s_axi_wstrb(3) => VCC_1, s_axi_wstrb(2) => VCC_1, s_axi_wstrb(1) => VCC_1, s_axi_wstrb(0) => VCC_1, s_axi_wvalid(2) => s02_couplers_to_xbar_WVALID, s_axi_wvalid(1) => s01_couplers_to_xbar_WVALID, s_axi_wvalid(0) => GND_1 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity triangle_intersect_processing_system7_0_axi_periph_0 is port ( ACLK : in STD_LOGIC; ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M00_ACLK : in STD_LOGIC; M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); M00_AXI_araddr : out STD_LOGIC_VECTOR ( 9 downto 0 ); M00_AXI_arready : in STD_LOGIC; M00_AXI_arvalid : out STD_LOGIC; M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 9 downto 0 ); M00_AXI_awready : in STD_LOGIC; M00_AXI_awvalid : out STD_LOGIC; M00_AXI_bready : out STD_LOGIC; M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_bvalid : in STD_LOGIC; M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); M00_AXI_rready : out STD_LOGIC; M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_rvalid : in STD_LOGIC; M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); M00_AXI_wready : in STD_LOGIC; M00_AXI_wvalid : out STD_LOGIC; S00_ACLK : in STD_LOGIC; S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 ); S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_arready : out STD_LOGIC; S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_arvalid : in STD_LOGIC; S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_awready : out STD_LOGIC; S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); S00_AXI_awvalid : in STD_LOGIC; S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_bready : in STD_LOGIC; S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_bvalid : out STD_LOGIC; S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_rlast : out STD_LOGIC; S00_AXI_rready : in STD_LOGIC; S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); S00_AXI_rvalid : out STD_LOGIC; S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); S00_AXI_wlast : in STD_LOGIC; S00_AXI_wready : out STD_LOGIC; S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); S00_AXI_wvalid : in STD_LOGIC ); end triangle_intersect_processing_system7_0_axi_periph_0; architecture STRUCTURE of triangle_intersect_processing_system7_0_axi_periph_0 is signal S00_ACLK_1 : STD_LOGIC; signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 ); signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC; signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC; signal s00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 9 downto 0 ); signal s00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC; signal s00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC; signal s00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 9 downto 0 ); signal s00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC; signal s00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC; signal s00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC; signal s00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC; signal s00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC; signal s00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC; signal s00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC; signal s00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC; begin M00_AXI_araddr(9 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_ARADDR(9 downto 0); M00_AXI_arvalid <= s00_couplers_to_processing_system7_0_axi_periph_ARVALID; M00_AXI_awaddr(9 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_AWADDR(9 downto 0); M00_AXI_awvalid <= s00_couplers_to_processing_system7_0_axi_periph_AWVALID; M00_AXI_bready <= s00_couplers_to_processing_system7_0_axi_periph_BREADY; M00_AXI_rready <= s00_couplers_to_processing_system7_0_axi_periph_RREADY; M00_AXI_wdata(31 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0); M00_AXI_wvalid <= s00_couplers_to_processing_system7_0_axi_periph_WVALID; S00_ACLK_1 <= S00_ACLK; S00_ARESETN_1(0) <= S00_ARESETN(0); S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY; S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY; S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0); S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0); S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID; S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0); S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0); S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST; S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0); S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID; S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY; processing_system7_0_axi_periph_ACLK_net <= M00_ACLK; processing_system7_0_axi_periph_ARESETN_net(0) <= M00_ARESETN(0); processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0); processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0); processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0); processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0); processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0); processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0); processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0); processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0); processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0); processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid; processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0); processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0); processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0); processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0); processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0); processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0); processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0); processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0); processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0); processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid; processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready; processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready; processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0); processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0); processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast; processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0); processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid; s00_couplers_to_processing_system7_0_axi_periph_ARREADY <= M00_AXI_arready; s00_couplers_to_processing_system7_0_axi_periph_AWREADY <= M00_AXI_awready; s00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0); s00_couplers_to_processing_system7_0_axi_periph_BVALID <= M00_AXI_bvalid; s00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0); s00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0); s00_couplers_to_processing_system7_0_axi_periph_RVALID <= M00_AXI_rvalid; s00_couplers_to_processing_system7_0_axi_periph_WREADY <= M00_AXI_wready; s00_couplers: entity work.s00_couplers_imp_18SS9VV port map ( M_ACLK => processing_system7_0_axi_periph_ACLK_net, M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0), M_AXI_araddr(9 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_ARADDR(9 downto 0), M_AXI_arready => s00_couplers_to_processing_system7_0_axi_periph_ARREADY, M_AXI_arvalid => s00_couplers_to_processing_system7_0_axi_periph_ARVALID, M_AXI_awaddr(9 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_AWADDR(9 downto 0), M_AXI_awready => s00_couplers_to_processing_system7_0_axi_periph_AWREADY, M_AXI_awvalid => s00_couplers_to_processing_system7_0_axi_periph_AWVALID, M_AXI_bready => s00_couplers_to_processing_system7_0_axi_periph_BREADY, M_AXI_bresp(1 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0), M_AXI_bvalid => s00_couplers_to_processing_system7_0_axi_periph_BVALID, M_AXI_rdata(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0), M_AXI_rready => s00_couplers_to_processing_system7_0_axi_periph_RREADY, M_AXI_rresp(1 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0), M_AXI_rvalid => s00_couplers_to_processing_system7_0_axi_periph_RVALID, M_AXI_wdata(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0), M_AXI_wready => s00_couplers_to_processing_system7_0_axi_periph_WREADY, M_AXI_wvalid => s00_couplers_to_processing_system7_0_axi_periph_WVALID, S_ACLK => S00_ACLK_1, S_ARESETN(0) => S00_ARESETN_1(0), S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0), S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0), S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0), S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0), S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0), S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0), S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0), S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0), S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY, S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0), S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID, S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0), S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0), S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0), S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0), S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0), S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0), S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0), S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0), S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY, S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0), S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID, S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0), S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY, S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0), S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID, S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0), S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0), S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST, S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY, S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0), S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID, S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0), S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0), S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST, S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY, S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0), S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity triangle_intersect is port ( DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_cas_n : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC ); attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of triangle_intersect : entity is "triangle_intersect,IP_Integrator,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=triangle_intersect,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=18,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,da_axi4_cnt=4,da_ps7_cnt=1,synth_mode=Global}"; attribute HW_HANDOFF : string; attribute HW_HANDOFF of triangle_intersect : entity is "triangle_intersect.hwdef"; end triangle_intersect; architecture STRUCTURE of triangle_intersect is component triangle_intersect_processing_system7_0_0 is port ( ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC; ENET0_SOF_RX : out STD_LOGIC; ENET0_SOF_TX : out STD_LOGIC; TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_ARREADY : out STD_LOGIC; S_AXI_HP0_AWREADY : out STD_LOGIC; S_AXI_HP0_BVALID : out STD_LOGIC; S_AXI_HP0_RLAST : out STD_LOGIC; S_AXI_HP0_RVALID : out STD_LOGIC; S_AXI_HP0_WREADY : out STD_LOGIC; S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_ACLK : in STD_LOGIC; S_AXI_HP0_ARVALID : in STD_LOGIC; S_AXI_HP0_AWVALID : in STD_LOGIC; S_AXI_HP0_BREADY : in STD_LOGIC; S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_RREADY : in STD_LOGIC; S_AXI_HP0_WLAST : in STD_LOGIC; S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_WVALID : in STD_LOGIC; S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); end component triangle_intersect_processing_system7_0_0; component triangle_intersect_axi_dma_0_0 is port ( s_axi_lite_aclk : in STD_LOGIC; m_axi_sg_aclk : in STD_LOGIC; m_axi_mm2s_aclk : in STD_LOGIC; m_axi_s2mm_aclk : in STD_LOGIC; axi_resetn : in STD_LOGIC; s_axi_lite_awvalid : in STD_LOGIC; s_axi_lite_awready : out STD_LOGIC; s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 ); s_axi_lite_wvalid : in STD_LOGIC; s_axi_lite_wready : out STD_LOGIC; s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_lite_bvalid : out STD_LOGIC; s_axi_lite_bready : in STD_LOGIC; s_axi_lite_arvalid : in STD_LOGIC; s_axi_lite_arready : out STD_LOGIC; s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 ); s_axi_lite_rvalid : out STD_LOGIC; s_axi_lite_rready : in STD_LOGIC; s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_sg_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_sg_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_sg_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_sg_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_sg_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_sg_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_sg_awvalid : out STD_LOGIC; m_axi_sg_awready : in STD_LOGIC; m_axi_sg_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_sg_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_sg_wlast : out STD_LOGIC; m_axi_sg_wvalid : out STD_LOGIC; m_axi_sg_wready : in STD_LOGIC; m_axi_sg_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_sg_bvalid : in STD_LOGIC; m_axi_sg_bready : out STD_LOGIC; m_axi_sg_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_sg_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_sg_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_sg_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_sg_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_sg_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_sg_arvalid : out STD_LOGIC; m_axi_sg_arready : in STD_LOGIC; m_axi_sg_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_sg_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_sg_rlast : in STD_LOGIC; m_axi_sg_rvalid : in STD_LOGIC; m_axi_sg_rready : out STD_LOGIC; m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_mm2s_arvalid : out STD_LOGIC; m_axi_mm2s_arready : in STD_LOGIC; m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_mm2s_rlast : in STD_LOGIC; m_axi_mm2s_rvalid : in STD_LOGIC; m_axi_mm2s_rready : out STD_LOGIC; mm2s_prmry_reset_out_n : out STD_LOGIC; m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axis_mm2s_tvalid : out STD_LOGIC; m_axis_mm2s_tready : in STD_LOGIC; m_axis_mm2s_tlast : out STD_LOGIC; m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_s2mm_awvalid : out STD_LOGIC; m_axi_s2mm_awready : in STD_LOGIC; m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_s2mm_wlast : out STD_LOGIC; m_axi_s2mm_wvalid : out STD_LOGIC; m_axi_s2mm_wready : in STD_LOGIC; m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_s2mm_bvalid : in STD_LOGIC; m_axi_s2mm_bready : out STD_LOGIC; s2mm_prmry_reset_out_n : out STD_LOGIC; s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axis_s2mm_tvalid : in STD_LOGIC; s_axis_s2mm_tready : out STD_LOGIC; s_axis_s2mm_tlast : in STD_LOGIC; mm2s_introut : out STD_LOGIC; s2mm_introut : out STD_LOGIC ); end component triangle_intersect_axi_dma_0_0; component triangle_intersect_rst_processing_system7_0_100M_0 is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); end component triangle_intersect_rst_processing_system7_0_100M_0; component triangle_intersect_xlconcat_0_0 is port ( In0 : in STD_LOGIC_VECTOR ( 0 to 0 ); In1 : in STD_LOGIC_VECTOR ( 0 to 0 ); dout : out STD_LOGIC_VECTOR ( 1 downto 0 ) ); end component triangle_intersect_xlconcat_0_0; component triangle_intersect_tri_intersect_0_1 is port ( ap_clk : in STD_LOGIC; ap_rst_n : in STD_LOGIC; ins_TVALID : in STD_LOGIC; ins_TREADY : out STD_LOGIC; ins_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); ins_TDEST : in STD_LOGIC_VECTOR ( 0 to 0 ); ins_TKEEP : in STD_LOGIC_VECTOR ( 3 downto 0 ); ins_TSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); ins_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 ); ins_TLAST : in STD_LOGIC_VECTOR ( 0 to 0 ); ins_TID : in STD_LOGIC_VECTOR ( 0 to 0 ); outs_TVALID : out STD_LOGIC; outs_TREADY : in STD_LOGIC; outs_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); outs_TDEST : out STD_LOGIC_VECTOR ( 0 to 0 ); outs_TKEEP : out STD_LOGIC_VECTOR ( 3 downto 0 ); outs_TSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); outs_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 ); outs_TLAST : out STD_LOGIC_VECTOR ( 0 to 0 ); outs_TID : out STD_LOGIC_VECTOR ( 0 to 0 ) ); end component triangle_intersect_tri_intersect_0_1; signal GND_1 : STD_LOGIC; signal VCC_1 : STD_LOGIC; signal axi_dma_0_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_dma_0_M_AXIS_MM2S_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_dma_0_M_AXIS_MM2S_TLAST : STD_LOGIC; signal axi_dma_0_M_AXIS_MM2S_TREADY : STD_LOGIC; signal axi_dma_0_M_AXIS_MM2S_TVALID : STD_LOGIC; signal axi_dma_0_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_dma_0_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_dma_0_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_dma_0_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axi_dma_0_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_dma_0_M_AXI_MM2S_ARREADY : STD_LOGIC; signal axi_dma_0_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_dma_0_M_AXI_MM2S_ARVALID : STD_LOGIC; signal axi_dma_0_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_dma_0_M_AXI_MM2S_RLAST : STD_LOGIC; signal axi_dma_0_M_AXI_MM2S_RREADY : STD_LOGIC; signal axi_dma_0_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_dma_0_M_AXI_MM2S_RVALID : STD_LOGIC; signal axi_dma_0_M_AXI_S2MM_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_dma_0_M_AXI_S2MM_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_dma_0_M_AXI_S2MM_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_dma_0_M_AXI_S2MM_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axi_dma_0_M_AXI_S2MM_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_dma_0_M_AXI_S2MM_AWREADY : STD_LOGIC; signal axi_dma_0_M_AXI_S2MM_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_dma_0_M_AXI_S2MM_AWVALID : STD_LOGIC; signal axi_dma_0_M_AXI_S2MM_BREADY : STD_LOGIC; signal axi_dma_0_M_AXI_S2MM_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_dma_0_M_AXI_S2MM_BVALID : STD_LOGIC; signal axi_dma_0_M_AXI_S2MM_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_dma_0_M_AXI_S2MM_WLAST : STD_LOGIC; signal axi_dma_0_M_AXI_S2MM_WREADY : STD_LOGIC; signal axi_dma_0_M_AXI_S2MM_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_dma_0_M_AXI_S2MM_WVALID : STD_LOGIC; signal axi_dma_0_M_AXI_SG_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_dma_0_M_AXI_SG_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_dma_0_M_AXI_SG_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_dma_0_M_AXI_SG_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axi_dma_0_M_AXI_SG_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_dma_0_M_AXI_SG_ARREADY : STD_LOGIC; signal axi_dma_0_M_AXI_SG_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_dma_0_M_AXI_SG_ARVALID : STD_LOGIC; signal axi_dma_0_M_AXI_SG_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_dma_0_M_AXI_SG_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_dma_0_M_AXI_SG_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_dma_0_M_AXI_SG_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axi_dma_0_M_AXI_SG_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_dma_0_M_AXI_SG_AWREADY : STD_LOGIC; signal axi_dma_0_M_AXI_SG_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_dma_0_M_AXI_SG_AWVALID : STD_LOGIC; signal axi_dma_0_M_AXI_SG_BREADY : STD_LOGIC; signal axi_dma_0_M_AXI_SG_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_dma_0_M_AXI_SG_BVALID : STD_LOGIC; signal axi_dma_0_M_AXI_SG_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_dma_0_M_AXI_SG_RLAST : STD_LOGIC; signal axi_dma_0_M_AXI_SG_RREADY : STD_LOGIC; signal axi_dma_0_M_AXI_SG_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_dma_0_M_AXI_SG_RVALID : STD_LOGIC; signal axi_dma_0_M_AXI_SG_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_dma_0_M_AXI_SG_WLAST : STD_LOGIC; signal axi_dma_0_M_AXI_SG_WREADY : STD_LOGIC; signal axi_dma_0_M_AXI_SG_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_dma_0_M_AXI_SG_WVALID : STD_LOGIC; signal axi_dma_0_mm2s_introut : STD_LOGIC; signal axi_dma_0_s2mm_introut : STD_LOGIC; signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC; signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC; signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC; signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC; signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 5 downto 0 ); signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC; signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC; signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 5 downto 0 ); signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC; signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC; signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC; signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); signal axi_mem_intercon_M00_AXI_WID : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC; signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC; signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC; signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 ); signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_DDR_CAS_N : STD_LOGIC; signal processing_system7_0_DDR_CKE : STD_LOGIC; signal processing_system7_0_DDR_CK_N : STD_LOGIC; signal processing_system7_0_DDR_CK_P : STD_LOGIC; signal processing_system7_0_DDR_CS_N : STD_LOGIC; signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_DDR_ODT : STD_LOGIC; signal processing_system7_0_DDR_RAS_N : STD_LOGIC; signal processing_system7_0_DDR_RESET_N : STD_LOGIC; signal processing_system7_0_DDR_WE_N : STD_LOGIC; signal processing_system7_0_FCLK_CLK0 : STD_LOGIC; signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC; signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC; signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC; signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC; signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC; signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 ); signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC; signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 9 downto 0 ); signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 9 downto 0 ); signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC; signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 ); signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 ); signal tri_intersect_0_outs_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal tri_intersect_0_outs_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 ); signal tri_intersect_0_outs_TLAST : STD_LOGIC_VECTOR ( 0 to 0 ); signal tri_intersect_0_outs_TREADY : STD_LOGIC; signal tri_intersect_0_outs_TVALID : STD_LOGIC; signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED : STD_LOGIC; signal NLW_axi_dma_0_s2mm_prmry_reset_out_n_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC; signal NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_tri_intersect_0_ins_TSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 ); signal NLW_tri_intersect_0_outs_TDEST_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_tri_intersect_0_outs_TID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_tri_intersect_0_outs_TSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_tri_intersect_0_outs_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); begin GND: unisim.vcomponents.GND port map ( G => GND_1 ); VCC: unisim.vcomponents.VCC port map ( P => VCC_1 ); axi_dma_0: component triangle_intersect_axi_dma_0_0 port map ( axi_resetn => rst_processing_system7_0_100M_peripheral_aresetn(0), m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0, m_axi_mm2s_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0), m_axi_mm2s_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0), m_axi_mm2s_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0), m_axi_mm2s_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0), m_axi_mm2s_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0), m_axi_mm2s_arready => axi_dma_0_M_AXI_MM2S_ARREADY, m_axi_mm2s_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0), m_axi_mm2s_arvalid => axi_dma_0_M_AXI_MM2S_ARVALID, m_axi_mm2s_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0), m_axi_mm2s_rlast => axi_dma_0_M_AXI_MM2S_RLAST, m_axi_mm2s_rready => axi_dma_0_M_AXI_MM2S_RREADY, m_axi_mm2s_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0), m_axi_mm2s_rvalid => axi_dma_0_M_AXI_MM2S_RVALID, m_axi_s2mm_aclk => processing_system7_0_FCLK_CLK0, m_axi_s2mm_awaddr(31 downto 0) => axi_dma_0_M_AXI_S2MM_AWADDR(31 downto 0), m_axi_s2mm_awburst(1 downto 0) => axi_dma_0_M_AXI_S2MM_AWBURST(1 downto 0), m_axi_s2mm_awcache(3 downto 0) => axi_dma_0_M_AXI_S2MM_AWCACHE(3 downto 0), m_axi_s2mm_awlen(7 downto 0) => axi_dma_0_M_AXI_S2MM_AWLEN(7 downto 0), m_axi_s2mm_awprot(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWPROT(2 downto 0), m_axi_s2mm_awready => axi_dma_0_M_AXI_S2MM_AWREADY, m_axi_s2mm_awsize(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWSIZE(2 downto 0), m_axi_s2mm_awvalid => axi_dma_0_M_AXI_S2MM_AWVALID, m_axi_s2mm_bready => axi_dma_0_M_AXI_S2MM_BREADY, m_axi_s2mm_bresp(1 downto 0) => axi_dma_0_M_AXI_S2MM_BRESP(1 downto 0), m_axi_s2mm_bvalid => axi_dma_0_M_AXI_S2MM_BVALID, m_axi_s2mm_wdata(31 downto 0) => axi_dma_0_M_AXI_S2MM_WDATA(31 downto 0), m_axi_s2mm_wlast => axi_dma_0_M_AXI_S2MM_WLAST, m_axi_s2mm_wready => axi_dma_0_M_AXI_S2MM_WREADY, m_axi_s2mm_wstrb(3 downto 0) => axi_dma_0_M_AXI_S2MM_WSTRB(3 downto 0), m_axi_s2mm_wvalid => axi_dma_0_M_AXI_S2MM_WVALID, m_axi_sg_aclk => processing_system7_0_FCLK_CLK0, m_axi_sg_araddr(31 downto 0) => axi_dma_0_M_AXI_SG_ARADDR(31 downto 0), m_axi_sg_arburst(1 downto 0) => axi_dma_0_M_AXI_SG_ARBURST(1 downto 0), m_axi_sg_arcache(3 downto 0) => axi_dma_0_M_AXI_SG_ARCACHE(3 downto 0), m_axi_sg_arlen(7 downto 0) => axi_dma_0_M_AXI_SG_ARLEN(7 downto 0), m_axi_sg_arprot(2 downto 0) => axi_dma_0_M_AXI_SG_ARPROT(2 downto 0), m_axi_sg_arready => axi_dma_0_M_AXI_SG_ARREADY, m_axi_sg_arsize(2 downto 0) => axi_dma_0_M_AXI_SG_ARSIZE(2 downto 0), m_axi_sg_arvalid => axi_dma_0_M_AXI_SG_ARVALID, m_axi_sg_awaddr(31 downto 0) => axi_dma_0_M_AXI_SG_AWADDR(31 downto 0), m_axi_sg_awburst(1 downto 0) => axi_dma_0_M_AXI_SG_AWBURST(1 downto 0), m_axi_sg_awcache(3 downto 0) => axi_dma_0_M_AXI_SG_AWCACHE(3 downto 0), m_axi_sg_awlen(7 downto 0) => axi_dma_0_M_AXI_SG_AWLEN(7 downto 0), m_axi_sg_awprot(2 downto 0) => axi_dma_0_M_AXI_SG_AWPROT(2 downto 0), m_axi_sg_awready => axi_dma_0_M_AXI_SG_AWREADY, m_axi_sg_awsize(2 downto 0) => axi_dma_0_M_AXI_SG_AWSIZE(2 downto 0), m_axi_sg_awvalid => axi_dma_0_M_AXI_SG_AWVALID, m_axi_sg_bready => axi_dma_0_M_AXI_SG_BREADY, m_axi_sg_bresp(1 downto 0) => axi_dma_0_M_AXI_SG_BRESP(1 downto 0), m_axi_sg_bvalid => axi_dma_0_M_AXI_SG_BVALID, m_axi_sg_rdata(31 downto 0) => axi_dma_0_M_AXI_SG_RDATA(31 downto 0), m_axi_sg_rlast => axi_dma_0_M_AXI_SG_RLAST, m_axi_sg_rready => axi_dma_0_M_AXI_SG_RREADY, m_axi_sg_rresp(1 downto 0) => axi_dma_0_M_AXI_SG_RRESP(1 downto 0), m_axi_sg_rvalid => axi_dma_0_M_AXI_SG_RVALID, m_axi_sg_wdata(31 downto 0) => axi_dma_0_M_AXI_SG_WDATA(31 downto 0), m_axi_sg_wlast => axi_dma_0_M_AXI_SG_WLAST, m_axi_sg_wready => axi_dma_0_M_AXI_SG_WREADY, m_axi_sg_wstrb(3 downto 0) => axi_dma_0_M_AXI_SG_WSTRB(3 downto 0), m_axi_sg_wvalid => axi_dma_0_M_AXI_SG_WVALID, m_axis_mm2s_tdata(31 downto 0) => axi_dma_0_M_AXIS_MM2S_TDATA(31 downto 0), m_axis_mm2s_tkeep(3 downto 0) => axi_dma_0_M_AXIS_MM2S_TKEEP(3 downto 0), m_axis_mm2s_tlast => axi_dma_0_M_AXIS_MM2S_TLAST, m_axis_mm2s_tready => axi_dma_0_M_AXIS_MM2S_TREADY, m_axis_mm2s_tvalid => axi_dma_0_M_AXIS_MM2S_TVALID, mm2s_introut => axi_dma_0_mm2s_introut, mm2s_prmry_reset_out_n => NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED, s2mm_introut => axi_dma_0_s2mm_introut, s2mm_prmry_reset_out_n => NLW_axi_dma_0_s2mm_prmry_reset_out_n_UNCONNECTED, s_axi_lite_aclk => processing_system7_0_FCLK_CLK0, s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(9 downto 0), s_axi_lite_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY, s_axi_lite_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID, s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(9 downto 0), s_axi_lite_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY, s_axi_lite_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID, s_axi_lite_bready => processing_system7_0_axi_periph_M00_AXI_BREADY, s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0), s_axi_lite_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID, s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0), s_axi_lite_rready => processing_system7_0_axi_periph_M00_AXI_RREADY, s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0), s_axi_lite_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID, s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0), s_axi_lite_wready => processing_system7_0_axi_periph_M00_AXI_WREADY, s_axi_lite_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID, s_axis_s2mm_tdata(31 downto 0) => tri_intersect_0_outs_TDATA(31 downto 0), s_axis_s2mm_tkeep(3 downto 0) => tri_intersect_0_outs_TKEEP(3 downto 0), s_axis_s2mm_tlast => tri_intersect_0_outs_TLAST(0), s_axis_s2mm_tready => tri_intersect_0_outs_TREADY, s_axis_s2mm_tvalid => tri_intersect_0_outs_TVALID ); axi_mem_intercon: entity work.triangle_intersect_axi_mem_intercon_0 port map ( ACLK => processing_system7_0_FCLK_CLK0, ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0), M00_ACLK => processing_system7_0_FCLK_CLK0, M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0), M00_AXI_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0), M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0), M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0), M00_AXI_arid(1 downto 0) => axi_mem_intercon_M00_AXI_ARID(1 downto 0), M00_AXI_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0), M00_AXI_arlock(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0), M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0), M00_AXI_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0), M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY, M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0), M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID, M00_AXI_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0), M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0), M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0), M00_AXI_awid(1 downto 0) => axi_mem_intercon_M00_AXI_AWID(1 downto 0), M00_AXI_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0), M00_AXI_awlock(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0), M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0), M00_AXI_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0), M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY, M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0), M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID, M00_AXI_bid(1 downto 0) => axi_mem_intercon_M00_AXI_BID(1 downto 0), M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY, M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0), M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID, M00_AXI_rdata(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0), M00_AXI_rid(1 downto 0) => axi_mem_intercon_M00_AXI_RID(1 downto 0), M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST, M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY, M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0), M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID, M00_AXI_wdata(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0), M00_AXI_wid(1 downto 0) => axi_mem_intercon_M00_AXI_WID(1 downto 0), M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST, M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY, M00_AXI_wstrb(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0), M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID, S00_ACLK => processing_system7_0_FCLK_CLK0, S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0), S00_AXI_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0), S00_AXI_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0), S00_AXI_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0), S00_AXI_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0), S00_AXI_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0), S00_AXI_arready => axi_dma_0_M_AXI_MM2S_ARREADY, S00_AXI_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0), S00_AXI_arvalid => axi_dma_0_M_AXI_MM2S_ARVALID, S00_AXI_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0), S00_AXI_rlast => axi_dma_0_M_AXI_MM2S_RLAST, S00_AXI_rready => axi_dma_0_M_AXI_MM2S_RREADY, S00_AXI_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0), S00_AXI_rvalid => axi_dma_0_M_AXI_MM2S_RVALID, S01_ACLK => processing_system7_0_FCLK_CLK0, S01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0), S01_AXI_awaddr(31 downto 0) => axi_dma_0_M_AXI_S2MM_AWADDR(31 downto 0), S01_AXI_awburst(1 downto 0) => axi_dma_0_M_AXI_S2MM_AWBURST(1 downto 0), S01_AXI_awcache(3 downto 0) => axi_dma_0_M_AXI_S2MM_AWCACHE(3 downto 0), S01_AXI_awlen(7 downto 0) => axi_dma_0_M_AXI_S2MM_AWLEN(7 downto 0), S01_AXI_awprot(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWPROT(2 downto 0), S01_AXI_awready => axi_dma_0_M_AXI_S2MM_AWREADY, S01_AXI_awsize(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWSIZE(2 downto 0), S01_AXI_awvalid => axi_dma_0_M_AXI_S2MM_AWVALID, S01_AXI_bready => axi_dma_0_M_AXI_S2MM_BREADY, S01_AXI_bresp(1 downto 0) => axi_dma_0_M_AXI_S2MM_BRESP(1 downto 0), S01_AXI_bvalid => axi_dma_0_M_AXI_S2MM_BVALID, S01_AXI_wdata(31 downto 0) => axi_dma_0_M_AXI_S2MM_WDATA(31 downto 0), S01_AXI_wlast => axi_dma_0_M_AXI_S2MM_WLAST, S01_AXI_wready => axi_dma_0_M_AXI_S2MM_WREADY, S01_AXI_wstrb(3 downto 0) => axi_dma_0_M_AXI_S2MM_WSTRB(3 downto 0), S01_AXI_wvalid => axi_dma_0_M_AXI_S2MM_WVALID, S02_ACLK => processing_system7_0_FCLK_CLK0, S02_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0), S02_AXI_araddr(31 downto 0) => axi_dma_0_M_AXI_SG_ARADDR(31 downto 0), S02_AXI_arburst(1 downto 0) => axi_dma_0_M_AXI_SG_ARBURST(1 downto 0), S02_AXI_arcache(3 downto 0) => axi_dma_0_M_AXI_SG_ARCACHE(3 downto 0), S02_AXI_arlen(7 downto 0) => axi_dma_0_M_AXI_SG_ARLEN(7 downto 0), S02_AXI_arprot(2 downto 0) => axi_dma_0_M_AXI_SG_ARPROT(2 downto 0), S02_AXI_arready => axi_dma_0_M_AXI_SG_ARREADY, S02_AXI_arsize(2 downto 0) => axi_dma_0_M_AXI_SG_ARSIZE(2 downto 0), S02_AXI_arvalid => axi_dma_0_M_AXI_SG_ARVALID, S02_AXI_awaddr(31 downto 0) => axi_dma_0_M_AXI_SG_AWADDR(31 downto 0), S02_AXI_awburst(1 downto 0) => axi_dma_0_M_AXI_SG_AWBURST(1 downto 0), S02_AXI_awcache(3 downto 0) => axi_dma_0_M_AXI_SG_AWCACHE(3 downto 0), S02_AXI_awlen(7 downto 0) => axi_dma_0_M_AXI_SG_AWLEN(7 downto 0), S02_AXI_awprot(2 downto 0) => axi_dma_0_M_AXI_SG_AWPROT(2 downto 0), S02_AXI_awready => axi_dma_0_M_AXI_SG_AWREADY, S02_AXI_awsize(2 downto 0) => axi_dma_0_M_AXI_SG_AWSIZE(2 downto 0), S02_AXI_awvalid => axi_dma_0_M_AXI_SG_AWVALID, S02_AXI_bready => axi_dma_0_M_AXI_SG_BREADY, S02_AXI_bresp(1 downto 0) => axi_dma_0_M_AXI_SG_BRESP(1 downto 0), S02_AXI_bvalid => axi_dma_0_M_AXI_SG_BVALID, S02_AXI_rdata(31 downto 0) => axi_dma_0_M_AXI_SG_RDATA(31 downto 0), S02_AXI_rlast => axi_dma_0_M_AXI_SG_RLAST, S02_AXI_rready => axi_dma_0_M_AXI_SG_RREADY, S02_AXI_rresp(1 downto 0) => axi_dma_0_M_AXI_SG_RRESP(1 downto 0), S02_AXI_rvalid => axi_dma_0_M_AXI_SG_RVALID, S02_AXI_wdata(31 downto 0) => axi_dma_0_M_AXI_SG_WDATA(31 downto 0), S02_AXI_wlast => axi_dma_0_M_AXI_SG_WLAST, S02_AXI_wready => axi_dma_0_M_AXI_SG_WREADY, S02_AXI_wstrb(3 downto 0) => axi_dma_0_M_AXI_SG_WSTRB(3 downto 0), S02_AXI_wvalid => axi_dma_0_M_AXI_SG_WVALID ); processing_system7_0: component triangle_intersect_processing_system7_0_0 port map ( DDR_Addr(14 downto 0) => DDR_addr(14 downto 0), DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0), DDR_CAS_n => DDR_cas_n, DDR_CKE => DDR_cke, DDR_CS_n => DDR_cs_n, DDR_Clk => DDR_ck_p, DDR_Clk_n => DDR_ck_n, DDR_DM(3 downto 0) => DDR_dm(3 downto 0), DDR_DQ(31 downto 0) => DDR_dq(31 downto 0), DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0), DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0), DDR_DRSTB => DDR_reset_n, DDR_ODT => DDR_odt, DDR_RAS_n => DDR_ras_n, DDR_VRN => FIXED_IO_ddr_vrn, DDR_VRP => FIXED_IO_ddr_vrp, DDR_WEB => DDR_we_n, ENET0_PTP_DELAY_REQ_RX => NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED, ENET0_PTP_DELAY_REQ_TX => NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED, ENET0_PTP_PDELAY_REQ_RX => NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED, ENET0_PTP_PDELAY_REQ_TX => NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED, ENET0_PTP_PDELAY_RESP_RX => NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED, ENET0_PTP_PDELAY_RESP_TX => NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED, ENET0_PTP_SYNC_FRAME_RX => NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED, ENET0_PTP_SYNC_FRAME_TX => NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED, ENET0_SOF_RX => NLW_processing_system7_0_ENET0_SOF_RX_UNCONNECTED, ENET0_SOF_TX => NLW_processing_system7_0_ENET0_SOF_TX_UNCONNECTED, FCLK_CLK0 => processing_system7_0_FCLK_CLK0, FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N, IRQ_F2P(1 downto 0) => xlconcat_0_dout(1 downto 0), MIO(53 downto 0) => FIXED_IO_mio(53 downto 0), M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0, M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0), M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0), M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0), M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0), M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0), M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0), M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0), M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0), M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY, M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0), M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID, M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0), M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0), M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0), M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0), M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0), M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0), M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0), M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0), M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY, M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0), M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID, M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0), M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY, M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0), M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID, M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0), M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0), M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST, M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY, M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0), M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID, M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0), M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0), M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST, M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY, M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0), M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID, PS_CLK => FIXED_IO_ps_clk, PS_PORB => FIXED_IO_ps_porb, PS_SRSTB => FIXED_IO_ps_srstb, S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0, S_AXI_HP0_ARADDR(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0), S_AXI_HP0_ARBURST(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0), S_AXI_HP0_ARCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0), S_AXI_HP0_ARID(5) => GND_1, S_AXI_HP0_ARID(4) => GND_1, S_AXI_HP0_ARID(3) => GND_1, S_AXI_HP0_ARID(2) => GND_1, S_AXI_HP0_ARID(1 downto 0) => axi_mem_intercon_M00_AXI_ARID(1 downto 0), S_AXI_HP0_ARLEN(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0), S_AXI_HP0_ARLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0), S_AXI_HP0_ARPROT(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0), S_AXI_HP0_ARQOS(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0), S_AXI_HP0_ARREADY => axi_mem_intercon_M00_AXI_ARREADY, S_AXI_HP0_ARSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0), S_AXI_HP0_ARVALID => axi_mem_intercon_M00_AXI_ARVALID, S_AXI_HP0_AWADDR(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0), S_AXI_HP0_AWBURST(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0), S_AXI_HP0_AWCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0), S_AXI_HP0_AWID(5) => GND_1, S_AXI_HP0_AWID(4) => GND_1, S_AXI_HP0_AWID(3) => GND_1, S_AXI_HP0_AWID(2) => GND_1, S_AXI_HP0_AWID(1 downto 0) => axi_mem_intercon_M00_AXI_AWID(1 downto 0), S_AXI_HP0_AWLEN(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0), S_AXI_HP0_AWLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0), S_AXI_HP0_AWPROT(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0), S_AXI_HP0_AWQOS(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0), S_AXI_HP0_AWREADY => axi_mem_intercon_M00_AXI_AWREADY, S_AXI_HP0_AWSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0), S_AXI_HP0_AWVALID => axi_mem_intercon_M00_AXI_AWVALID, S_AXI_HP0_BID(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0), S_AXI_HP0_BREADY => axi_mem_intercon_M00_AXI_BREADY, S_AXI_HP0_BRESP(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0), S_AXI_HP0_BVALID => axi_mem_intercon_M00_AXI_BVALID, S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_RDATA(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0), S_AXI_HP0_RDISSUECAP1_EN => GND_1, S_AXI_HP0_RID(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0), S_AXI_HP0_RLAST => axi_mem_intercon_M00_AXI_RLAST, S_AXI_HP0_RREADY => axi_mem_intercon_M00_AXI_RREADY, S_AXI_HP0_RRESP(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0), S_AXI_HP0_RVALID => axi_mem_intercon_M00_AXI_RVALID, S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_WDATA(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0), S_AXI_HP0_WID(5) => GND_1, S_AXI_HP0_WID(4) => GND_1, S_AXI_HP0_WID(3) => GND_1, S_AXI_HP0_WID(2) => GND_1, S_AXI_HP0_WID(1 downto 0) => axi_mem_intercon_M00_AXI_WID(1 downto 0), S_AXI_HP0_WLAST => axi_mem_intercon_M00_AXI_WLAST, S_AXI_HP0_WREADY => axi_mem_intercon_M00_AXI_WREADY, S_AXI_HP0_WRISSUECAP1_EN => GND_1, S_AXI_HP0_WSTRB(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0), S_AXI_HP0_WVALID => axi_mem_intercon_M00_AXI_WVALID, TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED, TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED, TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED, USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0), USB0_VBUS_PWRFAULT => GND_1, USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED ); processing_system7_0_axi_periph: entity work.triangle_intersect_processing_system7_0_axi_periph_0 port map ( ACLK => processing_system7_0_FCLK_CLK0, ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0), M00_ACLK => processing_system7_0_FCLK_CLK0, M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0), M00_AXI_araddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(9 downto 0), M00_AXI_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY, M00_AXI_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID, M00_AXI_awaddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(9 downto 0), M00_AXI_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY, M00_AXI_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID, M00_AXI_bready => processing_system7_0_axi_periph_M00_AXI_BREADY, M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0), M00_AXI_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID, M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0), M00_AXI_rready => processing_system7_0_axi_periph_M00_AXI_RREADY, M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0), M00_AXI_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID, M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0), M00_AXI_wready => processing_system7_0_axi_periph_M00_AXI_WREADY, M00_AXI_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID, S00_ACLK => processing_system7_0_FCLK_CLK0, S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0), S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0), S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0), S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0), S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0), S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0), S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0), S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0), S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0), S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY, S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0), S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID, S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0), S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0), S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0), S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0), S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0), S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0), S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0), S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0), S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY, S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0), S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID, S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0), S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY, S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0), S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID, S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0), S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0), S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST, S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY, S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0), S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID, S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0), S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0), S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST, S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY, S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0), S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID ); rst_processing_system7_0_100M: component triangle_intersect_rst_processing_system7_0_100M_0 port map ( aux_reset_in => VCC_1, bus_struct_reset(0) => NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED(0), dcm_locked => VCC_1, ext_reset_in => processing_system7_0_FCLK_RESET0_N, interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0), mb_debug_sys_rst => GND_1, mb_reset => NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED, peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0), peripheral_reset(0) => NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED(0), slowest_sync_clk => processing_system7_0_FCLK_CLK0 ); tri_intersect_0: component triangle_intersect_tri_intersect_0_1 port map ( ap_clk => processing_system7_0_FCLK_CLK0, ap_rst_n => rst_processing_system7_0_100M_peripheral_aresetn(0), ins_TDATA(31 downto 0) => axi_dma_0_M_AXIS_MM2S_TDATA(31 downto 0), ins_TDEST(0) => GND_1, ins_TID(0) => GND_1, ins_TKEEP(3 downto 0) => axi_dma_0_M_AXIS_MM2S_TKEEP(3 downto 0), ins_TLAST(0) => axi_dma_0_M_AXIS_MM2S_TLAST, ins_TREADY => axi_dma_0_M_AXIS_MM2S_TREADY, ins_TSTRB(3) => NLW_tri_intersect_0_ins_TSTRB_UNCONNECTED(3), ins_TSTRB(2) => VCC_1, ins_TSTRB(1) => VCC_1, ins_TSTRB(0) => VCC_1, ins_TUSER(0) => GND_1, ins_TVALID => axi_dma_0_M_AXIS_MM2S_TVALID, outs_TDATA(31 downto 0) => tri_intersect_0_outs_TDATA(31 downto 0), outs_TDEST(0) => NLW_tri_intersect_0_outs_TDEST_UNCONNECTED(0), outs_TID(0) => NLW_tri_intersect_0_outs_TID_UNCONNECTED(0), outs_TKEEP(3 downto 0) => tri_intersect_0_outs_TKEEP(3 downto 0), outs_TLAST(0) => tri_intersect_0_outs_TLAST(0), outs_TREADY => tri_intersect_0_outs_TREADY, outs_TSTRB(3 downto 0) => NLW_tri_intersect_0_outs_TSTRB_UNCONNECTED(3 downto 0), outs_TUSER(0) => NLW_tri_intersect_0_outs_TUSER_UNCONNECTED(0), outs_TVALID => tri_intersect_0_outs_TVALID ); xlconcat_0: component triangle_intersect_xlconcat_0_0 port map ( In0(0) => axi_dma_0_mm2s_introut, In1(0) => axi_dma_0_s2mm_introut, dout(1 downto 0) => xlconcat_0_dout(1 downto 0) ); end STRUCTURE;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; library work; use work.TbFuncs.all; entity AbsDiff_tb is end AbsDiff_tb; architecture behavior of AbsDiff_tb is component AbsDiff port ( A_i : in std_logic_vector(15 downto 0); B_i : in std_logic_vector(15 downto 0); D_o : out std_logic_vector(15 downto 0) ); end component; constant TestCases : natural := 10000; -- 0: try all (2**16 * 2**16) cases; >0: use random numbers constant CheckOutputDelay : time := 20 ns; constant SetupNextInputDelay : time := 20 ns; -- component generics constant Width : integer := 16; -- component ports signal A_i : std_logic_vector(Width-1 downto 0); signal B_i : std_logic_vector(Width-1 downto 0); signal D_o : std_logic_vector(Width-1 downto 0); procedure CheckAbsDiff ( constant A : in integer; constant B : in integer; signal A_i : out std_logic_vector(Width-1 downto 0); signal B_i : out std_logic_vector(Width-1 downto 0); signal D_o : in std_logic_vector(Width-1 downto 0) ) is variable D : integer; variable D_s : std_logic_vector(Width-1 downto 0); begin -- CheckAbsDiff D := abs(A - B); D_s := std_logic_vector(to_unsigned(D,Width)); -- set inputs A_i <= std_logic_vector(to_unsigned(A,Width)); B_i <= std_logic_vector(to_unsigned(B,Width)); wait for CheckOutputDelay; -- check output assert D_o = D_s report "Wrong Result " & Vector2String(D_o) & " for A = " & integer'image(A) & ", B = " & integer'image(B) & ", should be " & Vector2String(D_s) severity error; wait for SetupNextInputDelay; end CheckAbsDiff; begin -- behavior -- component instantiation DUT: AbsDiff port map ( A_i => A_i, B_i => B_i, D_o => D_o ); StimulusProc: process variable A : integer; variable B : integer; variable S1 : positive; variable S2 : positive; variable R : real; begin if TestCases = 0 then for A in 0 to 2**(Width-1) loop for B in 0 to 2**(Width-1) loop CheckAbsDiff(A,B,A_i,B_i,D_o); end loop; -- B end loop; -- A else for i in 1 to TestCases loop Uniform(S1,S2,R); A := integer(trunc(R * real(2**Width-1))); Uniform(S1,S2,R); B := integer(trunc(R * real(2**Width-1))); CheckAbsDiff(A,B,A_i,B_i,D_o); end loop; end if; -- End of simulation report "### Simulation Finished ###" severity failure; wait; end process StimulusProc; end behavior;
-- ------------------------------------------------------------- -- -- File Name: hdl_prj/hdlsrc/OFDM_transmitter/Complex3Multiply_block8.vhd -- Created: 2017-03-27 15:50:06 -- -- Generated by MATLAB 9.1 and HDL Coder 3.9 -- -- ------------------------------------------------------------- -- ------------------------------------------------------------- -- -- Module: Complex3Multiply_block8 -- Source Path: OFDM_transmitter/IFFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply -- Hierarchy Level: 3 -- -- ------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; ENTITY Complex3Multiply_block8 IS PORT( clk : IN std_logic; reset : IN std_logic; enb_1_16_0 : IN std_logic; din2_re_dly3 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13 din2_im_dly3 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13 di2_vld_dly3 : IN std_logic; twdl_3_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14 twdl_3_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14 softReset : IN std_logic; twdlXdin_14_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13 twdlXdin_14_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13 twdlXdin2_vld : OUT std_logic ); END Complex3Multiply_block8; ARCHITECTURE rtl OF Complex3Multiply_block8 IS -- Signals SIGNAL din2_re_dly3_signed : signed(15 DOWNTO 0); -- sfix16_En13 SIGNAL din_re_reg : signed(15 DOWNTO 0); -- sfix16_En13 SIGNAL din2_im_dly3_signed : signed(15 DOWNTO 0); -- sfix16_En13 SIGNAL din_im_reg : signed(15 DOWNTO 0); -- sfix16_En13 SIGNAL adder_add_cast : signed(16 DOWNTO 0); -- sfix17_En13 SIGNAL adder_add_cast_1 : signed(16 DOWNTO 0); -- sfix17_En13 SIGNAL din_sum : signed(16 DOWNTO 0); -- sfix17_En13 SIGNAL twdl_3_14_re_signed : signed(15 DOWNTO 0); -- sfix16_En14 SIGNAL twdl_re_reg : signed(15 DOWNTO 0); -- sfix16_En14 SIGNAL twdl_3_14_im_signed : signed(15 DOWNTO 0); -- sfix16_En14 SIGNAL twdl_im_reg : signed(15 DOWNTO 0); -- sfix16_En14 SIGNAL adder_add_cast_2 : signed(16 DOWNTO 0); -- sfix17_En14 SIGNAL adder_add_cast_3 : signed(16 DOWNTO 0); -- sfix17_En14 SIGNAL twdl_sum : signed(16 DOWNTO 0); -- sfix17_En14 SIGNAL Complex3Multiply_din1_re_pipe1 : signed(15 DOWNTO 0); -- sfix16 SIGNAL Complex3Multiply_din1_im_pipe1 : signed(15 DOWNTO 0); -- sfix16 SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(16 DOWNTO 0); -- sfix17 SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(31 DOWNTO 0); -- sfix32 SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(31 DOWNTO 0); -- sfix32 SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(33 DOWNTO 0); -- sfix34 SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(15 DOWNTO 0); -- sfix16 SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(15 DOWNTO 0); -- sfix16 SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(16 DOWNTO 0); -- sfix17 SIGNAL prodOfRe : signed(31 DOWNTO 0); -- sfix32_En27 SIGNAL prodOfIm : signed(31 DOWNTO 0); -- sfix32_En27 SIGNAL prodOfSum : signed(33 DOWNTO 0); -- sfix34_En27 SIGNAL din_vld_dly1 : std_logic; SIGNAL din_vld_dly2 : std_logic; SIGNAL din_vld_dly3 : std_logic; SIGNAL prod_vld : std_logic; SIGNAL Complex3Add_tmpResult_reg : signed(33 DOWNTO 0); -- sfix34 SIGNAL Complex3Add_multRes_re_reg1 : signed(32 DOWNTO 0); -- sfix33 SIGNAL Complex3Add_multRes_re_reg2 : signed(32 DOWNTO 0); -- sfix33 SIGNAL Complex3Add_multRes_im_reg : signed(34 DOWNTO 0); -- sfix35 SIGNAL Complex3Add_prod_vld_reg1 : std_logic; SIGNAL Complex3Add_prod_vld_reg2 : std_logic; SIGNAL Complex3Add_prodOfSum_reg : signed(33 DOWNTO 0); -- sfix34 SIGNAL Complex3Add_tmpResult_reg_next : signed(33 DOWNTO 0); -- sfix34_En27 SIGNAL Complex3Add_multRes_re_reg1_next : signed(32 DOWNTO 0); -- sfix33_En27 SIGNAL Complex3Add_multRes_re_reg2_next : signed(32 DOWNTO 0); -- sfix33_En27 SIGNAL Complex3Add_multRes_im_reg_next : signed(34 DOWNTO 0); -- sfix35_En27 SIGNAL Complex3Add_prod_vld_reg1_next : std_logic; SIGNAL Complex3Add_prod_vld_reg2_next : std_logic; SIGNAL Complex3Add_prodOfSum_reg_next : signed(33 DOWNTO 0); -- sfix34_En27 SIGNAL multResFP_re : signed(32 DOWNTO 0); -- sfix33_En27 SIGNAL multResFP_im : signed(34 DOWNTO 0); -- sfix35_En27 SIGNAL twdlXdin_14_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13 SIGNAL twdlXdin_14_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13 BEGIN din2_re_dly3_signed <= signed(din2_re_dly3); intdelay_process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN din_re_reg <= to_signed(16#0000#, 16); ELSIF clk'EVENT AND clk = '1' THEN IF enb_1_16_0 = '1' THEN IF softReset = '1' THEN din_re_reg <= to_signed(16#0000#, 16); ELSE din_re_reg <= din2_re_dly3_signed; END IF; END IF; END IF; END PROCESS intdelay_process; din2_im_dly3_signed <= signed(din2_im_dly3); intdelay_1_process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN din_im_reg <= to_signed(16#0000#, 16); ELSIF clk'EVENT AND clk = '1' THEN IF enb_1_16_0 = '1' THEN IF softReset = '1' THEN din_im_reg <= to_signed(16#0000#, 16); ELSE din_im_reg <= din2_im_dly3_signed; END IF; END IF; END IF; END PROCESS intdelay_1_process; adder_add_cast <= resize(din_re_reg, 17); adder_add_cast_1 <= resize(din_im_reg, 17); din_sum <= adder_add_cast + adder_add_cast_1; twdl_3_14_re_signed <= signed(twdl_3_14_re); intdelay_2_process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN twdl_re_reg <= to_signed(16#0000#, 16); ELSIF clk'EVENT AND clk = '1' THEN IF enb_1_16_0 = '1' THEN IF softReset = '1' THEN twdl_re_reg <= to_signed(16#0000#, 16); ELSE twdl_re_reg <= twdl_3_14_re_signed; END IF; END IF; END IF; END PROCESS intdelay_2_process; twdl_3_14_im_signed <= signed(twdl_3_14_im); intdelay_3_process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN twdl_im_reg <= to_signed(16#0000#, 16); ELSIF clk'EVENT AND clk = '1' THEN IF enb_1_16_0 = '1' THEN IF softReset = '1' THEN twdl_im_reg <= to_signed(16#0000#, 16); ELSE twdl_im_reg <= twdl_3_14_im_signed; END IF; END IF; END IF; END PROCESS intdelay_3_process; adder_add_cast_2 <= resize(twdl_re_reg, 17); adder_add_cast_3 <= resize(twdl_im_reg, 17); twdl_sum <= adder_add_cast_2 + adder_add_cast_3; -- Complex3Multiply Complex3Multiply_process : PROCESS (clk) BEGIN IF clk'EVENT AND clk = '1' THEN IF enb_1_16_0 = '1' THEN prodOfRe <= Complex3Multiply_prodOfRe_pipe1; prodOfIm <= Complex3Multiply_ProdOfIm_pipe1; prodOfSum <= Complex3Multiply_prodOfSum_pipe1; Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg; Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg; Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum; Complex3Multiply_din1_re_pipe1 <= din_re_reg; Complex3Multiply_din1_im_pipe1 <= din_im_reg; Complex3Multiply_din1_sum_pipe1 <= din_sum; Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1; Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1; Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1; END IF; END IF; END PROCESS Complex3Multiply_process; intdelay_4_process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN din_vld_dly1 <= '0'; ELSIF clk'EVENT AND clk = '1' THEN IF enb_1_16_0 = '1' THEN din_vld_dly1 <= di2_vld_dly3; END IF; END IF; END PROCESS intdelay_4_process; intdelay_5_process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN din_vld_dly2 <= '0'; ELSIF clk'EVENT AND clk = '1' THEN IF enb_1_16_0 = '1' THEN din_vld_dly2 <= din_vld_dly1; END IF; END IF; END PROCESS intdelay_5_process; intdelay_6_process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN din_vld_dly3 <= '0'; ELSIF clk'EVENT AND clk = '1' THEN IF enb_1_16_0 = '1' THEN din_vld_dly3 <= din_vld_dly2; END IF; END IF; END PROCESS intdelay_6_process; intdelay_7_process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN prod_vld <= '0'; ELSIF clk'EVENT AND clk = '1' THEN IF enb_1_16_0 = '1' THEN prod_vld <= din_vld_dly3; END IF; END IF; END PROCESS intdelay_7_process; -- Complex3Add Complex3Add_process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN Complex3Add_prodOfSum_reg <= to_signed(0, 34); Complex3Add_tmpResult_reg <= to_signed(0, 34); Complex3Add_multRes_re_reg1 <= to_signed(0, 33); Complex3Add_multRes_re_reg2 <= to_signed(0, 33); Complex3Add_multRes_im_reg <= to_signed(0, 35); Complex3Add_prod_vld_reg1 <= '0'; Complex3Add_prod_vld_reg2 <= '0'; ELSIF clk'EVENT AND clk = '1' THEN IF enb_1_16_0 = '1' THEN Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next; Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next; Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next; Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next; Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next; Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next; Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next; END IF; END IF; END PROCESS Complex3Add_process; Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1, Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg, Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2, Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld) VARIABLE sub_cast : signed(32 DOWNTO 0); VARIABLE sub_cast_0 : signed(32 DOWNTO 0); VARIABLE sub_cast_1 : signed(34 DOWNTO 0); VARIABLE sub_cast_2 : signed(34 DOWNTO 0); VARIABLE add_cast : signed(32 DOWNTO 0); VARIABLE add_cast_0 : signed(32 DOWNTO 0); VARIABLE add_temp : signed(32 DOWNTO 0); BEGIN Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg; Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1; Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg; Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1; IF prod_vld = '1' THEN sub_cast := resize(prodOfRe, 33); sub_cast_0 := resize(prodOfIm, 33); Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0; END IF; sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 35); sub_cast_2 := resize(Complex3Add_tmpResult_reg, 35); Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2; IF prod_vld = '1' THEN add_cast := resize(prodOfRe, 33); add_cast_0 := resize(prodOfIm, 33); add_temp := add_cast + add_cast_0; Complex3Add_tmpResult_reg_next <= resize(add_temp, 34); END IF; IF prod_vld = '1' THEN Complex3Add_prodOfSum_reg_next <= prodOfSum; END IF; Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1; Complex3Add_prod_vld_reg1_next <= prod_vld; multResFP_re <= Complex3Add_multRes_re_reg2; multResFP_im <= Complex3Add_multRes_im_reg; twdlXdin2_vld <= Complex3Add_prod_vld_reg2; END PROCESS Complex3Add_output; twdlXdin_14_re_tmp <= multResFP_re(29 DOWNTO 14); twdlXdin_14_re <= std_logic_vector(twdlXdin_14_re_tmp); twdlXdin_14_im_tmp <= multResFP_im(29 DOWNTO 14); twdlXdin_14_im <= std_logic_vector(twdlXdin_14_im_tmp); END rtl;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_18_fg_18_01.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- -- not in book library ieee; use ieee.std_logic_1164.all; entity fg_18_01_a is end entity fg_18_01_a; architecture writer of fg_18_01_a is begin process is subtype word is std_logic_vector(0 to 7); type load_file_type is file of word; file load_file : load_file_type open write_mode is "fg_18_01.dat"; begin write(load_file, word'(X"00")); write(load_file, word'(X"01")); write(load_file, word'(X"02")); write(load_file, word'(X"03")); write(load_file, word'(X"04")); write(load_file, word'(X"05")); write(load_file, word'(X"06")); write(load_file, word'(X"07")); write(load_file, word'(X"08")); write(load_file, word'(X"09")); write(load_file, word'(X"0A")); write(load_file, word'(X"0B")); write(load_file, word'(X"0C")); write(load_file, word'(X"0D")); write(load_file, word'(X"0E")); write(load_file, word'(X"0F")); wait; end process; end architecture writer; -- end not in book library ieee; use ieee.std_logic_1164.all; entity ROM is generic ( load_file_name : string ); port ( sel : in std_logic; address : in std_logic_vector; data : inout std_logic_vector ); end entity ROM; -------------------------------------------------- architecture behavioral of ROM is begin behavior : process is subtype word is std_logic_vector(0 to data'length - 1); type storage_array is array (natural range 0 to 2**address'length - 1) of word; variable storage : storage_array; variable index : natural; -- . . . -- other declarations type load_file_type is file of word; file load_file : load_file_type open read_mode is load_file_name; begin -- load ROM contents from load_file index := 0; while not endfile(load_file) loop read(load_file, storage(index)); index := index + 1; end loop; -- respond to ROM accesses loop -- . . . end loop; end process behavior; end architecture behavioral; -- not in book library ieee; use ieee.std_logic_1164.all; entity fg_18_01 is end entity fg_18_01; architecture test of fg_18_01 is signal sel : std_logic; signal address : std_logic_vector(3 downto 0); signal data : std_logic_vector(0 to 7); begin dut : entity work.ROM(behavioral) generic map ( load_file_name => "fg_18_01.dat" ) port map ( sel, address, data ); end architecture test; -- end not in book
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_18_fg_18_01.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- -- not in book library ieee; use ieee.std_logic_1164.all; entity fg_18_01_a is end entity fg_18_01_a; architecture writer of fg_18_01_a is begin process is subtype word is std_logic_vector(0 to 7); type load_file_type is file of word; file load_file : load_file_type open write_mode is "fg_18_01.dat"; begin write(load_file, word'(X"00")); write(load_file, word'(X"01")); write(load_file, word'(X"02")); write(load_file, word'(X"03")); write(load_file, word'(X"04")); write(load_file, word'(X"05")); write(load_file, word'(X"06")); write(load_file, word'(X"07")); write(load_file, word'(X"08")); write(load_file, word'(X"09")); write(load_file, word'(X"0A")); write(load_file, word'(X"0B")); write(load_file, word'(X"0C")); write(load_file, word'(X"0D")); write(load_file, word'(X"0E")); write(load_file, word'(X"0F")); wait; end process; end architecture writer; -- end not in book library ieee; use ieee.std_logic_1164.all; entity ROM is generic ( load_file_name : string ); port ( sel : in std_logic; address : in std_logic_vector; data : inout std_logic_vector ); end entity ROM; -------------------------------------------------- architecture behavioral of ROM is begin behavior : process is subtype word is std_logic_vector(0 to data'length - 1); type storage_array is array (natural range 0 to 2**address'length - 1) of word; variable storage : storage_array; variable index : natural; -- . . . -- other declarations type load_file_type is file of word; file load_file : load_file_type open read_mode is load_file_name; begin -- load ROM contents from load_file index := 0; while not endfile(load_file) loop read(load_file, storage(index)); index := index + 1; end loop; -- respond to ROM accesses loop -- . . . end loop; end process behavior; end architecture behavioral; -- not in book library ieee; use ieee.std_logic_1164.all; entity fg_18_01 is end entity fg_18_01; architecture test of fg_18_01 is signal sel : std_logic; signal address : std_logic_vector(3 downto 0); signal data : std_logic_vector(0 to 7); begin dut : entity work.ROM(behavioral) generic map ( load_file_name => "fg_18_01.dat" ) port map ( sel, address, data ); end architecture test; -- end not in book
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_18_fg_18_01.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- -- not in book library ieee; use ieee.std_logic_1164.all; entity fg_18_01_a is end entity fg_18_01_a; architecture writer of fg_18_01_a is begin process is subtype word is std_logic_vector(0 to 7); type load_file_type is file of word; file load_file : load_file_type open write_mode is "fg_18_01.dat"; begin write(load_file, word'(X"00")); write(load_file, word'(X"01")); write(load_file, word'(X"02")); write(load_file, word'(X"03")); write(load_file, word'(X"04")); write(load_file, word'(X"05")); write(load_file, word'(X"06")); write(load_file, word'(X"07")); write(load_file, word'(X"08")); write(load_file, word'(X"09")); write(load_file, word'(X"0A")); write(load_file, word'(X"0B")); write(load_file, word'(X"0C")); write(load_file, word'(X"0D")); write(load_file, word'(X"0E")); write(load_file, word'(X"0F")); wait; end process; end architecture writer; -- end not in book library ieee; use ieee.std_logic_1164.all; entity ROM is generic ( load_file_name : string ); port ( sel : in std_logic; address : in std_logic_vector; data : inout std_logic_vector ); end entity ROM; -------------------------------------------------- architecture behavioral of ROM is begin behavior : process is subtype word is std_logic_vector(0 to data'length - 1); type storage_array is array (natural range 0 to 2**address'length - 1) of word; variable storage : storage_array; variable index : natural; -- . . . -- other declarations type load_file_type is file of word; file load_file : load_file_type open read_mode is load_file_name; begin -- load ROM contents from load_file index := 0; while not endfile(load_file) loop read(load_file, storage(index)); index := index + 1; end loop; -- respond to ROM accesses loop -- . . . end loop; end process behavior; end architecture behavioral; -- not in book library ieee; use ieee.std_logic_1164.all; entity fg_18_01 is end entity fg_18_01; architecture test of fg_18_01 is signal sel : std_logic; signal address : std_logic_vector(3 downto 0); signal data : std_logic_vector(0 to 7); begin dut : entity work.ROM(behavioral) generic map ( load_file_name => "fg_18_01.dat" ) port map ( sel, address, data ); end architecture test; -- end not in book
-- -*- vhdl -*- ------------------------------------------------------------------------------- -- Copyright (c) 2012, The CARPE Project, All rights reserved. -- -- See the AUTHORS file for individual contributors. -- -- -- -- Copyright and related rights are licensed under the Solderpad -- -- Hardware License, Version 0.51 (the "License"); you may not use this -- -- file except in compliance with the License. You may obtain a copy of -- -- the License at http://solderpad.org/licenses/SHL-0.51. -- -- -- -- Unless required by applicable law or agreed to in writing, software, -- -- hardware and materials distributed under this License is distributed -- -- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -- -- either express or implied. See the License for the specific language -- -- governing permissions and limitations under the License. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library util; use util.types_pkg.all; use work.cpu_l1mem_data_cache_config_pkg.all; package cpu_l1mem_data_cache_replace_none_pkg is constant cpu_l1mem_data_cache_replace_none_state_bits : natural := 0; subtype cpu_l1mem_data_cache_replace_none_state_type is std_ulogic_vector(cpu_l1mem_data_cache_replace_none_state_bits-1 downto 0); type cpu_l1mem_data_cache_replace_none_ctrl_in_type is record re : std_ulogic; we : std_ulogic; wway : std_ulogic_vector(2**cpu_l1mem_data_cache_log2_assoc-1 downto 0); end record; type cpu_l1mem_data_cache_replace_none_ctrl_out_type is record rway : std_ulogic_vector(2**cpu_l1mem_data_cache_log2_assoc-1 downto 0); end record; type cpu_l1mem_data_cache_replace_none_dp_in_type is record rindex : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0); windex : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0); wstate : cpu_l1mem_data_cache_replace_none_state_type; end record; type cpu_l1mem_data_cache_replace_none_dp_out_type is record rstate : cpu_l1mem_data_cache_replace_none_state_type; end record; end package;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA entity tb_coeff_ram is end entity tb_coeff_ram; ---------------------------------------------------------------- architecture test_abstract of tb_coeff_ram is use work.coeff_ram_types.all; signal rd, wr : bit := '0'; signal addr : coeff_ram_address := 0; signal d_in, d_out : real := 0.0; begin dut : entity work.coeff_ram(abstract) port map ( rd => rd, wr => wr, addr => addr, d_in => d_in, d_out => d_out ); stumulus : process is begin wait for 100 ns; addr <= 10; d_in <= 10.0; wait for 10 ns; wr <= '1'; wait for 10 ns; d_in <= 20.0; wait for 10 ns; wr <= '0'; wait for 70 ns; addr <= 20; wait for 10 ns; rd <= '1'; wait for 10 ns; addr <= 10; wait for 10 ns; rd <= '0'; wait for 10 ns; wait; end process stumulus; end architecture test_abstract;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA entity tb_coeff_ram is end entity tb_coeff_ram; ---------------------------------------------------------------- architecture test_abstract of tb_coeff_ram is use work.coeff_ram_types.all; signal rd, wr : bit := '0'; signal addr : coeff_ram_address := 0; signal d_in, d_out : real := 0.0; begin dut : entity work.coeff_ram(abstract) port map ( rd => rd, wr => wr, addr => addr, d_in => d_in, d_out => d_out ); stumulus : process is begin wait for 100 ns; addr <= 10; d_in <= 10.0; wait for 10 ns; wr <= '1'; wait for 10 ns; d_in <= 20.0; wait for 10 ns; wr <= '0'; wait for 70 ns; addr <= 20; wait for 10 ns; rd <= '1'; wait for 10 ns; addr <= 10; wait for 10 ns; rd <= '0'; wait for 10 ns; wait; end process stumulus; end architecture test_abstract;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA entity tb_coeff_ram is end entity tb_coeff_ram; ---------------------------------------------------------------- architecture test_abstract of tb_coeff_ram is use work.coeff_ram_types.all; signal rd, wr : bit := '0'; signal addr : coeff_ram_address := 0; signal d_in, d_out : real := 0.0; begin dut : entity work.coeff_ram(abstract) port map ( rd => rd, wr => wr, addr => addr, d_in => d_in, d_out => d_out ); stumulus : process is begin wait for 100 ns; addr <= 10; d_in <= 10.0; wait for 10 ns; wr <= '1'; wait for 10 ns; d_in <= 20.0; wait for 10 ns; wr <= '0'; wait for 70 ns; addr <= 20; wait for 10 ns; rd <= '1'; wait for 10 ns; addr <= 10; wait for 10 ns; rd <= '0'; wait for 10 ns; wait; end process stumulus; end architecture test_abstract;
-- ------------------------------------------------------------- -- -- Generated Configuration for inst_shadow_10_e -- -- Generated -- by: wig -- on: Fri Jul 15 13:54:30 2005 -- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_shadow_10_e-c.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $ -- $Date: 2005/07/15 16:20:00 $ -- $Log: inst_shadow_10_e-c.vhd,v $ -- Revision 1.2 2005/07/15 16:20:00 wig -- Update all testcases; still problems though -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com -- (C) 2003 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/conf -- -- Start of Generated Configuration inst_shadow_10_rtl_conf / inst_shadow_10_e -- configuration inst_shadow_10_rtl_conf of inst_shadow_10_e is for rtl -- Generated Configuration end for; end inst_shadow_10_rtl_conf; -- -- End of Generated Configuration inst_shadow_10_rtl_conf -- -- --!End of Configuration/ies -- --------------------------------------------------------------
package impurefunc is signal a: bit; impure function impure_func return boolean; end package; package body impurefunc is impure function impure_func return boolean is begin a <= '1'; return FALSE; end function; end package body;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc3016.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- library WORK, STD; use STD.STANDARD.all; -- No_failure_here ENTITY c11s02b00x00p05n02i03016ent IS END c11s02b00x00p05n02i03016ent; ARCHITECTURE c11s02b00x00p05n02i03016arch OF c11s02b00x00p05n02i03016ent IS signal BV : BIT_VECTOR(0 to 7); BEGIN TESTING: PROCESS BEGIN BV <= "01010111" after 5 ns; wait for 10 ns; assert NOT( BV = "01010111" ) report "***PASSED TEST: c11s02b00x00p05n02i03016" severity NOTE; assert ( BV = "01010111" ) report "***FAILED TEST: c11s02b00x00p05n02i03016 - Library clause should appear as part of a context clause at the beginning of a design unit." severity ERROR; wait; END PROCESS TESTING; END c11s02b00x00p05n02i03016arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc3016.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- library WORK, STD; use STD.STANDARD.all; -- No_failure_here ENTITY c11s02b00x00p05n02i03016ent IS END c11s02b00x00p05n02i03016ent; ARCHITECTURE c11s02b00x00p05n02i03016arch OF c11s02b00x00p05n02i03016ent IS signal BV : BIT_VECTOR(0 to 7); BEGIN TESTING: PROCESS BEGIN BV <= "01010111" after 5 ns; wait for 10 ns; assert NOT( BV = "01010111" ) report "***PASSED TEST: c11s02b00x00p05n02i03016" severity NOTE; assert ( BV = "01010111" ) report "***FAILED TEST: c11s02b00x00p05n02i03016 - Library clause should appear as part of a context clause at the beginning of a design unit." severity ERROR; wait; END PROCESS TESTING; END c11s02b00x00p05n02i03016arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc3016.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- library WORK, STD; use STD.STANDARD.all; -- No_failure_here ENTITY c11s02b00x00p05n02i03016ent IS END c11s02b00x00p05n02i03016ent; ARCHITECTURE c11s02b00x00p05n02i03016arch OF c11s02b00x00p05n02i03016ent IS signal BV : BIT_VECTOR(0 to 7); BEGIN TESTING: PROCESS BEGIN BV <= "01010111" after 5 ns; wait for 10 ns; assert NOT( BV = "01010111" ) report "***PASSED TEST: c11s02b00x00p05n02i03016" severity NOTE; assert ( BV = "01010111" ) report "***FAILED TEST: c11s02b00x00p05n02i03016 - Library clause should appear as part of a context clause at the beginning of a design unit." severity ERROR; wait; END PROCESS TESTING; END c11s02b00x00p05n02i03016arch;
library ieee; use ieee.std_logic_1164.all; use work.types.all; use work.math.all; use work.sbox.all; entity cipher is port ( clk : in std_logic; reset : in std_logic; y : in std_logic_vector(1 downto 0); din : in state; rkey_in : in state; dout : out state ); function sub_bytes (din : state) return state is variable tin : s_list; variable tout : s_list; begin tin := to_s_list(din); for i in 0 to 15 loop tout(i) := sbox(tin(i)); end loop; return to_state(tout); end sub_bytes; function shift_rows (din : state) return state is variable tin : matrix; variable tout : matrix; begin tin := to_matrix(din); tout(0, 0) := tin(0, 0); tout(0, 1) := tin(0, 1); tout(0, 2) := tin(0, 2); tout(0, 3) := tin(0, 3); tout(1, 0) := tin(1, 1); tout(1, 1) := tin(1, 2); tout(1, 2) := tin(1, 3); tout(1, 3) := tin(1, 0); tout(2, 0) := tin(2, 2); tout(2, 1) := tin(2, 3); tout(2, 2) := tin(2, 0); tout(2, 3) := tin(2, 1); tout(3, 0) := tin(3, 3); tout(3, 1) := tin(3, 0); tout(3, 2) := tin(3, 1); tout(3, 3) := tin(3, 2); return to_state(tout); end shift_rows; function mix_columns (din : state) return state is variable tin : matrix; variable tout : matrix; begin tin := to_matrix(din); for col in 0 to 3 loop tout(0, col) := mul2(tin(0, col)) xor mul3(tin(1, col)) xor tin(2, col) xor tin(3, col); tout(1, col) := tin(0, col) xor mul2(tin(1, col)) xor mul3(tin(2, col)) xor tin(3, col); tout(2, col) := tin(0, col) xor tin(1, col) xor mul2(tin(2, col)) xor mul3(tin(3, col)); tout(3, col) := mul3(tin(0, col)) xor tin(1, col) xor tin(2, col) xor mul2(tin(3, col)); end loop; return to_state(tout); end mix_columns; function add_round_key (din : state; key : state) return state is variable tout : state; begin tout := din xor key; return tout; end add_round_key; end cipher; architecture behavioral of cipher is signal reg_D, reg_Q : state; signal sub_bytes_out, shift_rows_out, mix_columns_out, add_round_key_out, add_round_key_in : state; begin shift_rows_out <= shift_rows(sub_bytes(reg_Q)); mix_columns_out <= mix_columns(shift_rows_out); mux_3_1 : process(y, din, shift_rows_out, mix_columns_out) begin case y is when "00" => add_round_key_in <= din; when "01" => add_round_key_in <= mix_columns_out; when others => add_round_key_in <= shift_rows_out; end case; end process mux_3_1; add_round_key_out <= add_round_key(add_round_key_in, rkey_in); reg_D <= add_round_key_out; reg : entity work.state_reg port map(clk => clk, reset => reset, D => reg_D, Q => reg_Q ); dout <= reg_Q; end behavioral;
-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;
-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;
-- $Id: sys_tst_sram_n3.vhd 1181 2019-07-08 17:00:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_sram_n3 - syn -- Description: test of nexys3 sram and its controller -- -- Dependencies: vlib/xlib/s6_cmt_sfs -- vlib/genlib/clkdivce -- bplib/bpgen/bp_rs232_2l4l_iob -- bplib/bpgen/sn_humanio -- vlib/rlink/rlink_sp1c -- tst_sram -- bplib/nxcramlib/nx_cram_memctl_as -- -- Test bench: tb/tb_tst_sram_n3 -- -- Target Devices: generic -- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri -- 2014-12-20 614 14.7 131013 xc6slx16-2 922 1574 48 574 t 9.6 ns -- 2014-08-13 581 14.7 131013 xc6slx16-2 765 1261 32 441 t 9.6 ns -- 2011-12-21 442 13.4 O40d xc6slx16-2 722 1367 32 506 t 9.6 ns -- 2011-11-27 433 13.4 O40d xc6slx16-2 699 1194 20 406 t 8.9 ns -- -- Revision History: -- Date Rev Version Comment -- 2016-07-10 785 1.5.1 SWI(1) now XON; SWI(0) now portsel -- 2016-07-09 784 1.5 tst_sram with AWIDTH and 22bit support -- 2016-03-19 748 1.4.2 define rlink SYSID -- 2015-04-11 666 1.4.1 rearrange XON handling -- 2014-08-28 588 1.4 use new rlink v4 iface and 4 bit STAT -- 2014-08-15 583 1.3 rb_mreq addr now 16 bit -- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect -- 2011-12-21 442 1.1.1 use rlink_sp1c -- 2011-12-03 435 1.1 use int&ext serport and bp_rs232_2l4l_iob -- 2011-11-27 433 1.0 Initial version (derived from sys_tst_sram_n2) ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; use work.xlib.all; use work.genlib.all; use work.serportlib.all; use work.rblib.all; use work.rlinklib.all; use work.bpgenlib.all; use work.s3boardlib.all; use work.nxcramlib.all; use work.sys_conf.all; -- ---------------------------------------------------------------------------- entity sys_tst_sram_n3 is -- top level -- implements nexys3_fusp_aif port ( I_CLK100 : in slbit; -- 100 MHz clock I_RXD : in slbit; -- receive data (board view) O_TXD : out slbit; -- transmit data (board view) I_SWI : in slv8; -- n3 switches I_BTN : in slv5; -- n3 buttons O_LED : out slv8; -- n3 leds O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) O_MEM_WE_N : out slbit; -- cram: write enable (act.low) O_MEM_OE_N : out slbit; -- cram: output enable (act.low) O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) O_MEM_CLK : out slbit; -- cram: clock O_MEM_CRE : out slbit; -- cram: command register enable I_MEM_WAIT : in slbit; -- cram: mem wait O_MEM_ADDR : out slv23; -- cram: address lines IO_MEM_DATA : inout slv16; -- cram: data lines O_PPCM_CE_N : out slbit; -- ppcm: ... O_PPCM_RST_N : out slbit; -- ppcm: ... O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n I_FUSP_RXD : in slbit; -- fusp: rs232 rx O_FUSP_TXD : out slbit -- fusp: rs232 tx ); end sys_tst_sram_n3; architecture syn of sys_tst_sram_n3 is signal CLK : slbit := '0'; signal CE_USEC : slbit := '0'; signal CE_MSEC : slbit := '0'; signal GBL_RESET : slbit := '0'; signal RXD : slbit := '1'; signal TXD : slbit := '0'; signal CTS_N : slbit := '0'; signal RTS_N : slbit := '0'; signal SWI : slv8 := (others=>'0'); signal BTN : slv5 := (others=>'0'); signal LED : slv8 := (others=>'0'); signal DSP_DAT : slv16 := (others=>'0'); signal DSP_DP : slv4 := (others=>'0'); signal RB_MREQ : rb_mreq_type := rb_mreq_init; signal RB_SRES : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv4 := (others=>'0'); signal SER_MONI : serport_moni_type := serport_moni_init; signal RB_SRES_TST : rb_sres_type := rb_sres_init; signal RB_LAM_TST : slbit := '0'; signal MEM_RESET : slbit := '0'; signal MEM_REQ : slbit := '0'; signal MEM_WE : slbit := '0'; signal MEM_BUSY : slbit := '0'; signal MEM_ACK_R : slbit := '0'; signal MEM_ACK_W : slbit := '0'; signal MEM_ACT_R : slbit := '0'; signal MEM_ACT_W : slbit := '0'; signal MEM_ADDR : slv22 := (others=>'0'); signal MEM_BE : slv4 := (others=>'0'); signal MEM_DI : slv32 := (others=>'0'); signal MEM_DO : slv32 := (others=>'0'); constant sysid_proj : slv16 := x"0104"; -- tst_sram constant sysid_board : slv8 := x"03"; -- nexys3 constant sysid_vers : slv8 := x"00"; begin GEN_CLKSYS : s6_cmt_sfs generic map ( VCO_DIVIDE => sys_conf_clksys_vcodivide, VCO_MULTIPLY => sys_conf_clksys_vcomultiply, OUT_DIVIDE => sys_conf_clksys_outdivide, CLKIN_PERIOD => 10.0, CLKIN_JITTER => 0.01, STARTUP_WAIT => false, GEN_TYPE => sys_conf_clksys_gentype) port map ( CLKIN => I_CLK100, CLKFX => CLK, LOCKED => open ); CLKDIV : clkdivce generic map ( CDUWIDTH => 7, -- good for up to 127 MHz ! USECDIV => sys_conf_clksys_mhz, MSECDIV => 1000) port map ( CLK => CLK, CE_USEC => CE_USEC, CE_MSEC => CE_MSEC ); IOB_RS232 : bp_rs232_2l4l_iob port map ( CLK => CLK, RESET => '0', SEL => SWI(0), RXD => RXD, TXD => TXD, CTS_N => CTS_N, RTS_N => RTS_N, I_RXD0 => I_RXD, O_TXD0 => O_TXD, I_RXD1 => I_FUSP_RXD, O_TXD1 => O_FUSP_TXD, I_CTS1_N => I_FUSP_CTS_N, O_RTS1_N => O_FUSP_RTS_N ); HIO : sn_humanio generic map ( BWIDTH => 5) port map ( CLK => CLK, RESET => '0', CE_MSEC => CE_MSEC, SWI => SWI, BTN => BTN, LED => LED, DSP_DAT => DSP_DAT, DSP_DP => DSP_DP, I_SWI => I_SWI, I_BTN => I_BTN, O_LED => O_LED, O_ANO_N => O_ANO_N, O_SEG_N => O_SEG_N ); RLINK : rlink_sp1c generic map ( BTOWIDTH => 6, -- 64 cycles access timeout RTAWIDTH => 12, SYSID => sysid_proj & sysid_board & sysid_vers, IFAWIDTH => 5, -- 32 word input fifo OFAWIDTH => 5, -- 32 word output fifo ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, CDWIDTH => 13, CDINIT => sys_conf_ser2rri_cdinit, RBMON_AWIDTH => 0, RBMON_RBADDR => x"ffe8") port map ( CLK => CLK, CE_USEC => CE_USEC, CE_MSEC => CE_MSEC, CE_INT => CE_MSEC, RESET => GBL_RESET, ENAXON => SWI(1), ESCFILL => '0', RXSD => RXD, TXSD => TXD, CTS_N => CTS_N, RTS_N => RTS_N, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES, RB_LAM => RB_LAM, RB_STAT => RB_STAT, RL_MONI => open, SER_MONI => SER_MONI ); TST : entity work.tst_sram generic map ( RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)), AWIDTH => 22) port map ( CLK => CLK, RESET => GBL_RESET, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES_TST, RB_STAT => RB_STAT, RB_LAM => RB_LAM_TST, SWI => SWI, BTN => BTN(3 downto 0), LED => LED, DSP_DAT => DSP_DAT, MEM_RESET => MEM_RESET, MEM_REQ => MEM_REQ, MEM_WE => MEM_WE, MEM_BUSY => MEM_BUSY, MEM_ACK_R => MEM_ACK_R, MEM_ACK_W => MEM_ACK_W, MEM_ACT_R => MEM_ACT_R, MEM_ACT_W => MEM_ACT_W, MEM_ADDR => MEM_ADDR, MEM_BE => MEM_BE, MEM_DI => MEM_DI, MEM_DO => MEM_DO ); CRAMCTL : nx_cram_memctl_as generic map ( READ0DELAY => sys_conf_memctl_read0delay, -- was 2 for 50 MHz READ1DELAY => sys_conf_memctl_read1delay, -- was 2 " WRITEDELAY => sys_conf_memctl_writedelay) -- was 3 " port map ( CLK => CLK, RESET => MEM_RESET, REQ => MEM_REQ, WE => MEM_WE, BUSY => MEM_BUSY, ACK_R => MEM_ACK_R, ACK_W => MEM_ACK_W, ACT_R => MEM_ACT_R, ACT_W => MEM_ACT_W, ADDR => MEM_ADDR, BE => MEM_BE, DI => MEM_DI, DO => MEM_DO, O_MEM_CE_N => O_MEM_CE_N, O_MEM_BE_N => O_MEM_BE_N, O_MEM_WE_N => O_MEM_WE_N, O_MEM_OE_N => O_MEM_OE_N, O_MEM_ADV_N => O_MEM_ADV_N, O_MEM_CLK => O_MEM_CLK, O_MEM_CRE => O_MEM_CRE, I_MEM_WAIT => I_MEM_WAIT, O_MEM_ADDR => O_MEM_ADDR, IO_MEM_DATA => IO_MEM_DATA ); O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled O_PPCM_RST_N <= '1'; -- RB_SRES <= RB_SRES_TST; -- can be sres_or later... RB_LAM(0) <= RB_LAM_TST; DSP_DP(3) <= not SER_MONI.txok; DSP_DP(2) <= SER_MONI.txact; DSP_DP(1) <= not SER_MONI.rxok; DSP_DP(0) <= SER_MONI.rxact; end syn;
--! @file lfsr_ea.vhd --! @brief Direct Feedback LFSR implementation --! @author Scott Teal (Scott@Teals.org) --! @date 2013-11-06 --! @copyright --! Copyright 2013 Richard Scott Teal, Jr. --! --! Licensed under the Apache License, Version 2.0 (the "License"); you may not --! use this file except in compliance with the License. You may obtain a copy --! of the License at --! --! http://www.apache.org/licenses/LICENSE-2.0 --! --! Unless required by applicable law or agreed to in writing, software --! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT --! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the --! License for the specific language governing permissions and limitations --! under the License. --! Standard Library library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --! Import necessary local packages use work.util_pkg.all; --! Many-to-one Architecture of LFSR entity lfsr_direct is generic ( INTERNAL_SIZE : positive := 8; --! Set internal size of LFSR SEED : natural := 1; --! Choose custom seed of LFSR USE_XNOR : boolean := true; --! Use XNOR instead of XOR for feedback POLY : std_logic_vector --! Polynomial for LFSR to use ); port ( clk : in std_logic; --! System clock rst : in std_logic; --! System reset q : out std_logic_vector --! Output of LFSR ); end entity; --! Many-to-one Architecture of LFSR architecture rtl of lfsr_direct is --! LFSR full internal register signal lfsr_reg : std_logic_vector((INTERNAL_SIZE - 1) downto 0); --! Reversed polynomial constant used in direct feedback constant reverse_poly : std_logic_vector((INTERNAL_SIZE - 1) downto 0) := reverse(POLY); --! Reference to a bad seed of all '1'. Will cause lock-up state. constant BAD_SEED : std_logic_vector((INTERNAL_SIZE - 1) downto 0) := (others => '1'); begin -- State assumptions first assert std_logic_vector(to_unsigned(SEED, INTERNAL_SIZE)) /= BAD_SEED report "Chosen seed will cause LFSR lock-up" severity warning; assert INTERNAL_SIZE >= q'length report "Internal size must be at least as big as output" severity error; assert POLY'length = INTERNAL_SIZE report "Polynomial length must equal internal register size" severity error; --! Generate LFSR data_pipeline : process(clk, rst) begin if rising_edge(clk) then if rst = '1' then lfsr_reg <= std_logic_vector(to_unsigned(SEED, INTERNAL_SIZE)); else -- Many-to-one LFSR for i in lfsr_reg'range loop if i = lfsr_reg'high then lfsr_reg(i) <= xor ((not reverse_poly) or lfsr_reg); else lfsr_reg(i) <= lfsr_reg(i+1); end if; end loop; end if; -- rst = '1' end if; -- rising_edge(clk) end process; q <= lfsr_reg(q'range); end rtl;
-- hex_7seg_en -- conversor de dados hexadecimais para codigo de 7 segmentos -- com enable da saida library ieee; use ieee.std_logic_1164.all; entity hex_7seg_en is port ( hex : in std_logic_vector (3 downto 0); enable : in std_logic; d7seg : out std_logic_vector (6 downto 0) ); end hex_7seg_en; architecture hex_7seg_en of hex_7seg_en is signal segmentos : std_logic_vector(0 to 6); begin d7seg <= segmentos; process (hex,enable) begin if enable = '0' then segmentos <= "1111111"; -- apaga segmentos else case hex is when "0000" => segmentos <= "1000000"; -- 0 40 (hexa) when "0001" => segmentos <= "1111001"; -- 1 79 when "0010" => segmentos <= "0100100"; -- 2 24 when "0011" => segmentos <= "0110000"; -- 3 30 when "0100" => segmentos <= "0011001"; -- 4 19 when "0101" => segmentos <= "0010010"; -- 5 12 when "0110" => segmentos <= "0000010"; -- 6 02 when "0111" => segmentos <= "1011000"; -- 7 58 when "1000" => segmentos <= "0000000"; -- 8 00 when "1001" => segmentos <= "0010000"; -- 9 10 when "1010" => segmentos <= "0001000"; -- A 08 when "1011" => segmentos <= "0000011"; -- B 03 when "1100" => segmentos <= "1000110"; -- C 46 when "1101" => segmentos <= "0100001"; -- D 21 when "1110" => segmentos <= "0000110"; -- E 06 when others => segmentos <= "0001110"; -- F 0E end case; end if; end process; end hex_7seg_en;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block f6Oty/eDcaGLsYq7HUHaI50CR3KddeKCWngOPrYzxgssq5w1cJHPpguHxHGFdy9EIfCRoyTbcbsJ kzGkvWDMfw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block a03BS+f/GVrEwcrmiDY3uOfCIEA9kNUce+93LLKYgIl26Gpdil8/WWz92OplHD1bpM3jrixYXHbd BnEHPXgKM31RhVzuk/5zfTmy3nsu+VOf0JvjM2HHeNZ+jgbmWrZzt8xEvN100yexT3qCgLH3sVTa mOE4p/RZ+r3F8M7OokI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block nbUiSMAPmx4Uta8/yPjtP7MHRMUGv9u7CIISzhQDrv/X8gHcnpa6/8ubhCkNOCj54n3b7Bn8UxBw +F7p1GRc4oCPtwT5LTsoeOsukmuqS930j2k768KDUIqcoGPiZzBIaNulEraYDQiC2kt+eRpRPxMo JQRN1ZPr9DnZM5uZxeQoQxd959BvgqoC7gQakDUcu/tLh4AGSNRqM19H0DdzEj8/k3/9oepcPo0I DJ54cZYsEJmPZHTsPMmu0U8sU+8XKnOZkHerSO3cg6Ic2LKtKM23HBft8jb6t5JpiqGR4UTN9aAV zrcmnFt8zpphWudQkN7uqB2eI0Is7l/qdNe4Xw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block qvcDy9pMQR5dFHlKRINwzCU6wJ4e6PQXbV8+MnmLuLNhgau1fKZnkFgiRwpyf0UnKN1PEd+ix0Wc qmHHsPasKZF45LKqdY5LDM9mD1dWGBmaXOk6fsImJSTvf/EHa6SN6Cdzv2VDXj1RTDAt0Nhgm7VD vceZGP0d8idcHL1sHo4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ORJv3ey9G0h5DSRenT9jsgEdHTJUq1G3USaqvu86Um6q7L7Peke8GnAN5JYozuD9HwaZjtRqcq/R VtP0h+69M8H9yD5YTEYdsXkqq0RUXuS655hwWJ/uekzsap8YiIJRh6d/s+hDPz9jUHvu3GfIlNIA mg0YXQw2enlThFsTR2ezx9Rp1MZYGrkGUy/r3GbnT7gmSNFl7X3Q7VV2Sa2uwghsGojzMo0lHUqN 4LN2HwSfUrpvJ1/w8mLBRdNyHtTBXcqqbbbU/Yjq0lilXdnIMLuM4UwG1F3EANSbK0hmYN6o0gOI EQZrLP80jOpIgS5jgO4vLdGh8aOLHOe6FIfyIg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13712) `protect data_block znQjYNS3aAdNPe8VyLh/OvkxAa8F8tNwXWMv2jEuZYf/kECndfl7uAdCIVtS8KSCA/mTIYh0PWoT TT7LvrdwX17Y/QvQJRFTXMYG4z8h4AqkVV1AictktC4kUiSGF1ELVXwcXZ1gWLTzFmZLt+kwq3gy laAcwTsO7uv46nLVLBJN4N7BxfXKy/8K6rKEJc1FzUIYw6Kia+8NCgAucD37QawSUhfLNuUpm4wm aE7jobK7b1LzZjkEVsZrxGB/uj1q45YiTSzQM4VgSDE+zxESxqGLle7Oa1Flxvewe5GGMmmAqksa cA2VfNDLkZpK28SyvBMBU//y0+kn0g/NKmNESV0QDeJRc/GJffeVFUzL6/xwTb+bmO7xvG+iqEtf 1sEke/Ugx4+Yy6FV2szBiVXO9ByCVe+Yej1pFF+lT5TTUTNWe57BqXgzQNUTQSKCDMuMjiZ5BMfL 6VUZGPol3I1KHHDjlLyyQkubSb1UPykHiM4phhsINxAYnfWiZgvlNgY8lGK6ADCDlK7jSLihM1la Ghw6qOiVLGRA5QutLi3lzC5291eD2/ViUxeYVRpE+6L6TzPqgGsbXftqGChTL1uwEMXYoOHit4Oo JJgkoihyDdU9y0CCtWrTOBOVjrFhHTBu7c+01KsjWYMpi7MsKAySJpaz66sXgkP0s7uaKLNOOh6x /C0QY/Lyo+D237FXTI7hsD+6t3dFrql66vbuDoDGlUXCgroQ/dmR2t7iA7xztvQzka/W93S3j6bB sh5n/DMKWbC5e+lJbER9cULgXQOQV2o+7EvBFoNOFsFApdx0o6/COMeeb6j1aqfrTz3ZsU81XpJX tXrTVD1q+vyX55hw6jbjok+5usKji53//6Fqhaa3z8YeKUw7sMUDuPFsGboAdiXzoPpz+NKHPrwq P5tEKsgeb+/x4T9CWph4tDEUdBIrf/uGWu5GegJHveUu+flp47T3S1Kh7+VWotMTlokkmUFvyfcs 4n0AlyLaenFpsnVmztkyg4k50tp7YqjLLqLxWLTEe60nwn91DV8Y4mPeCfFE+9FRbt9c4zIHY5zR gpnWRQOBGokcP+yqQ9Fh4OPQbkb7JCIpAgaZL6TS3wMUJFHrdMlXKlNIqVbHw10KGVhhEUdD3QR2 Z8EfGIa8lOxSa9Vew3SrSSAyHbUcZe/HDuwJB0BHsVowcFyygyFrRWyCfknF5RY2lbQKwif6/+BS lDveW+vfy3BmbtI4ne7U73xC7avRA9oaXrhohC52o6U/vTAeB3+zxjdbuni1Vg83tSs/JgYm7gE0 sM3rUT7bvcEnTHRVwDtGhxezl7KGjGdMmGVUMJ2Yu/qruvXjK5iDOI421YzYw7EsP15or01f+2F7 l0eOMdcTKi3DIV+9wFn6ekq01/mfFh59XLsnomMkMNQEmVzXVXHYdh7nsiDEbIY6ZLHoffD+bBia bxpRRL8jCS2Zo72/1Y4v1NYjMSNOe/2jpOTCl021mOqlCxZW2/HJdJtL0yO9FpaM5bJkEaarqu7t F12UZ6SakGAAiD7HKU+bx40v+xnnvJWnWpSB9TZaDVVFaQcJFtZQTw5VY6rhhkKKwgddoYcAkwuO GKdthNz74UOmYbbUChnMCALA1UM/UZWbbcMdL7JjtVqrarIDG7sepxLsFktW4MBcxpteHsXQAg7F uEYr+uqlFqlavedFnQy5Dj/Py1UO9GHV1YNWRI6LBjqLShPMSRTgFhzmQmWjgF8DQBeb5MerX+4X KWc9dsn6MbRfYHnZmz2k5tHiF5D76juILuQfATDtax0vV01k0XXNTNQHDL1lX7mhtGBuUFleimQs q8pSFGvQO7U0KkNsTIA6/PyD/MAA1V45uXTb7oNFE6yR4oyAPhGjv5BGfFAkx5yFgacIT2PtVrZV OW6DJhULGuI0Tp6HynOSOWAUCUrep5GUv9vaaCHSHVsOyCxBk3pbEjeCuf6C1fX+/4OmGqQEJHAw D3/IfE5cOu5+o3w6qzL345zmHLdL+J5oYMkEHZm5nFHkT+UZrJPhbCUbUR4xxm9H1G0ppmm9NAan JiBodA5WYe07u13suOnaQntQg3ixYoJ1IjD2QX4t3z3Sz0/gmLei/fItXNzoPyYCcYl+n3WEASIf ZEScE6mgg2agK07RvCIgOMrRUDUigL8idhk4HcO5b2J4YUcDVrJwNUpfyzVXjFiModBvqyU6q2kl bclFPHL2Mkju3v6yLN1l0H6Sl+UIbLjpAIQAsqmQuICtCXtroM8MpFKULNtygQbimnI3NCV/iDEp kQ5XqoxNrnsVjp3++Smg13E2KDz4hnyV1QNImGgaZSKbhwBYcvQp2SD767ox0+fdyE3qRzN3hcBa 3PkixlX8YRJZNxJEu6u73hN/YSOATbxSHzFJppkTcFZHx+dQmoKCZjgDzxWSPIIQXEou4PI3JOgE POK9R6aLQdswBxzSy1MSNKj0nICQtE8X0zcdRpj+a4UqNW3ltbTwNP3bIGClDmdACETloct7U0Bk y7Ya2Cld1tVRLwK/Ldrg2fKIag17zcRXNjMXwICe+f57scMzEvGY9tTS9WApy7mWJEP2wWeodicb do+x7tyAVTBdrW+WKrlctmmKuZkA67JhoCFcC/IGI43UBcQkWipWxjc10YVDNOwCnhN+shANeGts 8NfBp3nEzuKlMNL3HD/QOmk5OTSfWmH4/GQ/T55hAm0gH2Fvvli99Btjx7+MhuBlA3kPL7ANxGgC barLIrYT+L4Zl+exStAXPFM2uZbJtdD++wWk2eB5mJOo8OZ9k6NHfMKt6hdRlq4PD5WQ/xCLWXht 4+2i8TAbGlb9X0KxsltfOM8G6KDJ2zZOhORRD4iJlqmfvon1mRQiKDTiOFiDSaaoFuXSoIALKW9h S0onMtnhjoOOLD8oQDpL1RBsAK1hSYgyhTu7lBZ//4XWRcdG/pHXLpNgN3HUYU4FH1ZQ++KWIRLH wXcIEBUD3lXeGicAGTTxnNuzvkHqnj62Ejt1yP0U2hVvOS5bPbkwJkDH+6ldkmNI1XSDqsD1PC6y UfBOrj4M12PQGwiC0SnxcfN0x6dQEslVniYgTq0VMRUf9xwX0Ze/M94ReKliPO4nM9JW9FdJr2u4 iKpUONXDP3uiCLTWe5G4Ph66tk45wtm+WOt2x9qpUOM5YSEGkYlcgIjRd4Qljhesaumd4RySr7oC k2VoMm0lN9ESqFGPTh2F7polporSK5Jezi+Kqyp9V9j8HesZn32nd5INBGc4fchCDGyz30LNZF6B iI49rLloBgvWjsoi4FKuPNhoG7GVWobHuGJ9WI3ojHr16EE7xKyaekeF7jx+5mP4840sEgnv8KuU G9ESEjcsLbKkAPXY4pXvSexegmwblRaECLnNXfRu93LrRMLuUGuRZizrAZQVO4eEZVkMelXIzRdN TQxO20IRBToKqWkQPsFgrhs7B9G4bCslYq+5rZkeaGRv2+zox3TYFCeJc1crQ421y3alTA/IaHB3 Exdr2NSeE0AC3QfB81TiyIerrLoLpwNngHVfPbXgq/CylG45va8b5uBMqWGuyhq/6dm3rb0fOOO4 CQX8PLtQuIpqLwmlQ6gOo921qqPuPmuULfYJST/e3lyZsr9C7/jqMBIJ6w15z2h/b9VV9NSiwavb V4uWLJPuyo59xWCyuMGoCXMp3gx1Rzp0kgTkQCvr5HLoLE75qimfol582BmmxvrEp9ExUfNcX9Lo eOkZtG5msxxoQK5Foyt+QObz5nHCOlaH/pzUmKaC6KgX8qzyUcdd1qOhRDtbm+ayKgKnMViWPR1h GTl0rG8r/+5hwa4Q3Yh5+6Q2je9T873L7twjyN7RXppH2I6y1GJvijRYXpkEAuNxMB5dfXqTQkiu qlw+qeuqkBz+d38h3mC00ai1MZMwU83+xrJYsfLbUv09JZ9pfvk1CfrgS7i6BCAueuO1/YygQB1f 4LnLqeK0Bzu/QhkMy7xNSucVRg1a9FXGLSmodfc6sY/IWLvwNQTC2WAXf+7a2hgeRvP+eC0tj13o yD1GMOkWcdGLd58I3HKyzN3xFFK6nHVnAbCmB4DRKSbtGvdO5wSVea2nEMrBLPsM/+ezL+A5aFH7 ngSMn5aiLfo9Gjive31QCU5YlziEGtjA+J+awGmhmszDAiBDaVKQ1KbQWTASNPGJxPJToj3ooemy +tcy0FIPFsML0W2hhrmatbfwUIxIkGe5N4q65CznyWqedg3ouWpsr9kXoTMM+tK+792RM6KzJRpA bstA4ETO+PtXr5KdloqW9yv0KaCO6FRE/5fuv8JnWKxvcLilSMle1J5YEkk9fSvcUS/ONQ8/evV5 UPJeafvTGcqmxyj3Hjb/xoqqQZvI8vCmeRISS/H1nImBr+0oy/bJomQy8vl0bNxqA4Z6JngOwvw/ LQU+boYj+okE/v8wST0t9ejzEd+0sHnskJXobmZuiwFFjmjvNl716hyfqfoQ5twBhzWWGaO7Fy7+ SAC8QtOW46qnTPyqenJdyO4Ucuge1Nv1sxoEsZdccYtFZu++PC76RPd9XZTSIOkO06k92X8z1Osa cVtzvam4qh+sI6xFvdAnyjkzmz6tkO/Ce1sG+yE1kd4y1hzN4z0GEECjq4dUoWAMR0TNIKTBmOaj 87lEZlesGDZ5ITJ0Xow5gw3kL+U5a7iWQB922JZjwOdckeAvFQX/4zy/FkzxGCiQwP44YCrkh6nZ 5Mx1eOD9g9NXxoeIKYcBCK0BNWqClfs6Pd+sKnIKXg9FHXVqS0OhX++V56h98/Pyb3ZU00H+bhzs U4ZBwlxFLC42XYTeLUb2KGfB0m83swOl4eGmBxgYQhgW0/5DKRZns03uvuyxwCHtHg0eSw+O5ogj 5JUR18uakkki7xCgEPtqP+ZW3siIMsAJNkLntFJ7WLYkWOMfFfLAoQ7Ys+c9GPsy+oJ8FbcLuNjm F8joiul1MSXcn68jRljwhemJ0C+d1IeQSTyKbgaYJnrn641qWuIS/p19Ez2D+vmqQhopgiWAz459 nRyG+l/2Ktc8BYFjA78jQM0vsvzihLcT13ATvafeBM15i7RkWO9mB2EgGtTgnvjerzaEyvqTv74K yxPc/0AsBNHZ9od7aZDlmPgK2qwGsQm4D1rnlIWx6ZrwCU6YnZY7okWf0VWOLyyJAU38WIP0eG0/ NxHslh0/GZjEPwqoqM/6MuB31d9NN7ZUYUFBg3JRX7vaq5hbNSxur1iLH0iGEUY03tOqwUwdHSFq p6LD7AaK+iT1Dx4qfYucpcPYAPZAl4DWTrAgORqP43x6rUHJJ7N7tnCDMiwCcci1bt3EZy5paLik cD69OFxgYbDLBgSNhpvp27MHcKvDHu0ti2ALIgqacsd+7jPYAxfkkog/KjMVnGNb3oirS7KNLIyP 87TjVTnZv5J6v8TDSWWqhazv6rOywn933rIt0upToVW5QU+PSSMjlnQuPOkLK409XEHdYzDG03fx 6oabCcu18qansSIibuDFFriZiCdScJ/pPqaNDpXVsdLHfq4ZDfvrvcZgtCAKKAbJw8U5aqfNOJ5q y/gqTrbvWR6HdDy9hqaAY6nfBXpXaHqd+KOqxXaWopvdXlJjQsx5qRIZJz2Hc0MOTDb0Lx7nW9sX 6BYodMo9EiYioo40SecBtWxnmoLW2BW9PYTVtBYRLRs2Ghfdi+4wZ1qDG0EtJODD1StLEPmo2TQH FQ9GkWAkEoUsntNPFIH4ySO35X7sKCLocq0eUW1FqcMUInNUUPHXUJa5ePwBlZ61uPg4qq9gQXGu YDPHU4EOLnCDyxoF0+zse4FkMapd5jLbP4YYUzs1cObrvJ21QtMFEIuBEGSU9p4bFicKoX/Gajhe Lblh4RZ4Cdb3jEKkm++7WSwcjo5cTX/sxRXFC42vC9HXveWuhy2qcVUPo1pkpEg7JYLo0QKtL7Ar t6IYxOa7RPjalA7JG5PYAoXSqdG0Zpzsn3MKAUJXP1UaJF0GyjIF8HVBKddBDqS/24owcS5kNCiH 9h6DL4dQG66JZ7AwzLJZ2Xs9JGu2EGL9ADFOKpPt43vIJX1tDvUY/01MtBp8nOVHkbWjGFPgv1pS ++51AJePe9Q+mHw42RigXt0dXPRRcWiK4MhGmTMHAq6AQ4chk/1SeU5tK0Jx69OINYimmlCfhDHB iuP2pQmH2cWrLT2LFK4knk4AijVJ/7pJVzSH7sCldbpv5Y6F90dQPAlC6YahI3r9v22VVIymBib0 15H3G0yINeoFNeCwpEYZNccjgtNz4qze+jHoHyZva6LgtG/7w/A0l8N9Rw0wipmktwLuajjrlqDh tIkEPTbMmk7+FrPHkzEDMDsOdjz1keOGKE4ByHNgY29GKuz51LOJZZ2CbfZDf+ZfRdrWuCZ6YRQD trqVjmhUiVH8JRpUgxhIMdJgIofM/DZJ/4Ce5Q15t0XXtMg+tl/t3lTqg/os3D9JTyW9IDrAF11l AD1m7KuF2sggTTe+mbekMOpQnSacgyblCoh/gxMuZQSPPMg27LmlExS9VGUCcPsq/5O25PAxyeZs WGfGtNumHyzoO8I2Qwm7fedIrv3C935zm2nO9AG0hj91oR1PiKXosYks5t5QDeb5VQtzkbYqicMh pzxhEqElaOfKzwYDb3RTSmYjIXR6hJy1/Q2ykVfh7CrxMkbK9ClnvE/JfRkJprhzjngNm0pweCAt 2mx5hTiiXZOw+ukbwvwQTqFIpNgWCJUmTMnMYLY1vdhF2LDbGa7c2B/l6yKdKgiV/LlgQRohPQxr N9RMN/0PhV6FDaPPVfAMrvx5oQ877uCyBEM2vJBfCpRYGbT5fwdA8V6mo+GSU8fVav4p2fbNrzZf 4dSTrEMq23zmd8x2rd1rv6H960YjRgctUjwMkG4AeDMua12I9Mea9uF2J2Kw857H9NFK1scbs+zX k1K6eG2T2CRiR0aPZYpobRO4JBt+kRB10yCetpSDQKJ7X0CxMgbu96p/mLWT0fzReRoGU3tcYTaU ofQcZJyGajmsg/itfHtR8gyeZ+pWhlRQoUxaVv/OZgpF3DDFT0/S0Z6/osF1hgymnH/sY5kw6Wfd nOrOR5G+gh8zIAui33kSWZBzmJoXXorjkRG7DysofJRW74QUmGJUWF1SFautoQTEHWuLKpzO32xL Y/mTFglhpbFB3f8QS8xhsl4B94uU3XYMgbzgkPVhHj5XOTBeJp3YA+nt/44qhuS2WcYk3AMXwq7B nupuFFEa8Mf2Fn6m3KJKDzFr1qre4vmMeAEn9bjPnBggd3rlgEbwO8LGyNVHciV4jbtJ4fxbEOXv Nk9Gv0avpt3v3ZfszE8hQV4lYM+5jRlvvFamBKUnka+VTdHqWuQK9NZuCeN+HoOCh9MRAWYkKrO8 D5f3PfkFnhx6E7LVrg8AQeKi6gc4IIlZByPQhpw5phj1XDdwETrPY/IcXPAOCHZxK47mg/T8IqoY 5b034tgDlHQHLar2v70/vastBwhroyWYReXM86eOp22aFjUqlkF2b/DD4SE3xOi349V/swW1JIEa LEf1cr+DNmxT3yg7CiYfT788pe5HaWG4+tznBNOcUbl+CLjCEFXdP4UN8aBBTcVb+q7s0V5/Qrkb rbM7hqUDlblWWj8AprR4Jfi6DPoalDbabB6yNb2QG/4bvjNUBWDUtjdxWl1cVd1J8GG4ItYrdA19 M2B2Lkf19ouv4J5D8FHPYkchoXdErVKOwuirNwzX0JSewTXyvBbkYLgImFsmpJKMevJY4VYwW25t KsWthsONph4M++Vmo2+ydiwh8GNWsarfOTHpku7VvTthnLOin006rhk/95OKF1oU42Sjlsv2ST+A 4Z4wzxdGDvPE7R2jzf8Mquy4WxGsaJKXPrbaMO/91DJzlgkTe1MMfONlmVv2f/EfMxxJ3rAC0Axv YNJqaBZqV5X6VuYj5oevE1hHS7pI2RlO1s+UA12LltHZ/qatlxqGbYbta6+olbp/I0R7bkyNoG79 Wc3lH1a+1z0Lpqfvosv1jKCSKfuY+ZkgM8NeHzOfZ0NS7ydNijmxaGG14cHkWbzQKOkwMZfqMmcr 6uMsxSfyEl4HXASx9x4Y77gQE1Sx+wlL1IwYcvi46l2FOO70WjXvhH97CQr1X6aV1PsWkIbvm7dt zbqhQDaYGbrTzxxvqfl2826Zd4ctAIPO1dJBEpkmCvOxE/jJnIFkoRpqkqybfs/rRtEF6GW2q7pc +Ti5pyC7n8OhHC9Aat2aE7jUJZpNODM6zNtU7EvkeomNBXRUEeNv1LflQMxp0r4U/fT6ty2k9QRo 0PvmsuOE5kuzacrMu7h4agOH7lspT2zO/L1E7TZWtSz7HRSOitKLTY3tCbMjn7MgxUFPdpPt1PmU VqB3R66IO5VnatPPLg7fD/ynemzfgvG0/TPntamAW+xaEjX8Qu2+ntWiwdts/dcwEcYqzTUJ93ix dOHZdlYP1220MmbYovb4Ol5PxneNFNQz1/d1rU8zNg1f2Rx0jKzJ28ux0T3Ieghtex3EGkvLtVh1 vLWsyVMymelmwOAmsbyxgZ7vLj7n+uqcdOqELKXWt874Zxg8YNh3wlZA7p/MgINJ1CI9fT6DpZjn V3YKsxPpsepYwLsbMmoP5ko6tadbYwT6FR9AJJA9KUWwkx40uS+4qap464vM1nkN7AxroLAH6/ln fR6PoYYzKxo6/lK3R8NwA/CwHJIkYpcfhfnWPGpp83OXfER64xVAuGmXxlNQeLgKFScTmV9vIj0/ aXTUk3jUY2VNK5hUrFGvXPhN6HBHxNouzU04fXGKyJQlLCt/RqwtzeuBXVm1B7Wwas/i8kT56Wwn aAF/inIdgQvCeT9XTLKQ4IQYetk1hPhPcUFiiUZAzk2iy/IQLNtgCd6RWiAnGaLqiwRhUuRKQpQ/ liFExfwfwP/xzmw85UMe9ohqlnH49fHcj+eEo++4bvJpH1CFZ4rwKmesLZpA22QIfkeYuWRBsKR8 /U5yBfbeGUfoqn7DrUcMuV6aQq6BlfW9U5YD04P/NJ/5nwC4K9QIJzkS/h4aej2SlWVdK1zdipZX kfL4JgJIB4kPjXnzNXR7CVFIJPSU3DlHUDxg3CSqp6MMemeP1nmUYknqly1lm0UAX+za6Mn045Mx VlsSymoTdCqTyz/PLBbRaZyMVreP4u1dAqHwwCuORM/ADRCev0WuEKf716ezRMdDLX9S9fTqGVSU AFr5HpgYnlSDpKLh3Q81uTPl5GSxz4wMwT1kBeiKUtSHaN81WH95JWekbp/ZYJzAiwah9EdYHIru uyieN7N81wpiJJgJYPXxL4+I3Ms89rb7JpFW/gOyxBp/i1suA3c6dw5+yiNKMa3+9FVVwjX9ZM5i Ox9Zf29uryDCK9eslWdrg/f3GjXgCuIRgxNnms/HWr7ctKMauqF4ckTXYT8OPUf52ipVgdUjYPKo ww840rTK61RS1gQU394bASUOKePrBDyg5RZNpLwz9HTPxNFEJ5Qo9V8RCjzgfiURgwtewPJrBGrm y5/50HUKxxnElpsLWHSsGni8pWRWw8Smwmox+RWm7jahKYTolxvAmsfl8uPoi6FHYqKBhrJpNN2j u5+34DYjVgsW5lRriT6kKbwpe5ZaLo83bJzOrkEik1G3lGSko6f3cPlMic3H+0UQpFK5f1kKH1dv ui+FmeQeTNAlOh13LDdrl2PfcPf88+YMJjDMyMzXXk5GVILlajwxJWdUT//um6yYp+jr2hl1TO0k E6XS2Dde0Qr6G9NGzl14npipmNEGqTi+MDRDttBfUSlXlUtFJUwUsn3/nbJT5JT9B/knee3mjuB2 gljrkzv+tYMBSSZUIK5MhtmSuKGxhwzPHfK4LrW+EgYGjzcNh9c5mDZHhVD+Odd31lIJVX0hQOQ9 pXV02PF8bqvyYWBu9b42adpKo9OVsI9buzNaFMPzvOsuvms9OkzfaUTOpa+vJ3fH4HSvggouo7PM mKHF6zN3VXht0oR1ZYQfMom1px7GQhwkl8TR4eWvdJtnL5NRFBXXj81WjeWJWeXU8oA+vPd5swi0 aHwqRxK0OmCRkLk5c6Zk0D/TTqS48RRoj+yG67QRzeVtqUNer/hrWOIYN/qm1EyLBuEPsfgLibn9 s+az+N85CLZDnEsphFEB0XmO4ijCSBJagvBX5lYpeeUaoyBscYICTusB/CRoNpHRH41XZIM8rquN PKvRsCoJdtwfRnVXdtO/ZIM3WBaZ35LcHPJrbAL1Dizt5BGkxzgq4oKwoGeqZVhuCKT1dMc8jkB0 YyTpGVEe3FHIvDoSU75DR0c9SH7r/VPh8XFDbRvadup1LiPeHeHVXtEQf/J9fslXLI+wIb4RirzS ve3d2vCvavZS4VhhfBHkspCL1uFaCOdZZyZG0fVJ8fQGx0hd2z+JmryS3Et42RPDDNTpKjsvBdg+ yI6BCUSQiN0QFX21JpDIKJ5hXOyiocUIHgvC0jsTpsPJ44XpkptLZ20TvdtaytWCgPwRPcnCtlBf CXeCCw1sRXgcIXp03LPOoFvs37vbcnLMNEqpInWSYrimqTlIH9oeIEqoAgHKBG7ZS0zqt6EP9kCH ISAEUoWJ0yuH5AYZ8m1THiaDaHfTyZDVdbF0OnmglTA34wmfJcQt5jWmAqOY2Fdvxve4PBbjh4Lm 5+aJjukGkVeYXpyq8x2wq4ljVCeLNkP33qbIrzHJQSPoDdVy8yLilhkaygvtEDbtZ84b9EVn4zQ2 S24hFVXV5Mg+nsL/byecTV1957DbCUBNlbDkv/Ru+r4FC4ukPs353RoOIvtN8RuzrOFnmoS67+FF adfNIgNoRBhpxQp54amVzR4s4twor0aO418JqlOiYfA4qdUZ43xulTTHKMH4d69C1qV0OtceVvWp 6Dpm9tu9CO1JYEjyxE9hWn1AXTWYN+h2LFeEjrsuECy3LP9fH8Uji2K3nCAoSzSTCNtDgICsainf oKkKuD0wOPlYx2cpaCQ26G74htC4zMCxK0t7BwTcLHRc+/RHYsfHAvDfY1ZGUge6m7Rn9gMQgWjZ eAJKir5x8R3uutZmxaj7zCOzaOHGmn8KLFzZIPjq48zXXGrj6F1842ddjn+bztKnoIXX09fP0aDL 8jHah/8vAtp0nEjswY2Ldbot5hC/Fy2j6PKiw0HsFxhIOdOzpfGaRkKvPqv98YlR6B0bulrCZyHP BUC5AAr3PH5QcMmBucXHLOg9LdovdNQz50RheKGbknpYBR5NIEirJxosY3uAMVB5WxSxvMlGgrZd OKIcPik2kcfaMbrpRcoppHhCaCyujyxUAKJ3egT4lqxwqX+RA4DFBQxWMz4TDHjMBlQwwhCP9UbN exHWTWCR14HUibEDRT3fVur+SQx5rsQ+P41Rx7h+SabagaZtUhOdhlvnDE4TVA1e2qYrS1RnOrXi b+5veBYQRV0eUDHdlG6iDiidiA0OCXJsedhMxjVZl2w3RLq+5CjAv7Yoz1F0NkQyfURqir1LrWU+ oczanhYU4u9lwU5Ekx3k9qD3BMZnfMPIuWN7u1wtdYlpxxgmalQIaLZ9bQxYBMxVgjpPqcoZ8u7Z /EPob52hKhTnWqLx1t9xL1IMfI+BNb16ypz8NUlYTsGxRPa10IEKFck10TEJbjqm3a2u6kdB/BtX dTbTA1KKvi1reEoJM7pzBmBgntRl/YawAcnHf6Gn8hEy/DNsg6hfkrGk7TrqTnHrT4ntc7hgkYJI wpybdgqR1y8gWiMnQMUIT8m7SHCqneMnxyze3IRN9b5HPzQyGTwbAXgUQ5qHWEVFYTOqtyxlcfiF gCuKUULrNeCxAWzBzBTLO/sUVYjqR4PWqRj8QmlwtyweDbBDqhIMce8/18XbD8C1HS4i9L5vTVwH zppztpukv0mbcwKQps9CwnR6Qt1roTFCKCZyAoZ4peKkifSczK8E8oY+eGh+gY2YAOUvUY3WmnKK xNfzTwc+en3BGH6FLt0fR6LnRgcQdjsKmuQfBd7jsYdR+y7mqDf3bnKDhtnnxdr46NcqGN90TBxo 3Jm7O6/mpF0WEP8+sxSxky/vREc2tneCln30BBuTgWiIVuBsdbVvgAvJg8yqRkTrS6Fmzjh397mZ 6BZaBgK2Iwj+GPGz2mhexLO+DQP4fwSXdJr9E+yoSl3+SE7MaAGfarD1hCbsdV1HoiiPKyCNANQT PuduIIG9sVA6XaZUszuBaEa7lzYInANKk0EQ3G0dc1Bjmyzd7MGb+MeAH/Tl0z7ECj1IelWsHP9s 8zJOUDDpXtO+wO6FQIYQYdBi5h9ETlxC5qwG59qx41QaOMGaLaPTfiZnq3xM3dL/+lPz4a6A9l+e 0G6wCAKwdAGWbHIkGEESLM8rAjsiPD6ztz7mTJzMpr3YXA/lwpz0i3hOQyLSRxRIoS7irGlHLhOs perA3d8lOoKGFeA8RAYrf0WD3XX8Bv006eTDqgYUUP79i+Wnd9D4U4aZEcjF3eK4Hqai6pajzMp6 90P34TtP5afcs5LC6Bc3u1EDZ+mD+l1PRWwpnp5IjiZQ3VHhEbuWMglW2WD+HGyLm3m1ksWCZcRl ME4CatHz5MjAp3RvLve+5G2EpsGZTWvFR+TNWjJy+xqO4Ix4NsQ+d8KSePKlinMNJr5eRtqG/BO1 5nXn6SlHHeB6cSZcdWsUkwEMPbtzVNW5UdbtQq/0OB1ZDRAWPacMMfNW4E4xqCfiKx8vFra4rVeV Gxb+mava7/a1W/xtqbPBwYfabhOdwKDtL2pjMO2oukUaiKo2EaRfev68wQSfICO4p0n7uNapp/rW g5rx08pJNMzrpwn1nN9WZDxZWeh3h3WWgeFrZUMfA++xpxJwJBFiR9u+UbGMyltlgOp/X0J8hJWF 3q3mP4FytPXI2klMYu6IYOv2W3eq0Gs8Zb93MWQBqxLlMGLtvVZr/N4PLXghtoWkDCrTnxjy3DHP mLBplk8D0Y3xkLQcsNimrfdiPMQsbk76tf3csegbfPc8nu6zw2Q2htrVPDIRczJffeDsbA/mydIe 1Pk5N92npW2zctyHwFkPcd9YVKuI+YMcOGF6SszqpE6AXPLlIrbpIPZAx47b+54+dW3CaLYpq+C6 mrYxaFJhyV+lyvVZjP79pLjXp9+bZi/RcuNVKJRJB7EOwcQH/Y6ArinUB3fptwYD/t10atLMOS8J s3iQ8mke58HejszKizMSyp+NNrHN2UdfuLbIcV4PH06suaIRUvBCcI1Fr6fG/iO/w9WXQiJW0OvE lp5AyMaTFj4QH2iRiIrmI82ZP9yTRcImWYSHaR6a9Sfyq/1tn+Dc5+yhcfpQsIRLf4mtoMtOv/Hg uOZhstz45PswqDMcJkRlD4dkPcZt3iidOQYjj82TJmxTAXUt3/B/AN3bj+B4kVzWw6PNYWlEcq8H aXcwNMVBMPYu6MEyqfMKUFRVz//sOtpb9qdrUIIsGPIAiiMMpYyV1SEhtBZdxjYZE8ZmKStDrMGB 4quM0eJNxRmg4JuLcJeZZRi6EngPTpEfCqtrZlS9jaX9ru+TDXKXQ72JEsGu9fzdjiE86ufjrvcd rxNlxV/IE6z32+r06lQfZLK22oAP4n1W2xDrbqkQb3loGbJABHFEsledqH542yv4XWV4zF2HpMzN 1wvczO/OyrQKGa0F+SceKo6gGB0M3Qwo/RctoSqgzBGrxKDc/soSYPnu1WZxSPfpi4oHmz16dLmD 8NzYp4zqEb4IJu+LWCYe1AfJHeEh5F/10/srHLuekdhVFbaq0FzY7ehVmcF7YoTKQo6l/muFjpdd AVfKJ3wAeVeMTlYTxO4M6/A46mWiQyyenMNdoX5kwXdRogUfrbRayfStgp6/OevDq1b8CDiJ1sU/ mKnWP3PPBz1eAZJxLzu1k33Qlu6FcZ6+I2yIgRFltORRj0NBbMr9jaCwiSNpb6vtRhYA1O54OYpF SEYtCjAWY4obbKY1CdlNtXlPzTr9+ps1d9U1xdTEzhTPJC2CWelduw3TAVN1ScNpmpFrda/nyXii VmlGd5mPB9suzfhSNYC5HLCWX+mB4S/CBfuG5kmYudGzGzaEUlDKoY+UcFjaglv5ruxVr6J37UHK C+J5rKxRByT8kWld95YPZrT3c4vWgGZcyQCy3XdrFyrzb218azXCkHo2txg7R0rZM8v793xGlLtP jVyluEPNV77qL1T3e/2uAZffxoMdOmHajmULn+rkXWAXLRY4DFtvb4GTb1WqCK51AQWkU9el2sen q8+KaeIgm0B5V3Mv+xazWjhIaGxh1vuojG5+1Hf5beCyI0fnEBgrTISogfWEYLAvRrTwDpehqxF4 hdxCpi4Vk7cfrOLW6+b2qas9r3l2a7eXZIt9onVAMYntevUITb9+wtP1YaAONDBC+Fa9g4LCdm2e xePVmpOypX5EUM95IGjzCF1OOEYRxdKqDGYNpSZj7t5YAO/J42Rxolup29PbiTyrdWfo7+eaTr5j 38KggbBtxCemCkl/0UMyM8oFJRdrcvp+EWejPONi8KF2Ix7zbrShV9Wv4uSOUv4bY5ixTMLCBkeu 90oveSXNzzX9y2od/UGxWdk4e6DTNke6XRuQWnmL8lj9qlyUbZ9KxHZjMpcWaEH85sJQv8KZOufh EHLT71um6SFn0uBSR7C7J3w3rXb0ZV7E0136QfqrLA2L6qnsoXPN0PkA0PDLl7qggoTC00Cceqet UxixOYqtum/CjMtC3IwDveIev09qijq4OU8IKQwbdi0PvQYLRLK8nLndTPGgae9Oq1u9yJLFz816 fezX+6AhNTw7P9OMwwHjTHrxYmQxND9sYBsxrX/RFU+0wO/nHR1jWdrFVQIYW4k1sIDWEPEoDI81 PgDVLoQ9E+AD3t9fggPEcy02ZOkXBPpmzTHOV3vggX96+uSuq5yBH5uyhnyFmr+803pFbq3BYXnH 6zN/6myXsy0OyRsiuSzeRj/OZZGwaEuPgz34DfvwT9ZVMdsYwn+bTc/20St0t8/987g4k//grRtr gP0/M1bptIbM2shk5ysoJLeEV41jBklJr/2l8DArmJ3cinSxU0bfEi13IPDt5rfnHoEGPBn6R5rj A0iP5luJmGYgZWXGLecFjNMJsOtbpEqhUVm6uWd61VXiZGeuCd5OdjulxN63AJ2VmxU3I6PCpqpQ ZzfRC2Cn++TkCRJmGAi8oAXwrv6HBqrHNY4RQErLxzn2IUD+Row7XvDHvKWaPYZ1T6r7Bokncg3o LUHuln8OWy6z+9bqka+oTJgrBYDqiKr1Y0PZsk5XCJwctf8ZmgGZd/GfZBw8VVfKN+vyRAAk4J8j HJ5yO0h00jV/IV0Kxci5yUQDokJronIwMeImu+SogYY2nnh/N1AGFEhf2fP+ZZAb6r+hpGBnnD6S ac1qBGuhHY2mzk15RCn0J9bD+2cR9w2q5DLK6JvR4DpJiVUlMBufoBqBpV2TGwvNSWScw5Y2PZTm 1Iyqx1vSe42n2Zuvh/c82pk/qhtRD3jLkvfRTIFpFsgZJikqSewWTqsN9WHZrcyzaFuuv3pC72do BTdCLBl7ksiH/kOXc9pPl6dfOy9r0kdqEbrLlxIK73LqMl/totbRkKDyp5KSBRCSmjHArTkR3P2V UMSHnJOsBIVbf7b2fzFSBqcTynSJTsO/jMvoSX8L8mXy1gvV8LjGbPINnb566cE7ctwudwC3WZRL rOgR4382wwKBMpigTwvwkBQk0ypN4xIWpld+ndl8KBnN8tKa3/kq7RcLFJXiyhmAdlWQ6GBEv9tk Z+uA+znPGFVp9hmnuR79LkkOg54gl61HjaqQ3DuM3AL1WsOrL8feSXqZHZViKLvgGStg+liPdvsU 1tc0XtWH62A9Bq1qWiJ3l52Q92KfdmdkUVsv/IYAREoWhtXkV4dytdb0eoaNdqWExr33xazv3UUF e6GL5HuDliyRmcOrT1c7t+S3Krg0coEfgU1CRMw7ZXsFgEwCO1E7bgC+hllS7nUfGJGtXgoHqJAs uw+KfMLe0DCfbCT2XGU0H1UteQ0KrEAp/cd5Dp/qbwETS6z6qsae6j8wbd6tOVzE5Z9XSrqfenIB 50EB5xCxLTV/1ji9UNJIELcfS9SUdCQH35wSwV+WrfS/YgAlVOhmj4+M8o5MGHit+/5PfSE30GLS kftN1BH4F6yvlgy29B/fFecgb1eW4qdsiuoD4oX4y1YvrjfZqxf8bCAO2lcY44CsJz8YjQojv213 4qq5IAa4Dp5UKQwEIrZYKrNu8MNWUD+0O0JjgespSt66v3H5fNyNqiiwT5zeeer3j0rXLNzemWYk RZTYroWgQM2BgSGYfA0xwSDecH3wkCZcwpUKW4tFDGI6egSgQFvmfLfBpdng9AhmWZ+Lh7FNNsfo OutrbqkCX4FdPsy79XR0+oZVGSZviqaUJN0FFe4PZz+DiSy8fiaOKZ69B0h1+ACKx6e4at5rKMS0 PvaNcUZ0FOvZVP/cjWxxzVF2gweH8BglmfktVZSL3Alz+Aia0suhCJjP1aqDbpLzVhJA+ZPMZKVm tGYNwNECRog8XMRMRMIuueMlMPDt6nczAlUSJPY+Rkz2p94MAD6MSOsVVLsrqHYRmIvzps9uP5ed bkIur57uYOU++62nQlmqfGNo+KDIcZ3xvy4z64yRHW7bbySUhS8HdcvoRk8wb4iRo/C7NsVVp/fe 5dHOawhhsIxVm246QkxRfvQ1oiu6Y7rRIhsWGVYCCJ6TSc+wmefCvqMTQjBjxE8OsnWphedGgZx7 duvX6HYFTeaVtlTtZe7qGgwNO7NSguD2dCA+epBq7eBvvOT+/jxg9DjbcrZfBq6I2uBut7am30dV b3Rkm09jesGqARwNn8VKnDz5mkq7/GgxwTmw1T46MaX1w54X/76MneZzukSUaXX4CrMAuXAtMueH Ba1Qx6BFhcfzE7g0f9LewZdL7hyAe4LSqNT32p7O13Gz1TGjcKYP2mccjHJFnHM4NxGE7ZoY8PDL vpAmOc/9QnP8onCjqUKY/kkdwTxV5bpv3SHxnvftfKtZm3vIUMyThxJhefpHZfJ9odlAidTji9iP 7PuKNM/A+/zKufUlpNx/E9RKAhIq4lpULdmIbcJx1WGacSg3Xt/q8SPDxxp9LpResF7g7yZ6dvio eGiK2RXuLD+YhITpbOA+hcpjwNZFrh0fQc7U/9ijVr+CDTB76mcfYIivGwKFc4mzT+PEB3MZqD0o 5gS3TPdvSkXq5fCnT86XOc2S+CFwI9ulZDAkOX76QjOVI6NBp053+3zkZXGGkPQXgtmSBRLbOPPu XD9/MAGlncxBHX2+phXqZJiTBM1vFfGds+AM4v/n+TvQEgPKruDNRScypzSMe101luiKKGOWeYW2 MtxoreLtN/BKqGYC0PCL2OzFPdG01UYUX+QxMgxDogXE9X39npHq5Tc2k4KeZ6ghzTH2irptBZ8D 7UhcRnxHbTDp8ApPamMvUXjQBdgLcbfR/g8bqkPMd+EbdzHs+WwYxz91KFDIOhTKkB1n1I8osYmd NyJdBXUn4957DKhMfEnisgocuNg2DcSsFTr9FSnhQxMP0/5YJgPx+igAVIjQaUz4js27FFtPS9F7 XXOo02MwhRiutlSsJSczoTIO9WaOUlD4kXScdvVtcTIc8Fq3L3O1HQK82gVVLbYTJsQdllvZyOs0 lC5jM7CCf9hrBsgXPUYBhWC3LNJ7PU7NpCb0t0McRFVqYwulJXn1gR4z0Ry+ahTLP6J/xDW5WlJw wLX4sQQ697Bqr5ab3J+GldU57m9QXaZIU1pD9X/7RksTLg94Cfs/06zWw9SNps3sQvMK6ePR+N4E 1J60hp7bHyzFP+Y1pIWORl8LkT+ixs1tXF37J6cKxhewklgnZ0MMHylG5nlexLhiF3chL827FNIg D+rH9QyeoFyO0RFakmTS1V/P3rM8ULlMSIT8El07CJ24TFYxlvp/OF8i3yExDU+cfA42rGY68Itb dcugluX2SkrMsNwRqtp9dMXBrVgtQ2Qcr9cKfNCIIl0KfAXWveWAiL+4NTt9ibUqRxnLy03F4qVu gCyudq/EclAi7JgZn3B8n9YRiEvURVqNMPjump8EuPQnQgCUc78jx11KIFrzdnNch2HxdJ0u41gK K+xAEaK+CVSBaNs32q2dHzzY0jtfFr5GvpmLgSIPRRI91r8pZXuob+t3kmxGE6zphDlgcWuuRn89 qGs5wss+A0hR+/SiWIckgX/KNQvNGmcQzLuu0DaaVwJlWueMZH0WqGXwvkxUMnX400gQvLQT2740 wfwP0UMldDqHkkuA4LLurGnjWNKeCaMVLDF9wbp1C4c= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block f6Oty/eDcaGLsYq7HUHaI50CR3KddeKCWngOPrYzxgssq5w1cJHPpguHxHGFdy9EIfCRoyTbcbsJ kzGkvWDMfw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block a03BS+f/GVrEwcrmiDY3uOfCIEA9kNUce+93LLKYgIl26Gpdil8/WWz92OplHD1bpM3jrixYXHbd BnEHPXgKM31RhVzuk/5zfTmy3nsu+VOf0JvjM2HHeNZ+jgbmWrZzt8xEvN100yexT3qCgLH3sVTa mOE4p/RZ+r3F8M7OokI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block nbUiSMAPmx4Uta8/yPjtP7MHRMUGv9u7CIISzhQDrv/X8gHcnpa6/8ubhCkNOCj54n3b7Bn8UxBw +F7p1GRc4oCPtwT5LTsoeOsukmuqS930j2k768KDUIqcoGPiZzBIaNulEraYDQiC2kt+eRpRPxMo JQRN1ZPr9DnZM5uZxeQoQxd959BvgqoC7gQakDUcu/tLh4AGSNRqM19H0DdzEj8/k3/9oepcPo0I DJ54cZYsEJmPZHTsPMmu0U8sU+8XKnOZkHerSO3cg6Ic2LKtKM23HBft8jb6t5JpiqGR4UTN9aAV zrcmnFt8zpphWudQkN7uqB2eI0Is7l/qdNe4Xw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block qvcDy9pMQR5dFHlKRINwzCU6wJ4e6PQXbV8+MnmLuLNhgau1fKZnkFgiRwpyf0UnKN1PEd+ix0Wc qmHHsPasKZF45LKqdY5LDM9mD1dWGBmaXOk6fsImJSTvf/EHa6SN6Cdzv2VDXj1RTDAt0Nhgm7VD vceZGP0d8idcHL1sHo4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ORJv3ey9G0h5DSRenT9jsgEdHTJUq1G3USaqvu86Um6q7L7Peke8GnAN5JYozuD9HwaZjtRqcq/R VtP0h+69M8H9yD5YTEYdsXkqq0RUXuS655hwWJ/uekzsap8YiIJRh6d/s+hDPz9jUHvu3GfIlNIA mg0YXQw2enlThFsTR2ezx9Rp1MZYGrkGUy/r3GbnT7gmSNFl7X3Q7VV2Sa2uwghsGojzMo0lHUqN 4LN2HwSfUrpvJ1/w8mLBRdNyHtTBXcqqbbbU/Yjq0lilXdnIMLuM4UwG1F3EANSbK0hmYN6o0gOI EQZrLP80jOpIgS5jgO4vLdGh8aOLHOe6FIfyIg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13712) `protect data_block znQjYNS3aAdNPe8VyLh/OvkxAa8F8tNwXWMv2jEuZYf/kECndfl7uAdCIVtS8KSCA/mTIYh0PWoT TT7LvrdwX17Y/QvQJRFTXMYG4z8h4AqkVV1AictktC4kUiSGF1ELVXwcXZ1gWLTzFmZLt+kwq3gy laAcwTsO7uv46nLVLBJN4N7BxfXKy/8K6rKEJc1FzUIYw6Kia+8NCgAucD37QawSUhfLNuUpm4wm aE7jobK7b1LzZjkEVsZrxGB/uj1q45YiTSzQM4VgSDE+zxESxqGLle7Oa1Flxvewe5GGMmmAqksa cA2VfNDLkZpK28SyvBMBU//y0+kn0g/NKmNESV0QDeJRc/GJffeVFUzL6/xwTb+bmO7xvG+iqEtf 1sEke/Ugx4+Yy6FV2szBiVXO9ByCVe+Yej1pFF+lT5TTUTNWe57BqXgzQNUTQSKCDMuMjiZ5BMfL 6VUZGPol3I1KHHDjlLyyQkubSb1UPykHiM4phhsINxAYnfWiZgvlNgY8lGK6ADCDlK7jSLihM1la Ghw6qOiVLGRA5QutLi3lzC5291eD2/ViUxeYVRpE+6L6TzPqgGsbXftqGChTL1uwEMXYoOHit4Oo JJgkoihyDdU9y0CCtWrTOBOVjrFhHTBu7c+01KsjWYMpi7MsKAySJpaz66sXgkP0s7uaKLNOOh6x /C0QY/Lyo+D237FXTI7hsD+6t3dFrql66vbuDoDGlUXCgroQ/dmR2t7iA7xztvQzka/W93S3j6bB sh5n/DMKWbC5e+lJbER9cULgXQOQV2o+7EvBFoNOFsFApdx0o6/COMeeb6j1aqfrTz3ZsU81XpJX tXrTVD1q+vyX55hw6jbjok+5usKji53//6Fqhaa3z8YeKUw7sMUDuPFsGboAdiXzoPpz+NKHPrwq P5tEKsgeb+/x4T9CWph4tDEUdBIrf/uGWu5GegJHveUu+flp47T3S1Kh7+VWotMTlokkmUFvyfcs 4n0AlyLaenFpsnVmztkyg4k50tp7YqjLLqLxWLTEe60nwn91DV8Y4mPeCfFE+9FRbt9c4zIHY5zR gpnWRQOBGokcP+yqQ9Fh4OPQbkb7JCIpAgaZL6TS3wMUJFHrdMlXKlNIqVbHw10KGVhhEUdD3QR2 Z8EfGIa8lOxSa9Vew3SrSSAyHbUcZe/HDuwJB0BHsVowcFyygyFrRWyCfknF5RY2lbQKwif6/+BS lDveW+vfy3BmbtI4ne7U73xC7avRA9oaXrhohC52o6U/vTAeB3+zxjdbuni1Vg83tSs/JgYm7gE0 sM3rUT7bvcEnTHRVwDtGhxezl7KGjGdMmGVUMJ2Yu/qruvXjK5iDOI421YzYw7EsP15or01f+2F7 l0eOMdcTKi3DIV+9wFn6ekq01/mfFh59XLsnomMkMNQEmVzXVXHYdh7nsiDEbIY6ZLHoffD+bBia bxpRRL8jCS2Zo72/1Y4v1NYjMSNOe/2jpOTCl021mOqlCxZW2/HJdJtL0yO9FpaM5bJkEaarqu7t F12UZ6SakGAAiD7HKU+bx40v+xnnvJWnWpSB9TZaDVVFaQcJFtZQTw5VY6rhhkKKwgddoYcAkwuO GKdthNz74UOmYbbUChnMCALA1UM/UZWbbcMdL7JjtVqrarIDG7sepxLsFktW4MBcxpteHsXQAg7F uEYr+uqlFqlavedFnQy5Dj/Py1UO9GHV1YNWRI6LBjqLShPMSRTgFhzmQmWjgF8DQBeb5MerX+4X KWc9dsn6MbRfYHnZmz2k5tHiF5D76juILuQfATDtax0vV01k0XXNTNQHDL1lX7mhtGBuUFleimQs q8pSFGvQO7U0KkNsTIA6/PyD/MAA1V45uXTb7oNFE6yR4oyAPhGjv5BGfFAkx5yFgacIT2PtVrZV OW6DJhULGuI0Tp6HynOSOWAUCUrep5GUv9vaaCHSHVsOyCxBk3pbEjeCuf6C1fX+/4OmGqQEJHAw D3/IfE5cOu5+o3w6qzL345zmHLdL+J5oYMkEHZm5nFHkT+UZrJPhbCUbUR4xxm9H1G0ppmm9NAan JiBodA5WYe07u13suOnaQntQg3ixYoJ1IjD2QX4t3z3Sz0/gmLei/fItXNzoPyYCcYl+n3WEASIf ZEScE6mgg2agK07RvCIgOMrRUDUigL8idhk4HcO5b2J4YUcDVrJwNUpfyzVXjFiModBvqyU6q2kl bclFPHL2Mkju3v6yLN1l0H6Sl+UIbLjpAIQAsqmQuICtCXtroM8MpFKULNtygQbimnI3NCV/iDEp kQ5XqoxNrnsVjp3++Smg13E2KDz4hnyV1QNImGgaZSKbhwBYcvQp2SD767ox0+fdyE3qRzN3hcBa 3PkixlX8YRJZNxJEu6u73hN/YSOATbxSHzFJppkTcFZHx+dQmoKCZjgDzxWSPIIQXEou4PI3JOgE POK9R6aLQdswBxzSy1MSNKj0nICQtE8X0zcdRpj+a4UqNW3ltbTwNP3bIGClDmdACETloct7U0Bk y7Ya2Cld1tVRLwK/Ldrg2fKIag17zcRXNjMXwICe+f57scMzEvGY9tTS9WApy7mWJEP2wWeodicb do+x7tyAVTBdrW+WKrlctmmKuZkA67JhoCFcC/IGI43UBcQkWipWxjc10YVDNOwCnhN+shANeGts 8NfBp3nEzuKlMNL3HD/QOmk5OTSfWmH4/GQ/T55hAm0gH2Fvvli99Btjx7+MhuBlA3kPL7ANxGgC barLIrYT+L4Zl+exStAXPFM2uZbJtdD++wWk2eB5mJOo8OZ9k6NHfMKt6hdRlq4PD5WQ/xCLWXht 4+2i8TAbGlb9X0KxsltfOM8G6KDJ2zZOhORRD4iJlqmfvon1mRQiKDTiOFiDSaaoFuXSoIALKW9h S0onMtnhjoOOLD8oQDpL1RBsAK1hSYgyhTu7lBZ//4XWRcdG/pHXLpNgN3HUYU4FH1ZQ++KWIRLH wXcIEBUD3lXeGicAGTTxnNuzvkHqnj62Ejt1yP0U2hVvOS5bPbkwJkDH+6ldkmNI1XSDqsD1PC6y UfBOrj4M12PQGwiC0SnxcfN0x6dQEslVniYgTq0VMRUf9xwX0Ze/M94ReKliPO4nM9JW9FdJr2u4 iKpUONXDP3uiCLTWe5G4Ph66tk45wtm+WOt2x9qpUOM5YSEGkYlcgIjRd4Qljhesaumd4RySr7oC k2VoMm0lN9ESqFGPTh2F7polporSK5Jezi+Kqyp9V9j8HesZn32nd5INBGc4fchCDGyz30LNZF6B iI49rLloBgvWjsoi4FKuPNhoG7GVWobHuGJ9WI3ojHr16EE7xKyaekeF7jx+5mP4840sEgnv8KuU G9ESEjcsLbKkAPXY4pXvSexegmwblRaECLnNXfRu93LrRMLuUGuRZizrAZQVO4eEZVkMelXIzRdN TQxO20IRBToKqWkQPsFgrhs7B9G4bCslYq+5rZkeaGRv2+zox3TYFCeJc1crQ421y3alTA/IaHB3 Exdr2NSeE0AC3QfB81TiyIerrLoLpwNngHVfPbXgq/CylG45va8b5uBMqWGuyhq/6dm3rb0fOOO4 CQX8PLtQuIpqLwmlQ6gOo921qqPuPmuULfYJST/e3lyZsr9C7/jqMBIJ6w15z2h/b9VV9NSiwavb V4uWLJPuyo59xWCyuMGoCXMp3gx1Rzp0kgTkQCvr5HLoLE75qimfol582BmmxvrEp9ExUfNcX9Lo eOkZtG5msxxoQK5Foyt+QObz5nHCOlaH/pzUmKaC6KgX8qzyUcdd1qOhRDtbm+ayKgKnMViWPR1h GTl0rG8r/+5hwa4Q3Yh5+6Q2je9T873L7twjyN7RXppH2I6y1GJvijRYXpkEAuNxMB5dfXqTQkiu qlw+qeuqkBz+d38h3mC00ai1MZMwU83+xrJYsfLbUv09JZ9pfvk1CfrgS7i6BCAueuO1/YygQB1f 4LnLqeK0Bzu/QhkMy7xNSucVRg1a9FXGLSmodfc6sY/IWLvwNQTC2WAXf+7a2hgeRvP+eC0tj13o yD1GMOkWcdGLd58I3HKyzN3xFFK6nHVnAbCmB4DRKSbtGvdO5wSVea2nEMrBLPsM/+ezL+A5aFH7 ngSMn5aiLfo9Gjive31QCU5YlziEGtjA+J+awGmhmszDAiBDaVKQ1KbQWTASNPGJxPJToj3ooemy +tcy0FIPFsML0W2hhrmatbfwUIxIkGe5N4q65CznyWqedg3ouWpsr9kXoTMM+tK+792RM6KzJRpA bstA4ETO+PtXr5KdloqW9yv0KaCO6FRE/5fuv8JnWKxvcLilSMle1J5YEkk9fSvcUS/ONQ8/evV5 UPJeafvTGcqmxyj3Hjb/xoqqQZvI8vCmeRISS/H1nImBr+0oy/bJomQy8vl0bNxqA4Z6JngOwvw/ LQU+boYj+okE/v8wST0t9ejzEd+0sHnskJXobmZuiwFFjmjvNl716hyfqfoQ5twBhzWWGaO7Fy7+ SAC8QtOW46qnTPyqenJdyO4Ucuge1Nv1sxoEsZdccYtFZu++PC76RPd9XZTSIOkO06k92X8z1Osa cVtzvam4qh+sI6xFvdAnyjkzmz6tkO/Ce1sG+yE1kd4y1hzN4z0GEECjq4dUoWAMR0TNIKTBmOaj 87lEZlesGDZ5ITJ0Xow5gw3kL+U5a7iWQB922JZjwOdckeAvFQX/4zy/FkzxGCiQwP44YCrkh6nZ 5Mx1eOD9g9NXxoeIKYcBCK0BNWqClfs6Pd+sKnIKXg9FHXVqS0OhX++V56h98/Pyb3ZU00H+bhzs U4ZBwlxFLC42XYTeLUb2KGfB0m83swOl4eGmBxgYQhgW0/5DKRZns03uvuyxwCHtHg0eSw+O5ogj 5JUR18uakkki7xCgEPtqP+ZW3siIMsAJNkLntFJ7WLYkWOMfFfLAoQ7Ys+c9GPsy+oJ8FbcLuNjm F8joiul1MSXcn68jRljwhemJ0C+d1IeQSTyKbgaYJnrn641qWuIS/p19Ez2D+vmqQhopgiWAz459 nRyG+l/2Ktc8BYFjA78jQM0vsvzihLcT13ATvafeBM15i7RkWO9mB2EgGtTgnvjerzaEyvqTv74K yxPc/0AsBNHZ9od7aZDlmPgK2qwGsQm4D1rnlIWx6ZrwCU6YnZY7okWf0VWOLyyJAU38WIP0eG0/ NxHslh0/GZjEPwqoqM/6MuB31d9NN7ZUYUFBg3JRX7vaq5hbNSxur1iLH0iGEUY03tOqwUwdHSFq p6LD7AaK+iT1Dx4qfYucpcPYAPZAl4DWTrAgORqP43x6rUHJJ7N7tnCDMiwCcci1bt3EZy5paLik cD69OFxgYbDLBgSNhpvp27MHcKvDHu0ti2ALIgqacsd+7jPYAxfkkog/KjMVnGNb3oirS7KNLIyP 87TjVTnZv5J6v8TDSWWqhazv6rOywn933rIt0upToVW5QU+PSSMjlnQuPOkLK409XEHdYzDG03fx 6oabCcu18qansSIibuDFFriZiCdScJ/pPqaNDpXVsdLHfq4ZDfvrvcZgtCAKKAbJw8U5aqfNOJ5q y/gqTrbvWR6HdDy9hqaAY6nfBXpXaHqd+KOqxXaWopvdXlJjQsx5qRIZJz2Hc0MOTDb0Lx7nW9sX 6BYodMo9EiYioo40SecBtWxnmoLW2BW9PYTVtBYRLRs2Ghfdi+4wZ1qDG0EtJODD1StLEPmo2TQH FQ9GkWAkEoUsntNPFIH4ySO35X7sKCLocq0eUW1FqcMUInNUUPHXUJa5ePwBlZ61uPg4qq9gQXGu YDPHU4EOLnCDyxoF0+zse4FkMapd5jLbP4YYUzs1cObrvJ21QtMFEIuBEGSU9p4bFicKoX/Gajhe Lblh4RZ4Cdb3jEKkm++7WSwcjo5cTX/sxRXFC42vC9HXveWuhy2qcVUPo1pkpEg7JYLo0QKtL7Ar t6IYxOa7RPjalA7JG5PYAoXSqdG0Zpzsn3MKAUJXP1UaJF0GyjIF8HVBKddBDqS/24owcS5kNCiH 9h6DL4dQG66JZ7AwzLJZ2Xs9JGu2EGL9ADFOKpPt43vIJX1tDvUY/01MtBp8nOVHkbWjGFPgv1pS ++51AJePe9Q+mHw42RigXt0dXPRRcWiK4MhGmTMHAq6AQ4chk/1SeU5tK0Jx69OINYimmlCfhDHB iuP2pQmH2cWrLT2LFK4knk4AijVJ/7pJVzSH7sCldbpv5Y6F90dQPAlC6YahI3r9v22VVIymBib0 15H3G0yINeoFNeCwpEYZNccjgtNz4qze+jHoHyZva6LgtG/7w/A0l8N9Rw0wipmktwLuajjrlqDh tIkEPTbMmk7+FrPHkzEDMDsOdjz1keOGKE4ByHNgY29GKuz51LOJZZ2CbfZDf+ZfRdrWuCZ6YRQD trqVjmhUiVH8JRpUgxhIMdJgIofM/DZJ/4Ce5Q15t0XXtMg+tl/t3lTqg/os3D9JTyW9IDrAF11l AD1m7KuF2sggTTe+mbekMOpQnSacgyblCoh/gxMuZQSPPMg27LmlExS9VGUCcPsq/5O25PAxyeZs WGfGtNumHyzoO8I2Qwm7fedIrv3C935zm2nO9AG0hj91oR1PiKXosYks5t5QDeb5VQtzkbYqicMh pzxhEqElaOfKzwYDb3RTSmYjIXR6hJy1/Q2ykVfh7CrxMkbK9ClnvE/JfRkJprhzjngNm0pweCAt 2mx5hTiiXZOw+ukbwvwQTqFIpNgWCJUmTMnMYLY1vdhF2LDbGa7c2B/l6yKdKgiV/LlgQRohPQxr N9RMN/0PhV6FDaPPVfAMrvx5oQ877uCyBEM2vJBfCpRYGbT5fwdA8V6mo+GSU8fVav4p2fbNrzZf 4dSTrEMq23zmd8x2rd1rv6H960YjRgctUjwMkG4AeDMua12I9Mea9uF2J2Kw857H9NFK1scbs+zX k1K6eG2T2CRiR0aPZYpobRO4JBt+kRB10yCetpSDQKJ7X0CxMgbu96p/mLWT0fzReRoGU3tcYTaU ofQcZJyGajmsg/itfHtR8gyeZ+pWhlRQoUxaVv/OZgpF3DDFT0/S0Z6/osF1hgymnH/sY5kw6Wfd nOrOR5G+gh8zIAui33kSWZBzmJoXXorjkRG7DysofJRW74QUmGJUWF1SFautoQTEHWuLKpzO32xL Y/mTFglhpbFB3f8QS8xhsl4B94uU3XYMgbzgkPVhHj5XOTBeJp3YA+nt/44qhuS2WcYk3AMXwq7B nupuFFEa8Mf2Fn6m3KJKDzFr1qre4vmMeAEn9bjPnBggd3rlgEbwO8LGyNVHciV4jbtJ4fxbEOXv Nk9Gv0avpt3v3ZfszE8hQV4lYM+5jRlvvFamBKUnka+VTdHqWuQK9NZuCeN+HoOCh9MRAWYkKrO8 D5f3PfkFnhx6E7LVrg8AQeKi6gc4IIlZByPQhpw5phj1XDdwETrPY/IcXPAOCHZxK47mg/T8IqoY 5b034tgDlHQHLar2v70/vastBwhroyWYReXM86eOp22aFjUqlkF2b/DD4SE3xOi349V/swW1JIEa LEf1cr+DNmxT3yg7CiYfT788pe5HaWG4+tznBNOcUbl+CLjCEFXdP4UN8aBBTcVb+q7s0V5/Qrkb rbM7hqUDlblWWj8AprR4Jfi6DPoalDbabB6yNb2QG/4bvjNUBWDUtjdxWl1cVd1J8GG4ItYrdA19 M2B2Lkf19ouv4J5D8FHPYkchoXdErVKOwuirNwzX0JSewTXyvBbkYLgImFsmpJKMevJY4VYwW25t KsWthsONph4M++Vmo2+ydiwh8GNWsarfOTHpku7VvTthnLOin006rhk/95OKF1oU42Sjlsv2ST+A 4Z4wzxdGDvPE7R2jzf8Mquy4WxGsaJKXPrbaMO/91DJzlgkTe1MMfONlmVv2f/EfMxxJ3rAC0Axv YNJqaBZqV5X6VuYj5oevE1hHS7pI2RlO1s+UA12LltHZ/qatlxqGbYbta6+olbp/I0R7bkyNoG79 Wc3lH1a+1z0Lpqfvosv1jKCSKfuY+ZkgM8NeHzOfZ0NS7ydNijmxaGG14cHkWbzQKOkwMZfqMmcr 6uMsxSfyEl4HXASx9x4Y77gQE1Sx+wlL1IwYcvi46l2FOO70WjXvhH97CQr1X6aV1PsWkIbvm7dt zbqhQDaYGbrTzxxvqfl2826Zd4ctAIPO1dJBEpkmCvOxE/jJnIFkoRpqkqybfs/rRtEF6GW2q7pc +Ti5pyC7n8OhHC9Aat2aE7jUJZpNODM6zNtU7EvkeomNBXRUEeNv1LflQMxp0r4U/fT6ty2k9QRo 0PvmsuOE5kuzacrMu7h4agOH7lspT2zO/L1E7TZWtSz7HRSOitKLTY3tCbMjn7MgxUFPdpPt1PmU VqB3R66IO5VnatPPLg7fD/ynemzfgvG0/TPntamAW+xaEjX8Qu2+ntWiwdts/dcwEcYqzTUJ93ix dOHZdlYP1220MmbYovb4Ol5PxneNFNQz1/d1rU8zNg1f2Rx0jKzJ28ux0T3Ieghtex3EGkvLtVh1 vLWsyVMymelmwOAmsbyxgZ7vLj7n+uqcdOqELKXWt874Zxg8YNh3wlZA7p/MgINJ1CI9fT6DpZjn V3YKsxPpsepYwLsbMmoP5ko6tadbYwT6FR9AJJA9KUWwkx40uS+4qap464vM1nkN7AxroLAH6/ln fR6PoYYzKxo6/lK3R8NwA/CwHJIkYpcfhfnWPGpp83OXfER64xVAuGmXxlNQeLgKFScTmV9vIj0/ aXTUk3jUY2VNK5hUrFGvXPhN6HBHxNouzU04fXGKyJQlLCt/RqwtzeuBXVm1B7Wwas/i8kT56Wwn aAF/inIdgQvCeT9XTLKQ4IQYetk1hPhPcUFiiUZAzk2iy/IQLNtgCd6RWiAnGaLqiwRhUuRKQpQ/ liFExfwfwP/xzmw85UMe9ohqlnH49fHcj+eEo++4bvJpH1CFZ4rwKmesLZpA22QIfkeYuWRBsKR8 /U5yBfbeGUfoqn7DrUcMuV6aQq6BlfW9U5YD04P/NJ/5nwC4K9QIJzkS/h4aej2SlWVdK1zdipZX kfL4JgJIB4kPjXnzNXR7CVFIJPSU3DlHUDxg3CSqp6MMemeP1nmUYknqly1lm0UAX+za6Mn045Mx VlsSymoTdCqTyz/PLBbRaZyMVreP4u1dAqHwwCuORM/ADRCev0WuEKf716ezRMdDLX9S9fTqGVSU AFr5HpgYnlSDpKLh3Q81uTPl5GSxz4wMwT1kBeiKUtSHaN81WH95JWekbp/ZYJzAiwah9EdYHIru uyieN7N81wpiJJgJYPXxL4+I3Ms89rb7JpFW/gOyxBp/i1suA3c6dw5+yiNKMa3+9FVVwjX9ZM5i Ox9Zf29uryDCK9eslWdrg/f3GjXgCuIRgxNnms/HWr7ctKMauqF4ckTXYT8OPUf52ipVgdUjYPKo ww840rTK61RS1gQU394bASUOKePrBDyg5RZNpLwz9HTPxNFEJ5Qo9V8RCjzgfiURgwtewPJrBGrm y5/50HUKxxnElpsLWHSsGni8pWRWw8Smwmox+RWm7jahKYTolxvAmsfl8uPoi6FHYqKBhrJpNN2j u5+34DYjVgsW5lRriT6kKbwpe5ZaLo83bJzOrkEik1G3lGSko6f3cPlMic3H+0UQpFK5f1kKH1dv ui+FmeQeTNAlOh13LDdrl2PfcPf88+YMJjDMyMzXXk5GVILlajwxJWdUT//um6yYp+jr2hl1TO0k E6XS2Dde0Qr6G9NGzl14npipmNEGqTi+MDRDttBfUSlXlUtFJUwUsn3/nbJT5JT9B/knee3mjuB2 gljrkzv+tYMBSSZUIK5MhtmSuKGxhwzPHfK4LrW+EgYGjzcNh9c5mDZHhVD+Odd31lIJVX0hQOQ9 pXV02PF8bqvyYWBu9b42adpKo9OVsI9buzNaFMPzvOsuvms9OkzfaUTOpa+vJ3fH4HSvggouo7PM mKHF6zN3VXht0oR1ZYQfMom1px7GQhwkl8TR4eWvdJtnL5NRFBXXj81WjeWJWeXU8oA+vPd5swi0 aHwqRxK0OmCRkLk5c6Zk0D/TTqS48RRoj+yG67QRzeVtqUNer/hrWOIYN/qm1EyLBuEPsfgLibn9 s+az+N85CLZDnEsphFEB0XmO4ijCSBJagvBX5lYpeeUaoyBscYICTusB/CRoNpHRH41XZIM8rquN PKvRsCoJdtwfRnVXdtO/ZIM3WBaZ35LcHPJrbAL1Dizt5BGkxzgq4oKwoGeqZVhuCKT1dMc8jkB0 YyTpGVEe3FHIvDoSU75DR0c9SH7r/VPh8XFDbRvadup1LiPeHeHVXtEQf/J9fslXLI+wIb4RirzS ve3d2vCvavZS4VhhfBHkspCL1uFaCOdZZyZG0fVJ8fQGx0hd2z+JmryS3Et42RPDDNTpKjsvBdg+ yI6BCUSQiN0QFX21JpDIKJ5hXOyiocUIHgvC0jsTpsPJ44XpkptLZ20TvdtaytWCgPwRPcnCtlBf CXeCCw1sRXgcIXp03LPOoFvs37vbcnLMNEqpInWSYrimqTlIH9oeIEqoAgHKBG7ZS0zqt6EP9kCH ISAEUoWJ0yuH5AYZ8m1THiaDaHfTyZDVdbF0OnmglTA34wmfJcQt5jWmAqOY2Fdvxve4PBbjh4Lm 5+aJjukGkVeYXpyq8x2wq4ljVCeLNkP33qbIrzHJQSPoDdVy8yLilhkaygvtEDbtZ84b9EVn4zQ2 S24hFVXV5Mg+nsL/byecTV1957DbCUBNlbDkv/Ru+r4FC4ukPs353RoOIvtN8RuzrOFnmoS67+FF adfNIgNoRBhpxQp54amVzR4s4twor0aO418JqlOiYfA4qdUZ43xulTTHKMH4d69C1qV0OtceVvWp 6Dpm9tu9CO1JYEjyxE9hWn1AXTWYN+h2LFeEjrsuECy3LP9fH8Uji2K3nCAoSzSTCNtDgICsainf oKkKuD0wOPlYx2cpaCQ26G74htC4zMCxK0t7BwTcLHRc+/RHYsfHAvDfY1ZGUge6m7Rn9gMQgWjZ eAJKir5x8R3uutZmxaj7zCOzaOHGmn8KLFzZIPjq48zXXGrj6F1842ddjn+bztKnoIXX09fP0aDL 8jHah/8vAtp0nEjswY2Ldbot5hC/Fy2j6PKiw0HsFxhIOdOzpfGaRkKvPqv98YlR6B0bulrCZyHP BUC5AAr3PH5QcMmBucXHLOg9LdovdNQz50RheKGbknpYBR5NIEirJxosY3uAMVB5WxSxvMlGgrZd OKIcPik2kcfaMbrpRcoppHhCaCyujyxUAKJ3egT4lqxwqX+RA4DFBQxWMz4TDHjMBlQwwhCP9UbN exHWTWCR14HUibEDRT3fVur+SQx5rsQ+P41Rx7h+SabagaZtUhOdhlvnDE4TVA1e2qYrS1RnOrXi b+5veBYQRV0eUDHdlG6iDiidiA0OCXJsedhMxjVZl2w3RLq+5CjAv7Yoz1F0NkQyfURqir1LrWU+ oczanhYU4u9lwU5Ekx3k9qD3BMZnfMPIuWN7u1wtdYlpxxgmalQIaLZ9bQxYBMxVgjpPqcoZ8u7Z /EPob52hKhTnWqLx1t9xL1IMfI+BNb16ypz8NUlYTsGxRPa10IEKFck10TEJbjqm3a2u6kdB/BtX dTbTA1KKvi1reEoJM7pzBmBgntRl/YawAcnHf6Gn8hEy/DNsg6hfkrGk7TrqTnHrT4ntc7hgkYJI wpybdgqR1y8gWiMnQMUIT8m7SHCqneMnxyze3IRN9b5HPzQyGTwbAXgUQ5qHWEVFYTOqtyxlcfiF gCuKUULrNeCxAWzBzBTLO/sUVYjqR4PWqRj8QmlwtyweDbBDqhIMce8/18XbD8C1HS4i9L5vTVwH zppztpukv0mbcwKQps9CwnR6Qt1roTFCKCZyAoZ4peKkifSczK8E8oY+eGh+gY2YAOUvUY3WmnKK xNfzTwc+en3BGH6FLt0fR6LnRgcQdjsKmuQfBd7jsYdR+y7mqDf3bnKDhtnnxdr46NcqGN90TBxo 3Jm7O6/mpF0WEP8+sxSxky/vREc2tneCln30BBuTgWiIVuBsdbVvgAvJg8yqRkTrS6Fmzjh397mZ 6BZaBgK2Iwj+GPGz2mhexLO+DQP4fwSXdJr9E+yoSl3+SE7MaAGfarD1hCbsdV1HoiiPKyCNANQT PuduIIG9sVA6XaZUszuBaEa7lzYInANKk0EQ3G0dc1Bjmyzd7MGb+MeAH/Tl0z7ECj1IelWsHP9s 8zJOUDDpXtO+wO6FQIYQYdBi5h9ETlxC5qwG59qx41QaOMGaLaPTfiZnq3xM3dL/+lPz4a6A9l+e 0G6wCAKwdAGWbHIkGEESLM8rAjsiPD6ztz7mTJzMpr3YXA/lwpz0i3hOQyLSRxRIoS7irGlHLhOs perA3d8lOoKGFeA8RAYrf0WD3XX8Bv006eTDqgYUUP79i+Wnd9D4U4aZEcjF3eK4Hqai6pajzMp6 90P34TtP5afcs5LC6Bc3u1EDZ+mD+l1PRWwpnp5IjiZQ3VHhEbuWMglW2WD+HGyLm3m1ksWCZcRl ME4CatHz5MjAp3RvLve+5G2EpsGZTWvFR+TNWjJy+xqO4Ix4NsQ+d8KSePKlinMNJr5eRtqG/BO1 5nXn6SlHHeB6cSZcdWsUkwEMPbtzVNW5UdbtQq/0OB1ZDRAWPacMMfNW4E4xqCfiKx8vFra4rVeV Gxb+mava7/a1W/xtqbPBwYfabhOdwKDtL2pjMO2oukUaiKo2EaRfev68wQSfICO4p0n7uNapp/rW g5rx08pJNMzrpwn1nN9WZDxZWeh3h3WWgeFrZUMfA++xpxJwJBFiR9u+UbGMyltlgOp/X0J8hJWF 3q3mP4FytPXI2klMYu6IYOv2W3eq0Gs8Zb93MWQBqxLlMGLtvVZr/N4PLXghtoWkDCrTnxjy3DHP mLBplk8D0Y3xkLQcsNimrfdiPMQsbk76tf3csegbfPc8nu6zw2Q2htrVPDIRczJffeDsbA/mydIe 1Pk5N92npW2zctyHwFkPcd9YVKuI+YMcOGF6SszqpE6AXPLlIrbpIPZAx47b+54+dW3CaLYpq+C6 mrYxaFJhyV+lyvVZjP79pLjXp9+bZi/RcuNVKJRJB7EOwcQH/Y6ArinUB3fptwYD/t10atLMOS8J s3iQ8mke58HejszKizMSyp+NNrHN2UdfuLbIcV4PH06suaIRUvBCcI1Fr6fG/iO/w9WXQiJW0OvE lp5AyMaTFj4QH2iRiIrmI82ZP9yTRcImWYSHaR6a9Sfyq/1tn+Dc5+yhcfpQsIRLf4mtoMtOv/Hg uOZhstz45PswqDMcJkRlD4dkPcZt3iidOQYjj82TJmxTAXUt3/B/AN3bj+B4kVzWw6PNYWlEcq8H aXcwNMVBMPYu6MEyqfMKUFRVz//sOtpb9qdrUIIsGPIAiiMMpYyV1SEhtBZdxjYZE8ZmKStDrMGB 4quM0eJNxRmg4JuLcJeZZRi6EngPTpEfCqtrZlS9jaX9ru+TDXKXQ72JEsGu9fzdjiE86ufjrvcd rxNlxV/IE6z32+r06lQfZLK22oAP4n1W2xDrbqkQb3loGbJABHFEsledqH542yv4XWV4zF2HpMzN 1wvczO/OyrQKGa0F+SceKo6gGB0M3Qwo/RctoSqgzBGrxKDc/soSYPnu1WZxSPfpi4oHmz16dLmD 8NzYp4zqEb4IJu+LWCYe1AfJHeEh5F/10/srHLuekdhVFbaq0FzY7ehVmcF7YoTKQo6l/muFjpdd AVfKJ3wAeVeMTlYTxO4M6/A46mWiQyyenMNdoX5kwXdRogUfrbRayfStgp6/OevDq1b8CDiJ1sU/ mKnWP3PPBz1eAZJxLzu1k33Qlu6FcZ6+I2yIgRFltORRj0NBbMr9jaCwiSNpb6vtRhYA1O54OYpF SEYtCjAWY4obbKY1CdlNtXlPzTr9+ps1d9U1xdTEzhTPJC2CWelduw3TAVN1ScNpmpFrda/nyXii VmlGd5mPB9suzfhSNYC5HLCWX+mB4S/CBfuG5kmYudGzGzaEUlDKoY+UcFjaglv5ruxVr6J37UHK C+J5rKxRByT8kWld95YPZrT3c4vWgGZcyQCy3XdrFyrzb218azXCkHo2txg7R0rZM8v793xGlLtP jVyluEPNV77qL1T3e/2uAZffxoMdOmHajmULn+rkXWAXLRY4DFtvb4GTb1WqCK51AQWkU9el2sen q8+KaeIgm0B5V3Mv+xazWjhIaGxh1vuojG5+1Hf5beCyI0fnEBgrTISogfWEYLAvRrTwDpehqxF4 hdxCpi4Vk7cfrOLW6+b2qas9r3l2a7eXZIt9onVAMYntevUITb9+wtP1YaAONDBC+Fa9g4LCdm2e xePVmpOypX5EUM95IGjzCF1OOEYRxdKqDGYNpSZj7t5YAO/J42Rxolup29PbiTyrdWfo7+eaTr5j 38KggbBtxCemCkl/0UMyM8oFJRdrcvp+EWejPONi8KF2Ix7zbrShV9Wv4uSOUv4bY5ixTMLCBkeu 90oveSXNzzX9y2od/UGxWdk4e6DTNke6XRuQWnmL8lj9qlyUbZ9KxHZjMpcWaEH85sJQv8KZOufh EHLT71um6SFn0uBSR7C7J3w3rXb0ZV7E0136QfqrLA2L6qnsoXPN0PkA0PDLl7qggoTC00Cceqet UxixOYqtum/CjMtC3IwDveIev09qijq4OU8IKQwbdi0PvQYLRLK8nLndTPGgae9Oq1u9yJLFz816 fezX+6AhNTw7P9OMwwHjTHrxYmQxND9sYBsxrX/RFU+0wO/nHR1jWdrFVQIYW4k1sIDWEPEoDI81 PgDVLoQ9E+AD3t9fggPEcy02ZOkXBPpmzTHOV3vggX96+uSuq5yBH5uyhnyFmr+803pFbq3BYXnH 6zN/6myXsy0OyRsiuSzeRj/OZZGwaEuPgz34DfvwT9ZVMdsYwn+bTc/20St0t8/987g4k//grRtr gP0/M1bptIbM2shk5ysoJLeEV41jBklJr/2l8DArmJ3cinSxU0bfEi13IPDt5rfnHoEGPBn6R5rj A0iP5luJmGYgZWXGLecFjNMJsOtbpEqhUVm6uWd61VXiZGeuCd5OdjulxN63AJ2VmxU3I6PCpqpQ ZzfRC2Cn++TkCRJmGAi8oAXwrv6HBqrHNY4RQErLxzn2IUD+Row7XvDHvKWaPYZ1T6r7Bokncg3o LUHuln8OWy6z+9bqka+oTJgrBYDqiKr1Y0PZsk5XCJwctf8ZmgGZd/GfZBw8VVfKN+vyRAAk4J8j HJ5yO0h00jV/IV0Kxci5yUQDokJronIwMeImu+SogYY2nnh/N1AGFEhf2fP+ZZAb6r+hpGBnnD6S ac1qBGuhHY2mzk15RCn0J9bD+2cR9w2q5DLK6JvR4DpJiVUlMBufoBqBpV2TGwvNSWScw5Y2PZTm 1Iyqx1vSe42n2Zuvh/c82pk/qhtRD3jLkvfRTIFpFsgZJikqSewWTqsN9WHZrcyzaFuuv3pC72do BTdCLBl7ksiH/kOXc9pPl6dfOy9r0kdqEbrLlxIK73LqMl/totbRkKDyp5KSBRCSmjHArTkR3P2V UMSHnJOsBIVbf7b2fzFSBqcTynSJTsO/jMvoSX8L8mXy1gvV8LjGbPINnb566cE7ctwudwC3WZRL rOgR4382wwKBMpigTwvwkBQk0ypN4xIWpld+ndl8KBnN8tKa3/kq7RcLFJXiyhmAdlWQ6GBEv9tk Z+uA+znPGFVp9hmnuR79LkkOg54gl61HjaqQ3DuM3AL1WsOrL8feSXqZHZViKLvgGStg+liPdvsU 1tc0XtWH62A9Bq1qWiJ3l52Q92KfdmdkUVsv/IYAREoWhtXkV4dytdb0eoaNdqWExr33xazv3UUF e6GL5HuDliyRmcOrT1c7t+S3Krg0coEfgU1CRMw7ZXsFgEwCO1E7bgC+hllS7nUfGJGtXgoHqJAs uw+KfMLe0DCfbCT2XGU0H1UteQ0KrEAp/cd5Dp/qbwETS6z6qsae6j8wbd6tOVzE5Z9XSrqfenIB 50EB5xCxLTV/1ji9UNJIELcfS9SUdCQH35wSwV+WrfS/YgAlVOhmj4+M8o5MGHit+/5PfSE30GLS kftN1BH4F6yvlgy29B/fFecgb1eW4qdsiuoD4oX4y1YvrjfZqxf8bCAO2lcY44CsJz8YjQojv213 4qq5IAa4Dp5UKQwEIrZYKrNu8MNWUD+0O0JjgespSt66v3H5fNyNqiiwT5zeeer3j0rXLNzemWYk RZTYroWgQM2BgSGYfA0xwSDecH3wkCZcwpUKW4tFDGI6egSgQFvmfLfBpdng9AhmWZ+Lh7FNNsfo OutrbqkCX4FdPsy79XR0+oZVGSZviqaUJN0FFe4PZz+DiSy8fiaOKZ69B0h1+ACKx6e4at5rKMS0 PvaNcUZ0FOvZVP/cjWxxzVF2gweH8BglmfktVZSL3Alz+Aia0suhCJjP1aqDbpLzVhJA+ZPMZKVm tGYNwNECRog8XMRMRMIuueMlMPDt6nczAlUSJPY+Rkz2p94MAD6MSOsVVLsrqHYRmIvzps9uP5ed bkIur57uYOU++62nQlmqfGNo+KDIcZ3xvy4z64yRHW7bbySUhS8HdcvoRk8wb4iRo/C7NsVVp/fe 5dHOawhhsIxVm246QkxRfvQ1oiu6Y7rRIhsWGVYCCJ6TSc+wmefCvqMTQjBjxE8OsnWphedGgZx7 duvX6HYFTeaVtlTtZe7qGgwNO7NSguD2dCA+epBq7eBvvOT+/jxg9DjbcrZfBq6I2uBut7am30dV b3Rkm09jesGqARwNn8VKnDz5mkq7/GgxwTmw1T46MaX1w54X/76MneZzukSUaXX4CrMAuXAtMueH Ba1Qx6BFhcfzE7g0f9LewZdL7hyAe4LSqNT32p7O13Gz1TGjcKYP2mccjHJFnHM4NxGE7ZoY8PDL vpAmOc/9QnP8onCjqUKY/kkdwTxV5bpv3SHxnvftfKtZm3vIUMyThxJhefpHZfJ9odlAidTji9iP 7PuKNM/A+/zKufUlpNx/E9RKAhIq4lpULdmIbcJx1WGacSg3Xt/q8SPDxxp9LpResF7g7yZ6dvio eGiK2RXuLD+YhITpbOA+hcpjwNZFrh0fQc7U/9ijVr+CDTB76mcfYIivGwKFc4mzT+PEB3MZqD0o 5gS3TPdvSkXq5fCnT86XOc2S+CFwI9ulZDAkOX76QjOVI6NBp053+3zkZXGGkPQXgtmSBRLbOPPu XD9/MAGlncxBHX2+phXqZJiTBM1vFfGds+AM4v/n+TvQEgPKruDNRScypzSMe101luiKKGOWeYW2 MtxoreLtN/BKqGYC0PCL2OzFPdG01UYUX+QxMgxDogXE9X39npHq5Tc2k4KeZ6ghzTH2irptBZ8D 7UhcRnxHbTDp8ApPamMvUXjQBdgLcbfR/g8bqkPMd+EbdzHs+WwYxz91KFDIOhTKkB1n1I8osYmd NyJdBXUn4957DKhMfEnisgocuNg2DcSsFTr9FSnhQxMP0/5YJgPx+igAVIjQaUz4js27FFtPS9F7 XXOo02MwhRiutlSsJSczoTIO9WaOUlD4kXScdvVtcTIc8Fq3L3O1HQK82gVVLbYTJsQdllvZyOs0 lC5jM7CCf9hrBsgXPUYBhWC3LNJ7PU7NpCb0t0McRFVqYwulJXn1gR4z0Ry+ahTLP6J/xDW5WlJw wLX4sQQ697Bqr5ab3J+GldU57m9QXaZIU1pD9X/7RksTLg94Cfs/06zWw9SNps3sQvMK6ePR+N4E 1J60hp7bHyzFP+Y1pIWORl8LkT+ixs1tXF37J6cKxhewklgnZ0MMHylG5nlexLhiF3chL827FNIg D+rH9QyeoFyO0RFakmTS1V/P3rM8ULlMSIT8El07CJ24TFYxlvp/OF8i3yExDU+cfA42rGY68Itb dcugluX2SkrMsNwRqtp9dMXBrVgtQ2Qcr9cKfNCIIl0KfAXWveWAiL+4NTt9ibUqRxnLy03F4qVu gCyudq/EclAi7JgZn3B8n9YRiEvURVqNMPjump8EuPQnQgCUc78jx11KIFrzdnNch2HxdJ0u41gK K+xAEaK+CVSBaNs32q2dHzzY0jtfFr5GvpmLgSIPRRI91r8pZXuob+t3kmxGE6zphDlgcWuuRn89 qGs5wss+A0hR+/SiWIckgX/KNQvNGmcQzLuu0DaaVwJlWueMZH0WqGXwvkxUMnX400gQvLQT2740 wfwP0UMldDqHkkuA4LLurGnjWNKeCaMVLDF9wbp1C4c= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block f6Oty/eDcaGLsYq7HUHaI50CR3KddeKCWngOPrYzxgssq5w1cJHPpguHxHGFdy9EIfCRoyTbcbsJ kzGkvWDMfw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block a03BS+f/GVrEwcrmiDY3uOfCIEA9kNUce+93LLKYgIl26Gpdil8/WWz92OplHD1bpM3jrixYXHbd BnEHPXgKM31RhVzuk/5zfTmy3nsu+VOf0JvjM2HHeNZ+jgbmWrZzt8xEvN100yexT3qCgLH3sVTa mOE4p/RZ+r3F8M7OokI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block nbUiSMAPmx4Uta8/yPjtP7MHRMUGv9u7CIISzhQDrv/X8gHcnpa6/8ubhCkNOCj54n3b7Bn8UxBw +F7p1GRc4oCPtwT5LTsoeOsukmuqS930j2k768KDUIqcoGPiZzBIaNulEraYDQiC2kt+eRpRPxMo JQRN1ZPr9DnZM5uZxeQoQxd959BvgqoC7gQakDUcu/tLh4AGSNRqM19H0DdzEj8/k3/9oepcPo0I DJ54cZYsEJmPZHTsPMmu0U8sU+8XKnOZkHerSO3cg6Ic2LKtKM23HBft8jb6t5JpiqGR4UTN9aAV zrcmnFt8zpphWudQkN7uqB2eI0Is7l/qdNe4Xw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block qvcDy9pMQR5dFHlKRINwzCU6wJ4e6PQXbV8+MnmLuLNhgau1fKZnkFgiRwpyf0UnKN1PEd+ix0Wc qmHHsPasKZF45LKqdY5LDM9mD1dWGBmaXOk6fsImJSTvf/EHa6SN6Cdzv2VDXj1RTDAt0Nhgm7VD vceZGP0d8idcHL1sHo4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ORJv3ey9G0h5DSRenT9jsgEdHTJUq1G3USaqvu86Um6q7L7Peke8GnAN5JYozuD9HwaZjtRqcq/R VtP0h+69M8H9yD5YTEYdsXkqq0RUXuS655hwWJ/uekzsap8YiIJRh6d/s+hDPz9jUHvu3GfIlNIA mg0YXQw2enlThFsTR2ezx9Rp1MZYGrkGUy/r3GbnT7gmSNFl7X3Q7VV2Sa2uwghsGojzMo0lHUqN 4LN2HwSfUrpvJ1/w8mLBRdNyHtTBXcqqbbbU/Yjq0lilXdnIMLuM4UwG1F3EANSbK0hmYN6o0gOI EQZrLP80jOpIgS5jgO4vLdGh8aOLHOe6FIfyIg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13712) `protect data_block znQjYNS3aAdNPe8VyLh/OvkxAa8F8tNwXWMv2jEuZYf/kECndfl7uAdCIVtS8KSCA/mTIYh0PWoT TT7LvrdwX17Y/QvQJRFTXMYG4z8h4AqkVV1AictktC4kUiSGF1ELVXwcXZ1gWLTzFmZLt+kwq3gy laAcwTsO7uv46nLVLBJN4N7BxfXKy/8K6rKEJc1FzUIYw6Kia+8NCgAucD37QawSUhfLNuUpm4wm aE7jobK7b1LzZjkEVsZrxGB/uj1q45YiTSzQM4VgSDE+zxESxqGLle7Oa1Flxvewe5GGMmmAqksa cA2VfNDLkZpK28SyvBMBU//y0+kn0g/NKmNESV0QDeJRc/GJffeVFUzL6/xwTb+bmO7xvG+iqEtf 1sEke/Ugx4+Yy6FV2szBiVXO9ByCVe+Yej1pFF+lT5TTUTNWe57BqXgzQNUTQSKCDMuMjiZ5BMfL 6VUZGPol3I1KHHDjlLyyQkubSb1UPykHiM4phhsINxAYnfWiZgvlNgY8lGK6ADCDlK7jSLihM1la Ghw6qOiVLGRA5QutLi3lzC5291eD2/ViUxeYVRpE+6L6TzPqgGsbXftqGChTL1uwEMXYoOHit4Oo JJgkoihyDdU9y0CCtWrTOBOVjrFhHTBu7c+01KsjWYMpi7MsKAySJpaz66sXgkP0s7uaKLNOOh6x /C0QY/Lyo+D237FXTI7hsD+6t3dFrql66vbuDoDGlUXCgroQ/dmR2t7iA7xztvQzka/W93S3j6bB sh5n/DMKWbC5e+lJbER9cULgXQOQV2o+7EvBFoNOFsFApdx0o6/COMeeb6j1aqfrTz3ZsU81XpJX tXrTVD1q+vyX55hw6jbjok+5usKji53//6Fqhaa3z8YeKUw7sMUDuPFsGboAdiXzoPpz+NKHPrwq P5tEKsgeb+/x4T9CWph4tDEUdBIrf/uGWu5GegJHveUu+flp47T3S1Kh7+VWotMTlokkmUFvyfcs 4n0AlyLaenFpsnVmztkyg4k50tp7YqjLLqLxWLTEe60nwn91DV8Y4mPeCfFE+9FRbt9c4zIHY5zR gpnWRQOBGokcP+yqQ9Fh4OPQbkb7JCIpAgaZL6TS3wMUJFHrdMlXKlNIqVbHw10KGVhhEUdD3QR2 Z8EfGIa8lOxSa9Vew3SrSSAyHbUcZe/HDuwJB0BHsVowcFyygyFrRWyCfknF5RY2lbQKwif6/+BS lDveW+vfy3BmbtI4ne7U73xC7avRA9oaXrhohC52o6U/vTAeB3+zxjdbuni1Vg83tSs/JgYm7gE0 sM3rUT7bvcEnTHRVwDtGhxezl7KGjGdMmGVUMJ2Yu/qruvXjK5iDOI421YzYw7EsP15or01f+2F7 l0eOMdcTKi3DIV+9wFn6ekq01/mfFh59XLsnomMkMNQEmVzXVXHYdh7nsiDEbIY6ZLHoffD+bBia bxpRRL8jCS2Zo72/1Y4v1NYjMSNOe/2jpOTCl021mOqlCxZW2/HJdJtL0yO9FpaM5bJkEaarqu7t F12UZ6SakGAAiD7HKU+bx40v+xnnvJWnWpSB9TZaDVVFaQcJFtZQTw5VY6rhhkKKwgddoYcAkwuO GKdthNz74UOmYbbUChnMCALA1UM/UZWbbcMdL7JjtVqrarIDG7sepxLsFktW4MBcxpteHsXQAg7F uEYr+uqlFqlavedFnQy5Dj/Py1UO9GHV1YNWRI6LBjqLShPMSRTgFhzmQmWjgF8DQBeb5MerX+4X KWc9dsn6MbRfYHnZmz2k5tHiF5D76juILuQfATDtax0vV01k0XXNTNQHDL1lX7mhtGBuUFleimQs q8pSFGvQO7U0KkNsTIA6/PyD/MAA1V45uXTb7oNFE6yR4oyAPhGjv5BGfFAkx5yFgacIT2PtVrZV OW6DJhULGuI0Tp6HynOSOWAUCUrep5GUv9vaaCHSHVsOyCxBk3pbEjeCuf6C1fX+/4OmGqQEJHAw D3/IfE5cOu5+o3w6qzL345zmHLdL+J5oYMkEHZm5nFHkT+UZrJPhbCUbUR4xxm9H1G0ppmm9NAan JiBodA5WYe07u13suOnaQntQg3ixYoJ1IjD2QX4t3z3Sz0/gmLei/fItXNzoPyYCcYl+n3WEASIf ZEScE6mgg2agK07RvCIgOMrRUDUigL8idhk4HcO5b2J4YUcDVrJwNUpfyzVXjFiModBvqyU6q2kl bclFPHL2Mkju3v6yLN1l0H6Sl+UIbLjpAIQAsqmQuICtCXtroM8MpFKULNtygQbimnI3NCV/iDEp kQ5XqoxNrnsVjp3++Smg13E2KDz4hnyV1QNImGgaZSKbhwBYcvQp2SD767ox0+fdyE3qRzN3hcBa 3PkixlX8YRJZNxJEu6u73hN/YSOATbxSHzFJppkTcFZHx+dQmoKCZjgDzxWSPIIQXEou4PI3JOgE POK9R6aLQdswBxzSy1MSNKj0nICQtE8X0zcdRpj+a4UqNW3ltbTwNP3bIGClDmdACETloct7U0Bk y7Ya2Cld1tVRLwK/Ldrg2fKIag17zcRXNjMXwICe+f57scMzEvGY9tTS9WApy7mWJEP2wWeodicb do+x7tyAVTBdrW+WKrlctmmKuZkA67JhoCFcC/IGI43UBcQkWipWxjc10YVDNOwCnhN+shANeGts 8NfBp3nEzuKlMNL3HD/QOmk5OTSfWmH4/GQ/T55hAm0gH2Fvvli99Btjx7+MhuBlA3kPL7ANxGgC barLIrYT+L4Zl+exStAXPFM2uZbJtdD++wWk2eB5mJOo8OZ9k6NHfMKt6hdRlq4PD5WQ/xCLWXht 4+2i8TAbGlb9X0KxsltfOM8G6KDJ2zZOhORRD4iJlqmfvon1mRQiKDTiOFiDSaaoFuXSoIALKW9h S0onMtnhjoOOLD8oQDpL1RBsAK1hSYgyhTu7lBZ//4XWRcdG/pHXLpNgN3HUYU4FH1ZQ++KWIRLH wXcIEBUD3lXeGicAGTTxnNuzvkHqnj62Ejt1yP0U2hVvOS5bPbkwJkDH+6ldkmNI1XSDqsD1PC6y UfBOrj4M12PQGwiC0SnxcfN0x6dQEslVniYgTq0VMRUf9xwX0Ze/M94ReKliPO4nM9JW9FdJr2u4 iKpUONXDP3uiCLTWe5G4Ph66tk45wtm+WOt2x9qpUOM5YSEGkYlcgIjRd4Qljhesaumd4RySr7oC k2VoMm0lN9ESqFGPTh2F7polporSK5Jezi+Kqyp9V9j8HesZn32nd5INBGc4fchCDGyz30LNZF6B iI49rLloBgvWjsoi4FKuPNhoG7GVWobHuGJ9WI3ojHr16EE7xKyaekeF7jx+5mP4840sEgnv8KuU G9ESEjcsLbKkAPXY4pXvSexegmwblRaECLnNXfRu93LrRMLuUGuRZizrAZQVO4eEZVkMelXIzRdN TQxO20IRBToKqWkQPsFgrhs7B9G4bCslYq+5rZkeaGRv2+zox3TYFCeJc1crQ421y3alTA/IaHB3 Exdr2NSeE0AC3QfB81TiyIerrLoLpwNngHVfPbXgq/CylG45va8b5uBMqWGuyhq/6dm3rb0fOOO4 CQX8PLtQuIpqLwmlQ6gOo921qqPuPmuULfYJST/e3lyZsr9C7/jqMBIJ6w15z2h/b9VV9NSiwavb V4uWLJPuyo59xWCyuMGoCXMp3gx1Rzp0kgTkQCvr5HLoLE75qimfol582BmmxvrEp9ExUfNcX9Lo eOkZtG5msxxoQK5Foyt+QObz5nHCOlaH/pzUmKaC6KgX8qzyUcdd1qOhRDtbm+ayKgKnMViWPR1h GTl0rG8r/+5hwa4Q3Yh5+6Q2je9T873L7twjyN7RXppH2I6y1GJvijRYXpkEAuNxMB5dfXqTQkiu qlw+qeuqkBz+d38h3mC00ai1MZMwU83+xrJYsfLbUv09JZ9pfvk1CfrgS7i6BCAueuO1/YygQB1f 4LnLqeK0Bzu/QhkMy7xNSucVRg1a9FXGLSmodfc6sY/IWLvwNQTC2WAXf+7a2hgeRvP+eC0tj13o yD1GMOkWcdGLd58I3HKyzN3xFFK6nHVnAbCmB4DRKSbtGvdO5wSVea2nEMrBLPsM/+ezL+A5aFH7 ngSMn5aiLfo9Gjive31QCU5YlziEGtjA+J+awGmhmszDAiBDaVKQ1KbQWTASNPGJxPJToj3ooemy +tcy0FIPFsML0W2hhrmatbfwUIxIkGe5N4q65CznyWqedg3ouWpsr9kXoTMM+tK+792RM6KzJRpA bstA4ETO+PtXr5KdloqW9yv0KaCO6FRE/5fuv8JnWKxvcLilSMle1J5YEkk9fSvcUS/ONQ8/evV5 UPJeafvTGcqmxyj3Hjb/xoqqQZvI8vCmeRISS/H1nImBr+0oy/bJomQy8vl0bNxqA4Z6JngOwvw/ LQU+boYj+okE/v8wST0t9ejzEd+0sHnskJXobmZuiwFFjmjvNl716hyfqfoQ5twBhzWWGaO7Fy7+ SAC8QtOW46qnTPyqenJdyO4Ucuge1Nv1sxoEsZdccYtFZu++PC76RPd9XZTSIOkO06k92X8z1Osa cVtzvam4qh+sI6xFvdAnyjkzmz6tkO/Ce1sG+yE1kd4y1hzN4z0GEECjq4dUoWAMR0TNIKTBmOaj 87lEZlesGDZ5ITJ0Xow5gw3kL+U5a7iWQB922JZjwOdckeAvFQX/4zy/FkzxGCiQwP44YCrkh6nZ 5Mx1eOD9g9NXxoeIKYcBCK0BNWqClfs6Pd+sKnIKXg9FHXVqS0OhX++V56h98/Pyb3ZU00H+bhzs U4ZBwlxFLC42XYTeLUb2KGfB0m83swOl4eGmBxgYQhgW0/5DKRZns03uvuyxwCHtHg0eSw+O5ogj 5JUR18uakkki7xCgEPtqP+ZW3siIMsAJNkLntFJ7WLYkWOMfFfLAoQ7Ys+c9GPsy+oJ8FbcLuNjm F8joiul1MSXcn68jRljwhemJ0C+d1IeQSTyKbgaYJnrn641qWuIS/p19Ez2D+vmqQhopgiWAz459 nRyG+l/2Ktc8BYFjA78jQM0vsvzihLcT13ATvafeBM15i7RkWO9mB2EgGtTgnvjerzaEyvqTv74K yxPc/0AsBNHZ9od7aZDlmPgK2qwGsQm4D1rnlIWx6ZrwCU6YnZY7okWf0VWOLyyJAU38WIP0eG0/ NxHslh0/GZjEPwqoqM/6MuB31d9NN7ZUYUFBg3JRX7vaq5hbNSxur1iLH0iGEUY03tOqwUwdHSFq p6LD7AaK+iT1Dx4qfYucpcPYAPZAl4DWTrAgORqP43x6rUHJJ7N7tnCDMiwCcci1bt3EZy5paLik cD69OFxgYbDLBgSNhpvp27MHcKvDHu0ti2ALIgqacsd+7jPYAxfkkog/KjMVnGNb3oirS7KNLIyP 87TjVTnZv5J6v8TDSWWqhazv6rOywn933rIt0upToVW5QU+PSSMjlnQuPOkLK409XEHdYzDG03fx 6oabCcu18qansSIibuDFFriZiCdScJ/pPqaNDpXVsdLHfq4ZDfvrvcZgtCAKKAbJw8U5aqfNOJ5q y/gqTrbvWR6HdDy9hqaAY6nfBXpXaHqd+KOqxXaWopvdXlJjQsx5qRIZJz2Hc0MOTDb0Lx7nW9sX 6BYodMo9EiYioo40SecBtWxnmoLW2BW9PYTVtBYRLRs2Ghfdi+4wZ1qDG0EtJODD1StLEPmo2TQH FQ9GkWAkEoUsntNPFIH4ySO35X7sKCLocq0eUW1FqcMUInNUUPHXUJa5ePwBlZ61uPg4qq9gQXGu YDPHU4EOLnCDyxoF0+zse4FkMapd5jLbP4YYUzs1cObrvJ21QtMFEIuBEGSU9p4bFicKoX/Gajhe Lblh4RZ4Cdb3jEKkm++7WSwcjo5cTX/sxRXFC42vC9HXveWuhy2qcVUPo1pkpEg7JYLo0QKtL7Ar t6IYxOa7RPjalA7JG5PYAoXSqdG0Zpzsn3MKAUJXP1UaJF0GyjIF8HVBKddBDqS/24owcS5kNCiH 9h6DL4dQG66JZ7AwzLJZ2Xs9JGu2EGL9ADFOKpPt43vIJX1tDvUY/01MtBp8nOVHkbWjGFPgv1pS ++51AJePe9Q+mHw42RigXt0dXPRRcWiK4MhGmTMHAq6AQ4chk/1SeU5tK0Jx69OINYimmlCfhDHB iuP2pQmH2cWrLT2LFK4knk4AijVJ/7pJVzSH7sCldbpv5Y6F90dQPAlC6YahI3r9v22VVIymBib0 15H3G0yINeoFNeCwpEYZNccjgtNz4qze+jHoHyZva6LgtG/7w/A0l8N9Rw0wipmktwLuajjrlqDh tIkEPTbMmk7+FrPHkzEDMDsOdjz1keOGKE4ByHNgY29GKuz51LOJZZ2CbfZDf+ZfRdrWuCZ6YRQD trqVjmhUiVH8JRpUgxhIMdJgIofM/DZJ/4Ce5Q15t0XXtMg+tl/t3lTqg/os3D9JTyW9IDrAF11l AD1m7KuF2sggTTe+mbekMOpQnSacgyblCoh/gxMuZQSPPMg27LmlExS9VGUCcPsq/5O25PAxyeZs WGfGtNumHyzoO8I2Qwm7fedIrv3C935zm2nO9AG0hj91oR1PiKXosYks5t5QDeb5VQtzkbYqicMh pzxhEqElaOfKzwYDb3RTSmYjIXR6hJy1/Q2ykVfh7CrxMkbK9ClnvE/JfRkJprhzjngNm0pweCAt 2mx5hTiiXZOw+ukbwvwQTqFIpNgWCJUmTMnMYLY1vdhF2LDbGa7c2B/l6yKdKgiV/LlgQRohPQxr N9RMN/0PhV6FDaPPVfAMrvx5oQ877uCyBEM2vJBfCpRYGbT5fwdA8V6mo+GSU8fVav4p2fbNrzZf 4dSTrEMq23zmd8x2rd1rv6H960YjRgctUjwMkG4AeDMua12I9Mea9uF2J2Kw857H9NFK1scbs+zX k1K6eG2T2CRiR0aPZYpobRO4JBt+kRB10yCetpSDQKJ7X0CxMgbu96p/mLWT0fzReRoGU3tcYTaU ofQcZJyGajmsg/itfHtR8gyeZ+pWhlRQoUxaVv/OZgpF3DDFT0/S0Z6/osF1hgymnH/sY5kw6Wfd nOrOR5G+gh8zIAui33kSWZBzmJoXXorjkRG7DysofJRW74QUmGJUWF1SFautoQTEHWuLKpzO32xL Y/mTFglhpbFB3f8QS8xhsl4B94uU3XYMgbzgkPVhHj5XOTBeJp3YA+nt/44qhuS2WcYk3AMXwq7B nupuFFEa8Mf2Fn6m3KJKDzFr1qre4vmMeAEn9bjPnBggd3rlgEbwO8LGyNVHciV4jbtJ4fxbEOXv Nk9Gv0avpt3v3ZfszE8hQV4lYM+5jRlvvFamBKUnka+VTdHqWuQK9NZuCeN+HoOCh9MRAWYkKrO8 D5f3PfkFnhx6E7LVrg8AQeKi6gc4IIlZByPQhpw5phj1XDdwETrPY/IcXPAOCHZxK47mg/T8IqoY 5b034tgDlHQHLar2v70/vastBwhroyWYReXM86eOp22aFjUqlkF2b/DD4SE3xOi349V/swW1JIEa LEf1cr+DNmxT3yg7CiYfT788pe5HaWG4+tznBNOcUbl+CLjCEFXdP4UN8aBBTcVb+q7s0V5/Qrkb rbM7hqUDlblWWj8AprR4Jfi6DPoalDbabB6yNb2QG/4bvjNUBWDUtjdxWl1cVd1J8GG4ItYrdA19 M2B2Lkf19ouv4J5D8FHPYkchoXdErVKOwuirNwzX0JSewTXyvBbkYLgImFsmpJKMevJY4VYwW25t KsWthsONph4M++Vmo2+ydiwh8GNWsarfOTHpku7VvTthnLOin006rhk/95OKF1oU42Sjlsv2ST+A 4Z4wzxdGDvPE7R2jzf8Mquy4WxGsaJKXPrbaMO/91DJzlgkTe1MMfONlmVv2f/EfMxxJ3rAC0Axv YNJqaBZqV5X6VuYj5oevE1hHS7pI2RlO1s+UA12LltHZ/qatlxqGbYbta6+olbp/I0R7bkyNoG79 Wc3lH1a+1z0Lpqfvosv1jKCSKfuY+ZkgM8NeHzOfZ0NS7ydNijmxaGG14cHkWbzQKOkwMZfqMmcr 6uMsxSfyEl4HXASx9x4Y77gQE1Sx+wlL1IwYcvi46l2FOO70WjXvhH97CQr1X6aV1PsWkIbvm7dt zbqhQDaYGbrTzxxvqfl2826Zd4ctAIPO1dJBEpkmCvOxE/jJnIFkoRpqkqybfs/rRtEF6GW2q7pc +Ti5pyC7n8OhHC9Aat2aE7jUJZpNODM6zNtU7EvkeomNBXRUEeNv1LflQMxp0r4U/fT6ty2k9QRo 0PvmsuOE5kuzacrMu7h4agOH7lspT2zO/L1E7TZWtSz7HRSOitKLTY3tCbMjn7MgxUFPdpPt1PmU VqB3R66IO5VnatPPLg7fD/ynemzfgvG0/TPntamAW+xaEjX8Qu2+ntWiwdts/dcwEcYqzTUJ93ix dOHZdlYP1220MmbYovb4Ol5PxneNFNQz1/d1rU8zNg1f2Rx0jKzJ28ux0T3Ieghtex3EGkvLtVh1 vLWsyVMymelmwOAmsbyxgZ7vLj7n+uqcdOqELKXWt874Zxg8YNh3wlZA7p/MgINJ1CI9fT6DpZjn V3YKsxPpsepYwLsbMmoP5ko6tadbYwT6FR9AJJA9KUWwkx40uS+4qap464vM1nkN7AxroLAH6/ln fR6PoYYzKxo6/lK3R8NwA/CwHJIkYpcfhfnWPGpp83OXfER64xVAuGmXxlNQeLgKFScTmV9vIj0/ aXTUk3jUY2VNK5hUrFGvXPhN6HBHxNouzU04fXGKyJQlLCt/RqwtzeuBXVm1B7Wwas/i8kT56Wwn aAF/inIdgQvCeT9XTLKQ4IQYetk1hPhPcUFiiUZAzk2iy/IQLNtgCd6RWiAnGaLqiwRhUuRKQpQ/ liFExfwfwP/xzmw85UMe9ohqlnH49fHcj+eEo++4bvJpH1CFZ4rwKmesLZpA22QIfkeYuWRBsKR8 /U5yBfbeGUfoqn7DrUcMuV6aQq6BlfW9U5YD04P/NJ/5nwC4K9QIJzkS/h4aej2SlWVdK1zdipZX kfL4JgJIB4kPjXnzNXR7CVFIJPSU3DlHUDxg3CSqp6MMemeP1nmUYknqly1lm0UAX+za6Mn045Mx VlsSymoTdCqTyz/PLBbRaZyMVreP4u1dAqHwwCuORM/ADRCev0WuEKf716ezRMdDLX9S9fTqGVSU AFr5HpgYnlSDpKLh3Q81uTPl5GSxz4wMwT1kBeiKUtSHaN81WH95JWekbp/ZYJzAiwah9EdYHIru uyieN7N81wpiJJgJYPXxL4+I3Ms89rb7JpFW/gOyxBp/i1suA3c6dw5+yiNKMa3+9FVVwjX9ZM5i Ox9Zf29uryDCK9eslWdrg/f3GjXgCuIRgxNnms/HWr7ctKMauqF4ckTXYT8OPUf52ipVgdUjYPKo ww840rTK61RS1gQU394bASUOKePrBDyg5RZNpLwz9HTPxNFEJ5Qo9V8RCjzgfiURgwtewPJrBGrm y5/50HUKxxnElpsLWHSsGni8pWRWw8Smwmox+RWm7jahKYTolxvAmsfl8uPoi6FHYqKBhrJpNN2j u5+34DYjVgsW5lRriT6kKbwpe5ZaLo83bJzOrkEik1G3lGSko6f3cPlMic3H+0UQpFK5f1kKH1dv ui+FmeQeTNAlOh13LDdrl2PfcPf88+YMJjDMyMzXXk5GVILlajwxJWdUT//um6yYp+jr2hl1TO0k E6XS2Dde0Qr6G9NGzl14npipmNEGqTi+MDRDttBfUSlXlUtFJUwUsn3/nbJT5JT9B/knee3mjuB2 gljrkzv+tYMBSSZUIK5MhtmSuKGxhwzPHfK4LrW+EgYGjzcNh9c5mDZHhVD+Odd31lIJVX0hQOQ9 pXV02PF8bqvyYWBu9b42adpKo9OVsI9buzNaFMPzvOsuvms9OkzfaUTOpa+vJ3fH4HSvggouo7PM mKHF6zN3VXht0oR1ZYQfMom1px7GQhwkl8TR4eWvdJtnL5NRFBXXj81WjeWJWeXU8oA+vPd5swi0 aHwqRxK0OmCRkLk5c6Zk0D/TTqS48RRoj+yG67QRzeVtqUNer/hrWOIYN/qm1EyLBuEPsfgLibn9 s+az+N85CLZDnEsphFEB0XmO4ijCSBJagvBX5lYpeeUaoyBscYICTusB/CRoNpHRH41XZIM8rquN PKvRsCoJdtwfRnVXdtO/ZIM3WBaZ35LcHPJrbAL1Dizt5BGkxzgq4oKwoGeqZVhuCKT1dMc8jkB0 YyTpGVEe3FHIvDoSU75DR0c9SH7r/VPh8XFDbRvadup1LiPeHeHVXtEQf/J9fslXLI+wIb4RirzS ve3d2vCvavZS4VhhfBHkspCL1uFaCOdZZyZG0fVJ8fQGx0hd2z+JmryS3Et42RPDDNTpKjsvBdg+ yI6BCUSQiN0QFX21JpDIKJ5hXOyiocUIHgvC0jsTpsPJ44XpkptLZ20TvdtaytWCgPwRPcnCtlBf CXeCCw1sRXgcIXp03LPOoFvs37vbcnLMNEqpInWSYrimqTlIH9oeIEqoAgHKBG7ZS0zqt6EP9kCH ISAEUoWJ0yuH5AYZ8m1THiaDaHfTyZDVdbF0OnmglTA34wmfJcQt5jWmAqOY2Fdvxve4PBbjh4Lm 5+aJjukGkVeYXpyq8x2wq4ljVCeLNkP33qbIrzHJQSPoDdVy8yLilhkaygvtEDbtZ84b9EVn4zQ2 S24hFVXV5Mg+nsL/byecTV1957DbCUBNlbDkv/Ru+r4FC4ukPs353RoOIvtN8RuzrOFnmoS67+FF adfNIgNoRBhpxQp54amVzR4s4twor0aO418JqlOiYfA4qdUZ43xulTTHKMH4d69C1qV0OtceVvWp 6Dpm9tu9CO1JYEjyxE9hWn1AXTWYN+h2LFeEjrsuECy3LP9fH8Uji2K3nCAoSzSTCNtDgICsainf oKkKuD0wOPlYx2cpaCQ26G74htC4zMCxK0t7BwTcLHRc+/RHYsfHAvDfY1ZGUge6m7Rn9gMQgWjZ eAJKir5x8R3uutZmxaj7zCOzaOHGmn8KLFzZIPjq48zXXGrj6F1842ddjn+bztKnoIXX09fP0aDL 8jHah/8vAtp0nEjswY2Ldbot5hC/Fy2j6PKiw0HsFxhIOdOzpfGaRkKvPqv98YlR6B0bulrCZyHP BUC5AAr3PH5QcMmBucXHLOg9LdovdNQz50RheKGbknpYBR5NIEirJxosY3uAMVB5WxSxvMlGgrZd OKIcPik2kcfaMbrpRcoppHhCaCyujyxUAKJ3egT4lqxwqX+RA4DFBQxWMz4TDHjMBlQwwhCP9UbN exHWTWCR14HUibEDRT3fVur+SQx5rsQ+P41Rx7h+SabagaZtUhOdhlvnDE4TVA1e2qYrS1RnOrXi b+5veBYQRV0eUDHdlG6iDiidiA0OCXJsedhMxjVZl2w3RLq+5CjAv7Yoz1F0NkQyfURqir1LrWU+ oczanhYU4u9lwU5Ekx3k9qD3BMZnfMPIuWN7u1wtdYlpxxgmalQIaLZ9bQxYBMxVgjpPqcoZ8u7Z /EPob52hKhTnWqLx1t9xL1IMfI+BNb16ypz8NUlYTsGxRPa10IEKFck10TEJbjqm3a2u6kdB/BtX dTbTA1KKvi1reEoJM7pzBmBgntRl/YawAcnHf6Gn8hEy/DNsg6hfkrGk7TrqTnHrT4ntc7hgkYJI wpybdgqR1y8gWiMnQMUIT8m7SHCqneMnxyze3IRN9b5HPzQyGTwbAXgUQ5qHWEVFYTOqtyxlcfiF gCuKUULrNeCxAWzBzBTLO/sUVYjqR4PWqRj8QmlwtyweDbBDqhIMce8/18XbD8C1HS4i9L5vTVwH zppztpukv0mbcwKQps9CwnR6Qt1roTFCKCZyAoZ4peKkifSczK8E8oY+eGh+gY2YAOUvUY3WmnKK xNfzTwc+en3BGH6FLt0fR6LnRgcQdjsKmuQfBd7jsYdR+y7mqDf3bnKDhtnnxdr46NcqGN90TBxo 3Jm7O6/mpF0WEP8+sxSxky/vREc2tneCln30BBuTgWiIVuBsdbVvgAvJg8yqRkTrS6Fmzjh397mZ 6BZaBgK2Iwj+GPGz2mhexLO+DQP4fwSXdJr9E+yoSl3+SE7MaAGfarD1hCbsdV1HoiiPKyCNANQT PuduIIG9sVA6XaZUszuBaEa7lzYInANKk0EQ3G0dc1Bjmyzd7MGb+MeAH/Tl0z7ECj1IelWsHP9s 8zJOUDDpXtO+wO6FQIYQYdBi5h9ETlxC5qwG59qx41QaOMGaLaPTfiZnq3xM3dL/+lPz4a6A9l+e 0G6wCAKwdAGWbHIkGEESLM8rAjsiPD6ztz7mTJzMpr3YXA/lwpz0i3hOQyLSRxRIoS7irGlHLhOs perA3d8lOoKGFeA8RAYrf0WD3XX8Bv006eTDqgYUUP79i+Wnd9D4U4aZEcjF3eK4Hqai6pajzMp6 90P34TtP5afcs5LC6Bc3u1EDZ+mD+l1PRWwpnp5IjiZQ3VHhEbuWMglW2WD+HGyLm3m1ksWCZcRl ME4CatHz5MjAp3RvLve+5G2EpsGZTWvFR+TNWjJy+xqO4Ix4NsQ+d8KSePKlinMNJr5eRtqG/BO1 5nXn6SlHHeB6cSZcdWsUkwEMPbtzVNW5UdbtQq/0OB1ZDRAWPacMMfNW4E4xqCfiKx8vFra4rVeV Gxb+mava7/a1W/xtqbPBwYfabhOdwKDtL2pjMO2oukUaiKo2EaRfev68wQSfICO4p0n7uNapp/rW g5rx08pJNMzrpwn1nN9WZDxZWeh3h3WWgeFrZUMfA++xpxJwJBFiR9u+UbGMyltlgOp/X0J8hJWF 3q3mP4FytPXI2klMYu6IYOv2W3eq0Gs8Zb93MWQBqxLlMGLtvVZr/N4PLXghtoWkDCrTnxjy3DHP mLBplk8D0Y3xkLQcsNimrfdiPMQsbk76tf3csegbfPc8nu6zw2Q2htrVPDIRczJffeDsbA/mydIe 1Pk5N92npW2zctyHwFkPcd9YVKuI+YMcOGF6SszqpE6AXPLlIrbpIPZAx47b+54+dW3CaLYpq+C6 mrYxaFJhyV+lyvVZjP79pLjXp9+bZi/RcuNVKJRJB7EOwcQH/Y6ArinUB3fptwYD/t10atLMOS8J s3iQ8mke58HejszKizMSyp+NNrHN2UdfuLbIcV4PH06suaIRUvBCcI1Fr6fG/iO/w9WXQiJW0OvE lp5AyMaTFj4QH2iRiIrmI82ZP9yTRcImWYSHaR6a9Sfyq/1tn+Dc5+yhcfpQsIRLf4mtoMtOv/Hg uOZhstz45PswqDMcJkRlD4dkPcZt3iidOQYjj82TJmxTAXUt3/B/AN3bj+B4kVzWw6PNYWlEcq8H aXcwNMVBMPYu6MEyqfMKUFRVz//sOtpb9qdrUIIsGPIAiiMMpYyV1SEhtBZdxjYZE8ZmKStDrMGB 4quM0eJNxRmg4JuLcJeZZRi6EngPTpEfCqtrZlS9jaX9ru+TDXKXQ72JEsGu9fzdjiE86ufjrvcd rxNlxV/IE6z32+r06lQfZLK22oAP4n1W2xDrbqkQb3loGbJABHFEsledqH542yv4XWV4zF2HpMzN 1wvczO/OyrQKGa0F+SceKo6gGB0M3Qwo/RctoSqgzBGrxKDc/soSYPnu1WZxSPfpi4oHmz16dLmD 8NzYp4zqEb4IJu+LWCYe1AfJHeEh5F/10/srHLuekdhVFbaq0FzY7ehVmcF7YoTKQo6l/muFjpdd AVfKJ3wAeVeMTlYTxO4M6/A46mWiQyyenMNdoX5kwXdRogUfrbRayfStgp6/OevDq1b8CDiJ1sU/ mKnWP3PPBz1eAZJxLzu1k33Qlu6FcZ6+I2yIgRFltORRj0NBbMr9jaCwiSNpb6vtRhYA1O54OYpF SEYtCjAWY4obbKY1CdlNtXlPzTr9+ps1d9U1xdTEzhTPJC2CWelduw3TAVN1ScNpmpFrda/nyXii VmlGd5mPB9suzfhSNYC5HLCWX+mB4S/CBfuG5kmYudGzGzaEUlDKoY+UcFjaglv5ruxVr6J37UHK C+J5rKxRByT8kWld95YPZrT3c4vWgGZcyQCy3XdrFyrzb218azXCkHo2txg7R0rZM8v793xGlLtP jVyluEPNV77qL1T3e/2uAZffxoMdOmHajmULn+rkXWAXLRY4DFtvb4GTb1WqCK51AQWkU9el2sen q8+KaeIgm0B5V3Mv+xazWjhIaGxh1vuojG5+1Hf5beCyI0fnEBgrTISogfWEYLAvRrTwDpehqxF4 hdxCpi4Vk7cfrOLW6+b2qas9r3l2a7eXZIt9onVAMYntevUITb9+wtP1YaAONDBC+Fa9g4LCdm2e xePVmpOypX5EUM95IGjzCF1OOEYRxdKqDGYNpSZj7t5YAO/J42Rxolup29PbiTyrdWfo7+eaTr5j 38KggbBtxCemCkl/0UMyM8oFJRdrcvp+EWejPONi8KF2Ix7zbrShV9Wv4uSOUv4bY5ixTMLCBkeu 90oveSXNzzX9y2od/UGxWdk4e6DTNke6XRuQWnmL8lj9qlyUbZ9KxHZjMpcWaEH85sJQv8KZOufh EHLT71um6SFn0uBSR7C7J3w3rXb0ZV7E0136QfqrLA2L6qnsoXPN0PkA0PDLl7qggoTC00Cceqet UxixOYqtum/CjMtC3IwDveIev09qijq4OU8IKQwbdi0PvQYLRLK8nLndTPGgae9Oq1u9yJLFz816 fezX+6AhNTw7P9OMwwHjTHrxYmQxND9sYBsxrX/RFU+0wO/nHR1jWdrFVQIYW4k1sIDWEPEoDI81 PgDVLoQ9E+AD3t9fggPEcy02ZOkXBPpmzTHOV3vggX96+uSuq5yBH5uyhnyFmr+803pFbq3BYXnH 6zN/6myXsy0OyRsiuSzeRj/OZZGwaEuPgz34DfvwT9ZVMdsYwn+bTc/20St0t8/987g4k//grRtr gP0/M1bptIbM2shk5ysoJLeEV41jBklJr/2l8DArmJ3cinSxU0bfEi13IPDt5rfnHoEGPBn6R5rj A0iP5luJmGYgZWXGLecFjNMJsOtbpEqhUVm6uWd61VXiZGeuCd5OdjulxN63AJ2VmxU3I6PCpqpQ ZzfRC2Cn++TkCRJmGAi8oAXwrv6HBqrHNY4RQErLxzn2IUD+Row7XvDHvKWaPYZ1T6r7Bokncg3o LUHuln8OWy6z+9bqka+oTJgrBYDqiKr1Y0PZsk5XCJwctf8ZmgGZd/GfZBw8VVfKN+vyRAAk4J8j HJ5yO0h00jV/IV0Kxci5yUQDokJronIwMeImu+SogYY2nnh/N1AGFEhf2fP+ZZAb6r+hpGBnnD6S ac1qBGuhHY2mzk15RCn0J9bD+2cR9w2q5DLK6JvR4DpJiVUlMBufoBqBpV2TGwvNSWScw5Y2PZTm 1Iyqx1vSe42n2Zuvh/c82pk/qhtRD3jLkvfRTIFpFsgZJikqSewWTqsN9WHZrcyzaFuuv3pC72do BTdCLBl7ksiH/kOXc9pPl6dfOy9r0kdqEbrLlxIK73LqMl/totbRkKDyp5KSBRCSmjHArTkR3P2V UMSHnJOsBIVbf7b2fzFSBqcTynSJTsO/jMvoSX8L8mXy1gvV8LjGbPINnb566cE7ctwudwC3WZRL rOgR4382wwKBMpigTwvwkBQk0ypN4xIWpld+ndl8KBnN8tKa3/kq7RcLFJXiyhmAdlWQ6GBEv9tk Z+uA+znPGFVp9hmnuR79LkkOg54gl61HjaqQ3DuM3AL1WsOrL8feSXqZHZViKLvgGStg+liPdvsU 1tc0XtWH62A9Bq1qWiJ3l52Q92KfdmdkUVsv/IYAREoWhtXkV4dytdb0eoaNdqWExr33xazv3UUF e6GL5HuDliyRmcOrT1c7t+S3Krg0coEfgU1CRMw7ZXsFgEwCO1E7bgC+hllS7nUfGJGtXgoHqJAs uw+KfMLe0DCfbCT2XGU0H1UteQ0KrEAp/cd5Dp/qbwETS6z6qsae6j8wbd6tOVzE5Z9XSrqfenIB 50EB5xCxLTV/1ji9UNJIELcfS9SUdCQH35wSwV+WrfS/YgAlVOhmj4+M8o5MGHit+/5PfSE30GLS kftN1BH4F6yvlgy29B/fFecgb1eW4qdsiuoD4oX4y1YvrjfZqxf8bCAO2lcY44CsJz8YjQojv213 4qq5IAa4Dp5UKQwEIrZYKrNu8MNWUD+0O0JjgespSt66v3H5fNyNqiiwT5zeeer3j0rXLNzemWYk RZTYroWgQM2BgSGYfA0xwSDecH3wkCZcwpUKW4tFDGI6egSgQFvmfLfBpdng9AhmWZ+Lh7FNNsfo OutrbqkCX4FdPsy79XR0+oZVGSZviqaUJN0FFe4PZz+DiSy8fiaOKZ69B0h1+ACKx6e4at5rKMS0 PvaNcUZ0FOvZVP/cjWxxzVF2gweH8BglmfktVZSL3Alz+Aia0suhCJjP1aqDbpLzVhJA+ZPMZKVm tGYNwNECRog8XMRMRMIuueMlMPDt6nczAlUSJPY+Rkz2p94MAD6MSOsVVLsrqHYRmIvzps9uP5ed bkIur57uYOU++62nQlmqfGNo+KDIcZ3xvy4z64yRHW7bbySUhS8HdcvoRk8wb4iRo/C7NsVVp/fe 5dHOawhhsIxVm246QkxRfvQ1oiu6Y7rRIhsWGVYCCJ6TSc+wmefCvqMTQjBjxE8OsnWphedGgZx7 duvX6HYFTeaVtlTtZe7qGgwNO7NSguD2dCA+epBq7eBvvOT+/jxg9DjbcrZfBq6I2uBut7am30dV b3Rkm09jesGqARwNn8VKnDz5mkq7/GgxwTmw1T46MaX1w54X/76MneZzukSUaXX4CrMAuXAtMueH Ba1Qx6BFhcfzE7g0f9LewZdL7hyAe4LSqNT32p7O13Gz1TGjcKYP2mccjHJFnHM4NxGE7ZoY8PDL vpAmOc/9QnP8onCjqUKY/kkdwTxV5bpv3SHxnvftfKtZm3vIUMyThxJhefpHZfJ9odlAidTji9iP 7PuKNM/A+/zKufUlpNx/E9RKAhIq4lpULdmIbcJx1WGacSg3Xt/q8SPDxxp9LpResF7g7yZ6dvio eGiK2RXuLD+YhITpbOA+hcpjwNZFrh0fQc7U/9ijVr+CDTB76mcfYIivGwKFc4mzT+PEB3MZqD0o 5gS3TPdvSkXq5fCnT86XOc2S+CFwI9ulZDAkOX76QjOVI6NBp053+3zkZXGGkPQXgtmSBRLbOPPu XD9/MAGlncxBHX2+phXqZJiTBM1vFfGds+AM4v/n+TvQEgPKruDNRScypzSMe101luiKKGOWeYW2 MtxoreLtN/BKqGYC0PCL2OzFPdG01UYUX+QxMgxDogXE9X39npHq5Tc2k4KeZ6ghzTH2irptBZ8D 7UhcRnxHbTDp8ApPamMvUXjQBdgLcbfR/g8bqkPMd+EbdzHs+WwYxz91KFDIOhTKkB1n1I8osYmd NyJdBXUn4957DKhMfEnisgocuNg2DcSsFTr9FSnhQxMP0/5YJgPx+igAVIjQaUz4js27FFtPS9F7 XXOo02MwhRiutlSsJSczoTIO9WaOUlD4kXScdvVtcTIc8Fq3L3O1HQK82gVVLbYTJsQdllvZyOs0 lC5jM7CCf9hrBsgXPUYBhWC3LNJ7PU7NpCb0t0McRFVqYwulJXn1gR4z0Ry+ahTLP6J/xDW5WlJw wLX4sQQ697Bqr5ab3J+GldU57m9QXaZIU1pD9X/7RksTLg94Cfs/06zWw9SNps3sQvMK6ePR+N4E 1J60hp7bHyzFP+Y1pIWORl8LkT+ixs1tXF37J6cKxhewklgnZ0MMHylG5nlexLhiF3chL827FNIg D+rH9QyeoFyO0RFakmTS1V/P3rM8ULlMSIT8El07CJ24TFYxlvp/OF8i3yExDU+cfA42rGY68Itb dcugluX2SkrMsNwRqtp9dMXBrVgtQ2Qcr9cKfNCIIl0KfAXWveWAiL+4NTt9ibUqRxnLy03F4qVu gCyudq/EclAi7JgZn3B8n9YRiEvURVqNMPjump8EuPQnQgCUc78jx11KIFrzdnNch2HxdJ0u41gK K+xAEaK+CVSBaNs32q2dHzzY0jtfFr5GvpmLgSIPRRI91r8pZXuob+t3kmxGE6zphDlgcWuuRn89 qGs5wss+A0hR+/SiWIckgX/KNQvNGmcQzLuu0DaaVwJlWueMZH0WqGXwvkxUMnX400gQvLQT2740 wfwP0UMldDqHkkuA4LLurGnjWNKeCaMVLDF9wbp1C4c= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block TRcoZtqjn2mG6m34VrAup3Ue3mXUdsp9Svi1yOdUyuJ18aNmZzMqBL74/JYXAGMp7kyUseTthYI3 PrI0QWq4hg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block FPMMqj9RaKUiXlcYwEXFaXQj6iTZvDXB3ovRbqMXkBKErB6okVtT7N25cw0P4DrPAX3uTf1/DjZP g9FGVgqB8LxAQapqrXO27frLQX/jtpP5BRN/3UyLQQ5tmeo2wvGsRYc6Ptmw5XXPXjfubR1uMIvq n/KnJrhMohYd24Nm6S0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block hmQ19Z9b511LayHM++uE0XsD77aCTvi2D5+tVo/slhNcSgfFOCWou7QB72DRXWqLm1hI0yRUpD++ 6M4B9gDAGymLNt4kJfLjIH35OM6bL+USAdP5LzqI73Y5A9Ex2dA7XXtW38Kapk4g+yOtlcspGQ3v mipApCouubIDIKzAKfit6i+3D5zl06BKC5+/oMSR90fI/572drXx35dvozy88MbJh8nfL5OjT9y6 tufG7IpOsbuhtIaWR26UAUyCxZ5GOOwUvB2fS9q4Es/JzlrcdmqBkwl4ixHzLmdkNChDQXjCJVtg DP9+/cLV+QeiYTROca+/iv6JtjPVTSGXYAp7KA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KGFNy15frm7DKeh26HgilQgudk+s92inzv6E6/4SwA14yIblinRVK3XaIL/wyVEMSS/Nvx17YpaU YVWGfrmqIII72ql+J97vctL8UoKOHRk+u89CmFhhNIsJnQoGfxdh8DOXKgydwIo8DtyknF+rigwD Wrn0cHGnf+DzHJ1IlOw= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block IRcwaJ9nbddmu/9RW2bhH0oH/sFHVn1S2tsx6hwo1+XOm3bHWHP+ulk+4hbdqZE1Olkl9QC1qtoY ePy+TB2nSwbY99tK/zHUTTzEr9V7pe7cC+aCydi5fu9j5sMPnFmsQadzUgekG4OiSkic9/qlG8tY Nia8+0GODU2GsN9eE2823xR9kslK5c5LHAFyOnzohuZuaNQpgH9FgGbNWtWQ6Q+SNaCkDDwUMJRB XMWJMBZ7ADG8CfZuEbYaJpB3sP361wZWR2CVzTkDaWPuOvVZnunE0ob6QwvKmIm6q/myrsa7qCip ZmcNqxskerCWcqETss8HlKwYY/ryLcmRLUXsbQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15248) `protect data_block lo2tFyFjziJNXhyZZC97XYl3f0ZrW0Q7WwUD9LVmJ9QBi2joO2dZ8TfhlWwhm39tu85pBzGhL0bU lLGx5TJC7bSGiCErXI+tXOdZbJN7BwD743jxvfTNU2raF5ycnehTY1hGqwT/pWpIC2JtRTQTyzBp jg0TCqLY1rtHmFowyZv6918XEG724JEsdzGw6PjyfRjRLZtokRZ+0zbRXq68SjqEoVWFXEf047xz U1lXxDoOT917H2vpfPYaJlAmCz0h8k1/fCal34SYbx73cHMUWFnCTybEbJmesL5gfaookMOfBxRk sWQIao+sOuGvP38D26sAUf3oTnFHhf4FeA0y0GfIpGs4c9o0m1EYVlZJolMEBOS91rz0jpo2qyO4 FotW+gt3+tARFTW3lkQliIHC7eWV+CzKIs05UnbWOX2SkiuLdqLxOSfvNuWxAtliF1fFNjG0J4e2 FfC9OGxbUUJo1RrpiOuacWpSLpdl4+QKPVWCQuyMstdh6mUS1MWuoq6F8/mRGq7yZL2pdZIpB7m1 FqTQVbrAzKa9Cqe54k3eQnNS00lwUaAnIU+CzSg7CoiosWSIBg71HYudiGoiBoBnZLEqIkt2ib0G YZPWoBJ4XLzNcluQ1Ajkwv/Xv7R2wBRSej0W3uwSBWm6fUAXxP2We4RT2a/8nGQcnRSmWtH6tvn1 toUbZDD8+Ooeq6eb0K8NO/8rJFhNJV7JNyQXElREEK63JtrgaSZcKCtnBW+wsroNhNIOskBUnQYV 0CCOIW97dIQavxtVUm8QElbLu5USzKEeLvh9GD+tbqC72nrYJbHQnB1ohbEHiElv0JwdtOtSflWL pytwBnhoxQ5UT0UDv+wUPioK6HKBPFktp1w2/8kV+msFfnPCYTZvAF2GVF73mpjIWNSQk99VZ/qf 9K6lAwSib3XEYyTtUO7OnwZNIJUwEDWugnn96iYwnYYes9kgSrOfR2iKOJcSmX2D1CE53neDgkVH xkC47PePhGeYQ+9CruOehZDBHHKc/Fx8iiqW1oWzim0a0wA8NBVV2OqueD1dwZX1CZsTEAO+2Mcf rJFOE7NbOnbN0WJ1EJ5BRuVz2S/x94hwZ8o4JmDKl5Pxa37bk/BXyfiPL6ngdHZz+s8AcqBsyTxu 25sSBxZaeLoumhdgEd1YTf2MrAQZF1LOmD7ZmxpQXxUqzDi0fCC9JKUEAusjFvHSE1xwVYpyGp4u JNI5GpLffojoQV8tfutFGd5oTy2RMT9ZAP6bmqaKWsy+rlq4PgDvJmiJxYPF+FxmKJy4Se7UTCQY 2tGopjkFaSVlGV15HPI95mnUmA4BX23/QHo7TwIzY1um4MKqhwtkxITazjhYc0NiEbzJcop6bimU 5Hd7Ad7cMRDj1a3Xo1DKie1GROb0LBMAKcfeNv2zhs1tkeLMXkNcvX+W8v63l3HmlbO7RZi15Cm/ 2BWj9XfFFMG99MOAbLXeMsJqC+dpxdTsOguJfZxshnmn34b5AcWmmOZRX9sgP8wpUknH+6V6v0GM M8HKbo+sm2eHaAl1FWozeJJQUvPa6Wc4rq7pSjwdGk5FV+syvS5mCsU1fEEac9pxRE2PbEr3vB2V DRnHV0llczoF8jgqeLDTmKG4oyKDJBnssnwbQCarP764MWnhOLRtJkEoKwN9+btcZ1VdJ1avFa94 J6sQAvRmJuUd70Mnii74Zk/EZfliu4yf5b41Xkp0j+lywStXrsAZDldoSf+yNBaEMrVsL3IBAJyL BOT1Rd4YxlmaqzqmbsQ5YRX4Ub5NyDh3sZ03W2HdiS0oJRlV45N5cK1OCkUQAY5cfVuPBGvt5GRA MlBA6ms8n2mGPaNAr3e1b7yydC71SvA2ReRI5Pd03Vz2SAqGhP/59Ge75gqaOW/G2IZoUC11UCDU 31QBFFxVvxTiuKYudkKmOFxFBtVpOVX5BR7/lN+BDExAVuiwAlh0Hu5VDxIm48y/OH9B/R5LdcxH Ekw8rrHH7EGDSZ9Fe373bH13i6PTtHSKCiscmJeqMg+iRxzvY+BYYAtvQxMeaM65oZeHO1cwWQAx ALVsCF6TftT/Rc9MlqkzPpIV2mJ55DHMAQWKWb8QkBjdcs/AB7cnCVg07jbNLP4Jy5RTGGXHwFPi MZhK6ZPQH+3FRieYtmnhUP7xTYheG0c8xaBl2Q5rzribOMk8lVx5rTzHrNPvYdjp66A593lzLTyd mzIocbG/auEuspS1QZ37zHsdA6+QMZzeVdz9hwhwNioBFtgScmQzWrGhF8ppCfURQNObhR+UQBk4 Mkpe9DtCAaggrUW4TaZ2P9ZWxLVzR7jpjApAJsYlqdHXGRaWPT0f7AbJhvzAPz9go8J4/wPMJWBA P8u7WpWVrvnCuVV5PCjsTYZ5eaTAG4JT+q9Roq18Gl60ZmctUFnPlsN2t8Iw2nY2ru895Etg/5MR Q5ic1xjhIY/r4T6qcoJurG+efqeTYn3BsbJIg3gg7va8t1gOGGJ5bTW7FEeibIl0IQPwmhiZXcaG ll+Rcykz2XZzDFCJm1kn2DSeQzDqXz+eaB4O/AG0iC8SJofVp2apAQ29vRIxo+URABT1X7EAk2YP XBZBSV6sg48AbgQSNOXltxjle3f9zd4+0jzoex3KqFIi5B6Jhz3AIemALfWqZnvhUsy3ZD+O65+L z7iRBMVTD+Pzs/xo255Mwm9jeu/MYWRlZ68lFOi3zSBcsBItIlO/PPOAzyOyIWhU6OxP/SJDjuhF mE9ensZ7JNQAbDlglmjZ5EnmdEmyMjtRpUlTxLYNlwZYtyHFPLS1XmiE4UoTB36ClKq1wMYEsT46 j6OXa7Ae6Sz1zjvBXSolixvc4Q46i3M5pJxpTFpU/6tMz7IXkQGWUF6BRt9T27SEIResbJQgKlVX K5pPzrUYjfeh9dwsNU6un5VQLsQtkGbYUdCGgwrglawDVwvo+7GCXnSpxpjPUCGKCnT2WyzBmfOW Pi4Yih/HToHDNUkNypdJEZJ78w27VFhc6XgQl266RK3GoXcRm/4sxYpLwyPaWDBzuSb7qFS7Kfac d7s+Sqss1A2KS0zvlTMBW6j5yXVsQJl7Jbjc+1MNHWfsn0q9rxLoze2HT/OXytLWmfeOtJiPRp8J IPylF2iey2lTQ0Il2bLWnN/Twl7v8RsHM5XyIJlJaqJ5nhekSeOURwG5TsyiIfDcKuc/Gzpe9xgz 5t7aiOCvjTs9UUbNZSIgXj4tdBatEeuAht4UJpVXkWheAgt5qasssjYGpMdom+S+NWms1aa4c7cU rdrz5h2spaEGbgSz61nGMAfONrXan/iojpkD2AAiB/Gb5qug/KrwLDvp6HwKlPWXrBqwHAyhTPEh +dk1VMcvLdYrbwtUyZVi7JiQbap0gpDxQtw1Ce2MOTVUzcUMu5c+XRYSTaCnwMDZVr9vQIAFIKOE jgJSLbzPtsdcy8Bu1LS7pFjY1eKlqWq1LcfhJDCyblf6cEESmsGivg4uVmK6gp8PsPDNWvUy9zM+ q2us3j7GC/daeIegUa4TzRNbtGrBG3yf3zJLs583MMAGQBbczPg9dtSfI/AlQX+5alVGtbNoXrls ER7y8p+bbYSX0Rsw+ytWm/JkeKmiNuviV+SCxQVwdx2Q8CC1he63DAx0GuGOulCUdXuVidVG+GWu EGOqTIyMBG6qTzvG9T2dhRbujJLP+bWec1FYWqjz+YEStYcm80SqY5ilecjQdxJeE7b1PmYgDxTm /iqg8EJewLrF2IeYECtFqYPf0gFAMuWifV4XiS0Abc+f6+B3tCMDwC1yfUgcekyCRIe5P4A0Sql5 /3KWdaeh3eVrZmlsOZrgibyGtY2VofAGToxxZgCP3SvOncAv259/SlswvHOHEHw17krFaMaqwCXt KaZCUgELk4LMZwxd9nJc0AHVMT8TY52JyAm6C6MtRsL45cs8fPbzN29yicUJDgELyqd5OtLx6SnI vwdBT0Vxgws/He+tfW8WXytpb6TQ1weCZBOAaQtwNfhSJcV/CrQ0LMaDsjCORTqgPHtlhrDi6Whe s8BwlZfMZK7DjdE7BpbMDXkpW7xvwxjRxqgMdNmwg95N3EvPbmV+mYCluh6wuXgbJ5rxsKJUtKvW p5aJrbnhIiCATUNOVAABcb2v/V0ZDNPEnIDNkgN9lVy4qYdEIuL9/nuDeik9+0O20VXyd+R8dQN5 a4++rqVcbFmQQfjkfaXX+kiYIlQMhsmz1edAXnOT+UNQH0oqO6GtlTyMRPucmatg8js/JS6PVW4U R8Sy0xjX0CmVYvXlvVbfhR07kQjXfznA67gEZblgvpXTRoHX7Sr7DUNE7QXg1g4jtXgjBvVsO9lQ nQTrR8HadMCgElnYWB1MUrtROAGZoTnBxfHfUHgsSDhj9Feh9Idtwbv4JImkI6DiBrpiG0LQsYwp OsqCIY63+3K69v8JsJqbjGRU34iQm/j6nP0J3YsZ5iyWetQcQ2TqQPzClr10sj5B/QgVQTyy++Hw +s5CDh6ocLBpj1KbPY7um/k56sK0aOwlgg0wSqi35Av5YM7C1+wwS5nCmnNItHXe+WslwIVX83hL 6MEJPXqYQCfS9Rg+mVvASxz/v3FDbVwVKljjkFeJ7oxg+ho3TI9+lNBhY/B7rkDeIdIFgZIU2tkw UeGXme8J3NK/c4gOPpwyfBIWcKDThmGa0d4Se8XxxBtQQYCs7oXYBucxlKVkr3k290pU26hnkyau ULF2ny043WWmhqXJWDvG90oDuOI3KJftR54o9hysqhRD5maT+w04buQrPqf/xgr/vwEAM4VYTE6Z /Q68yFUrPHd1Q9zfVU8ItZu6kvc/iJDBGxiY689Lk9EKs5MdBis+rbZgKtnHgKQbkk6P8hvQ+Hz3 QrSvi6c1abPqfQTFzOl78QvOtpAxQXG42aYe1cumjaTO+YwHHL1/OcrmNug2WDB22+B5yYspHMMr pghggC5YE14ZK6SLRRyznvi6/0j6JhUfVvgPAp/DWQkh0XCEcgptvAjjhDXqI/DV5vcxdpZui3xq DgaHNZnLlN+AiSwhiUvdqdcAgAgbqWcppIqvXreYG/5DLtlu2KYqyFHwzd1jufRuB79FslLk+8kc pE2+4rpbb5I7+T2BfGWB49MciXCEEmlXlHRbI1aj8FMCawqNYI+SaTxAW2Lpb44opWQqc6rMs2MB RtxcdjCq6WcCe/a67b2uEW+Bn9IgNF9c5/Xd5KsX/yzm+GRQv4s5TRgvGOd1PmDS5CXpmgPbNMh1 7maofr4z/xm46/gy1FX+/cZzX4z8B4HWNSq8ao+MokF+twMaXFVVOoh19LMZeHpeAy+yaNOMUlB4 ZHByjXkYxiPQUoEEi8ZxUkWNQEXBxfS6JnfMTM6PitDDiUaH4v5mG+cgP/GyMwlwSbCVuYtd+ZLj Z1Vo8jk1TbUy4YwVZN6YZ7k8H5+bnhOdSlYm5VsvX4R0RPPfDElc+ULn1p8VVbAP22fDB7vjpg+r Fw+xC6TL7NY/It4Pt/lGmgYLhdOBItWGqWEw9w5BtgvKWICb7oKpkt0OYoL8RpgVrDKL4TZFPHEx TF+QEEAWi/qBHtpFefgmlcpp0cOMv/1SyDx/YosFuPM2nmj/S1kIQ0nIphjSxRlgDnTVx8V34pk8 BfzcQQWpAKoKcp1Sq3ls5m3tm309Er2uvSnwkiR3Py6zHkT3w0Hi9++VsmPe0btjY/REO7oyFVg6 R95dXw3Yho+iq+RM9mchg4BHOre9/KJbc65qPF47mKBnO+PvAmU+hl5lsEamo1BPencnba/P8o0z SbZN1wcIzlnbS1+XYPPlZO+lCOWnVCXwBiMxPiNzAUKHUY/ch6KpYGM4y8DzbzeWJKbQqJUx6bGw Htq8GEioSyFGOgSLfAgprrgSfvBbNnr3o+2XEN9i06V4HOGGP51M0BuhOZxsXM7LC17T2bno2lxx g3MNBexWh1Il+f7p32f0p4zchekCfXuxi9ewbdnsdhoTZWGMx1SR50pKRuetNKn4lG/wCYuBtMvh eN5mHMzz9sNs6mExAUsCDuuZTKFm5ozosPvCWIhsviNFQ4fJnmOAIQCyuybW9MU5ua9T08mNXEEJ 6lGpuV7d6XTL6AEyHe7ZfR+GlGyHtWFmnmuNh8HgVvtx++CDnqP1/WhsvQ8bDSZuW3NviXmCzWw4 Gt2pKlFzptQIC6Zfl3RnuK2c94Manvfx8P/8eYsrotrR06wP5TPCdnELK/6Umb/fbqzERjSedVtH C/XNkMeW/0AbeuNKu30powhGQj5XDKwjoJRQNXdKllJRgkWHMdkyLwAMMh5XSq75MVUJ1jGvRFpV kPtMik/7OSZ9aV9QgtERkL4tQVIKznYjD6cNl74hKrilOaPTxC3MnGUwgWgaMnkDyTGPbgI7IoQb SmbhzcikqOd6IUbBprZvw6ayE0OvckZjRoOfficSz7j67b0DUGKTTV1nbVEp4Ob/tBPY6NJsjJKb z4sTlAm4ozcDYfpnhcmgAHuXvHiFFBkMBNZ3rjYT2cEriQ9TFLF3mizXSvt6Y9lGNjnsELiSVkPZ RFto74jJku8Hss6xrKO49xXr32YVTl7TgSZBYBEReZSDER0F/9Smcx6PxcaJbEbHcoIgaCinTWDr xbClLt//kAW0biTwE+PgAgoIYlf7HXMO0iCrf0mD/NlAKxr1hLVveiz6c4/fddjlT+7789I5+4wX uP1L854G79hcQIDuJUlxMBN20YgfOFUJtzkDPbG4Y93b46Rzs6fZn3Zp53ui5gkJRnKQIx6wllzZ KGRD0se9BG6W4fHDS85OKRa84HvXcWNex6fUE86DO4fF3z/VLNoalpz8xfHzl/1BbFMTWoxvBuex Ewmn6Z7qXBrsz6rp605BFeNwjhcEl5rbKnvtx38car/MBj+kpci2RmvwtfYvrnFnmonQVEhlqqtb izVSQZTvDvDylxyI6KejyO+ad+O7KhFt1ObvtioLPhjtD8o4wAKHpqAR2Hu4XrAlkqR3GgQi33AY efXDINfwKWhvU4CTCyYdxJoAZuCZJp3VYpqygSeZPSM5WeY2E5wcbvPG7jTqIlnJ7NPBPkYnpns9 giuPumUmUOOcVFAh+1CMZW/i314PWY6dqh3jiFAUTMd2pAQlhzp0COASBkI8yHscCuL9e76LrNEl phK0zem4ZXVqvQfeVpDjlV1sqjkZH1bX/jm/plr8dpen5FxOm090bHN1BTwSx3G/mdGH75jaC27s ceIOGoUwoN/jYig7YwIJchD8FpwjGlocKJDBXKwQcEkAFDczNefFi4ziWDNI3YZTq5+thfPxOEFj TGGLOA97s/C58H/TQ02vedrKqR+cTEiVINTohDV+noR/pHiUWOgPDa/QVi9UZh1pv/uISiZ1dRQu Nq2qa1skuihcQK01oxJjvzePeXBQZ2qTzuUpfd5EN2ZyRny5dHBXJVMGeIYHDtTdh8pGBwDlAxYl 0G1e3k6mxqAjAIbYKg/fX/tnFMNY8haPyljcp4x2gBI4a0AZa6JtZpg9UfSlBe+Kl6KF9L3xTYMg ova0I+v2YhQPCmumDF1d+iDw3Fqkk8UoOkhh8DPP3LKU2pZJTLBSe2V02otyUo/C24nSt6n7MfV9 tTTVIzTvDeaMXwCb9GZxY/SeIJPOdaKmsmD1fMSCCsnr9aNmX0Y5pNUJDyTIuNBZAqVg1e4N4/bg wI/4dmn2Je6ixx8VUYRktKUsL6H5wc8cK16cWLMq7/XpfvPWADFWRlKdxzO4cRhSiYOka0YTRX7M d+cF5YXSMaXGd2imY96irnT526iu2uUVhoEnfCtxxvPuRf4jP6dwQ/W3Dwl5mjf6YgVw9LEvQdGD OtNhvBnzj9oO5OmZNsPpZlnZAu+wCFCaZnEsoT/8zttWrCWQYVLlmCMDGZqkIyYOmKZWq/gccVvR A5doD934rvPOkUR52VfkpIap29Zb34WqexqRn/0IC/DsFN7H73s2bLdm5k4vIdOSUJPrVoOMlunH fEgOAXDejR1OA0srkMW6DirEbc6T+3BH4lBAh1VqdqsQEAaOJZg2uHj7x06rVH+ZKKlimvQKRYKN vvaH3/maL+3obAIoMsvRXtzFP3BVjPVSDWlrQngRtmjDMASn4pDgQPic9xmdGeLucC8wW/D7bQqG 3vFNQaWdOwNAEAJg1Fxdrw4+FoSZ1+tJuaem1QXlLZp2MWnmc2naNfy0+frSvhWZLnd5HTZdmjZ8 jmmFY+wYNqnivDXnBgXQt+lTaZxmbiTsBDYd1LxnrPzBdWSLsYIHwSc4qknEunO5DFFeU7J/gRBD oLvMA11R0nbZW8FqjRQegzJTfXB3hCElqcU63wMkM3BDPrFqSn9jMY8AtqyTZmtrXoXB/JgzhAlu RWpCGYM/yQU+VaODjSS6ahedrwnZfEucVY3S9uIJOiCZKDxQP6gvtJwHr+r9mj8muQoOva/k7shP kDDFoYx7yIzd/PX18UAnuQw0swQiWnFq3Ysamrz3cEb3w7KCWCE0miZadUqagWh4Ui1EoA4BtTCm XH+ULndTI8KXBTQtdiSaIelm8c4+Hsg0C9LoAmezce4IxO4XYdeG5mTOuyhdvbaf5aZPhYiHfCiI 5byWtx4XeofT5LYNa+4oJv6J/fs5re14ShP++4ZKMOnGmUcB0xqymmMzKZeFzu5qZK9C+EJniLlZ 8X3ypMzEUK9VjeCEvjNhAi3kE6NAMjguWHtVAoxGk0FI/+e6I/x0exhvmD6+PsENXHhXNgiGv006 kLSDnkx+6CJgztcEI4r3sXw3dTeiaYYzJhTJUw/z+GZmodZpeCbVrsAMv6bW62Ock5wdtXqJagLV VSPRSxklebpditAz2peVOrKx6ekkD3hlFH10CWt7N0b6mlRFpGzRIbArJnIkhZImFhfLHYxrdG+u Q5QWVQ/qK1qjjWUkpMLZn8KZpRWY6Iv6/OD7Ms/rIAfGwrG0WQEh2CoA5kH+kVtf/KjD0kUznGzs uiq3DYtmVnkzXkjgSTWONZIQMe4uUy1cDbwde97AS+8lFfBBUOrzGikwN3CnatU4RSReVfMfsmj/ PiUvI+VVIfB7fLmIYirpkTyJlLbNqgCbxTC3/YUKvQeKsgdPYRZ1AQ+X2EECrxumRyYdjdzdM266 q/ngQdXkaptEq+pWick9hXGMZv4EXwb/JiIrIW7ZzIyeRw/iWU9yREE99wH8dhvG7F8ZuJYODoZq Z16s7UDgdwZUz1WAASUCVAfQ3Dz4Ys/qpMTTBwP5weg2M2dpSnI7P61q/kp34JaDu+mDwNRk0OwM S3MjEJmn7M9bosNMEbdM33rNvuBPGrGvt+N2snTNy1pQCQVZhjxY2RTzluBYwLnmqOulukiROf2T lArRBTBcutYaPwNKiLDgtbC263UZD7nXmBMnFbxEdHQ1ciWmpHo0nZ8vvOpG870/W9B0bIU00Zf/ mcQGtsdoYUq4AKCGeYuT86AIsnm9QubUYTdvBvU3355svrEH+FrAn85xkA6Qj+KEgjcTOsEO2c5v a8QvtrsHm7QlyZz4nmX0z+c2xrfYF4NYwB1W5swgvEVPbo4m3MZ2Px6uQ4tZ7Jr+wdowt/fLBqCX uejBBNkZayRvIeXXegOy82MWj9Sj5U8GmR2j4Ufp5Tz5cl09egSavAg314dcMTUbqJ6jko/G/s0z hal9n1np6/6hYCO88KZOCHYsK3yBMSXLeTryLK5iIwAmSKbm9hltXEyqJiU/Ykw2gjkbjNYFYZyK OHlDaFUUF8Dhk5sLXXK0BwJjB+7JpKt9g99BATyq2YOzoXh8tzq/r3PIhNKefbBMhJPdvtA7oWKl 9BfWupKNcvAuMYMENnX6MVjyiMEoFSq8Q2c0/0cv5SidXn6pvp27hiMYAviHq0/ii9bYOBmwWQID rFWstI+te9vAVdgtKckvIK+bTRd+gYyq9379EVHT83riumNh79bKQg0kgGASNv1Uw7qIDGI8AYe4 3Cr2lbdTaIBcgw2Tvs6tCkZTOj4tbt90jk+jhkBt/kfzyHkFq/hU1/tPwEg+ei1zO65wpOl2J/Hj zqdIelYk+Q2gMDD4UO7B4QJrq2maRaOh3NAPNsNttqNh9PtnRIZSIhmd5DeNgbe4Q8JUB1BBA/Db JsHJ28cwqoLKRQSTa9PtlDgLzK/NKIuy41SAJ1FSZmQK+bUhGdPEwKMPlvNOF86H3w3FB91qra5r t13g66yCkK2nICykaW0+ctvVWO3DnQt5dQNlWp3TtwC+UU5R3WJ4y/KFK7Tc+hyB5J1440FQbJoA mpuZepfQ443UsJjyxTanoZhHKOD7Yvpu9CUn6Zp2ktivQoqNB5T+rqM1EgThdTTt98MM8DcwEg1L cszhN8IqINLpY4sFYtBhA2qTuoeWkr5RoLqT1hNi7H2xnoLA/L0wQHLjIKKqmRGyBX70bMIj9bsY ch3AzRyhbdYrUqvruR4h/V1egVCDHLMUhpxyGacBypyCswL6q5ji2LFtQ7nVCqHSOqJc5Npym9fM /UrTlm/16RpH/DuxDBck+pbAmHknMlME1lvMkvsxo8vMkwGvPuIKZr7n+S8Om+Vv9ne6FuIdbzgk iY/KzqzQBx92OXH0B5uSdtUeXsIalMo9BN3mNG9UXV5y5BJ3MOvtnBPeTkI/N08QG6YKJzUS/iWl 4W/9JSe6d9oYzuciEUrxzlxX3HUS160cyAQ+ODwTRnDtLi1U4hRgGFgIOg8BwEs2ilLtuXDxORKl bDSwNX4I/PW/qhR06nNwbRjyVfIi4VEn0ULSFm8XIPzEJ/t+xQsSK8cRx3XShqsDrberE4kcF6tg TsuJ8lO5r8rDwKCZOzPkOktohxlDzfICQphnJ5xRK6sehksPxetSeYsrGBplI0VPdhJLFAsnUFJd Ev6OqHdkRzMJ8+CdkuLN/snC4oRaUvANsK0doQmZ9+c2NoNuhNcVod8kKpw/3twWUJdfa0QIGJyX qzI+dQhuU3lWQBhEcJhG2DzZaUbDxrbX3YCGd+k1wavEf7VqLSwaTmmEwdZ7jtRmuK6HJ0rRISjP f4bD6ffOZjQ6jYL8ORBWeiI18SoNK6YO5RYGBfBdFqyxzJNmYSlofk85khFYSEtHVqecaPnuaHdV A6gZQC8sgAX1dfe/II0uTSstSA85bk+rpeDP4VHMB0X1lMFwrpVV9b7Y1Di/T0f7rQn2P/PPC8vQ 4JLGXzybsadQGJ3W0zxfq6PJLdRyCfJyHIttZEiARP7nqBDcTIyFCg+PvJcQZ768hNO8jAeI5jbd msSsFZC4D3N1YQDVZwj/7vmIilJ+i9qJnvUTwUBySXbq4FY1JyZSGjV2GWZ29ruIU3MwbAdW8m1S 8XTvHsbcxiaPOc/0ek7gt+0+b74qNTeX6VWf7fYDz0SZaKntTeuiDevjmzuF77fbaITL/5ISEq+I BtyvYS29P3b9B8LA9WC1N7tSTt6E0OIJxmwZlujkOJES9mM6Z+91WHY59qFKpa2siTL4jl/unDC3 uOuUsFOdpOp6OgWVfA4U88/JJrs3XraZDrp7DLnvDxEiss4+J8j9p0bw9hfz/ZPt9o/6Uv8h+z0P 0FRGjl6c7lSreB79+W0JPk5s5gfUN6tTwD98zYuEjyv0TIOWxsgQQOUE3DPnCEkTyCCwTqLktu3p ZbAGkWSivgpDi8580gURDEmQKDXhnks2yBDsXxiZx+N+UqfI8u1RYwL7sKZVDsjL+5mS9igixKJu mi6g1L08K6EDnZY73csqvUrwEVmlRdOTzVloSY+YdTJFeGdmKYyB1As6DDkFKmSB+eztHKVE6V7J bnAUyg8DRbGxU4KXgrC4UiJRgUaSYSVe8KHSshXafQ7DPFMKCB/GechX2JL7p8dmDbJWRYbq3c3D VMhRwP3vts5oXVTfCoNn4Ep3xMja6QsusMNZi1papKFd3yVv1l4skzpTWAg6o9EWYEnqzjznoUT1 HrfRKo7S2KqkgK1g14Ipvf5gs4HrxpzJEgZuUK8pGZH8jbP71j6nuOlCB0Hpr3ERm4DrKn3/DIFV mT8lJzUbiW+KEHjV0PjT9SLWH25lIbLWQIRxB9dSjAmOM9k0j1SHqlfPU5PX9UQi41XcoqWF1/bf HnAiHpCNxFAyWodIw9PzqVGZ03ei4Us0GAC4j0PZBcaZ0jZTD4SYgR1WAaom04ad5An2SupDMqD6 i/zj1uMkN1ftCXWyyAYzEknvYDhlGSGqD+pgEx8jyNJwbLN6dijDF8o4EwiSgu4rs3zkTetGVXbL ZZiW6gvzetc8r8CVSkDS990IslEBE7FEog6tPOs9nAysN4zANCHAB/syxXsIqyaqDLxj08oCHAN9 Ea0E1TcxVd4p5aMrsZtaPXUny0WsQcZmrVua+pUORYcdpMtEpDhvNun7+d7Yexd7yMiL1GUXbGBn 55J7dkquCalG/Xmy9e4QOaxqOqW+fLjL9VWuDLKU9I4iXyc7CFC1H+GtUT/gMBymfmMxz/Q98/Yn inr8+5CbwWjD7si0setE2IM+NeUnQa/gtS4vfFkIdPi00vXllAM6pSC6/0QeBaWa3+r1czPVFObj PWH7rYqR1ooR25vC9ZbZT403w7uhulpM0H08ajEmWIAkOGsH5pQS088ug2MLhd/hO26L4IydGeo6 3NJdiNd2TsdbmuJoUSGGh8mJf7yFL20HUgmUQDeoEGFqgtWO9hcieiUbBjhXP6almms3b+QF7EB+ V36WocNhOtAOiQMUjP7amBx6BWL80y7ZG0C5mf8ceE1zlOP6JSqIKZ2W2ctmKMKCzQDQGvCAR697 3oxFl7KClk72SSKOq15uzytrapXDRz5aKpyyrxpphsZ65VzcLdqV6Dojj5fnaE4u7A9xRt46mmNI R3KCXahZ0diUKnV5O3bZX7GFF5iaaJHwiBCwxadX6E52fTHqJ9yr291p4tG0pUlhCni+Y4O37EEq fwWvrSrkv3NqI+z2V3Ifl7Zh1oY3E5v+/mO05jsJmthiTfptmfo4jfUKFl5vHlQUIKwDvAGQUvAg syriuscwJEXegC6+8l5wdH8flHjlXHsQa8+uBEqX7KqZ9C6wQSIvc4OmKI7Vz6KBtqEuFqTb5dHq /as5/RH/jGlNFwZjxlQZuD71nrhq4+Oz/jZbm1LpWZ5NXkc1Om9bx18JGA+1sYR1xe5R1zs/eay9 yQETW4yLT5sKie3PwxLcmjPq5ttZ540kwE4y/K8ZEX0dCsJvwBDTPvftVJVws32pLrhd6lavVuIV c5F/9O9wt3B4X1NWTlchrQwc9yKzvp5L5o1kr6Lg5IQe1eBkFQZX66eSgK5cWPkdqyq4yMniZEZ8 oYrcPivSsc4lOI7GEYsE8wLnE9clMOPlm9nriJxTDZ2i7/HmnL1Q0IiPMmg9kdgtz3VlAuMQN9RN R1iS9ykHnegJPyKBWmIO/K/BrHJen7afnI62YQbUp0Fr6IcNROoqq0bsYmSBruT3W75JIG0Cc174 /PyIiLpmjWhJ7sl+686Ml3/vhYFFD5jlDOQ8DLKpSmaMscH50ZsQihpoKJhP1JNtd9JrOd4SdQ+I px6bNnblous1n5h522nqwM6XosLtL/G87CJ/bOSeIdbixbyZHxJXOIxNuLdRQPb4QrqiDHXMQeah eWPEMuQpf6dnYjM1KnkKjxh/CxJtCRmkUjJe8WqDLzpdI6l/+L0JhoDyQuH/9S+V3bgmBC1C/tRk n6xVuQr19CtS+Xg8oQP9zBFToFMk0fN88FqXnqAkJ8BOu18iSPMpTTNWAs6kNUw84Po/gZ+fcy4X wB8bdIiQEAAztvib1K/zwMw+cMVzX195FEMZAJ617/s7L5wRqluMeECknM0HC9AsZb08tQ7q0FBH vl61Hyap/2Vjte/O/g8RlkXO6FICuys6T+qFHYHwrNzhUtaMXqkdGddnHVh/E343B0WBE9GXpeR7 lGji7OfIToIlLxunpXzjw57MBUgjLBCzZPsPSJSa4io30B0kMP+PCx+qFp//LncbGBwtgPWkAgHL IsQhLL/xfkZh/36LEGgpPNlnS4ETUoifcxEVusUOVrwv3/tleOCN1JMljt99t2sXt4GRoGCvQZaO NrVh3sd2KrXhII0gfcLdpbryzJwaZ80HMG8KCqLC3Ga0yT/FPdDa/eOJJ8KL7fQtaDwXSCL9cOhM Pe7qiIINL27Mim7MzaFHp5qUtpYlVv/Ex8bJ9zNFYLn0uO7H2Sn5JOuwuqmGkR2SNCz6Fupox8/z D8LVeAe26qFrZOsLD59zLdgbLl3asB1h8osvKcLkvCQCSXQjhQntaj3PjjbVBNWrOLztNATp3Env v0FW90WhtZiU9R0xHi1sqsHDYZ35slEh9gKRRyw9tKM9OLvY0Wg4XNA+mhDsls1SiQbQOqC9i+3X IxgawQKwDnEkrbn+DXTaV2CTV8ak6V9WIDsfw8rqGcrGaII+sQhmbbfZAvM1+uWubre3kQlezwuK PoVfogigSpV0tNW6S2/LnMr7OOLeHvpFV2ikQWTbx9oirYNSEPJbWoomWNdL8HgkwDoHyknAsPxN j+YV8KYlzrLNeOQqfh/dZ1RhZbz0DJMx6mPpZSv3wxe/cnCuLOq/t625aVMNRyuqV4nkGpV3bEKb Sq5w/UAdn289Ylqbk9amvEHPGi3JViwXmlml23kzleLaClulOSgtec660aGPQ+NkmvpfRKoQfS/Z jVqqGAIy+pKJbg1ijmXawOzL2MWbm9g1Cc0wUsDxw1SYbxQ8ZR7HaqEyPcCy+fJi512Ts0OLt5qe hnkaR6rzQ610uluGwmmaqnNe/JpmSETIqGhAZYlkGJgYqLau80r9i3vhe8k0QMKSaOnaLsiieYHs bR1H0Go+tU/Um5zKqEtjIUYxEFeFmLiPdU6qFVy1VqDviqJnMgToA/u4jaqI4/WkPz7i5Jwg5/M4 x8MIXD+CMxg4sM/KbEfro9Xcc9ysF5OStAOT3zn3Gs7dZkLSuboaLGS+QWJrsVH7jmxlxyQddLE1 ZuFeh6ItwlGKXuitv5MkMxWnZEOLwNPIHF9CfqES3PX8Mu4nHsdRb+xeNrbTC9mYEMvxQgMLtR8D UjQlZm9qIBKCdU1Qx+ssRmtB7hB6HpTDFkCXj7fw5EhPX/TWHxqRYe6TMnj2HlBZVK2FNWIwmoD1 z2kUSyWa2h/aKvRs9G+nWyPmT0j3dRuZqMkZBAsJuJp0iGYVKPICWos7uo4TYNqm0rrcN3UAhljZ WGlcu1o5LpU/rnRV0wzS2X+YMTxz0Giaz9gpJ/sqOdgBiuFYXJDckfQnKeOdLesW5Hhil6CCc1Uh PZ+acLCcStjGwBl9sxyAdpiJZGhoSZ0LyUTT+x2sWKi14HJ8c0pIAMvwq60AEthGSTnAXDu8y2+t 7WyNiUepk3gURbhqidaE/Pu3frJMq5BwZaFbR70Mj20NE7pA5Sg+BxQsaysUV/Grmfc6iap/u07k hQ0d58AwvkMOCUCRuVpGUzfEY7jAUB8logHqIYRt/Gg3y0TCL2GKpRYcBw/cXruXF4PsqphMbz9S EetAjixDXFHFuIwiRAeTjSQu70P6HOMpsfpe08dQVthvCCy+PudKH59SdelBTsNBPVcmyIumGsLb p3Tr6N9UjYyY90j4y+cAMp+4RmTgEegTSMeUbpbVeNYUI7Wu0H7RcjrVDrWSxtY6UPQ/Dx1hn8qj 5fAdd5SBIUcGlrHxWNN9a32r3ZZZEOsNVfCCYmVv+iAMDe0oNAodyu7w/q/qcwppLWxXUAMEhqSv vt75VzFD6UTBN6Gpl0xlB6ofPSHMtOTyMry+w3kvzLxLczALwH5vuuQScuo7eMKgVJ97jh/NbD5r 5mWWFGiiYGToHBdP0Yp76oOepOPjDn97NxkHvVoXYZY09wHSD67M7DoZ6mFay9tgR1MjVJ/07MrJ Gqfz5hsG/96fNz6NVX1sGtS4n/YCo+e5vOdb2lL9yfknjD5VeFRXw74rt2rZRVT4OGEKPY+z//f5 MErU7acWK7pqGvN10o4KvM2y7GPDIOdszj3V+5zGxaRsbenLDNz/YtPWlkVihCzomhhBXLtGRH5Z JIHrEch2Qq+V+cI65CSviLaYXN7wqiicv7a5JPIQbol/4EPgN4OFCYQx7GwDmjp8rX8jBjtws6fe y12wpztmaykpcO2/b5mJ+bm9tNHw+Z/vekRgHoQEBAAIaCdQWjCjxstRIm4LHDbTKa3gsUGCoSg2 Tbw/UUgoj+fFcKvzt4bjxU+RWbQ+f78UGB7OUEDSVYLkqHAfolUvw5rpm6Bw8FF2HsrtR378Iv0h J2pm/4MwDHnAxQVkpg/MDCQI5JVCaO8px+xlGOMtGC7/BMrIxTjYRqo9LpFGIlOwScNgfpBrvjAF 3yqFFXduKrWYOOTsTHz7o8jBXyo5MP9YEw0IiUsmX0Ykj+sSswtoOk3arr11bzp/SNylQ75n2S+t mSAvjUlBJW7JuAwA218g14d1KrExYh1l9OEOgcmp95E2XKHXZhmRgr+2+EYAvsMiLWwm8kIl41lt CGDTL5/3CqDKnHHzc9p858NOue+6MTuwSopBPSkq9Ita1y9kgJxrnJgafEl9BX3l4sBZFafEBDWh epXRZ0iTEE8b4dzZ2WnR+yF7sV56SvH/HVsJxHUGj+zvukJmGva8H5aEy8l4jveswxKcSi43vpPl rwLz6soAsP3MixinEYYI8v1A8JGWpttM+VzOMr+zkvLlCyk40XcWFzFjoKrW2dUgB0CaP+aq43jS yWTW75ZxP50PQBEVXeHGy78vMDCIZLPimV143fxuqyrO5X8utlxdTB8FDRds6fGAyxDcMyheh1tN jbaF6wMhWnEYH2zSkI3bG6VsUgLxEb8Vs4jXmF4C+cuuflN7r//s+jYo06cDgpOgqM53SmH9MIlw AYOYD3WJ13Nwr5+6Hb/ZyRksdUe9B1A6Aru73cRGAS0GDocaLdJVVtnqpqoq9jPi2ZzvlUDVJL2s BPS9o7k+dVVldul/SsgANNDzUm0Y8A/EuepyJEYnPZskvkY2kabzB0PR4OGwgpnmAkeXMX+YWAzj lJqDmsv2U5SyB8lx6NOOUKLTUiF0lgGRK7mg4YATGiLsCGuxeomuFVjC3oZzPFpx2ZTKeVNMyE/J VsfU4zQPsCpOYUrbxffaRilHAB6mm9kBpplbasLi68vkkXj+U7cyx2GRBT78H1iH5erJ4L6Io6sV FdjdPw9oOsGREAwYnhl49HB+rAKU3Ja0rLFRz0b+TiF6JjVQHosDcAIJ0BInTbxunV5DazDH+J9P QzmyGbzIyqpd0SFjlJzlvQ26OO1NW+W5q1yWN1bgXOivwqYXWGdLRqrze3QyjcT593wqN/Lf5FoU nS1xpsXAzeKlwCW5Tc38ArA7SsYn3BTRFc8Oyb/Wzm9tLCo/wJHDyn9DMTf/kn3TxBfQ7BSDfqmM Jg8x8ZVbJ8gTC6Wy7oabBzL34r2tznrdsgm4PNgTlJEajPkkdhzhecxD4aGpRo0qRQRrfTud7Mze V49P8U9kC8zzF3mSFQEN45MghlyzJS/w6oMZhzdtvH0MMkLmm6J55jQrjD/MmOpoMG6m6o9S7bgZ zLGok/elhTN0YwpezWoJ8s4XKgvpp9z5s5CH1AH+4M/La2tWKpGjn+6fgaIqQfVLqSetEMayZL5W g4x8+tLc/wKBoX2LVdScspDi89PBIxPHEj8XVVjnpwFQ2ORwc54wYlRYvMlhnNfMk6QmKZyDsb04 cLNCOgE8cCEU/NXXrmFoCj5BV59wYehYjW5rJb7dY6cNdG27z7m/gsKakAy+MsZkBcxY20ta8ujf 5PoJG6Ih28Zezexk4VfWoybDX6/Hi8k9kUVOHNFNhoqsHvv5kna0B70fctkMW/PEGsemkKX7VlQu ZP9243QAJSAesf1tiZIqUpwx3627F+HhAPGipKuBelFtdRXNcESyUBoZrPuF9C4QLjmUOise0g8k QLSwOKKDl+3LuhacLJUhLjLZhcm0WSe9BFx8iM0WxsRxEo39N/BAtAvdYt208h3w8AerunI+sCR1 ByJ+GV+eG3UCZjgcR+9/VozqwcBCZG72hPRCrf7pQxVwpqrTtHc36XVh4/xmtcceVhtsMPcVx/F+ PK0x06AeV7lK5kCUl2nfMSo/mr/+auY4FjNIRCa8yRfQPWTsOCdVC3cg0fLoAe/Fv3L5Vg+RImnQ YbEw8V8C4mXdZGpMbDS96EKSshF8yfCtsnxpuNmDR10S0VtePcn0zDrmum7uQH6TN4e7ficj01wU 8jL/vhOsGloFgPeJ2T2beG/LK3fXd4XIHAX88udns2ReMK7JONlH/4qwXxl5FKrMwzQy3bLwGgq4 m2ZUcUClHuAuMBFzCa2PCNCohOzTomBJVd+uFTPzW4ibW8rK3EhVDAgBFw6sJLTCYSYHO86d83zj souvG7MPaMSsGShxZ5FyQXGBmVfPD2CqZALYHqNqZENf07cH5sfE4L8L4+7O6sUcrb+Npb0LsWkE aewWKCLi4QElc+zRvASHrXDYv2bvzMc8lOk9fnThaqdFxjTMTiVr8BugLRnBSECgWUIsGwdnKF5R ADrDY8/8FFuiFvsw4liqb6FQdHROoUfVX6gVQmJNANCZcGttmn61FtAiAHWT6smZeC0RepcxyubY RJzldA8EUPuHQweNwtPqEFCUbLTvZMzmSs+ToHvnOy7U99iJogm130ZiiGLzEgKKPeSruhv4xHVV pK9SoEaXneexYJPF/Dxr5QGXK51vpobQeN+aSTEs3aEmnZbAwMtNfTP6bbibpJA/ZtL81rJCv6da A7rQ+/OsOA0VMvGCc3gpDWJDfoEs6fhivba+/06Z8SCaQIXCdS0Q1RiVcHw+UA5aLwMCJ0yFNb84 prxwUw7Hx/3YTuO/rlVxEYjAuz8WSCLSndjntzgGDfu0FJDvl03VUlx05elYViplu0Dzx0wQ+ffT BKDasDJlMt3ap8NZ5dsHGwXAc6MUM8btAYaoCOssIo96rOawxBHVnr+rqcBC3GVnnYJaPQqcVvY5 hsagQGLmqUma8Z048eCjiCPKdVPPZon6SfgMTOapvXaVP5eFRaWok8YDZIeQCPcJ7vNX6ib5cRXA oueUZzdXkljsGnm9SjTKFjoJf935JUt9vBvdzpCjZeSdMkUfvpAtHAiovo0K3mKb3ouOV7xYcRzR gBrQEqrC5PZjKcT44mSG6oDZNABCJ0JbEgvXJV2d4SzdMOdCoKLV53TArZCM1mY1fm4UtE4glFLa jtau4K5M7dwFZMiR9aePZPUUcEcxcbQL8mAwNrI4qklp1utJUh5BMatlsPLWFoURCxMmMpe8spNZ xdCtMpFccKC0dTz0eawQZyLIbM9SYj+Y+dMXrNhYndaw8SFOgZedp/W1EiIxHfnFhNip06mSqx+l Or8npo/OuOPJnY23NCx42e0aSQy3JEET6QmwDKo2PF7CadsQ4oUd5BWCRG7CK7gMMskUHIiIPYnO rtws9MrlEHxdAas4XjbT1WMwxJemYUqcl2ZjyzBmrm5cDPyeCiFNHeSrzQRulRomXnYoUf3XfcIY zBrmmGowEKsmSkuAwLy6PVsZN68uYw7TUP9Zh8Zl6t8o17YDwBLjN8jJNNTcYGvaR58E05M7PJrK 9rXQJzJZYmdKTc7cxuhL8HF7wtxFkyYqPKwD90tGfD26CViakChuKY59zAUPciUW8j3EMXo4cMEi xHWFFgXrw7EgzwSE7pQLFyk1njycQ688CuARfqwMwbsS4HG3Me6sIRAtHjZ1PVhoNcP6LMWIrU6t GffBsYylgoPbTfe8O6tTYu6oTo7RvdiW0tViu1XkihwTKJjtCgHDeVSgeVdbNPUafJMXiDmKT5YC 4c+Ih7u18V6qBar3pRkseN+F6//AYskUxAeYpUuwh9ifxbXfk1Rs/vcte3mc6TX+9ZfD/hbZivwJ cgySx0mpnPLaEWkAjLwCW2mehGmOZVJxucW2pgg5nBojO+m2/+WAG++EQ26eoLuZLqEMsSoboe4e hyztGjnTu5vHVtOHT0YMFXx8lHrOz21k1kWG/sSlnju0eaKFKZjWPoELxhfi/dq00xdvdhuGR1jY uJ1P2Gh+CCgRXy044opH95iRsHfO+dIscQoQ/mCA7SczM5lAtfjuEeXXVSQ/XsgK1n9aeBtOHbso 99R2WajBIGUeMypniu3VKUOfQjuPCapEaksz6Fq9148tokw1YE+HHP9/mi+W+J33QNNol19fG0vQ Cq8G5oVVxfFqMozcuwvKLeLCTYrwptE+WBeZgoSY2pWLjLbw0EXyTXhm7TA70LXNo09EV41UpjNt Jts6yCKP3q9XgSeafukZYENWE4aP/35k0cP7ALY= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block TRcoZtqjn2mG6m34VrAup3Ue3mXUdsp9Svi1yOdUyuJ18aNmZzMqBL74/JYXAGMp7kyUseTthYI3 PrI0QWq4hg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block FPMMqj9RaKUiXlcYwEXFaXQj6iTZvDXB3ovRbqMXkBKErB6okVtT7N25cw0P4DrPAX3uTf1/DjZP g9FGVgqB8LxAQapqrXO27frLQX/jtpP5BRN/3UyLQQ5tmeo2wvGsRYc6Ptmw5XXPXjfubR1uMIvq n/KnJrhMohYd24Nm6S0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block hmQ19Z9b511LayHM++uE0XsD77aCTvi2D5+tVo/slhNcSgfFOCWou7QB72DRXWqLm1hI0yRUpD++ 6M4B9gDAGymLNt4kJfLjIH35OM6bL+USAdP5LzqI73Y5A9Ex2dA7XXtW38Kapk4g+yOtlcspGQ3v mipApCouubIDIKzAKfit6i+3D5zl06BKC5+/oMSR90fI/572drXx35dvozy88MbJh8nfL5OjT9y6 tufG7IpOsbuhtIaWR26UAUyCxZ5GOOwUvB2fS9q4Es/JzlrcdmqBkwl4ixHzLmdkNChDQXjCJVtg DP9+/cLV+QeiYTROca+/iv6JtjPVTSGXYAp7KA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KGFNy15frm7DKeh26HgilQgudk+s92inzv6E6/4SwA14yIblinRVK3XaIL/wyVEMSS/Nvx17YpaU YVWGfrmqIII72ql+J97vctL8UoKOHRk+u89CmFhhNIsJnQoGfxdh8DOXKgydwIo8DtyknF+rigwD Wrn0cHGnf+DzHJ1IlOw= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block IRcwaJ9nbddmu/9RW2bhH0oH/sFHVn1S2tsx6hwo1+XOm3bHWHP+ulk+4hbdqZE1Olkl9QC1qtoY ePy+TB2nSwbY99tK/zHUTTzEr9V7pe7cC+aCydi5fu9j5sMPnFmsQadzUgekG4OiSkic9/qlG8tY Nia8+0GODU2GsN9eE2823xR9kslK5c5LHAFyOnzohuZuaNQpgH9FgGbNWtWQ6Q+SNaCkDDwUMJRB XMWJMBZ7ADG8CfZuEbYaJpB3sP361wZWR2CVzTkDaWPuOvVZnunE0ob6QwvKmIm6q/myrsa7qCip ZmcNqxskerCWcqETss8HlKwYY/ryLcmRLUXsbQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15248) `protect data_block lo2tFyFjziJNXhyZZC97XYl3f0ZrW0Q7WwUD9LVmJ9QBi2joO2dZ8TfhlWwhm39tu85pBzGhL0bU lLGx5TJC7bSGiCErXI+tXOdZbJN7BwD743jxvfTNU2raF5ycnehTY1hGqwT/pWpIC2JtRTQTyzBp jg0TCqLY1rtHmFowyZv6918XEG724JEsdzGw6PjyfRjRLZtokRZ+0zbRXq68SjqEoVWFXEf047xz U1lXxDoOT917H2vpfPYaJlAmCz0h8k1/fCal34SYbx73cHMUWFnCTybEbJmesL5gfaookMOfBxRk sWQIao+sOuGvP38D26sAUf3oTnFHhf4FeA0y0GfIpGs4c9o0m1EYVlZJolMEBOS91rz0jpo2qyO4 FotW+gt3+tARFTW3lkQliIHC7eWV+CzKIs05UnbWOX2SkiuLdqLxOSfvNuWxAtliF1fFNjG0J4e2 FfC9OGxbUUJo1RrpiOuacWpSLpdl4+QKPVWCQuyMstdh6mUS1MWuoq6F8/mRGq7yZL2pdZIpB7m1 FqTQVbrAzKa9Cqe54k3eQnNS00lwUaAnIU+CzSg7CoiosWSIBg71HYudiGoiBoBnZLEqIkt2ib0G YZPWoBJ4XLzNcluQ1Ajkwv/Xv7R2wBRSej0W3uwSBWm6fUAXxP2We4RT2a/8nGQcnRSmWtH6tvn1 toUbZDD8+Ooeq6eb0K8NO/8rJFhNJV7JNyQXElREEK63JtrgaSZcKCtnBW+wsroNhNIOskBUnQYV 0CCOIW97dIQavxtVUm8QElbLu5USzKEeLvh9GD+tbqC72nrYJbHQnB1ohbEHiElv0JwdtOtSflWL pytwBnhoxQ5UT0UDv+wUPioK6HKBPFktp1w2/8kV+msFfnPCYTZvAF2GVF73mpjIWNSQk99VZ/qf 9K6lAwSib3XEYyTtUO7OnwZNIJUwEDWugnn96iYwnYYes9kgSrOfR2iKOJcSmX2D1CE53neDgkVH xkC47PePhGeYQ+9CruOehZDBHHKc/Fx8iiqW1oWzim0a0wA8NBVV2OqueD1dwZX1CZsTEAO+2Mcf rJFOE7NbOnbN0WJ1EJ5BRuVz2S/x94hwZ8o4JmDKl5Pxa37bk/BXyfiPL6ngdHZz+s8AcqBsyTxu 25sSBxZaeLoumhdgEd1YTf2MrAQZF1LOmD7ZmxpQXxUqzDi0fCC9JKUEAusjFvHSE1xwVYpyGp4u JNI5GpLffojoQV8tfutFGd5oTy2RMT9ZAP6bmqaKWsy+rlq4PgDvJmiJxYPF+FxmKJy4Se7UTCQY 2tGopjkFaSVlGV15HPI95mnUmA4BX23/QHo7TwIzY1um4MKqhwtkxITazjhYc0NiEbzJcop6bimU 5Hd7Ad7cMRDj1a3Xo1DKie1GROb0LBMAKcfeNv2zhs1tkeLMXkNcvX+W8v63l3HmlbO7RZi15Cm/ 2BWj9XfFFMG99MOAbLXeMsJqC+dpxdTsOguJfZxshnmn34b5AcWmmOZRX9sgP8wpUknH+6V6v0GM M8HKbo+sm2eHaAl1FWozeJJQUvPa6Wc4rq7pSjwdGk5FV+syvS5mCsU1fEEac9pxRE2PbEr3vB2V DRnHV0llczoF8jgqeLDTmKG4oyKDJBnssnwbQCarP764MWnhOLRtJkEoKwN9+btcZ1VdJ1avFa94 J6sQAvRmJuUd70Mnii74Zk/EZfliu4yf5b41Xkp0j+lywStXrsAZDldoSf+yNBaEMrVsL3IBAJyL BOT1Rd4YxlmaqzqmbsQ5YRX4Ub5NyDh3sZ03W2HdiS0oJRlV45N5cK1OCkUQAY5cfVuPBGvt5GRA MlBA6ms8n2mGPaNAr3e1b7yydC71SvA2ReRI5Pd03Vz2SAqGhP/59Ge75gqaOW/G2IZoUC11UCDU 31QBFFxVvxTiuKYudkKmOFxFBtVpOVX5BR7/lN+BDExAVuiwAlh0Hu5VDxIm48y/OH9B/R5LdcxH Ekw8rrHH7EGDSZ9Fe373bH13i6PTtHSKCiscmJeqMg+iRxzvY+BYYAtvQxMeaM65oZeHO1cwWQAx ALVsCF6TftT/Rc9MlqkzPpIV2mJ55DHMAQWKWb8QkBjdcs/AB7cnCVg07jbNLP4Jy5RTGGXHwFPi MZhK6ZPQH+3FRieYtmnhUP7xTYheG0c8xaBl2Q5rzribOMk8lVx5rTzHrNPvYdjp66A593lzLTyd mzIocbG/auEuspS1QZ37zHsdA6+QMZzeVdz9hwhwNioBFtgScmQzWrGhF8ppCfURQNObhR+UQBk4 Mkpe9DtCAaggrUW4TaZ2P9ZWxLVzR7jpjApAJsYlqdHXGRaWPT0f7AbJhvzAPz9go8J4/wPMJWBA P8u7WpWVrvnCuVV5PCjsTYZ5eaTAG4JT+q9Roq18Gl60ZmctUFnPlsN2t8Iw2nY2ru895Etg/5MR Q5ic1xjhIY/r4T6qcoJurG+efqeTYn3BsbJIg3gg7va8t1gOGGJ5bTW7FEeibIl0IQPwmhiZXcaG ll+Rcykz2XZzDFCJm1kn2DSeQzDqXz+eaB4O/AG0iC8SJofVp2apAQ29vRIxo+URABT1X7EAk2YP XBZBSV6sg48AbgQSNOXltxjle3f9zd4+0jzoex3KqFIi5B6Jhz3AIemALfWqZnvhUsy3ZD+O65+L z7iRBMVTD+Pzs/xo255Mwm9jeu/MYWRlZ68lFOi3zSBcsBItIlO/PPOAzyOyIWhU6OxP/SJDjuhF mE9ensZ7JNQAbDlglmjZ5EnmdEmyMjtRpUlTxLYNlwZYtyHFPLS1XmiE4UoTB36ClKq1wMYEsT46 j6OXa7Ae6Sz1zjvBXSolixvc4Q46i3M5pJxpTFpU/6tMz7IXkQGWUF6BRt9T27SEIResbJQgKlVX K5pPzrUYjfeh9dwsNU6un5VQLsQtkGbYUdCGgwrglawDVwvo+7GCXnSpxpjPUCGKCnT2WyzBmfOW Pi4Yih/HToHDNUkNypdJEZJ78w27VFhc6XgQl266RK3GoXcRm/4sxYpLwyPaWDBzuSb7qFS7Kfac d7s+Sqss1A2KS0zvlTMBW6j5yXVsQJl7Jbjc+1MNHWfsn0q9rxLoze2HT/OXytLWmfeOtJiPRp8J IPylF2iey2lTQ0Il2bLWnN/Twl7v8RsHM5XyIJlJaqJ5nhekSeOURwG5TsyiIfDcKuc/Gzpe9xgz 5t7aiOCvjTs9UUbNZSIgXj4tdBatEeuAht4UJpVXkWheAgt5qasssjYGpMdom+S+NWms1aa4c7cU rdrz5h2spaEGbgSz61nGMAfONrXan/iojpkD2AAiB/Gb5qug/KrwLDvp6HwKlPWXrBqwHAyhTPEh +dk1VMcvLdYrbwtUyZVi7JiQbap0gpDxQtw1Ce2MOTVUzcUMu5c+XRYSTaCnwMDZVr9vQIAFIKOE jgJSLbzPtsdcy8Bu1LS7pFjY1eKlqWq1LcfhJDCyblf6cEESmsGivg4uVmK6gp8PsPDNWvUy9zM+ q2us3j7GC/daeIegUa4TzRNbtGrBG3yf3zJLs583MMAGQBbczPg9dtSfI/AlQX+5alVGtbNoXrls ER7y8p+bbYSX0Rsw+ytWm/JkeKmiNuviV+SCxQVwdx2Q8CC1he63DAx0GuGOulCUdXuVidVG+GWu EGOqTIyMBG6qTzvG9T2dhRbujJLP+bWec1FYWqjz+YEStYcm80SqY5ilecjQdxJeE7b1PmYgDxTm /iqg8EJewLrF2IeYECtFqYPf0gFAMuWifV4XiS0Abc+f6+B3tCMDwC1yfUgcekyCRIe5P4A0Sql5 /3KWdaeh3eVrZmlsOZrgibyGtY2VofAGToxxZgCP3SvOncAv259/SlswvHOHEHw17krFaMaqwCXt KaZCUgELk4LMZwxd9nJc0AHVMT8TY52JyAm6C6MtRsL45cs8fPbzN29yicUJDgELyqd5OtLx6SnI vwdBT0Vxgws/He+tfW8WXytpb6TQ1weCZBOAaQtwNfhSJcV/CrQ0LMaDsjCORTqgPHtlhrDi6Whe s8BwlZfMZK7DjdE7BpbMDXkpW7xvwxjRxqgMdNmwg95N3EvPbmV+mYCluh6wuXgbJ5rxsKJUtKvW p5aJrbnhIiCATUNOVAABcb2v/V0ZDNPEnIDNkgN9lVy4qYdEIuL9/nuDeik9+0O20VXyd+R8dQN5 a4++rqVcbFmQQfjkfaXX+kiYIlQMhsmz1edAXnOT+UNQH0oqO6GtlTyMRPucmatg8js/JS6PVW4U R8Sy0xjX0CmVYvXlvVbfhR07kQjXfznA67gEZblgvpXTRoHX7Sr7DUNE7QXg1g4jtXgjBvVsO9lQ nQTrR8HadMCgElnYWB1MUrtROAGZoTnBxfHfUHgsSDhj9Feh9Idtwbv4JImkI6DiBrpiG0LQsYwp OsqCIY63+3K69v8JsJqbjGRU34iQm/j6nP0J3YsZ5iyWetQcQ2TqQPzClr10sj5B/QgVQTyy++Hw +s5CDh6ocLBpj1KbPY7um/k56sK0aOwlgg0wSqi35Av5YM7C1+wwS5nCmnNItHXe+WslwIVX83hL 6MEJPXqYQCfS9Rg+mVvASxz/v3FDbVwVKljjkFeJ7oxg+ho3TI9+lNBhY/B7rkDeIdIFgZIU2tkw UeGXme8J3NK/c4gOPpwyfBIWcKDThmGa0d4Se8XxxBtQQYCs7oXYBucxlKVkr3k290pU26hnkyau ULF2ny043WWmhqXJWDvG90oDuOI3KJftR54o9hysqhRD5maT+w04buQrPqf/xgr/vwEAM4VYTE6Z /Q68yFUrPHd1Q9zfVU8ItZu6kvc/iJDBGxiY689Lk9EKs5MdBis+rbZgKtnHgKQbkk6P8hvQ+Hz3 QrSvi6c1abPqfQTFzOl78QvOtpAxQXG42aYe1cumjaTO+YwHHL1/OcrmNug2WDB22+B5yYspHMMr pghggC5YE14ZK6SLRRyznvi6/0j6JhUfVvgPAp/DWQkh0XCEcgptvAjjhDXqI/DV5vcxdpZui3xq DgaHNZnLlN+AiSwhiUvdqdcAgAgbqWcppIqvXreYG/5DLtlu2KYqyFHwzd1jufRuB79FslLk+8kc pE2+4rpbb5I7+T2BfGWB49MciXCEEmlXlHRbI1aj8FMCawqNYI+SaTxAW2Lpb44opWQqc6rMs2MB RtxcdjCq6WcCe/a67b2uEW+Bn9IgNF9c5/Xd5KsX/yzm+GRQv4s5TRgvGOd1PmDS5CXpmgPbNMh1 7maofr4z/xm46/gy1FX+/cZzX4z8B4HWNSq8ao+MokF+twMaXFVVOoh19LMZeHpeAy+yaNOMUlB4 ZHByjXkYxiPQUoEEi8ZxUkWNQEXBxfS6JnfMTM6PitDDiUaH4v5mG+cgP/GyMwlwSbCVuYtd+ZLj Z1Vo8jk1TbUy4YwVZN6YZ7k8H5+bnhOdSlYm5VsvX4R0RPPfDElc+ULn1p8VVbAP22fDB7vjpg+r Fw+xC6TL7NY/It4Pt/lGmgYLhdOBItWGqWEw9w5BtgvKWICb7oKpkt0OYoL8RpgVrDKL4TZFPHEx TF+QEEAWi/qBHtpFefgmlcpp0cOMv/1SyDx/YosFuPM2nmj/S1kIQ0nIphjSxRlgDnTVx8V34pk8 BfzcQQWpAKoKcp1Sq3ls5m3tm309Er2uvSnwkiR3Py6zHkT3w0Hi9++VsmPe0btjY/REO7oyFVg6 R95dXw3Yho+iq+RM9mchg4BHOre9/KJbc65qPF47mKBnO+PvAmU+hl5lsEamo1BPencnba/P8o0z SbZN1wcIzlnbS1+XYPPlZO+lCOWnVCXwBiMxPiNzAUKHUY/ch6KpYGM4y8DzbzeWJKbQqJUx6bGw Htq8GEioSyFGOgSLfAgprrgSfvBbNnr3o+2XEN9i06V4HOGGP51M0BuhOZxsXM7LC17T2bno2lxx g3MNBexWh1Il+f7p32f0p4zchekCfXuxi9ewbdnsdhoTZWGMx1SR50pKRuetNKn4lG/wCYuBtMvh eN5mHMzz9sNs6mExAUsCDuuZTKFm5ozosPvCWIhsviNFQ4fJnmOAIQCyuybW9MU5ua9T08mNXEEJ 6lGpuV7d6XTL6AEyHe7ZfR+GlGyHtWFmnmuNh8HgVvtx++CDnqP1/WhsvQ8bDSZuW3NviXmCzWw4 Gt2pKlFzptQIC6Zfl3RnuK2c94Manvfx8P/8eYsrotrR06wP5TPCdnELK/6Umb/fbqzERjSedVtH C/XNkMeW/0AbeuNKu30powhGQj5XDKwjoJRQNXdKllJRgkWHMdkyLwAMMh5XSq75MVUJ1jGvRFpV kPtMik/7OSZ9aV9QgtERkL4tQVIKznYjD6cNl74hKrilOaPTxC3MnGUwgWgaMnkDyTGPbgI7IoQb SmbhzcikqOd6IUbBprZvw6ayE0OvckZjRoOfficSz7j67b0DUGKTTV1nbVEp4Ob/tBPY6NJsjJKb z4sTlAm4ozcDYfpnhcmgAHuXvHiFFBkMBNZ3rjYT2cEriQ9TFLF3mizXSvt6Y9lGNjnsELiSVkPZ RFto74jJku8Hss6xrKO49xXr32YVTl7TgSZBYBEReZSDER0F/9Smcx6PxcaJbEbHcoIgaCinTWDr xbClLt//kAW0biTwE+PgAgoIYlf7HXMO0iCrf0mD/NlAKxr1hLVveiz6c4/fddjlT+7789I5+4wX uP1L854G79hcQIDuJUlxMBN20YgfOFUJtzkDPbG4Y93b46Rzs6fZn3Zp53ui5gkJRnKQIx6wllzZ KGRD0se9BG6W4fHDS85OKRa84HvXcWNex6fUE86DO4fF3z/VLNoalpz8xfHzl/1BbFMTWoxvBuex Ewmn6Z7qXBrsz6rp605BFeNwjhcEl5rbKnvtx38car/MBj+kpci2RmvwtfYvrnFnmonQVEhlqqtb izVSQZTvDvDylxyI6KejyO+ad+O7KhFt1ObvtioLPhjtD8o4wAKHpqAR2Hu4XrAlkqR3GgQi33AY efXDINfwKWhvU4CTCyYdxJoAZuCZJp3VYpqygSeZPSM5WeY2E5wcbvPG7jTqIlnJ7NPBPkYnpns9 giuPumUmUOOcVFAh+1CMZW/i314PWY6dqh3jiFAUTMd2pAQlhzp0COASBkI8yHscCuL9e76LrNEl phK0zem4ZXVqvQfeVpDjlV1sqjkZH1bX/jm/plr8dpen5FxOm090bHN1BTwSx3G/mdGH75jaC27s ceIOGoUwoN/jYig7YwIJchD8FpwjGlocKJDBXKwQcEkAFDczNefFi4ziWDNI3YZTq5+thfPxOEFj TGGLOA97s/C58H/TQ02vedrKqR+cTEiVINTohDV+noR/pHiUWOgPDa/QVi9UZh1pv/uISiZ1dRQu Nq2qa1skuihcQK01oxJjvzePeXBQZ2qTzuUpfd5EN2ZyRny5dHBXJVMGeIYHDtTdh8pGBwDlAxYl 0G1e3k6mxqAjAIbYKg/fX/tnFMNY8haPyljcp4x2gBI4a0AZa6JtZpg9UfSlBe+Kl6KF9L3xTYMg ova0I+v2YhQPCmumDF1d+iDw3Fqkk8UoOkhh8DPP3LKU2pZJTLBSe2V02otyUo/C24nSt6n7MfV9 tTTVIzTvDeaMXwCb9GZxY/SeIJPOdaKmsmD1fMSCCsnr9aNmX0Y5pNUJDyTIuNBZAqVg1e4N4/bg wI/4dmn2Je6ixx8VUYRktKUsL6H5wc8cK16cWLMq7/XpfvPWADFWRlKdxzO4cRhSiYOka0YTRX7M d+cF5YXSMaXGd2imY96irnT526iu2uUVhoEnfCtxxvPuRf4jP6dwQ/W3Dwl5mjf6YgVw9LEvQdGD OtNhvBnzj9oO5OmZNsPpZlnZAu+wCFCaZnEsoT/8zttWrCWQYVLlmCMDGZqkIyYOmKZWq/gccVvR A5doD934rvPOkUR52VfkpIap29Zb34WqexqRn/0IC/DsFN7H73s2bLdm5k4vIdOSUJPrVoOMlunH fEgOAXDejR1OA0srkMW6DirEbc6T+3BH4lBAh1VqdqsQEAaOJZg2uHj7x06rVH+ZKKlimvQKRYKN vvaH3/maL+3obAIoMsvRXtzFP3BVjPVSDWlrQngRtmjDMASn4pDgQPic9xmdGeLucC8wW/D7bQqG 3vFNQaWdOwNAEAJg1Fxdrw4+FoSZ1+tJuaem1QXlLZp2MWnmc2naNfy0+frSvhWZLnd5HTZdmjZ8 jmmFY+wYNqnivDXnBgXQt+lTaZxmbiTsBDYd1LxnrPzBdWSLsYIHwSc4qknEunO5DFFeU7J/gRBD oLvMA11R0nbZW8FqjRQegzJTfXB3hCElqcU63wMkM3BDPrFqSn9jMY8AtqyTZmtrXoXB/JgzhAlu RWpCGYM/yQU+VaODjSS6ahedrwnZfEucVY3S9uIJOiCZKDxQP6gvtJwHr+r9mj8muQoOva/k7shP kDDFoYx7yIzd/PX18UAnuQw0swQiWnFq3Ysamrz3cEb3w7KCWCE0miZadUqagWh4Ui1EoA4BtTCm XH+ULndTI8KXBTQtdiSaIelm8c4+Hsg0C9LoAmezce4IxO4XYdeG5mTOuyhdvbaf5aZPhYiHfCiI 5byWtx4XeofT5LYNa+4oJv6J/fs5re14ShP++4ZKMOnGmUcB0xqymmMzKZeFzu5qZK9C+EJniLlZ 8X3ypMzEUK9VjeCEvjNhAi3kE6NAMjguWHtVAoxGk0FI/+e6I/x0exhvmD6+PsENXHhXNgiGv006 kLSDnkx+6CJgztcEI4r3sXw3dTeiaYYzJhTJUw/z+GZmodZpeCbVrsAMv6bW62Ock5wdtXqJagLV VSPRSxklebpditAz2peVOrKx6ekkD3hlFH10CWt7N0b6mlRFpGzRIbArJnIkhZImFhfLHYxrdG+u Q5QWVQ/qK1qjjWUkpMLZn8KZpRWY6Iv6/OD7Ms/rIAfGwrG0WQEh2CoA5kH+kVtf/KjD0kUznGzs uiq3DYtmVnkzXkjgSTWONZIQMe4uUy1cDbwde97AS+8lFfBBUOrzGikwN3CnatU4RSReVfMfsmj/ PiUvI+VVIfB7fLmIYirpkTyJlLbNqgCbxTC3/YUKvQeKsgdPYRZ1AQ+X2EECrxumRyYdjdzdM266 q/ngQdXkaptEq+pWick9hXGMZv4EXwb/JiIrIW7ZzIyeRw/iWU9yREE99wH8dhvG7F8ZuJYODoZq Z16s7UDgdwZUz1WAASUCVAfQ3Dz4Ys/qpMTTBwP5weg2M2dpSnI7P61q/kp34JaDu+mDwNRk0OwM S3MjEJmn7M9bosNMEbdM33rNvuBPGrGvt+N2snTNy1pQCQVZhjxY2RTzluBYwLnmqOulukiROf2T lArRBTBcutYaPwNKiLDgtbC263UZD7nXmBMnFbxEdHQ1ciWmpHo0nZ8vvOpG870/W9B0bIU00Zf/ mcQGtsdoYUq4AKCGeYuT86AIsnm9QubUYTdvBvU3355svrEH+FrAn85xkA6Qj+KEgjcTOsEO2c5v a8QvtrsHm7QlyZz4nmX0z+c2xrfYF4NYwB1W5swgvEVPbo4m3MZ2Px6uQ4tZ7Jr+wdowt/fLBqCX uejBBNkZayRvIeXXegOy82MWj9Sj5U8GmR2j4Ufp5Tz5cl09egSavAg314dcMTUbqJ6jko/G/s0z hal9n1np6/6hYCO88KZOCHYsK3yBMSXLeTryLK5iIwAmSKbm9hltXEyqJiU/Ykw2gjkbjNYFYZyK OHlDaFUUF8Dhk5sLXXK0BwJjB+7JpKt9g99BATyq2YOzoXh8tzq/r3PIhNKefbBMhJPdvtA7oWKl 9BfWupKNcvAuMYMENnX6MVjyiMEoFSq8Q2c0/0cv5SidXn6pvp27hiMYAviHq0/ii9bYOBmwWQID rFWstI+te9vAVdgtKckvIK+bTRd+gYyq9379EVHT83riumNh79bKQg0kgGASNv1Uw7qIDGI8AYe4 3Cr2lbdTaIBcgw2Tvs6tCkZTOj4tbt90jk+jhkBt/kfzyHkFq/hU1/tPwEg+ei1zO65wpOl2J/Hj zqdIelYk+Q2gMDD4UO7B4QJrq2maRaOh3NAPNsNttqNh9PtnRIZSIhmd5DeNgbe4Q8JUB1BBA/Db JsHJ28cwqoLKRQSTa9PtlDgLzK/NKIuy41SAJ1FSZmQK+bUhGdPEwKMPlvNOF86H3w3FB91qra5r t13g66yCkK2nICykaW0+ctvVWO3DnQt5dQNlWp3TtwC+UU5R3WJ4y/KFK7Tc+hyB5J1440FQbJoA mpuZepfQ443UsJjyxTanoZhHKOD7Yvpu9CUn6Zp2ktivQoqNB5T+rqM1EgThdTTt98MM8DcwEg1L cszhN8IqINLpY4sFYtBhA2qTuoeWkr5RoLqT1hNi7H2xnoLA/L0wQHLjIKKqmRGyBX70bMIj9bsY ch3AzRyhbdYrUqvruR4h/V1egVCDHLMUhpxyGacBypyCswL6q5ji2LFtQ7nVCqHSOqJc5Npym9fM /UrTlm/16RpH/DuxDBck+pbAmHknMlME1lvMkvsxo8vMkwGvPuIKZr7n+S8Om+Vv9ne6FuIdbzgk iY/KzqzQBx92OXH0B5uSdtUeXsIalMo9BN3mNG9UXV5y5BJ3MOvtnBPeTkI/N08QG6YKJzUS/iWl 4W/9JSe6d9oYzuciEUrxzlxX3HUS160cyAQ+ODwTRnDtLi1U4hRgGFgIOg8BwEs2ilLtuXDxORKl bDSwNX4I/PW/qhR06nNwbRjyVfIi4VEn0ULSFm8XIPzEJ/t+xQsSK8cRx3XShqsDrberE4kcF6tg TsuJ8lO5r8rDwKCZOzPkOktohxlDzfICQphnJ5xRK6sehksPxetSeYsrGBplI0VPdhJLFAsnUFJd Ev6OqHdkRzMJ8+CdkuLN/snC4oRaUvANsK0doQmZ9+c2NoNuhNcVod8kKpw/3twWUJdfa0QIGJyX qzI+dQhuU3lWQBhEcJhG2DzZaUbDxrbX3YCGd+k1wavEf7VqLSwaTmmEwdZ7jtRmuK6HJ0rRISjP f4bD6ffOZjQ6jYL8ORBWeiI18SoNK6YO5RYGBfBdFqyxzJNmYSlofk85khFYSEtHVqecaPnuaHdV A6gZQC8sgAX1dfe/II0uTSstSA85bk+rpeDP4VHMB0X1lMFwrpVV9b7Y1Di/T0f7rQn2P/PPC8vQ 4JLGXzybsadQGJ3W0zxfq6PJLdRyCfJyHIttZEiARP7nqBDcTIyFCg+PvJcQZ768hNO8jAeI5jbd msSsFZC4D3N1YQDVZwj/7vmIilJ+i9qJnvUTwUBySXbq4FY1JyZSGjV2GWZ29ruIU3MwbAdW8m1S 8XTvHsbcxiaPOc/0ek7gt+0+b74qNTeX6VWf7fYDz0SZaKntTeuiDevjmzuF77fbaITL/5ISEq+I BtyvYS29P3b9B8LA9WC1N7tSTt6E0OIJxmwZlujkOJES9mM6Z+91WHY59qFKpa2siTL4jl/unDC3 uOuUsFOdpOp6OgWVfA4U88/JJrs3XraZDrp7DLnvDxEiss4+J8j9p0bw9hfz/ZPt9o/6Uv8h+z0P 0FRGjl6c7lSreB79+W0JPk5s5gfUN6tTwD98zYuEjyv0TIOWxsgQQOUE3DPnCEkTyCCwTqLktu3p ZbAGkWSivgpDi8580gURDEmQKDXhnks2yBDsXxiZx+N+UqfI8u1RYwL7sKZVDsjL+5mS9igixKJu mi6g1L08K6EDnZY73csqvUrwEVmlRdOTzVloSY+YdTJFeGdmKYyB1As6DDkFKmSB+eztHKVE6V7J bnAUyg8DRbGxU4KXgrC4UiJRgUaSYSVe8KHSshXafQ7DPFMKCB/GechX2JL7p8dmDbJWRYbq3c3D VMhRwP3vts5oXVTfCoNn4Ep3xMja6QsusMNZi1papKFd3yVv1l4skzpTWAg6o9EWYEnqzjznoUT1 HrfRKo7S2KqkgK1g14Ipvf5gs4HrxpzJEgZuUK8pGZH8jbP71j6nuOlCB0Hpr3ERm4DrKn3/DIFV mT8lJzUbiW+KEHjV0PjT9SLWH25lIbLWQIRxB9dSjAmOM9k0j1SHqlfPU5PX9UQi41XcoqWF1/bf HnAiHpCNxFAyWodIw9PzqVGZ03ei4Us0GAC4j0PZBcaZ0jZTD4SYgR1WAaom04ad5An2SupDMqD6 i/zj1uMkN1ftCXWyyAYzEknvYDhlGSGqD+pgEx8jyNJwbLN6dijDF8o4EwiSgu4rs3zkTetGVXbL ZZiW6gvzetc8r8CVSkDS990IslEBE7FEog6tPOs9nAysN4zANCHAB/syxXsIqyaqDLxj08oCHAN9 Ea0E1TcxVd4p5aMrsZtaPXUny0WsQcZmrVua+pUORYcdpMtEpDhvNun7+d7Yexd7yMiL1GUXbGBn 55J7dkquCalG/Xmy9e4QOaxqOqW+fLjL9VWuDLKU9I4iXyc7CFC1H+GtUT/gMBymfmMxz/Q98/Yn inr8+5CbwWjD7si0setE2IM+NeUnQa/gtS4vfFkIdPi00vXllAM6pSC6/0QeBaWa3+r1czPVFObj PWH7rYqR1ooR25vC9ZbZT403w7uhulpM0H08ajEmWIAkOGsH5pQS088ug2MLhd/hO26L4IydGeo6 3NJdiNd2TsdbmuJoUSGGh8mJf7yFL20HUgmUQDeoEGFqgtWO9hcieiUbBjhXP6almms3b+QF7EB+ V36WocNhOtAOiQMUjP7amBx6BWL80y7ZG0C5mf8ceE1zlOP6JSqIKZ2W2ctmKMKCzQDQGvCAR697 3oxFl7KClk72SSKOq15uzytrapXDRz5aKpyyrxpphsZ65VzcLdqV6Dojj5fnaE4u7A9xRt46mmNI R3KCXahZ0diUKnV5O3bZX7GFF5iaaJHwiBCwxadX6E52fTHqJ9yr291p4tG0pUlhCni+Y4O37EEq fwWvrSrkv3NqI+z2V3Ifl7Zh1oY3E5v+/mO05jsJmthiTfptmfo4jfUKFl5vHlQUIKwDvAGQUvAg syriuscwJEXegC6+8l5wdH8flHjlXHsQa8+uBEqX7KqZ9C6wQSIvc4OmKI7Vz6KBtqEuFqTb5dHq /as5/RH/jGlNFwZjxlQZuD71nrhq4+Oz/jZbm1LpWZ5NXkc1Om9bx18JGA+1sYR1xe5R1zs/eay9 yQETW4yLT5sKie3PwxLcmjPq5ttZ540kwE4y/K8ZEX0dCsJvwBDTPvftVJVws32pLrhd6lavVuIV c5F/9O9wt3B4X1NWTlchrQwc9yKzvp5L5o1kr6Lg5IQe1eBkFQZX66eSgK5cWPkdqyq4yMniZEZ8 oYrcPivSsc4lOI7GEYsE8wLnE9clMOPlm9nriJxTDZ2i7/HmnL1Q0IiPMmg9kdgtz3VlAuMQN9RN R1iS9ykHnegJPyKBWmIO/K/BrHJen7afnI62YQbUp0Fr6IcNROoqq0bsYmSBruT3W75JIG0Cc174 /PyIiLpmjWhJ7sl+686Ml3/vhYFFD5jlDOQ8DLKpSmaMscH50ZsQihpoKJhP1JNtd9JrOd4SdQ+I px6bNnblous1n5h522nqwM6XosLtL/G87CJ/bOSeIdbixbyZHxJXOIxNuLdRQPb4QrqiDHXMQeah eWPEMuQpf6dnYjM1KnkKjxh/CxJtCRmkUjJe8WqDLzpdI6l/+L0JhoDyQuH/9S+V3bgmBC1C/tRk n6xVuQr19CtS+Xg8oQP9zBFToFMk0fN88FqXnqAkJ8BOu18iSPMpTTNWAs6kNUw84Po/gZ+fcy4X wB8bdIiQEAAztvib1K/zwMw+cMVzX195FEMZAJ617/s7L5wRqluMeECknM0HC9AsZb08tQ7q0FBH vl61Hyap/2Vjte/O/g8RlkXO6FICuys6T+qFHYHwrNzhUtaMXqkdGddnHVh/E343B0WBE9GXpeR7 lGji7OfIToIlLxunpXzjw57MBUgjLBCzZPsPSJSa4io30B0kMP+PCx+qFp//LncbGBwtgPWkAgHL IsQhLL/xfkZh/36LEGgpPNlnS4ETUoifcxEVusUOVrwv3/tleOCN1JMljt99t2sXt4GRoGCvQZaO NrVh3sd2KrXhII0gfcLdpbryzJwaZ80HMG8KCqLC3Ga0yT/FPdDa/eOJJ8KL7fQtaDwXSCL9cOhM Pe7qiIINL27Mim7MzaFHp5qUtpYlVv/Ex8bJ9zNFYLn0uO7H2Sn5JOuwuqmGkR2SNCz6Fupox8/z D8LVeAe26qFrZOsLD59zLdgbLl3asB1h8osvKcLkvCQCSXQjhQntaj3PjjbVBNWrOLztNATp3Env v0FW90WhtZiU9R0xHi1sqsHDYZ35slEh9gKRRyw9tKM9OLvY0Wg4XNA+mhDsls1SiQbQOqC9i+3X IxgawQKwDnEkrbn+DXTaV2CTV8ak6V9WIDsfw8rqGcrGaII+sQhmbbfZAvM1+uWubre3kQlezwuK PoVfogigSpV0tNW6S2/LnMr7OOLeHvpFV2ikQWTbx9oirYNSEPJbWoomWNdL8HgkwDoHyknAsPxN j+YV8KYlzrLNeOQqfh/dZ1RhZbz0DJMx6mPpZSv3wxe/cnCuLOq/t625aVMNRyuqV4nkGpV3bEKb Sq5w/UAdn289Ylqbk9amvEHPGi3JViwXmlml23kzleLaClulOSgtec660aGPQ+NkmvpfRKoQfS/Z jVqqGAIy+pKJbg1ijmXawOzL2MWbm9g1Cc0wUsDxw1SYbxQ8ZR7HaqEyPcCy+fJi512Ts0OLt5qe hnkaR6rzQ610uluGwmmaqnNe/JpmSETIqGhAZYlkGJgYqLau80r9i3vhe8k0QMKSaOnaLsiieYHs bR1H0Go+tU/Um5zKqEtjIUYxEFeFmLiPdU6qFVy1VqDviqJnMgToA/u4jaqI4/WkPz7i5Jwg5/M4 x8MIXD+CMxg4sM/KbEfro9Xcc9ysF5OStAOT3zn3Gs7dZkLSuboaLGS+QWJrsVH7jmxlxyQddLE1 ZuFeh6ItwlGKXuitv5MkMxWnZEOLwNPIHF9CfqES3PX8Mu4nHsdRb+xeNrbTC9mYEMvxQgMLtR8D UjQlZm9qIBKCdU1Qx+ssRmtB7hB6HpTDFkCXj7fw5EhPX/TWHxqRYe6TMnj2HlBZVK2FNWIwmoD1 z2kUSyWa2h/aKvRs9G+nWyPmT0j3dRuZqMkZBAsJuJp0iGYVKPICWos7uo4TYNqm0rrcN3UAhljZ WGlcu1o5LpU/rnRV0wzS2X+YMTxz0Giaz9gpJ/sqOdgBiuFYXJDckfQnKeOdLesW5Hhil6CCc1Uh PZ+acLCcStjGwBl9sxyAdpiJZGhoSZ0LyUTT+x2sWKi14HJ8c0pIAMvwq60AEthGSTnAXDu8y2+t 7WyNiUepk3gURbhqidaE/Pu3frJMq5BwZaFbR70Mj20NE7pA5Sg+BxQsaysUV/Grmfc6iap/u07k hQ0d58AwvkMOCUCRuVpGUzfEY7jAUB8logHqIYRt/Gg3y0TCL2GKpRYcBw/cXruXF4PsqphMbz9S EetAjixDXFHFuIwiRAeTjSQu70P6HOMpsfpe08dQVthvCCy+PudKH59SdelBTsNBPVcmyIumGsLb p3Tr6N9UjYyY90j4y+cAMp+4RmTgEegTSMeUbpbVeNYUI7Wu0H7RcjrVDrWSxtY6UPQ/Dx1hn8qj 5fAdd5SBIUcGlrHxWNN9a32r3ZZZEOsNVfCCYmVv+iAMDe0oNAodyu7w/q/qcwppLWxXUAMEhqSv vt75VzFD6UTBN6Gpl0xlB6ofPSHMtOTyMry+w3kvzLxLczALwH5vuuQScuo7eMKgVJ97jh/NbD5r 5mWWFGiiYGToHBdP0Yp76oOepOPjDn97NxkHvVoXYZY09wHSD67M7DoZ6mFay9tgR1MjVJ/07MrJ Gqfz5hsG/96fNz6NVX1sGtS4n/YCo+e5vOdb2lL9yfknjD5VeFRXw74rt2rZRVT4OGEKPY+z//f5 MErU7acWK7pqGvN10o4KvM2y7GPDIOdszj3V+5zGxaRsbenLDNz/YtPWlkVihCzomhhBXLtGRH5Z JIHrEch2Qq+V+cI65CSviLaYXN7wqiicv7a5JPIQbol/4EPgN4OFCYQx7GwDmjp8rX8jBjtws6fe y12wpztmaykpcO2/b5mJ+bm9tNHw+Z/vekRgHoQEBAAIaCdQWjCjxstRIm4LHDbTKa3gsUGCoSg2 Tbw/UUgoj+fFcKvzt4bjxU+RWbQ+f78UGB7OUEDSVYLkqHAfolUvw5rpm6Bw8FF2HsrtR378Iv0h J2pm/4MwDHnAxQVkpg/MDCQI5JVCaO8px+xlGOMtGC7/BMrIxTjYRqo9LpFGIlOwScNgfpBrvjAF 3yqFFXduKrWYOOTsTHz7o8jBXyo5MP9YEw0IiUsmX0Ykj+sSswtoOk3arr11bzp/SNylQ75n2S+t mSAvjUlBJW7JuAwA218g14d1KrExYh1l9OEOgcmp95E2XKHXZhmRgr+2+EYAvsMiLWwm8kIl41lt CGDTL5/3CqDKnHHzc9p858NOue+6MTuwSopBPSkq9Ita1y9kgJxrnJgafEl9BX3l4sBZFafEBDWh epXRZ0iTEE8b4dzZ2WnR+yF7sV56SvH/HVsJxHUGj+zvukJmGva8H5aEy8l4jveswxKcSi43vpPl rwLz6soAsP3MixinEYYI8v1A8JGWpttM+VzOMr+zkvLlCyk40XcWFzFjoKrW2dUgB0CaP+aq43jS yWTW75ZxP50PQBEVXeHGy78vMDCIZLPimV143fxuqyrO5X8utlxdTB8FDRds6fGAyxDcMyheh1tN jbaF6wMhWnEYH2zSkI3bG6VsUgLxEb8Vs4jXmF4C+cuuflN7r//s+jYo06cDgpOgqM53SmH9MIlw AYOYD3WJ13Nwr5+6Hb/ZyRksdUe9B1A6Aru73cRGAS0GDocaLdJVVtnqpqoq9jPi2ZzvlUDVJL2s BPS9o7k+dVVldul/SsgANNDzUm0Y8A/EuepyJEYnPZskvkY2kabzB0PR4OGwgpnmAkeXMX+YWAzj lJqDmsv2U5SyB8lx6NOOUKLTUiF0lgGRK7mg4YATGiLsCGuxeomuFVjC3oZzPFpx2ZTKeVNMyE/J VsfU4zQPsCpOYUrbxffaRilHAB6mm9kBpplbasLi68vkkXj+U7cyx2GRBT78H1iH5erJ4L6Io6sV FdjdPw9oOsGREAwYnhl49HB+rAKU3Ja0rLFRz0b+TiF6JjVQHosDcAIJ0BInTbxunV5DazDH+J9P QzmyGbzIyqpd0SFjlJzlvQ26OO1NW+W5q1yWN1bgXOivwqYXWGdLRqrze3QyjcT593wqN/Lf5FoU nS1xpsXAzeKlwCW5Tc38ArA7SsYn3BTRFc8Oyb/Wzm9tLCo/wJHDyn9DMTf/kn3TxBfQ7BSDfqmM Jg8x8ZVbJ8gTC6Wy7oabBzL34r2tznrdsgm4PNgTlJEajPkkdhzhecxD4aGpRo0qRQRrfTud7Mze V49P8U9kC8zzF3mSFQEN45MghlyzJS/w6oMZhzdtvH0MMkLmm6J55jQrjD/MmOpoMG6m6o9S7bgZ zLGok/elhTN0YwpezWoJ8s4XKgvpp9z5s5CH1AH+4M/La2tWKpGjn+6fgaIqQfVLqSetEMayZL5W g4x8+tLc/wKBoX2LVdScspDi89PBIxPHEj8XVVjnpwFQ2ORwc54wYlRYvMlhnNfMk6QmKZyDsb04 cLNCOgE8cCEU/NXXrmFoCj5BV59wYehYjW5rJb7dY6cNdG27z7m/gsKakAy+MsZkBcxY20ta8ujf 5PoJG6Ih28Zezexk4VfWoybDX6/Hi8k9kUVOHNFNhoqsHvv5kna0B70fctkMW/PEGsemkKX7VlQu ZP9243QAJSAesf1tiZIqUpwx3627F+HhAPGipKuBelFtdRXNcESyUBoZrPuF9C4QLjmUOise0g8k QLSwOKKDl+3LuhacLJUhLjLZhcm0WSe9BFx8iM0WxsRxEo39N/BAtAvdYt208h3w8AerunI+sCR1 ByJ+GV+eG3UCZjgcR+9/VozqwcBCZG72hPRCrf7pQxVwpqrTtHc36XVh4/xmtcceVhtsMPcVx/F+ PK0x06AeV7lK5kCUl2nfMSo/mr/+auY4FjNIRCa8yRfQPWTsOCdVC3cg0fLoAe/Fv3L5Vg+RImnQ YbEw8V8C4mXdZGpMbDS96EKSshF8yfCtsnxpuNmDR10S0VtePcn0zDrmum7uQH6TN4e7ficj01wU 8jL/vhOsGloFgPeJ2T2beG/LK3fXd4XIHAX88udns2ReMK7JONlH/4qwXxl5FKrMwzQy3bLwGgq4 m2ZUcUClHuAuMBFzCa2PCNCohOzTomBJVd+uFTPzW4ibW8rK3EhVDAgBFw6sJLTCYSYHO86d83zj souvG7MPaMSsGShxZ5FyQXGBmVfPD2CqZALYHqNqZENf07cH5sfE4L8L4+7O6sUcrb+Npb0LsWkE aewWKCLi4QElc+zRvASHrXDYv2bvzMc8lOk9fnThaqdFxjTMTiVr8BugLRnBSECgWUIsGwdnKF5R ADrDY8/8FFuiFvsw4liqb6FQdHROoUfVX6gVQmJNANCZcGttmn61FtAiAHWT6smZeC0RepcxyubY RJzldA8EUPuHQweNwtPqEFCUbLTvZMzmSs+ToHvnOy7U99iJogm130ZiiGLzEgKKPeSruhv4xHVV pK9SoEaXneexYJPF/Dxr5QGXK51vpobQeN+aSTEs3aEmnZbAwMtNfTP6bbibpJA/ZtL81rJCv6da A7rQ+/OsOA0VMvGCc3gpDWJDfoEs6fhivba+/06Z8SCaQIXCdS0Q1RiVcHw+UA5aLwMCJ0yFNb84 prxwUw7Hx/3YTuO/rlVxEYjAuz8WSCLSndjntzgGDfu0FJDvl03VUlx05elYViplu0Dzx0wQ+ffT BKDasDJlMt3ap8NZ5dsHGwXAc6MUM8btAYaoCOssIo96rOawxBHVnr+rqcBC3GVnnYJaPQqcVvY5 hsagQGLmqUma8Z048eCjiCPKdVPPZon6SfgMTOapvXaVP5eFRaWok8YDZIeQCPcJ7vNX6ib5cRXA oueUZzdXkljsGnm9SjTKFjoJf935JUt9vBvdzpCjZeSdMkUfvpAtHAiovo0K3mKb3ouOV7xYcRzR gBrQEqrC5PZjKcT44mSG6oDZNABCJ0JbEgvXJV2d4SzdMOdCoKLV53TArZCM1mY1fm4UtE4glFLa jtau4K5M7dwFZMiR9aePZPUUcEcxcbQL8mAwNrI4qklp1utJUh5BMatlsPLWFoURCxMmMpe8spNZ xdCtMpFccKC0dTz0eawQZyLIbM9SYj+Y+dMXrNhYndaw8SFOgZedp/W1EiIxHfnFhNip06mSqx+l Or8npo/OuOPJnY23NCx42e0aSQy3JEET6QmwDKo2PF7CadsQ4oUd5BWCRG7CK7gMMskUHIiIPYnO rtws9MrlEHxdAas4XjbT1WMwxJemYUqcl2ZjyzBmrm5cDPyeCiFNHeSrzQRulRomXnYoUf3XfcIY zBrmmGowEKsmSkuAwLy6PVsZN68uYw7TUP9Zh8Zl6t8o17YDwBLjN8jJNNTcYGvaR58E05M7PJrK 9rXQJzJZYmdKTc7cxuhL8HF7wtxFkyYqPKwD90tGfD26CViakChuKY59zAUPciUW8j3EMXo4cMEi xHWFFgXrw7EgzwSE7pQLFyk1njycQ688CuARfqwMwbsS4HG3Me6sIRAtHjZ1PVhoNcP6LMWIrU6t GffBsYylgoPbTfe8O6tTYu6oTo7RvdiW0tViu1XkihwTKJjtCgHDeVSgeVdbNPUafJMXiDmKT5YC 4c+Ih7u18V6qBar3pRkseN+F6//AYskUxAeYpUuwh9ifxbXfk1Rs/vcte3mc6TX+9ZfD/hbZivwJ cgySx0mpnPLaEWkAjLwCW2mehGmOZVJxucW2pgg5nBojO+m2/+WAG++EQ26eoLuZLqEMsSoboe4e hyztGjnTu5vHVtOHT0YMFXx8lHrOz21k1kWG/sSlnju0eaKFKZjWPoELxhfi/dq00xdvdhuGR1jY uJ1P2Gh+CCgRXy044opH95iRsHfO+dIscQoQ/mCA7SczM5lAtfjuEeXXVSQ/XsgK1n9aeBtOHbso 99R2WajBIGUeMypniu3VKUOfQjuPCapEaksz6Fq9148tokw1YE+HHP9/mi+W+J33QNNol19fG0vQ Cq8G5oVVxfFqMozcuwvKLeLCTYrwptE+WBeZgoSY2pWLjLbw0EXyTXhm7TA70LXNo09EV41UpjNt Jts6yCKP3q9XgSeafukZYENWE4aP/35k0cP7ALY= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block TRcoZtqjn2mG6m34VrAup3Ue3mXUdsp9Svi1yOdUyuJ18aNmZzMqBL74/JYXAGMp7kyUseTthYI3 PrI0QWq4hg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block FPMMqj9RaKUiXlcYwEXFaXQj6iTZvDXB3ovRbqMXkBKErB6okVtT7N25cw0P4DrPAX3uTf1/DjZP g9FGVgqB8LxAQapqrXO27frLQX/jtpP5BRN/3UyLQQ5tmeo2wvGsRYc6Ptmw5XXPXjfubR1uMIvq n/KnJrhMohYd24Nm6S0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block hmQ19Z9b511LayHM++uE0XsD77aCTvi2D5+tVo/slhNcSgfFOCWou7QB72DRXWqLm1hI0yRUpD++ 6M4B9gDAGymLNt4kJfLjIH35OM6bL+USAdP5LzqI73Y5A9Ex2dA7XXtW38Kapk4g+yOtlcspGQ3v mipApCouubIDIKzAKfit6i+3D5zl06BKC5+/oMSR90fI/572drXx35dvozy88MbJh8nfL5OjT9y6 tufG7IpOsbuhtIaWR26UAUyCxZ5GOOwUvB2fS9q4Es/JzlrcdmqBkwl4ixHzLmdkNChDQXjCJVtg DP9+/cLV+QeiYTROca+/iv6JtjPVTSGXYAp7KA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KGFNy15frm7DKeh26HgilQgudk+s92inzv6E6/4SwA14yIblinRVK3XaIL/wyVEMSS/Nvx17YpaU YVWGfrmqIII72ql+J97vctL8UoKOHRk+u89CmFhhNIsJnQoGfxdh8DOXKgydwIo8DtyknF+rigwD Wrn0cHGnf+DzHJ1IlOw= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block IRcwaJ9nbddmu/9RW2bhH0oH/sFHVn1S2tsx6hwo1+XOm3bHWHP+ulk+4hbdqZE1Olkl9QC1qtoY ePy+TB2nSwbY99tK/zHUTTzEr9V7pe7cC+aCydi5fu9j5sMPnFmsQadzUgekG4OiSkic9/qlG8tY Nia8+0GODU2GsN9eE2823xR9kslK5c5LHAFyOnzohuZuaNQpgH9FgGbNWtWQ6Q+SNaCkDDwUMJRB XMWJMBZ7ADG8CfZuEbYaJpB3sP361wZWR2CVzTkDaWPuOvVZnunE0ob6QwvKmIm6q/myrsa7qCip ZmcNqxskerCWcqETss8HlKwYY/ryLcmRLUXsbQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15248) `protect data_block lo2tFyFjziJNXhyZZC97XYl3f0ZrW0Q7WwUD9LVmJ9QBi2joO2dZ8TfhlWwhm39tu85pBzGhL0bU lLGx5TJC7bSGiCErXI+tXOdZbJN7BwD743jxvfTNU2raF5ycnehTY1hGqwT/pWpIC2JtRTQTyzBp jg0TCqLY1rtHmFowyZv6918XEG724JEsdzGw6PjyfRjRLZtokRZ+0zbRXq68SjqEoVWFXEf047xz U1lXxDoOT917H2vpfPYaJlAmCz0h8k1/fCal34SYbx73cHMUWFnCTybEbJmesL5gfaookMOfBxRk sWQIao+sOuGvP38D26sAUf3oTnFHhf4FeA0y0GfIpGs4c9o0m1EYVlZJolMEBOS91rz0jpo2qyO4 FotW+gt3+tARFTW3lkQliIHC7eWV+CzKIs05UnbWOX2SkiuLdqLxOSfvNuWxAtliF1fFNjG0J4e2 FfC9OGxbUUJo1RrpiOuacWpSLpdl4+QKPVWCQuyMstdh6mUS1MWuoq6F8/mRGq7yZL2pdZIpB7m1 FqTQVbrAzKa9Cqe54k3eQnNS00lwUaAnIU+CzSg7CoiosWSIBg71HYudiGoiBoBnZLEqIkt2ib0G YZPWoBJ4XLzNcluQ1Ajkwv/Xv7R2wBRSej0W3uwSBWm6fUAXxP2We4RT2a/8nGQcnRSmWtH6tvn1 toUbZDD8+Ooeq6eb0K8NO/8rJFhNJV7JNyQXElREEK63JtrgaSZcKCtnBW+wsroNhNIOskBUnQYV 0CCOIW97dIQavxtVUm8QElbLu5USzKEeLvh9GD+tbqC72nrYJbHQnB1ohbEHiElv0JwdtOtSflWL pytwBnhoxQ5UT0UDv+wUPioK6HKBPFktp1w2/8kV+msFfnPCYTZvAF2GVF73mpjIWNSQk99VZ/qf 9K6lAwSib3XEYyTtUO7OnwZNIJUwEDWugnn96iYwnYYes9kgSrOfR2iKOJcSmX2D1CE53neDgkVH xkC47PePhGeYQ+9CruOehZDBHHKc/Fx8iiqW1oWzim0a0wA8NBVV2OqueD1dwZX1CZsTEAO+2Mcf rJFOE7NbOnbN0WJ1EJ5BRuVz2S/x94hwZ8o4JmDKl5Pxa37bk/BXyfiPL6ngdHZz+s8AcqBsyTxu 25sSBxZaeLoumhdgEd1YTf2MrAQZF1LOmD7ZmxpQXxUqzDi0fCC9JKUEAusjFvHSE1xwVYpyGp4u JNI5GpLffojoQV8tfutFGd5oTy2RMT9ZAP6bmqaKWsy+rlq4PgDvJmiJxYPF+FxmKJy4Se7UTCQY 2tGopjkFaSVlGV15HPI95mnUmA4BX23/QHo7TwIzY1um4MKqhwtkxITazjhYc0NiEbzJcop6bimU 5Hd7Ad7cMRDj1a3Xo1DKie1GROb0LBMAKcfeNv2zhs1tkeLMXkNcvX+W8v63l3HmlbO7RZi15Cm/ 2BWj9XfFFMG99MOAbLXeMsJqC+dpxdTsOguJfZxshnmn34b5AcWmmOZRX9sgP8wpUknH+6V6v0GM M8HKbo+sm2eHaAl1FWozeJJQUvPa6Wc4rq7pSjwdGk5FV+syvS5mCsU1fEEac9pxRE2PbEr3vB2V DRnHV0llczoF8jgqeLDTmKG4oyKDJBnssnwbQCarP764MWnhOLRtJkEoKwN9+btcZ1VdJ1avFa94 J6sQAvRmJuUd70Mnii74Zk/EZfliu4yf5b41Xkp0j+lywStXrsAZDldoSf+yNBaEMrVsL3IBAJyL BOT1Rd4YxlmaqzqmbsQ5YRX4Ub5NyDh3sZ03W2HdiS0oJRlV45N5cK1OCkUQAY5cfVuPBGvt5GRA MlBA6ms8n2mGPaNAr3e1b7yydC71SvA2ReRI5Pd03Vz2SAqGhP/59Ge75gqaOW/G2IZoUC11UCDU 31QBFFxVvxTiuKYudkKmOFxFBtVpOVX5BR7/lN+BDExAVuiwAlh0Hu5VDxIm48y/OH9B/R5LdcxH Ekw8rrHH7EGDSZ9Fe373bH13i6PTtHSKCiscmJeqMg+iRxzvY+BYYAtvQxMeaM65oZeHO1cwWQAx ALVsCF6TftT/Rc9MlqkzPpIV2mJ55DHMAQWKWb8QkBjdcs/AB7cnCVg07jbNLP4Jy5RTGGXHwFPi MZhK6ZPQH+3FRieYtmnhUP7xTYheG0c8xaBl2Q5rzribOMk8lVx5rTzHrNPvYdjp66A593lzLTyd mzIocbG/auEuspS1QZ37zHsdA6+QMZzeVdz9hwhwNioBFtgScmQzWrGhF8ppCfURQNObhR+UQBk4 Mkpe9DtCAaggrUW4TaZ2P9ZWxLVzR7jpjApAJsYlqdHXGRaWPT0f7AbJhvzAPz9go8J4/wPMJWBA P8u7WpWVrvnCuVV5PCjsTYZ5eaTAG4JT+q9Roq18Gl60ZmctUFnPlsN2t8Iw2nY2ru895Etg/5MR Q5ic1xjhIY/r4T6qcoJurG+efqeTYn3BsbJIg3gg7va8t1gOGGJ5bTW7FEeibIl0IQPwmhiZXcaG ll+Rcykz2XZzDFCJm1kn2DSeQzDqXz+eaB4O/AG0iC8SJofVp2apAQ29vRIxo+URABT1X7EAk2YP XBZBSV6sg48AbgQSNOXltxjle3f9zd4+0jzoex3KqFIi5B6Jhz3AIemALfWqZnvhUsy3ZD+O65+L z7iRBMVTD+Pzs/xo255Mwm9jeu/MYWRlZ68lFOi3zSBcsBItIlO/PPOAzyOyIWhU6OxP/SJDjuhF mE9ensZ7JNQAbDlglmjZ5EnmdEmyMjtRpUlTxLYNlwZYtyHFPLS1XmiE4UoTB36ClKq1wMYEsT46 j6OXa7Ae6Sz1zjvBXSolixvc4Q46i3M5pJxpTFpU/6tMz7IXkQGWUF6BRt9T27SEIResbJQgKlVX K5pPzrUYjfeh9dwsNU6un5VQLsQtkGbYUdCGgwrglawDVwvo+7GCXnSpxpjPUCGKCnT2WyzBmfOW Pi4Yih/HToHDNUkNypdJEZJ78w27VFhc6XgQl266RK3GoXcRm/4sxYpLwyPaWDBzuSb7qFS7Kfac d7s+Sqss1A2KS0zvlTMBW6j5yXVsQJl7Jbjc+1MNHWfsn0q9rxLoze2HT/OXytLWmfeOtJiPRp8J IPylF2iey2lTQ0Il2bLWnN/Twl7v8RsHM5XyIJlJaqJ5nhekSeOURwG5TsyiIfDcKuc/Gzpe9xgz 5t7aiOCvjTs9UUbNZSIgXj4tdBatEeuAht4UJpVXkWheAgt5qasssjYGpMdom+S+NWms1aa4c7cU rdrz5h2spaEGbgSz61nGMAfONrXan/iojpkD2AAiB/Gb5qug/KrwLDvp6HwKlPWXrBqwHAyhTPEh +dk1VMcvLdYrbwtUyZVi7JiQbap0gpDxQtw1Ce2MOTVUzcUMu5c+XRYSTaCnwMDZVr9vQIAFIKOE jgJSLbzPtsdcy8Bu1LS7pFjY1eKlqWq1LcfhJDCyblf6cEESmsGivg4uVmK6gp8PsPDNWvUy9zM+ q2us3j7GC/daeIegUa4TzRNbtGrBG3yf3zJLs583MMAGQBbczPg9dtSfI/AlQX+5alVGtbNoXrls ER7y8p+bbYSX0Rsw+ytWm/JkeKmiNuviV+SCxQVwdx2Q8CC1he63DAx0GuGOulCUdXuVidVG+GWu EGOqTIyMBG6qTzvG9T2dhRbujJLP+bWec1FYWqjz+YEStYcm80SqY5ilecjQdxJeE7b1PmYgDxTm /iqg8EJewLrF2IeYECtFqYPf0gFAMuWifV4XiS0Abc+f6+B3tCMDwC1yfUgcekyCRIe5P4A0Sql5 /3KWdaeh3eVrZmlsOZrgibyGtY2VofAGToxxZgCP3SvOncAv259/SlswvHOHEHw17krFaMaqwCXt KaZCUgELk4LMZwxd9nJc0AHVMT8TY52JyAm6C6MtRsL45cs8fPbzN29yicUJDgELyqd5OtLx6SnI vwdBT0Vxgws/He+tfW8WXytpb6TQ1weCZBOAaQtwNfhSJcV/CrQ0LMaDsjCORTqgPHtlhrDi6Whe s8BwlZfMZK7DjdE7BpbMDXkpW7xvwxjRxqgMdNmwg95N3EvPbmV+mYCluh6wuXgbJ5rxsKJUtKvW p5aJrbnhIiCATUNOVAABcb2v/V0ZDNPEnIDNkgN9lVy4qYdEIuL9/nuDeik9+0O20VXyd+R8dQN5 a4++rqVcbFmQQfjkfaXX+kiYIlQMhsmz1edAXnOT+UNQH0oqO6GtlTyMRPucmatg8js/JS6PVW4U R8Sy0xjX0CmVYvXlvVbfhR07kQjXfznA67gEZblgvpXTRoHX7Sr7DUNE7QXg1g4jtXgjBvVsO9lQ nQTrR8HadMCgElnYWB1MUrtROAGZoTnBxfHfUHgsSDhj9Feh9Idtwbv4JImkI6DiBrpiG0LQsYwp OsqCIY63+3K69v8JsJqbjGRU34iQm/j6nP0J3YsZ5iyWetQcQ2TqQPzClr10sj5B/QgVQTyy++Hw +s5CDh6ocLBpj1KbPY7um/k56sK0aOwlgg0wSqi35Av5YM7C1+wwS5nCmnNItHXe+WslwIVX83hL 6MEJPXqYQCfS9Rg+mVvASxz/v3FDbVwVKljjkFeJ7oxg+ho3TI9+lNBhY/B7rkDeIdIFgZIU2tkw UeGXme8J3NK/c4gOPpwyfBIWcKDThmGa0d4Se8XxxBtQQYCs7oXYBucxlKVkr3k290pU26hnkyau ULF2ny043WWmhqXJWDvG90oDuOI3KJftR54o9hysqhRD5maT+w04buQrPqf/xgr/vwEAM4VYTE6Z /Q68yFUrPHd1Q9zfVU8ItZu6kvc/iJDBGxiY689Lk9EKs5MdBis+rbZgKtnHgKQbkk6P8hvQ+Hz3 QrSvi6c1abPqfQTFzOl78QvOtpAxQXG42aYe1cumjaTO+YwHHL1/OcrmNug2WDB22+B5yYspHMMr pghggC5YE14ZK6SLRRyznvi6/0j6JhUfVvgPAp/DWQkh0XCEcgptvAjjhDXqI/DV5vcxdpZui3xq DgaHNZnLlN+AiSwhiUvdqdcAgAgbqWcppIqvXreYG/5DLtlu2KYqyFHwzd1jufRuB79FslLk+8kc pE2+4rpbb5I7+T2BfGWB49MciXCEEmlXlHRbI1aj8FMCawqNYI+SaTxAW2Lpb44opWQqc6rMs2MB RtxcdjCq6WcCe/a67b2uEW+Bn9IgNF9c5/Xd5KsX/yzm+GRQv4s5TRgvGOd1PmDS5CXpmgPbNMh1 7maofr4z/xm46/gy1FX+/cZzX4z8B4HWNSq8ao+MokF+twMaXFVVOoh19LMZeHpeAy+yaNOMUlB4 ZHByjXkYxiPQUoEEi8ZxUkWNQEXBxfS6JnfMTM6PitDDiUaH4v5mG+cgP/GyMwlwSbCVuYtd+ZLj Z1Vo8jk1TbUy4YwVZN6YZ7k8H5+bnhOdSlYm5VsvX4R0RPPfDElc+ULn1p8VVbAP22fDB7vjpg+r Fw+xC6TL7NY/It4Pt/lGmgYLhdOBItWGqWEw9w5BtgvKWICb7oKpkt0OYoL8RpgVrDKL4TZFPHEx TF+QEEAWi/qBHtpFefgmlcpp0cOMv/1SyDx/YosFuPM2nmj/S1kIQ0nIphjSxRlgDnTVx8V34pk8 BfzcQQWpAKoKcp1Sq3ls5m3tm309Er2uvSnwkiR3Py6zHkT3w0Hi9++VsmPe0btjY/REO7oyFVg6 R95dXw3Yho+iq+RM9mchg4BHOre9/KJbc65qPF47mKBnO+PvAmU+hl5lsEamo1BPencnba/P8o0z SbZN1wcIzlnbS1+XYPPlZO+lCOWnVCXwBiMxPiNzAUKHUY/ch6KpYGM4y8DzbzeWJKbQqJUx6bGw Htq8GEioSyFGOgSLfAgprrgSfvBbNnr3o+2XEN9i06V4HOGGP51M0BuhOZxsXM7LC17T2bno2lxx g3MNBexWh1Il+f7p32f0p4zchekCfXuxi9ewbdnsdhoTZWGMx1SR50pKRuetNKn4lG/wCYuBtMvh eN5mHMzz9sNs6mExAUsCDuuZTKFm5ozosPvCWIhsviNFQ4fJnmOAIQCyuybW9MU5ua9T08mNXEEJ 6lGpuV7d6XTL6AEyHe7ZfR+GlGyHtWFmnmuNh8HgVvtx++CDnqP1/WhsvQ8bDSZuW3NviXmCzWw4 Gt2pKlFzptQIC6Zfl3RnuK2c94Manvfx8P/8eYsrotrR06wP5TPCdnELK/6Umb/fbqzERjSedVtH C/XNkMeW/0AbeuNKu30powhGQj5XDKwjoJRQNXdKllJRgkWHMdkyLwAMMh5XSq75MVUJ1jGvRFpV kPtMik/7OSZ9aV9QgtERkL4tQVIKznYjD6cNl74hKrilOaPTxC3MnGUwgWgaMnkDyTGPbgI7IoQb SmbhzcikqOd6IUbBprZvw6ayE0OvckZjRoOfficSz7j67b0DUGKTTV1nbVEp4Ob/tBPY6NJsjJKb z4sTlAm4ozcDYfpnhcmgAHuXvHiFFBkMBNZ3rjYT2cEriQ9TFLF3mizXSvt6Y9lGNjnsELiSVkPZ RFto74jJku8Hss6xrKO49xXr32YVTl7TgSZBYBEReZSDER0F/9Smcx6PxcaJbEbHcoIgaCinTWDr xbClLt//kAW0biTwE+PgAgoIYlf7HXMO0iCrf0mD/NlAKxr1hLVveiz6c4/fddjlT+7789I5+4wX uP1L854G79hcQIDuJUlxMBN20YgfOFUJtzkDPbG4Y93b46Rzs6fZn3Zp53ui5gkJRnKQIx6wllzZ KGRD0se9BG6W4fHDS85OKRa84HvXcWNex6fUE86DO4fF3z/VLNoalpz8xfHzl/1BbFMTWoxvBuex Ewmn6Z7qXBrsz6rp605BFeNwjhcEl5rbKnvtx38car/MBj+kpci2RmvwtfYvrnFnmonQVEhlqqtb izVSQZTvDvDylxyI6KejyO+ad+O7KhFt1ObvtioLPhjtD8o4wAKHpqAR2Hu4XrAlkqR3GgQi33AY efXDINfwKWhvU4CTCyYdxJoAZuCZJp3VYpqygSeZPSM5WeY2E5wcbvPG7jTqIlnJ7NPBPkYnpns9 giuPumUmUOOcVFAh+1CMZW/i314PWY6dqh3jiFAUTMd2pAQlhzp0COASBkI8yHscCuL9e76LrNEl phK0zem4ZXVqvQfeVpDjlV1sqjkZH1bX/jm/plr8dpen5FxOm090bHN1BTwSx3G/mdGH75jaC27s ceIOGoUwoN/jYig7YwIJchD8FpwjGlocKJDBXKwQcEkAFDczNefFi4ziWDNI3YZTq5+thfPxOEFj TGGLOA97s/C58H/TQ02vedrKqR+cTEiVINTohDV+noR/pHiUWOgPDa/QVi9UZh1pv/uISiZ1dRQu Nq2qa1skuihcQK01oxJjvzePeXBQZ2qTzuUpfd5EN2ZyRny5dHBXJVMGeIYHDtTdh8pGBwDlAxYl 0G1e3k6mxqAjAIbYKg/fX/tnFMNY8haPyljcp4x2gBI4a0AZa6JtZpg9UfSlBe+Kl6KF9L3xTYMg ova0I+v2YhQPCmumDF1d+iDw3Fqkk8UoOkhh8DPP3LKU2pZJTLBSe2V02otyUo/C24nSt6n7MfV9 tTTVIzTvDeaMXwCb9GZxY/SeIJPOdaKmsmD1fMSCCsnr9aNmX0Y5pNUJDyTIuNBZAqVg1e4N4/bg wI/4dmn2Je6ixx8VUYRktKUsL6H5wc8cK16cWLMq7/XpfvPWADFWRlKdxzO4cRhSiYOka0YTRX7M d+cF5YXSMaXGd2imY96irnT526iu2uUVhoEnfCtxxvPuRf4jP6dwQ/W3Dwl5mjf6YgVw9LEvQdGD OtNhvBnzj9oO5OmZNsPpZlnZAu+wCFCaZnEsoT/8zttWrCWQYVLlmCMDGZqkIyYOmKZWq/gccVvR A5doD934rvPOkUR52VfkpIap29Zb34WqexqRn/0IC/DsFN7H73s2bLdm5k4vIdOSUJPrVoOMlunH fEgOAXDejR1OA0srkMW6DirEbc6T+3BH4lBAh1VqdqsQEAaOJZg2uHj7x06rVH+ZKKlimvQKRYKN vvaH3/maL+3obAIoMsvRXtzFP3BVjPVSDWlrQngRtmjDMASn4pDgQPic9xmdGeLucC8wW/D7bQqG 3vFNQaWdOwNAEAJg1Fxdrw4+FoSZ1+tJuaem1QXlLZp2MWnmc2naNfy0+frSvhWZLnd5HTZdmjZ8 jmmFY+wYNqnivDXnBgXQt+lTaZxmbiTsBDYd1LxnrPzBdWSLsYIHwSc4qknEunO5DFFeU7J/gRBD oLvMA11R0nbZW8FqjRQegzJTfXB3hCElqcU63wMkM3BDPrFqSn9jMY8AtqyTZmtrXoXB/JgzhAlu RWpCGYM/yQU+VaODjSS6ahedrwnZfEucVY3S9uIJOiCZKDxQP6gvtJwHr+r9mj8muQoOva/k7shP kDDFoYx7yIzd/PX18UAnuQw0swQiWnFq3Ysamrz3cEb3w7KCWCE0miZadUqagWh4Ui1EoA4BtTCm XH+ULndTI8KXBTQtdiSaIelm8c4+Hsg0C9LoAmezce4IxO4XYdeG5mTOuyhdvbaf5aZPhYiHfCiI 5byWtx4XeofT5LYNa+4oJv6J/fs5re14ShP++4ZKMOnGmUcB0xqymmMzKZeFzu5qZK9C+EJniLlZ 8X3ypMzEUK9VjeCEvjNhAi3kE6NAMjguWHtVAoxGk0FI/+e6I/x0exhvmD6+PsENXHhXNgiGv006 kLSDnkx+6CJgztcEI4r3sXw3dTeiaYYzJhTJUw/z+GZmodZpeCbVrsAMv6bW62Ock5wdtXqJagLV VSPRSxklebpditAz2peVOrKx6ekkD3hlFH10CWt7N0b6mlRFpGzRIbArJnIkhZImFhfLHYxrdG+u Q5QWVQ/qK1qjjWUkpMLZn8KZpRWY6Iv6/OD7Ms/rIAfGwrG0WQEh2CoA5kH+kVtf/KjD0kUznGzs uiq3DYtmVnkzXkjgSTWONZIQMe4uUy1cDbwde97AS+8lFfBBUOrzGikwN3CnatU4RSReVfMfsmj/ PiUvI+VVIfB7fLmIYirpkTyJlLbNqgCbxTC3/YUKvQeKsgdPYRZ1AQ+X2EECrxumRyYdjdzdM266 q/ngQdXkaptEq+pWick9hXGMZv4EXwb/JiIrIW7ZzIyeRw/iWU9yREE99wH8dhvG7F8ZuJYODoZq Z16s7UDgdwZUz1WAASUCVAfQ3Dz4Ys/qpMTTBwP5weg2M2dpSnI7P61q/kp34JaDu+mDwNRk0OwM S3MjEJmn7M9bosNMEbdM33rNvuBPGrGvt+N2snTNy1pQCQVZhjxY2RTzluBYwLnmqOulukiROf2T lArRBTBcutYaPwNKiLDgtbC263UZD7nXmBMnFbxEdHQ1ciWmpHo0nZ8vvOpG870/W9B0bIU00Zf/ mcQGtsdoYUq4AKCGeYuT86AIsnm9QubUYTdvBvU3355svrEH+FrAn85xkA6Qj+KEgjcTOsEO2c5v a8QvtrsHm7QlyZz4nmX0z+c2xrfYF4NYwB1W5swgvEVPbo4m3MZ2Px6uQ4tZ7Jr+wdowt/fLBqCX uejBBNkZayRvIeXXegOy82MWj9Sj5U8GmR2j4Ufp5Tz5cl09egSavAg314dcMTUbqJ6jko/G/s0z hal9n1np6/6hYCO88KZOCHYsK3yBMSXLeTryLK5iIwAmSKbm9hltXEyqJiU/Ykw2gjkbjNYFYZyK OHlDaFUUF8Dhk5sLXXK0BwJjB+7JpKt9g99BATyq2YOzoXh8tzq/r3PIhNKefbBMhJPdvtA7oWKl 9BfWupKNcvAuMYMENnX6MVjyiMEoFSq8Q2c0/0cv5SidXn6pvp27hiMYAviHq0/ii9bYOBmwWQID rFWstI+te9vAVdgtKckvIK+bTRd+gYyq9379EVHT83riumNh79bKQg0kgGASNv1Uw7qIDGI8AYe4 3Cr2lbdTaIBcgw2Tvs6tCkZTOj4tbt90jk+jhkBt/kfzyHkFq/hU1/tPwEg+ei1zO65wpOl2J/Hj zqdIelYk+Q2gMDD4UO7B4QJrq2maRaOh3NAPNsNttqNh9PtnRIZSIhmd5DeNgbe4Q8JUB1BBA/Db JsHJ28cwqoLKRQSTa9PtlDgLzK/NKIuy41SAJ1FSZmQK+bUhGdPEwKMPlvNOF86H3w3FB91qra5r t13g66yCkK2nICykaW0+ctvVWO3DnQt5dQNlWp3TtwC+UU5R3WJ4y/KFK7Tc+hyB5J1440FQbJoA mpuZepfQ443UsJjyxTanoZhHKOD7Yvpu9CUn6Zp2ktivQoqNB5T+rqM1EgThdTTt98MM8DcwEg1L cszhN8IqINLpY4sFYtBhA2qTuoeWkr5RoLqT1hNi7H2xnoLA/L0wQHLjIKKqmRGyBX70bMIj9bsY ch3AzRyhbdYrUqvruR4h/V1egVCDHLMUhpxyGacBypyCswL6q5ji2LFtQ7nVCqHSOqJc5Npym9fM /UrTlm/16RpH/DuxDBck+pbAmHknMlME1lvMkvsxo8vMkwGvPuIKZr7n+S8Om+Vv9ne6FuIdbzgk iY/KzqzQBx92OXH0B5uSdtUeXsIalMo9BN3mNG9UXV5y5BJ3MOvtnBPeTkI/N08QG6YKJzUS/iWl 4W/9JSe6d9oYzuciEUrxzlxX3HUS160cyAQ+ODwTRnDtLi1U4hRgGFgIOg8BwEs2ilLtuXDxORKl bDSwNX4I/PW/qhR06nNwbRjyVfIi4VEn0ULSFm8XIPzEJ/t+xQsSK8cRx3XShqsDrberE4kcF6tg TsuJ8lO5r8rDwKCZOzPkOktohxlDzfICQphnJ5xRK6sehksPxetSeYsrGBplI0VPdhJLFAsnUFJd Ev6OqHdkRzMJ8+CdkuLN/snC4oRaUvANsK0doQmZ9+c2NoNuhNcVod8kKpw/3twWUJdfa0QIGJyX qzI+dQhuU3lWQBhEcJhG2DzZaUbDxrbX3YCGd+k1wavEf7VqLSwaTmmEwdZ7jtRmuK6HJ0rRISjP f4bD6ffOZjQ6jYL8ORBWeiI18SoNK6YO5RYGBfBdFqyxzJNmYSlofk85khFYSEtHVqecaPnuaHdV A6gZQC8sgAX1dfe/II0uTSstSA85bk+rpeDP4VHMB0X1lMFwrpVV9b7Y1Di/T0f7rQn2P/PPC8vQ 4JLGXzybsadQGJ3W0zxfq6PJLdRyCfJyHIttZEiARP7nqBDcTIyFCg+PvJcQZ768hNO8jAeI5jbd msSsFZC4D3N1YQDVZwj/7vmIilJ+i9qJnvUTwUBySXbq4FY1JyZSGjV2GWZ29ruIU3MwbAdW8m1S 8XTvHsbcxiaPOc/0ek7gt+0+b74qNTeX6VWf7fYDz0SZaKntTeuiDevjmzuF77fbaITL/5ISEq+I BtyvYS29P3b9B8LA9WC1N7tSTt6E0OIJxmwZlujkOJES9mM6Z+91WHY59qFKpa2siTL4jl/unDC3 uOuUsFOdpOp6OgWVfA4U88/JJrs3XraZDrp7DLnvDxEiss4+J8j9p0bw9hfz/ZPt9o/6Uv8h+z0P 0FRGjl6c7lSreB79+W0JPk5s5gfUN6tTwD98zYuEjyv0TIOWxsgQQOUE3DPnCEkTyCCwTqLktu3p ZbAGkWSivgpDi8580gURDEmQKDXhnks2yBDsXxiZx+N+UqfI8u1RYwL7sKZVDsjL+5mS9igixKJu mi6g1L08K6EDnZY73csqvUrwEVmlRdOTzVloSY+YdTJFeGdmKYyB1As6DDkFKmSB+eztHKVE6V7J bnAUyg8DRbGxU4KXgrC4UiJRgUaSYSVe8KHSshXafQ7DPFMKCB/GechX2JL7p8dmDbJWRYbq3c3D VMhRwP3vts5oXVTfCoNn4Ep3xMja6QsusMNZi1papKFd3yVv1l4skzpTWAg6o9EWYEnqzjznoUT1 HrfRKo7S2KqkgK1g14Ipvf5gs4HrxpzJEgZuUK8pGZH8jbP71j6nuOlCB0Hpr3ERm4DrKn3/DIFV mT8lJzUbiW+KEHjV0PjT9SLWH25lIbLWQIRxB9dSjAmOM9k0j1SHqlfPU5PX9UQi41XcoqWF1/bf HnAiHpCNxFAyWodIw9PzqVGZ03ei4Us0GAC4j0PZBcaZ0jZTD4SYgR1WAaom04ad5An2SupDMqD6 i/zj1uMkN1ftCXWyyAYzEknvYDhlGSGqD+pgEx8jyNJwbLN6dijDF8o4EwiSgu4rs3zkTetGVXbL ZZiW6gvzetc8r8CVSkDS990IslEBE7FEog6tPOs9nAysN4zANCHAB/syxXsIqyaqDLxj08oCHAN9 Ea0E1TcxVd4p5aMrsZtaPXUny0WsQcZmrVua+pUORYcdpMtEpDhvNun7+d7Yexd7yMiL1GUXbGBn 55J7dkquCalG/Xmy9e4QOaxqOqW+fLjL9VWuDLKU9I4iXyc7CFC1H+GtUT/gMBymfmMxz/Q98/Yn inr8+5CbwWjD7si0setE2IM+NeUnQa/gtS4vfFkIdPi00vXllAM6pSC6/0QeBaWa3+r1czPVFObj PWH7rYqR1ooR25vC9ZbZT403w7uhulpM0H08ajEmWIAkOGsH5pQS088ug2MLhd/hO26L4IydGeo6 3NJdiNd2TsdbmuJoUSGGh8mJf7yFL20HUgmUQDeoEGFqgtWO9hcieiUbBjhXP6almms3b+QF7EB+ V36WocNhOtAOiQMUjP7amBx6BWL80y7ZG0C5mf8ceE1zlOP6JSqIKZ2W2ctmKMKCzQDQGvCAR697 3oxFl7KClk72SSKOq15uzytrapXDRz5aKpyyrxpphsZ65VzcLdqV6Dojj5fnaE4u7A9xRt46mmNI R3KCXahZ0diUKnV5O3bZX7GFF5iaaJHwiBCwxadX6E52fTHqJ9yr291p4tG0pUlhCni+Y4O37EEq fwWvrSrkv3NqI+z2V3Ifl7Zh1oY3E5v+/mO05jsJmthiTfptmfo4jfUKFl5vHlQUIKwDvAGQUvAg syriuscwJEXegC6+8l5wdH8flHjlXHsQa8+uBEqX7KqZ9C6wQSIvc4OmKI7Vz6KBtqEuFqTb5dHq /as5/RH/jGlNFwZjxlQZuD71nrhq4+Oz/jZbm1LpWZ5NXkc1Om9bx18JGA+1sYR1xe5R1zs/eay9 yQETW4yLT5sKie3PwxLcmjPq5ttZ540kwE4y/K8ZEX0dCsJvwBDTPvftVJVws32pLrhd6lavVuIV c5F/9O9wt3B4X1NWTlchrQwc9yKzvp5L5o1kr6Lg5IQe1eBkFQZX66eSgK5cWPkdqyq4yMniZEZ8 oYrcPivSsc4lOI7GEYsE8wLnE9clMOPlm9nriJxTDZ2i7/HmnL1Q0IiPMmg9kdgtz3VlAuMQN9RN R1iS9ykHnegJPyKBWmIO/K/BrHJen7afnI62YQbUp0Fr6IcNROoqq0bsYmSBruT3W75JIG0Cc174 /PyIiLpmjWhJ7sl+686Ml3/vhYFFD5jlDOQ8DLKpSmaMscH50ZsQihpoKJhP1JNtd9JrOd4SdQ+I px6bNnblous1n5h522nqwM6XosLtL/G87CJ/bOSeIdbixbyZHxJXOIxNuLdRQPb4QrqiDHXMQeah eWPEMuQpf6dnYjM1KnkKjxh/CxJtCRmkUjJe8WqDLzpdI6l/+L0JhoDyQuH/9S+V3bgmBC1C/tRk n6xVuQr19CtS+Xg8oQP9zBFToFMk0fN88FqXnqAkJ8BOu18iSPMpTTNWAs6kNUw84Po/gZ+fcy4X wB8bdIiQEAAztvib1K/zwMw+cMVzX195FEMZAJ617/s7L5wRqluMeECknM0HC9AsZb08tQ7q0FBH vl61Hyap/2Vjte/O/g8RlkXO6FICuys6T+qFHYHwrNzhUtaMXqkdGddnHVh/E343B0WBE9GXpeR7 lGji7OfIToIlLxunpXzjw57MBUgjLBCzZPsPSJSa4io30B0kMP+PCx+qFp//LncbGBwtgPWkAgHL IsQhLL/xfkZh/36LEGgpPNlnS4ETUoifcxEVusUOVrwv3/tleOCN1JMljt99t2sXt4GRoGCvQZaO NrVh3sd2KrXhII0gfcLdpbryzJwaZ80HMG8KCqLC3Ga0yT/FPdDa/eOJJ8KL7fQtaDwXSCL9cOhM Pe7qiIINL27Mim7MzaFHp5qUtpYlVv/Ex8bJ9zNFYLn0uO7H2Sn5JOuwuqmGkR2SNCz6Fupox8/z D8LVeAe26qFrZOsLD59zLdgbLl3asB1h8osvKcLkvCQCSXQjhQntaj3PjjbVBNWrOLztNATp3Env v0FW90WhtZiU9R0xHi1sqsHDYZ35slEh9gKRRyw9tKM9OLvY0Wg4XNA+mhDsls1SiQbQOqC9i+3X IxgawQKwDnEkrbn+DXTaV2CTV8ak6V9WIDsfw8rqGcrGaII+sQhmbbfZAvM1+uWubre3kQlezwuK PoVfogigSpV0tNW6S2/LnMr7OOLeHvpFV2ikQWTbx9oirYNSEPJbWoomWNdL8HgkwDoHyknAsPxN j+YV8KYlzrLNeOQqfh/dZ1RhZbz0DJMx6mPpZSv3wxe/cnCuLOq/t625aVMNRyuqV4nkGpV3bEKb Sq5w/UAdn289Ylqbk9amvEHPGi3JViwXmlml23kzleLaClulOSgtec660aGPQ+NkmvpfRKoQfS/Z jVqqGAIy+pKJbg1ijmXawOzL2MWbm9g1Cc0wUsDxw1SYbxQ8ZR7HaqEyPcCy+fJi512Ts0OLt5qe hnkaR6rzQ610uluGwmmaqnNe/JpmSETIqGhAZYlkGJgYqLau80r9i3vhe8k0QMKSaOnaLsiieYHs bR1H0Go+tU/Um5zKqEtjIUYxEFeFmLiPdU6qFVy1VqDviqJnMgToA/u4jaqI4/WkPz7i5Jwg5/M4 x8MIXD+CMxg4sM/KbEfro9Xcc9ysF5OStAOT3zn3Gs7dZkLSuboaLGS+QWJrsVH7jmxlxyQddLE1 ZuFeh6ItwlGKXuitv5MkMxWnZEOLwNPIHF9CfqES3PX8Mu4nHsdRb+xeNrbTC9mYEMvxQgMLtR8D UjQlZm9qIBKCdU1Qx+ssRmtB7hB6HpTDFkCXj7fw5EhPX/TWHxqRYe6TMnj2HlBZVK2FNWIwmoD1 z2kUSyWa2h/aKvRs9G+nWyPmT0j3dRuZqMkZBAsJuJp0iGYVKPICWos7uo4TYNqm0rrcN3UAhljZ WGlcu1o5LpU/rnRV0wzS2X+YMTxz0Giaz9gpJ/sqOdgBiuFYXJDckfQnKeOdLesW5Hhil6CCc1Uh PZ+acLCcStjGwBl9sxyAdpiJZGhoSZ0LyUTT+x2sWKi14HJ8c0pIAMvwq60AEthGSTnAXDu8y2+t 7WyNiUepk3gURbhqidaE/Pu3frJMq5BwZaFbR70Mj20NE7pA5Sg+BxQsaysUV/Grmfc6iap/u07k hQ0d58AwvkMOCUCRuVpGUzfEY7jAUB8logHqIYRt/Gg3y0TCL2GKpRYcBw/cXruXF4PsqphMbz9S EetAjixDXFHFuIwiRAeTjSQu70P6HOMpsfpe08dQVthvCCy+PudKH59SdelBTsNBPVcmyIumGsLb p3Tr6N9UjYyY90j4y+cAMp+4RmTgEegTSMeUbpbVeNYUI7Wu0H7RcjrVDrWSxtY6UPQ/Dx1hn8qj 5fAdd5SBIUcGlrHxWNN9a32r3ZZZEOsNVfCCYmVv+iAMDe0oNAodyu7w/q/qcwppLWxXUAMEhqSv vt75VzFD6UTBN6Gpl0xlB6ofPSHMtOTyMry+w3kvzLxLczALwH5vuuQScuo7eMKgVJ97jh/NbD5r 5mWWFGiiYGToHBdP0Yp76oOepOPjDn97NxkHvVoXYZY09wHSD67M7DoZ6mFay9tgR1MjVJ/07MrJ Gqfz5hsG/96fNz6NVX1sGtS4n/YCo+e5vOdb2lL9yfknjD5VeFRXw74rt2rZRVT4OGEKPY+z//f5 MErU7acWK7pqGvN10o4KvM2y7GPDIOdszj3V+5zGxaRsbenLDNz/YtPWlkVihCzomhhBXLtGRH5Z JIHrEch2Qq+V+cI65CSviLaYXN7wqiicv7a5JPIQbol/4EPgN4OFCYQx7GwDmjp8rX8jBjtws6fe y12wpztmaykpcO2/b5mJ+bm9tNHw+Z/vekRgHoQEBAAIaCdQWjCjxstRIm4LHDbTKa3gsUGCoSg2 Tbw/UUgoj+fFcKvzt4bjxU+RWbQ+f78UGB7OUEDSVYLkqHAfolUvw5rpm6Bw8FF2HsrtR378Iv0h J2pm/4MwDHnAxQVkpg/MDCQI5JVCaO8px+xlGOMtGC7/BMrIxTjYRqo9LpFGIlOwScNgfpBrvjAF 3yqFFXduKrWYOOTsTHz7o8jBXyo5MP9YEw0IiUsmX0Ykj+sSswtoOk3arr11bzp/SNylQ75n2S+t mSAvjUlBJW7JuAwA218g14d1KrExYh1l9OEOgcmp95E2XKHXZhmRgr+2+EYAvsMiLWwm8kIl41lt CGDTL5/3CqDKnHHzc9p858NOue+6MTuwSopBPSkq9Ita1y9kgJxrnJgafEl9BX3l4sBZFafEBDWh epXRZ0iTEE8b4dzZ2WnR+yF7sV56SvH/HVsJxHUGj+zvukJmGva8H5aEy8l4jveswxKcSi43vpPl rwLz6soAsP3MixinEYYI8v1A8JGWpttM+VzOMr+zkvLlCyk40XcWFzFjoKrW2dUgB0CaP+aq43jS yWTW75ZxP50PQBEVXeHGy78vMDCIZLPimV143fxuqyrO5X8utlxdTB8FDRds6fGAyxDcMyheh1tN jbaF6wMhWnEYH2zSkI3bG6VsUgLxEb8Vs4jXmF4C+cuuflN7r//s+jYo06cDgpOgqM53SmH9MIlw AYOYD3WJ13Nwr5+6Hb/ZyRksdUe9B1A6Aru73cRGAS0GDocaLdJVVtnqpqoq9jPi2ZzvlUDVJL2s BPS9o7k+dVVldul/SsgANNDzUm0Y8A/EuepyJEYnPZskvkY2kabzB0PR4OGwgpnmAkeXMX+YWAzj lJqDmsv2U5SyB8lx6NOOUKLTUiF0lgGRK7mg4YATGiLsCGuxeomuFVjC3oZzPFpx2ZTKeVNMyE/J VsfU4zQPsCpOYUrbxffaRilHAB6mm9kBpplbasLi68vkkXj+U7cyx2GRBT78H1iH5erJ4L6Io6sV FdjdPw9oOsGREAwYnhl49HB+rAKU3Ja0rLFRz0b+TiF6JjVQHosDcAIJ0BInTbxunV5DazDH+J9P QzmyGbzIyqpd0SFjlJzlvQ26OO1NW+W5q1yWN1bgXOivwqYXWGdLRqrze3QyjcT593wqN/Lf5FoU nS1xpsXAzeKlwCW5Tc38ArA7SsYn3BTRFc8Oyb/Wzm9tLCo/wJHDyn9DMTf/kn3TxBfQ7BSDfqmM Jg8x8ZVbJ8gTC6Wy7oabBzL34r2tznrdsgm4PNgTlJEajPkkdhzhecxD4aGpRo0qRQRrfTud7Mze V49P8U9kC8zzF3mSFQEN45MghlyzJS/w6oMZhzdtvH0MMkLmm6J55jQrjD/MmOpoMG6m6o9S7bgZ zLGok/elhTN0YwpezWoJ8s4XKgvpp9z5s5CH1AH+4M/La2tWKpGjn+6fgaIqQfVLqSetEMayZL5W g4x8+tLc/wKBoX2LVdScspDi89PBIxPHEj8XVVjnpwFQ2ORwc54wYlRYvMlhnNfMk6QmKZyDsb04 cLNCOgE8cCEU/NXXrmFoCj5BV59wYehYjW5rJb7dY6cNdG27z7m/gsKakAy+MsZkBcxY20ta8ujf 5PoJG6Ih28Zezexk4VfWoybDX6/Hi8k9kUVOHNFNhoqsHvv5kna0B70fctkMW/PEGsemkKX7VlQu ZP9243QAJSAesf1tiZIqUpwx3627F+HhAPGipKuBelFtdRXNcESyUBoZrPuF9C4QLjmUOise0g8k QLSwOKKDl+3LuhacLJUhLjLZhcm0WSe9BFx8iM0WxsRxEo39N/BAtAvdYt208h3w8AerunI+sCR1 ByJ+GV+eG3UCZjgcR+9/VozqwcBCZG72hPRCrf7pQxVwpqrTtHc36XVh4/xmtcceVhtsMPcVx/F+ PK0x06AeV7lK5kCUl2nfMSo/mr/+auY4FjNIRCa8yRfQPWTsOCdVC3cg0fLoAe/Fv3L5Vg+RImnQ YbEw8V8C4mXdZGpMbDS96EKSshF8yfCtsnxpuNmDR10S0VtePcn0zDrmum7uQH6TN4e7ficj01wU 8jL/vhOsGloFgPeJ2T2beG/LK3fXd4XIHAX88udns2ReMK7JONlH/4qwXxl5FKrMwzQy3bLwGgq4 m2ZUcUClHuAuMBFzCa2PCNCohOzTomBJVd+uFTPzW4ibW8rK3EhVDAgBFw6sJLTCYSYHO86d83zj souvG7MPaMSsGShxZ5FyQXGBmVfPD2CqZALYHqNqZENf07cH5sfE4L8L4+7O6sUcrb+Npb0LsWkE aewWKCLi4QElc+zRvASHrXDYv2bvzMc8lOk9fnThaqdFxjTMTiVr8BugLRnBSECgWUIsGwdnKF5R ADrDY8/8FFuiFvsw4liqb6FQdHROoUfVX6gVQmJNANCZcGttmn61FtAiAHWT6smZeC0RepcxyubY RJzldA8EUPuHQweNwtPqEFCUbLTvZMzmSs+ToHvnOy7U99iJogm130ZiiGLzEgKKPeSruhv4xHVV pK9SoEaXneexYJPF/Dxr5QGXK51vpobQeN+aSTEs3aEmnZbAwMtNfTP6bbibpJA/ZtL81rJCv6da A7rQ+/OsOA0VMvGCc3gpDWJDfoEs6fhivba+/06Z8SCaQIXCdS0Q1RiVcHw+UA5aLwMCJ0yFNb84 prxwUw7Hx/3YTuO/rlVxEYjAuz8WSCLSndjntzgGDfu0FJDvl03VUlx05elYViplu0Dzx0wQ+ffT BKDasDJlMt3ap8NZ5dsHGwXAc6MUM8btAYaoCOssIo96rOawxBHVnr+rqcBC3GVnnYJaPQqcVvY5 hsagQGLmqUma8Z048eCjiCPKdVPPZon6SfgMTOapvXaVP5eFRaWok8YDZIeQCPcJ7vNX6ib5cRXA oueUZzdXkljsGnm9SjTKFjoJf935JUt9vBvdzpCjZeSdMkUfvpAtHAiovo0K3mKb3ouOV7xYcRzR gBrQEqrC5PZjKcT44mSG6oDZNABCJ0JbEgvXJV2d4SzdMOdCoKLV53TArZCM1mY1fm4UtE4glFLa jtau4K5M7dwFZMiR9aePZPUUcEcxcbQL8mAwNrI4qklp1utJUh5BMatlsPLWFoURCxMmMpe8spNZ xdCtMpFccKC0dTz0eawQZyLIbM9SYj+Y+dMXrNhYndaw8SFOgZedp/W1EiIxHfnFhNip06mSqx+l Or8npo/OuOPJnY23NCx42e0aSQy3JEET6QmwDKo2PF7CadsQ4oUd5BWCRG7CK7gMMskUHIiIPYnO rtws9MrlEHxdAas4XjbT1WMwxJemYUqcl2ZjyzBmrm5cDPyeCiFNHeSrzQRulRomXnYoUf3XfcIY zBrmmGowEKsmSkuAwLy6PVsZN68uYw7TUP9Zh8Zl6t8o17YDwBLjN8jJNNTcYGvaR58E05M7PJrK 9rXQJzJZYmdKTc7cxuhL8HF7wtxFkyYqPKwD90tGfD26CViakChuKY59zAUPciUW8j3EMXo4cMEi xHWFFgXrw7EgzwSE7pQLFyk1njycQ688CuARfqwMwbsS4HG3Me6sIRAtHjZ1PVhoNcP6LMWIrU6t GffBsYylgoPbTfe8O6tTYu6oTo7RvdiW0tViu1XkihwTKJjtCgHDeVSgeVdbNPUafJMXiDmKT5YC 4c+Ih7u18V6qBar3pRkseN+F6//AYskUxAeYpUuwh9ifxbXfk1Rs/vcte3mc6TX+9ZfD/hbZivwJ cgySx0mpnPLaEWkAjLwCW2mehGmOZVJxucW2pgg5nBojO+m2/+WAG++EQ26eoLuZLqEMsSoboe4e hyztGjnTu5vHVtOHT0YMFXx8lHrOz21k1kWG/sSlnju0eaKFKZjWPoELxhfi/dq00xdvdhuGR1jY uJ1P2Gh+CCgRXy044opH95iRsHfO+dIscQoQ/mCA7SczM5lAtfjuEeXXVSQ/XsgK1n9aeBtOHbso 99R2WajBIGUeMypniu3VKUOfQjuPCapEaksz6Fq9148tokw1YE+HHP9/mi+W+J33QNNol19fG0vQ Cq8G5oVVxfFqMozcuwvKLeLCTYrwptE+WBeZgoSY2pWLjLbw0EXyTXhm7TA70LXNo09EV41UpjNt Jts6yCKP3q9XgSeafukZYENWE4aP/35k0cP7ALY= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block TRcoZtqjn2mG6m34VrAup3Ue3mXUdsp9Svi1yOdUyuJ18aNmZzMqBL74/JYXAGMp7kyUseTthYI3 PrI0QWq4hg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block FPMMqj9RaKUiXlcYwEXFaXQj6iTZvDXB3ovRbqMXkBKErB6okVtT7N25cw0P4DrPAX3uTf1/DjZP g9FGVgqB8LxAQapqrXO27frLQX/jtpP5BRN/3UyLQQ5tmeo2wvGsRYc6Ptmw5XXPXjfubR1uMIvq n/KnJrhMohYd24Nm6S0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block hmQ19Z9b511LayHM++uE0XsD77aCTvi2D5+tVo/slhNcSgfFOCWou7QB72DRXWqLm1hI0yRUpD++ 6M4B9gDAGymLNt4kJfLjIH35OM6bL+USAdP5LzqI73Y5A9Ex2dA7XXtW38Kapk4g+yOtlcspGQ3v mipApCouubIDIKzAKfit6i+3D5zl06BKC5+/oMSR90fI/572drXx35dvozy88MbJh8nfL5OjT9y6 tufG7IpOsbuhtIaWR26UAUyCxZ5GOOwUvB2fS9q4Es/JzlrcdmqBkwl4ixHzLmdkNChDQXjCJVtg DP9+/cLV+QeiYTROca+/iv6JtjPVTSGXYAp7KA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KGFNy15frm7DKeh26HgilQgudk+s92inzv6E6/4SwA14yIblinRVK3XaIL/wyVEMSS/Nvx17YpaU YVWGfrmqIII72ql+J97vctL8UoKOHRk+u89CmFhhNIsJnQoGfxdh8DOXKgydwIo8DtyknF+rigwD Wrn0cHGnf+DzHJ1IlOw= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block IRcwaJ9nbddmu/9RW2bhH0oH/sFHVn1S2tsx6hwo1+XOm3bHWHP+ulk+4hbdqZE1Olkl9QC1qtoY ePy+TB2nSwbY99tK/zHUTTzEr9V7pe7cC+aCydi5fu9j5sMPnFmsQadzUgekG4OiSkic9/qlG8tY Nia8+0GODU2GsN9eE2823xR9kslK5c5LHAFyOnzohuZuaNQpgH9FgGbNWtWQ6Q+SNaCkDDwUMJRB XMWJMBZ7ADG8CfZuEbYaJpB3sP361wZWR2CVzTkDaWPuOvVZnunE0ob6QwvKmIm6q/myrsa7qCip ZmcNqxskerCWcqETss8HlKwYY/ryLcmRLUXsbQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15248) `protect data_block lo2tFyFjziJNXhyZZC97XYl3f0ZrW0Q7WwUD9LVmJ9QBi2joO2dZ8TfhlWwhm39tu85pBzGhL0bU lLGx5TJC7bSGiCErXI+tXOdZbJN7BwD743jxvfTNU2raF5ycnehTY1hGqwT/pWpIC2JtRTQTyzBp jg0TCqLY1rtHmFowyZv6918XEG724JEsdzGw6PjyfRjRLZtokRZ+0zbRXq68SjqEoVWFXEf047xz U1lXxDoOT917H2vpfPYaJlAmCz0h8k1/fCal34SYbx73cHMUWFnCTybEbJmesL5gfaookMOfBxRk sWQIao+sOuGvP38D26sAUf3oTnFHhf4FeA0y0GfIpGs4c9o0m1EYVlZJolMEBOS91rz0jpo2qyO4 FotW+gt3+tARFTW3lkQliIHC7eWV+CzKIs05UnbWOX2SkiuLdqLxOSfvNuWxAtliF1fFNjG0J4e2 FfC9OGxbUUJo1RrpiOuacWpSLpdl4+QKPVWCQuyMstdh6mUS1MWuoq6F8/mRGq7yZL2pdZIpB7m1 FqTQVbrAzKa9Cqe54k3eQnNS00lwUaAnIU+CzSg7CoiosWSIBg71HYudiGoiBoBnZLEqIkt2ib0G YZPWoBJ4XLzNcluQ1Ajkwv/Xv7R2wBRSej0W3uwSBWm6fUAXxP2We4RT2a/8nGQcnRSmWtH6tvn1 toUbZDD8+Ooeq6eb0K8NO/8rJFhNJV7JNyQXElREEK63JtrgaSZcKCtnBW+wsroNhNIOskBUnQYV 0CCOIW97dIQavxtVUm8QElbLu5USzKEeLvh9GD+tbqC72nrYJbHQnB1ohbEHiElv0JwdtOtSflWL pytwBnhoxQ5UT0UDv+wUPioK6HKBPFktp1w2/8kV+msFfnPCYTZvAF2GVF73mpjIWNSQk99VZ/qf 9K6lAwSib3XEYyTtUO7OnwZNIJUwEDWugnn96iYwnYYes9kgSrOfR2iKOJcSmX2D1CE53neDgkVH xkC47PePhGeYQ+9CruOehZDBHHKc/Fx8iiqW1oWzim0a0wA8NBVV2OqueD1dwZX1CZsTEAO+2Mcf rJFOE7NbOnbN0WJ1EJ5BRuVz2S/x94hwZ8o4JmDKl5Pxa37bk/BXyfiPL6ngdHZz+s8AcqBsyTxu 25sSBxZaeLoumhdgEd1YTf2MrAQZF1LOmD7ZmxpQXxUqzDi0fCC9JKUEAusjFvHSE1xwVYpyGp4u JNI5GpLffojoQV8tfutFGd5oTy2RMT9ZAP6bmqaKWsy+rlq4PgDvJmiJxYPF+FxmKJy4Se7UTCQY 2tGopjkFaSVlGV15HPI95mnUmA4BX23/QHo7TwIzY1um4MKqhwtkxITazjhYc0NiEbzJcop6bimU 5Hd7Ad7cMRDj1a3Xo1DKie1GROb0LBMAKcfeNv2zhs1tkeLMXkNcvX+W8v63l3HmlbO7RZi15Cm/ 2BWj9XfFFMG99MOAbLXeMsJqC+dpxdTsOguJfZxshnmn34b5AcWmmOZRX9sgP8wpUknH+6V6v0GM M8HKbo+sm2eHaAl1FWozeJJQUvPa6Wc4rq7pSjwdGk5FV+syvS5mCsU1fEEac9pxRE2PbEr3vB2V DRnHV0llczoF8jgqeLDTmKG4oyKDJBnssnwbQCarP764MWnhOLRtJkEoKwN9+btcZ1VdJ1avFa94 J6sQAvRmJuUd70Mnii74Zk/EZfliu4yf5b41Xkp0j+lywStXrsAZDldoSf+yNBaEMrVsL3IBAJyL BOT1Rd4YxlmaqzqmbsQ5YRX4Ub5NyDh3sZ03W2HdiS0oJRlV45N5cK1OCkUQAY5cfVuPBGvt5GRA MlBA6ms8n2mGPaNAr3e1b7yydC71SvA2ReRI5Pd03Vz2SAqGhP/59Ge75gqaOW/G2IZoUC11UCDU 31QBFFxVvxTiuKYudkKmOFxFBtVpOVX5BR7/lN+BDExAVuiwAlh0Hu5VDxIm48y/OH9B/R5LdcxH Ekw8rrHH7EGDSZ9Fe373bH13i6PTtHSKCiscmJeqMg+iRxzvY+BYYAtvQxMeaM65oZeHO1cwWQAx ALVsCF6TftT/Rc9MlqkzPpIV2mJ55DHMAQWKWb8QkBjdcs/AB7cnCVg07jbNLP4Jy5RTGGXHwFPi MZhK6ZPQH+3FRieYtmnhUP7xTYheG0c8xaBl2Q5rzribOMk8lVx5rTzHrNPvYdjp66A593lzLTyd mzIocbG/auEuspS1QZ37zHsdA6+QMZzeVdz9hwhwNioBFtgScmQzWrGhF8ppCfURQNObhR+UQBk4 Mkpe9DtCAaggrUW4TaZ2P9ZWxLVzR7jpjApAJsYlqdHXGRaWPT0f7AbJhvzAPz9go8J4/wPMJWBA P8u7WpWVrvnCuVV5PCjsTYZ5eaTAG4JT+q9Roq18Gl60ZmctUFnPlsN2t8Iw2nY2ru895Etg/5MR Q5ic1xjhIY/r4T6qcoJurG+efqeTYn3BsbJIg3gg7va8t1gOGGJ5bTW7FEeibIl0IQPwmhiZXcaG ll+Rcykz2XZzDFCJm1kn2DSeQzDqXz+eaB4O/AG0iC8SJofVp2apAQ29vRIxo+URABT1X7EAk2YP XBZBSV6sg48AbgQSNOXltxjle3f9zd4+0jzoex3KqFIi5B6Jhz3AIemALfWqZnvhUsy3ZD+O65+L z7iRBMVTD+Pzs/xo255Mwm9jeu/MYWRlZ68lFOi3zSBcsBItIlO/PPOAzyOyIWhU6OxP/SJDjuhF mE9ensZ7JNQAbDlglmjZ5EnmdEmyMjtRpUlTxLYNlwZYtyHFPLS1XmiE4UoTB36ClKq1wMYEsT46 j6OXa7Ae6Sz1zjvBXSolixvc4Q46i3M5pJxpTFpU/6tMz7IXkQGWUF6BRt9T27SEIResbJQgKlVX K5pPzrUYjfeh9dwsNU6un5VQLsQtkGbYUdCGgwrglawDVwvo+7GCXnSpxpjPUCGKCnT2WyzBmfOW Pi4Yih/HToHDNUkNypdJEZJ78w27VFhc6XgQl266RK3GoXcRm/4sxYpLwyPaWDBzuSb7qFS7Kfac d7s+Sqss1A2KS0zvlTMBW6j5yXVsQJl7Jbjc+1MNHWfsn0q9rxLoze2HT/OXytLWmfeOtJiPRp8J IPylF2iey2lTQ0Il2bLWnN/Twl7v8RsHM5XyIJlJaqJ5nhekSeOURwG5TsyiIfDcKuc/Gzpe9xgz 5t7aiOCvjTs9UUbNZSIgXj4tdBatEeuAht4UJpVXkWheAgt5qasssjYGpMdom+S+NWms1aa4c7cU rdrz5h2spaEGbgSz61nGMAfONrXan/iojpkD2AAiB/Gb5qug/KrwLDvp6HwKlPWXrBqwHAyhTPEh +dk1VMcvLdYrbwtUyZVi7JiQbap0gpDxQtw1Ce2MOTVUzcUMu5c+XRYSTaCnwMDZVr9vQIAFIKOE jgJSLbzPtsdcy8Bu1LS7pFjY1eKlqWq1LcfhJDCyblf6cEESmsGivg4uVmK6gp8PsPDNWvUy9zM+ q2us3j7GC/daeIegUa4TzRNbtGrBG3yf3zJLs583MMAGQBbczPg9dtSfI/AlQX+5alVGtbNoXrls ER7y8p+bbYSX0Rsw+ytWm/JkeKmiNuviV+SCxQVwdx2Q8CC1he63DAx0GuGOulCUdXuVidVG+GWu EGOqTIyMBG6qTzvG9T2dhRbujJLP+bWec1FYWqjz+YEStYcm80SqY5ilecjQdxJeE7b1PmYgDxTm /iqg8EJewLrF2IeYECtFqYPf0gFAMuWifV4XiS0Abc+f6+B3tCMDwC1yfUgcekyCRIe5P4A0Sql5 /3KWdaeh3eVrZmlsOZrgibyGtY2VofAGToxxZgCP3SvOncAv259/SlswvHOHEHw17krFaMaqwCXt KaZCUgELk4LMZwxd9nJc0AHVMT8TY52JyAm6C6MtRsL45cs8fPbzN29yicUJDgELyqd5OtLx6SnI vwdBT0Vxgws/He+tfW8WXytpb6TQ1weCZBOAaQtwNfhSJcV/CrQ0LMaDsjCORTqgPHtlhrDi6Whe s8BwlZfMZK7DjdE7BpbMDXkpW7xvwxjRxqgMdNmwg95N3EvPbmV+mYCluh6wuXgbJ5rxsKJUtKvW p5aJrbnhIiCATUNOVAABcb2v/V0ZDNPEnIDNkgN9lVy4qYdEIuL9/nuDeik9+0O20VXyd+R8dQN5 a4++rqVcbFmQQfjkfaXX+kiYIlQMhsmz1edAXnOT+UNQH0oqO6GtlTyMRPucmatg8js/JS6PVW4U R8Sy0xjX0CmVYvXlvVbfhR07kQjXfznA67gEZblgvpXTRoHX7Sr7DUNE7QXg1g4jtXgjBvVsO9lQ nQTrR8HadMCgElnYWB1MUrtROAGZoTnBxfHfUHgsSDhj9Feh9Idtwbv4JImkI6DiBrpiG0LQsYwp OsqCIY63+3K69v8JsJqbjGRU34iQm/j6nP0J3YsZ5iyWetQcQ2TqQPzClr10sj5B/QgVQTyy++Hw +s5CDh6ocLBpj1KbPY7um/k56sK0aOwlgg0wSqi35Av5YM7C1+wwS5nCmnNItHXe+WslwIVX83hL 6MEJPXqYQCfS9Rg+mVvASxz/v3FDbVwVKljjkFeJ7oxg+ho3TI9+lNBhY/B7rkDeIdIFgZIU2tkw UeGXme8J3NK/c4gOPpwyfBIWcKDThmGa0d4Se8XxxBtQQYCs7oXYBucxlKVkr3k290pU26hnkyau ULF2ny043WWmhqXJWDvG90oDuOI3KJftR54o9hysqhRD5maT+w04buQrPqf/xgr/vwEAM4VYTE6Z /Q68yFUrPHd1Q9zfVU8ItZu6kvc/iJDBGxiY689Lk9EKs5MdBis+rbZgKtnHgKQbkk6P8hvQ+Hz3 QrSvi6c1abPqfQTFzOl78QvOtpAxQXG42aYe1cumjaTO+YwHHL1/OcrmNug2WDB22+B5yYspHMMr pghggC5YE14ZK6SLRRyznvi6/0j6JhUfVvgPAp/DWQkh0XCEcgptvAjjhDXqI/DV5vcxdpZui3xq DgaHNZnLlN+AiSwhiUvdqdcAgAgbqWcppIqvXreYG/5DLtlu2KYqyFHwzd1jufRuB79FslLk+8kc pE2+4rpbb5I7+T2BfGWB49MciXCEEmlXlHRbI1aj8FMCawqNYI+SaTxAW2Lpb44opWQqc6rMs2MB RtxcdjCq6WcCe/a67b2uEW+Bn9IgNF9c5/Xd5KsX/yzm+GRQv4s5TRgvGOd1PmDS5CXpmgPbNMh1 7maofr4z/xm46/gy1FX+/cZzX4z8B4HWNSq8ao+MokF+twMaXFVVOoh19LMZeHpeAy+yaNOMUlB4 ZHByjXkYxiPQUoEEi8ZxUkWNQEXBxfS6JnfMTM6PitDDiUaH4v5mG+cgP/GyMwlwSbCVuYtd+ZLj Z1Vo8jk1TbUy4YwVZN6YZ7k8H5+bnhOdSlYm5VsvX4R0RPPfDElc+ULn1p8VVbAP22fDB7vjpg+r Fw+xC6TL7NY/It4Pt/lGmgYLhdOBItWGqWEw9w5BtgvKWICb7oKpkt0OYoL8RpgVrDKL4TZFPHEx TF+QEEAWi/qBHtpFefgmlcpp0cOMv/1SyDx/YosFuPM2nmj/S1kIQ0nIphjSxRlgDnTVx8V34pk8 BfzcQQWpAKoKcp1Sq3ls5m3tm309Er2uvSnwkiR3Py6zHkT3w0Hi9++VsmPe0btjY/REO7oyFVg6 R95dXw3Yho+iq+RM9mchg4BHOre9/KJbc65qPF47mKBnO+PvAmU+hl5lsEamo1BPencnba/P8o0z SbZN1wcIzlnbS1+XYPPlZO+lCOWnVCXwBiMxPiNzAUKHUY/ch6KpYGM4y8DzbzeWJKbQqJUx6bGw Htq8GEioSyFGOgSLfAgprrgSfvBbNnr3o+2XEN9i06V4HOGGP51M0BuhOZxsXM7LC17T2bno2lxx g3MNBexWh1Il+f7p32f0p4zchekCfXuxi9ewbdnsdhoTZWGMx1SR50pKRuetNKn4lG/wCYuBtMvh eN5mHMzz9sNs6mExAUsCDuuZTKFm5ozosPvCWIhsviNFQ4fJnmOAIQCyuybW9MU5ua9T08mNXEEJ 6lGpuV7d6XTL6AEyHe7ZfR+GlGyHtWFmnmuNh8HgVvtx++CDnqP1/WhsvQ8bDSZuW3NviXmCzWw4 Gt2pKlFzptQIC6Zfl3RnuK2c94Manvfx8P/8eYsrotrR06wP5TPCdnELK/6Umb/fbqzERjSedVtH C/XNkMeW/0AbeuNKu30powhGQj5XDKwjoJRQNXdKllJRgkWHMdkyLwAMMh5XSq75MVUJ1jGvRFpV kPtMik/7OSZ9aV9QgtERkL4tQVIKznYjD6cNl74hKrilOaPTxC3MnGUwgWgaMnkDyTGPbgI7IoQb SmbhzcikqOd6IUbBprZvw6ayE0OvckZjRoOfficSz7j67b0DUGKTTV1nbVEp4Ob/tBPY6NJsjJKb z4sTlAm4ozcDYfpnhcmgAHuXvHiFFBkMBNZ3rjYT2cEriQ9TFLF3mizXSvt6Y9lGNjnsELiSVkPZ RFto74jJku8Hss6xrKO49xXr32YVTl7TgSZBYBEReZSDER0F/9Smcx6PxcaJbEbHcoIgaCinTWDr xbClLt//kAW0biTwE+PgAgoIYlf7HXMO0iCrf0mD/NlAKxr1hLVveiz6c4/fddjlT+7789I5+4wX uP1L854G79hcQIDuJUlxMBN20YgfOFUJtzkDPbG4Y93b46Rzs6fZn3Zp53ui5gkJRnKQIx6wllzZ KGRD0se9BG6W4fHDS85OKRa84HvXcWNex6fUE86DO4fF3z/VLNoalpz8xfHzl/1BbFMTWoxvBuex Ewmn6Z7qXBrsz6rp605BFeNwjhcEl5rbKnvtx38car/MBj+kpci2RmvwtfYvrnFnmonQVEhlqqtb izVSQZTvDvDylxyI6KejyO+ad+O7KhFt1ObvtioLPhjtD8o4wAKHpqAR2Hu4XrAlkqR3GgQi33AY efXDINfwKWhvU4CTCyYdxJoAZuCZJp3VYpqygSeZPSM5WeY2E5wcbvPG7jTqIlnJ7NPBPkYnpns9 giuPumUmUOOcVFAh+1CMZW/i314PWY6dqh3jiFAUTMd2pAQlhzp0COASBkI8yHscCuL9e76LrNEl phK0zem4ZXVqvQfeVpDjlV1sqjkZH1bX/jm/plr8dpen5FxOm090bHN1BTwSx3G/mdGH75jaC27s ceIOGoUwoN/jYig7YwIJchD8FpwjGlocKJDBXKwQcEkAFDczNefFi4ziWDNI3YZTq5+thfPxOEFj TGGLOA97s/C58H/TQ02vedrKqR+cTEiVINTohDV+noR/pHiUWOgPDa/QVi9UZh1pv/uISiZ1dRQu Nq2qa1skuihcQK01oxJjvzePeXBQZ2qTzuUpfd5EN2ZyRny5dHBXJVMGeIYHDtTdh8pGBwDlAxYl 0G1e3k6mxqAjAIbYKg/fX/tnFMNY8haPyljcp4x2gBI4a0AZa6JtZpg9UfSlBe+Kl6KF9L3xTYMg ova0I+v2YhQPCmumDF1d+iDw3Fqkk8UoOkhh8DPP3LKU2pZJTLBSe2V02otyUo/C24nSt6n7MfV9 tTTVIzTvDeaMXwCb9GZxY/SeIJPOdaKmsmD1fMSCCsnr9aNmX0Y5pNUJDyTIuNBZAqVg1e4N4/bg wI/4dmn2Je6ixx8VUYRktKUsL6H5wc8cK16cWLMq7/XpfvPWADFWRlKdxzO4cRhSiYOka0YTRX7M d+cF5YXSMaXGd2imY96irnT526iu2uUVhoEnfCtxxvPuRf4jP6dwQ/W3Dwl5mjf6YgVw9LEvQdGD OtNhvBnzj9oO5OmZNsPpZlnZAu+wCFCaZnEsoT/8zttWrCWQYVLlmCMDGZqkIyYOmKZWq/gccVvR A5doD934rvPOkUR52VfkpIap29Zb34WqexqRn/0IC/DsFN7H73s2bLdm5k4vIdOSUJPrVoOMlunH fEgOAXDejR1OA0srkMW6DirEbc6T+3BH4lBAh1VqdqsQEAaOJZg2uHj7x06rVH+ZKKlimvQKRYKN vvaH3/maL+3obAIoMsvRXtzFP3BVjPVSDWlrQngRtmjDMASn4pDgQPic9xmdGeLucC8wW/D7bQqG 3vFNQaWdOwNAEAJg1Fxdrw4+FoSZ1+tJuaem1QXlLZp2MWnmc2naNfy0+frSvhWZLnd5HTZdmjZ8 jmmFY+wYNqnivDXnBgXQt+lTaZxmbiTsBDYd1LxnrPzBdWSLsYIHwSc4qknEunO5DFFeU7J/gRBD oLvMA11R0nbZW8FqjRQegzJTfXB3hCElqcU63wMkM3BDPrFqSn9jMY8AtqyTZmtrXoXB/JgzhAlu RWpCGYM/yQU+VaODjSS6ahedrwnZfEucVY3S9uIJOiCZKDxQP6gvtJwHr+r9mj8muQoOva/k7shP kDDFoYx7yIzd/PX18UAnuQw0swQiWnFq3Ysamrz3cEb3w7KCWCE0miZadUqagWh4Ui1EoA4BtTCm XH+ULndTI8KXBTQtdiSaIelm8c4+Hsg0C9LoAmezce4IxO4XYdeG5mTOuyhdvbaf5aZPhYiHfCiI 5byWtx4XeofT5LYNa+4oJv6J/fs5re14ShP++4ZKMOnGmUcB0xqymmMzKZeFzu5qZK9C+EJniLlZ 8X3ypMzEUK9VjeCEvjNhAi3kE6NAMjguWHtVAoxGk0FI/+e6I/x0exhvmD6+PsENXHhXNgiGv006 kLSDnkx+6CJgztcEI4r3sXw3dTeiaYYzJhTJUw/z+GZmodZpeCbVrsAMv6bW62Ock5wdtXqJagLV VSPRSxklebpditAz2peVOrKx6ekkD3hlFH10CWt7N0b6mlRFpGzRIbArJnIkhZImFhfLHYxrdG+u Q5QWVQ/qK1qjjWUkpMLZn8KZpRWY6Iv6/OD7Ms/rIAfGwrG0WQEh2CoA5kH+kVtf/KjD0kUznGzs uiq3DYtmVnkzXkjgSTWONZIQMe4uUy1cDbwde97AS+8lFfBBUOrzGikwN3CnatU4RSReVfMfsmj/ PiUvI+VVIfB7fLmIYirpkTyJlLbNqgCbxTC3/YUKvQeKsgdPYRZ1AQ+X2EECrxumRyYdjdzdM266 q/ngQdXkaptEq+pWick9hXGMZv4EXwb/JiIrIW7ZzIyeRw/iWU9yREE99wH8dhvG7F8ZuJYODoZq Z16s7UDgdwZUz1WAASUCVAfQ3Dz4Ys/qpMTTBwP5weg2M2dpSnI7P61q/kp34JaDu+mDwNRk0OwM S3MjEJmn7M9bosNMEbdM33rNvuBPGrGvt+N2snTNy1pQCQVZhjxY2RTzluBYwLnmqOulukiROf2T lArRBTBcutYaPwNKiLDgtbC263UZD7nXmBMnFbxEdHQ1ciWmpHo0nZ8vvOpG870/W9B0bIU00Zf/ mcQGtsdoYUq4AKCGeYuT86AIsnm9QubUYTdvBvU3355svrEH+FrAn85xkA6Qj+KEgjcTOsEO2c5v a8QvtrsHm7QlyZz4nmX0z+c2xrfYF4NYwB1W5swgvEVPbo4m3MZ2Px6uQ4tZ7Jr+wdowt/fLBqCX uejBBNkZayRvIeXXegOy82MWj9Sj5U8GmR2j4Ufp5Tz5cl09egSavAg314dcMTUbqJ6jko/G/s0z hal9n1np6/6hYCO88KZOCHYsK3yBMSXLeTryLK5iIwAmSKbm9hltXEyqJiU/Ykw2gjkbjNYFYZyK OHlDaFUUF8Dhk5sLXXK0BwJjB+7JpKt9g99BATyq2YOzoXh8tzq/r3PIhNKefbBMhJPdvtA7oWKl 9BfWupKNcvAuMYMENnX6MVjyiMEoFSq8Q2c0/0cv5SidXn6pvp27hiMYAviHq0/ii9bYOBmwWQID rFWstI+te9vAVdgtKckvIK+bTRd+gYyq9379EVHT83riumNh79bKQg0kgGASNv1Uw7qIDGI8AYe4 3Cr2lbdTaIBcgw2Tvs6tCkZTOj4tbt90jk+jhkBt/kfzyHkFq/hU1/tPwEg+ei1zO65wpOl2J/Hj zqdIelYk+Q2gMDD4UO7B4QJrq2maRaOh3NAPNsNttqNh9PtnRIZSIhmd5DeNgbe4Q8JUB1BBA/Db JsHJ28cwqoLKRQSTa9PtlDgLzK/NKIuy41SAJ1FSZmQK+bUhGdPEwKMPlvNOF86H3w3FB91qra5r t13g66yCkK2nICykaW0+ctvVWO3DnQt5dQNlWp3TtwC+UU5R3WJ4y/KFK7Tc+hyB5J1440FQbJoA mpuZepfQ443UsJjyxTanoZhHKOD7Yvpu9CUn6Zp2ktivQoqNB5T+rqM1EgThdTTt98MM8DcwEg1L cszhN8IqINLpY4sFYtBhA2qTuoeWkr5RoLqT1hNi7H2xnoLA/L0wQHLjIKKqmRGyBX70bMIj9bsY ch3AzRyhbdYrUqvruR4h/V1egVCDHLMUhpxyGacBypyCswL6q5ji2LFtQ7nVCqHSOqJc5Npym9fM /UrTlm/16RpH/DuxDBck+pbAmHknMlME1lvMkvsxo8vMkwGvPuIKZr7n+S8Om+Vv9ne6FuIdbzgk iY/KzqzQBx92OXH0B5uSdtUeXsIalMo9BN3mNG9UXV5y5BJ3MOvtnBPeTkI/N08QG6YKJzUS/iWl 4W/9JSe6d9oYzuciEUrxzlxX3HUS160cyAQ+ODwTRnDtLi1U4hRgGFgIOg8BwEs2ilLtuXDxORKl bDSwNX4I/PW/qhR06nNwbRjyVfIi4VEn0ULSFm8XIPzEJ/t+xQsSK8cRx3XShqsDrberE4kcF6tg TsuJ8lO5r8rDwKCZOzPkOktohxlDzfICQphnJ5xRK6sehksPxetSeYsrGBplI0VPdhJLFAsnUFJd Ev6OqHdkRzMJ8+CdkuLN/snC4oRaUvANsK0doQmZ9+c2NoNuhNcVod8kKpw/3twWUJdfa0QIGJyX qzI+dQhuU3lWQBhEcJhG2DzZaUbDxrbX3YCGd+k1wavEf7VqLSwaTmmEwdZ7jtRmuK6HJ0rRISjP f4bD6ffOZjQ6jYL8ORBWeiI18SoNK6YO5RYGBfBdFqyxzJNmYSlofk85khFYSEtHVqecaPnuaHdV A6gZQC8sgAX1dfe/II0uTSstSA85bk+rpeDP4VHMB0X1lMFwrpVV9b7Y1Di/T0f7rQn2P/PPC8vQ 4JLGXzybsadQGJ3W0zxfq6PJLdRyCfJyHIttZEiARP7nqBDcTIyFCg+PvJcQZ768hNO8jAeI5jbd msSsFZC4D3N1YQDVZwj/7vmIilJ+i9qJnvUTwUBySXbq4FY1JyZSGjV2GWZ29ruIU3MwbAdW8m1S 8XTvHsbcxiaPOc/0ek7gt+0+b74qNTeX6VWf7fYDz0SZaKntTeuiDevjmzuF77fbaITL/5ISEq+I BtyvYS29P3b9B8LA9WC1N7tSTt6E0OIJxmwZlujkOJES9mM6Z+91WHY59qFKpa2siTL4jl/unDC3 uOuUsFOdpOp6OgWVfA4U88/JJrs3XraZDrp7DLnvDxEiss4+J8j9p0bw9hfz/ZPt9o/6Uv8h+z0P 0FRGjl6c7lSreB79+W0JPk5s5gfUN6tTwD98zYuEjyv0TIOWxsgQQOUE3DPnCEkTyCCwTqLktu3p ZbAGkWSivgpDi8580gURDEmQKDXhnks2yBDsXxiZx+N+UqfI8u1RYwL7sKZVDsjL+5mS9igixKJu mi6g1L08K6EDnZY73csqvUrwEVmlRdOTzVloSY+YdTJFeGdmKYyB1As6DDkFKmSB+eztHKVE6V7J bnAUyg8DRbGxU4KXgrC4UiJRgUaSYSVe8KHSshXafQ7DPFMKCB/GechX2JL7p8dmDbJWRYbq3c3D VMhRwP3vts5oXVTfCoNn4Ep3xMja6QsusMNZi1papKFd3yVv1l4skzpTWAg6o9EWYEnqzjznoUT1 HrfRKo7S2KqkgK1g14Ipvf5gs4HrxpzJEgZuUK8pGZH8jbP71j6nuOlCB0Hpr3ERm4DrKn3/DIFV mT8lJzUbiW+KEHjV0PjT9SLWH25lIbLWQIRxB9dSjAmOM9k0j1SHqlfPU5PX9UQi41XcoqWF1/bf HnAiHpCNxFAyWodIw9PzqVGZ03ei4Us0GAC4j0PZBcaZ0jZTD4SYgR1WAaom04ad5An2SupDMqD6 i/zj1uMkN1ftCXWyyAYzEknvYDhlGSGqD+pgEx8jyNJwbLN6dijDF8o4EwiSgu4rs3zkTetGVXbL ZZiW6gvzetc8r8CVSkDS990IslEBE7FEog6tPOs9nAysN4zANCHAB/syxXsIqyaqDLxj08oCHAN9 Ea0E1TcxVd4p5aMrsZtaPXUny0WsQcZmrVua+pUORYcdpMtEpDhvNun7+d7Yexd7yMiL1GUXbGBn 55J7dkquCalG/Xmy9e4QOaxqOqW+fLjL9VWuDLKU9I4iXyc7CFC1H+GtUT/gMBymfmMxz/Q98/Yn inr8+5CbwWjD7si0setE2IM+NeUnQa/gtS4vfFkIdPi00vXllAM6pSC6/0QeBaWa3+r1czPVFObj PWH7rYqR1ooR25vC9ZbZT403w7uhulpM0H08ajEmWIAkOGsH5pQS088ug2MLhd/hO26L4IydGeo6 3NJdiNd2TsdbmuJoUSGGh8mJf7yFL20HUgmUQDeoEGFqgtWO9hcieiUbBjhXP6almms3b+QF7EB+ V36WocNhOtAOiQMUjP7amBx6BWL80y7ZG0C5mf8ceE1zlOP6JSqIKZ2W2ctmKMKCzQDQGvCAR697 3oxFl7KClk72SSKOq15uzytrapXDRz5aKpyyrxpphsZ65VzcLdqV6Dojj5fnaE4u7A9xRt46mmNI R3KCXahZ0diUKnV5O3bZX7GFF5iaaJHwiBCwxadX6E52fTHqJ9yr291p4tG0pUlhCni+Y4O37EEq fwWvrSrkv3NqI+z2V3Ifl7Zh1oY3E5v+/mO05jsJmthiTfptmfo4jfUKFl5vHlQUIKwDvAGQUvAg syriuscwJEXegC6+8l5wdH8flHjlXHsQa8+uBEqX7KqZ9C6wQSIvc4OmKI7Vz6KBtqEuFqTb5dHq /as5/RH/jGlNFwZjxlQZuD71nrhq4+Oz/jZbm1LpWZ5NXkc1Om9bx18JGA+1sYR1xe5R1zs/eay9 yQETW4yLT5sKie3PwxLcmjPq5ttZ540kwE4y/K8ZEX0dCsJvwBDTPvftVJVws32pLrhd6lavVuIV c5F/9O9wt3B4X1NWTlchrQwc9yKzvp5L5o1kr6Lg5IQe1eBkFQZX66eSgK5cWPkdqyq4yMniZEZ8 oYrcPivSsc4lOI7GEYsE8wLnE9clMOPlm9nriJxTDZ2i7/HmnL1Q0IiPMmg9kdgtz3VlAuMQN9RN R1iS9ykHnegJPyKBWmIO/K/BrHJen7afnI62YQbUp0Fr6IcNROoqq0bsYmSBruT3W75JIG0Cc174 /PyIiLpmjWhJ7sl+686Ml3/vhYFFD5jlDOQ8DLKpSmaMscH50ZsQihpoKJhP1JNtd9JrOd4SdQ+I px6bNnblous1n5h522nqwM6XosLtL/G87CJ/bOSeIdbixbyZHxJXOIxNuLdRQPb4QrqiDHXMQeah eWPEMuQpf6dnYjM1KnkKjxh/CxJtCRmkUjJe8WqDLzpdI6l/+L0JhoDyQuH/9S+V3bgmBC1C/tRk n6xVuQr19CtS+Xg8oQP9zBFToFMk0fN88FqXnqAkJ8BOu18iSPMpTTNWAs6kNUw84Po/gZ+fcy4X wB8bdIiQEAAztvib1K/zwMw+cMVzX195FEMZAJ617/s7L5wRqluMeECknM0HC9AsZb08tQ7q0FBH vl61Hyap/2Vjte/O/g8RlkXO6FICuys6T+qFHYHwrNzhUtaMXqkdGddnHVh/E343B0WBE9GXpeR7 lGji7OfIToIlLxunpXzjw57MBUgjLBCzZPsPSJSa4io30B0kMP+PCx+qFp//LncbGBwtgPWkAgHL IsQhLL/xfkZh/36LEGgpPNlnS4ETUoifcxEVusUOVrwv3/tleOCN1JMljt99t2sXt4GRoGCvQZaO NrVh3sd2KrXhII0gfcLdpbryzJwaZ80HMG8KCqLC3Ga0yT/FPdDa/eOJJ8KL7fQtaDwXSCL9cOhM Pe7qiIINL27Mim7MzaFHp5qUtpYlVv/Ex8bJ9zNFYLn0uO7H2Sn5JOuwuqmGkR2SNCz6Fupox8/z D8LVeAe26qFrZOsLD59zLdgbLl3asB1h8osvKcLkvCQCSXQjhQntaj3PjjbVBNWrOLztNATp3Env v0FW90WhtZiU9R0xHi1sqsHDYZ35slEh9gKRRyw9tKM9OLvY0Wg4XNA+mhDsls1SiQbQOqC9i+3X IxgawQKwDnEkrbn+DXTaV2CTV8ak6V9WIDsfw8rqGcrGaII+sQhmbbfZAvM1+uWubre3kQlezwuK PoVfogigSpV0tNW6S2/LnMr7OOLeHvpFV2ikQWTbx9oirYNSEPJbWoomWNdL8HgkwDoHyknAsPxN j+YV8KYlzrLNeOQqfh/dZ1RhZbz0DJMx6mPpZSv3wxe/cnCuLOq/t625aVMNRyuqV4nkGpV3bEKb Sq5w/UAdn289Ylqbk9amvEHPGi3JViwXmlml23kzleLaClulOSgtec660aGPQ+NkmvpfRKoQfS/Z jVqqGAIy+pKJbg1ijmXawOzL2MWbm9g1Cc0wUsDxw1SYbxQ8ZR7HaqEyPcCy+fJi512Ts0OLt5qe hnkaR6rzQ610uluGwmmaqnNe/JpmSETIqGhAZYlkGJgYqLau80r9i3vhe8k0QMKSaOnaLsiieYHs bR1H0Go+tU/Um5zKqEtjIUYxEFeFmLiPdU6qFVy1VqDviqJnMgToA/u4jaqI4/WkPz7i5Jwg5/M4 x8MIXD+CMxg4sM/KbEfro9Xcc9ysF5OStAOT3zn3Gs7dZkLSuboaLGS+QWJrsVH7jmxlxyQddLE1 ZuFeh6ItwlGKXuitv5MkMxWnZEOLwNPIHF9CfqES3PX8Mu4nHsdRb+xeNrbTC9mYEMvxQgMLtR8D UjQlZm9qIBKCdU1Qx+ssRmtB7hB6HpTDFkCXj7fw5EhPX/TWHxqRYe6TMnj2HlBZVK2FNWIwmoD1 z2kUSyWa2h/aKvRs9G+nWyPmT0j3dRuZqMkZBAsJuJp0iGYVKPICWos7uo4TYNqm0rrcN3UAhljZ WGlcu1o5LpU/rnRV0wzS2X+YMTxz0Giaz9gpJ/sqOdgBiuFYXJDckfQnKeOdLesW5Hhil6CCc1Uh PZ+acLCcStjGwBl9sxyAdpiJZGhoSZ0LyUTT+x2sWKi14HJ8c0pIAMvwq60AEthGSTnAXDu8y2+t 7WyNiUepk3gURbhqidaE/Pu3frJMq5BwZaFbR70Mj20NE7pA5Sg+BxQsaysUV/Grmfc6iap/u07k hQ0d58AwvkMOCUCRuVpGUzfEY7jAUB8logHqIYRt/Gg3y0TCL2GKpRYcBw/cXruXF4PsqphMbz9S EetAjixDXFHFuIwiRAeTjSQu70P6HOMpsfpe08dQVthvCCy+PudKH59SdelBTsNBPVcmyIumGsLb p3Tr6N9UjYyY90j4y+cAMp+4RmTgEegTSMeUbpbVeNYUI7Wu0H7RcjrVDrWSxtY6UPQ/Dx1hn8qj 5fAdd5SBIUcGlrHxWNN9a32r3ZZZEOsNVfCCYmVv+iAMDe0oNAodyu7w/q/qcwppLWxXUAMEhqSv vt75VzFD6UTBN6Gpl0xlB6ofPSHMtOTyMry+w3kvzLxLczALwH5vuuQScuo7eMKgVJ97jh/NbD5r 5mWWFGiiYGToHBdP0Yp76oOepOPjDn97NxkHvVoXYZY09wHSD67M7DoZ6mFay9tgR1MjVJ/07MrJ Gqfz5hsG/96fNz6NVX1sGtS4n/YCo+e5vOdb2lL9yfknjD5VeFRXw74rt2rZRVT4OGEKPY+z//f5 MErU7acWK7pqGvN10o4KvM2y7GPDIOdszj3V+5zGxaRsbenLDNz/YtPWlkVihCzomhhBXLtGRH5Z JIHrEch2Qq+V+cI65CSviLaYXN7wqiicv7a5JPIQbol/4EPgN4OFCYQx7GwDmjp8rX8jBjtws6fe y12wpztmaykpcO2/b5mJ+bm9tNHw+Z/vekRgHoQEBAAIaCdQWjCjxstRIm4LHDbTKa3gsUGCoSg2 Tbw/UUgoj+fFcKvzt4bjxU+RWbQ+f78UGB7OUEDSVYLkqHAfolUvw5rpm6Bw8FF2HsrtR378Iv0h J2pm/4MwDHnAxQVkpg/MDCQI5JVCaO8px+xlGOMtGC7/BMrIxTjYRqo9LpFGIlOwScNgfpBrvjAF 3yqFFXduKrWYOOTsTHz7o8jBXyo5MP9YEw0IiUsmX0Ykj+sSswtoOk3arr11bzp/SNylQ75n2S+t mSAvjUlBJW7JuAwA218g14d1KrExYh1l9OEOgcmp95E2XKHXZhmRgr+2+EYAvsMiLWwm8kIl41lt CGDTL5/3CqDKnHHzc9p858NOue+6MTuwSopBPSkq9Ita1y9kgJxrnJgafEl9BX3l4sBZFafEBDWh epXRZ0iTEE8b4dzZ2WnR+yF7sV56SvH/HVsJxHUGj+zvukJmGva8H5aEy8l4jveswxKcSi43vpPl rwLz6soAsP3MixinEYYI8v1A8JGWpttM+VzOMr+zkvLlCyk40XcWFzFjoKrW2dUgB0CaP+aq43jS yWTW75ZxP50PQBEVXeHGy78vMDCIZLPimV143fxuqyrO5X8utlxdTB8FDRds6fGAyxDcMyheh1tN jbaF6wMhWnEYH2zSkI3bG6VsUgLxEb8Vs4jXmF4C+cuuflN7r//s+jYo06cDgpOgqM53SmH9MIlw AYOYD3WJ13Nwr5+6Hb/ZyRksdUe9B1A6Aru73cRGAS0GDocaLdJVVtnqpqoq9jPi2ZzvlUDVJL2s BPS9o7k+dVVldul/SsgANNDzUm0Y8A/EuepyJEYnPZskvkY2kabzB0PR4OGwgpnmAkeXMX+YWAzj lJqDmsv2U5SyB8lx6NOOUKLTUiF0lgGRK7mg4YATGiLsCGuxeomuFVjC3oZzPFpx2ZTKeVNMyE/J VsfU4zQPsCpOYUrbxffaRilHAB6mm9kBpplbasLi68vkkXj+U7cyx2GRBT78H1iH5erJ4L6Io6sV FdjdPw9oOsGREAwYnhl49HB+rAKU3Ja0rLFRz0b+TiF6JjVQHosDcAIJ0BInTbxunV5DazDH+J9P QzmyGbzIyqpd0SFjlJzlvQ26OO1NW+W5q1yWN1bgXOivwqYXWGdLRqrze3QyjcT593wqN/Lf5FoU nS1xpsXAzeKlwCW5Tc38ArA7SsYn3BTRFc8Oyb/Wzm9tLCo/wJHDyn9DMTf/kn3TxBfQ7BSDfqmM Jg8x8ZVbJ8gTC6Wy7oabBzL34r2tznrdsgm4PNgTlJEajPkkdhzhecxD4aGpRo0qRQRrfTud7Mze V49P8U9kC8zzF3mSFQEN45MghlyzJS/w6oMZhzdtvH0MMkLmm6J55jQrjD/MmOpoMG6m6o9S7bgZ zLGok/elhTN0YwpezWoJ8s4XKgvpp9z5s5CH1AH+4M/La2tWKpGjn+6fgaIqQfVLqSetEMayZL5W g4x8+tLc/wKBoX2LVdScspDi89PBIxPHEj8XVVjnpwFQ2ORwc54wYlRYvMlhnNfMk6QmKZyDsb04 cLNCOgE8cCEU/NXXrmFoCj5BV59wYehYjW5rJb7dY6cNdG27z7m/gsKakAy+MsZkBcxY20ta8ujf 5PoJG6Ih28Zezexk4VfWoybDX6/Hi8k9kUVOHNFNhoqsHvv5kna0B70fctkMW/PEGsemkKX7VlQu ZP9243QAJSAesf1tiZIqUpwx3627F+HhAPGipKuBelFtdRXNcESyUBoZrPuF9C4QLjmUOise0g8k QLSwOKKDl+3LuhacLJUhLjLZhcm0WSe9BFx8iM0WxsRxEo39N/BAtAvdYt208h3w8AerunI+sCR1 ByJ+GV+eG3UCZjgcR+9/VozqwcBCZG72hPRCrf7pQxVwpqrTtHc36XVh4/xmtcceVhtsMPcVx/F+ PK0x06AeV7lK5kCUl2nfMSo/mr/+auY4FjNIRCa8yRfQPWTsOCdVC3cg0fLoAe/Fv3L5Vg+RImnQ YbEw8V8C4mXdZGpMbDS96EKSshF8yfCtsnxpuNmDR10S0VtePcn0zDrmum7uQH6TN4e7ficj01wU 8jL/vhOsGloFgPeJ2T2beG/LK3fXd4XIHAX88udns2ReMK7JONlH/4qwXxl5FKrMwzQy3bLwGgq4 m2ZUcUClHuAuMBFzCa2PCNCohOzTomBJVd+uFTPzW4ibW8rK3EhVDAgBFw6sJLTCYSYHO86d83zj souvG7MPaMSsGShxZ5FyQXGBmVfPD2CqZALYHqNqZENf07cH5sfE4L8L4+7O6sUcrb+Npb0LsWkE aewWKCLi4QElc+zRvASHrXDYv2bvzMc8lOk9fnThaqdFxjTMTiVr8BugLRnBSECgWUIsGwdnKF5R ADrDY8/8FFuiFvsw4liqb6FQdHROoUfVX6gVQmJNANCZcGttmn61FtAiAHWT6smZeC0RepcxyubY RJzldA8EUPuHQweNwtPqEFCUbLTvZMzmSs+ToHvnOy7U99iJogm130ZiiGLzEgKKPeSruhv4xHVV pK9SoEaXneexYJPF/Dxr5QGXK51vpobQeN+aSTEs3aEmnZbAwMtNfTP6bbibpJA/ZtL81rJCv6da A7rQ+/OsOA0VMvGCc3gpDWJDfoEs6fhivba+/06Z8SCaQIXCdS0Q1RiVcHw+UA5aLwMCJ0yFNb84 prxwUw7Hx/3YTuO/rlVxEYjAuz8WSCLSndjntzgGDfu0FJDvl03VUlx05elYViplu0Dzx0wQ+ffT BKDasDJlMt3ap8NZ5dsHGwXAc6MUM8btAYaoCOssIo96rOawxBHVnr+rqcBC3GVnnYJaPQqcVvY5 hsagQGLmqUma8Z048eCjiCPKdVPPZon6SfgMTOapvXaVP5eFRaWok8YDZIeQCPcJ7vNX6ib5cRXA oueUZzdXkljsGnm9SjTKFjoJf935JUt9vBvdzpCjZeSdMkUfvpAtHAiovo0K3mKb3ouOV7xYcRzR gBrQEqrC5PZjKcT44mSG6oDZNABCJ0JbEgvXJV2d4SzdMOdCoKLV53TArZCM1mY1fm4UtE4glFLa jtau4K5M7dwFZMiR9aePZPUUcEcxcbQL8mAwNrI4qklp1utJUh5BMatlsPLWFoURCxMmMpe8spNZ xdCtMpFccKC0dTz0eawQZyLIbM9SYj+Y+dMXrNhYndaw8SFOgZedp/W1EiIxHfnFhNip06mSqx+l Or8npo/OuOPJnY23NCx42e0aSQy3JEET6QmwDKo2PF7CadsQ4oUd5BWCRG7CK7gMMskUHIiIPYnO rtws9MrlEHxdAas4XjbT1WMwxJemYUqcl2ZjyzBmrm5cDPyeCiFNHeSrzQRulRomXnYoUf3XfcIY zBrmmGowEKsmSkuAwLy6PVsZN68uYw7TUP9Zh8Zl6t8o17YDwBLjN8jJNNTcYGvaR58E05M7PJrK 9rXQJzJZYmdKTc7cxuhL8HF7wtxFkyYqPKwD90tGfD26CViakChuKY59zAUPciUW8j3EMXo4cMEi xHWFFgXrw7EgzwSE7pQLFyk1njycQ688CuARfqwMwbsS4HG3Me6sIRAtHjZ1PVhoNcP6LMWIrU6t GffBsYylgoPbTfe8O6tTYu6oTo7RvdiW0tViu1XkihwTKJjtCgHDeVSgeVdbNPUafJMXiDmKT5YC 4c+Ih7u18V6qBar3pRkseN+F6//AYskUxAeYpUuwh9ifxbXfk1Rs/vcte3mc6TX+9ZfD/hbZivwJ cgySx0mpnPLaEWkAjLwCW2mehGmOZVJxucW2pgg5nBojO+m2/+WAG++EQ26eoLuZLqEMsSoboe4e hyztGjnTu5vHVtOHT0YMFXx8lHrOz21k1kWG/sSlnju0eaKFKZjWPoELxhfi/dq00xdvdhuGR1jY uJ1P2Gh+CCgRXy044opH95iRsHfO+dIscQoQ/mCA7SczM5lAtfjuEeXXVSQ/XsgK1n9aeBtOHbso 99R2WajBIGUeMypniu3VKUOfQjuPCapEaksz6Fq9148tokw1YE+HHP9/mi+W+J33QNNol19fG0vQ Cq8G5oVVxfFqMozcuwvKLeLCTYrwptE+WBeZgoSY2pWLjLbw0EXyTXhm7TA70LXNo09EV41UpjNt Jts6yCKP3q9XgSeafukZYENWE4aP/35k0cP7ALY= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block TRcoZtqjn2mG6m34VrAup3Ue3mXUdsp9Svi1yOdUyuJ18aNmZzMqBL74/JYXAGMp7kyUseTthYI3 PrI0QWq4hg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block FPMMqj9RaKUiXlcYwEXFaXQj6iTZvDXB3ovRbqMXkBKErB6okVtT7N25cw0P4DrPAX3uTf1/DjZP g9FGVgqB8LxAQapqrXO27frLQX/jtpP5BRN/3UyLQQ5tmeo2wvGsRYc6Ptmw5XXPXjfubR1uMIvq n/KnJrhMohYd24Nm6S0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block hmQ19Z9b511LayHM++uE0XsD77aCTvi2D5+tVo/slhNcSgfFOCWou7QB72DRXWqLm1hI0yRUpD++ 6M4B9gDAGymLNt4kJfLjIH35OM6bL+USAdP5LzqI73Y5A9Ex2dA7XXtW38Kapk4g+yOtlcspGQ3v mipApCouubIDIKzAKfit6i+3D5zl06BKC5+/oMSR90fI/572drXx35dvozy88MbJh8nfL5OjT9y6 tufG7IpOsbuhtIaWR26UAUyCxZ5GOOwUvB2fS9q4Es/JzlrcdmqBkwl4ixHzLmdkNChDQXjCJVtg DP9+/cLV+QeiYTROca+/iv6JtjPVTSGXYAp7KA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KGFNy15frm7DKeh26HgilQgudk+s92inzv6E6/4SwA14yIblinRVK3XaIL/wyVEMSS/Nvx17YpaU YVWGfrmqIII72ql+J97vctL8UoKOHRk+u89CmFhhNIsJnQoGfxdh8DOXKgydwIo8DtyknF+rigwD Wrn0cHGnf+DzHJ1IlOw= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block IRcwaJ9nbddmu/9RW2bhH0oH/sFHVn1S2tsx6hwo1+XOm3bHWHP+ulk+4hbdqZE1Olkl9QC1qtoY ePy+TB2nSwbY99tK/zHUTTzEr9V7pe7cC+aCydi5fu9j5sMPnFmsQadzUgekG4OiSkic9/qlG8tY Nia8+0GODU2GsN9eE2823xR9kslK5c5LHAFyOnzohuZuaNQpgH9FgGbNWtWQ6Q+SNaCkDDwUMJRB XMWJMBZ7ADG8CfZuEbYaJpB3sP361wZWR2CVzTkDaWPuOvVZnunE0ob6QwvKmIm6q/myrsa7qCip ZmcNqxskerCWcqETss8HlKwYY/ryLcmRLUXsbQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15248) `protect data_block lo2tFyFjziJNXhyZZC97XYl3f0ZrW0Q7WwUD9LVmJ9QBi2joO2dZ8TfhlWwhm39tu85pBzGhL0bU lLGx5TJC7bSGiCErXI+tXOdZbJN7BwD743jxvfTNU2raF5ycnehTY1hGqwT/pWpIC2JtRTQTyzBp jg0TCqLY1rtHmFowyZv6918XEG724JEsdzGw6PjyfRjRLZtokRZ+0zbRXq68SjqEoVWFXEf047xz U1lXxDoOT917H2vpfPYaJlAmCz0h8k1/fCal34SYbx73cHMUWFnCTybEbJmesL5gfaookMOfBxRk sWQIao+sOuGvP38D26sAUf3oTnFHhf4FeA0y0GfIpGs4c9o0m1EYVlZJolMEBOS91rz0jpo2qyO4 FotW+gt3+tARFTW3lkQliIHC7eWV+CzKIs05UnbWOX2SkiuLdqLxOSfvNuWxAtliF1fFNjG0J4e2 FfC9OGxbUUJo1RrpiOuacWpSLpdl4+QKPVWCQuyMstdh6mUS1MWuoq6F8/mRGq7yZL2pdZIpB7m1 FqTQVbrAzKa9Cqe54k3eQnNS00lwUaAnIU+CzSg7CoiosWSIBg71HYudiGoiBoBnZLEqIkt2ib0G YZPWoBJ4XLzNcluQ1Ajkwv/Xv7R2wBRSej0W3uwSBWm6fUAXxP2We4RT2a/8nGQcnRSmWtH6tvn1 toUbZDD8+Ooeq6eb0K8NO/8rJFhNJV7JNyQXElREEK63JtrgaSZcKCtnBW+wsroNhNIOskBUnQYV 0CCOIW97dIQavxtVUm8QElbLu5USzKEeLvh9GD+tbqC72nrYJbHQnB1ohbEHiElv0JwdtOtSflWL pytwBnhoxQ5UT0UDv+wUPioK6HKBPFktp1w2/8kV+msFfnPCYTZvAF2GVF73mpjIWNSQk99VZ/qf 9K6lAwSib3XEYyTtUO7OnwZNIJUwEDWugnn96iYwnYYes9kgSrOfR2iKOJcSmX2D1CE53neDgkVH xkC47PePhGeYQ+9CruOehZDBHHKc/Fx8iiqW1oWzim0a0wA8NBVV2OqueD1dwZX1CZsTEAO+2Mcf rJFOE7NbOnbN0WJ1EJ5BRuVz2S/x94hwZ8o4JmDKl5Pxa37bk/BXyfiPL6ngdHZz+s8AcqBsyTxu 25sSBxZaeLoumhdgEd1YTf2MrAQZF1LOmD7ZmxpQXxUqzDi0fCC9JKUEAusjFvHSE1xwVYpyGp4u JNI5GpLffojoQV8tfutFGd5oTy2RMT9ZAP6bmqaKWsy+rlq4PgDvJmiJxYPF+FxmKJy4Se7UTCQY 2tGopjkFaSVlGV15HPI95mnUmA4BX23/QHo7TwIzY1um4MKqhwtkxITazjhYc0NiEbzJcop6bimU 5Hd7Ad7cMRDj1a3Xo1DKie1GROb0LBMAKcfeNv2zhs1tkeLMXkNcvX+W8v63l3HmlbO7RZi15Cm/ 2BWj9XfFFMG99MOAbLXeMsJqC+dpxdTsOguJfZxshnmn34b5AcWmmOZRX9sgP8wpUknH+6V6v0GM M8HKbo+sm2eHaAl1FWozeJJQUvPa6Wc4rq7pSjwdGk5FV+syvS5mCsU1fEEac9pxRE2PbEr3vB2V DRnHV0llczoF8jgqeLDTmKG4oyKDJBnssnwbQCarP764MWnhOLRtJkEoKwN9+btcZ1VdJ1avFa94 J6sQAvRmJuUd70Mnii74Zk/EZfliu4yf5b41Xkp0j+lywStXrsAZDldoSf+yNBaEMrVsL3IBAJyL BOT1Rd4YxlmaqzqmbsQ5YRX4Ub5NyDh3sZ03W2HdiS0oJRlV45N5cK1OCkUQAY5cfVuPBGvt5GRA MlBA6ms8n2mGPaNAr3e1b7yydC71SvA2ReRI5Pd03Vz2SAqGhP/59Ge75gqaOW/G2IZoUC11UCDU 31QBFFxVvxTiuKYudkKmOFxFBtVpOVX5BR7/lN+BDExAVuiwAlh0Hu5VDxIm48y/OH9B/R5LdcxH Ekw8rrHH7EGDSZ9Fe373bH13i6PTtHSKCiscmJeqMg+iRxzvY+BYYAtvQxMeaM65oZeHO1cwWQAx ALVsCF6TftT/Rc9MlqkzPpIV2mJ55DHMAQWKWb8QkBjdcs/AB7cnCVg07jbNLP4Jy5RTGGXHwFPi MZhK6ZPQH+3FRieYtmnhUP7xTYheG0c8xaBl2Q5rzribOMk8lVx5rTzHrNPvYdjp66A593lzLTyd mzIocbG/auEuspS1QZ37zHsdA6+QMZzeVdz9hwhwNioBFtgScmQzWrGhF8ppCfURQNObhR+UQBk4 Mkpe9DtCAaggrUW4TaZ2P9ZWxLVzR7jpjApAJsYlqdHXGRaWPT0f7AbJhvzAPz9go8J4/wPMJWBA P8u7WpWVrvnCuVV5PCjsTYZ5eaTAG4JT+q9Roq18Gl60ZmctUFnPlsN2t8Iw2nY2ru895Etg/5MR Q5ic1xjhIY/r4T6qcoJurG+efqeTYn3BsbJIg3gg7va8t1gOGGJ5bTW7FEeibIl0IQPwmhiZXcaG ll+Rcykz2XZzDFCJm1kn2DSeQzDqXz+eaB4O/AG0iC8SJofVp2apAQ29vRIxo+URABT1X7EAk2YP XBZBSV6sg48AbgQSNOXltxjle3f9zd4+0jzoex3KqFIi5B6Jhz3AIemALfWqZnvhUsy3ZD+O65+L z7iRBMVTD+Pzs/xo255Mwm9jeu/MYWRlZ68lFOi3zSBcsBItIlO/PPOAzyOyIWhU6OxP/SJDjuhF mE9ensZ7JNQAbDlglmjZ5EnmdEmyMjtRpUlTxLYNlwZYtyHFPLS1XmiE4UoTB36ClKq1wMYEsT46 j6OXa7Ae6Sz1zjvBXSolixvc4Q46i3M5pJxpTFpU/6tMz7IXkQGWUF6BRt9T27SEIResbJQgKlVX K5pPzrUYjfeh9dwsNU6un5VQLsQtkGbYUdCGgwrglawDVwvo+7GCXnSpxpjPUCGKCnT2WyzBmfOW Pi4Yih/HToHDNUkNypdJEZJ78w27VFhc6XgQl266RK3GoXcRm/4sxYpLwyPaWDBzuSb7qFS7Kfac d7s+Sqss1A2KS0zvlTMBW6j5yXVsQJl7Jbjc+1MNHWfsn0q9rxLoze2HT/OXytLWmfeOtJiPRp8J IPylF2iey2lTQ0Il2bLWnN/Twl7v8RsHM5XyIJlJaqJ5nhekSeOURwG5TsyiIfDcKuc/Gzpe9xgz 5t7aiOCvjTs9UUbNZSIgXj4tdBatEeuAht4UJpVXkWheAgt5qasssjYGpMdom+S+NWms1aa4c7cU rdrz5h2spaEGbgSz61nGMAfONrXan/iojpkD2AAiB/Gb5qug/KrwLDvp6HwKlPWXrBqwHAyhTPEh +dk1VMcvLdYrbwtUyZVi7JiQbap0gpDxQtw1Ce2MOTVUzcUMu5c+XRYSTaCnwMDZVr9vQIAFIKOE jgJSLbzPtsdcy8Bu1LS7pFjY1eKlqWq1LcfhJDCyblf6cEESmsGivg4uVmK6gp8PsPDNWvUy9zM+ q2us3j7GC/daeIegUa4TzRNbtGrBG3yf3zJLs583MMAGQBbczPg9dtSfI/AlQX+5alVGtbNoXrls ER7y8p+bbYSX0Rsw+ytWm/JkeKmiNuviV+SCxQVwdx2Q8CC1he63DAx0GuGOulCUdXuVidVG+GWu EGOqTIyMBG6qTzvG9T2dhRbujJLP+bWec1FYWqjz+YEStYcm80SqY5ilecjQdxJeE7b1PmYgDxTm /iqg8EJewLrF2IeYECtFqYPf0gFAMuWifV4XiS0Abc+f6+B3tCMDwC1yfUgcekyCRIe5P4A0Sql5 /3KWdaeh3eVrZmlsOZrgibyGtY2VofAGToxxZgCP3SvOncAv259/SlswvHOHEHw17krFaMaqwCXt KaZCUgELk4LMZwxd9nJc0AHVMT8TY52JyAm6C6MtRsL45cs8fPbzN29yicUJDgELyqd5OtLx6SnI vwdBT0Vxgws/He+tfW8WXytpb6TQ1weCZBOAaQtwNfhSJcV/CrQ0LMaDsjCORTqgPHtlhrDi6Whe s8BwlZfMZK7DjdE7BpbMDXkpW7xvwxjRxqgMdNmwg95N3EvPbmV+mYCluh6wuXgbJ5rxsKJUtKvW p5aJrbnhIiCATUNOVAABcb2v/V0ZDNPEnIDNkgN9lVy4qYdEIuL9/nuDeik9+0O20VXyd+R8dQN5 a4++rqVcbFmQQfjkfaXX+kiYIlQMhsmz1edAXnOT+UNQH0oqO6GtlTyMRPucmatg8js/JS6PVW4U R8Sy0xjX0CmVYvXlvVbfhR07kQjXfznA67gEZblgvpXTRoHX7Sr7DUNE7QXg1g4jtXgjBvVsO9lQ nQTrR8HadMCgElnYWB1MUrtROAGZoTnBxfHfUHgsSDhj9Feh9Idtwbv4JImkI6DiBrpiG0LQsYwp OsqCIY63+3K69v8JsJqbjGRU34iQm/j6nP0J3YsZ5iyWetQcQ2TqQPzClr10sj5B/QgVQTyy++Hw +s5CDh6ocLBpj1KbPY7um/k56sK0aOwlgg0wSqi35Av5YM7C1+wwS5nCmnNItHXe+WslwIVX83hL 6MEJPXqYQCfS9Rg+mVvASxz/v3FDbVwVKljjkFeJ7oxg+ho3TI9+lNBhY/B7rkDeIdIFgZIU2tkw UeGXme8J3NK/c4gOPpwyfBIWcKDThmGa0d4Se8XxxBtQQYCs7oXYBucxlKVkr3k290pU26hnkyau ULF2ny043WWmhqXJWDvG90oDuOI3KJftR54o9hysqhRD5maT+w04buQrPqf/xgr/vwEAM4VYTE6Z /Q68yFUrPHd1Q9zfVU8ItZu6kvc/iJDBGxiY689Lk9EKs5MdBis+rbZgKtnHgKQbkk6P8hvQ+Hz3 QrSvi6c1abPqfQTFzOl78QvOtpAxQXG42aYe1cumjaTO+YwHHL1/OcrmNug2WDB22+B5yYspHMMr pghggC5YE14ZK6SLRRyznvi6/0j6JhUfVvgPAp/DWQkh0XCEcgptvAjjhDXqI/DV5vcxdpZui3xq DgaHNZnLlN+AiSwhiUvdqdcAgAgbqWcppIqvXreYG/5DLtlu2KYqyFHwzd1jufRuB79FslLk+8kc pE2+4rpbb5I7+T2BfGWB49MciXCEEmlXlHRbI1aj8FMCawqNYI+SaTxAW2Lpb44opWQqc6rMs2MB RtxcdjCq6WcCe/a67b2uEW+Bn9IgNF9c5/Xd5KsX/yzm+GRQv4s5TRgvGOd1PmDS5CXpmgPbNMh1 7maofr4z/xm46/gy1FX+/cZzX4z8B4HWNSq8ao+MokF+twMaXFVVOoh19LMZeHpeAy+yaNOMUlB4 ZHByjXkYxiPQUoEEi8ZxUkWNQEXBxfS6JnfMTM6PitDDiUaH4v5mG+cgP/GyMwlwSbCVuYtd+ZLj Z1Vo8jk1TbUy4YwVZN6YZ7k8H5+bnhOdSlYm5VsvX4R0RPPfDElc+ULn1p8VVbAP22fDB7vjpg+r Fw+xC6TL7NY/It4Pt/lGmgYLhdOBItWGqWEw9w5BtgvKWICb7oKpkt0OYoL8RpgVrDKL4TZFPHEx TF+QEEAWi/qBHtpFefgmlcpp0cOMv/1SyDx/YosFuPM2nmj/S1kIQ0nIphjSxRlgDnTVx8V34pk8 BfzcQQWpAKoKcp1Sq3ls5m3tm309Er2uvSnwkiR3Py6zHkT3w0Hi9++VsmPe0btjY/REO7oyFVg6 R95dXw3Yho+iq+RM9mchg4BHOre9/KJbc65qPF47mKBnO+PvAmU+hl5lsEamo1BPencnba/P8o0z SbZN1wcIzlnbS1+XYPPlZO+lCOWnVCXwBiMxPiNzAUKHUY/ch6KpYGM4y8DzbzeWJKbQqJUx6bGw Htq8GEioSyFGOgSLfAgprrgSfvBbNnr3o+2XEN9i06V4HOGGP51M0BuhOZxsXM7LC17T2bno2lxx g3MNBexWh1Il+f7p32f0p4zchekCfXuxi9ewbdnsdhoTZWGMx1SR50pKRuetNKn4lG/wCYuBtMvh eN5mHMzz9sNs6mExAUsCDuuZTKFm5ozosPvCWIhsviNFQ4fJnmOAIQCyuybW9MU5ua9T08mNXEEJ 6lGpuV7d6XTL6AEyHe7ZfR+GlGyHtWFmnmuNh8HgVvtx++CDnqP1/WhsvQ8bDSZuW3NviXmCzWw4 Gt2pKlFzptQIC6Zfl3RnuK2c94Manvfx8P/8eYsrotrR06wP5TPCdnELK/6Umb/fbqzERjSedVtH C/XNkMeW/0AbeuNKu30powhGQj5XDKwjoJRQNXdKllJRgkWHMdkyLwAMMh5XSq75MVUJ1jGvRFpV kPtMik/7OSZ9aV9QgtERkL4tQVIKznYjD6cNl74hKrilOaPTxC3MnGUwgWgaMnkDyTGPbgI7IoQb SmbhzcikqOd6IUbBprZvw6ayE0OvckZjRoOfficSz7j67b0DUGKTTV1nbVEp4Ob/tBPY6NJsjJKb z4sTlAm4ozcDYfpnhcmgAHuXvHiFFBkMBNZ3rjYT2cEriQ9TFLF3mizXSvt6Y9lGNjnsELiSVkPZ RFto74jJku8Hss6xrKO49xXr32YVTl7TgSZBYBEReZSDER0F/9Smcx6PxcaJbEbHcoIgaCinTWDr xbClLt//kAW0biTwE+PgAgoIYlf7HXMO0iCrf0mD/NlAKxr1hLVveiz6c4/fddjlT+7789I5+4wX uP1L854G79hcQIDuJUlxMBN20YgfOFUJtzkDPbG4Y93b46Rzs6fZn3Zp53ui5gkJRnKQIx6wllzZ KGRD0se9BG6W4fHDS85OKRa84HvXcWNex6fUE86DO4fF3z/VLNoalpz8xfHzl/1BbFMTWoxvBuex Ewmn6Z7qXBrsz6rp605BFeNwjhcEl5rbKnvtx38car/MBj+kpci2RmvwtfYvrnFnmonQVEhlqqtb izVSQZTvDvDylxyI6KejyO+ad+O7KhFt1ObvtioLPhjtD8o4wAKHpqAR2Hu4XrAlkqR3GgQi33AY efXDINfwKWhvU4CTCyYdxJoAZuCZJp3VYpqygSeZPSM5WeY2E5wcbvPG7jTqIlnJ7NPBPkYnpns9 giuPumUmUOOcVFAh+1CMZW/i314PWY6dqh3jiFAUTMd2pAQlhzp0COASBkI8yHscCuL9e76LrNEl phK0zem4ZXVqvQfeVpDjlV1sqjkZH1bX/jm/plr8dpen5FxOm090bHN1BTwSx3G/mdGH75jaC27s ceIOGoUwoN/jYig7YwIJchD8FpwjGlocKJDBXKwQcEkAFDczNefFi4ziWDNI3YZTq5+thfPxOEFj TGGLOA97s/C58H/TQ02vedrKqR+cTEiVINTohDV+noR/pHiUWOgPDa/QVi9UZh1pv/uISiZ1dRQu Nq2qa1skuihcQK01oxJjvzePeXBQZ2qTzuUpfd5EN2ZyRny5dHBXJVMGeIYHDtTdh8pGBwDlAxYl 0G1e3k6mxqAjAIbYKg/fX/tnFMNY8haPyljcp4x2gBI4a0AZa6JtZpg9UfSlBe+Kl6KF9L3xTYMg ova0I+v2YhQPCmumDF1d+iDw3Fqkk8UoOkhh8DPP3LKU2pZJTLBSe2V02otyUo/C24nSt6n7MfV9 tTTVIzTvDeaMXwCb9GZxY/SeIJPOdaKmsmD1fMSCCsnr9aNmX0Y5pNUJDyTIuNBZAqVg1e4N4/bg wI/4dmn2Je6ixx8VUYRktKUsL6H5wc8cK16cWLMq7/XpfvPWADFWRlKdxzO4cRhSiYOka0YTRX7M d+cF5YXSMaXGd2imY96irnT526iu2uUVhoEnfCtxxvPuRf4jP6dwQ/W3Dwl5mjf6YgVw9LEvQdGD OtNhvBnzj9oO5OmZNsPpZlnZAu+wCFCaZnEsoT/8zttWrCWQYVLlmCMDGZqkIyYOmKZWq/gccVvR A5doD934rvPOkUR52VfkpIap29Zb34WqexqRn/0IC/DsFN7H73s2bLdm5k4vIdOSUJPrVoOMlunH fEgOAXDejR1OA0srkMW6DirEbc6T+3BH4lBAh1VqdqsQEAaOJZg2uHj7x06rVH+ZKKlimvQKRYKN vvaH3/maL+3obAIoMsvRXtzFP3BVjPVSDWlrQngRtmjDMASn4pDgQPic9xmdGeLucC8wW/D7bQqG 3vFNQaWdOwNAEAJg1Fxdrw4+FoSZ1+tJuaem1QXlLZp2MWnmc2naNfy0+frSvhWZLnd5HTZdmjZ8 jmmFY+wYNqnivDXnBgXQt+lTaZxmbiTsBDYd1LxnrPzBdWSLsYIHwSc4qknEunO5DFFeU7J/gRBD oLvMA11R0nbZW8FqjRQegzJTfXB3hCElqcU63wMkM3BDPrFqSn9jMY8AtqyTZmtrXoXB/JgzhAlu RWpCGYM/yQU+VaODjSS6ahedrwnZfEucVY3S9uIJOiCZKDxQP6gvtJwHr+r9mj8muQoOva/k7shP kDDFoYx7yIzd/PX18UAnuQw0swQiWnFq3Ysamrz3cEb3w7KCWCE0miZadUqagWh4Ui1EoA4BtTCm XH+ULndTI8KXBTQtdiSaIelm8c4+Hsg0C9LoAmezce4IxO4XYdeG5mTOuyhdvbaf5aZPhYiHfCiI 5byWtx4XeofT5LYNa+4oJv6J/fs5re14ShP++4ZKMOnGmUcB0xqymmMzKZeFzu5qZK9C+EJniLlZ 8X3ypMzEUK9VjeCEvjNhAi3kE6NAMjguWHtVAoxGk0FI/+e6I/x0exhvmD6+PsENXHhXNgiGv006 kLSDnkx+6CJgztcEI4r3sXw3dTeiaYYzJhTJUw/z+GZmodZpeCbVrsAMv6bW62Ock5wdtXqJagLV VSPRSxklebpditAz2peVOrKx6ekkD3hlFH10CWt7N0b6mlRFpGzRIbArJnIkhZImFhfLHYxrdG+u Q5QWVQ/qK1qjjWUkpMLZn8KZpRWY6Iv6/OD7Ms/rIAfGwrG0WQEh2CoA5kH+kVtf/KjD0kUznGzs uiq3DYtmVnkzXkjgSTWONZIQMe4uUy1cDbwde97AS+8lFfBBUOrzGikwN3CnatU4RSReVfMfsmj/ PiUvI+VVIfB7fLmIYirpkTyJlLbNqgCbxTC3/YUKvQeKsgdPYRZ1AQ+X2EECrxumRyYdjdzdM266 q/ngQdXkaptEq+pWick9hXGMZv4EXwb/JiIrIW7ZzIyeRw/iWU9yREE99wH8dhvG7F8ZuJYODoZq Z16s7UDgdwZUz1WAASUCVAfQ3Dz4Ys/qpMTTBwP5weg2M2dpSnI7P61q/kp34JaDu+mDwNRk0OwM S3MjEJmn7M9bosNMEbdM33rNvuBPGrGvt+N2snTNy1pQCQVZhjxY2RTzluBYwLnmqOulukiROf2T lArRBTBcutYaPwNKiLDgtbC263UZD7nXmBMnFbxEdHQ1ciWmpHo0nZ8vvOpG870/W9B0bIU00Zf/ mcQGtsdoYUq4AKCGeYuT86AIsnm9QubUYTdvBvU3355svrEH+FrAn85xkA6Qj+KEgjcTOsEO2c5v a8QvtrsHm7QlyZz4nmX0z+c2xrfYF4NYwB1W5swgvEVPbo4m3MZ2Px6uQ4tZ7Jr+wdowt/fLBqCX uejBBNkZayRvIeXXegOy82MWj9Sj5U8GmR2j4Ufp5Tz5cl09egSavAg314dcMTUbqJ6jko/G/s0z hal9n1np6/6hYCO88KZOCHYsK3yBMSXLeTryLK5iIwAmSKbm9hltXEyqJiU/Ykw2gjkbjNYFYZyK OHlDaFUUF8Dhk5sLXXK0BwJjB+7JpKt9g99BATyq2YOzoXh8tzq/r3PIhNKefbBMhJPdvtA7oWKl 9BfWupKNcvAuMYMENnX6MVjyiMEoFSq8Q2c0/0cv5SidXn6pvp27hiMYAviHq0/ii9bYOBmwWQID rFWstI+te9vAVdgtKckvIK+bTRd+gYyq9379EVHT83riumNh79bKQg0kgGASNv1Uw7qIDGI8AYe4 3Cr2lbdTaIBcgw2Tvs6tCkZTOj4tbt90jk+jhkBt/kfzyHkFq/hU1/tPwEg+ei1zO65wpOl2J/Hj zqdIelYk+Q2gMDD4UO7B4QJrq2maRaOh3NAPNsNttqNh9PtnRIZSIhmd5DeNgbe4Q8JUB1BBA/Db JsHJ28cwqoLKRQSTa9PtlDgLzK/NKIuy41SAJ1FSZmQK+bUhGdPEwKMPlvNOF86H3w3FB91qra5r t13g66yCkK2nICykaW0+ctvVWO3DnQt5dQNlWp3TtwC+UU5R3WJ4y/KFK7Tc+hyB5J1440FQbJoA mpuZepfQ443UsJjyxTanoZhHKOD7Yvpu9CUn6Zp2ktivQoqNB5T+rqM1EgThdTTt98MM8DcwEg1L cszhN8IqINLpY4sFYtBhA2qTuoeWkr5RoLqT1hNi7H2xnoLA/L0wQHLjIKKqmRGyBX70bMIj9bsY ch3AzRyhbdYrUqvruR4h/V1egVCDHLMUhpxyGacBypyCswL6q5ji2LFtQ7nVCqHSOqJc5Npym9fM /UrTlm/16RpH/DuxDBck+pbAmHknMlME1lvMkvsxo8vMkwGvPuIKZr7n+S8Om+Vv9ne6FuIdbzgk iY/KzqzQBx92OXH0B5uSdtUeXsIalMo9BN3mNG9UXV5y5BJ3MOvtnBPeTkI/N08QG6YKJzUS/iWl 4W/9JSe6d9oYzuciEUrxzlxX3HUS160cyAQ+ODwTRnDtLi1U4hRgGFgIOg8BwEs2ilLtuXDxORKl bDSwNX4I/PW/qhR06nNwbRjyVfIi4VEn0ULSFm8XIPzEJ/t+xQsSK8cRx3XShqsDrberE4kcF6tg TsuJ8lO5r8rDwKCZOzPkOktohxlDzfICQphnJ5xRK6sehksPxetSeYsrGBplI0VPdhJLFAsnUFJd Ev6OqHdkRzMJ8+CdkuLN/snC4oRaUvANsK0doQmZ9+c2NoNuhNcVod8kKpw/3twWUJdfa0QIGJyX qzI+dQhuU3lWQBhEcJhG2DzZaUbDxrbX3YCGd+k1wavEf7VqLSwaTmmEwdZ7jtRmuK6HJ0rRISjP f4bD6ffOZjQ6jYL8ORBWeiI18SoNK6YO5RYGBfBdFqyxzJNmYSlofk85khFYSEtHVqecaPnuaHdV A6gZQC8sgAX1dfe/II0uTSstSA85bk+rpeDP4VHMB0X1lMFwrpVV9b7Y1Di/T0f7rQn2P/PPC8vQ 4JLGXzybsadQGJ3W0zxfq6PJLdRyCfJyHIttZEiARP7nqBDcTIyFCg+PvJcQZ768hNO8jAeI5jbd msSsFZC4D3N1YQDVZwj/7vmIilJ+i9qJnvUTwUBySXbq4FY1JyZSGjV2GWZ29ruIU3MwbAdW8m1S 8XTvHsbcxiaPOc/0ek7gt+0+b74qNTeX6VWf7fYDz0SZaKntTeuiDevjmzuF77fbaITL/5ISEq+I BtyvYS29P3b9B8LA9WC1N7tSTt6E0OIJxmwZlujkOJES9mM6Z+91WHY59qFKpa2siTL4jl/unDC3 uOuUsFOdpOp6OgWVfA4U88/JJrs3XraZDrp7DLnvDxEiss4+J8j9p0bw9hfz/ZPt9o/6Uv8h+z0P 0FRGjl6c7lSreB79+W0JPk5s5gfUN6tTwD98zYuEjyv0TIOWxsgQQOUE3DPnCEkTyCCwTqLktu3p ZbAGkWSivgpDi8580gURDEmQKDXhnks2yBDsXxiZx+N+UqfI8u1RYwL7sKZVDsjL+5mS9igixKJu mi6g1L08K6EDnZY73csqvUrwEVmlRdOTzVloSY+YdTJFeGdmKYyB1As6DDkFKmSB+eztHKVE6V7J bnAUyg8DRbGxU4KXgrC4UiJRgUaSYSVe8KHSshXafQ7DPFMKCB/GechX2JL7p8dmDbJWRYbq3c3D VMhRwP3vts5oXVTfCoNn4Ep3xMja6QsusMNZi1papKFd3yVv1l4skzpTWAg6o9EWYEnqzjznoUT1 HrfRKo7S2KqkgK1g14Ipvf5gs4HrxpzJEgZuUK8pGZH8jbP71j6nuOlCB0Hpr3ERm4DrKn3/DIFV mT8lJzUbiW+KEHjV0PjT9SLWH25lIbLWQIRxB9dSjAmOM9k0j1SHqlfPU5PX9UQi41XcoqWF1/bf HnAiHpCNxFAyWodIw9PzqVGZ03ei4Us0GAC4j0PZBcaZ0jZTD4SYgR1WAaom04ad5An2SupDMqD6 i/zj1uMkN1ftCXWyyAYzEknvYDhlGSGqD+pgEx8jyNJwbLN6dijDF8o4EwiSgu4rs3zkTetGVXbL ZZiW6gvzetc8r8CVSkDS990IslEBE7FEog6tPOs9nAysN4zANCHAB/syxXsIqyaqDLxj08oCHAN9 Ea0E1TcxVd4p5aMrsZtaPXUny0WsQcZmrVua+pUORYcdpMtEpDhvNun7+d7Yexd7yMiL1GUXbGBn 55J7dkquCalG/Xmy9e4QOaxqOqW+fLjL9VWuDLKU9I4iXyc7CFC1H+GtUT/gMBymfmMxz/Q98/Yn inr8+5CbwWjD7si0setE2IM+NeUnQa/gtS4vfFkIdPi00vXllAM6pSC6/0QeBaWa3+r1czPVFObj PWH7rYqR1ooR25vC9ZbZT403w7uhulpM0H08ajEmWIAkOGsH5pQS088ug2MLhd/hO26L4IydGeo6 3NJdiNd2TsdbmuJoUSGGh8mJf7yFL20HUgmUQDeoEGFqgtWO9hcieiUbBjhXP6almms3b+QF7EB+ V36WocNhOtAOiQMUjP7amBx6BWL80y7ZG0C5mf8ceE1zlOP6JSqIKZ2W2ctmKMKCzQDQGvCAR697 3oxFl7KClk72SSKOq15uzytrapXDRz5aKpyyrxpphsZ65VzcLdqV6Dojj5fnaE4u7A9xRt46mmNI R3KCXahZ0diUKnV5O3bZX7GFF5iaaJHwiBCwxadX6E52fTHqJ9yr291p4tG0pUlhCni+Y4O37EEq fwWvrSrkv3NqI+z2V3Ifl7Zh1oY3E5v+/mO05jsJmthiTfptmfo4jfUKFl5vHlQUIKwDvAGQUvAg syriuscwJEXegC6+8l5wdH8flHjlXHsQa8+uBEqX7KqZ9C6wQSIvc4OmKI7Vz6KBtqEuFqTb5dHq /as5/RH/jGlNFwZjxlQZuD71nrhq4+Oz/jZbm1LpWZ5NXkc1Om9bx18JGA+1sYR1xe5R1zs/eay9 yQETW4yLT5sKie3PwxLcmjPq5ttZ540kwE4y/K8ZEX0dCsJvwBDTPvftVJVws32pLrhd6lavVuIV c5F/9O9wt3B4X1NWTlchrQwc9yKzvp5L5o1kr6Lg5IQe1eBkFQZX66eSgK5cWPkdqyq4yMniZEZ8 oYrcPivSsc4lOI7GEYsE8wLnE9clMOPlm9nriJxTDZ2i7/HmnL1Q0IiPMmg9kdgtz3VlAuMQN9RN R1iS9ykHnegJPyKBWmIO/K/BrHJen7afnI62YQbUp0Fr6IcNROoqq0bsYmSBruT3W75JIG0Cc174 /PyIiLpmjWhJ7sl+686Ml3/vhYFFD5jlDOQ8DLKpSmaMscH50ZsQihpoKJhP1JNtd9JrOd4SdQ+I px6bNnblous1n5h522nqwM6XosLtL/G87CJ/bOSeIdbixbyZHxJXOIxNuLdRQPb4QrqiDHXMQeah eWPEMuQpf6dnYjM1KnkKjxh/CxJtCRmkUjJe8WqDLzpdI6l/+L0JhoDyQuH/9S+V3bgmBC1C/tRk n6xVuQr19CtS+Xg8oQP9zBFToFMk0fN88FqXnqAkJ8BOu18iSPMpTTNWAs6kNUw84Po/gZ+fcy4X wB8bdIiQEAAztvib1K/zwMw+cMVzX195FEMZAJ617/s7L5wRqluMeECknM0HC9AsZb08tQ7q0FBH vl61Hyap/2Vjte/O/g8RlkXO6FICuys6T+qFHYHwrNzhUtaMXqkdGddnHVh/E343B0WBE9GXpeR7 lGji7OfIToIlLxunpXzjw57MBUgjLBCzZPsPSJSa4io30B0kMP+PCx+qFp//LncbGBwtgPWkAgHL IsQhLL/xfkZh/36LEGgpPNlnS4ETUoifcxEVusUOVrwv3/tleOCN1JMljt99t2sXt4GRoGCvQZaO NrVh3sd2KrXhII0gfcLdpbryzJwaZ80HMG8KCqLC3Ga0yT/FPdDa/eOJJ8KL7fQtaDwXSCL9cOhM Pe7qiIINL27Mim7MzaFHp5qUtpYlVv/Ex8bJ9zNFYLn0uO7H2Sn5JOuwuqmGkR2SNCz6Fupox8/z D8LVeAe26qFrZOsLD59zLdgbLl3asB1h8osvKcLkvCQCSXQjhQntaj3PjjbVBNWrOLztNATp3Env v0FW90WhtZiU9R0xHi1sqsHDYZ35slEh9gKRRyw9tKM9OLvY0Wg4XNA+mhDsls1SiQbQOqC9i+3X IxgawQKwDnEkrbn+DXTaV2CTV8ak6V9WIDsfw8rqGcrGaII+sQhmbbfZAvM1+uWubre3kQlezwuK PoVfogigSpV0tNW6S2/LnMr7OOLeHvpFV2ikQWTbx9oirYNSEPJbWoomWNdL8HgkwDoHyknAsPxN j+YV8KYlzrLNeOQqfh/dZ1RhZbz0DJMx6mPpZSv3wxe/cnCuLOq/t625aVMNRyuqV4nkGpV3bEKb Sq5w/UAdn289Ylqbk9amvEHPGi3JViwXmlml23kzleLaClulOSgtec660aGPQ+NkmvpfRKoQfS/Z jVqqGAIy+pKJbg1ijmXawOzL2MWbm9g1Cc0wUsDxw1SYbxQ8ZR7HaqEyPcCy+fJi512Ts0OLt5qe hnkaR6rzQ610uluGwmmaqnNe/JpmSETIqGhAZYlkGJgYqLau80r9i3vhe8k0QMKSaOnaLsiieYHs bR1H0Go+tU/Um5zKqEtjIUYxEFeFmLiPdU6qFVy1VqDviqJnMgToA/u4jaqI4/WkPz7i5Jwg5/M4 x8MIXD+CMxg4sM/KbEfro9Xcc9ysF5OStAOT3zn3Gs7dZkLSuboaLGS+QWJrsVH7jmxlxyQddLE1 ZuFeh6ItwlGKXuitv5MkMxWnZEOLwNPIHF9CfqES3PX8Mu4nHsdRb+xeNrbTC9mYEMvxQgMLtR8D UjQlZm9qIBKCdU1Qx+ssRmtB7hB6HpTDFkCXj7fw5EhPX/TWHxqRYe6TMnj2HlBZVK2FNWIwmoD1 z2kUSyWa2h/aKvRs9G+nWyPmT0j3dRuZqMkZBAsJuJp0iGYVKPICWos7uo4TYNqm0rrcN3UAhljZ WGlcu1o5LpU/rnRV0wzS2X+YMTxz0Giaz9gpJ/sqOdgBiuFYXJDckfQnKeOdLesW5Hhil6CCc1Uh PZ+acLCcStjGwBl9sxyAdpiJZGhoSZ0LyUTT+x2sWKi14HJ8c0pIAMvwq60AEthGSTnAXDu8y2+t 7WyNiUepk3gURbhqidaE/Pu3frJMq5BwZaFbR70Mj20NE7pA5Sg+BxQsaysUV/Grmfc6iap/u07k hQ0d58AwvkMOCUCRuVpGUzfEY7jAUB8logHqIYRt/Gg3y0TCL2GKpRYcBw/cXruXF4PsqphMbz9S EetAjixDXFHFuIwiRAeTjSQu70P6HOMpsfpe08dQVthvCCy+PudKH59SdelBTsNBPVcmyIumGsLb p3Tr6N9UjYyY90j4y+cAMp+4RmTgEegTSMeUbpbVeNYUI7Wu0H7RcjrVDrWSxtY6UPQ/Dx1hn8qj 5fAdd5SBIUcGlrHxWNN9a32r3ZZZEOsNVfCCYmVv+iAMDe0oNAodyu7w/q/qcwppLWxXUAMEhqSv vt75VzFD6UTBN6Gpl0xlB6ofPSHMtOTyMry+w3kvzLxLczALwH5vuuQScuo7eMKgVJ97jh/NbD5r 5mWWFGiiYGToHBdP0Yp76oOepOPjDn97NxkHvVoXYZY09wHSD67M7DoZ6mFay9tgR1MjVJ/07MrJ Gqfz5hsG/96fNz6NVX1sGtS4n/YCo+e5vOdb2lL9yfknjD5VeFRXw74rt2rZRVT4OGEKPY+z//f5 MErU7acWK7pqGvN10o4KvM2y7GPDIOdszj3V+5zGxaRsbenLDNz/YtPWlkVihCzomhhBXLtGRH5Z JIHrEch2Qq+V+cI65CSviLaYXN7wqiicv7a5JPIQbol/4EPgN4OFCYQx7GwDmjp8rX8jBjtws6fe y12wpztmaykpcO2/b5mJ+bm9tNHw+Z/vekRgHoQEBAAIaCdQWjCjxstRIm4LHDbTKa3gsUGCoSg2 Tbw/UUgoj+fFcKvzt4bjxU+RWbQ+f78UGB7OUEDSVYLkqHAfolUvw5rpm6Bw8FF2HsrtR378Iv0h J2pm/4MwDHnAxQVkpg/MDCQI5JVCaO8px+xlGOMtGC7/BMrIxTjYRqo9LpFGIlOwScNgfpBrvjAF 3yqFFXduKrWYOOTsTHz7o8jBXyo5MP9YEw0IiUsmX0Ykj+sSswtoOk3arr11bzp/SNylQ75n2S+t mSAvjUlBJW7JuAwA218g14d1KrExYh1l9OEOgcmp95E2XKHXZhmRgr+2+EYAvsMiLWwm8kIl41lt CGDTL5/3CqDKnHHzc9p858NOue+6MTuwSopBPSkq9Ita1y9kgJxrnJgafEl9BX3l4sBZFafEBDWh epXRZ0iTEE8b4dzZ2WnR+yF7sV56SvH/HVsJxHUGj+zvukJmGva8H5aEy8l4jveswxKcSi43vpPl rwLz6soAsP3MixinEYYI8v1A8JGWpttM+VzOMr+zkvLlCyk40XcWFzFjoKrW2dUgB0CaP+aq43jS yWTW75ZxP50PQBEVXeHGy78vMDCIZLPimV143fxuqyrO5X8utlxdTB8FDRds6fGAyxDcMyheh1tN jbaF6wMhWnEYH2zSkI3bG6VsUgLxEb8Vs4jXmF4C+cuuflN7r//s+jYo06cDgpOgqM53SmH9MIlw AYOYD3WJ13Nwr5+6Hb/ZyRksdUe9B1A6Aru73cRGAS0GDocaLdJVVtnqpqoq9jPi2ZzvlUDVJL2s BPS9o7k+dVVldul/SsgANNDzUm0Y8A/EuepyJEYnPZskvkY2kabzB0PR4OGwgpnmAkeXMX+YWAzj lJqDmsv2U5SyB8lx6NOOUKLTUiF0lgGRK7mg4YATGiLsCGuxeomuFVjC3oZzPFpx2ZTKeVNMyE/J VsfU4zQPsCpOYUrbxffaRilHAB6mm9kBpplbasLi68vkkXj+U7cyx2GRBT78H1iH5erJ4L6Io6sV FdjdPw9oOsGREAwYnhl49HB+rAKU3Ja0rLFRz0b+TiF6JjVQHosDcAIJ0BInTbxunV5DazDH+J9P QzmyGbzIyqpd0SFjlJzlvQ26OO1NW+W5q1yWN1bgXOivwqYXWGdLRqrze3QyjcT593wqN/Lf5FoU nS1xpsXAzeKlwCW5Tc38ArA7SsYn3BTRFc8Oyb/Wzm9tLCo/wJHDyn9DMTf/kn3TxBfQ7BSDfqmM Jg8x8ZVbJ8gTC6Wy7oabBzL34r2tznrdsgm4PNgTlJEajPkkdhzhecxD4aGpRo0qRQRrfTud7Mze V49P8U9kC8zzF3mSFQEN45MghlyzJS/w6oMZhzdtvH0MMkLmm6J55jQrjD/MmOpoMG6m6o9S7bgZ zLGok/elhTN0YwpezWoJ8s4XKgvpp9z5s5CH1AH+4M/La2tWKpGjn+6fgaIqQfVLqSetEMayZL5W g4x8+tLc/wKBoX2LVdScspDi89PBIxPHEj8XVVjnpwFQ2ORwc54wYlRYvMlhnNfMk6QmKZyDsb04 cLNCOgE8cCEU/NXXrmFoCj5BV59wYehYjW5rJb7dY6cNdG27z7m/gsKakAy+MsZkBcxY20ta8ujf 5PoJG6Ih28Zezexk4VfWoybDX6/Hi8k9kUVOHNFNhoqsHvv5kna0B70fctkMW/PEGsemkKX7VlQu ZP9243QAJSAesf1tiZIqUpwx3627F+HhAPGipKuBelFtdRXNcESyUBoZrPuF9C4QLjmUOise0g8k QLSwOKKDl+3LuhacLJUhLjLZhcm0WSe9BFx8iM0WxsRxEo39N/BAtAvdYt208h3w8AerunI+sCR1 ByJ+GV+eG3UCZjgcR+9/VozqwcBCZG72hPRCrf7pQxVwpqrTtHc36XVh4/xmtcceVhtsMPcVx/F+ PK0x06AeV7lK5kCUl2nfMSo/mr/+auY4FjNIRCa8yRfQPWTsOCdVC3cg0fLoAe/Fv3L5Vg+RImnQ YbEw8V8C4mXdZGpMbDS96EKSshF8yfCtsnxpuNmDR10S0VtePcn0zDrmum7uQH6TN4e7ficj01wU 8jL/vhOsGloFgPeJ2T2beG/LK3fXd4XIHAX88udns2ReMK7JONlH/4qwXxl5FKrMwzQy3bLwGgq4 m2ZUcUClHuAuMBFzCa2PCNCohOzTomBJVd+uFTPzW4ibW8rK3EhVDAgBFw6sJLTCYSYHO86d83zj souvG7MPaMSsGShxZ5FyQXGBmVfPD2CqZALYHqNqZENf07cH5sfE4L8L4+7O6sUcrb+Npb0LsWkE aewWKCLi4QElc+zRvASHrXDYv2bvzMc8lOk9fnThaqdFxjTMTiVr8BugLRnBSECgWUIsGwdnKF5R ADrDY8/8FFuiFvsw4liqb6FQdHROoUfVX6gVQmJNANCZcGttmn61FtAiAHWT6smZeC0RepcxyubY RJzldA8EUPuHQweNwtPqEFCUbLTvZMzmSs+ToHvnOy7U99iJogm130ZiiGLzEgKKPeSruhv4xHVV pK9SoEaXneexYJPF/Dxr5QGXK51vpobQeN+aSTEs3aEmnZbAwMtNfTP6bbibpJA/ZtL81rJCv6da A7rQ+/OsOA0VMvGCc3gpDWJDfoEs6fhivba+/06Z8SCaQIXCdS0Q1RiVcHw+UA5aLwMCJ0yFNb84 prxwUw7Hx/3YTuO/rlVxEYjAuz8WSCLSndjntzgGDfu0FJDvl03VUlx05elYViplu0Dzx0wQ+ffT BKDasDJlMt3ap8NZ5dsHGwXAc6MUM8btAYaoCOssIo96rOawxBHVnr+rqcBC3GVnnYJaPQqcVvY5 hsagQGLmqUma8Z048eCjiCPKdVPPZon6SfgMTOapvXaVP5eFRaWok8YDZIeQCPcJ7vNX6ib5cRXA oueUZzdXkljsGnm9SjTKFjoJf935JUt9vBvdzpCjZeSdMkUfvpAtHAiovo0K3mKb3ouOV7xYcRzR gBrQEqrC5PZjKcT44mSG6oDZNABCJ0JbEgvXJV2d4SzdMOdCoKLV53TArZCM1mY1fm4UtE4glFLa jtau4K5M7dwFZMiR9aePZPUUcEcxcbQL8mAwNrI4qklp1utJUh5BMatlsPLWFoURCxMmMpe8spNZ xdCtMpFccKC0dTz0eawQZyLIbM9SYj+Y+dMXrNhYndaw8SFOgZedp/W1EiIxHfnFhNip06mSqx+l Or8npo/OuOPJnY23NCx42e0aSQy3JEET6QmwDKo2PF7CadsQ4oUd5BWCRG7CK7gMMskUHIiIPYnO rtws9MrlEHxdAas4XjbT1WMwxJemYUqcl2ZjyzBmrm5cDPyeCiFNHeSrzQRulRomXnYoUf3XfcIY zBrmmGowEKsmSkuAwLy6PVsZN68uYw7TUP9Zh8Zl6t8o17YDwBLjN8jJNNTcYGvaR58E05M7PJrK 9rXQJzJZYmdKTc7cxuhL8HF7wtxFkyYqPKwD90tGfD26CViakChuKY59zAUPciUW8j3EMXo4cMEi xHWFFgXrw7EgzwSE7pQLFyk1njycQ688CuARfqwMwbsS4HG3Me6sIRAtHjZ1PVhoNcP6LMWIrU6t GffBsYylgoPbTfe8O6tTYu6oTo7RvdiW0tViu1XkihwTKJjtCgHDeVSgeVdbNPUafJMXiDmKT5YC 4c+Ih7u18V6qBar3pRkseN+F6//AYskUxAeYpUuwh9ifxbXfk1Rs/vcte3mc6TX+9ZfD/hbZivwJ cgySx0mpnPLaEWkAjLwCW2mehGmOZVJxucW2pgg5nBojO+m2/+WAG++EQ26eoLuZLqEMsSoboe4e hyztGjnTu5vHVtOHT0YMFXx8lHrOz21k1kWG/sSlnju0eaKFKZjWPoELxhfi/dq00xdvdhuGR1jY uJ1P2Gh+CCgRXy044opH95iRsHfO+dIscQoQ/mCA7SczM5lAtfjuEeXXVSQ/XsgK1n9aeBtOHbso 99R2WajBIGUeMypniu3VKUOfQjuPCapEaksz6Fq9148tokw1YE+HHP9/mi+W+J33QNNol19fG0vQ Cq8G5oVVxfFqMozcuwvKLeLCTYrwptE+WBeZgoSY2pWLjLbw0EXyTXhm7TA70LXNo09EV41UpjNt Jts6yCKP3q9XgSeafukZYENWE4aP/35k0cP7ALY= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block TRcoZtqjn2mG6m34VrAup3Ue3mXUdsp9Svi1yOdUyuJ18aNmZzMqBL74/JYXAGMp7kyUseTthYI3 PrI0QWq4hg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block FPMMqj9RaKUiXlcYwEXFaXQj6iTZvDXB3ovRbqMXkBKErB6okVtT7N25cw0P4DrPAX3uTf1/DjZP g9FGVgqB8LxAQapqrXO27frLQX/jtpP5BRN/3UyLQQ5tmeo2wvGsRYc6Ptmw5XXPXjfubR1uMIvq n/KnJrhMohYd24Nm6S0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block hmQ19Z9b511LayHM++uE0XsD77aCTvi2D5+tVo/slhNcSgfFOCWou7QB72DRXWqLm1hI0yRUpD++ 6M4B9gDAGymLNt4kJfLjIH35OM6bL+USAdP5LzqI73Y5A9Ex2dA7XXtW38Kapk4g+yOtlcspGQ3v mipApCouubIDIKzAKfit6i+3D5zl06BKC5+/oMSR90fI/572drXx35dvozy88MbJh8nfL5OjT9y6 tufG7IpOsbuhtIaWR26UAUyCxZ5GOOwUvB2fS9q4Es/JzlrcdmqBkwl4ixHzLmdkNChDQXjCJVtg DP9+/cLV+QeiYTROca+/iv6JtjPVTSGXYAp7KA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KGFNy15frm7DKeh26HgilQgudk+s92inzv6E6/4SwA14yIblinRVK3XaIL/wyVEMSS/Nvx17YpaU YVWGfrmqIII72ql+J97vctL8UoKOHRk+u89CmFhhNIsJnQoGfxdh8DOXKgydwIo8DtyknF+rigwD Wrn0cHGnf+DzHJ1IlOw= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block IRcwaJ9nbddmu/9RW2bhH0oH/sFHVn1S2tsx6hwo1+XOm3bHWHP+ulk+4hbdqZE1Olkl9QC1qtoY ePy+TB2nSwbY99tK/zHUTTzEr9V7pe7cC+aCydi5fu9j5sMPnFmsQadzUgekG4OiSkic9/qlG8tY Nia8+0GODU2GsN9eE2823xR9kslK5c5LHAFyOnzohuZuaNQpgH9FgGbNWtWQ6Q+SNaCkDDwUMJRB XMWJMBZ7ADG8CfZuEbYaJpB3sP361wZWR2CVzTkDaWPuOvVZnunE0ob6QwvKmIm6q/myrsa7qCip ZmcNqxskerCWcqETss8HlKwYY/ryLcmRLUXsbQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15248) `protect data_block lo2tFyFjziJNXhyZZC97XYl3f0ZrW0Q7WwUD9LVmJ9QBi2joO2dZ8TfhlWwhm39tu85pBzGhL0bU lLGx5TJC7bSGiCErXI+tXOdZbJN7BwD743jxvfTNU2raF5ycnehTY1hGqwT/pWpIC2JtRTQTyzBp jg0TCqLY1rtHmFowyZv6918XEG724JEsdzGw6PjyfRjRLZtokRZ+0zbRXq68SjqEoVWFXEf047xz U1lXxDoOT917H2vpfPYaJlAmCz0h8k1/fCal34SYbx73cHMUWFnCTybEbJmesL5gfaookMOfBxRk sWQIao+sOuGvP38D26sAUf3oTnFHhf4FeA0y0GfIpGs4c9o0m1EYVlZJolMEBOS91rz0jpo2qyO4 FotW+gt3+tARFTW3lkQliIHC7eWV+CzKIs05UnbWOX2SkiuLdqLxOSfvNuWxAtliF1fFNjG0J4e2 FfC9OGxbUUJo1RrpiOuacWpSLpdl4+QKPVWCQuyMstdh6mUS1MWuoq6F8/mRGq7yZL2pdZIpB7m1 FqTQVbrAzKa9Cqe54k3eQnNS00lwUaAnIU+CzSg7CoiosWSIBg71HYudiGoiBoBnZLEqIkt2ib0G YZPWoBJ4XLzNcluQ1Ajkwv/Xv7R2wBRSej0W3uwSBWm6fUAXxP2We4RT2a/8nGQcnRSmWtH6tvn1 toUbZDD8+Ooeq6eb0K8NO/8rJFhNJV7JNyQXElREEK63JtrgaSZcKCtnBW+wsroNhNIOskBUnQYV 0CCOIW97dIQavxtVUm8QElbLu5USzKEeLvh9GD+tbqC72nrYJbHQnB1ohbEHiElv0JwdtOtSflWL pytwBnhoxQ5UT0UDv+wUPioK6HKBPFktp1w2/8kV+msFfnPCYTZvAF2GVF73mpjIWNSQk99VZ/qf 9K6lAwSib3XEYyTtUO7OnwZNIJUwEDWugnn96iYwnYYes9kgSrOfR2iKOJcSmX2D1CE53neDgkVH xkC47PePhGeYQ+9CruOehZDBHHKc/Fx8iiqW1oWzim0a0wA8NBVV2OqueD1dwZX1CZsTEAO+2Mcf rJFOE7NbOnbN0WJ1EJ5BRuVz2S/x94hwZ8o4JmDKl5Pxa37bk/BXyfiPL6ngdHZz+s8AcqBsyTxu 25sSBxZaeLoumhdgEd1YTf2MrAQZF1LOmD7ZmxpQXxUqzDi0fCC9JKUEAusjFvHSE1xwVYpyGp4u JNI5GpLffojoQV8tfutFGd5oTy2RMT9ZAP6bmqaKWsy+rlq4PgDvJmiJxYPF+FxmKJy4Se7UTCQY 2tGopjkFaSVlGV15HPI95mnUmA4BX23/QHo7TwIzY1um4MKqhwtkxITazjhYc0NiEbzJcop6bimU 5Hd7Ad7cMRDj1a3Xo1DKie1GROb0LBMAKcfeNv2zhs1tkeLMXkNcvX+W8v63l3HmlbO7RZi15Cm/ 2BWj9XfFFMG99MOAbLXeMsJqC+dpxdTsOguJfZxshnmn34b5AcWmmOZRX9sgP8wpUknH+6V6v0GM M8HKbo+sm2eHaAl1FWozeJJQUvPa6Wc4rq7pSjwdGk5FV+syvS5mCsU1fEEac9pxRE2PbEr3vB2V DRnHV0llczoF8jgqeLDTmKG4oyKDJBnssnwbQCarP764MWnhOLRtJkEoKwN9+btcZ1VdJ1avFa94 J6sQAvRmJuUd70Mnii74Zk/EZfliu4yf5b41Xkp0j+lywStXrsAZDldoSf+yNBaEMrVsL3IBAJyL BOT1Rd4YxlmaqzqmbsQ5YRX4Ub5NyDh3sZ03W2HdiS0oJRlV45N5cK1OCkUQAY5cfVuPBGvt5GRA MlBA6ms8n2mGPaNAr3e1b7yydC71SvA2ReRI5Pd03Vz2SAqGhP/59Ge75gqaOW/G2IZoUC11UCDU 31QBFFxVvxTiuKYudkKmOFxFBtVpOVX5BR7/lN+BDExAVuiwAlh0Hu5VDxIm48y/OH9B/R5LdcxH Ekw8rrHH7EGDSZ9Fe373bH13i6PTtHSKCiscmJeqMg+iRxzvY+BYYAtvQxMeaM65oZeHO1cwWQAx ALVsCF6TftT/Rc9MlqkzPpIV2mJ55DHMAQWKWb8QkBjdcs/AB7cnCVg07jbNLP4Jy5RTGGXHwFPi MZhK6ZPQH+3FRieYtmnhUP7xTYheG0c8xaBl2Q5rzribOMk8lVx5rTzHrNPvYdjp66A593lzLTyd mzIocbG/auEuspS1QZ37zHsdA6+QMZzeVdz9hwhwNioBFtgScmQzWrGhF8ppCfURQNObhR+UQBk4 Mkpe9DtCAaggrUW4TaZ2P9ZWxLVzR7jpjApAJsYlqdHXGRaWPT0f7AbJhvzAPz9go8J4/wPMJWBA P8u7WpWVrvnCuVV5PCjsTYZ5eaTAG4JT+q9Roq18Gl60ZmctUFnPlsN2t8Iw2nY2ru895Etg/5MR Q5ic1xjhIY/r4T6qcoJurG+efqeTYn3BsbJIg3gg7va8t1gOGGJ5bTW7FEeibIl0IQPwmhiZXcaG ll+Rcykz2XZzDFCJm1kn2DSeQzDqXz+eaB4O/AG0iC8SJofVp2apAQ29vRIxo+URABT1X7EAk2YP XBZBSV6sg48AbgQSNOXltxjle3f9zd4+0jzoex3KqFIi5B6Jhz3AIemALfWqZnvhUsy3ZD+O65+L z7iRBMVTD+Pzs/xo255Mwm9jeu/MYWRlZ68lFOi3zSBcsBItIlO/PPOAzyOyIWhU6OxP/SJDjuhF mE9ensZ7JNQAbDlglmjZ5EnmdEmyMjtRpUlTxLYNlwZYtyHFPLS1XmiE4UoTB36ClKq1wMYEsT46 j6OXa7Ae6Sz1zjvBXSolixvc4Q46i3M5pJxpTFpU/6tMz7IXkQGWUF6BRt9T27SEIResbJQgKlVX K5pPzrUYjfeh9dwsNU6un5VQLsQtkGbYUdCGgwrglawDVwvo+7GCXnSpxpjPUCGKCnT2WyzBmfOW Pi4Yih/HToHDNUkNypdJEZJ78w27VFhc6XgQl266RK3GoXcRm/4sxYpLwyPaWDBzuSb7qFS7Kfac d7s+Sqss1A2KS0zvlTMBW6j5yXVsQJl7Jbjc+1MNHWfsn0q9rxLoze2HT/OXytLWmfeOtJiPRp8J IPylF2iey2lTQ0Il2bLWnN/Twl7v8RsHM5XyIJlJaqJ5nhekSeOURwG5TsyiIfDcKuc/Gzpe9xgz 5t7aiOCvjTs9UUbNZSIgXj4tdBatEeuAht4UJpVXkWheAgt5qasssjYGpMdom+S+NWms1aa4c7cU rdrz5h2spaEGbgSz61nGMAfONrXan/iojpkD2AAiB/Gb5qug/KrwLDvp6HwKlPWXrBqwHAyhTPEh +dk1VMcvLdYrbwtUyZVi7JiQbap0gpDxQtw1Ce2MOTVUzcUMu5c+XRYSTaCnwMDZVr9vQIAFIKOE jgJSLbzPtsdcy8Bu1LS7pFjY1eKlqWq1LcfhJDCyblf6cEESmsGivg4uVmK6gp8PsPDNWvUy9zM+ q2us3j7GC/daeIegUa4TzRNbtGrBG3yf3zJLs583MMAGQBbczPg9dtSfI/AlQX+5alVGtbNoXrls ER7y8p+bbYSX0Rsw+ytWm/JkeKmiNuviV+SCxQVwdx2Q8CC1he63DAx0GuGOulCUdXuVidVG+GWu EGOqTIyMBG6qTzvG9T2dhRbujJLP+bWec1FYWqjz+YEStYcm80SqY5ilecjQdxJeE7b1PmYgDxTm /iqg8EJewLrF2IeYECtFqYPf0gFAMuWifV4XiS0Abc+f6+B3tCMDwC1yfUgcekyCRIe5P4A0Sql5 /3KWdaeh3eVrZmlsOZrgibyGtY2VofAGToxxZgCP3SvOncAv259/SlswvHOHEHw17krFaMaqwCXt KaZCUgELk4LMZwxd9nJc0AHVMT8TY52JyAm6C6MtRsL45cs8fPbzN29yicUJDgELyqd5OtLx6SnI vwdBT0Vxgws/He+tfW8WXytpb6TQ1weCZBOAaQtwNfhSJcV/CrQ0LMaDsjCORTqgPHtlhrDi6Whe s8BwlZfMZK7DjdE7BpbMDXkpW7xvwxjRxqgMdNmwg95N3EvPbmV+mYCluh6wuXgbJ5rxsKJUtKvW p5aJrbnhIiCATUNOVAABcb2v/V0ZDNPEnIDNkgN9lVy4qYdEIuL9/nuDeik9+0O20VXyd+R8dQN5 a4++rqVcbFmQQfjkfaXX+kiYIlQMhsmz1edAXnOT+UNQH0oqO6GtlTyMRPucmatg8js/JS6PVW4U R8Sy0xjX0CmVYvXlvVbfhR07kQjXfznA67gEZblgvpXTRoHX7Sr7DUNE7QXg1g4jtXgjBvVsO9lQ nQTrR8HadMCgElnYWB1MUrtROAGZoTnBxfHfUHgsSDhj9Feh9Idtwbv4JImkI6DiBrpiG0LQsYwp OsqCIY63+3K69v8JsJqbjGRU34iQm/j6nP0J3YsZ5iyWetQcQ2TqQPzClr10sj5B/QgVQTyy++Hw +s5CDh6ocLBpj1KbPY7um/k56sK0aOwlgg0wSqi35Av5YM7C1+wwS5nCmnNItHXe+WslwIVX83hL 6MEJPXqYQCfS9Rg+mVvASxz/v3FDbVwVKljjkFeJ7oxg+ho3TI9+lNBhY/B7rkDeIdIFgZIU2tkw UeGXme8J3NK/c4gOPpwyfBIWcKDThmGa0d4Se8XxxBtQQYCs7oXYBucxlKVkr3k290pU26hnkyau ULF2ny043WWmhqXJWDvG90oDuOI3KJftR54o9hysqhRD5maT+w04buQrPqf/xgr/vwEAM4VYTE6Z /Q68yFUrPHd1Q9zfVU8ItZu6kvc/iJDBGxiY689Lk9EKs5MdBis+rbZgKtnHgKQbkk6P8hvQ+Hz3 QrSvi6c1abPqfQTFzOl78QvOtpAxQXG42aYe1cumjaTO+YwHHL1/OcrmNug2WDB22+B5yYspHMMr pghggC5YE14ZK6SLRRyznvi6/0j6JhUfVvgPAp/DWQkh0XCEcgptvAjjhDXqI/DV5vcxdpZui3xq DgaHNZnLlN+AiSwhiUvdqdcAgAgbqWcppIqvXreYG/5DLtlu2KYqyFHwzd1jufRuB79FslLk+8kc pE2+4rpbb5I7+T2BfGWB49MciXCEEmlXlHRbI1aj8FMCawqNYI+SaTxAW2Lpb44opWQqc6rMs2MB RtxcdjCq6WcCe/a67b2uEW+Bn9IgNF9c5/Xd5KsX/yzm+GRQv4s5TRgvGOd1PmDS5CXpmgPbNMh1 7maofr4z/xm46/gy1FX+/cZzX4z8B4HWNSq8ao+MokF+twMaXFVVOoh19LMZeHpeAy+yaNOMUlB4 ZHByjXkYxiPQUoEEi8ZxUkWNQEXBxfS6JnfMTM6PitDDiUaH4v5mG+cgP/GyMwlwSbCVuYtd+ZLj Z1Vo8jk1TbUy4YwVZN6YZ7k8H5+bnhOdSlYm5VsvX4R0RPPfDElc+ULn1p8VVbAP22fDB7vjpg+r Fw+xC6TL7NY/It4Pt/lGmgYLhdOBItWGqWEw9w5BtgvKWICb7oKpkt0OYoL8RpgVrDKL4TZFPHEx TF+QEEAWi/qBHtpFefgmlcpp0cOMv/1SyDx/YosFuPM2nmj/S1kIQ0nIphjSxRlgDnTVx8V34pk8 BfzcQQWpAKoKcp1Sq3ls5m3tm309Er2uvSnwkiR3Py6zHkT3w0Hi9++VsmPe0btjY/REO7oyFVg6 R95dXw3Yho+iq+RM9mchg4BHOre9/KJbc65qPF47mKBnO+PvAmU+hl5lsEamo1BPencnba/P8o0z SbZN1wcIzlnbS1+XYPPlZO+lCOWnVCXwBiMxPiNzAUKHUY/ch6KpYGM4y8DzbzeWJKbQqJUx6bGw Htq8GEioSyFGOgSLfAgprrgSfvBbNnr3o+2XEN9i06V4HOGGP51M0BuhOZxsXM7LC17T2bno2lxx g3MNBexWh1Il+f7p32f0p4zchekCfXuxi9ewbdnsdhoTZWGMx1SR50pKRuetNKn4lG/wCYuBtMvh eN5mHMzz9sNs6mExAUsCDuuZTKFm5ozosPvCWIhsviNFQ4fJnmOAIQCyuybW9MU5ua9T08mNXEEJ 6lGpuV7d6XTL6AEyHe7ZfR+GlGyHtWFmnmuNh8HgVvtx++CDnqP1/WhsvQ8bDSZuW3NviXmCzWw4 Gt2pKlFzptQIC6Zfl3RnuK2c94Manvfx8P/8eYsrotrR06wP5TPCdnELK/6Umb/fbqzERjSedVtH C/XNkMeW/0AbeuNKu30powhGQj5XDKwjoJRQNXdKllJRgkWHMdkyLwAMMh5XSq75MVUJ1jGvRFpV kPtMik/7OSZ9aV9QgtERkL4tQVIKznYjD6cNl74hKrilOaPTxC3MnGUwgWgaMnkDyTGPbgI7IoQb SmbhzcikqOd6IUbBprZvw6ayE0OvckZjRoOfficSz7j67b0DUGKTTV1nbVEp4Ob/tBPY6NJsjJKb z4sTlAm4ozcDYfpnhcmgAHuXvHiFFBkMBNZ3rjYT2cEriQ9TFLF3mizXSvt6Y9lGNjnsELiSVkPZ RFto74jJku8Hss6xrKO49xXr32YVTl7TgSZBYBEReZSDER0F/9Smcx6PxcaJbEbHcoIgaCinTWDr xbClLt//kAW0biTwE+PgAgoIYlf7HXMO0iCrf0mD/NlAKxr1hLVveiz6c4/fddjlT+7789I5+4wX uP1L854G79hcQIDuJUlxMBN20YgfOFUJtzkDPbG4Y93b46Rzs6fZn3Zp53ui5gkJRnKQIx6wllzZ KGRD0se9BG6W4fHDS85OKRa84HvXcWNex6fUE86DO4fF3z/VLNoalpz8xfHzl/1BbFMTWoxvBuex Ewmn6Z7qXBrsz6rp605BFeNwjhcEl5rbKnvtx38car/MBj+kpci2RmvwtfYvrnFnmonQVEhlqqtb izVSQZTvDvDylxyI6KejyO+ad+O7KhFt1ObvtioLPhjtD8o4wAKHpqAR2Hu4XrAlkqR3GgQi33AY efXDINfwKWhvU4CTCyYdxJoAZuCZJp3VYpqygSeZPSM5WeY2E5wcbvPG7jTqIlnJ7NPBPkYnpns9 giuPumUmUOOcVFAh+1CMZW/i314PWY6dqh3jiFAUTMd2pAQlhzp0COASBkI8yHscCuL9e76LrNEl phK0zem4ZXVqvQfeVpDjlV1sqjkZH1bX/jm/plr8dpen5FxOm090bHN1BTwSx3G/mdGH75jaC27s ceIOGoUwoN/jYig7YwIJchD8FpwjGlocKJDBXKwQcEkAFDczNefFi4ziWDNI3YZTq5+thfPxOEFj TGGLOA97s/C58H/TQ02vedrKqR+cTEiVINTohDV+noR/pHiUWOgPDa/QVi9UZh1pv/uISiZ1dRQu Nq2qa1skuihcQK01oxJjvzePeXBQZ2qTzuUpfd5EN2ZyRny5dHBXJVMGeIYHDtTdh8pGBwDlAxYl 0G1e3k6mxqAjAIbYKg/fX/tnFMNY8haPyljcp4x2gBI4a0AZa6JtZpg9UfSlBe+Kl6KF9L3xTYMg ova0I+v2YhQPCmumDF1d+iDw3Fqkk8UoOkhh8DPP3LKU2pZJTLBSe2V02otyUo/C24nSt6n7MfV9 tTTVIzTvDeaMXwCb9GZxY/SeIJPOdaKmsmD1fMSCCsnr9aNmX0Y5pNUJDyTIuNBZAqVg1e4N4/bg wI/4dmn2Je6ixx8VUYRktKUsL6H5wc8cK16cWLMq7/XpfvPWADFWRlKdxzO4cRhSiYOka0YTRX7M d+cF5YXSMaXGd2imY96irnT526iu2uUVhoEnfCtxxvPuRf4jP6dwQ/W3Dwl5mjf6YgVw9LEvQdGD OtNhvBnzj9oO5OmZNsPpZlnZAu+wCFCaZnEsoT/8zttWrCWQYVLlmCMDGZqkIyYOmKZWq/gccVvR A5doD934rvPOkUR52VfkpIap29Zb34WqexqRn/0IC/DsFN7H73s2bLdm5k4vIdOSUJPrVoOMlunH fEgOAXDejR1OA0srkMW6DirEbc6T+3BH4lBAh1VqdqsQEAaOJZg2uHj7x06rVH+ZKKlimvQKRYKN vvaH3/maL+3obAIoMsvRXtzFP3BVjPVSDWlrQngRtmjDMASn4pDgQPic9xmdGeLucC8wW/D7bQqG 3vFNQaWdOwNAEAJg1Fxdrw4+FoSZ1+tJuaem1QXlLZp2MWnmc2naNfy0+frSvhWZLnd5HTZdmjZ8 jmmFY+wYNqnivDXnBgXQt+lTaZxmbiTsBDYd1LxnrPzBdWSLsYIHwSc4qknEunO5DFFeU7J/gRBD oLvMA11R0nbZW8FqjRQegzJTfXB3hCElqcU63wMkM3BDPrFqSn9jMY8AtqyTZmtrXoXB/JgzhAlu RWpCGYM/yQU+VaODjSS6ahedrwnZfEucVY3S9uIJOiCZKDxQP6gvtJwHr+r9mj8muQoOva/k7shP kDDFoYx7yIzd/PX18UAnuQw0swQiWnFq3Ysamrz3cEb3w7KCWCE0miZadUqagWh4Ui1EoA4BtTCm XH+ULndTI8KXBTQtdiSaIelm8c4+Hsg0C9LoAmezce4IxO4XYdeG5mTOuyhdvbaf5aZPhYiHfCiI 5byWtx4XeofT5LYNa+4oJv6J/fs5re14ShP++4ZKMOnGmUcB0xqymmMzKZeFzu5qZK9C+EJniLlZ 8X3ypMzEUK9VjeCEvjNhAi3kE6NAMjguWHtVAoxGk0FI/+e6I/x0exhvmD6+PsENXHhXNgiGv006 kLSDnkx+6CJgztcEI4r3sXw3dTeiaYYzJhTJUw/z+GZmodZpeCbVrsAMv6bW62Ock5wdtXqJagLV VSPRSxklebpditAz2peVOrKx6ekkD3hlFH10CWt7N0b6mlRFpGzRIbArJnIkhZImFhfLHYxrdG+u Q5QWVQ/qK1qjjWUkpMLZn8KZpRWY6Iv6/OD7Ms/rIAfGwrG0WQEh2CoA5kH+kVtf/KjD0kUznGzs uiq3DYtmVnkzXkjgSTWONZIQMe4uUy1cDbwde97AS+8lFfBBUOrzGikwN3CnatU4RSReVfMfsmj/ PiUvI+VVIfB7fLmIYirpkTyJlLbNqgCbxTC3/YUKvQeKsgdPYRZ1AQ+X2EECrxumRyYdjdzdM266 q/ngQdXkaptEq+pWick9hXGMZv4EXwb/JiIrIW7ZzIyeRw/iWU9yREE99wH8dhvG7F8ZuJYODoZq Z16s7UDgdwZUz1WAASUCVAfQ3Dz4Ys/qpMTTBwP5weg2M2dpSnI7P61q/kp34JaDu+mDwNRk0OwM S3MjEJmn7M9bosNMEbdM33rNvuBPGrGvt+N2snTNy1pQCQVZhjxY2RTzluBYwLnmqOulukiROf2T lArRBTBcutYaPwNKiLDgtbC263UZD7nXmBMnFbxEdHQ1ciWmpHo0nZ8vvOpG870/W9B0bIU00Zf/ mcQGtsdoYUq4AKCGeYuT86AIsnm9QubUYTdvBvU3355svrEH+FrAn85xkA6Qj+KEgjcTOsEO2c5v a8QvtrsHm7QlyZz4nmX0z+c2xrfYF4NYwB1W5swgvEVPbo4m3MZ2Px6uQ4tZ7Jr+wdowt/fLBqCX uejBBNkZayRvIeXXegOy82MWj9Sj5U8GmR2j4Ufp5Tz5cl09egSavAg314dcMTUbqJ6jko/G/s0z hal9n1np6/6hYCO88KZOCHYsK3yBMSXLeTryLK5iIwAmSKbm9hltXEyqJiU/Ykw2gjkbjNYFYZyK OHlDaFUUF8Dhk5sLXXK0BwJjB+7JpKt9g99BATyq2YOzoXh8tzq/r3PIhNKefbBMhJPdvtA7oWKl 9BfWupKNcvAuMYMENnX6MVjyiMEoFSq8Q2c0/0cv5SidXn6pvp27hiMYAviHq0/ii9bYOBmwWQID rFWstI+te9vAVdgtKckvIK+bTRd+gYyq9379EVHT83riumNh79bKQg0kgGASNv1Uw7qIDGI8AYe4 3Cr2lbdTaIBcgw2Tvs6tCkZTOj4tbt90jk+jhkBt/kfzyHkFq/hU1/tPwEg+ei1zO65wpOl2J/Hj zqdIelYk+Q2gMDD4UO7B4QJrq2maRaOh3NAPNsNttqNh9PtnRIZSIhmd5DeNgbe4Q8JUB1BBA/Db JsHJ28cwqoLKRQSTa9PtlDgLzK/NKIuy41SAJ1FSZmQK+bUhGdPEwKMPlvNOF86H3w3FB91qra5r t13g66yCkK2nICykaW0+ctvVWO3DnQt5dQNlWp3TtwC+UU5R3WJ4y/KFK7Tc+hyB5J1440FQbJoA mpuZepfQ443UsJjyxTanoZhHKOD7Yvpu9CUn6Zp2ktivQoqNB5T+rqM1EgThdTTt98MM8DcwEg1L cszhN8IqINLpY4sFYtBhA2qTuoeWkr5RoLqT1hNi7H2xnoLA/L0wQHLjIKKqmRGyBX70bMIj9bsY ch3AzRyhbdYrUqvruR4h/V1egVCDHLMUhpxyGacBypyCswL6q5ji2LFtQ7nVCqHSOqJc5Npym9fM /UrTlm/16RpH/DuxDBck+pbAmHknMlME1lvMkvsxo8vMkwGvPuIKZr7n+S8Om+Vv9ne6FuIdbzgk iY/KzqzQBx92OXH0B5uSdtUeXsIalMo9BN3mNG9UXV5y5BJ3MOvtnBPeTkI/N08QG6YKJzUS/iWl 4W/9JSe6d9oYzuciEUrxzlxX3HUS160cyAQ+ODwTRnDtLi1U4hRgGFgIOg8BwEs2ilLtuXDxORKl bDSwNX4I/PW/qhR06nNwbRjyVfIi4VEn0ULSFm8XIPzEJ/t+xQsSK8cRx3XShqsDrberE4kcF6tg TsuJ8lO5r8rDwKCZOzPkOktohxlDzfICQphnJ5xRK6sehksPxetSeYsrGBplI0VPdhJLFAsnUFJd Ev6OqHdkRzMJ8+CdkuLN/snC4oRaUvANsK0doQmZ9+c2NoNuhNcVod8kKpw/3twWUJdfa0QIGJyX qzI+dQhuU3lWQBhEcJhG2DzZaUbDxrbX3YCGd+k1wavEf7VqLSwaTmmEwdZ7jtRmuK6HJ0rRISjP f4bD6ffOZjQ6jYL8ORBWeiI18SoNK6YO5RYGBfBdFqyxzJNmYSlofk85khFYSEtHVqecaPnuaHdV A6gZQC8sgAX1dfe/II0uTSstSA85bk+rpeDP4VHMB0X1lMFwrpVV9b7Y1Di/T0f7rQn2P/PPC8vQ 4JLGXzybsadQGJ3W0zxfq6PJLdRyCfJyHIttZEiARP7nqBDcTIyFCg+PvJcQZ768hNO8jAeI5jbd msSsFZC4D3N1YQDVZwj/7vmIilJ+i9qJnvUTwUBySXbq4FY1JyZSGjV2GWZ29ruIU3MwbAdW8m1S 8XTvHsbcxiaPOc/0ek7gt+0+b74qNTeX6VWf7fYDz0SZaKntTeuiDevjmzuF77fbaITL/5ISEq+I BtyvYS29P3b9B8LA9WC1N7tSTt6E0OIJxmwZlujkOJES9mM6Z+91WHY59qFKpa2siTL4jl/unDC3 uOuUsFOdpOp6OgWVfA4U88/JJrs3XraZDrp7DLnvDxEiss4+J8j9p0bw9hfz/ZPt9o/6Uv8h+z0P 0FRGjl6c7lSreB79+W0JPk5s5gfUN6tTwD98zYuEjyv0TIOWxsgQQOUE3DPnCEkTyCCwTqLktu3p ZbAGkWSivgpDi8580gURDEmQKDXhnks2yBDsXxiZx+N+UqfI8u1RYwL7sKZVDsjL+5mS9igixKJu mi6g1L08K6EDnZY73csqvUrwEVmlRdOTzVloSY+YdTJFeGdmKYyB1As6DDkFKmSB+eztHKVE6V7J bnAUyg8DRbGxU4KXgrC4UiJRgUaSYSVe8KHSshXafQ7DPFMKCB/GechX2JL7p8dmDbJWRYbq3c3D VMhRwP3vts5oXVTfCoNn4Ep3xMja6QsusMNZi1papKFd3yVv1l4skzpTWAg6o9EWYEnqzjznoUT1 HrfRKo7S2KqkgK1g14Ipvf5gs4HrxpzJEgZuUK8pGZH8jbP71j6nuOlCB0Hpr3ERm4DrKn3/DIFV mT8lJzUbiW+KEHjV0PjT9SLWH25lIbLWQIRxB9dSjAmOM9k0j1SHqlfPU5PX9UQi41XcoqWF1/bf HnAiHpCNxFAyWodIw9PzqVGZ03ei4Us0GAC4j0PZBcaZ0jZTD4SYgR1WAaom04ad5An2SupDMqD6 i/zj1uMkN1ftCXWyyAYzEknvYDhlGSGqD+pgEx8jyNJwbLN6dijDF8o4EwiSgu4rs3zkTetGVXbL ZZiW6gvzetc8r8CVSkDS990IslEBE7FEog6tPOs9nAysN4zANCHAB/syxXsIqyaqDLxj08oCHAN9 Ea0E1TcxVd4p5aMrsZtaPXUny0WsQcZmrVua+pUORYcdpMtEpDhvNun7+d7Yexd7yMiL1GUXbGBn 55J7dkquCalG/Xmy9e4QOaxqOqW+fLjL9VWuDLKU9I4iXyc7CFC1H+GtUT/gMBymfmMxz/Q98/Yn inr8+5CbwWjD7si0setE2IM+NeUnQa/gtS4vfFkIdPi00vXllAM6pSC6/0QeBaWa3+r1czPVFObj PWH7rYqR1ooR25vC9ZbZT403w7uhulpM0H08ajEmWIAkOGsH5pQS088ug2MLhd/hO26L4IydGeo6 3NJdiNd2TsdbmuJoUSGGh8mJf7yFL20HUgmUQDeoEGFqgtWO9hcieiUbBjhXP6almms3b+QF7EB+ V36WocNhOtAOiQMUjP7amBx6BWL80y7ZG0C5mf8ceE1zlOP6JSqIKZ2W2ctmKMKCzQDQGvCAR697 3oxFl7KClk72SSKOq15uzytrapXDRz5aKpyyrxpphsZ65VzcLdqV6Dojj5fnaE4u7A9xRt46mmNI R3KCXahZ0diUKnV5O3bZX7GFF5iaaJHwiBCwxadX6E52fTHqJ9yr291p4tG0pUlhCni+Y4O37EEq fwWvrSrkv3NqI+z2V3Ifl7Zh1oY3E5v+/mO05jsJmthiTfptmfo4jfUKFl5vHlQUIKwDvAGQUvAg syriuscwJEXegC6+8l5wdH8flHjlXHsQa8+uBEqX7KqZ9C6wQSIvc4OmKI7Vz6KBtqEuFqTb5dHq /as5/RH/jGlNFwZjxlQZuD71nrhq4+Oz/jZbm1LpWZ5NXkc1Om9bx18JGA+1sYR1xe5R1zs/eay9 yQETW4yLT5sKie3PwxLcmjPq5ttZ540kwE4y/K8ZEX0dCsJvwBDTPvftVJVws32pLrhd6lavVuIV c5F/9O9wt3B4X1NWTlchrQwc9yKzvp5L5o1kr6Lg5IQe1eBkFQZX66eSgK5cWPkdqyq4yMniZEZ8 oYrcPivSsc4lOI7GEYsE8wLnE9clMOPlm9nriJxTDZ2i7/HmnL1Q0IiPMmg9kdgtz3VlAuMQN9RN R1iS9ykHnegJPyKBWmIO/K/BrHJen7afnI62YQbUp0Fr6IcNROoqq0bsYmSBruT3W75JIG0Cc174 /PyIiLpmjWhJ7sl+686Ml3/vhYFFD5jlDOQ8DLKpSmaMscH50ZsQihpoKJhP1JNtd9JrOd4SdQ+I px6bNnblous1n5h522nqwM6XosLtL/G87CJ/bOSeIdbixbyZHxJXOIxNuLdRQPb4QrqiDHXMQeah eWPEMuQpf6dnYjM1KnkKjxh/CxJtCRmkUjJe8WqDLzpdI6l/+L0JhoDyQuH/9S+V3bgmBC1C/tRk n6xVuQr19CtS+Xg8oQP9zBFToFMk0fN88FqXnqAkJ8BOu18iSPMpTTNWAs6kNUw84Po/gZ+fcy4X wB8bdIiQEAAztvib1K/zwMw+cMVzX195FEMZAJ617/s7L5wRqluMeECknM0HC9AsZb08tQ7q0FBH vl61Hyap/2Vjte/O/g8RlkXO6FICuys6T+qFHYHwrNzhUtaMXqkdGddnHVh/E343B0WBE9GXpeR7 lGji7OfIToIlLxunpXzjw57MBUgjLBCzZPsPSJSa4io30B0kMP+PCx+qFp//LncbGBwtgPWkAgHL IsQhLL/xfkZh/36LEGgpPNlnS4ETUoifcxEVusUOVrwv3/tleOCN1JMljt99t2sXt4GRoGCvQZaO NrVh3sd2KrXhII0gfcLdpbryzJwaZ80HMG8KCqLC3Ga0yT/FPdDa/eOJJ8KL7fQtaDwXSCL9cOhM Pe7qiIINL27Mim7MzaFHp5qUtpYlVv/Ex8bJ9zNFYLn0uO7H2Sn5JOuwuqmGkR2SNCz6Fupox8/z D8LVeAe26qFrZOsLD59zLdgbLl3asB1h8osvKcLkvCQCSXQjhQntaj3PjjbVBNWrOLztNATp3Env v0FW90WhtZiU9R0xHi1sqsHDYZ35slEh9gKRRyw9tKM9OLvY0Wg4XNA+mhDsls1SiQbQOqC9i+3X IxgawQKwDnEkrbn+DXTaV2CTV8ak6V9WIDsfw8rqGcrGaII+sQhmbbfZAvM1+uWubre3kQlezwuK PoVfogigSpV0tNW6S2/LnMr7OOLeHvpFV2ikQWTbx9oirYNSEPJbWoomWNdL8HgkwDoHyknAsPxN j+YV8KYlzrLNeOQqfh/dZ1RhZbz0DJMx6mPpZSv3wxe/cnCuLOq/t625aVMNRyuqV4nkGpV3bEKb Sq5w/UAdn289Ylqbk9amvEHPGi3JViwXmlml23kzleLaClulOSgtec660aGPQ+NkmvpfRKoQfS/Z jVqqGAIy+pKJbg1ijmXawOzL2MWbm9g1Cc0wUsDxw1SYbxQ8ZR7HaqEyPcCy+fJi512Ts0OLt5qe hnkaR6rzQ610uluGwmmaqnNe/JpmSETIqGhAZYlkGJgYqLau80r9i3vhe8k0QMKSaOnaLsiieYHs bR1H0Go+tU/Um5zKqEtjIUYxEFeFmLiPdU6qFVy1VqDviqJnMgToA/u4jaqI4/WkPz7i5Jwg5/M4 x8MIXD+CMxg4sM/KbEfro9Xcc9ysF5OStAOT3zn3Gs7dZkLSuboaLGS+QWJrsVH7jmxlxyQddLE1 ZuFeh6ItwlGKXuitv5MkMxWnZEOLwNPIHF9CfqES3PX8Mu4nHsdRb+xeNrbTC9mYEMvxQgMLtR8D UjQlZm9qIBKCdU1Qx+ssRmtB7hB6HpTDFkCXj7fw5EhPX/TWHxqRYe6TMnj2HlBZVK2FNWIwmoD1 z2kUSyWa2h/aKvRs9G+nWyPmT0j3dRuZqMkZBAsJuJp0iGYVKPICWos7uo4TYNqm0rrcN3UAhljZ WGlcu1o5LpU/rnRV0wzS2X+YMTxz0Giaz9gpJ/sqOdgBiuFYXJDckfQnKeOdLesW5Hhil6CCc1Uh PZ+acLCcStjGwBl9sxyAdpiJZGhoSZ0LyUTT+x2sWKi14HJ8c0pIAMvwq60AEthGSTnAXDu8y2+t 7WyNiUepk3gURbhqidaE/Pu3frJMq5BwZaFbR70Mj20NE7pA5Sg+BxQsaysUV/Grmfc6iap/u07k hQ0d58AwvkMOCUCRuVpGUzfEY7jAUB8logHqIYRt/Gg3y0TCL2GKpRYcBw/cXruXF4PsqphMbz9S EetAjixDXFHFuIwiRAeTjSQu70P6HOMpsfpe08dQVthvCCy+PudKH59SdelBTsNBPVcmyIumGsLb p3Tr6N9UjYyY90j4y+cAMp+4RmTgEegTSMeUbpbVeNYUI7Wu0H7RcjrVDrWSxtY6UPQ/Dx1hn8qj 5fAdd5SBIUcGlrHxWNN9a32r3ZZZEOsNVfCCYmVv+iAMDe0oNAodyu7w/q/qcwppLWxXUAMEhqSv vt75VzFD6UTBN6Gpl0xlB6ofPSHMtOTyMry+w3kvzLxLczALwH5vuuQScuo7eMKgVJ97jh/NbD5r 5mWWFGiiYGToHBdP0Yp76oOepOPjDn97NxkHvVoXYZY09wHSD67M7DoZ6mFay9tgR1MjVJ/07MrJ Gqfz5hsG/96fNz6NVX1sGtS4n/YCo+e5vOdb2lL9yfknjD5VeFRXw74rt2rZRVT4OGEKPY+z//f5 MErU7acWK7pqGvN10o4KvM2y7GPDIOdszj3V+5zGxaRsbenLDNz/YtPWlkVihCzomhhBXLtGRH5Z JIHrEch2Qq+V+cI65CSviLaYXN7wqiicv7a5JPIQbol/4EPgN4OFCYQx7GwDmjp8rX8jBjtws6fe y12wpztmaykpcO2/b5mJ+bm9tNHw+Z/vekRgHoQEBAAIaCdQWjCjxstRIm4LHDbTKa3gsUGCoSg2 Tbw/UUgoj+fFcKvzt4bjxU+RWbQ+f78UGB7OUEDSVYLkqHAfolUvw5rpm6Bw8FF2HsrtR378Iv0h J2pm/4MwDHnAxQVkpg/MDCQI5JVCaO8px+xlGOMtGC7/BMrIxTjYRqo9LpFGIlOwScNgfpBrvjAF 3yqFFXduKrWYOOTsTHz7o8jBXyo5MP9YEw0IiUsmX0Ykj+sSswtoOk3arr11bzp/SNylQ75n2S+t mSAvjUlBJW7JuAwA218g14d1KrExYh1l9OEOgcmp95E2XKHXZhmRgr+2+EYAvsMiLWwm8kIl41lt CGDTL5/3CqDKnHHzc9p858NOue+6MTuwSopBPSkq9Ita1y9kgJxrnJgafEl9BX3l4sBZFafEBDWh epXRZ0iTEE8b4dzZ2WnR+yF7sV56SvH/HVsJxHUGj+zvukJmGva8H5aEy8l4jveswxKcSi43vpPl rwLz6soAsP3MixinEYYI8v1A8JGWpttM+VzOMr+zkvLlCyk40XcWFzFjoKrW2dUgB0CaP+aq43jS yWTW75ZxP50PQBEVXeHGy78vMDCIZLPimV143fxuqyrO5X8utlxdTB8FDRds6fGAyxDcMyheh1tN jbaF6wMhWnEYH2zSkI3bG6VsUgLxEb8Vs4jXmF4C+cuuflN7r//s+jYo06cDgpOgqM53SmH9MIlw AYOYD3WJ13Nwr5+6Hb/ZyRksdUe9B1A6Aru73cRGAS0GDocaLdJVVtnqpqoq9jPi2ZzvlUDVJL2s BPS9o7k+dVVldul/SsgANNDzUm0Y8A/EuepyJEYnPZskvkY2kabzB0PR4OGwgpnmAkeXMX+YWAzj lJqDmsv2U5SyB8lx6NOOUKLTUiF0lgGRK7mg4YATGiLsCGuxeomuFVjC3oZzPFpx2ZTKeVNMyE/J VsfU4zQPsCpOYUrbxffaRilHAB6mm9kBpplbasLi68vkkXj+U7cyx2GRBT78H1iH5erJ4L6Io6sV FdjdPw9oOsGREAwYnhl49HB+rAKU3Ja0rLFRz0b+TiF6JjVQHosDcAIJ0BInTbxunV5DazDH+J9P QzmyGbzIyqpd0SFjlJzlvQ26OO1NW+W5q1yWN1bgXOivwqYXWGdLRqrze3QyjcT593wqN/Lf5FoU nS1xpsXAzeKlwCW5Tc38ArA7SsYn3BTRFc8Oyb/Wzm9tLCo/wJHDyn9DMTf/kn3TxBfQ7BSDfqmM Jg8x8ZVbJ8gTC6Wy7oabBzL34r2tznrdsgm4PNgTlJEajPkkdhzhecxD4aGpRo0qRQRrfTud7Mze V49P8U9kC8zzF3mSFQEN45MghlyzJS/w6oMZhzdtvH0MMkLmm6J55jQrjD/MmOpoMG6m6o9S7bgZ zLGok/elhTN0YwpezWoJ8s4XKgvpp9z5s5CH1AH+4M/La2tWKpGjn+6fgaIqQfVLqSetEMayZL5W g4x8+tLc/wKBoX2LVdScspDi89PBIxPHEj8XVVjnpwFQ2ORwc54wYlRYvMlhnNfMk6QmKZyDsb04 cLNCOgE8cCEU/NXXrmFoCj5BV59wYehYjW5rJb7dY6cNdG27z7m/gsKakAy+MsZkBcxY20ta8ujf 5PoJG6Ih28Zezexk4VfWoybDX6/Hi8k9kUVOHNFNhoqsHvv5kna0B70fctkMW/PEGsemkKX7VlQu ZP9243QAJSAesf1tiZIqUpwx3627F+HhAPGipKuBelFtdRXNcESyUBoZrPuF9C4QLjmUOise0g8k QLSwOKKDl+3LuhacLJUhLjLZhcm0WSe9BFx8iM0WxsRxEo39N/BAtAvdYt208h3w8AerunI+sCR1 ByJ+GV+eG3UCZjgcR+9/VozqwcBCZG72hPRCrf7pQxVwpqrTtHc36XVh4/xmtcceVhtsMPcVx/F+ PK0x06AeV7lK5kCUl2nfMSo/mr/+auY4FjNIRCa8yRfQPWTsOCdVC3cg0fLoAe/Fv3L5Vg+RImnQ YbEw8V8C4mXdZGpMbDS96EKSshF8yfCtsnxpuNmDR10S0VtePcn0zDrmum7uQH6TN4e7ficj01wU 8jL/vhOsGloFgPeJ2T2beG/LK3fXd4XIHAX88udns2ReMK7JONlH/4qwXxl5FKrMwzQy3bLwGgq4 m2ZUcUClHuAuMBFzCa2PCNCohOzTomBJVd+uFTPzW4ibW8rK3EhVDAgBFw6sJLTCYSYHO86d83zj souvG7MPaMSsGShxZ5FyQXGBmVfPD2CqZALYHqNqZENf07cH5sfE4L8L4+7O6sUcrb+Npb0LsWkE aewWKCLi4QElc+zRvASHrXDYv2bvzMc8lOk9fnThaqdFxjTMTiVr8BugLRnBSECgWUIsGwdnKF5R ADrDY8/8FFuiFvsw4liqb6FQdHROoUfVX6gVQmJNANCZcGttmn61FtAiAHWT6smZeC0RepcxyubY RJzldA8EUPuHQweNwtPqEFCUbLTvZMzmSs+ToHvnOy7U99iJogm130ZiiGLzEgKKPeSruhv4xHVV pK9SoEaXneexYJPF/Dxr5QGXK51vpobQeN+aSTEs3aEmnZbAwMtNfTP6bbibpJA/ZtL81rJCv6da A7rQ+/OsOA0VMvGCc3gpDWJDfoEs6fhivba+/06Z8SCaQIXCdS0Q1RiVcHw+UA5aLwMCJ0yFNb84 prxwUw7Hx/3YTuO/rlVxEYjAuz8WSCLSndjntzgGDfu0FJDvl03VUlx05elYViplu0Dzx0wQ+ffT BKDasDJlMt3ap8NZ5dsHGwXAc6MUM8btAYaoCOssIo96rOawxBHVnr+rqcBC3GVnnYJaPQqcVvY5 hsagQGLmqUma8Z048eCjiCPKdVPPZon6SfgMTOapvXaVP5eFRaWok8YDZIeQCPcJ7vNX6ib5cRXA oueUZzdXkljsGnm9SjTKFjoJf935JUt9vBvdzpCjZeSdMkUfvpAtHAiovo0K3mKb3ouOV7xYcRzR gBrQEqrC5PZjKcT44mSG6oDZNABCJ0JbEgvXJV2d4SzdMOdCoKLV53TArZCM1mY1fm4UtE4glFLa jtau4K5M7dwFZMiR9aePZPUUcEcxcbQL8mAwNrI4qklp1utJUh5BMatlsPLWFoURCxMmMpe8spNZ xdCtMpFccKC0dTz0eawQZyLIbM9SYj+Y+dMXrNhYndaw8SFOgZedp/W1EiIxHfnFhNip06mSqx+l Or8npo/OuOPJnY23NCx42e0aSQy3JEET6QmwDKo2PF7CadsQ4oUd5BWCRG7CK7gMMskUHIiIPYnO rtws9MrlEHxdAas4XjbT1WMwxJemYUqcl2ZjyzBmrm5cDPyeCiFNHeSrzQRulRomXnYoUf3XfcIY zBrmmGowEKsmSkuAwLy6PVsZN68uYw7TUP9Zh8Zl6t8o17YDwBLjN8jJNNTcYGvaR58E05M7PJrK 9rXQJzJZYmdKTc7cxuhL8HF7wtxFkyYqPKwD90tGfD26CViakChuKY59zAUPciUW8j3EMXo4cMEi xHWFFgXrw7EgzwSE7pQLFyk1njycQ688CuARfqwMwbsS4HG3Me6sIRAtHjZ1PVhoNcP6LMWIrU6t GffBsYylgoPbTfe8O6tTYu6oTo7RvdiW0tViu1XkihwTKJjtCgHDeVSgeVdbNPUafJMXiDmKT5YC 4c+Ih7u18V6qBar3pRkseN+F6//AYskUxAeYpUuwh9ifxbXfk1Rs/vcte3mc6TX+9ZfD/hbZivwJ cgySx0mpnPLaEWkAjLwCW2mehGmOZVJxucW2pgg5nBojO+m2/+WAG++EQ26eoLuZLqEMsSoboe4e hyztGjnTu5vHVtOHT0YMFXx8lHrOz21k1kWG/sSlnju0eaKFKZjWPoELxhfi/dq00xdvdhuGR1jY uJ1P2Gh+CCgRXy044opH95iRsHfO+dIscQoQ/mCA7SczM5lAtfjuEeXXVSQ/XsgK1n9aeBtOHbso 99R2WajBIGUeMypniu3VKUOfQjuPCapEaksz6Fq9148tokw1YE+HHP9/mi+W+J33QNNol19fG0vQ Cq8G5oVVxfFqMozcuwvKLeLCTYrwptE+WBeZgoSY2pWLjLbw0EXyTXhm7TA70LXNo09EV41UpjNt Jts6yCKP3q9XgSeafukZYENWE4aP/35k0cP7ALY= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block TRcoZtqjn2mG6m34VrAup3Ue3mXUdsp9Svi1yOdUyuJ18aNmZzMqBL74/JYXAGMp7kyUseTthYI3 PrI0QWq4hg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block FPMMqj9RaKUiXlcYwEXFaXQj6iTZvDXB3ovRbqMXkBKErB6okVtT7N25cw0P4DrPAX3uTf1/DjZP g9FGVgqB8LxAQapqrXO27frLQX/jtpP5BRN/3UyLQQ5tmeo2wvGsRYc6Ptmw5XXPXjfubR1uMIvq n/KnJrhMohYd24Nm6S0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block hmQ19Z9b511LayHM++uE0XsD77aCTvi2D5+tVo/slhNcSgfFOCWou7QB72DRXWqLm1hI0yRUpD++ 6M4B9gDAGymLNt4kJfLjIH35OM6bL+USAdP5LzqI73Y5A9Ex2dA7XXtW38Kapk4g+yOtlcspGQ3v mipApCouubIDIKzAKfit6i+3D5zl06BKC5+/oMSR90fI/572drXx35dvozy88MbJh8nfL5OjT9y6 tufG7IpOsbuhtIaWR26UAUyCxZ5GOOwUvB2fS9q4Es/JzlrcdmqBkwl4ixHzLmdkNChDQXjCJVtg DP9+/cLV+QeiYTROca+/iv6JtjPVTSGXYAp7KA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KGFNy15frm7DKeh26HgilQgudk+s92inzv6E6/4SwA14yIblinRVK3XaIL/wyVEMSS/Nvx17YpaU YVWGfrmqIII72ql+J97vctL8UoKOHRk+u89CmFhhNIsJnQoGfxdh8DOXKgydwIo8DtyknF+rigwD Wrn0cHGnf+DzHJ1IlOw= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block IRcwaJ9nbddmu/9RW2bhH0oH/sFHVn1S2tsx6hwo1+XOm3bHWHP+ulk+4hbdqZE1Olkl9QC1qtoY ePy+TB2nSwbY99tK/zHUTTzEr9V7pe7cC+aCydi5fu9j5sMPnFmsQadzUgekG4OiSkic9/qlG8tY Nia8+0GODU2GsN9eE2823xR9kslK5c5LHAFyOnzohuZuaNQpgH9FgGbNWtWQ6Q+SNaCkDDwUMJRB XMWJMBZ7ADG8CfZuEbYaJpB3sP361wZWR2CVzTkDaWPuOvVZnunE0ob6QwvKmIm6q/myrsa7qCip ZmcNqxskerCWcqETss8HlKwYY/ryLcmRLUXsbQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15248) `protect data_block lo2tFyFjziJNXhyZZC97XYl3f0ZrW0Q7WwUD9LVmJ9QBi2joO2dZ8TfhlWwhm39tu85pBzGhL0bU lLGx5TJC7bSGiCErXI+tXOdZbJN7BwD743jxvfTNU2raF5ycnehTY1hGqwT/pWpIC2JtRTQTyzBp jg0TCqLY1rtHmFowyZv6918XEG724JEsdzGw6PjyfRjRLZtokRZ+0zbRXq68SjqEoVWFXEf047xz U1lXxDoOT917H2vpfPYaJlAmCz0h8k1/fCal34SYbx73cHMUWFnCTybEbJmesL5gfaookMOfBxRk sWQIao+sOuGvP38D26sAUf3oTnFHhf4FeA0y0GfIpGs4c9o0m1EYVlZJolMEBOS91rz0jpo2qyO4 FotW+gt3+tARFTW3lkQliIHC7eWV+CzKIs05UnbWOX2SkiuLdqLxOSfvNuWxAtliF1fFNjG0J4e2 FfC9OGxbUUJo1RrpiOuacWpSLpdl4+QKPVWCQuyMstdh6mUS1MWuoq6F8/mRGq7yZL2pdZIpB7m1 FqTQVbrAzKa9Cqe54k3eQnNS00lwUaAnIU+CzSg7CoiosWSIBg71HYudiGoiBoBnZLEqIkt2ib0G YZPWoBJ4XLzNcluQ1Ajkwv/Xv7R2wBRSej0W3uwSBWm6fUAXxP2We4RT2a/8nGQcnRSmWtH6tvn1 toUbZDD8+Ooeq6eb0K8NO/8rJFhNJV7JNyQXElREEK63JtrgaSZcKCtnBW+wsroNhNIOskBUnQYV 0CCOIW97dIQavxtVUm8QElbLu5USzKEeLvh9GD+tbqC72nrYJbHQnB1ohbEHiElv0JwdtOtSflWL pytwBnhoxQ5UT0UDv+wUPioK6HKBPFktp1w2/8kV+msFfnPCYTZvAF2GVF73mpjIWNSQk99VZ/qf 9K6lAwSib3XEYyTtUO7OnwZNIJUwEDWugnn96iYwnYYes9kgSrOfR2iKOJcSmX2D1CE53neDgkVH xkC47PePhGeYQ+9CruOehZDBHHKc/Fx8iiqW1oWzim0a0wA8NBVV2OqueD1dwZX1CZsTEAO+2Mcf rJFOE7NbOnbN0WJ1EJ5BRuVz2S/x94hwZ8o4JmDKl5Pxa37bk/BXyfiPL6ngdHZz+s8AcqBsyTxu 25sSBxZaeLoumhdgEd1YTf2MrAQZF1LOmD7ZmxpQXxUqzDi0fCC9JKUEAusjFvHSE1xwVYpyGp4u JNI5GpLffojoQV8tfutFGd5oTy2RMT9ZAP6bmqaKWsy+rlq4PgDvJmiJxYPF+FxmKJy4Se7UTCQY 2tGopjkFaSVlGV15HPI95mnUmA4BX23/QHo7TwIzY1um4MKqhwtkxITazjhYc0NiEbzJcop6bimU 5Hd7Ad7cMRDj1a3Xo1DKie1GROb0LBMAKcfeNv2zhs1tkeLMXkNcvX+W8v63l3HmlbO7RZi15Cm/ 2BWj9XfFFMG99MOAbLXeMsJqC+dpxdTsOguJfZxshnmn34b5AcWmmOZRX9sgP8wpUknH+6V6v0GM M8HKbo+sm2eHaAl1FWozeJJQUvPa6Wc4rq7pSjwdGk5FV+syvS5mCsU1fEEac9pxRE2PbEr3vB2V DRnHV0llczoF8jgqeLDTmKG4oyKDJBnssnwbQCarP764MWnhOLRtJkEoKwN9+btcZ1VdJ1avFa94 J6sQAvRmJuUd70Mnii74Zk/EZfliu4yf5b41Xkp0j+lywStXrsAZDldoSf+yNBaEMrVsL3IBAJyL BOT1Rd4YxlmaqzqmbsQ5YRX4Ub5NyDh3sZ03W2HdiS0oJRlV45N5cK1OCkUQAY5cfVuPBGvt5GRA MlBA6ms8n2mGPaNAr3e1b7yydC71SvA2ReRI5Pd03Vz2SAqGhP/59Ge75gqaOW/G2IZoUC11UCDU 31QBFFxVvxTiuKYudkKmOFxFBtVpOVX5BR7/lN+BDExAVuiwAlh0Hu5VDxIm48y/OH9B/R5LdcxH Ekw8rrHH7EGDSZ9Fe373bH13i6PTtHSKCiscmJeqMg+iRxzvY+BYYAtvQxMeaM65oZeHO1cwWQAx ALVsCF6TftT/Rc9MlqkzPpIV2mJ55DHMAQWKWb8QkBjdcs/AB7cnCVg07jbNLP4Jy5RTGGXHwFPi MZhK6ZPQH+3FRieYtmnhUP7xTYheG0c8xaBl2Q5rzribOMk8lVx5rTzHrNPvYdjp66A593lzLTyd mzIocbG/auEuspS1QZ37zHsdA6+QMZzeVdz9hwhwNioBFtgScmQzWrGhF8ppCfURQNObhR+UQBk4 Mkpe9DtCAaggrUW4TaZ2P9ZWxLVzR7jpjApAJsYlqdHXGRaWPT0f7AbJhvzAPz9go8J4/wPMJWBA P8u7WpWVrvnCuVV5PCjsTYZ5eaTAG4JT+q9Roq18Gl60ZmctUFnPlsN2t8Iw2nY2ru895Etg/5MR Q5ic1xjhIY/r4T6qcoJurG+efqeTYn3BsbJIg3gg7va8t1gOGGJ5bTW7FEeibIl0IQPwmhiZXcaG ll+Rcykz2XZzDFCJm1kn2DSeQzDqXz+eaB4O/AG0iC8SJofVp2apAQ29vRIxo+URABT1X7EAk2YP XBZBSV6sg48AbgQSNOXltxjle3f9zd4+0jzoex3KqFIi5B6Jhz3AIemALfWqZnvhUsy3ZD+O65+L z7iRBMVTD+Pzs/xo255Mwm9jeu/MYWRlZ68lFOi3zSBcsBItIlO/PPOAzyOyIWhU6OxP/SJDjuhF mE9ensZ7JNQAbDlglmjZ5EnmdEmyMjtRpUlTxLYNlwZYtyHFPLS1XmiE4UoTB36ClKq1wMYEsT46 j6OXa7Ae6Sz1zjvBXSolixvc4Q46i3M5pJxpTFpU/6tMz7IXkQGWUF6BRt9T27SEIResbJQgKlVX K5pPzrUYjfeh9dwsNU6un5VQLsQtkGbYUdCGgwrglawDVwvo+7GCXnSpxpjPUCGKCnT2WyzBmfOW Pi4Yih/HToHDNUkNypdJEZJ78w27VFhc6XgQl266RK3GoXcRm/4sxYpLwyPaWDBzuSb7qFS7Kfac d7s+Sqss1A2KS0zvlTMBW6j5yXVsQJl7Jbjc+1MNHWfsn0q9rxLoze2HT/OXytLWmfeOtJiPRp8J IPylF2iey2lTQ0Il2bLWnN/Twl7v8RsHM5XyIJlJaqJ5nhekSeOURwG5TsyiIfDcKuc/Gzpe9xgz 5t7aiOCvjTs9UUbNZSIgXj4tdBatEeuAht4UJpVXkWheAgt5qasssjYGpMdom+S+NWms1aa4c7cU rdrz5h2spaEGbgSz61nGMAfONrXan/iojpkD2AAiB/Gb5qug/KrwLDvp6HwKlPWXrBqwHAyhTPEh +dk1VMcvLdYrbwtUyZVi7JiQbap0gpDxQtw1Ce2MOTVUzcUMu5c+XRYSTaCnwMDZVr9vQIAFIKOE jgJSLbzPtsdcy8Bu1LS7pFjY1eKlqWq1LcfhJDCyblf6cEESmsGivg4uVmK6gp8PsPDNWvUy9zM+ q2us3j7GC/daeIegUa4TzRNbtGrBG3yf3zJLs583MMAGQBbczPg9dtSfI/AlQX+5alVGtbNoXrls ER7y8p+bbYSX0Rsw+ytWm/JkeKmiNuviV+SCxQVwdx2Q8CC1he63DAx0GuGOulCUdXuVidVG+GWu EGOqTIyMBG6qTzvG9T2dhRbujJLP+bWec1FYWqjz+YEStYcm80SqY5ilecjQdxJeE7b1PmYgDxTm /iqg8EJewLrF2IeYECtFqYPf0gFAMuWifV4XiS0Abc+f6+B3tCMDwC1yfUgcekyCRIe5P4A0Sql5 /3KWdaeh3eVrZmlsOZrgibyGtY2VofAGToxxZgCP3SvOncAv259/SlswvHOHEHw17krFaMaqwCXt KaZCUgELk4LMZwxd9nJc0AHVMT8TY52JyAm6C6MtRsL45cs8fPbzN29yicUJDgELyqd5OtLx6SnI vwdBT0Vxgws/He+tfW8WXytpb6TQ1weCZBOAaQtwNfhSJcV/CrQ0LMaDsjCORTqgPHtlhrDi6Whe s8BwlZfMZK7DjdE7BpbMDXkpW7xvwxjRxqgMdNmwg95N3EvPbmV+mYCluh6wuXgbJ5rxsKJUtKvW p5aJrbnhIiCATUNOVAABcb2v/V0ZDNPEnIDNkgN9lVy4qYdEIuL9/nuDeik9+0O20VXyd+R8dQN5 a4++rqVcbFmQQfjkfaXX+kiYIlQMhsmz1edAXnOT+UNQH0oqO6GtlTyMRPucmatg8js/JS6PVW4U R8Sy0xjX0CmVYvXlvVbfhR07kQjXfznA67gEZblgvpXTRoHX7Sr7DUNE7QXg1g4jtXgjBvVsO9lQ nQTrR8HadMCgElnYWB1MUrtROAGZoTnBxfHfUHgsSDhj9Feh9Idtwbv4JImkI6DiBrpiG0LQsYwp OsqCIY63+3K69v8JsJqbjGRU34iQm/j6nP0J3YsZ5iyWetQcQ2TqQPzClr10sj5B/QgVQTyy++Hw +s5CDh6ocLBpj1KbPY7um/k56sK0aOwlgg0wSqi35Av5YM7C1+wwS5nCmnNItHXe+WslwIVX83hL 6MEJPXqYQCfS9Rg+mVvASxz/v3FDbVwVKljjkFeJ7oxg+ho3TI9+lNBhY/B7rkDeIdIFgZIU2tkw UeGXme8J3NK/c4gOPpwyfBIWcKDThmGa0d4Se8XxxBtQQYCs7oXYBucxlKVkr3k290pU26hnkyau ULF2ny043WWmhqXJWDvG90oDuOI3KJftR54o9hysqhRD5maT+w04buQrPqf/xgr/vwEAM4VYTE6Z /Q68yFUrPHd1Q9zfVU8ItZu6kvc/iJDBGxiY689Lk9EKs5MdBis+rbZgKtnHgKQbkk6P8hvQ+Hz3 QrSvi6c1abPqfQTFzOl78QvOtpAxQXG42aYe1cumjaTO+YwHHL1/OcrmNug2WDB22+B5yYspHMMr pghggC5YE14ZK6SLRRyznvi6/0j6JhUfVvgPAp/DWQkh0XCEcgptvAjjhDXqI/DV5vcxdpZui3xq DgaHNZnLlN+AiSwhiUvdqdcAgAgbqWcppIqvXreYG/5DLtlu2KYqyFHwzd1jufRuB79FslLk+8kc pE2+4rpbb5I7+T2BfGWB49MciXCEEmlXlHRbI1aj8FMCawqNYI+SaTxAW2Lpb44opWQqc6rMs2MB RtxcdjCq6WcCe/a67b2uEW+Bn9IgNF9c5/Xd5KsX/yzm+GRQv4s5TRgvGOd1PmDS5CXpmgPbNMh1 7maofr4z/xm46/gy1FX+/cZzX4z8B4HWNSq8ao+MokF+twMaXFVVOoh19LMZeHpeAy+yaNOMUlB4 ZHByjXkYxiPQUoEEi8ZxUkWNQEXBxfS6JnfMTM6PitDDiUaH4v5mG+cgP/GyMwlwSbCVuYtd+ZLj Z1Vo8jk1TbUy4YwVZN6YZ7k8H5+bnhOdSlYm5VsvX4R0RPPfDElc+ULn1p8VVbAP22fDB7vjpg+r Fw+xC6TL7NY/It4Pt/lGmgYLhdOBItWGqWEw9w5BtgvKWICb7oKpkt0OYoL8RpgVrDKL4TZFPHEx TF+QEEAWi/qBHtpFefgmlcpp0cOMv/1SyDx/YosFuPM2nmj/S1kIQ0nIphjSxRlgDnTVx8V34pk8 BfzcQQWpAKoKcp1Sq3ls5m3tm309Er2uvSnwkiR3Py6zHkT3w0Hi9++VsmPe0btjY/REO7oyFVg6 R95dXw3Yho+iq+RM9mchg4BHOre9/KJbc65qPF47mKBnO+PvAmU+hl5lsEamo1BPencnba/P8o0z SbZN1wcIzlnbS1+XYPPlZO+lCOWnVCXwBiMxPiNzAUKHUY/ch6KpYGM4y8DzbzeWJKbQqJUx6bGw Htq8GEioSyFGOgSLfAgprrgSfvBbNnr3o+2XEN9i06V4HOGGP51M0BuhOZxsXM7LC17T2bno2lxx g3MNBexWh1Il+f7p32f0p4zchekCfXuxi9ewbdnsdhoTZWGMx1SR50pKRuetNKn4lG/wCYuBtMvh eN5mHMzz9sNs6mExAUsCDuuZTKFm5ozosPvCWIhsviNFQ4fJnmOAIQCyuybW9MU5ua9T08mNXEEJ 6lGpuV7d6XTL6AEyHe7ZfR+GlGyHtWFmnmuNh8HgVvtx++CDnqP1/WhsvQ8bDSZuW3NviXmCzWw4 Gt2pKlFzptQIC6Zfl3RnuK2c94Manvfx8P/8eYsrotrR06wP5TPCdnELK/6Umb/fbqzERjSedVtH C/XNkMeW/0AbeuNKu30powhGQj5XDKwjoJRQNXdKllJRgkWHMdkyLwAMMh5XSq75MVUJ1jGvRFpV kPtMik/7OSZ9aV9QgtERkL4tQVIKznYjD6cNl74hKrilOaPTxC3MnGUwgWgaMnkDyTGPbgI7IoQb SmbhzcikqOd6IUbBprZvw6ayE0OvckZjRoOfficSz7j67b0DUGKTTV1nbVEp4Ob/tBPY6NJsjJKb z4sTlAm4ozcDYfpnhcmgAHuXvHiFFBkMBNZ3rjYT2cEriQ9TFLF3mizXSvt6Y9lGNjnsELiSVkPZ RFto74jJku8Hss6xrKO49xXr32YVTl7TgSZBYBEReZSDER0F/9Smcx6PxcaJbEbHcoIgaCinTWDr xbClLt//kAW0biTwE+PgAgoIYlf7HXMO0iCrf0mD/NlAKxr1hLVveiz6c4/fddjlT+7789I5+4wX uP1L854G79hcQIDuJUlxMBN20YgfOFUJtzkDPbG4Y93b46Rzs6fZn3Zp53ui5gkJRnKQIx6wllzZ KGRD0se9BG6W4fHDS85OKRa84HvXcWNex6fUE86DO4fF3z/VLNoalpz8xfHzl/1BbFMTWoxvBuex Ewmn6Z7qXBrsz6rp605BFeNwjhcEl5rbKnvtx38car/MBj+kpci2RmvwtfYvrnFnmonQVEhlqqtb izVSQZTvDvDylxyI6KejyO+ad+O7KhFt1ObvtioLPhjtD8o4wAKHpqAR2Hu4XrAlkqR3GgQi33AY efXDINfwKWhvU4CTCyYdxJoAZuCZJp3VYpqygSeZPSM5WeY2E5wcbvPG7jTqIlnJ7NPBPkYnpns9 giuPumUmUOOcVFAh+1CMZW/i314PWY6dqh3jiFAUTMd2pAQlhzp0COASBkI8yHscCuL9e76LrNEl phK0zem4ZXVqvQfeVpDjlV1sqjkZH1bX/jm/plr8dpen5FxOm090bHN1BTwSx3G/mdGH75jaC27s ceIOGoUwoN/jYig7YwIJchD8FpwjGlocKJDBXKwQcEkAFDczNefFi4ziWDNI3YZTq5+thfPxOEFj TGGLOA97s/C58H/TQ02vedrKqR+cTEiVINTohDV+noR/pHiUWOgPDa/QVi9UZh1pv/uISiZ1dRQu Nq2qa1skuihcQK01oxJjvzePeXBQZ2qTzuUpfd5EN2ZyRny5dHBXJVMGeIYHDtTdh8pGBwDlAxYl 0G1e3k6mxqAjAIbYKg/fX/tnFMNY8haPyljcp4x2gBI4a0AZa6JtZpg9UfSlBe+Kl6KF9L3xTYMg ova0I+v2YhQPCmumDF1d+iDw3Fqkk8UoOkhh8DPP3LKU2pZJTLBSe2V02otyUo/C24nSt6n7MfV9 tTTVIzTvDeaMXwCb9GZxY/SeIJPOdaKmsmD1fMSCCsnr9aNmX0Y5pNUJDyTIuNBZAqVg1e4N4/bg wI/4dmn2Je6ixx8VUYRktKUsL6H5wc8cK16cWLMq7/XpfvPWADFWRlKdxzO4cRhSiYOka0YTRX7M d+cF5YXSMaXGd2imY96irnT526iu2uUVhoEnfCtxxvPuRf4jP6dwQ/W3Dwl5mjf6YgVw9LEvQdGD OtNhvBnzj9oO5OmZNsPpZlnZAu+wCFCaZnEsoT/8zttWrCWQYVLlmCMDGZqkIyYOmKZWq/gccVvR A5doD934rvPOkUR52VfkpIap29Zb34WqexqRn/0IC/DsFN7H73s2bLdm5k4vIdOSUJPrVoOMlunH fEgOAXDejR1OA0srkMW6DirEbc6T+3BH4lBAh1VqdqsQEAaOJZg2uHj7x06rVH+ZKKlimvQKRYKN vvaH3/maL+3obAIoMsvRXtzFP3BVjPVSDWlrQngRtmjDMASn4pDgQPic9xmdGeLucC8wW/D7bQqG 3vFNQaWdOwNAEAJg1Fxdrw4+FoSZ1+tJuaem1QXlLZp2MWnmc2naNfy0+frSvhWZLnd5HTZdmjZ8 jmmFY+wYNqnivDXnBgXQt+lTaZxmbiTsBDYd1LxnrPzBdWSLsYIHwSc4qknEunO5DFFeU7J/gRBD oLvMA11R0nbZW8FqjRQegzJTfXB3hCElqcU63wMkM3BDPrFqSn9jMY8AtqyTZmtrXoXB/JgzhAlu RWpCGYM/yQU+VaODjSS6ahedrwnZfEucVY3S9uIJOiCZKDxQP6gvtJwHr+r9mj8muQoOva/k7shP kDDFoYx7yIzd/PX18UAnuQw0swQiWnFq3Ysamrz3cEb3w7KCWCE0miZadUqagWh4Ui1EoA4BtTCm XH+ULndTI8KXBTQtdiSaIelm8c4+Hsg0C9LoAmezce4IxO4XYdeG5mTOuyhdvbaf5aZPhYiHfCiI 5byWtx4XeofT5LYNa+4oJv6J/fs5re14ShP++4ZKMOnGmUcB0xqymmMzKZeFzu5qZK9C+EJniLlZ 8X3ypMzEUK9VjeCEvjNhAi3kE6NAMjguWHtVAoxGk0FI/+e6I/x0exhvmD6+PsENXHhXNgiGv006 kLSDnkx+6CJgztcEI4r3sXw3dTeiaYYzJhTJUw/z+GZmodZpeCbVrsAMv6bW62Ock5wdtXqJagLV VSPRSxklebpditAz2peVOrKx6ekkD3hlFH10CWt7N0b6mlRFpGzRIbArJnIkhZImFhfLHYxrdG+u Q5QWVQ/qK1qjjWUkpMLZn8KZpRWY6Iv6/OD7Ms/rIAfGwrG0WQEh2CoA5kH+kVtf/KjD0kUznGzs uiq3DYtmVnkzXkjgSTWONZIQMe4uUy1cDbwde97AS+8lFfBBUOrzGikwN3CnatU4RSReVfMfsmj/ PiUvI+VVIfB7fLmIYirpkTyJlLbNqgCbxTC3/YUKvQeKsgdPYRZ1AQ+X2EECrxumRyYdjdzdM266 q/ngQdXkaptEq+pWick9hXGMZv4EXwb/JiIrIW7ZzIyeRw/iWU9yREE99wH8dhvG7F8ZuJYODoZq Z16s7UDgdwZUz1WAASUCVAfQ3Dz4Ys/qpMTTBwP5weg2M2dpSnI7P61q/kp34JaDu+mDwNRk0OwM S3MjEJmn7M9bosNMEbdM33rNvuBPGrGvt+N2snTNy1pQCQVZhjxY2RTzluBYwLnmqOulukiROf2T lArRBTBcutYaPwNKiLDgtbC263UZD7nXmBMnFbxEdHQ1ciWmpHo0nZ8vvOpG870/W9B0bIU00Zf/ mcQGtsdoYUq4AKCGeYuT86AIsnm9QubUYTdvBvU3355svrEH+FrAn85xkA6Qj+KEgjcTOsEO2c5v a8QvtrsHm7QlyZz4nmX0z+c2xrfYF4NYwB1W5swgvEVPbo4m3MZ2Px6uQ4tZ7Jr+wdowt/fLBqCX uejBBNkZayRvIeXXegOy82MWj9Sj5U8GmR2j4Ufp5Tz5cl09egSavAg314dcMTUbqJ6jko/G/s0z hal9n1np6/6hYCO88KZOCHYsK3yBMSXLeTryLK5iIwAmSKbm9hltXEyqJiU/Ykw2gjkbjNYFYZyK OHlDaFUUF8Dhk5sLXXK0BwJjB+7JpKt9g99BATyq2YOzoXh8tzq/r3PIhNKefbBMhJPdvtA7oWKl 9BfWupKNcvAuMYMENnX6MVjyiMEoFSq8Q2c0/0cv5SidXn6pvp27hiMYAviHq0/ii9bYOBmwWQID rFWstI+te9vAVdgtKckvIK+bTRd+gYyq9379EVHT83riumNh79bKQg0kgGASNv1Uw7qIDGI8AYe4 3Cr2lbdTaIBcgw2Tvs6tCkZTOj4tbt90jk+jhkBt/kfzyHkFq/hU1/tPwEg+ei1zO65wpOl2J/Hj zqdIelYk+Q2gMDD4UO7B4QJrq2maRaOh3NAPNsNttqNh9PtnRIZSIhmd5DeNgbe4Q8JUB1BBA/Db JsHJ28cwqoLKRQSTa9PtlDgLzK/NKIuy41SAJ1FSZmQK+bUhGdPEwKMPlvNOF86H3w3FB91qra5r t13g66yCkK2nICykaW0+ctvVWO3DnQt5dQNlWp3TtwC+UU5R3WJ4y/KFK7Tc+hyB5J1440FQbJoA mpuZepfQ443UsJjyxTanoZhHKOD7Yvpu9CUn6Zp2ktivQoqNB5T+rqM1EgThdTTt98MM8DcwEg1L cszhN8IqINLpY4sFYtBhA2qTuoeWkr5RoLqT1hNi7H2xnoLA/L0wQHLjIKKqmRGyBX70bMIj9bsY ch3AzRyhbdYrUqvruR4h/V1egVCDHLMUhpxyGacBypyCswL6q5ji2LFtQ7nVCqHSOqJc5Npym9fM /UrTlm/16RpH/DuxDBck+pbAmHknMlME1lvMkvsxo8vMkwGvPuIKZr7n+S8Om+Vv9ne6FuIdbzgk iY/KzqzQBx92OXH0B5uSdtUeXsIalMo9BN3mNG9UXV5y5BJ3MOvtnBPeTkI/N08QG6YKJzUS/iWl 4W/9JSe6d9oYzuciEUrxzlxX3HUS160cyAQ+ODwTRnDtLi1U4hRgGFgIOg8BwEs2ilLtuXDxORKl bDSwNX4I/PW/qhR06nNwbRjyVfIi4VEn0ULSFm8XIPzEJ/t+xQsSK8cRx3XShqsDrberE4kcF6tg TsuJ8lO5r8rDwKCZOzPkOktohxlDzfICQphnJ5xRK6sehksPxetSeYsrGBplI0VPdhJLFAsnUFJd Ev6OqHdkRzMJ8+CdkuLN/snC4oRaUvANsK0doQmZ9+c2NoNuhNcVod8kKpw/3twWUJdfa0QIGJyX qzI+dQhuU3lWQBhEcJhG2DzZaUbDxrbX3YCGd+k1wavEf7VqLSwaTmmEwdZ7jtRmuK6HJ0rRISjP f4bD6ffOZjQ6jYL8ORBWeiI18SoNK6YO5RYGBfBdFqyxzJNmYSlofk85khFYSEtHVqecaPnuaHdV A6gZQC8sgAX1dfe/II0uTSstSA85bk+rpeDP4VHMB0X1lMFwrpVV9b7Y1Di/T0f7rQn2P/PPC8vQ 4JLGXzybsadQGJ3W0zxfq6PJLdRyCfJyHIttZEiARP7nqBDcTIyFCg+PvJcQZ768hNO8jAeI5jbd msSsFZC4D3N1YQDVZwj/7vmIilJ+i9qJnvUTwUBySXbq4FY1JyZSGjV2GWZ29ruIU3MwbAdW8m1S 8XTvHsbcxiaPOc/0ek7gt+0+b74qNTeX6VWf7fYDz0SZaKntTeuiDevjmzuF77fbaITL/5ISEq+I BtyvYS29P3b9B8LA9WC1N7tSTt6E0OIJxmwZlujkOJES9mM6Z+91WHY59qFKpa2siTL4jl/unDC3 uOuUsFOdpOp6OgWVfA4U88/JJrs3XraZDrp7DLnvDxEiss4+J8j9p0bw9hfz/ZPt9o/6Uv8h+z0P 0FRGjl6c7lSreB79+W0JPk5s5gfUN6tTwD98zYuEjyv0TIOWxsgQQOUE3DPnCEkTyCCwTqLktu3p ZbAGkWSivgpDi8580gURDEmQKDXhnks2yBDsXxiZx+N+UqfI8u1RYwL7sKZVDsjL+5mS9igixKJu mi6g1L08K6EDnZY73csqvUrwEVmlRdOTzVloSY+YdTJFeGdmKYyB1As6DDkFKmSB+eztHKVE6V7J bnAUyg8DRbGxU4KXgrC4UiJRgUaSYSVe8KHSshXafQ7DPFMKCB/GechX2JL7p8dmDbJWRYbq3c3D VMhRwP3vts5oXVTfCoNn4Ep3xMja6QsusMNZi1papKFd3yVv1l4skzpTWAg6o9EWYEnqzjznoUT1 HrfRKo7S2KqkgK1g14Ipvf5gs4HrxpzJEgZuUK8pGZH8jbP71j6nuOlCB0Hpr3ERm4DrKn3/DIFV mT8lJzUbiW+KEHjV0PjT9SLWH25lIbLWQIRxB9dSjAmOM9k0j1SHqlfPU5PX9UQi41XcoqWF1/bf HnAiHpCNxFAyWodIw9PzqVGZ03ei4Us0GAC4j0PZBcaZ0jZTD4SYgR1WAaom04ad5An2SupDMqD6 i/zj1uMkN1ftCXWyyAYzEknvYDhlGSGqD+pgEx8jyNJwbLN6dijDF8o4EwiSgu4rs3zkTetGVXbL ZZiW6gvzetc8r8CVSkDS990IslEBE7FEog6tPOs9nAysN4zANCHAB/syxXsIqyaqDLxj08oCHAN9 Ea0E1TcxVd4p5aMrsZtaPXUny0WsQcZmrVua+pUORYcdpMtEpDhvNun7+d7Yexd7yMiL1GUXbGBn 55J7dkquCalG/Xmy9e4QOaxqOqW+fLjL9VWuDLKU9I4iXyc7CFC1H+GtUT/gMBymfmMxz/Q98/Yn inr8+5CbwWjD7si0setE2IM+NeUnQa/gtS4vfFkIdPi00vXllAM6pSC6/0QeBaWa3+r1czPVFObj PWH7rYqR1ooR25vC9ZbZT403w7uhulpM0H08ajEmWIAkOGsH5pQS088ug2MLhd/hO26L4IydGeo6 3NJdiNd2TsdbmuJoUSGGh8mJf7yFL20HUgmUQDeoEGFqgtWO9hcieiUbBjhXP6almms3b+QF7EB+ V36WocNhOtAOiQMUjP7amBx6BWL80y7ZG0C5mf8ceE1zlOP6JSqIKZ2W2ctmKMKCzQDQGvCAR697 3oxFl7KClk72SSKOq15uzytrapXDRz5aKpyyrxpphsZ65VzcLdqV6Dojj5fnaE4u7A9xRt46mmNI R3KCXahZ0diUKnV5O3bZX7GFF5iaaJHwiBCwxadX6E52fTHqJ9yr291p4tG0pUlhCni+Y4O37EEq fwWvrSrkv3NqI+z2V3Ifl7Zh1oY3E5v+/mO05jsJmthiTfptmfo4jfUKFl5vHlQUIKwDvAGQUvAg syriuscwJEXegC6+8l5wdH8flHjlXHsQa8+uBEqX7KqZ9C6wQSIvc4OmKI7Vz6KBtqEuFqTb5dHq /as5/RH/jGlNFwZjxlQZuD71nrhq4+Oz/jZbm1LpWZ5NXkc1Om9bx18JGA+1sYR1xe5R1zs/eay9 yQETW4yLT5sKie3PwxLcmjPq5ttZ540kwE4y/K8ZEX0dCsJvwBDTPvftVJVws32pLrhd6lavVuIV c5F/9O9wt3B4X1NWTlchrQwc9yKzvp5L5o1kr6Lg5IQe1eBkFQZX66eSgK5cWPkdqyq4yMniZEZ8 oYrcPivSsc4lOI7GEYsE8wLnE9clMOPlm9nriJxTDZ2i7/HmnL1Q0IiPMmg9kdgtz3VlAuMQN9RN R1iS9ykHnegJPyKBWmIO/K/BrHJen7afnI62YQbUp0Fr6IcNROoqq0bsYmSBruT3W75JIG0Cc174 /PyIiLpmjWhJ7sl+686Ml3/vhYFFD5jlDOQ8DLKpSmaMscH50ZsQihpoKJhP1JNtd9JrOd4SdQ+I px6bNnblous1n5h522nqwM6XosLtL/G87CJ/bOSeIdbixbyZHxJXOIxNuLdRQPb4QrqiDHXMQeah eWPEMuQpf6dnYjM1KnkKjxh/CxJtCRmkUjJe8WqDLzpdI6l/+L0JhoDyQuH/9S+V3bgmBC1C/tRk n6xVuQr19CtS+Xg8oQP9zBFToFMk0fN88FqXnqAkJ8BOu18iSPMpTTNWAs6kNUw84Po/gZ+fcy4X wB8bdIiQEAAztvib1K/zwMw+cMVzX195FEMZAJ617/s7L5wRqluMeECknM0HC9AsZb08tQ7q0FBH vl61Hyap/2Vjte/O/g8RlkXO6FICuys6T+qFHYHwrNzhUtaMXqkdGddnHVh/E343B0WBE9GXpeR7 lGji7OfIToIlLxunpXzjw57MBUgjLBCzZPsPSJSa4io30B0kMP+PCx+qFp//LncbGBwtgPWkAgHL IsQhLL/xfkZh/36LEGgpPNlnS4ETUoifcxEVusUOVrwv3/tleOCN1JMljt99t2sXt4GRoGCvQZaO NrVh3sd2KrXhII0gfcLdpbryzJwaZ80HMG8KCqLC3Ga0yT/FPdDa/eOJJ8KL7fQtaDwXSCL9cOhM Pe7qiIINL27Mim7MzaFHp5qUtpYlVv/Ex8bJ9zNFYLn0uO7H2Sn5JOuwuqmGkR2SNCz6Fupox8/z D8LVeAe26qFrZOsLD59zLdgbLl3asB1h8osvKcLkvCQCSXQjhQntaj3PjjbVBNWrOLztNATp3Env v0FW90WhtZiU9R0xHi1sqsHDYZ35slEh9gKRRyw9tKM9OLvY0Wg4XNA+mhDsls1SiQbQOqC9i+3X IxgawQKwDnEkrbn+DXTaV2CTV8ak6V9WIDsfw8rqGcrGaII+sQhmbbfZAvM1+uWubre3kQlezwuK PoVfogigSpV0tNW6S2/LnMr7OOLeHvpFV2ikQWTbx9oirYNSEPJbWoomWNdL8HgkwDoHyknAsPxN j+YV8KYlzrLNeOQqfh/dZ1RhZbz0DJMx6mPpZSv3wxe/cnCuLOq/t625aVMNRyuqV4nkGpV3bEKb Sq5w/UAdn289Ylqbk9amvEHPGi3JViwXmlml23kzleLaClulOSgtec660aGPQ+NkmvpfRKoQfS/Z jVqqGAIy+pKJbg1ijmXawOzL2MWbm9g1Cc0wUsDxw1SYbxQ8ZR7HaqEyPcCy+fJi512Ts0OLt5qe hnkaR6rzQ610uluGwmmaqnNe/JpmSETIqGhAZYlkGJgYqLau80r9i3vhe8k0QMKSaOnaLsiieYHs bR1H0Go+tU/Um5zKqEtjIUYxEFeFmLiPdU6qFVy1VqDviqJnMgToA/u4jaqI4/WkPz7i5Jwg5/M4 x8MIXD+CMxg4sM/KbEfro9Xcc9ysF5OStAOT3zn3Gs7dZkLSuboaLGS+QWJrsVH7jmxlxyQddLE1 ZuFeh6ItwlGKXuitv5MkMxWnZEOLwNPIHF9CfqES3PX8Mu4nHsdRb+xeNrbTC9mYEMvxQgMLtR8D UjQlZm9qIBKCdU1Qx+ssRmtB7hB6HpTDFkCXj7fw5EhPX/TWHxqRYe6TMnj2HlBZVK2FNWIwmoD1 z2kUSyWa2h/aKvRs9G+nWyPmT0j3dRuZqMkZBAsJuJp0iGYVKPICWos7uo4TYNqm0rrcN3UAhljZ WGlcu1o5LpU/rnRV0wzS2X+YMTxz0Giaz9gpJ/sqOdgBiuFYXJDckfQnKeOdLesW5Hhil6CCc1Uh PZ+acLCcStjGwBl9sxyAdpiJZGhoSZ0LyUTT+x2sWKi14HJ8c0pIAMvwq60AEthGSTnAXDu8y2+t 7WyNiUepk3gURbhqidaE/Pu3frJMq5BwZaFbR70Mj20NE7pA5Sg+BxQsaysUV/Grmfc6iap/u07k hQ0d58AwvkMOCUCRuVpGUzfEY7jAUB8logHqIYRt/Gg3y0TCL2GKpRYcBw/cXruXF4PsqphMbz9S EetAjixDXFHFuIwiRAeTjSQu70P6HOMpsfpe08dQVthvCCy+PudKH59SdelBTsNBPVcmyIumGsLb p3Tr6N9UjYyY90j4y+cAMp+4RmTgEegTSMeUbpbVeNYUI7Wu0H7RcjrVDrWSxtY6UPQ/Dx1hn8qj 5fAdd5SBIUcGlrHxWNN9a32r3ZZZEOsNVfCCYmVv+iAMDe0oNAodyu7w/q/qcwppLWxXUAMEhqSv vt75VzFD6UTBN6Gpl0xlB6ofPSHMtOTyMry+w3kvzLxLczALwH5vuuQScuo7eMKgVJ97jh/NbD5r 5mWWFGiiYGToHBdP0Yp76oOepOPjDn97NxkHvVoXYZY09wHSD67M7DoZ6mFay9tgR1MjVJ/07MrJ Gqfz5hsG/96fNz6NVX1sGtS4n/YCo+e5vOdb2lL9yfknjD5VeFRXw74rt2rZRVT4OGEKPY+z//f5 MErU7acWK7pqGvN10o4KvM2y7GPDIOdszj3V+5zGxaRsbenLDNz/YtPWlkVihCzomhhBXLtGRH5Z JIHrEch2Qq+V+cI65CSviLaYXN7wqiicv7a5JPIQbol/4EPgN4OFCYQx7GwDmjp8rX8jBjtws6fe y12wpztmaykpcO2/b5mJ+bm9tNHw+Z/vekRgHoQEBAAIaCdQWjCjxstRIm4LHDbTKa3gsUGCoSg2 Tbw/UUgoj+fFcKvzt4bjxU+RWbQ+f78UGB7OUEDSVYLkqHAfolUvw5rpm6Bw8FF2HsrtR378Iv0h J2pm/4MwDHnAxQVkpg/MDCQI5JVCaO8px+xlGOMtGC7/BMrIxTjYRqo9LpFGIlOwScNgfpBrvjAF 3yqFFXduKrWYOOTsTHz7o8jBXyo5MP9YEw0IiUsmX0Ykj+sSswtoOk3arr11bzp/SNylQ75n2S+t mSAvjUlBJW7JuAwA218g14d1KrExYh1l9OEOgcmp95E2XKHXZhmRgr+2+EYAvsMiLWwm8kIl41lt CGDTL5/3CqDKnHHzc9p858NOue+6MTuwSopBPSkq9Ita1y9kgJxrnJgafEl9BX3l4sBZFafEBDWh epXRZ0iTEE8b4dzZ2WnR+yF7sV56SvH/HVsJxHUGj+zvukJmGva8H5aEy8l4jveswxKcSi43vpPl rwLz6soAsP3MixinEYYI8v1A8JGWpttM+VzOMr+zkvLlCyk40XcWFzFjoKrW2dUgB0CaP+aq43jS yWTW75ZxP50PQBEVXeHGy78vMDCIZLPimV143fxuqyrO5X8utlxdTB8FDRds6fGAyxDcMyheh1tN jbaF6wMhWnEYH2zSkI3bG6VsUgLxEb8Vs4jXmF4C+cuuflN7r//s+jYo06cDgpOgqM53SmH9MIlw AYOYD3WJ13Nwr5+6Hb/ZyRksdUe9B1A6Aru73cRGAS0GDocaLdJVVtnqpqoq9jPi2ZzvlUDVJL2s BPS9o7k+dVVldul/SsgANNDzUm0Y8A/EuepyJEYnPZskvkY2kabzB0PR4OGwgpnmAkeXMX+YWAzj lJqDmsv2U5SyB8lx6NOOUKLTUiF0lgGRK7mg4YATGiLsCGuxeomuFVjC3oZzPFpx2ZTKeVNMyE/J VsfU4zQPsCpOYUrbxffaRilHAB6mm9kBpplbasLi68vkkXj+U7cyx2GRBT78H1iH5erJ4L6Io6sV FdjdPw9oOsGREAwYnhl49HB+rAKU3Ja0rLFRz0b+TiF6JjVQHosDcAIJ0BInTbxunV5DazDH+J9P QzmyGbzIyqpd0SFjlJzlvQ26OO1NW+W5q1yWN1bgXOivwqYXWGdLRqrze3QyjcT593wqN/Lf5FoU nS1xpsXAzeKlwCW5Tc38ArA7SsYn3BTRFc8Oyb/Wzm9tLCo/wJHDyn9DMTf/kn3TxBfQ7BSDfqmM Jg8x8ZVbJ8gTC6Wy7oabBzL34r2tznrdsgm4PNgTlJEajPkkdhzhecxD4aGpRo0qRQRrfTud7Mze V49P8U9kC8zzF3mSFQEN45MghlyzJS/w6oMZhzdtvH0MMkLmm6J55jQrjD/MmOpoMG6m6o9S7bgZ zLGok/elhTN0YwpezWoJ8s4XKgvpp9z5s5CH1AH+4M/La2tWKpGjn+6fgaIqQfVLqSetEMayZL5W g4x8+tLc/wKBoX2LVdScspDi89PBIxPHEj8XVVjnpwFQ2ORwc54wYlRYvMlhnNfMk6QmKZyDsb04 cLNCOgE8cCEU/NXXrmFoCj5BV59wYehYjW5rJb7dY6cNdG27z7m/gsKakAy+MsZkBcxY20ta8ujf 5PoJG6Ih28Zezexk4VfWoybDX6/Hi8k9kUVOHNFNhoqsHvv5kna0B70fctkMW/PEGsemkKX7VlQu ZP9243QAJSAesf1tiZIqUpwx3627F+HhAPGipKuBelFtdRXNcESyUBoZrPuF9C4QLjmUOise0g8k QLSwOKKDl+3LuhacLJUhLjLZhcm0WSe9BFx8iM0WxsRxEo39N/BAtAvdYt208h3w8AerunI+sCR1 ByJ+GV+eG3UCZjgcR+9/VozqwcBCZG72hPRCrf7pQxVwpqrTtHc36XVh4/xmtcceVhtsMPcVx/F+ PK0x06AeV7lK5kCUl2nfMSo/mr/+auY4FjNIRCa8yRfQPWTsOCdVC3cg0fLoAe/Fv3L5Vg+RImnQ YbEw8V8C4mXdZGpMbDS96EKSshF8yfCtsnxpuNmDR10S0VtePcn0zDrmum7uQH6TN4e7ficj01wU 8jL/vhOsGloFgPeJ2T2beG/LK3fXd4XIHAX88udns2ReMK7JONlH/4qwXxl5FKrMwzQy3bLwGgq4 m2ZUcUClHuAuMBFzCa2PCNCohOzTomBJVd+uFTPzW4ibW8rK3EhVDAgBFw6sJLTCYSYHO86d83zj souvG7MPaMSsGShxZ5FyQXGBmVfPD2CqZALYHqNqZENf07cH5sfE4L8L4+7O6sUcrb+Npb0LsWkE aewWKCLi4QElc+zRvASHrXDYv2bvzMc8lOk9fnThaqdFxjTMTiVr8BugLRnBSECgWUIsGwdnKF5R ADrDY8/8FFuiFvsw4liqb6FQdHROoUfVX6gVQmJNANCZcGttmn61FtAiAHWT6smZeC0RepcxyubY RJzldA8EUPuHQweNwtPqEFCUbLTvZMzmSs+ToHvnOy7U99iJogm130ZiiGLzEgKKPeSruhv4xHVV pK9SoEaXneexYJPF/Dxr5QGXK51vpobQeN+aSTEs3aEmnZbAwMtNfTP6bbibpJA/ZtL81rJCv6da A7rQ+/OsOA0VMvGCc3gpDWJDfoEs6fhivba+/06Z8SCaQIXCdS0Q1RiVcHw+UA5aLwMCJ0yFNb84 prxwUw7Hx/3YTuO/rlVxEYjAuz8WSCLSndjntzgGDfu0FJDvl03VUlx05elYViplu0Dzx0wQ+ffT BKDasDJlMt3ap8NZ5dsHGwXAc6MUM8btAYaoCOssIo96rOawxBHVnr+rqcBC3GVnnYJaPQqcVvY5 hsagQGLmqUma8Z048eCjiCPKdVPPZon6SfgMTOapvXaVP5eFRaWok8YDZIeQCPcJ7vNX6ib5cRXA oueUZzdXkljsGnm9SjTKFjoJf935JUt9vBvdzpCjZeSdMkUfvpAtHAiovo0K3mKb3ouOV7xYcRzR gBrQEqrC5PZjKcT44mSG6oDZNABCJ0JbEgvXJV2d4SzdMOdCoKLV53TArZCM1mY1fm4UtE4glFLa jtau4K5M7dwFZMiR9aePZPUUcEcxcbQL8mAwNrI4qklp1utJUh5BMatlsPLWFoURCxMmMpe8spNZ xdCtMpFccKC0dTz0eawQZyLIbM9SYj+Y+dMXrNhYndaw8SFOgZedp/W1EiIxHfnFhNip06mSqx+l Or8npo/OuOPJnY23NCx42e0aSQy3JEET6QmwDKo2PF7CadsQ4oUd5BWCRG7CK7gMMskUHIiIPYnO rtws9MrlEHxdAas4XjbT1WMwxJemYUqcl2ZjyzBmrm5cDPyeCiFNHeSrzQRulRomXnYoUf3XfcIY zBrmmGowEKsmSkuAwLy6PVsZN68uYw7TUP9Zh8Zl6t8o17YDwBLjN8jJNNTcYGvaR58E05M7PJrK 9rXQJzJZYmdKTc7cxuhL8HF7wtxFkyYqPKwD90tGfD26CViakChuKY59zAUPciUW8j3EMXo4cMEi xHWFFgXrw7EgzwSE7pQLFyk1njycQ688CuARfqwMwbsS4HG3Me6sIRAtHjZ1PVhoNcP6LMWIrU6t GffBsYylgoPbTfe8O6tTYu6oTo7RvdiW0tViu1XkihwTKJjtCgHDeVSgeVdbNPUafJMXiDmKT5YC 4c+Ih7u18V6qBar3pRkseN+F6//AYskUxAeYpUuwh9ifxbXfk1Rs/vcte3mc6TX+9ZfD/hbZivwJ cgySx0mpnPLaEWkAjLwCW2mehGmOZVJxucW2pgg5nBojO+m2/+WAG++EQ26eoLuZLqEMsSoboe4e hyztGjnTu5vHVtOHT0YMFXx8lHrOz21k1kWG/sSlnju0eaKFKZjWPoELxhfi/dq00xdvdhuGR1jY uJ1P2Gh+CCgRXy044opH95iRsHfO+dIscQoQ/mCA7SczM5lAtfjuEeXXVSQ/XsgK1n9aeBtOHbso 99R2WajBIGUeMypniu3VKUOfQjuPCapEaksz6Fq9148tokw1YE+HHP9/mi+W+J33QNNol19fG0vQ Cq8G5oVVxfFqMozcuwvKLeLCTYrwptE+WBeZgoSY2pWLjLbw0EXyTXhm7TA70LXNo09EV41UpjNt Jts6yCKP3q9XgSeafukZYENWE4aP/35k0cP7ALY= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block TRcoZtqjn2mG6m34VrAup3Ue3mXUdsp9Svi1yOdUyuJ18aNmZzMqBL74/JYXAGMp7kyUseTthYI3 PrI0QWq4hg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block FPMMqj9RaKUiXlcYwEXFaXQj6iTZvDXB3ovRbqMXkBKErB6okVtT7N25cw0P4DrPAX3uTf1/DjZP g9FGVgqB8LxAQapqrXO27frLQX/jtpP5BRN/3UyLQQ5tmeo2wvGsRYc6Ptmw5XXPXjfubR1uMIvq n/KnJrhMohYd24Nm6S0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block hmQ19Z9b511LayHM++uE0XsD77aCTvi2D5+tVo/slhNcSgfFOCWou7QB72DRXWqLm1hI0yRUpD++ 6M4B9gDAGymLNt4kJfLjIH35OM6bL+USAdP5LzqI73Y5A9Ex2dA7XXtW38Kapk4g+yOtlcspGQ3v mipApCouubIDIKzAKfit6i+3D5zl06BKC5+/oMSR90fI/572drXx35dvozy88MbJh8nfL5OjT9y6 tufG7IpOsbuhtIaWR26UAUyCxZ5GOOwUvB2fS9q4Es/JzlrcdmqBkwl4ixHzLmdkNChDQXjCJVtg DP9+/cLV+QeiYTROca+/iv6JtjPVTSGXYAp7KA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KGFNy15frm7DKeh26HgilQgudk+s92inzv6E6/4SwA14yIblinRVK3XaIL/wyVEMSS/Nvx17YpaU YVWGfrmqIII72ql+J97vctL8UoKOHRk+u89CmFhhNIsJnQoGfxdh8DOXKgydwIo8DtyknF+rigwD Wrn0cHGnf+DzHJ1IlOw= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block IRcwaJ9nbddmu/9RW2bhH0oH/sFHVn1S2tsx6hwo1+XOm3bHWHP+ulk+4hbdqZE1Olkl9QC1qtoY ePy+TB2nSwbY99tK/zHUTTzEr9V7pe7cC+aCydi5fu9j5sMPnFmsQadzUgekG4OiSkic9/qlG8tY Nia8+0GODU2GsN9eE2823xR9kslK5c5LHAFyOnzohuZuaNQpgH9FgGbNWtWQ6Q+SNaCkDDwUMJRB XMWJMBZ7ADG8CfZuEbYaJpB3sP361wZWR2CVzTkDaWPuOvVZnunE0ob6QwvKmIm6q/myrsa7qCip ZmcNqxskerCWcqETss8HlKwYY/ryLcmRLUXsbQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15248) `protect data_block lo2tFyFjziJNXhyZZC97XYl3f0ZrW0Q7WwUD9LVmJ9QBi2joO2dZ8TfhlWwhm39tu85pBzGhL0bU lLGx5TJC7bSGiCErXI+tXOdZbJN7BwD743jxvfTNU2raF5ycnehTY1hGqwT/pWpIC2JtRTQTyzBp jg0TCqLY1rtHmFowyZv6918XEG724JEsdzGw6PjyfRjRLZtokRZ+0zbRXq68SjqEoVWFXEf047xz U1lXxDoOT917H2vpfPYaJlAmCz0h8k1/fCal34SYbx73cHMUWFnCTybEbJmesL5gfaookMOfBxRk sWQIao+sOuGvP38D26sAUf3oTnFHhf4FeA0y0GfIpGs4c9o0m1EYVlZJolMEBOS91rz0jpo2qyO4 FotW+gt3+tARFTW3lkQliIHC7eWV+CzKIs05UnbWOX2SkiuLdqLxOSfvNuWxAtliF1fFNjG0J4e2 FfC9OGxbUUJo1RrpiOuacWpSLpdl4+QKPVWCQuyMstdh6mUS1MWuoq6F8/mRGq7yZL2pdZIpB7m1 FqTQVbrAzKa9Cqe54k3eQnNS00lwUaAnIU+CzSg7CoiosWSIBg71HYudiGoiBoBnZLEqIkt2ib0G YZPWoBJ4XLzNcluQ1Ajkwv/Xv7R2wBRSej0W3uwSBWm6fUAXxP2We4RT2a/8nGQcnRSmWtH6tvn1 toUbZDD8+Ooeq6eb0K8NO/8rJFhNJV7JNyQXElREEK63JtrgaSZcKCtnBW+wsroNhNIOskBUnQYV 0CCOIW97dIQavxtVUm8QElbLu5USzKEeLvh9GD+tbqC72nrYJbHQnB1ohbEHiElv0JwdtOtSflWL pytwBnhoxQ5UT0UDv+wUPioK6HKBPFktp1w2/8kV+msFfnPCYTZvAF2GVF73mpjIWNSQk99VZ/qf 9K6lAwSib3XEYyTtUO7OnwZNIJUwEDWugnn96iYwnYYes9kgSrOfR2iKOJcSmX2D1CE53neDgkVH xkC47PePhGeYQ+9CruOehZDBHHKc/Fx8iiqW1oWzim0a0wA8NBVV2OqueD1dwZX1CZsTEAO+2Mcf rJFOE7NbOnbN0WJ1EJ5BRuVz2S/x94hwZ8o4JmDKl5Pxa37bk/BXyfiPL6ngdHZz+s8AcqBsyTxu 25sSBxZaeLoumhdgEd1YTf2MrAQZF1LOmD7ZmxpQXxUqzDi0fCC9JKUEAusjFvHSE1xwVYpyGp4u JNI5GpLffojoQV8tfutFGd5oTy2RMT9ZAP6bmqaKWsy+rlq4PgDvJmiJxYPF+FxmKJy4Se7UTCQY 2tGopjkFaSVlGV15HPI95mnUmA4BX23/QHo7TwIzY1um4MKqhwtkxITazjhYc0NiEbzJcop6bimU 5Hd7Ad7cMRDj1a3Xo1DKie1GROb0LBMAKcfeNv2zhs1tkeLMXkNcvX+W8v63l3HmlbO7RZi15Cm/ 2BWj9XfFFMG99MOAbLXeMsJqC+dpxdTsOguJfZxshnmn34b5AcWmmOZRX9sgP8wpUknH+6V6v0GM M8HKbo+sm2eHaAl1FWozeJJQUvPa6Wc4rq7pSjwdGk5FV+syvS5mCsU1fEEac9pxRE2PbEr3vB2V DRnHV0llczoF8jgqeLDTmKG4oyKDJBnssnwbQCarP764MWnhOLRtJkEoKwN9+btcZ1VdJ1avFa94 J6sQAvRmJuUd70Mnii74Zk/EZfliu4yf5b41Xkp0j+lywStXrsAZDldoSf+yNBaEMrVsL3IBAJyL BOT1Rd4YxlmaqzqmbsQ5YRX4Ub5NyDh3sZ03W2HdiS0oJRlV45N5cK1OCkUQAY5cfVuPBGvt5GRA MlBA6ms8n2mGPaNAr3e1b7yydC71SvA2ReRI5Pd03Vz2SAqGhP/59Ge75gqaOW/G2IZoUC11UCDU 31QBFFxVvxTiuKYudkKmOFxFBtVpOVX5BR7/lN+BDExAVuiwAlh0Hu5VDxIm48y/OH9B/R5LdcxH Ekw8rrHH7EGDSZ9Fe373bH13i6PTtHSKCiscmJeqMg+iRxzvY+BYYAtvQxMeaM65oZeHO1cwWQAx ALVsCF6TftT/Rc9MlqkzPpIV2mJ55DHMAQWKWb8QkBjdcs/AB7cnCVg07jbNLP4Jy5RTGGXHwFPi MZhK6ZPQH+3FRieYtmnhUP7xTYheG0c8xaBl2Q5rzribOMk8lVx5rTzHrNPvYdjp66A593lzLTyd mzIocbG/auEuspS1QZ37zHsdA6+QMZzeVdz9hwhwNioBFtgScmQzWrGhF8ppCfURQNObhR+UQBk4 Mkpe9DtCAaggrUW4TaZ2P9ZWxLVzR7jpjApAJsYlqdHXGRaWPT0f7AbJhvzAPz9go8J4/wPMJWBA P8u7WpWVrvnCuVV5PCjsTYZ5eaTAG4JT+q9Roq18Gl60ZmctUFnPlsN2t8Iw2nY2ru895Etg/5MR Q5ic1xjhIY/r4T6qcoJurG+efqeTYn3BsbJIg3gg7va8t1gOGGJ5bTW7FEeibIl0IQPwmhiZXcaG ll+Rcykz2XZzDFCJm1kn2DSeQzDqXz+eaB4O/AG0iC8SJofVp2apAQ29vRIxo+URABT1X7EAk2YP XBZBSV6sg48AbgQSNOXltxjle3f9zd4+0jzoex3KqFIi5B6Jhz3AIemALfWqZnvhUsy3ZD+O65+L z7iRBMVTD+Pzs/xo255Mwm9jeu/MYWRlZ68lFOi3zSBcsBItIlO/PPOAzyOyIWhU6OxP/SJDjuhF mE9ensZ7JNQAbDlglmjZ5EnmdEmyMjtRpUlTxLYNlwZYtyHFPLS1XmiE4UoTB36ClKq1wMYEsT46 j6OXa7Ae6Sz1zjvBXSolixvc4Q46i3M5pJxpTFpU/6tMz7IXkQGWUF6BRt9T27SEIResbJQgKlVX K5pPzrUYjfeh9dwsNU6un5VQLsQtkGbYUdCGgwrglawDVwvo+7GCXnSpxpjPUCGKCnT2WyzBmfOW Pi4Yih/HToHDNUkNypdJEZJ78w27VFhc6XgQl266RK3GoXcRm/4sxYpLwyPaWDBzuSb7qFS7Kfac d7s+Sqss1A2KS0zvlTMBW6j5yXVsQJl7Jbjc+1MNHWfsn0q9rxLoze2HT/OXytLWmfeOtJiPRp8J IPylF2iey2lTQ0Il2bLWnN/Twl7v8RsHM5XyIJlJaqJ5nhekSeOURwG5TsyiIfDcKuc/Gzpe9xgz 5t7aiOCvjTs9UUbNZSIgXj4tdBatEeuAht4UJpVXkWheAgt5qasssjYGpMdom+S+NWms1aa4c7cU rdrz5h2spaEGbgSz61nGMAfONrXan/iojpkD2AAiB/Gb5qug/KrwLDvp6HwKlPWXrBqwHAyhTPEh +dk1VMcvLdYrbwtUyZVi7JiQbap0gpDxQtw1Ce2MOTVUzcUMu5c+XRYSTaCnwMDZVr9vQIAFIKOE jgJSLbzPtsdcy8Bu1LS7pFjY1eKlqWq1LcfhJDCyblf6cEESmsGivg4uVmK6gp8PsPDNWvUy9zM+ q2us3j7GC/daeIegUa4TzRNbtGrBG3yf3zJLs583MMAGQBbczPg9dtSfI/AlQX+5alVGtbNoXrls ER7y8p+bbYSX0Rsw+ytWm/JkeKmiNuviV+SCxQVwdx2Q8CC1he63DAx0GuGOulCUdXuVidVG+GWu EGOqTIyMBG6qTzvG9T2dhRbujJLP+bWec1FYWqjz+YEStYcm80SqY5ilecjQdxJeE7b1PmYgDxTm /iqg8EJewLrF2IeYECtFqYPf0gFAMuWifV4XiS0Abc+f6+B3tCMDwC1yfUgcekyCRIe5P4A0Sql5 /3KWdaeh3eVrZmlsOZrgibyGtY2VofAGToxxZgCP3SvOncAv259/SlswvHOHEHw17krFaMaqwCXt KaZCUgELk4LMZwxd9nJc0AHVMT8TY52JyAm6C6MtRsL45cs8fPbzN29yicUJDgELyqd5OtLx6SnI vwdBT0Vxgws/He+tfW8WXytpb6TQ1weCZBOAaQtwNfhSJcV/CrQ0LMaDsjCORTqgPHtlhrDi6Whe s8BwlZfMZK7DjdE7BpbMDXkpW7xvwxjRxqgMdNmwg95N3EvPbmV+mYCluh6wuXgbJ5rxsKJUtKvW p5aJrbnhIiCATUNOVAABcb2v/V0ZDNPEnIDNkgN9lVy4qYdEIuL9/nuDeik9+0O20VXyd+R8dQN5 a4++rqVcbFmQQfjkfaXX+kiYIlQMhsmz1edAXnOT+UNQH0oqO6GtlTyMRPucmatg8js/JS6PVW4U R8Sy0xjX0CmVYvXlvVbfhR07kQjXfznA67gEZblgvpXTRoHX7Sr7DUNE7QXg1g4jtXgjBvVsO9lQ nQTrR8HadMCgElnYWB1MUrtROAGZoTnBxfHfUHgsSDhj9Feh9Idtwbv4JImkI6DiBrpiG0LQsYwp OsqCIY63+3K69v8JsJqbjGRU34iQm/j6nP0J3YsZ5iyWetQcQ2TqQPzClr10sj5B/QgVQTyy++Hw +s5CDh6ocLBpj1KbPY7um/k56sK0aOwlgg0wSqi35Av5YM7C1+wwS5nCmnNItHXe+WslwIVX83hL 6MEJPXqYQCfS9Rg+mVvASxz/v3FDbVwVKljjkFeJ7oxg+ho3TI9+lNBhY/B7rkDeIdIFgZIU2tkw UeGXme8J3NK/c4gOPpwyfBIWcKDThmGa0d4Se8XxxBtQQYCs7oXYBucxlKVkr3k290pU26hnkyau ULF2ny043WWmhqXJWDvG90oDuOI3KJftR54o9hysqhRD5maT+w04buQrPqf/xgr/vwEAM4VYTE6Z /Q68yFUrPHd1Q9zfVU8ItZu6kvc/iJDBGxiY689Lk9EKs5MdBis+rbZgKtnHgKQbkk6P8hvQ+Hz3 QrSvi6c1abPqfQTFzOl78QvOtpAxQXG42aYe1cumjaTO+YwHHL1/OcrmNug2WDB22+B5yYspHMMr pghggC5YE14ZK6SLRRyznvi6/0j6JhUfVvgPAp/DWQkh0XCEcgptvAjjhDXqI/DV5vcxdpZui3xq DgaHNZnLlN+AiSwhiUvdqdcAgAgbqWcppIqvXreYG/5DLtlu2KYqyFHwzd1jufRuB79FslLk+8kc pE2+4rpbb5I7+T2BfGWB49MciXCEEmlXlHRbI1aj8FMCawqNYI+SaTxAW2Lpb44opWQqc6rMs2MB RtxcdjCq6WcCe/a67b2uEW+Bn9IgNF9c5/Xd5KsX/yzm+GRQv4s5TRgvGOd1PmDS5CXpmgPbNMh1 7maofr4z/xm46/gy1FX+/cZzX4z8B4HWNSq8ao+MokF+twMaXFVVOoh19LMZeHpeAy+yaNOMUlB4 ZHByjXkYxiPQUoEEi8ZxUkWNQEXBxfS6JnfMTM6PitDDiUaH4v5mG+cgP/GyMwlwSbCVuYtd+ZLj Z1Vo8jk1TbUy4YwVZN6YZ7k8H5+bnhOdSlYm5VsvX4R0RPPfDElc+ULn1p8VVbAP22fDB7vjpg+r Fw+xC6TL7NY/It4Pt/lGmgYLhdOBItWGqWEw9w5BtgvKWICb7oKpkt0OYoL8RpgVrDKL4TZFPHEx TF+QEEAWi/qBHtpFefgmlcpp0cOMv/1SyDx/YosFuPM2nmj/S1kIQ0nIphjSxRlgDnTVx8V34pk8 BfzcQQWpAKoKcp1Sq3ls5m3tm309Er2uvSnwkiR3Py6zHkT3w0Hi9++VsmPe0btjY/REO7oyFVg6 R95dXw3Yho+iq+RM9mchg4BHOre9/KJbc65qPF47mKBnO+PvAmU+hl5lsEamo1BPencnba/P8o0z SbZN1wcIzlnbS1+XYPPlZO+lCOWnVCXwBiMxPiNzAUKHUY/ch6KpYGM4y8DzbzeWJKbQqJUx6bGw Htq8GEioSyFGOgSLfAgprrgSfvBbNnr3o+2XEN9i06V4HOGGP51M0BuhOZxsXM7LC17T2bno2lxx g3MNBexWh1Il+f7p32f0p4zchekCfXuxi9ewbdnsdhoTZWGMx1SR50pKRuetNKn4lG/wCYuBtMvh eN5mHMzz9sNs6mExAUsCDuuZTKFm5ozosPvCWIhsviNFQ4fJnmOAIQCyuybW9MU5ua9T08mNXEEJ 6lGpuV7d6XTL6AEyHe7ZfR+GlGyHtWFmnmuNh8HgVvtx++CDnqP1/WhsvQ8bDSZuW3NviXmCzWw4 Gt2pKlFzptQIC6Zfl3RnuK2c94Manvfx8P/8eYsrotrR06wP5TPCdnELK/6Umb/fbqzERjSedVtH C/XNkMeW/0AbeuNKu30powhGQj5XDKwjoJRQNXdKllJRgkWHMdkyLwAMMh5XSq75MVUJ1jGvRFpV kPtMik/7OSZ9aV9QgtERkL4tQVIKznYjD6cNl74hKrilOaPTxC3MnGUwgWgaMnkDyTGPbgI7IoQb SmbhzcikqOd6IUbBprZvw6ayE0OvckZjRoOfficSz7j67b0DUGKTTV1nbVEp4Ob/tBPY6NJsjJKb z4sTlAm4ozcDYfpnhcmgAHuXvHiFFBkMBNZ3rjYT2cEriQ9TFLF3mizXSvt6Y9lGNjnsELiSVkPZ RFto74jJku8Hss6xrKO49xXr32YVTl7TgSZBYBEReZSDER0F/9Smcx6PxcaJbEbHcoIgaCinTWDr xbClLt//kAW0biTwE+PgAgoIYlf7HXMO0iCrf0mD/NlAKxr1hLVveiz6c4/fddjlT+7789I5+4wX uP1L854G79hcQIDuJUlxMBN20YgfOFUJtzkDPbG4Y93b46Rzs6fZn3Zp53ui5gkJRnKQIx6wllzZ KGRD0se9BG6W4fHDS85OKRa84HvXcWNex6fUE86DO4fF3z/VLNoalpz8xfHzl/1BbFMTWoxvBuex Ewmn6Z7qXBrsz6rp605BFeNwjhcEl5rbKnvtx38car/MBj+kpci2RmvwtfYvrnFnmonQVEhlqqtb izVSQZTvDvDylxyI6KejyO+ad+O7KhFt1ObvtioLPhjtD8o4wAKHpqAR2Hu4XrAlkqR3GgQi33AY efXDINfwKWhvU4CTCyYdxJoAZuCZJp3VYpqygSeZPSM5WeY2E5wcbvPG7jTqIlnJ7NPBPkYnpns9 giuPumUmUOOcVFAh+1CMZW/i314PWY6dqh3jiFAUTMd2pAQlhzp0COASBkI8yHscCuL9e76LrNEl phK0zem4ZXVqvQfeVpDjlV1sqjkZH1bX/jm/plr8dpen5FxOm090bHN1BTwSx3G/mdGH75jaC27s ceIOGoUwoN/jYig7YwIJchD8FpwjGlocKJDBXKwQcEkAFDczNefFi4ziWDNI3YZTq5+thfPxOEFj TGGLOA97s/C58H/TQ02vedrKqR+cTEiVINTohDV+noR/pHiUWOgPDa/QVi9UZh1pv/uISiZ1dRQu Nq2qa1skuihcQK01oxJjvzePeXBQZ2qTzuUpfd5EN2ZyRny5dHBXJVMGeIYHDtTdh8pGBwDlAxYl 0G1e3k6mxqAjAIbYKg/fX/tnFMNY8haPyljcp4x2gBI4a0AZa6JtZpg9UfSlBe+Kl6KF9L3xTYMg ova0I+v2YhQPCmumDF1d+iDw3Fqkk8UoOkhh8DPP3LKU2pZJTLBSe2V02otyUo/C24nSt6n7MfV9 tTTVIzTvDeaMXwCb9GZxY/SeIJPOdaKmsmD1fMSCCsnr9aNmX0Y5pNUJDyTIuNBZAqVg1e4N4/bg wI/4dmn2Je6ixx8VUYRktKUsL6H5wc8cK16cWLMq7/XpfvPWADFWRlKdxzO4cRhSiYOka0YTRX7M d+cF5YXSMaXGd2imY96irnT526iu2uUVhoEnfCtxxvPuRf4jP6dwQ/W3Dwl5mjf6YgVw9LEvQdGD OtNhvBnzj9oO5OmZNsPpZlnZAu+wCFCaZnEsoT/8zttWrCWQYVLlmCMDGZqkIyYOmKZWq/gccVvR A5doD934rvPOkUR52VfkpIap29Zb34WqexqRn/0IC/DsFN7H73s2bLdm5k4vIdOSUJPrVoOMlunH fEgOAXDejR1OA0srkMW6DirEbc6T+3BH4lBAh1VqdqsQEAaOJZg2uHj7x06rVH+ZKKlimvQKRYKN vvaH3/maL+3obAIoMsvRXtzFP3BVjPVSDWlrQngRtmjDMASn4pDgQPic9xmdGeLucC8wW/D7bQqG 3vFNQaWdOwNAEAJg1Fxdrw4+FoSZ1+tJuaem1QXlLZp2MWnmc2naNfy0+frSvhWZLnd5HTZdmjZ8 jmmFY+wYNqnivDXnBgXQt+lTaZxmbiTsBDYd1LxnrPzBdWSLsYIHwSc4qknEunO5DFFeU7J/gRBD oLvMA11R0nbZW8FqjRQegzJTfXB3hCElqcU63wMkM3BDPrFqSn9jMY8AtqyTZmtrXoXB/JgzhAlu RWpCGYM/yQU+VaODjSS6ahedrwnZfEucVY3S9uIJOiCZKDxQP6gvtJwHr+r9mj8muQoOva/k7shP kDDFoYx7yIzd/PX18UAnuQw0swQiWnFq3Ysamrz3cEb3w7KCWCE0miZadUqagWh4Ui1EoA4BtTCm XH+ULndTI8KXBTQtdiSaIelm8c4+Hsg0C9LoAmezce4IxO4XYdeG5mTOuyhdvbaf5aZPhYiHfCiI 5byWtx4XeofT5LYNa+4oJv6J/fs5re14ShP++4ZKMOnGmUcB0xqymmMzKZeFzu5qZK9C+EJniLlZ 8X3ypMzEUK9VjeCEvjNhAi3kE6NAMjguWHtVAoxGk0FI/+e6I/x0exhvmD6+PsENXHhXNgiGv006 kLSDnkx+6CJgztcEI4r3sXw3dTeiaYYzJhTJUw/z+GZmodZpeCbVrsAMv6bW62Ock5wdtXqJagLV VSPRSxklebpditAz2peVOrKx6ekkD3hlFH10CWt7N0b6mlRFpGzRIbArJnIkhZImFhfLHYxrdG+u Q5QWVQ/qK1qjjWUkpMLZn8KZpRWY6Iv6/OD7Ms/rIAfGwrG0WQEh2CoA5kH+kVtf/KjD0kUznGzs uiq3DYtmVnkzXkjgSTWONZIQMe4uUy1cDbwde97AS+8lFfBBUOrzGikwN3CnatU4RSReVfMfsmj/ PiUvI+VVIfB7fLmIYirpkTyJlLbNqgCbxTC3/YUKvQeKsgdPYRZ1AQ+X2EECrxumRyYdjdzdM266 q/ngQdXkaptEq+pWick9hXGMZv4EXwb/JiIrIW7ZzIyeRw/iWU9yREE99wH8dhvG7F8ZuJYODoZq Z16s7UDgdwZUz1WAASUCVAfQ3Dz4Ys/qpMTTBwP5weg2M2dpSnI7P61q/kp34JaDu+mDwNRk0OwM S3MjEJmn7M9bosNMEbdM33rNvuBPGrGvt+N2snTNy1pQCQVZhjxY2RTzluBYwLnmqOulukiROf2T lArRBTBcutYaPwNKiLDgtbC263UZD7nXmBMnFbxEdHQ1ciWmpHo0nZ8vvOpG870/W9B0bIU00Zf/ mcQGtsdoYUq4AKCGeYuT86AIsnm9QubUYTdvBvU3355svrEH+FrAn85xkA6Qj+KEgjcTOsEO2c5v a8QvtrsHm7QlyZz4nmX0z+c2xrfYF4NYwB1W5swgvEVPbo4m3MZ2Px6uQ4tZ7Jr+wdowt/fLBqCX uejBBNkZayRvIeXXegOy82MWj9Sj5U8GmR2j4Ufp5Tz5cl09egSavAg314dcMTUbqJ6jko/G/s0z hal9n1np6/6hYCO88KZOCHYsK3yBMSXLeTryLK5iIwAmSKbm9hltXEyqJiU/Ykw2gjkbjNYFYZyK OHlDaFUUF8Dhk5sLXXK0BwJjB+7JpKt9g99BATyq2YOzoXh8tzq/r3PIhNKefbBMhJPdvtA7oWKl 9BfWupKNcvAuMYMENnX6MVjyiMEoFSq8Q2c0/0cv5SidXn6pvp27hiMYAviHq0/ii9bYOBmwWQID rFWstI+te9vAVdgtKckvIK+bTRd+gYyq9379EVHT83riumNh79bKQg0kgGASNv1Uw7qIDGI8AYe4 3Cr2lbdTaIBcgw2Tvs6tCkZTOj4tbt90jk+jhkBt/kfzyHkFq/hU1/tPwEg+ei1zO65wpOl2J/Hj zqdIelYk+Q2gMDD4UO7B4QJrq2maRaOh3NAPNsNttqNh9PtnRIZSIhmd5DeNgbe4Q8JUB1BBA/Db JsHJ28cwqoLKRQSTa9PtlDgLzK/NKIuy41SAJ1FSZmQK+bUhGdPEwKMPlvNOF86H3w3FB91qra5r t13g66yCkK2nICykaW0+ctvVWO3DnQt5dQNlWp3TtwC+UU5R3WJ4y/KFK7Tc+hyB5J1440FQbJoA mpuZepfQ443UsJjyxTanoZhHKOD7Yvpu9CUn6Zp2ktivQoqNB5T+rqM1EgThdTTt98MM8DcwEg1L cszhN8IqINLpY4sFYtBhA2qTuoeWkr5RoLqT1hNi7H2xnoLA/L0wQHLjIKKqmRGyBX70bMIj9bsY ch3AzRyhbdYrUqvruR4h/V1egVCDHLMUhpxyGacBypyCswL6q5ji2LFtQ7nVCqHSOqJc5Npym9fM /UrTlm/16RpH/DuxDBck+pbAmHknMlME1lvMkvsxo8vMkwGvPuIKZr7n+S8Om+Vv9ne6FuIdbzgk iY/KzqzQBx92OXH0B5uSdtUeXsIalMo9BN3mNG9UXV5y5BJ3MOvtnBPeTkI/N08QG6YKJzUS/iWl 4W/9JSe6d9oYzuciEUrxzlxX3HUS160cyAQ+ODwTRnDtLi1U4hRgGFgIOg8BwEs2ilLtuXDxORKl bDSwNX4I/PW/qhR06nNwbRjyVfIi4VEn0ULSFm8XIPzEJ/t+xQsSK8cRx3XShqsDrberE4kcF6tg TsuJ8lO5r8rDwKCZOzPkOktohxlDzfICQphnJ5xRK6sehksPxetSeYsrGBplI0VPdhJLFAsnUFJd Ev6OqHdkRzMJ8+CdkuLN/snC4oRaUvANsK0doQmZ9+c2NoNuhNcVod8kKpw/3twWUJdfa0QIGJyX qzI+dQhuU3lWQBhEcJhG2DzZaUbDxrbX3YCGd+k1wavEf7VqLSwaTmmEwdZ7jtRmuK6HJ0rRISjP f4bD6ffOZjQ6jYL8ORBWeiI18SoNK6YO5RYGBfBdFqyxzJNmYSlofk85khFYSEtHVqecaPnuaHdV A6gZQC8sgAX1dfe/II0uTSstSA85bk+rpeDP4VHMB0X1lMFwrpVV9b7Y1Di/T0f7rQn2P/PPC8vQ 4JLGXzybsadQGJ3W0zxfq6PJLdRyCfJyHIttZEiARP7nqBDcTIyFCg+PvJcQZ768hNO8jAeI5jbd msSsFZC4D3N1YQDVZwj/7vmIilJ+i9qJnvUTwUBySXbq4FY1JyZSGjV2GWZ29ruIU3MwbAdW8m1S 8XTvHsbcxiaPOc/0ek7gt+0+b74qNTeX6VWf7fYDz0SZaKntTeuiDevjmzuF77fbaITL/5ISEq+I BtyvYS29P3b9B8LA9WC1N7tSTt6E0OIJxmwZlujkOJES9mM6Z+91WHY59qFKpa2siTL4jl/unDC3 uOuUsFOdpOp6OgWVfA4U88/JJrs3XraZDrp7DLnvDxEiss4+J8j9p0bw9hfz/ZPt9o/6Uv8h+z0P 0FRGjl6c7lSreB79+W0JPk5s5gfUN6tTwD98zYuEjyv0TIOWxsgQQOUE3DPnCEkTyCCwTqLktu3p ZbAGkWSivgpDi8580gURDEmQKDXhnks2yBDsXxiZx+N+UqfI8u1RYwL7sKZVDsjL+5mS9igixKJu mi6g1L08K6EDnZY73csqvUrwEVmlRdOTzVloSY+YdTJFeGdmKYyB1As6DDkFKmSB+eztHKVE6V7J bnAUyg8DRbGxU4KXgrC4UiJRgUaSYSVe8KHSshXafQ7DPFMKCB/GechX2JL7p8dmDbJWRYbq3c3D VMhRwP3vts5oXVTfCoNn4Ep3xMja6QsusMNZi1papKFd3yVv1l4skzpTWAg6o9EWYEnqzjznoUT1 HrfRKo7S2KqkgK1g14Ipvf5gs4HrxpzJEgZuUK8pGZH8jbP71j6nuOlCB0Hpr3ERm4DrKn3/DIFV mT8lJzUbiW+KEHjV0PjT9SLWH25lIbLWQIRxB9dSjAmOM9k0j1SHqlfPU5PX9UQi41XcoqWF1/bf HnAiHpCNxFAyWodIw9PzqVGZ03ei4Us0GAC4j0PZBcaZ0jZTD4SYgR1WAaom04ad5An2SupDMqD6 i/zj1uMkN1ftCXWyyAYzEknvYDhlGSGqD+pgEx8jyNJwbLN6dijDF8o4EwiSgu4rs3zkTetGVXbL ZZiW6gvzetc8r8CVSkDS990IslEBE7FEog6tPOs9nAysN4zANCHAB/syxXsIqyaqDLxj08oCHAN9 Ea0E1TcxVd4p5aMrsZtaPXUny0WsQcZmrVua+pUORYcdpMtEpDhvNun7+d7Yexd7yMiL1GUXbGBn 55J7dkquCalG/Xmy9e4QOaxqOqW+fLjL9VWuDLKU9I4iXyc7CFC1H+GtUT/gMBymfmMxz/Q98/Yn inr8+5CbwWjD7si0setE2IM+NeUnQa/gtS4vfFkIdPi00vXllAM6pSC6/0QeBaWa3+r1czPVFObj PWH7rYqR1ooR25vC9ZbZT403w7uhulpM0H08ajEmWIAkOGsH5pQS088ug2MLhd/hO26L4IydGeo6 3NJdiNd2TsdbmuJoUSGGh8mJf7yFL20HUgmUQDeoEGFqgtWO9hcieiUbBjhXP6almms3b+QF7EB+ V36WocNhOtAOiQMUjP7amBx6BWL80y7ZG0C5mf8ceE1zlOP6JSqIKZ2W2ctmKMKCzQDQGvCAR697 3oxFl7KClk72SSKOq15uzytrapXDRz5aKpyyrxpphsZ65VzcLdqV6Dojj5fnaE4u7A9xRt46mmNI R3KCXahZ0diUKnV5O3bZX7GFF5iaaJHwiBCwxadX6E52fTHqJ9yr291p4tG0pUlhCni+Y4O37EEq fwWvrSrkv3NqI+z2V3Ifl7Zh1oY3E5v+/mO05jsJmthiTfptmfo4jfUKFl5vHlQUIKwDvAGQUvAg syriuscwJEXegC6+8l5wdH8flHjlXHsQa8+uBEqX7KqZ9C6wQSIvc4OmKI7Vz6KBtqEuFqTb5dHq /as5/RH/jGlNFwZjxlQZuD71nrhq4+Oz/jZbm1LpWZ5NXkc1Om9bx18JGA+1sYR1xe5R1zs/eay9 yQETW4yLT5sKie3PwxLcmjPq5ttZ540kwE4y/K8ZEX0dCsJvwBDTPvftVJVws32pLrhd6lavVuIV c5F/9O9wt3B4X1NWTlchrQwc9yKzvp5L5o1kr6Lg5IQe1eBkFQZX66eSgK5cWPkdqyq4yMniZEZ8 oYrcPivSsc4lOI7GEYsE8wLnE9clMOPlm9nriJxTDZ2i7/HmnL1Q0IiPMmg9kdgtz3VlAuMQN9RN R1iS9ykHnegJPyKBWmIO/K/BrHJen7afnI62YQbUp0Fr6IcNROoqq0bsYmSBruT3W75JIG0Cc174 /PyIiLpmjWhJ7sl+686Ml3/vhYFFD5jlDOQ8DLKpSmaMscH50ZsQihpoKJhP1JNtd9JrOd4SdQ+I px6bNnblous1n5h522nqwM6XosLtL/G87CJ/bOSeIdbixbyZHxJXOIxNuLdRQPb4QrqiDHXMQeah eWPEMuQpf6dnYjM1KnkKjxh/CxJtCRmkUjJe8WqDLzpdI6l/+L0JhoDyQuH/9S+V3bgmBC1C/tRk n6xVuQr19CtS+Xg8oQP9zBFToFMk0fN88FqXnqAkJ8BOu18iSPMpTTNWAs6kNUw84Po/gZ+fcy4X wB8bdIiQEAAztvib1K/zwMw+cMVzX195FEMZAJ617/s7L5wRqluMeECknM0HC9AsZb08tQ7q0FBH vl61Hyap/2Vjte/O/g8RlkXO6FICuys6T+qFHYHwrNzhUtaMXqkdGddnHVh/E343B0WBE9GXpeR7 lGji7OfIToIlLxunpXzjw57MBUgjLBCzZPsPSJSa4io30B0kMP+PCx+qFp//LncbGBwtgPWkAgHL IsQhLL/xfkZh/36LEGgpPNlnS4ETUoifcxEVusUOVrwv3/tleOCN1JMljt99t2sXt4GRoGCvQZaO NrVh3sd2KrXhII0gfcLdpbryzJwaZ80HMG8KCqLC3Ga0yT/FPdDa/eOJJ8KL7fQtaDwXSCL9cOhM Pe7qiIINL27Mim7MzaFHp5qUtpYlVv/Ex8bJ9zNFYLn0uO7H2Sn5JOuwuqmGkR2SNCz6Fupox8/z D8LVeAe26qFrZOsLD59zLdgbLl3asB1h8osvKcLkvCQCSXQjhQntaj3PjjbVBNWrOLztNATp3Env v0FW90WhtZiU9R0xHi1sqsHDYZ35slEh9gKRRyw9tKM9OLvY0Wg4XNA+mhDsls1SiQbQOqC9i+3X IxgawQKwDnEkrbn+DXTaV2CTV8ak6V9WIDsfw8rqGcrGaII+sQhmbbfZAvM1+uWubre3kQlezwuK PoVfogigSpV0tNW6S2/LnMr7OOLeHvpFV2ikQWTbx9oirYNSEPJbWoomWNdL8HgkwDoHyknAsPxN j+YV8KYlzrLNeOQqfh/dZ1RhZbz0DJMx6mPpZSv3wxe/cnCuLOq/t625aVMNRyuqV4nkGpV3bEKb Sq5w/UAdn289Ylqbk9amvEHPGi3JViwXmlml23kzleLaClulOSgtec660aGPQ+NkmvpfRKoQfS/Z jVqqGAIy+pKJbg1ijmXawOzL2MWbm9g1Cc0wUsDxw1SYbxQ8ZR7HaqEyPcCy+fJi512Ts0OLt5qe hnkaR6rzQ610uluGwmmaqnNe/JpmSETIqGhAZYlkGJgYqLau80r9i3vhe8k0QMKSaOnaLsiieYHs bR1H0Go+tU/Um5zKqEtjIUYxEFeFmLiPdU6qFVy1VqDviqJnMgToA/u4jaqI4/WkPz7i5Jwg5/M4 x8MIXD+CMxg4sM/KbEfro9Xcc9ysF5OStAOT3zn3Gs7dZkLSuboaLGS+QWJrsVH7jmxlxyQddLE1 ZuFeh6ItwlGKXuitv5MkMxWnZEOLwNPIHF9CfqES3PX8Mu4nHsdRb+xeNrbTC9mYEMvxQgMLtR8D UjQlZm9qIBKCdU1Qx+ssRmtB7hB6HpTDFkCXj7fw5EhPX/TWHxqRYe6TMnj2HlBZVK2FNWIwmoD1 z2kUSyWa2h/aKvRs9G+nWyPmT0j3dRuZqMkZBAsJuJp0iGYVKPICWos7uo4TYNqm0rrcN3UAhljZ WGlcu1o5LpU/rnRV0wzS2X+YMTxz0Giaz9gpJ/sqOdgBiuFYXJDckfQnKeOdLesW5Hhil6CCc1Uh PZ+acLCcStjGwBl9sxyAdpiJZGhoSZ0LyUTT+x2sWKi14HJ8c0pIAMvwq60AEthGSTnAXDu8y2+t 7WyNiUepk3gURbhqidaE/Pu3frJMq5BwZaFbR70Mj20NE7pA5Sg+BxQsaysUV/Grmfc6iap/u07k hQ0d58AwvkMOCUCRuVpGUzfEY7jAUB8logHqIYRt/Gg3y0TCL2GKpRYcBw/cXruXF4PsqphMbz9S EetAjixDXFHFuIwiRAeTjSQu70P6HOMpsfpe08dQVthvCCy+PudKH59SdelBTsNBPVcmyIumGsLb p3Tr6N9UjYyY90j4y+cAMp+4RmTgEegTSMeUbpbVeNYUI7Wu0H7RcjrVDrWSxtY6UPQ/Dx1hn8qj 5fAdd5SBIUcGlrHxWNN9a32r3ZZZEOsNVfCCYmVv+iAMDe0oNAodyu7w/q/qcwppLWxXUAMEhqSv vt75VzFD6UTBN6Gpl0xlB6ofPSHMtOTyMry+w3kvzLxLczALwH5vuuQScuo7eMKgVJ97jh/NbD5r 5mWWFGiiYGToHBdP0Yp76oOepOPjDn97NxkHvVoXYZY09wHSD67M7DoZ6mFay9tgR1MjVJ/07MrJ Gqfz5hsG/96fNz6NVX1sGtS4n/YCo+e5vOdb2lL9yfknjD5VeFRXw74rt2rZRVT4OGEKPY+z//f5 MErU7acWK7pqGvN10o4KvM2y7GPDIOdszj3V+5zGxaRsbenLDNz/YtPWlkVihCzomhhBXLtGRH5Z JIHrEch2Qq+V+cI65CSviLaYXN7wqiicv7a5JPIQbol/4EPgN4OFCYQx7GwDmjp8rX8jBjtws6fe y12wpztmaykpcO2/b5mJ+bm9tNHw+Z/vekRgHoQEBAAIaCdQWjCjxstRIm4LHDbTKa3gsUGCoSg2 Tbw/UUgoj+fFcKvzt4bjxU+RWbQ+f78UGB7OUEDSVYLkqHAfolUvw5rpm6Bw8FF2HsrtR378Iv0h J2pm/4MwDHnAxQVkpg/MDCQI5JVCaO8px+xlGOMtGC7/BMrIxTjYRqo9LpFGIlOwScNgfpBrvjAF 3yqFFXduKrWYOOTsTHz7o8jBXyo5MP9YEw0IiUsmX0Ykj+sSswtoOk3arr11bzp/SNylQ75n2S+t mSAvjUlBJW7JuAwA218g14d1KrExYh1l9OEOgcmp95E2XKHXZhmRgr+2+EYAvsMiLWwm8kIl41lt CGDTL5/3CqDKnHHzc9p858NOue+6MTuwSopBPSkq9Ita1y9kgJxrnJgafEl9BX3l4sBZFafEBDWh epXRZ0iTEE8b4dzZ2WnR+yF7sV56SvH/HVsJxHUGj+zvukJmGva8H5aEy8l4jveswxKcSi43vpPl rwLz6soAsP3MixinEYYI8v1A8JGWpttM+VzOMr+zkvLlCyk40XcWFzFjoKrW2dUgB0CaP+aq43jS yWTW75ZxP50PQBEVXeHGy78vMDCIZLPimV143fxuqyrO5X8utlxdTB8FDRds6fGAyxDcMyheh1tN jbaF6wMhWnEYH2zSkI3bG6VsUgLxEb8Vs4jXmF4C+cuuflN7r//s+jYo06cDgpOgqM53SmH9MIlw AYOYD3WJ13Nwr5+6Hb/ZyRksdUe9B1A6Aru73cRGAS0GDocaLdJVVtnqpqoq9jPi2ZzvlUDVJL2s BPS9o7k+dVVldul/SsgANNDzUm0Y8A/EuepyJEYnPZskvkY2kabzB0PR4OGwgpnmAkeXMX+YWAzj lJqDmsv2U5SyB8lx6NOOUKLTUiF0lgGRK7mg4YATGiLsCGuxeomuFVjC3oZzPFpx2ZTKeVNMyE/J VsfU4zQPsCpOYUrbxffaRilHAB6mm9kBpplbasLi68vkkXj+U7cyx2GRBT78H1iH5erJ4L6Io6sV FdjdPw9oOsGREAwYnhl49HB+rAKU3Ja0rLFRz0b+TiF6JjVQHosDcAIJ0BInTbxunV5DazDH+J9P QzmyGbzIyqpd0SFjlJzlvQ26OO1NW+W5q1yWN1bgXOivwqYXWGdLRqrze3QyjcT593wqN/Lf5FoU nS1xpsXAzeKlwCW5Tc38ArA7SsYn3BTRFc8Oyb/Wzm9tLCo/wJHDyn9DMTf/kn3TxBfQ7BSDfqmM Jg8x8ZVbJ8gTC6Wy7oabBzL34r2tznrdsgm4PNgTlJEajPkkdhzhecxD4aGpRo0qRQRrfTud7Mze V49P8U9kC8zzF3mSFQEN45MghlyzJS/w6oMZhzdtvH0MMkLmm6J55jQrjD/MmOpoMG6m6o9S7bgZ zLGok/elhTN0YwpezWoJ8s4XKgvpp9z5s5CH1AH+4M/La2tWKpGjn+6fgaIqQfVLqSetEMayZL5W g4x8+tLc/wKBoX2LVdScspDi89PBIxPHEj8XVVjnpwFQ2ORwc54wYlRYvMlhnNfMk6QmKZyDsb04 cLNCOgE8cCEU/NXXrmFoCj5BV59wYehYjW5rJb7dY6cNdG27z7m/gsKakAy+MsZkBcxY20ta8ujf 5PoJG6Ih28Zezexk4VfWoybDX6/Hi8k9kUVOHNFNhoqsHvv5kna0B70fctkMW/PEGsemkKX7VlQu ZP9243QAJSAesf1tiZIqUpwx3627F+HhAPGipKuBelFtdRXNcESyUBoZrPuF9C4QLjmUOise0g8k QLSwOKKDl+3LuhacLJUhLjLZhcm0WSe9BFx8iM0WxsRxEo39N/BAtAvdYt208h3w8AerunI+sCR1 ByJ+GV+eG3UCZjgcR+9/VozqwcBCZG72hPRCrf7pQxVwpqrTtHc36XVh4/xmtcceVhtsMPcVx/F+ PK0x06AeV7lK5kCUl2nfMSo/mr/+auY4FjNIRCa8yRfQPWTsOCdVC3cg0fLoAe/Fv3L5Vg+RImnQ YbEw8V8C4mXdZGpMbDS96EKSshF8yfCtsnxpuNmDR10S0VtePcn0zDrmum7uQH6TN4e7ficj01wU 8jL/vhOsGloFgPeJ2T2beG/LK3fXd4XIHAX88udns2ReMK7JONlH/4qwXxl5FKrMwzQy3bLwGgq4 m2ZUcUClHuAuMBFzCa2PCNCohOzTomBJVd+uFTPzW4ibW8rK3EhVDAgBFw6sJLTCYSYHO86d83zj souvG7MPaMSsGShxZ5FyQXGBmVfPD2CqZALYHqNqZENf07cH5sfE4L8L4+7O6sUcrb+Npb0LsWkE aewWKCLi4QElc+zRvASHrXDYv2bvzMc8lOk9fnThaqdFxjTMTiVr8BugLRnBSECgWUIsGwdnKF5R ADrDY8/8FFuiFvsw4liqb6FQdHROoUfVX6gVQmJNANCZcGttmn61FtAiAHWT6smZeC0RepcxyubY RJzldA8EUPuHQweNwtPqEFCUbLTvZMzmSs+ToHvnOy7U99iJogm130ZiiGLzEgKKPeSruhv4xHVV pK9SoEaXneexYJPF/Dxr5QGXK51vpobQeN+aSTEs3aEmnZbAwMtNfTP6bbibpJA/ZtL81rJCv6da A7rQ+/OsOA0VMvGCc3gpDWJDfoEs6fhivba+/06Z8SCaQIXCdS0Q1RiVcHw+UA5aLwMCJ0yFNb84 prxwUw7Hx/3YTuO/rlVxEYjAuz8WSCLSndjntzgGDfu0FJDvl03VUlx05elYViplu0Dzx0wQ+ffT BKDasDJlMt3ap8NZ5dsHGwXAc6MUM8btAYaoCOssIo96rOawxBHVnr+rqcBC3GVnnYJaPQqcVvY5 hsagQGLmqUma8Z048eCjiCPKdVPPZon6SfgMTOapvXaVP5eFRaWok8YDZIeQCPcJ7vNX6ib5cRXA oueUZzdXkljsGnm9SjTKFjoJf935JUt9vBvdzpCjZeSdMkUfvpAtHAiovo0K3mKb3ouOV7xYcRzR gBrQEqrC5PZjKcT44mSG6oDZNABCJ0JbEgvXJV2d4SzdMOdCoKLV53TArZCM1mY1fm4UtE4glFLa jtau4K5M7dwFZMiR9aePZPUUcEcxcbQL8mAwNrI4qklp1utJUh5BMatlsPLWFoURCxMmMpe8spNZ xdCtMpFccKC0dTz0eawQZyLIbM9SYj+Y+dMXrNhYndaw8SFOgZedp/W1EiIxHfnFhNip06mSqx+l Or8npo/OuOPJnY23NCx42e0aSQy3JEET6QmwDKo2PF7CadsQ4oUd5BWCRG7CK7gMMskUHIiIPYnO rtws9MrlEHxdAas4XjbT1WMwxJemYUqcl2ZjyzBmrm5cDPyeCiFNHeSrzQRulRomXnYoUf3XfcIY zBrmmGowEKsmSkuAwLy6PVsZN68uYw7TUP9Zh8Zl6t8o17YDwBLjN8jJNNTcYGvaR58E05M7PJrK 9rXQJzJZYmdKTc7cxuhL8HF7wtxFkyYqPKwD90tGfD26CViakChuKY59zAUPciUW8j3EMXo4cMEi xHWFFgXrw7EgzwSE7pQLFyk1njycQ688CuARfqwMwbsS4HG3Me6sIRAtHjZ1PVhoNcP6LMWIrU6t GffBsYylgoPbTfe8O6tTYu6oTo7RvdiW0tViu1XkihwTKJjtCgHDeVSgeVdbNPUafJMXiDmKT5YC 4c+Ih7u18V6qBar3pRkseN+F6//AYskUxAeYpUuwh9ifxbXfk1Rs/vcte3mc6TX+9ZfD/hbZivwJ cgySx0mpnPLaEWkAjLwCW2mehGmOZVJxucW2pgg5nBojO+m2/+WAG++EQ26eoLuZLqEMsSoboe4e hyztGjnTu5vHVtOHT0YMFXx8lHrOz21k1kWG/sSlnju0eaKFKZjWPoELxhfi/dq00xdvdhuGR1jY uJ1P2Gh+CCgRXy044opH95iRsHfO+dIscQoQ/mCA7SczM5lAtfjuEeXXVSQ/XsgK1n9aeBtOHbso 99R2WajBIGUeMypniu3VKUOfQjuPCapEaksz6Fq9148tokw1YE+HHP9/mi+W+J33QNNol19fG0vQ Cq8G5oVVxfFqMozcuwvKLeLCTYrwptE+WBeZgoSY2pWLjLbw0EXyTXhm7TA70LXNo09EV41UpjNt Jts6yCKP3q9XgSeafukZYENWE4aP/35k0cP7ALY= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block TRcoZtqjn2mG6m34VrAup3Ue3mXUdsp9Svi1yOdUyuJ18aNmZzMqBL74/JYXAGMp7kyUseTthYI3 PrI0QWq4hg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block FPMMqj9RaKUiXlcYwEXFaXQj6iTZvDXB3ovRbqMXkBKErB6okVtT7N25cw0P4DrPAX3uTf1/DjZP g9FGVgqB8LxAQapqrXO27frLQX/jtpP5BRN/3UyLQQ5tmeo2wvGsRYc6Ptmw5XXPXjfubR1uMIvq n/KnJrhMohYd24Nm6S0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block hmQ19Z9b511LayHM++uE0XsD77aCTvi2D5+tVo/slhNcSgfFOCWou7QB72DRXWqLm1hI0yRUpD++ 6M4B9gDAGymLNt4kJfLjIH35OM6bL+USAdP5LzqI73Y5A9Ex2dA7XXtW38Kapk4g+yOtlcspGQ3v mipApCouubIDIKzAKfit6i+3D5zl06BKC5+/oMSR90fI/572drXx35dvozy88MbJh8nfL5OjT9y6 tufG7IpOsbuhtIaWR26UAUyCxZ5GOOwUvB2fS9q4Es/JzlrcdmqBkwl4ixHzLmdkNChDQXjCJVtg DP9+/cLV+QeiYTROca+/iv6JtjPVTSGXYAp7KA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KGFNy15frm7DKeh26HgilQgudk+s92inzv6E6/4SwA14yIblinRVK3XaIL/wyVEMSS/Nvx17YpaU YVWGfrmqIII72ql+J97vctL8UoKOHRk+u89CmFhhNIsJnQoGfxdh8DOXKgydwIo8DtyknF+rigwD Wrn0cHGnf+DzHJ1IlOw= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block IRcwaJ9nbddmu/9RW2bhH0oH/sFHVn1S2tsx6hwo1+XOm3bHWHP+ulk+4hbdqZE1Olkl9QC1qtoY ePy+TB2nSwbY99tK/zHUTTzEr9V7pe7cC+aCydi5fu9j5sMPnFmsQadzUgekG4OiSkic9/qlG8tY Nia8+0GODU2GsN9eE2823xR9kslK5c5LHAFyOnzohuZuaNQpgH9FgGbNWtWQ6Q+SNaCkDDwUMJRB XMWJMBZ7ADG8CfZuEbYaJpB3sP361wZWR2CVzTkDaWPuOvVZnunE0ob6QwvKmIm6q/myrsa7qCip ZmcNqxskerCWcqETss8HlKwYY/ryLcmRLUXsbQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15248) `protect data_block lo2tFyFjziJNXhyZZC97XYl3f0ZrW0Q7WwUD9LVmJ9QBi2joO2dZ8TfhlWwhm39tu85pBzGhL0bU lLGx5TJC7bSGiCErXI+tXOdZbJN7BwD743jxvfTNU2raF5ycnehTY1hGqwT/pWpIC2JtRTQTyzBp jg0TCqLY1rtHmFowyZv6918XEG724JEsdzGw6PjyfRjRLZtokRZ+0zbRXq68SjqEoVWFXEf047xz U1lXxDoOT917H2vpfPYaJlAmCz0h8k1/fCal34SYbx73cHMUWFnCTybEbJmesL5gfaookMOfBxRk sWQIao+sOuGvP38D26sAUf3oTnFHhf4FeA0y0GfIpGs4c9o0m1EYVlZJolMEBOS91rz0jpo2qyO4 FotW+gt3+tARFTW3lkQliIHC7eWV+CzKIs05UnbWOX2SkiuLdqLxOSfvNuWxAtliF1fFNjG0J4e2 FfC9OGxbUUJo1RrpiOuacWpSLpdl4+QKPVWCQuyMstdh6mUS1MWuoq6F8/mRGq7yZL2pdZIpB7m1 FqTQVbrAzKa9Cqe54k3eQnNS00lwUaAnIU+CzSg7CoiosWSIBg71HYudiGoiBoBnZLEqIkt2ib0G YZPWoBJ4XLzNcluQ1Ajkwv/Xv7R2wBRSej0W3uwSBWm6fUAXxP2We4RT2a/8nGQcnRSmWtH6tvn1 toUbZDD8+Ooeq6eb0K8NO/8rJFhNJV7JNyQXElREEK63JtrgaSZcKCtnBW+wsroNhNIOskBUnQYV 0CCOIW97dIQavxtVUm8QElbLu5USzKEeLvh9GD+tbqC72nrYJbHQnB1ohbEHiElv0JwdtOtSflWL pytwBnhoxQ5UT0UDv+wUPioK6HKBPFktp1w2/8kV+msFfnPCYTZvAF2GVF73mpjIWNSQk99VZ/qf 9K6lAwSib3XEYyTtUO7OnwZNIJUwEDWugnn96iYwnYYes9kgSrOfR2iKOJcSmX2D1CE53neDgkVH xkC47PePhGeYQ+9CruOehZDBHHKc/Fx8iiqW1oWzim0a0wA8NBVV2OqueD1dwZX1CZsTEAO+2Mcf rJFOE7NbOnbN0WJ1EJ5BRuVz2S/x94hwZ8o4JmDKl5Pxa37bk/BXyfiPL6ngdHZz+s8AcqBsyTxu 25sSBxZaeLoumhdgEd1YTf2MrAQZF1LOmD7ZmxpQXxUqzDi0fCC9JKUEAusjFvHSE1xwVYpyGp4u JNI5GpLffojoQV8tfutFGd5oTy2RMT9ZAP6bmqaKWsy+rlq4PgDvJmiJxYPF+FxmKJy4Se7UTCQY 2tGopjkFaSVlGV15HPI95mnUmA4BX23/QHo7TwIzY1um4MKqhwtkxITazjhYc0NiEbzJcop6bimU 5Hd7Ad7cMRDj1a3Xo1DKie1GROb0LBMAKcfeNv2zhs1tkeLMXkNcvX+W8v63l3HmlbO7RZi15Cm/ 2BWj9XfFFMG99MOAbLXeMsJqC+dpxdTsOguJfZxshnmn34b5AcWmmOZRX9sgP8wpUknH+6V6v0GM M8HKbo+sm2eHaAl1FWozeJJQUvPa6Wc4rq7pSjwdGk5FV+syvS5mCsU1fEEac9pxRE2PbEr3vB2V DRnHV0llczoF8jgqeLDTmKG4oyKDJBnssnwbQCarP764MWnhOLRtJkEoKwN9+btcZ1VdJ1avFa94 J6sQAvRmJuUd70Mnii74Zk/EZfliu4yf5b41Xkp0j+lywStXrsAZDldoSf+yNBaEMrVsL3IBAJyL BOT1Rd4YxlmaqzqmbsQ5YRX4Ub5NyDh3sZ03W2HdiS0oJRlV45N5cK1OCkUQAY5cfVuPBGvt5GRA MlBA6ms8n2mGPaNAr3e1b7yydC71SvA2ReRI5Pd03Vz2SAqGhP/59Ge75gqaOW/G2IZoUC11UCDU 31QBFFxVvxTiuKYudkKmOFxFBtVpOVX5BR7/lN+BDExAVuiwAlh0Hu5VDxIm48y/OH9B/R5LdcxH Ekw8rrHH7EGDSZ9Fe373bH13i6PTtHSKCiscmJeqMg+iRxzvY+BYYAtvQxMeaM65oZeHO1cwWQAx ALVsCF6TftT/Rc9MlqkzPpIV2mJ55DHMAQWKWb8QkBjdcs/AB7cnCVg07jbNLP4Jy5RTGGXHwFPi MZhK6ZPQH+3FRieYtmnhUP7xTYheG0c8xaBl2Q5rzribOMk8lVx5rTzHrNPvYdjp66A593lzLTyd mzIocbG/auEuspS1QZ37zHsdA6+QMZzeVdz9hwhwNioBFtgScmQzWrGhF8ppCfURQNObhR+UQBk4 Mkpe9DtCAaggrUW4TaZ2P9ZWxLVzR7jpjApAJsYlqdHXGRaWPT0f7AbJhvzAPz9go8J4/wPMJWBA P8u7WpWVrvnCuVV5PCjsTYZ5eaTAG4JT+q9Roq18Gl60ZmctUFnPlsN2t8Iw2nY2ru895Etg/5MR Q5ic1xjhIY/r4T6qcoJurG+efqeTYn3BsbJIg3gg7va8t1gOGGJ5bTW7FEeibIl0IQPwmhiZXcaG ll+Rcykz2XZzDFCJm1kn2DSeQzDqXz+eaB4O/AG0iC8SJofVp2apAQ29vRIxo+URABT1X7EAk2YP XBZBSV6sg48AbgQSNOXltxjle3f9zd4+0jzoex3KqFIi5B6Jhz3AIemALfWqZnvhUsy3ZD+O65+L z7iRBMVTD+Pzs/xo255Mwm9jeu/MYWRlZ68lFOi3zSBcsBItIlO/PPOAzyOyIWhU6OxP/SJDjuhF mE9ensZ7JNQAbDlglmjZ5EnmdEmyMjtRpUlTxLYNlwZYtyHFPLS1XmiE4UoTB36ClKq1wMYEsT46 j6OXa7Ae6Sz1zjvBXSolixvc4Q46i3M5pJxpTFpU/6tMz7IXkQGWUF6BRt9T27SEIResbJQgKlVX K5pPzrUYjfeh9dwsNU6un5VQLsQtkGbYUdCGgwrglawDVwvo+7GCXnSpxpjPUCGKCnT2WyzBmfOW Pi4Yih/HToHDNUkNypdJEZJ78w27VFhc6XgQl266RK3GoXcRm/4sxYpLwyPaWDBzuSb7qFS7Kfac d7s+Sqss1A2KS0zvlTMBW6j5yXVsQJl7Jbjc+1MNHWfsn0q9rxLoze2HT/OXytLWmfeOtJiPRp8J IPylF2iey2lTQ0Il2bLWnN/Twl7v8RsHM5XyIJlJaqJ5nhekSeOURwG5TsyiIfDcKuc/Gzpe9xgz 5t7aiOCvjTs9UUbNZSIgXj4tdBatEeuAht4UJpVXkWheAgt5qasssjYGpMdom+S+NWms1aa4c7cU rdrz5h2spaEGbgSz61nGMAfONrXan/iojpkD2AAiB/Gb5qug/KrwLDvp6HwKlPWXrBqwHAyhTPEh +dk1VMcvLdYrbwtUyZVi7JiQbap0gpDxQtw1Ce2MOTVUzcUMu5c+XRYSTaCnwMDZVr9vQIAFIKOE jgJSLbzPtsdcy8Bu1LS7pFjY1eKlqWq1LcfhJDCyblf6cEESmsGivg4uVmK6gp8PsPDNWvUy9zM+ q2us3j7GC/daeIegUa4TzRNbtGrBG3yf3zJLs583MMAGQBbczPg9dtSfI/AlQX+5alVGtbNoXrls ER7y8p+bbYSX0Rsw+ytWm/JkeKmiNuviV+SCxQVwdx2Q8CC1he63DAx0GuGOulCUdXuVidVG+GWu EGOqTIyMBG6qTzvG9T2dhRbujJLP+bWec1FYWqjz+YEStYcm80SqY5ilecjQdxJeE7b1PmYgDxTm /iqg8EJewLrF2IeYECtFqYPf0gFAMuWifV4XiS0Abc+f6+B3tCMDwC1yfUgcekyCRIe5P4A0Sql5 /3KWdaeh3eVrZmlsOZrgibyGtY2VofAGToxxZgCP3SvOncAv259/SlswvHOHEHw17krFaMaqwCXt KaZCUgELk4LMZwxd9nJc0AHVMT8TY52JyAm6C6MtRsL45cs8fPbzN29yicUJDgELyqd5OtLx6SnI vwdBT0Vxgws/He+tfW8WXytpb6TQ1weCZBOAaQtwNfhSJcV/CrQ0LMaDsjCORTqgPHtlhrDi6Whe s8BwlZfMZK7DjdE7BpbMDXkpW7xvwxjRxqgMdNmwg95N3EvPbmV+mYCluh6wuXgbJ5rxsKJUtKvW p5aJrbnhIiCATUNOVAABcb2v/V0ZDNPEnIDNkgN9lVy4qYdEIuL9/nuDeik9+0O20VXyd+R8dQN5 a4++rqVcbFmQQfjkfaXX+kiYIlQMhsmz1edAXnOT+UNQH0oqO6GtlTyMRPucmatg8js/JS6PVW4U R8Sy0xjX0CmVYvXlvVbfhR07kQjXfznA67gEZblgvpXTRoHX7Sr7DUNE7QXg1g4jtXgjBvVsO9lQ nQTrR8HadMCgElnYWB1MUrtROAGZoTnBxfHfUHgsSDhj9Feh9Idtwbv4JImkI6DiBrpiG0LQsYwp OsqCIY63+3K69v8JsJqbjGRU34iQm/j6nP0J3YsZ5iyWetQcQ2TqQPzClr10sj5B/QgVQTyy++Hw +s5CDh6ocLBpj1KbPY7um/k56sK0aOwlgg0wSqi35Av5YM7C1+wwS5nCmnNItHXe+WslwIVX83hL 6MEJPXqYQCfS9Rg+mVvASxz/v3FDbVwVKljjkFeJ7oxg+ho3TI9+lNBhY/B7rkDeIdIFgZIU2tkw UeGXme8J3NK/c4gOPpwyfBIWcKDThmGa0d4Se8XxxBtQQYCs7oXYBucxlKVkr3k290pU26hnkyau ULF2ny043WWmhqXJWDvG90oDuOI3KJftR54o9hysqhRD5maT+w04buQrPqf/xgr/vwEAM4VYTE6Z /Q68yFUrPHd1Q9zfVU8ItZu6kvc/iJDBGxiY689Lk9EKs5MdBis+rbZgKtnHgKQbkk6P8hvQ+Hz3 QrSvi6c1abPqfQTFzOl78QvOtpAxQXG42aYe1cumjaTO+YwHHL1/OcrmNug2WDB22+B5yYspHMMr pghggC5YE14ZK6SLRRyznvi6/0j6JhUfVvgPAp/DWQkh0XCEcgptvAjjhDXqI/DV5vcxdpZui3xq DgaHNZnLlN+AiSwhiUvdqdcAgAgbqWcppIqvXreYG/5DLtlu2KYqyFHwzd1jufRuB79FslLk+8kc pE2+4rpbb5I7+T2BfGWB49MciXCEEmlXlHRbI1aj8FMCawqNYI+SaTxAW2Lpb44opWQqc6rMs2MB RtxcdjCq6WcCe/a67b2uEW+Bn9IgNF9c5/Xd5KsX/yzm+GRQv4s5TRgvGOd1PmDS5CXpmgPbNMh1 7maofr4z/xm46/gy1FX+/cZzX4z8B4HWNSq8ao+MokF+twMaXFVVOoh19LMZeHpeAy+yaNOMUlB4 ZHByjXkYxiPQUoEEi8ZxUkWNQEXBxfS6JnfMTM6PitDDiUaH4v5mG+cgP/GyMwlwSbCVuYtd+ZLj Z1Vo8jk1TbUy4YwVZN6YZ7k8H5+bnhOdSlYm5VsvX4R0RPPfDElc+ULn1p8VVbAP22fDB7vjpg+r Fw+xC6TL7NY/It4Pt/lGmgYLhdOBItWGqWEw9w5BtgvKWICb7oKpkt0OYoL8RpgVrDKL4TZFPHEx TF+QEEAWi/qBHtpFefgmlcpp0cOMv/1SyDx/YosFuPM2nmj/S1kIQ0nIphjSxRlgDnTVx8V34pk8 BfzcQQWpAKoKcp1Sq3ls5m3tm309Er2uvSnwkiR3Py6zHkT3w0Hi9++VsmPe0btjY/REO7oyFVg6 R95dXw3Yho+iq+RM9mchg4BHOre9/KJbc65qPF47mKBnO+PvAmU+hl5lsEamo1BPencnba/P8o0z SbZN1wcIzlnbS1+XYPPlZO+lCOWnVCXwBiMxPiNzAUKHUY/ch6KpYGM4y8DzbzeWJKbQqJUx6bGw Htq8GEioSyFGOgSLfAgprrgSfvBbNnr3o+2XEN9i06V4HOGGP51M0BuhOZxsXM7LC17T2bno2lxx g3MNBexWh1Il+f7p32f0p4zchekCfXuxi9ewbdnsdhoTZWGMx1SR50pKRuetNKn4lG/wCYuBtMvh eN5mHMzz9sNs6mExAUsCDuuZTKFm5ozosPvCWIhsviNFQ4fJnmOAIQCyuybW9MU5ua9T08mNXEEJ 6lGpuV7d6XTL6AEyHe7ZfR+GlGyHtWFmnmuNh8HgVvtx++CDnqP1/WhsvQ8bDSZuW3NviXmCzWw4 Gt2pKlFzptQIC6Zfl3RnuK2c94Manvfx8P/8eYsrotrR06wP5TPCdnELK/6Umb/fbqzERjSedVtH C/XNkMeW/0AbeuNKu30powhGQj5XDKwjoJRQNXdKllJRgkWHMdkyLwAMMh5XSq75MVUJ1jGvRFpV kPtMik/7OSZ9aV9QgtERkL4tQVIKznYjD6cNl74hKrilOaPTxC3MnGUwgWgaMnkDyTGPbgI7IoQb SmbhzcikqOd6IUbBprZvw6ayE0OvckZjRoOfficSz7j67b0DUGKTTV1nbVEp4Ob/tBPY6NJsjJKb z4sTlAm4ozcDYfpnhcmgAHuXvHiFFBkMBNZ3rjYT2cEriQ9TFLF3mizXSvt6Y9lGNjnsELiSVkPZ RFto74jJku8Hss6xrKO49xXr32YVTl7TgSZBYBEReZSDER0F/9Smcx6PxcaJbEbHcoIgaCinTWDr xbClLt//kAW0biTwE+PgAgoIYlf7HXMO0iCrf0mD/NlAKxr1hLVveiz6c4/fddjlT+7789I5+4wX uP1L854G79hcQIDuJUlxMBN20YgfOFUJtzkDPbG4Y93b46Rzs6fZn3Zp53ui5gkJRnKQIx6wllzZ KGRD0se9BG6W4fHDS85OKRa84HvXcWNex6fUE86DO4fF3z/VLNoalpz8xfHzl/1BbFMTWoxvBuex Ewmn6Z7qXBrsz6rp605BFeNwjhcEl5rbKnvtx38car/MBj+kpci2RmvwtfYvrnFnmonQVEhlqqtb izVSQZTvDvDylxyI6KejyO+ad+O7KhFt1ObvtioLPhjtD8o4wAKHpqAR2Hu4XrAlkqR3GgQi33AY efXDINfwKWhvU4CTCyYdxJoAZuCZJp3VYpqygSeZPSM5WeY2E5wcbvPG7jTqIlnJ7NPBPkYnpns9 giuPumUmUOOcVFAh+1CMZW/i314PWY6dqh3jiFAUTMd2pAQlhzp0COASBkI8yHscCuL9e76LrNEl phK0zem4ZXVqvQfeVpDjlV1sqjkZH1bX/jm/plr8dpen5FxOm090bHN1BTwSx3G/mdGH75jaC27s ceIOGoUwoN/jYig7YwIJchD8FpwjGlocKJDBXKwQcEkAFDczNefFi4ziWDNI3YZTq5+thfPxOEFj TGGLOA97s/C58H/TQ02vedrKqR+cTEiVINTohDV+noR/pHiUWOgPDa/QVi9UZh1pv/uISiZ1dRQu Nq2qa1skuihcQK01oxJjvzePeXBQZ2qTzuUpfd5EN2ZyRny5dHBXJVMGeIYHDtTdh8pGBwDlAxYl 0G1e3k6mxqAjAIbYKg/fX/tnFMNY8haPyljcp4x2gBI4a0AZa6JtZpg9UfSlBe+Kl6KF9L3xTYMg ova0I+v2YhQPCmumDF1d+iDw3Fqkk8UoOkhh8DPP3LKU2pZJTLBSe2V02otyUo/C24nSt6n7MfV9 tTTVIzTvDeaMXwCb9GZxY/SeIJPOdaKmsmD1fMSCCsnr9aNmX0Y5pNUJDyTIuNBZAqVg1e4N4/bg wI/4dmn2Je6ixx8VUYRktKUsL6H5wc8cK16cWLMq7/XpfvPWADFWRlKdxzO4cRhSiYOka0YTRX7M d+cF5YXSMaXGd2imY96irnT526iu2uUVhoEnfCtxxvPuRf4jP6dwQ/W3Dwl5mjf6YgVw9LEvQdGD OtNhvBnzj9oO5OmZNsPpZlnZAu+wCFCaZnEsoT/8zttWrCWQYVLlmCMDGZqkIyYOmKZWq/gccVvR A5doD934rvPOkUR52VfkpIap29Zb34WqexqRn/0IC/DsFN7H73s2bLdm5k4vIdOSUJPrVoOMlunH fEgOAXDejR1OA0srkMW6DirEbc6T+3BH4lBAh1VqdqsQEAaOJZg2uHj7x06rVH+ZKKlimvQKRYKN vvaH3/maL+3obAIoMsvRXtzFP3BVjPVSDWlrQngRtmjDMASn4pDgQPic9xmdGeLucC8wW/D7bQqG 3vFNQaWdOwNAEAJg1Fxdrw4+FoSZ1+tJuaem1QXlLZp2MWnmc2naNfy0+frSvhWZLnd5HTZdmjZ8 jmmFY+wYNqnivDXnBgXQt+lTaZxmbiTsBDYd1LxnrPzBdWSLsYIHwSc4qknEunO5DFFeU7J/gRBD oLvMA11R0nbZW8FqjRQegzJTfXB3hCElqcU63wMkM3BDPrFqSn9jMY8AtqyTZmtrXoXB/JgzhAlu RWpCGYM/yQU+VaODjSS6ahedrwnZfEucVY3S9uIJOiCZKDxQP6gvtJwHr+r9mj8muQoOva/k7shP kDDFoYx7yIzd/PX18UAnuQw0swQiWnFq3Ysamrz3cEb3w7KCWCE0miZadUqagWh4Ui1EoA4BtTCm XH+ULndTI8KXBTQtdiSaIelm8c4+Hsg0C9LoAmezce4IxO4XYdeG5mTOuyhdvbaf5aZPhYiHfCiI 5byWtx4XeofT5LYNa+4oJv6J/fs5re14ShP++4ZKMOnGmUcB0xqymmMzKZeFzu5qZK9C+EJniLlZ 8X3ypMzEUK9VjeCEvjNhAi3kE6NAMjguWHtVAoxGk0FI/+e6I/x0exhvmD6+PsENXHhXNgiGv006 kLSDnkx+6CJgztcEI4r3sXw3dTeiaYYzJhTJUw/z+GZmodZpeCbVrsAMv6bW62Ock5wdtXqJagLV VSPRSxklebpditAz2peVOrKx6ekkD3hlFH10CWt7N0b6mlRFpGzRIbArJnIkhZImFhfLHYxrdG+u Q5QWVQ/qK1qjjWUkpMLZn8KZpRWY6Iv6/OD7Ms/rIAfGwrG0WQEh2CoA5kH+kVtf/KjD0kUznGzs uiq3DYtmVnkzXkjgSTWONZIQMe4uUy1cDbwde97AS+8lFfBBUOrzGikwN3CnatU4RSReVfMfsmj/ PiUvI+VVIfB7fLmIYirpkTyJlLbNqgCbxTC3/YUKvQeKsgdPYRZ1AQ+X2EECrxumRyYdjdzdM266 q/ngQdXkaptEq+pWick9hXGMZv4EXwb/JiIrIW7ZzIyeRw/iWU9yREE99wH8dhvG7F8ZuJYODoZq Z16s7UDgdwZUz1WAASUCVAfQ3Dz4Ys/qpMTTBwP5weg2M2dpSnI7P61q/kp34JaDu+mDwNRk0OwM S3MjEJmn7M9bosNMEbdM33rNvuBPGrGvt+N2snTNy1pQCQVZhjxY2RTzluBYwLnmqOulukiROf2T lArRBTBcutYaPwNKiLDgtbC263UZD7nXmBMnFbxEdHQ1ciWmpHo0nZ8vvOpG870/W9B0bIU00Zf/ mcQGtsdoYUq4AKCGeYuT86AIsnm9QubUYTdvBvU3355svrEH+FrAn85xkA6Qj+KEgjcTOsEO2c5v a8QvtrsHm7QlyZz4nmX0z+c2xrfYF4NYwB1W5swgvEVPbo4m3MZ2Px6uQ4tZ7Jr+wdowt/fLBqCX uejBBNkZayRvIeXXegOy82MWj9Sj5U8GmR2j4Ufp5Tz5cl09egSavAg314dcMTUbqJ6jko/G/s0z hal9n1np6/6hYCO88KZOCHYsK3yBMSXLeTryLK5iIwAmSKbm9hltXEyqJiU/Ykw2gjkbjNYFYZyK OHlDaFUUF8Dhk5sLXXK0BwJjB+7JpKt9g99BATyq2YOzoXh8tzq/r3PIhNKefbBMhJPdvtA7oWKl 9BfWupKNcvAuMYMENnX6MVjyiMEoFSq8Q2c0/0cv5SidXn6pvp27hiMYAviHq0/ii9bYOBmwWQID rFWstI+te9vAVdgtKckvIK+bTRd+gYyq9379EVHT83riumNh79bKQg0kgGASNv1Uw7qIDGI8AYe4 3Cr2lbdTaIBcgw2Tvs6tCkZTOj4tbt90jk+jhkBt/kfzyHkFq/hU1/tPwEg+ei1zO65wpOl2J/Hj zqdIelYk+Q2gMDD4UO7B4QJrq2maRaOh3NAPNsNttqNh9PtnRIZSIhmd5DeNgbe4Q8JUB1BBA/Db JsHJ28cwqoLKRQSTa9PtlDgLzK/NKIuy41SAJ1FSZmQK+bUhGdPEwKMPlvNOF86H3w3FB91qra5r t13g66yCkK2nICykaW0+ctvVWO3DnQt5dQNlWp3TtwC+UU5R3WJ4y/KFK7Tc+hyB5J1440FQbJoA mpuZepfQ443UsJjyxTanoZhHKOD7Yvpu9CUn6Zp2ktivQoqNB5T+rqM1EgThdTTt98MM8DcwEg1L cszhN8IqINLpY4sFYtBhA2qTuoeWkr5RoLqT1hNi7H2xnoLA/L0wQHLjIKKqmRGyBX70bMIj9bsY ch3AzRyhbdYrUqvruR4h/V1egVCDHLMUhpxyGacBypyCswL6q5ji2LFtQ7nVCqHSOqJc5Npym9fM /UrTlm/16RpH/DuxDBck+pbAmHknMlME1lvMkvsxo8vMkwGvPuIKZr7n+S8Om+Vv9ne6FuIdbzgk iY/KzqzQBx92OXH0B5uSdtUeXsIalMo9BN3mNG9UXV5y5BJ3MOvtnBPeTkI/N08QG6YKJzUS/iWl 4W/9JSe6d9oYzuciEUrxzlxX3HUS160cyAQ+ODwTRnDtLi1U4hRgGFgIOg8BwEs2ilLtuXDxORKl bDSwNX4I/PW/qhR06nNwbRjyVfIi4VEn0ULSFm8XIPzEJ/t+xQsSK8cRx3XShqsDrberE4kcF6tg TsuJ8lO5r8rDwKCZOzPkOktohxlDzfICQphnJ5xRK6sehksPxetSeYsrGBplI0VPdhJLFAsnUFJd Ev6OqHdkRzMJ8+CdkuLN/snC4oRaUvANsK0doQmZ9+c2NoNuhNcVod8kKpw/3twWUJdfa0QIGJyX qzI+dQhuU3lWQBhEcJhG2DzZaUbDxrbX3YCGd+k1wavEf7VqLSwaTmmEwdZ7jtRmuK6HJ0rRISjP f4bD6ffOZjQ6jYL8ORBWeiI18SoNK6YO5RYGBfBdFqyxzJNmYSlofk85khFYSEtHVqecaPnuaHdV A6gZQC8sgAX1dfe/II0uTSstSA85bk+rpeDP4VHMB0X1lMFwrpVV9b7Y1Di/T0f7rQn2P/PPC8vQ 4JLGXzybsadQGJ3W0zxfq6PJLdRyCfJyHIttZEiARP7nqBDcTIyFCg+PvJcQZ768hNO8jAeI5jbd msSsFZC4D3N1YQDVZwj/7vmIilJ+i9qJnvUTwUBySXbq4FY1JyZSGjV2GWZ29ruIU3MwbAdW8m1S 8XTvHsbcxiaPOc/0ek7gt+0+b74qNTeX6VWf7fYDz0SZaKntTeuiDevjmzuF77fbaITL/5ISEq+I BtyvYS29P3b9B8LA9WC1N7tSTt6E0OIJxmwZlujkOJES9mM6Z+91WHY59qFKpa2siTL4jl/unDC3 uOuUsFOdpOp6OgWVfA4U88/JJrs3XraZDrp7DLnvDxEiss4+J8j9p0bw9hfz/ZPt9o/6Uv8h+z0P 0FRGjl6c7lSreB79+W0JPk5s5gfUN6tTwD98zYuEjyv0TIOWxsgQQOUE3DPnCEkTyCCwTqLktu3p ZbAGkWSivgpDi8580gURDEmQKDXhnks2yBDsXxiZx+N+UqfI8u1RYwL7sKZVDsjL+5mS9igixKJu mi6g1L08K6EDnZY73csqvUrwEVmlRdOTzVloSY+YdTJFeGdmKYyB1As6DDkFKmSB+eztHKVE6V7J bnAUyg8DRbGxU4KXgrC4UiJRgUaSYSVe8KHSshXafQ7DPFMKCB/GechX2JL7p8dmDbJWRYbq3c3D VMhRwP3vts5oXVTfCoNn4Ep3xMja6QsusMNZi1papKFd3yVv1l4skzpTWAg6o9EWYEnqzjznoUT1 HrfRKo7S2KqkgK1g14Ipvf5gs4HrxpzJEgZuUK8pGZH8jbP71j6nuOlCB0Hpr3ERm4DrKn3/DIFV mT8lJzUbiW+KEHjV0PjT9SLWH25lIbLWQIRxB9dSjAmOM9k0j1SHqlfPU5PX9UQi41XcoqWF1/bf HnAiHpCNxFAyWodIw9PzqVGZ03ei4Us0GAC4j0PZBcaZ0jZTD4SYgR1WAaom04ad5An2SupDMqD6 i/zj1uMkN1ftCXWyyAYzEknvYDhlGSGqD+pgEx8jyNJwbLN6dijDF8o4EwiSgu4rs3zkTetGVXbL ZZiW6gvzetc8r8CVSkDS990IslEBE7FEog6tPOs9nAysN4zANCHAB/syxXsIqyaqDLxj08oCHAN9 Ea0E1TcxVd4p5aMrsZtaPXUny0WsQcZmrVua+pUORYcdpMtEpDhvNun7+d7Yexd7yMiL1GUXbGBn 55J7dkquCalG/Xmy9e4QOaxqOqW+fLjL9VWuDLKU9I4iXyc7CFC1H+GtUT/gMBymfmMxz/Q98/Yn inr8+5CbwWjD7si0setE2IM+NeUnQa/gtS4vfFkIdPi00vXllAM6pSC6/0QeBaWa3+r1czPVFObj PWH7rYqR1ooR25vC9ZbZT403w7uhulpM0H08ajEmWIAkOGsH5pQS088ug2MLhd/hO26L4IydGeo6 3NJdiNd2TsdbmuJoUSGGh8mJf7yFL20HUgmUQDeoEGFqgtWO9hcieiUbBjhXP6almms3b+QF7EB+ V36WocNhOtAOiQMUjP7amBx6BWL80y7ZG0C5mf8ceE1zlOP6JSqIKZ2W2ctmKMKCzQDQGvCAR697 3oxFl7KClk72SSKOq15uzytrapXDRz5aKpyyrxpphsZ65VzcLdqV6Dojj5fnaE4u7A9xRt46mmNI R3KCXahZ0diUKnV5O3bZX7GFF5iaaJHwiBCwxadX6E52fTHqJ9yr291p4tG0pUlhCni+Y4O37EEq fwWvrSrkv3NqI+z2V3Ifl7Zh1oY3E5v+/mO05jsJmthiTfptmfo4jfUKFl5vHlQUIKwDvAGQUvAg syriuscwJEXegC6+8l5wdH8flHjlXHsQa8+uBEqX7KqZ9C6wQSIvc4OmKI7Vz6KBtqEuFqTb5dHq /as5/RH/jGlNFwZjxlQZuD71nrhq4+Oz/jZbm1LpWZ5NXkc1Om9bx18JGA+1sYR1xe5R1zs/eay9 yQETW4yLT5sKie3PwxLcmjPq5ttZ540kwE4y/K8ZEX0dCsJvwBDTPvftVJVws32pLrhd6lavVuIV c5F/9O9wt3B4X1NWTlchrQwc9yKzvp5L5o1kr6Lg5IQe1eBkFQZX66eSgK5cWPkdqyq4yMniZEZ8 oYrcPivSsc4lOI7GEYsE8wLnE9clMOPlm9nriJxTDZ2i7/HmnL1Q0IiPMmg9kdgtz3VlAuMQN9RN R1iS9ykHnegJPyKBWmIO/K/BrHJen7afnI62YQbUp0Fr6IcNROoqq0bsYmSBruT3W75JIG0Cc174 /PyIiLpmjWhJ7sl+686Ml3/vhYFFD5jlDOQ8DLKpSmaMscH50ZsQihpoKJhP1JNtd9JrOd4SdQ+I px6bNnblous1n5h522nqwM6XosLtL/G87CJ/bOSeIdbixbyZHxJXOIxNuLdRQPb4QrqiDHXMQeah eWPEMuQpf6dnYjM1KnkKjxh/CxJtCRmkUjJe8WqDLzpdI6l/+L0JhoDyQuH/9S+V3bgmBC1C/tRk n6xVuQr19CtS+Xg8oQP9zBFToFMk0fN88FqXnqAkJ8BOu18iSPMpTTNWAs6kNUw84Po/gZ+fcy4X wB8bdIiQEAAztvib1K/zwMw+cMVzX195FEMZAJ617/s7L5wRqluMeECknM0HC9AsZb08tQ7q0FBH vl61Hyap/2Vjte/O/g8RlkXO6FICuys6T+qFHYHwrNzhUtaMXqkdGddnHVh/E343B0WBE9GXpeR7 lGji7OfIToIlLxunpXzjw57MBUgjLBCzZPsPSJSa4io30B0kMP+PCx+qFp//LncbGBwtgPWkAgHL IsQhLL/xfkZh/36LEGgpPNlnS4ETUoifcxEVusUOVrwv3/tleOCN1JMljt99t2sXt4GRoGCvQZaO NrVh3sd2KrXhII0gfcLdpbryzJwaZ80HMG8KCqLC3Ga0yT/FPdDa/eOJJ8KL7fQtaDwXSCL9cOhM Pe7qiIINL27Mim7MzaFHp5qUtpYlVv/Ex8bJ9zNFYLn0uO7H2Sn5JOuwuqmGkR2SNCz6Fupox8/z D8LVeAe26qFrZOsLD59zLdgbLl3asB1h8osvKcLkvCQCSXQjhQntaj3PjjbVBNWrOLztNATp3Env v0FW90WhtZiU9R0xHi1sqsHDYZ35slEh9gKRRyw9tKM9OLvY0Wg4XNA+mhDsls1SiQbQOqC9i+3X IxgawQKwDnEkrbn+DXTaV2CTV8ak6V9WIDsfw8rqGcrGaII+sQhmbbfZAvM1+uWubre3kQlezwuK PoVfogigSpV0tNW6S2/LnMr7OOLeHvpFV2ikQWTbx9oirYNSEPJbWoomWNdL8HgkwDoHyknAsPxN j+YV8KYlzrLNeOQqfh/dZ1RhZbz0DJMx6mPpZSv3wxe/cnCuLOq/t625aVMNRyuqV4nkGpV3bEKb Sq5w/UAdn289Ylqbk9amvEHPGi3JViwXmlml23kzleLaClulOSgtec660aGPQ+NkmvpfRKoQfS/Z jVqqGAIy+pKJbg1ijmXawOzL2MWbm9g1Cc0wUsDxw1SYbxQ8ZR7HaqEyPcCy+fJi512Ts0OLt5qe hnkaR6rzQ610uluGwmmaqnNe/JpmSETIqGhAZYlkGJgYqLau80r9i3vhe8k0QMKSaOnaLsiieYHs bR1H0Go+tU/Um5zKqEtjIUYxEFeFmLiPdU6qFVy1VqDviqJnMgToA/u4jaqI4/WkPz7i5Jwg5/M4 x8MIXD+CMxg4sM/KbEfro9Xcc9ysF5OStAOT3zn3Gs7dZkLSuboaLGS+QWJrsVH7jmxlxyQddLE1 ZuFeh6ItwlGKXuitv5MkMxWnZEOLwNPIHF9CfqES3PX8Mu4nHsdRb+xeNrbTC9mYEMvxQgMLtR8D UjQlZm9qIBKCdU1Qx+ssRmtB7hB6HpTDFkCXj7fw5EhPX/TWHxqRYe6TMnj2HlBZVK2FNWIwmoD1 z2kUSyWa2h/aKvRs9G+nWyPmT0j3dRuZqMkZBAsJuJp0iGYVKPICWos7uo4TYNqm0rrcN3UAhljZ WGlcu1o5LpU/rnRV0wzS2X+YMTxz0Giaz9gpJ/sqOdgBiuFYXJDckfQnKeOdLesW5Hhil6CCc1Uh PZ+acLCcStjGwBl9sxyAdpiJZGhoSZ0LyUTT+x2sWKi14HJ8c0pIAMvwq60AEthGSTnAXDu8y2+t 7WyNiUepk3gURbhqidaE/Pu3frJMq5BwZaFbR70Mj20NE7pA5Sg+BxQsaysUV/Grmfc6iap/u07k hQ0d58AwvkMOCUCRuVpGUzfEY7jAUB8logHqIYRt/Gg3y0TCL2GKpRYcBw/cXruXF4PsqphMbz9S EetAjixDXFHFuIwiRAeTjSQu70P6HOMpsfpe08dQVthvCCy+PudKH59SdelBTsNBPVcmyIumGsLb p3Tr6N9UjYyY90j4y+cAMp+4RmTgEegTSMeUbpbVeNYUI7Wu0H7RcjrVDrWSxtY6UPQ/Dx1hn8qj 5fAdd5SBIUcGlrHxWNN9a32r3ZZZEOsNVfCCYmVv+iAMDe0oNAodyu7w/q/qcwppLWxXUAMEhqSv vt75VzFD6UTBN6Gpl0xlB6ofPSHMtOTyMry+w3kvzLxLczALwH5vuuQScuo7eMKgVJ97jh/NbD5r 5mWWFGiiYGToHBdP0Yp76oOepOPjDn97NxkHvVoXYZY09wHSD67M7DoZ6mFay9tgR1MjVJ/07MrJ Gqfz5hsG/96fNz6NVX1sGtS4n/YCo+e5vOdb2lL9yfknjD5VeFRXw74rt2rZRVT4OGEKPY+z//f5 MErU7acWK7pqGvN10o4KvM2y7GPDIOdszj3V+5zGxaRsbenLDNz/YtPWlkVihCzomhhBXLtGRH5Z JIHrEch2Qq+V+cI65CSviLaYXN7wqiicv7a5JPIQbol/4EPgN4OFCYQx7GwDmjp8rX8jBjtws6fe y12wpztmaykpcO2/b5mJ+bm9tNHw+Z/vekRgHoQEBAAIaCdQWjCjxstRIm4LHDbTKa3gsUGCoSg2 Tbw/UUgoj+fFcKvzt4bjxU+RWbQ+f78UGB7OUEDSVYLkqHAfolUvw5rpm6Bw8FF2HsrtR378Iv0h J2pm/4MwDHnAxQVkpg/MDCQI5JVCaO8px+xlGOMtGC7/BMrIxTjYRqo9LpFGIlOwScNgfpBrvjAF 3yqFFXduKrWYOOTsTHz7o8jBXyo5MP9YEw0IiUsmX0Ykj+sSswtoOk3arr11bzp/SNylQ75n2S+t mSAvjUlBJW7JuAwA218g14d1KrExYh1l9OEOgcmp95E2XKHXZhmRgr+2+EYAvsMiLWwm8kIl41lt CGDTL5/3CqDKnHHzc9p858NOue+6MTuwSopBPSkq9Ita1y9kgJxrnJgafEl9BX3l4sBZFafEBDWh epXRZ0iTEE8b4dzZ2WnR+yF7sV56SvH/HVsJxHUGj+zvukJmGva8H5aEy8l4jveswxKcSi43vpPl rwLz6soAsP3MixinEYYI8v1A8JGWpttM+VzOMr+zkvLlCyk40XcWFzFjoKrW2dUgB0CaP+aq43jS yWTW75ZxP50PQBEVXeHGy78vMDCIZLPimV143fxuqyrO5X8utlxdTB8FDRds6fGAyxDcMyheh1tN jbaF6wMhWnEYH2zSkI3bG6VsUgLxEb8Vs4jXmF4C+cuuflN7r//s+jYo06cDgpOgqM53SmH9MIlw AYOYD3WJ13Nwr5+6Hb/ZyRksdUe9B1A6Aru73cRGAS0GDocaLdJVVtnqpqoq9jPi2ZzvlUDVJL2s BPS9o7k+dVVldul/SsgANNDzUm0Y8A/EuepyJEYnPZskvkY2kabzB0PR4OGwgpnmAkeXMX+YWAzj lJqDmsv2U5SyB8lx6NOOUKLTUiF0lgGRK7mg4YATGiLsCGuxeomuFVjC3oZzPFpx2ZTKeVNMyE/J VsfU4zQPsCpOYUrbxffaRilHAB6mm9kBpplbasLi68vkkXj+U7cyx2GRBT78H1iH5erJ4L6Io6sV FdjdPw9oOsGREAwYnhl49HB+rAKU3Ja0rLFRz0b+TiF6JjVQHosDcAIJ0BInTbxunV5DazDH+J9P QzmyGbzIyqpd0SFjlJzlvQ26OO1NW+W5q1yWN1bgXOivwqYXWGdLRqrze3QyjcT593wqN/Lf5FoU nS1xpsXAzeKlwCW5Tc38ArA7SsYn3BTRFc8Oyb/Wzm9tLCo/wJHDyn9DMTf/kn3TxBfQ7BSDfqmM Jg8x8ZVbJ8gTC6Wy7oabBzL34r2tznrdsgm4PNgTlJEajPkkdhzhecxD4aGpRo0qRQRrfTud7Mze V49P8U9kC8zzF3mSFQEN45MghlyzJS/w6oMZhzdtvH0MMkLmm6J55jQrjD/MmOpoMG6m6o9S7bgZ zLGok/elhTN0YwpezWoJ8s4XKgvpp9z5s5CH1AH+4M/La2tWKpGjn+6fgaIqQfVLqSetEMayZL5W g4x8+tLc/wKBoX2LVdScspDi89PBIxPHEj8XVVjnpwFQ2ORwc54wYlRYvMlhnNfMk6QmKZyDsb04 cLNCOgE8cCEU/NXXrmFoCj5BV59wYehYjW5rJb7dY6cNdG27z7m/gsKakAy+MsZkBcxY20ta8ujf 5PoJG6Ih28Zezexk4VfWoybDX6/Hi8k9kUVOHNFNhoqsHvv5kna0B70fctkMW/PEGsemkKX7VlQu ZP9243QAJSAesf1tiZIqUpwx3627F+HhAPGipKuBelFtdRXNcESyUBoZrPuF9C4QLjmUOise0g8k QLSwOKKDl+3LuhacLJUhLjLZhcm0WSe9BFx8iM0WxsRxEo39N/BAtAvdYt208h3w8AerunI+sCR1 ByJ+GV+eG3UCZjgcR+9/VozqwcBCZG72hPRCrf7pQxVwpqrTtHc36XVh4/xmtcceVhtsMPcVx/F+ PK0x06AeV7lK5kCUl2nfMSo/mr/+auY4FjNIRCa8yRfQPWTsOCdVC3cg0fLoAe/Fv3L5Vg+RImnQ YbEw8V8C4mXdZGpMbDS96EKSshF8yfCtsnxpuNmDR10S0VtePcn0zDrmum7uQH6TN4e7ficj01wU 8jL/vhOsGloFgPeJ2T2beG/LK3fXd4XIHAX88udns2ReMK7JONlH/4qwXxl5FKrMwzQy3bLwGgq4 m2ZUcUClHuAuMBFzCa2PCNCohOzTomBJVd+uFTPzW4ibW8rK3EhVDAgBFw6sJLTCYSYHO86d83zj souvG7MPaMSsGShxZ5FyQXGBmVfPD2CqZALYHqNqZENf07cH5sfE4L8L4+7O6sUcrb+Npb0LsWkE aewWKCLi4QElc+zRvASHrXDYv2bvzMc8lOk9fnThaqdFxjTMTiVr8BugLRnBSECgWUIsGwdnKF5R ADrDY8/8FFuiFvsw4liqb6FQdHROoUfVX6gVQmJNANCZcGttmn61FtAiAHWT6smZeC0RepcxyubY RJzldA8EUPuHQweNwtPqEFCUbLTvZMzmSs+ToHvnOy7U99iJogm130ZiiGLzEgKKPeSruhv4xHVV pK9SoEaXneexYJPF/Dxr5QGXK51vpobQeN+aSTEs3aEmnZbAwMtNfTP6bbibpJA/ZtL81rJCv6da A7rQ+/OsOA0VMvGCc3gpDWJDfoEs6fhivba+/06Z8SCaQIXCdS0Q1RiVcHw+UA5aLwMCJ0yFNb84 prxwUw7Hx/3YTuO/rlVxEYjAuz8WSCLSndjntzgGDfu0FJDvl03VUlx05elYViplu0Dzx0wQ+ffT BKDasDJlMt3ap8NZ5dsHGwXAc6MUM8btAYaoCOssIo96rOawxBHVnr+rqcBC3GVnnYJaPQqcVvY5 hsagQGLmqUma8Z048eCjiCPKdVPPZon6SfgMTOapvXaVP5eFRaWok8YDZIeQCPcJ7vNX6ib5cRXA oueUZzdXkljsGnm9SjTKFjoJf935JUt9vBvdzpCjZeSdMkUfvpAtHAiovo0K3mKb3ouOV7xYcRzR gBrQEqrC5PZjKcT44mSG6oDZNABCJ0JbEgvXJV2d4SzdMOdCoKLV53TArZCM1mY1fm4UtE4glFLa jtau4K5M7dwFZMiR9aePZPUUcEcxcbQL8mAwNrI4qklp1utJUh5BMatlsPLWFoURCxMmMpe8spNZ xdCtMpFccKC0dTz0eawQZyLIbM9SYj+Y+dMXrNhYndaw8SFOgZedp/W1EiIxHfnFhNip06mSqx+l Or8npo/OuOPJnY23NCx42e0aSQy3JEET6QmwDKo2PF7CadsQ4oUd5BWCRG7CK7gMMskUHIiIPYnO rtws9MrlEHxdAas4XjbT1WMwxJemYUqcl2ZjyzBmrm5cDPyeCiFNHeSrzQRulRomXnYoUf3XfcIY zBrmmGowEKsmSkuAwLy6PVsZN68uYw7TUP9Zh8Zl6t8o17YDwBLjN8jJNNTcYGvaR58E05M7PJrK 9rXQJzJZYmdKTc7cxuhL8HF7wtxFkyYqPKwD90tGfD26CViakChuKY59zAUPciUW8j3EMXo4cMEi xHWFFgXrw7EgzwSE7pQLFyk1njycQ688CuARfqwMwbsS4HG3Me6sIRAtHjZ1PVhoNcP6LMWIrU6t GffBsYylgoPbTfe8O6tTYu6oTo7RvdiW0tViu1XkihwTKJjtCgHDeVSgeVdbNPUafJMXiDmKT5YC 4c+Ih7u18V6qBar3pRkseN+F6//AYskUxAeYpUuwh9ifxbXfk1Rs/vcte3mc6TX+9ZfD/hbZivwJ cgySx0mpnPLaEWkAjLwCW2mehGmOZVJxucW2pgg5nBojO+m2/+WAG++EQ26eoLuZLqEMsSoboe4e hyztGjnTu5vHVtOHT0YMFXx8lHrOz21k1kWG/sSlnju0eaKFKZjWPoELxhfi/dq00xdvdhuGR1jY uJ1P2Gh+CCgRXy044opH95iRsHfO+dIscQoQ/mCA7SczM5lAtfjuEeXXVSQ/XsgK1n9aeBtOHbso 99R2WajBIGUeMypniu3VKUOfQjuPCapEaksz6Fq9148tokw1YE+HHP9/mi+W+J33QNNol19fG0vQ Cq8G5oVVxfFqMozcuwvKLeLCTYrwptE+WBeZgoSY2pWLjLbw0EXyTXhm7TA70LXNo09EV41UpjNt Jts6yCKP3q9XgSeafukZYENWE4aP/35k0cP7ALY= `protect end_protected
-- This file is part of easyFPGA. -- Copyright 2013-2015 os-cillation GmbH -- -- easyFPGA is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- easyFPGA is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- -- F R A M E C O N T R O L L E R (frame_ctrl.vhd) ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.interfaces.all; use work.constants.all; ------------------------------------------------------------------------------- -- Entity ------------------------------------------------------------------------------- entity frame_ctrl is port ( clk : in std_logic; rst : in std_logic; d : in frame_ctrl_in_type; q : out frame_ctrl_out_type; wbi : in wbm_in_type; wbo : out wbm_out_type ); end frame_ctrl; architecture two_proc of frame_ctrl is type state_type is ( idle, -- initial/reset state opcode_check, -- check opcode, store frame id and check parity -- parity check fails or opcode unknown nack0, -- initiate transmission of NACK nack1, -- wait until transmission done -- acknowledge ack0, -- initiate transmission of an ACK frame ack1, -- wait until transmission done -- MCU_SEL mcu_select0, -- send reply mcu_select1, -- wait until transmitted mcu_select2, -- assert mcu select flag (enable_ctrl) -- DETECT detect0, -- send reply detect1, -- wait until transmitted -- REGISTER_WR wr_init, -- send register write command and wait until acknowledged wr_finish, -- finally clear receive buffer -- For both MWR and AWR multi_init, -- store total length, store full register address -- REGISTER_MWR (writing multiple values in a row into one register) mwr_process, -- 1st wishbone cycle step, central state mwr_write1, -- 2nd wishbone cycle step, write data mwr_write2, -- 3rd wishbone cycle step, de-assert control signals and return to reg_mwr_init mwr_flush, -- flush rx buffer mwr_wait, -- wait until receive buffer has further data -- REGISTER_AWR (auto-address increment, writing multiple values in multiple adjacent registers) awr_process, -- 1st wishbone cycle step, central state awr_write1, -- 2nd wishbone cycle step, write data awr_write2, -- 3rd wishbone cycle step, de-assert control signals and return to reg_mwr_init awr_flush, -- flush rx buffer awr_wait, -- wait until receive buffer has further data -- REGISTER_RD rd_init, rd_buffer, rdre_init, rdre_finish, -- REGISTER_MRD (multi-read: read a single register multiple times) mrd_init1, -- send opcode and id, store address and length mrd_init2, -- wait until tx buffer is done with opcode and id, clear rx buffer mrd_process, -- 1st wishbone cycle step, central state mrd_read1, -- 2nd wishbone read cycle step, read data mrd_read2, -- 3rd wishbone read cycle step, reset control signals and increment counters mrdre_forward, -- send data that were buffered in mrd_process mrdre_wait, -- wait until tx buffer is done mrd_finish1, -- init sending parity mrd_finish2, -- wait until parity sent -- REGISTER_ARD (auto-address-increment, reading multiple adjacent registers) ard_init1, -- send opcode and id, store start address and length ard_init2, -- wait until tx buffer is done with opcode and id, clear rx buffer ard_process, -- 1st wishbone cycle step, central state ard_read1, -- 2nd wishbone read cycle step. Read data ard_read2, -- 3rd wishbone read cycle step. Reset control signals and increment counters ardre_forward, -- send data that were buffered in ard_process ardre_wait, -- wait until tx buffer is done ard_finish1, -- init sending parity ard_finish2, -- wait until parity sent -- interrupts int_init, int_finish, int_en ); type reg_type is record state : state_type; rdre_buffer : std_logic_vector(WB_DW-1 downto 0); ardre_buffer : std_logic_vector((FIFO_WIDTH*PROTO_WC_TX_MAX)-1 downto 0); -- used to buffer auto-address-increment -- read data before forwarding to tx buffer interrupt_en : std_logic; timeout_cnt : integer range 0 to WB_TIMEOUT_CYCLES-1; frame_id : std_logic_vector(FIFO_WIDTH-1 downto 0); error_code : std_logic_vector(FIFO_WIDTH-1 downto 0); start_address : std_logic_vector(WB_AW-1 downto 0); -- start address (mwr, awr and ard) length : integer range 0 to REGISTER_DAT_MAX + REGISTER_MWR_LEN; -- total length of mwr/awr frames -- data-only length of ard frames process_cnt : integer range 0 to REGISTER_DAT_MAX; -- number of bytes already written (mwr/awr) or -- number of reads (ard) receive_cnt : integer range 1 to ((REGISTER_DAT_MAX + REGISTER_MWR_LEN) / 16) + 1; -- how many times the rx-buffer has asserted complete next_byte_pos : integer range 0 to PROTO_WC_RX_MAX; -- position of the next byte to write parity : std_logic_vector(FIFO_WIDTH-1 downto 0); -- stores a parity that is calculated in more than one state end record; signal reg_out, reg_in : reg_type; begin --===========================================================================-- COMBINATIONAL : process(d, reg_out, wbi) --===========================================================================-- variable tmp : reg_type; begin tmp := reg_out; -- default assignments case tmp.state is --IDLE------------------------------------------------------------------- when idle => -- outputs q.recbuf_clear <= '0'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '0'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- reset register values tmp.timeout_cnt := 0; tmp.frame_id := x"00"; tmp.next_byte_pos := 0; tmp.length := 0; tmp.process_cnt := 0; tmp.parity := (others => '0'); tmp.receive_cnt := 1; tmp.ardre_buffer := (others => '-'); -- set error code to unknown tmp.error_code := ERROR_UNKNOWN; -- next state if (wbi.girq = '1' AND tmp.interrupt_en = '1') then -- irq tmp.state := int_init; elsif (d.recbuf_complete = '1') then -- frame received tmp.state := opcode_check; else tmp.state := idle; end if; --INT_INIT--------------------------------------------------------------- when int_init => -- outputs q.recbuf_clear <= '0'; q.trabuf_valid <= '1'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '1'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- compose frame q.trabuf_frame(q.trabuf_frame'length-1 downto 24) <= (others => '-'); q.trabuf_frame(23 downto 0) <= wbi.int_adr & -- parity (= core address) wbi.int_adr & -- core address (8 bit) SOC_INT_OPC; -- next state if (d.trabuf_busy = '1') then tmp.state := int_finish; else tmp.state := int_init; end if; --INT_FINISH------------------------------------------------------------- when int_finish => -- outputs q.recbuf_clear <= '0'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '1'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- disable interrupts (to avoid sending infinite interrupts) tmp.interrupt_en := '0'; -- next state if d.trabuf_busy = '1' then tmp.state := int_finish; else tmp.state := idle; end if; --OPCODE_CHECK----------------------------------------------------------- when opcode_check => -- outputs (the same as in idle) q.recbuf_clear <= '0'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '0'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- store frame id tmp.frame_id := d.recbuf_frame(15 downto 8); -- mcu_select if (d.recbuf_frame(7 downto 0) = MCU_SEL_OPC) then -- parity check if (( MCU_SEL_OPC xor d.recbuf_frame(15 downto 8)) = d.recbuf_frame(23 downto 16)) then tmp.state := mcu_select0; else tmp.error_code := ERROR_PARITY; tmp.state := nack0; end if; -- detect elsif (d.recbuf_frame(7 downto 0) = DETECT_OPC) then tmp.state := detect0; -- soc_int_en elsif (d.recbuf_frame(7 downto 0) = SOC_INT_EN_OPC) then --assert false report "received SOC_INT_EN" severity note; -- parity check if (( SOC_INT_EN_OPC xor d.recbuf_frame(15 downto 8)) = d.recbuf_frame(23 downto 16)) then tmp.state := int_en; else tmp.error_code := ERROR_PARITY; tmp.state := nack0; end if; -- register_wr elsif (d.recbuf_frame(7 downto 0) = REGISTER_WR_OPC) then --assert false report "received REGISTER_WR" severity note; -- parity check if (( REGISTER_WR_OPC xor d.recbuf_frame(15 downto 8) xor d.recbuf_frame(23 downto 16) xor d.recbuf_frame(31 downto 24) xor d.recbuf_frame(39 downto 32)) = d.recbuf_frame(47 downto 40)) then tmp.state := wr_init; else tmp.error_code := ERROR_PARITY; tmp.state := nack0; end if; -- register_mwr elsif (d.recbuf_frame(7 downto 0) = REGISTER_MWR_OPC) then --assert false report "received REGISTER_MWR" severity note; tmp.state := multi_init; -- register_awr elsif (d.recbuf_frame(7 downto 0) = REGISTER_AWR_OPC) then --assert false report "received REGISTER_AWR" severity note; tmp.state := multi_init; -- register_rd elsif (d.recbuf_frame(7 downto 0) = REGISTER_RD_OPC) then --assert false report "received REGISTER_RD" severity note; -- parity check if (( REGISTER_RD_OPC xor d.recbuf_frame(15 downto 8) xor d.recbuf_frame(23 downto 16) xor d.recbuf_frame(31 downto 24)) = d.recbuf_frame(39 downto 32)) then tmp.state := rd_init; else tmp.error_code := ERROR_PARITY; tmp.state := nack0; end if; -- register_mrd elsif (d.recbuf_frame(7 downto 0) = REGISTER_MRD_OPC) then --assert false report "received REGISTER_MRD" severity note; -- parity check if (( REGISTER_MRD_OPC xor d.recbuf_frame(15 downto 8) xor d.recbuf_frame(23 downto 16) xor d.recbuf_frame(31 downto 24) xor d.recbuf_frame(39 downto 32)) = d.recbuf_frame(47 downto 40)) then tmp.state := mrd_init1; else tmp.error_code := ERROR_PARITY; tmp.state := nack0; end if; -- register_ard elsif (d.recbuf_frame(7 downto 0) = REGISTER_ARD_OPC) then --assert false report "received REGISTER_ARD" severity note; -- parity check if (( REGISTER_ARD_OPC xor d.recbuf_frame(15 downto 8) xor d.recbuf_frame(23 downto 16) xor d.recbuf_frame(31 downto 24) xor d.recbuf_frame(39 downto 32)) = d.recbuf_frame(47 downto 40)) then tmp.state := ard_init1; else tmp.error_code := ERROR_PARITY; tmp.state := nack0; end if; -- unknown opcode: send nack after a timeout else -- stay in this state until timeout (use process_cnt for counting) if (tmp.process_cnt < OPCODE_UNKNOWN_TIMEOUT) then tmp.state := opcode_check; tmp.process_cnt := tmp.process_cnt + 1; else assert false report "received unknown opcode, will now reply nack" severity warning; -- send nack (assume correct ID reception) tmp.error_code := ERROR_OPC_UNKNOWN; tmp.state := nack0; tmp.frame_id := d.recbuf_frame(15 downto 8); end if; end if; --WR_INIT---------------------------------------------------------------- when wr_init => -- outputs q.recbuf_clear <= '0'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '0'; wbo.dat <= d.recbuf_frame(39 downto 32); -- |--- core address ---| |--- register address ---| wbo.adr <= d.recbuf_frame(23 downto 16) & d.recbuf_frame(31 downto 24); wbo.stb <= '1'; wbo.we <= '1'; wbo.cyc <= '1'; -- increment timeout counter tmp.timeout_cnt := tmp.timeout_cnt + 1; -- next state if (wbi.ack = '1') then tmp.state := wr_finish; elsif (tmp.timeout_cnt < WB_TIMEOUT_CYCLES - 1) then tmp.state := wr_init; else -- timout tmp.error_code := ERROR_WB_TIMEOUT; tmp.state := nack0; end if; --WR_FINISH-------------------------------------------------------------- when wr_finish => -- outputs q.recbuf_clear <= '1'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '0'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state tmp.state := ack0; --MULTI_INIT------------------------------------------------------------- when multi_init => -- outputs q.recbuf_clear <= '0'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '0'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- store address tmp.start_address := d.recbuf_frame(23 downto 16) & d.recbuf_frame(31 downto 24); -- store length if (d.recbuf_frame(7 downto 0) = REGISTER_MWR_OPC) then tmp.length := to_integer(unsigned(d.recbuf_frame(39 downto 32))) + REGISTER_MWR_LEN; elsif (d.recbuf_frame(7 downto 0) = REGISTER_AWR_OPC) then tmp.length := to_integer(unsigned(d.recbuf_frame(39 downto 32))) + REGISTER_AWR_LEN; end if; -- reset process counter (which is used as write-counter) tmp.process_cnt := 0; -- set initial byte position tmp.next_byte_pos := 5; -- one rx-buffer is already received, "reset" to one has been done in idle state -- tmp.receive_cnt := 1; -- calculate parity over opcode, id, both address bytes and length tmp.parity := d.recbuf_frame(7 downto 0) xor d.recbuf_frame(15 downto 8) xor d.recbuf_frame(23 downto 16) xor d.recbuf_frame(31 downto 24) xor d.recbuf_frame(39 downto 32); -- next state, proceed after 6 bytes received if (d.recbuf_frame(7 downto 0) = REGISTER_MWR_OPC) then tmp.state := mwr_process; elsif (d.recbuf_frame(7 downto 0) = REGISTER_AWR_OPC) then tmp.state := awr_process; end if; --MWR_PROCESS------------------------------------------------------------ when mwr_process => --outputs q.recbuf_clear <= '0'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '0'; -- everything has been written, don't write the parity byte if (tmp.length = REGISTER_MWR_LEN + tmp.process_cnt) then wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state will be flush, don't write elsif (tmp.next_byte_pos = PROTO_WC_RX_MAX) then wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- init wishbone cycle else wbo.dat <= d.recbuf_frame((tmp.next_byte_pos * 8) + 7 downto tmp.next_byte_pos * 8); wbo.adr <= tmp.start_address; wbo.stb <= '1'; wbo.we <= '1'; wbo.cyc <= '1'; -- increment timeout counter tmp.timeout_cnt := tmp.timeout_cnt + 1; end if; -- next state -- if complete, enter wr_finish if ((tmp.length = REGISTER_MWR_LEN + tmp.process_cnt) and -- length = overhead + write count --> all writes done (tmp.receive_cnt * 16 >= tmp.length)) then -- potentially received bytes >= length --> all bytes (parity incl.) received -- parity check if (tmp.parity = d.recbuf_frame((tmp.next_byte_pos * 8) + 7 downto tmp.next_byte_pos * 8)) then tmp.state := wr_finish; else tmp.error_code := ERROR_PARITY; tmp.state := nack0; end if; -- enter flush when buffer processed but bytes left (byte position overruns buffer width) elsif (tmp.next_byte_pos = PROTO_WC_RX_MAX) then tmp.state := mwr_flush; -- enter next_byte after core acknowledges, until then stay in this state unless timeout elsif (wbi.ack = '1') then -- xor data byte to parity tmp.parity := tmp.parity xor d.recbuf_frame((tmp.next_byte_pos * 8) + 7 downto tmp.next_byte_pos * 8); tmp.state := mwr_write1; elsif (tmp.timeout_cnt < WB_TIMEOUT_CYCLES - 1) then tmp.state := mwr_process; else -- timeout tmp.error_code := ERROR_WB_TIMEOUT; tmp.state := nack0; end if; --MWR_WRITE1------------------------------------------------------------- when mwr_write1 => -- outputs q.recbuf_clear <= '0'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '0'; -- 2nd wishbone cycle wbo.dat <= d.recbuf_frame((tmp.next_byte_pos * 8) + 7 downto tmp.next_byte_pos * 8); wbo.adr <= tmp.start_address; wbo.stb <= '1'; wbo.we <= '1'; wbo.cyc <= '1'; -- next state tmp.state := mwr_write2; --MWR_WRITE2------------------------------------------------------------- when mwr_write2 => -- outputs q.recbuf_clear <= '0'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '0'; -- 3rd wishbone cycle wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- increment write counter and byte position tmp.process_cnt := tmp.process_cnt + 1; tmp.next_byte_pos := tmp.next_byte_pos + 1; -- reset timeout counter tmp.timeout_cnt := 0; -- next state tmp.state := mwr_process; --MWR_FLUSH-------------------------------------------------------------- when mwr_flush => -- outputs q.recbuf_clear <= '1'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '0'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- start at the beginning after flush tmp.next_byte_pos := 0; -- next state tmp.state := mwr_wait; --MWR_WAIT--------------------------------------------------------------- when mwr_wait => -- outputs q.recbuf_clear <= '0'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '0'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state if (d.recbuf_complete = '1') then tmp.state := mwr_process; -- after this state one more buffer is completely received tmp.receive_cnt := tmp.receive_cnt + 1; else tmp.state := mwr_wait; end if; --AWR_PROCESS------------------------------------------------------------ when awr_process => --outputs q.recbuf_clear <= '0'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '0'; -- everything has been written, don't write the parity byte if (tmp.length = REGISTER_MWR_LEN + tmp.process_cnt) then wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state will be flush, don't write elsif (tmp.next_byte_pos = PROTO_WC_RX_MAX) then wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- 1st wishbone cycle else wbo.dat <= d.recbuf_frame((tmp.next_byte_pos * 8) + 7 downto tmp.next_byte_pos * 8); wbo.stb <= '1'; wbo.we <= '1'; wbo.cyc <= '1'; -- core address-part gets incremented by process_cnt (write counter) wbo.adr <= tmp.start_address(WB_AW - 1 downto WB_AW - WB_REG_AW) & std_logic_vector(to_unsigned( to_integer(unsigned(tmp.start_address(WB_REG_AW - 1 downto 0))) + tmp.process_cnt , WB_CORE_AW)); -- increment timeout counter tmp.timeout_cnt := tmp.timeout_cnt + 1; end if; -- next state -- if complete, enter wr_finish if ((tmp.length = REGISTER_MWR_LEN + tmp.process_cnt) and -- length = overhead + write count AND --> all writes done (tmp.receive_cnt * 16 >= tmp.length)) then -- potentially received bytes >= length --> all bytes (parity incl.) received -- parity check if (tmp.parity = d.recbuf_frame((tmp.next_byte_pos * 8) + 7 downto tmp.next_byte_pos * 8)) then tmp.state := wr_finish; else tmp.error_code := ERROR_PARITY; tmp.state := nack0; end if; -- enter flush when buffer processed but bytes left (byte position overruns buffer width) elsif (tmp.next_byte_pos = PROTO_WC_RX_MAX) then tmp.state := awr_flush; -- enter next_byte after core acknowledges, until then stay in this state unless timeout elsif (wbi.ack = '1') then -- xor data byte to parity tmp.parity := tmp.parity xor d.recbuf_frame((tmp.next_byte_pos * 8) + 7 downto tmp.next_byte_pos * 8); tmp.state := awr_write1; elsif (tmp.timeout_cnt < WB_TIMEOUT_CYCLES - 1) then tmp.state := awr_process; else -- timeout tmp.error_code := ERROR_WB_TIMEOUT; tmp.state := nack0; end if; --AWR_WRITE1------------------------------------------------------------- when awr_write1 => -- outputs q.recbuf_clear <= '0'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '0'; -- 2nd wishbone cycle wbo.dat <= d.recbuf_frame((tmp.next_byte_pos * 8) + 7 downto tmp.next_byte_pos * 8); wbo.stb <= '1'; wbo.we <= '1'; wbo.cyc <= '1'; -- core address-part gets incremented by process_cnt (write counter) wbo.adr <= tmp.start_address(WB_AW - 1 downto WB_AW - WB_REG_AW) & std_logic_vector(to_unsigned( to_integer(unsigned(tmp.start_address(WB_REG_AW - 1 downto 0))) + tmp.process_cnt , WB_CORE_AW)); -- next state tmp.state := awr_write2; --AWR_WRITE2------------------------------------------------------------- when awr_write2 => -- outputs q.recbuf_clear <= '0'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '0'; -- 3rd wishbone cycle wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- increment write counter and byte position tmp.process_cnt := tmp.process_cnt + 1; tmp.next_byte_pos := tmp.next_byte_pos + 1; -- reset timeout counter tmp.timeout_cnt := 0; -- next state tmp.state := awr_process; --AWR_FLUSH-------------------------------------------------------------- when awr_flush => -- outputs q.recbuf_clear <= '1'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '0'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- start at the beginning after flush tmp.next_byte_pos := 0; -- next state tmp.state := awr_wait; --AWR_WAIT--------------------------------------------------------------- when awr_wait => -- outputs q.recbuf_clear <= '0'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '0'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state if (d.recbuf_complete = '1') then tmp.state := awr_process; -- after this state one more buffer is completely received tmp.receive_cnt := tmp.receive_cnt + 1; else tmp.state := awr_wait; end if; --RD_INIT---------------------------------------------------------------- when rd_init => -- outputs q.recbuf_clear <= '0'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '0'; wbo.dat <= (others => '-'); -- |--- core address ---| |--- register address ---| wbo.adr <= d.recbuf_frame(23 downto 16) & d.recbuf_frame(31 downto 24); wbo.stb <= '1'; wbo.we <= '0'; wbo.cyc <= '1'; -- increment timeout counter tmp.timeout_cnt := tmp.timeout_cnt + 1; -- next state: wait until slave acknowledges if (wbi.ack = '1') then tmp.state := rd_buffer; elsif (tmp.timeout_cnt < WB_TIMEOUT_CYCLES - 1) then tmp.state := rd_init; else -- timeout tmp.error_code := ERROR_WB_TIMEOUT; tmp.state := nack0; end if; --RD_BUFFER-------------------------------------------------------------- when rd_buffer => -- outputs: clear recbuf, store reply in buffer q.recbuf_clear <= '1'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '0'; wbo.dat <= (others => '-'); -- |--- core address ---| |--- register address ---| wbo.adr <= d.recbuf_frame(23 downto 16) & d.recbuf_frame(31 downto 24); wbo.stb <= '1'; wbo.we <= '0'; wbo.cyc <= '1'; -- store reply in buffer tmp.rdre_buffer := wbi.dat; -- next state tmp.state := rdre_init; --RDRE_INIT-------------------------------------------------------------- when rdre_init => -- outputs: send REGISTER_RDRE to trabuf, close wb cycle -- compose frame q.trabuf_frame(7 downto 0) <= REGISTER_RDRE_OPC; -- opcode q.trabuf_frame(15 downto 8) <= tmp.frame_id; -- frame id q.trabuf_frame(23 downto 16) <= tmp.rdre_buffer(7 downto 0); -- data q.trabuf_frame(31 downto 24) <= REGISTER_RDRE_OPC XOR -- parity tmp.frame_id XOR tmp.rdre_buffer(7 downto 0); q.trabuf_frame(q.trabuf_frame'length-1 downto 32) <= (others => '-'); q.trabuf_valid <= '1'; q.trabuf_length <= 0; q.recbuf_clear <= '1'; q.mcu_select <= '0'; q.transmitter_mode <= '1'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state: Wait until trabuf is busy if (d.trabuf_busy = '1') then tmp.state := rdre_finish; else tmp.state := rdre_init; end if; --RDRE_FINISH------------------------------------------------------------ when rdre_finish => -- outputs q.recbuf_clear <= '1'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '1'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state: Wait until trabuf is done if (d.trabuf_busy = '1') then tmp.state := rdre_finish; else tmp.state := idle; end if; --MRD_INIT1-------------------------------------------------------------- when mrd_init1 => -- outputs q.recbuf_clear <= '0'; q.mcu_select <= '0'; q.transmitter_mode <= '1'; -- already transmit opcode and id q.trabuf_valid <= '1'; q.trabuf_length <= 2; q.trabuf_frame(q.trabuf_frame'length-1 downto 16) <= (others => '-'); q.trabuf_frame(15 downto 0) <= d.recbuf_frame(15 downto 8) & -- id REGISTER_MRDRE_OPC; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- init parity tmp.parity := REGISTER_MRDRE_OPC xor d.recbuf_frame(15 downto 8); -- opc xor id -- store address tmp.start_address := d.recbuf_frame(23 downto 16) & d.recbuf_frame(31 downto 24); -- store length tmp.length := to_integer(unsigned(d.recbuf_frame(39 downto 32))); -- reset process (read) counter and next byte position tmp.process_cnt := 0; tmp.next_byte_pos := 0; -- next state: proceed when trabuf is busy if (d.trabuf_busy = '1') then tmp.state := mrd_init2; else tmp.state := mrd_init1; end if; --MRD_INIT2-------------------------------------------------------------- when mrd_init2 => -- outputs q.recbuf_clear <= '1'; q.mcu_select <= '0'; q.transmitter_mode <= '1'; q.trabuf_valid <= '0'; q.trabuf_length <= 2; q.trabuf_frame <= (others => '-'); wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state: proceed when trabuf done if (d.trabuf_busy = '0') then tmp.state := mrd_process; else tmp.state := mrd_init2; end if; --MRD_PROCESS------------------------------------------------------------ when mrd_process => -- outputs q.recbuf_clear <= '0'; q.mcu_select <= '0'; q.transmitter_mode <= '0'; q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.trabuf_frame <= (others => '-'); -- if mrdre buffer is full if (tmp.next_byte_pos = PROTO_WC_TX_MAX) then wbo.adr <= (others => '-'); wbo.dat <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- if there is data left to read elsif (tmp.process_cnt < tmp.length) then -- 1st wishbone read cycle wbo.adr <= tmp.start_address; wbo.dat <= (others => '-'); wbo.stb <= '1'; wbo.we <= '0'; wbo.cyc <= '1'; -- buffer is not full, but there is no data to read else wbo.adr <= (others => '-'); wbo.dat <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; end if; -- increment wishbone timeout counter tmp.timeout_cnt := tmp.timeout_cnt + 1; -- next state if (not (tmp.length = 0)) then -- forward if mrdre buffer is full ... if (tmp.next_byte_pos = PROTO_WC_TX_MAX) then -- wait here when tx buffer is busy if (d.trabuf_busy = '0') then tmp.state := mrdre_forward; else tmp.state := mrd_process; end if; -- ... or if processing has finish (all data read) elsif (tmp.process_cnt = tmp.length) then tmp.state := mrdre_forward; elsif (wbi.ack = '1') then tmp.state := mrd_read1; elsif (tmp.timeout_cnt < WB_TIMEOUT_CYCLES - 1) then tmp.state := mrd_process; else -- timeout tmp.error_code := ERROR_WB_TIMEOUT; tmp.state := nack0; end if; -- if length = 0 else tmp.state := mrd_finish1; end if; --MRD_READ1-------------------------------------------------------------- when mrd_read1 => -- outputs q.recbuf_clear <= '0'; q.mcu_select <= '0'; q.transmitter_mode <= '0'; q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.trabuf_frame <= (others => '-'); -- 2nd wishbone read cycle wbo.adr <= tmp.start_address; wbo.dat <= (others => '-'); wbo.stb <= '1'; wbo.we <= '0'; wbo.cyc <= '1'; -- buffer register content tmp.ardre_buffer(((tmp.next_byte_pos*FIFO_WIDTH) + 7) downto (tmp.next_byte_pos*FIFO_WIDTH)) := wbi.dat; -- update parity tmp.parity := tmp.parity xor wbi.dat; -- next state tmp.state := mrd_read2; --MRD_READ2-------------------------------------------------------------- when mrd_read2 => -- outputs q.recbuf_clear <= '0'; q.mcu_select <= '0'; q.transmitter_mode <= '0'; q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.trabuf_frame <= (others => '-'); -- 3rd wishbone read cycle wbo.adr <= (others => '-'); wbo.dat <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- increment process (read) counter and next byte position tmp.process_cnt := tmp.process_cnt + 1; tmp.next_byte_pos := tmp.next_byte_pos + 1; -- reset wishbone timeout counter tmp.timeout_cnt := 0; -- next state tmp.state := mrd_process; --MRDRE_WAIT------------------------------------------------------------- when mrdre_wait => -- outputs q.recbuf_clear <= '0'; q.mcu_select <= '0'; q.transmitter_mode <= '1'; q.trabuf_valid <= '0'; q.trabuf_length <= tmp.next_byte_pos; q.trabuf_frame <= tmp.ardre_buffer; wbo.adr <= (others => '-'); wbo.dat <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state, proceed when transmit buffer is done if (d.trabuf_busy = '0') then -- if there is data left to read if (tmp.process_cnt < tmp.length) then tmp.next_byte_pos := 0; tmp.state := mrd_process; else tmp.state := mrd_finish1; end if; else tmp.state := mrdre_wait; end if; --MRD_FINISH1------------------------------------------------------------ when mrd_finish1 => -- outputs q.recbuf_clear <= '1'; q.mcu_select <= '0'; q.transmitter_mode <= '1'; q.trabuf_valid <= '1'; q.trabuf_length <= 1; q.trabuf_frame(q.trabuf_frame'length-1 downto 8) <= (others => '-'); q.trabuf_frame(7 downto 0) <= tmp.parity; wbo.adr <= (others => '-'); wbo.dat <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state if (d.trabuf_busy = '1') then tmp.state := mrd_finish2; else tmp.state := mrd_finish1; end if; --MRD_FINISH2------------------------------------------------------------ when mrd_finish2 => -- outputs q.recbuf_clear <= '1'; q.mcu_select <= '0'; q.transmitter_mode <= '1'; q.trabuf_valid <= '0'; q.trabuf_length <= 1; q.trabuf_frame(q.trabuf_frame'length-1 downto 8) <= (others => '-'); q.trabuf_frame(7 downto 0) <= tmp.parity; wbo.adr <= (others => '-'); wbo.dat <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state if (d.trabuf_busy = '1') then tmp.state := mrd_finish2; else tmp.state := idle; end if; --MRDRE_FORWARD---------------------------------------------------------- when mrdre_forward => -- outputs q.recbuf_clear <= '0'; q.mcu_select <= '0'; q.transmitter_mode <= '1'; q.trabuf_valid <= '1'; q.trabuf_length <= tmp.next_byte_pos; q.trabuf_frame <= tmp.ardre_buffer; wbo.adr <= (others => '-'); wbo.dat <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state tmp.state := mrdre_wait; --ARD_INIT1-------------------------------------------------------------- when ard_init1 => -- outputs q.recbuf_clear <= '0'; q.mcu_select <= '0'; q.transmitter_mode <= '1'; -- already transmit opcode and id q.trabuf_valid <= '1'; q.trabuf_length <= 2; q.trabuf_frame(q.trabuf_frame'length-1 downto 16) <= (others => '-'); q.trabuf_frame(15 downto 0) <= d.recbuf_frame(15 downto 8) & -- id REGISTER_ARDRE_OPC; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- init parity tmp.parity := REGISTER_ARDRE_OPC xor d.recbuf_frame(15 downto 8); -- store start address tmp.start_address := d.recbuf_frame(23 downto 16) & d.recbuf_frame(31 downto 24); -- store length tmp.length := to_integer(unsigned(d.recbuf_frame(39 downto 32))); -- reset process (read) counter and next byte position tmp.process_cnt := 0; tmp.next_byte_pos := 0; -- next state: proceed when trabuf is busy if (d.trabuf_busy = '1') then tmp.state := ard_init2; else tmp.state := ard_init1; end if; --ARD_INIT2-------------------------------------------------------------- when ard_init2 => -- outputs q.recbuf_clear <= '1'; q.mcu_select <= '0'; q.transmitter_mode <= '1'; q.trabuf_valid <= '0'; q.trabuf_length <= 2; q.trabuf_frame <= (others => '-'); wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state: proceed when trabuf done if (d.trabuf_busy = '0') then tmp.state := ard_process; else tmp.state := ard_init2; end if; --ARD_PROCESS------------------------------------------------------------ when ard_process => -- outputs q.recbuf_clear <= '0'; q.mcu_select <= '0'; q.transmitter_mode <= '0'; q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.trabuf_frame <= (others => '-'); -- if ardre buffer is full if (tmp.next_byte_pos = PROTO_WC_TX_MAX) then wbo.adr <= (others => '-'); wbo.dat <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- if there is data left to read elsif (tmp.process_cnt < tmp.length) then -- 1st wishbone read cycle wbo.adr <= tmp.start_address(WB_AW-1 downto WB_CORE_AW) & std_logic_vector(to_unsigned((to_integer(unsigned(tmp.start_address(WB_CORE_AW-1 downto 0))) + tmp.process_cnt), WB_CORE_AW)); wbo.dat <= (others => '-'); wbo.stb <= '1'; wbo.we <= '0'; wbo.cyc <= '1'; -- buffer is not full, but there is no data to read else wbo.adr <= (others => '-'); wbo.dat <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; end if; -- increment wishbone timeout counter tmp.timeout_cnt := tmp.timeout_cnt + 1; -- next state if (not (tmp.length = 0)) then -- forward if ardre buffer is full ... if (tmp.next_byte_pos = PROTO_WC_TX_MAX) then -- wait here when tx buffer is busy if (d.trabuf_busy = '0') then tmp.state := ardre_forward; else tmp.state := ard_process; end if; -- ... or if processing has finish (all data read) elsif (tmp.process_cnt = tmp.length) then tmp.state := ardre_forward; elsif (wbi.ack = '1') then tmp.state := ard_read1; elsif (tmp.timeout_cnt < WB_TIMEOUT_CYCLES - 1) then tmp.state := ard_process; else -- timeout tmp.error_code := ERROR_WB_TIMEOUT; tmp.state := nack0; end if; -- if length = 0 else tmp.state := ard_finish1; end if; --ARD_READ1-------------------------------------------------------------- when ard_read1 => -- outputs q.recbuf_clear <= '0'; q.mcu_select <= '0'; q.transmitter_mode <= '0'; q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.trabuf_frame <= (others => '-'); -- 2nd wishbone read cycle wbo.adr <= tmp.start_address(WB_AW-1 downto WB_CORE_AW) & std_logic_vector(to_unsigned((to_integer(unsigned(tmp.start_address(WB_CORE_AW-1 downto 0))) + tmp.process_cnt), WB_CORE_AW)); wbo.dat <= (others => '-'); wbo.stb <= '1'; wbo.we <= '0'; wbo.cyc <= '1'; -- buffer register content tmp.ardre_buffer(((tmp.next_byte_pos*FIFO_WIDTH) + 7) downto (tmp.next_byte_pos*FIFO_WIDTH)) := wbi.dat; -- update parity tmp.parity := tmp.parity xor wbi.dat; -- next state tmp.state := ard_read2; --ARD_READ2-------------------------------------------------------------- when ard_read2 => -- outputs q.recbuf_clear <= '0'; q.mcu_select <= '0'; q.transmitter_mode <= '0'; q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.trabuf_frame <= (others => '-'); -- 3rd wishbone read cycle wbo.adr <= (others => '-'); wbo.dat <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- increment process (read) counter and next byte position tmp.process_cnt := tmp.process_cnt + 1; tmp.next_byte_pos := tmp.next_byte_pos + 1; -- reset wishbone timeout counter tmp.timeout_cnt := 0; -- next state tmp.state := ard_process; --ARDRE_FORWARD---------------------------------------------------------- when ardre_forward => -- outputs q.recbuf_clear <= '0'; q.mcu_select <= '0'; q.transmitter_mode <= '1'; q.trabuf_valid <= '1'; q.trabuf_length <= tmp.next_byte_pos; q.trabuf_frame <= tmp.ardre_buffer; wbo.adr <= (others => '-'); wbo.dat <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state tmp.state := ardre_wait; --ARDRE_WAIT------------------------------------------------------------- when ardre_wait => -- outputs q.recbuf_clear <= '0'; q.mcu_select <= '0'; q.transmitter_mode <= '1'; q.trabuf_valid <= '0'; q.trabuf_length <= tmp.next_byte_pos; q.trabuf_frame <= tmp.ardre_buffer; wbo.adr <= (others => '-'); wbo.dat <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state, proceed when transmit buffer is done if (d.trabuf_busy = '0') then -- if there is data left to read if (tmp.process_cnt < tmp.length) then tmp.next_byte_pos := 0; tmp.state := ard_process; else tmp.state := ard_finish1; end if; else tmp.state := ardre_wait; end if; --ARD_FINISH1------------------------------------------------------------ when ard_finish1 => -- outputs q.recbuf_clear <= '1'; q.mcu_select <= '0'; q.transmitter_mode <= '1'; q.trabuf_valid <= '1'; q.trabuf_length <= 1; q.trabuf_frame(q.trabuf_frame'length-1 downto 8) <= (others => '-'); q.trabuf_frame(7 downto 0) <= tmp.parity; wbo.adr <= (others => '-'); wbo.dat <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state if (d.trabuf_busy = '1') then tmp.state := ard_finish2; else tmp.state := ard_finish1; end if; --ARD_FINISH2------------------------------------------------------------ when ard_finish2 => -- outputs q.recbuf_clear <= '1'; q.mcu_select <= '0'; q.transmitter_mode <= '1'; q.trabuf_valid <= '0'; q.trabuf_length <= 1; q.trabuf_frame(q.trabuf_frame'length-1 downto 8) <= (others => '-'); q.trabuf_frame(7 downto 0) <= tmp.parity; wbo.adr <= (others => '-'); wbo.dat <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state if (d.trabuf_busy = '1') then tmp.state := ard_finish2; else tmp.state := idle; end if; --NACK0------------------------------------------------------------------ when nack0 => -- outputs -- compose frame q.trabuf_frame(7 downto 0) <= NACK_OPC; -- opcode q.trabuf_frame(15 downto 8) <= tmp.frame_id; -- frame id q.trabuf_frame(23 downto 16) <= tmp.error_code; -- error code q.trabuf_frame(31 downto 24) <= NACK_OPC XOR -- parity tmp.frame_id XOR tmp.error_code; q.trabuf_frame(q.trabuf_frame'length-1 downto 32) <= (others => '-'); q.recbuf_clear <= '1'; q.trabuf_valid <= '1'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '1'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state: wait until transmission buffer is busy if (d.trabuf_busy = '1') then tmp.state := nack1; else tmp.state := nack0; end if; --NACK1------------------------------------------------------------------ when nack1 => -- outputs q.recbuf_clear <= '1'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '1'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state: wait until transmission buffer is done if (d.trabuf_busy = '1') then tmp.state := nack1; else tmp.state := idle; end if; --ACK0------------------------------------------------------------------- when ack0 => -- outputs -- compose frame q.trabuf_frame(7 downto 0) <= ACK_OPC; -- opcode q.trabuf_frame(15 downto 8) <= tmp.frame_id; -- frame id q.trabuf_frame(23 downto 16) <= ACK_OPC XOR tmp.frame_id; -- parity q.trabuf_frame(q.trabuf_frame'length-1 downto 24) <= (others => '-'); q.recbuf_clear <= '1'; q.trabuf_valid <= '1'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '1'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state: wait until transmission buffer is busy if (d.trabuf_busy = '1') then tmp.state := ack1; else tmp.state := ack0; end if; --ACK1------------------------------------------------------------------- when ack1 => -- outputs q.recbuf_clear <= '1'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '1'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state: wait until transmission buffer is done if (d.trabuf_busy = '1') then tmp.state := ack1; else tmp.state := idle; end if; --MCU_SELECT0 : Send reply----------------------------------------------- when mcu_select0 => -- outputs -- compose frame q.trabuf_frame(7 downto 0) <= ACK_OPC; -- opcode q.trabuf_frame(15 downto 8) <= tmp.frame_id; -- frame id q.trabuf_frame(23 downto 16) <= ACK_OPC XOR tmp.frame_id; -- parity q.trabuf_frame(q.trabuf_frame'length-1 downto 24) <= (others => '-'); q.recbuf_clear <= '1'; q.trabuf_valid <= '1'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '1'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state: wait until transmission buffer is busy if (d.trabuf_busy = '1') then tmp.state := mcu_select1; else tmp.state := mcu_select0; end if; --MCU_SELECT1 : Wait until transmitted----------------------------------- when mcu_select1 => -- outputs q.recbuf_clear <= '1'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '1'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state: wait until transmission buffer is done if (d.trabuf_busy = '1') then tmp.state := mcu_select1; else tmp.state := mcu_select2; end if; --MCU_SELECT2 : Switch to MCU-------------------------------------------- when mcu_select2 => -- outputs (mcu_select and recbuf_clear asserted) q.recbuf_clear <= '1'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '1'; q.transmitter_mode <= '0'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state tmp.state := idle; --DETECT0 : Transmit reply----------------------------------------------- when detect0 => -- reply frame q.trabuf_frame(7 downto 0) <= DETECT_REPLY_OPC; -- opcode q.trabuf_frame(15 downto 8) <= DETECT_REPLY_FPGA; -- fpga identifier q.trabuf_frame(23 downto 16) <= DETECT_REPLY_OPC XOR DETECT_REPLY_FPGA; q.trabuf_frame(q.trabuf_frame'length-1 downto 24) <= (others => '-'); -- outputs q.recbuf_clear <= '1'; q.trabuf_valid <= '1'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '1'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state: wait until transmission buffer is busy if (d.trabuf_busy = '1') then tmp.state := detect1; else tmp.state := detect0; end if; --DETECT1 : Wait until transmitted--------------------------------------- when detect1 => -- outputs q.recbuf_clear <= '1'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '1'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- next state: wait until transmission buffer is done if (d.trabuf_busy = '1') then tmp.state := detect1; else tmp.state := idle; end if; --SOC_INT_EN------------------------------------------------------------- when int_en => -- outputs q.recbuf_clear <= '0'; q.trabuf_frame <= (others => '-'); q.trabuf_valid <= '0'; q.trabuf_length <= 0; q.mcu_select <= '0'; q.transmitter_mode <= '0'; wbo.dat <= (others => '-'); wbo.adr <= (others => '-'); wbo.stb <= '0'; wbo.we <= '0'; wbo.cyc <= '0'; -- store frame id tmp.frame_id := d.recbuf_frame(15 downto 8); -- enable interrupts tmp.interrupt_en := '1'; -- next state tmp.state := ack0; end case; ------------------------------------------------------------------------- reg_in <= tmp; -- drive register inputs end process COMBINATIONAL; --===========================================================================-- REGISTERS : process(clk,rst) --===========================================================================-- begin if rising_edge(clk) then if (rst = '1') then reg_out.state <= idle; else reg_out <= reg_in; end if; end if; end process REGISTERS; end two_proc;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ece324_clock_divider is port ( masterClk : in std_logic; period : in std_logic_vector(3 downto 0); clockHR : out std_logic; clockLR : out std_logic ); end ece324_clock_divider; architecture Behavioral of ece324_clock_divider is signal count1 : std_logic_vector(12 downto 0); signal count2 : std_logic_vector(3 downto 0); signal count3 : std_logic_vector(7 downto 0); signal clk, clk1Hz, clkPeriod : std_logic; begin -- 1 HZ Clock Clock1HZ: process(masterClk) begin if(masterClk'EVENT and masterClk = '1') then if(count1 = "1111111001001") then count1 <= "0000000000000"; else count1 <= count1 + 1; end if; end if; end process; clk1Hz <= count1(12); -- period based clock ClockPeriod: process(masterClk) begin if(masterClk'EVENT and masterClk = '1') then if(count2 = period) then count2 <= "0000"; clkPeriod <= '1'; else count2 <= count2 + 1; clkPeriod <= '0'; end if; end if; end process; -- clocked multiplexer Mux: process(masterClk) begin if(masterClk'EVENT and masterClk = '1') then if(period = "0000") then clk <= clk1Hz; else clk <= clkPeriod; end if; end if; end process; -- 50% duty cycle outputs ClockMain: process(clk) begin if(clk'EVENT and clk = '1') then if(count3 = "11111111") then count3 <= "00000000"; else count3 <= count3 + 1; end if; end if; end process; -- assign outputs clockLR <= count3(7); clockHR <= count3(1); end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ece324_clock_divider is port ( masterClk : in std_logic; period : in std_logic_vector(3 downto 0); clockHR : out std_logic; clockLR : out std_logic ); end ece324_clock_divider; architecture Behavioral of ece324_clock_divider is signal count1 : std_logic_vector(12 downto 0); signal count2 : std_logic_vector(3 downto 0); signal count3 : std_logic_vector(7 downto 0); signal clk, clk1Hz, clkPeriod : std_logic; begin -- 1 HZ Clock Clock1HZ: process(masterClk) begin if(masterClk'EVENT and masterClk = '1') then if(count1 = "1111111001001") then count1 <= "0000000000000"; else count1 <= count1 + 1; end if; end if; end process; clk1Hz <= count1(12); -- period based clock ClockPeriod: process(masterClk) begin if(masterClk'EVENT and masterClk = '1') then if(count2 = period) then count2 <= "0000"; clkPeriod <= '1'; else count2 <= count2 + 1; clkPeriod <= '0'; end if; end if; end process; -- clocked multiplexer Mux: process(masterClk) begin if(masterClk'EVENT and masterClk = '1') then if(period = "0000") then clk <= clk1Hz; else clk <= clkPeriod; end if; end if; end process; -- 50% duty cycle outputs ClockMain: process(clk) begin if(clk'EVENT and clk = '1') then if(count3 = "11111111") then count3 <= "00000000"; else count3 <= count3 + 1; end if; end if; end process; -- assign outputs clockLR <= count3(7); clockHR <= count3(1); end Behavioral;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: fg_tb_pkg.vhd -- -- Description: -- This is the demo testbench package file for fifo_generator_v8.4 core. -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE ieee.std_logic_arith.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; PACKAGE fg_tb_pkg IS FUNCTION divroundup ( data_value : INTEGER; divisor : INTEGER) RETURN INTEGER; ------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : INTEGER; false_case : INTEGER) RETURN INTEGER; ------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : STD_LOGIC; false_case : STD_LOGIC) RETURN STD_LOGIC; ------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : TIME; false_case : TIME) RETURN TIME; ------------------------ FUNCTION log2roundup ( data_value : INTEGER) RETURN INTEGER; ------------------------ FUNCTION hexstr_to_std_logic_vec( arg1 : string; size : integer ) RETURN std_logic_vector; ------------------------ COMPONENT fg_tb_rng IS GENERIC (WIDTH : integer := 8; SEED : integer := 3); PORT ( CLK : IN STD_LOGIC; RESET : IN STD_LOGIC; ENABLE : IN STD_LOGIC; RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) ); END COMPONENT; ------------------------ COMPONENT fg_tb_dgen IS GENERIC ( C_DIN_WIDTH : INTEGER := 32; C_DOUT_WIDTH : INTEGER := 32; C_CH_TYPE : INTEGER := 0; TB_SEED : INTEGER := 2 ); PORT ( RESET : IN STD_LOGIC; WR_CLK : IN STD_LOGIC; PRC_WR_EN : IN STD_LOGIC; FULL : IN STD_LOGIC; WR_EN : OUT STD_LOGIC; WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) ); END COMPONENT; ------------------------ COMPONENT fg_tb_dverif IS GENERIC( C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_USE_EMBEDDED_REG : INTEGER := 0; C_CH_TYPE : INTEGER := 0; TB_SEED : INTEGER := 2 ); PORT( RESET : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; PRC_RD_EN : IN STD_LOGIC; EMPTY : IN STD_LOGIC; DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); RD_EN : OUT STD_LOGIC; DOUT_CHK : OUT STD_LOGIC ); END COMPONENT; ------------------------ COMPONENT fg_tb_pctrl IS GENERIC( AXI_CHANNEL : STRING := "NONE"; C_APPLICATION_TYPE : INTEGER := 0; C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_WR_PNTR_WIDTH : INTEGER := 0; C_RD_PNTR_WIDTH : INTEGER := 0; C_CH_TYPE : INTEGER := 0; FREEZEON_ERROR : INTEGER := 0; TB_STOP_CNT : INTEGER := 2; TB_SEED : INTEGER := 2 ); PORT( RESET_WR : IN STD_LOGIC; RESET_RD : IN STD_LOGIC; WR_CLK : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; FULL : IN STD_LOGIC; EMPTY : IN STD_LOGIC; ALMOST_FULL : IN STD_LOGIC; ALMOST_EMPTY : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); DOUT_CHK : IN STD_LOGIC; PRC_WR_EN : OUT STD_LOGIC; PRC_RD_EN : OUT STD_LOGIC; RESET_EN : OUT STD_LOGIC; SIM_DONE : OUT STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; ------------------------ COMPONENT fg_tb_synth IS GENERIC( FREEZEON_ERROR : INTEGER := 0; TB_STOP_CNT : INTEGER := 0; TB_SEED : INTEGER := 1 ); PORT( CLK : IN STD_LOGIC; RESET : IN STD_LOGIC; SIM_DONE : OUT STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; ------------------------ COMPONENT fifo_69x512_hf_top IS PORT ( CLK : IN std_logic; RST : IN std_logic; PROG_FULL : OUT std_logic; WR_EN : IN std_logic; RD_EN : IN std_logic; DIN : IN std_logic_vector(69-1 DOWNTO 0); DOUT : OUT std_logic_vector(69-1 DOWNTO 0); FULL : OUT std_logic; EMPTY : OUT std_logic); END COMPONENT; ------------------------ END fg_tb_pkg; PACKAGE BODY fg_tb_pkg IS FUNCTION divroundup ( data_value : INTEGER; divisor : INTEGER) RETURN INTEGER IS VARIABLE div : INTEGER; BEGIN div := data_value/divisor; IF ( (data_value MOD divisor) /= 0) THEN div := div+1; END IF; RETURN div; END divroundup; --------------------------------- FUNCTION if_then_else ( condition : BOOLEAN; true_case : INTEGER; false_case : INTEGER) RETURN INTEGER IS VARIABLE retval : INTEGER := 0; BEGIN IF condition=false THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; --------------------------------- FUNCTION if_then_else ( condition : BOOLEAN; true_case : STD_LOGIC; false_case : STD_LOGIC) RETURN STD_LOGIC IS VARIABLE retval : STD_LOGIC := '0'; BEGIN IF condition=false THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; --------------------------------- FUNCTION if_then_else ( condition : BOOLEAN; true_case : TIME; false_case : TIME) RETURN TIME IS VARIABLE retval : TIME := 0 ps; BEGIN IF condition=false THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; ------------------------------- FUNCTION log2roundup ( data_value : INTEGER) RETURN INTEGER IS VARIABLE width : INTEGER := 0; VARIABLE cnt : INTEGER := 1; BEGIN IF (data_value <= 1) THEN width := 1; ELSE WHILE (cnt < data_value) LOOP width := width + 1; cnt := cnt *2; END LOOP; END IF; RETURN width; END log2roundup; ------------------------------------------------------------------------------ -- hexstr_to_std_logic_vec -- This function converts a hex string to a std_logic_vector ------------------------------------------------------------------------------ FUNCTION hexstr_to_std_logic_vec( arg1 : string; size : integer ) RETURN std_logic_vector IS VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); VARIABLE bin : std_logic_vector(3 DOWNTO 0); VARIABLE index : integer := 0; BEGIN FOR i IN arg1'reverse_range LOOP CASE arg1(i) IS WHEN '0' => bin := (OTHERS => '0'); WHEN '1' => bin := (0 => '1', OTHERS => '0'); WHEN '2' => bin := (1 => '1', OTHERS => '0'); WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); WHEN '4' => bin := (2 => '1', OTHERS => '0'); WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); WHEN '7' => bin := (3 => '0', OTHERS => '1'); WHEN '8' => bin := (3 => '1', OTHERS => '0'); WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'B' => bin := (2 => '0', OTHERS => '1'); WHEN 'b' => bin := (2 => '0', OTHERS => '1'); WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'D' => bin := (1 => '0', OTHERS => '1'); WHEN 'd' => bin := (1 => '0', OTHERS => '1'); WHEN 'E' => bin := (0 => '0', OTHERS => '1'); WHEN 'e' => bin := (0 => '0', OTHERS => '1'); WHEN 'F' => bin := (OTHERS => '1'); WHEN 'f' => bin := (OTHERS => '1'); WHEN OTHERS => FOR j IN 0 TO 3 LOOP bin(j) := 'X'; END LOOP; END CASE; FOR j IN 0 TO 3 LOOP IF (index*4)+j < size THEN result((index*4)+j) := bin(j); END IF; END LOOP; index := index + 1; END LOOP; RETURN result; END hexstr_to_std_logic_vec; END fg_tb_pkg;
architecture rtl of fifo is begin process begin var1 := '0' when rd_en = '1' else '1'; var2 := '0' when rd_en = '1' else '1'; wr_en_a <= force '0' when rd_en = '1' else '1'; wr_en_b <= force '0' when rd_en = '1' else '1'; end process; concurrent_wr_en_a <= '0' when rd_en = '1' ELSE '1'; concurrent_wr_en_b <= '0' when rd_en = '1' else '1'; end architecture rtl;
{{define "basicFB"}}-- This file has been automatically generated by goFB and should not be edited by hand -- Compiler written by Hammond Pearce and available at github.com/kiwih/goFB -- VHDL support is EXPERIMENTAL ONLY {{$block := index .Blocks .BlockIndex}}{{$blocks := .Blocks}}{{$basicFB := $block.BasicFB}} -- This file represents the Basic Function Block for {{$block.Name}} library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; {{template "_entityFB" .}} architecture rtl of {{$block.Name}} is -- Build an enumerated type for the state machine type state_type is ({{range $index, $state := $basicFB.States}}{{if $index}}, {{end}}STATE_{{$state.Name}}{{end}}); -- Register to hold the current state signal state : state_type := STATE_{{(index $basicFB.States 0).Name}}; {{if $block.InputVars}}-- signals to store variable sampled on enable {{range $index, $var := $block.InputVars.Variables}} signal {{$var.Name}} : {{getVhdlType $var.Type}} := {{if eq (getVhdlType $var.Type) "std_logic"}}'0'{{else}}(others => '0'){{end}}; --register for input{{end}} {{end}} {{if $block.OutputVars}}-- signals to rename outputs {{range $index, $var := $block.OutputVars.Variables}} signal {{$var.Name}} : {{getVhdlType $var.Type}} := {{if eq (getVhdlType $var.Type) "std_logic"}}'0'{{else}}(others => '0'){{end}}; {{end}} {{end}} {{if $block.EventOutputs}} --signals to rename output events {{range $index, $event := $block.EventOutputs.Events}}signal {{$event.Name}}_eO_ecc_out : std_logic := '0'; --used when event driven from ECC (normal FB behaviour) signal {{$event.Name}}_eO_alg_out : std_logic := '0'; --used when event driven from algorithm (normal SIFB behaviour) {{end}}{{end}} -- signals for enabling algorithms {{range $algIndex, $alg := $basicFB.Algorithms}} signal {{$alg.Name}}_alg_en : std_logic := '0'; signal {{$alg.Name}}_alg_done : std_logic := '1'; {{end}} -- signal for algorithm completion signal AlgorithmsStart : std_logic := '0'; signal AlgorithmsDone : std_logic; {{if $basicFB.InternalVars}}--internal variables {{range $varIndex, $var := $basicFB.InternalVars.Variables}}{{if not (or (variableIsTOPIO_IN $var) (variableIsTOPIO_OUT $var))}}{{/*ignore the special IO cos they are in the port list*/}} signal {{$var.Name}} : {{getVhdlType $var.Type}}; --type was {{$var.Type}} {{end}}{{end}}{{end}} begin {{if $block.EventInputs}}{{if $block.InputVars}}-- Registers for data variables (only updated on relevant events) process (clk) begin if rising_edge(clk) then if sync = '1' then {{range $eventIndex, $event := $block.EventInputs.Events}}{{if $event.With}} if {{$event.Name}}_eI = '1' then{{range $varIndex, $var := $block.InputVars.Variables}}{{if $event.IsLoadFor $var}} {{$var.Name}} <= {{$var.Name}}_I;{{end}}{{end}} end if; {{end}}{{end}} end if; end if; end process;{{end}}{{end}} {{if $block.OutputVars}}--output var renaming, no output registers as inputs are stored where they are processed {{range $varIndex, $var := $block.OutputVars.Variables}}{{$var.Name}}_O <= {{$var.Name}}; {{end}}{{end}} -- Logic to advance to the next state process (clk, reset) begin if reset = '1' then state <= STATE_{{(index $basicFB.States 0).Name}}; AlgorithmsStart <= '1'; elsif (rising_edge(clk)) then if AlgorithmsStart = '1' then --algorithms should be triggered only once via this pulse signal AlgorithmsStart <= '0'; elsif enable = '1' then --default values state <= state; AlgorithmsStart <= '0'; --next state logic case state is {{range $curStateIndex, $curState := $basicFB.States}}when STATE_{{$curState.Name}} => {{range $transIndex, $trans := $basicFB.GetTransitionsForState $curState.Name}}{{if $transIndex}}els{{end}}if {{getVhdlECCTransitionCondition $trans.Condition}} then state <= STATE_{{$trans.Destination}}; AlgorithmsStart <= '1'; {{end}}end if; {{end}} end case; end if; end if; end process; -- Event outputs and internal algorithm triggers depend solely on the current state process (state) begin --default values {{if $block.EventOutputs}}--events {{range $index, $event := $block.EventOutputs.Events}}{{$event.Name}}_eO_ecc_out <= '0'; {{end}}{{end}} {{if $basicFB.Algorithms}}--algorithms{{range $algIndex, $alg := $basicFB.Algorithms}} {{$alg.Name}}_alg_en <= '0'; {{end}}{{end}} case state is {{range $curStateIndex, $curState := $basicFB.States}}when STATE_{{$curState.Name}} => {{range $actionIndex, $action := $curState.ECActions}}{{if $action.Algorithm}}{{$action.Algorithm}}_alg_en <= '1'; {{end}}{{if $action.Output}}{{$action.Output}}_eO_ecc_out <= '1'; {{end}}{{end}} {{end}} end case; end process; {{if $basicFB.Algorithms}}-- Algorithms process process(clk) begin if rising_edge(clk) then if AlgorithmsStart = '1' then {{range $algIndex, $alg := $basicFB.Algorithms}} if {{$alg.Name}}_alg_en = '1' then -- Algorithm {{$alg.Name}} {{$alg.Name}}_alg_done <= '0'; {{if $block.EventOutputs}} --logic for resetting algorithm-driven output events {{range $index, $event := $block.EventOutputs.Events}}{{$event.Name}}_eO_alg_out <= '0'; {{end}}{{end}} end if; {{end}} end if; {{range $algIndex, $alg := $basicFB.Algorithms}} if {{$alg.Name}}_alg_done = '0' then -- Algorithm {{$alg.Name}} --begin algorithm raw text {{renameDoneSignal $alg.Other.Text $alg.Name}} --end algorithm raw text end if; {{end}} end if; end process;{{else}}--This Basic FB had no algorithms {{end}} --Done signal AlgorithmsDone <= (not AlgorithmsStart) and (not enable){{if $basicFB.Algorithms}} and{{range $algIndex, $alg := $basicFB.Algorithms}}{{if $algIndex}} and{{end}} {{$alg.Name}}_alg_done{{end}}{{end}}; Done <= AlgorithmsDone; {{if $block.EventOutputs}} --logic for renamed output events {{range $index, $event := $block.EventOutputs.Events}}{{$event.Name}}_eO <= {{$event.Name}}_eO_ecc_out or {{$event.Name}}_eO_alg_out; {{end}}{{end}} end rtl; {{end}}
--/************************************************************************************************************** --* --* L Z R W 1 E N C O D E R C O R E --* --* A high throughput loss less data compression core. --* --* Copyright 2012-2013 Lukas Schrittwieser (LS) --* --* This program is free software: you can redistribute it and/or modify --* it under the terms of the GNU General Public License as published by --* the Free Software Foundation, either version 2 of the License, or --* (at your option) any later version. --* --* This program is distributed in the hope that it will be useful, --* but WITHOUT ANY WARRANTY; without even the implied warranty of --* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --* GNU General Public License for more details. --* --* You should have received a copy of the GNU General Public License --* along with this program; if not, write to the Free Software --* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. --* Or see <http://www.gnu.org/licenses/> --* --*************************************************************************************************************** --* --* Change Log: --* --* Version 1.0 - 2012/10/16 - LS --* started file --* --* Version 1.0 - 2013/04/05 - LS --* released --* --*************************************************************************************************************** --* --* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html --* --*************************************************************************************************************** --* --* Top level file for data compressor. Implements the wishbone interfaces, a --* simple DMA controller and some glue logic. --* --*************************************************************************************************************** library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library UNISIM; use UNISIM.VComponents.all; entity CompressorTop is port ( ClkxCI : in std_logic; RstxRI : in std_logic; -- wishbone config and data input interface (32 bit access only!!) SlCycxSI : in std_logic; SlStbxSI : in std_logic; SlWexSI : in std_logic; SlSelxDI : in std_logic_vector(3 downto 0); SlAdrxDI : in std_logic_vector(4 downto 2); SlDatxDI : in std_logic_vector(31 downto 0); SlDatxDO : out std_logic_vector(31 downto 0); SlAckxSO : out std_logic; SlErrxSO : out std_logic; IntxSO : out std_logic; -- wishbone dma master interface MaCycxSO : out std_logic; MaStbxSO : out std_logic; MaWexSO : out std_logic; MaSelxDO : out std_logic_vector(3 downto 0); MaAdrxDO : out std_logic_vector(31 downto 0); MaDatxDO : out std_logic_vector(31 downto 0); MaDatxDI : in std_logic_vector(31 downto 0); MaAckxSI : in std_logic; MaErrxSI : in std_logic ); end CompressorTop; architecture Behavioral of CompressorTop is component InputFIFO port ( ClkxCI : in std_logic; RstxRI : in std_logic; DInxDI : in std_logic_vector(31 downto 0); WExSI : in std_logic; StopOutputxSI : in std_logic; BusyxSO : out std_logic; DOutxDO : out std_logic_vector(7 downto 0); OutStrobexSO : out std_logic; LengthxDO : out integer range 0 to 2048); end component; component LZRWcompressor port ( ClkxCI : in std_logic; RstxRI : in std_logic; DataInxDI : in std_logic_vector(7 downto 0); StrobexSI : in std_logic; FlushBufxSI : in std_logic; BusyxSO : out std_logic; DonexSO : out std_logic; BufOutxDO : out std_logic_vector(7 downto 0); OutputValidxSO : out std_logic; RdStrobexSI : in std_logic; LengthxDO : out integer range 0 to 1024); end component; constant INPUT_FIFO_SIZE : integer := 1024; -- length of input fifo in bytes constant DMA_LEN_SIZE : integer := 16; -- size of dma len counter in bits --constant MAX_DMA_LEN_VALUE : integer := 2**16-1; -- maximum value of the dma length counter signal RstCorexSN, RstCorexSP : std_logic := '1'; signal WeInFIFOxS : std_logic; signal InFIFOLenxD : integer range 0 to INPUT_FIFO_SIZE; signal CoreBusyxS : std_logic; signal CoreDonexS : std_logic; signal CoreDatInxD : std_logic_vector(7 downto 0); signal CoreStbxS : std_logic; signal FIFOBusyxS : std_logic; signal FlushxSN, FlushxSP : std_logic := '0'; signal FlushCorexSN, FlushCorexSP : std_logic := '0'; signal CoreRdStbxS : std_logic; signal OutFIFOLenxD : integer range 0 to 1024; signal CoreDatOutxD : std_logic_vector(7 downto 0); signal CoreOutValidxS : std_logic; signal ClearIntFlagsxSN, ClearIntFlagsxSP : std_logic := '0'; signal ClearInFIFOFlagsxS, ClearOutFIFOFlagsxS : std_logic; signal InFIFOEmptyFlgxSN, InFIFOEmptyFlgxSP : std_logic := '0'; signal InFIFOFullFlgxSN, InFIFOFullFlgxSP : std_logic := '0'; signal OutFIFOEmptyFlgxSN, OutFIFOEmptyFlgxSP : std_logic := '0'; signal OutFIFOFullFlgxSN, OutFIFOFullFlgxSP : std_logic := '0'; signal IEInFIFOEmptyxSN, IEInFIFOEmptyxSP : std_logic := '0'; signal IEInFIFOFullxSN, IEInFIFOFullxSP : std_logic := '0'; signal IEOutFIFOEmptyxSN, IEOutFIFOEmptyxSP : std_logic := '0'; signal IEOutFIFOFullxSN, IEOutFIFOFullxSP : std_logic := '0'; signal IEDmaErrxSN, IEDmaErrxSP : std_logic := '0'; signal IECoreDonexSN, IECoreDonexSP : std_logic := '0'; signal IRQxSN, IRQxSP : std_logic := '0'; signal InFIFOEmptyThrxDN, InFIFOEmptyThrxDP : std_logic_vector(15 downto 0) := (others => '0'); signal InFIFOFullThrxDN, InFIFOFullThrxDP : std_logic_vector(15 downto 0) := (others => '1'); signal OutFIFOEmptyThrxDN, OutFIFOEmptyThrxDP : std_logic_vector(15 downto 0) := (others => '0'); signal OutFIFOFullThrxDN, OutFIFOFullThrxDP : std_logic_vector(15 downto 0) := (others => '1'); signal IncDestAdrFlgxSN, IncDestAdrFlgxSP : std_logic := '0'; signal DmaErrFlgxSN, DmaErrFlgxSP : std_logic := '0'; signal WrDmaDestAdrxS : std_logic; signal WrDmaLenxS : std_logic; signal DmaBusyxSN, DmaBusyxSP : std_logic := '0'; signal DmaDestAdrxDN, DmaDestAdrxDP : std_logic_vector(31 downto 0) := (others => '0'); signal XferByteCntxDN, XferByteCntxDP : integer range 0 to 4 := 0; signal DmaLenxDN, DmaLenxDP : integer range 0 to 2**DMA_LEN_SIZE-1 := 0; signal DmaDataOutxDN, DmaDataOutxDP : std_logic_vector(31 downto 0) := (others => '0'); signal DmaSelxSN, DmaSelxSP : std_logic_vector(3 downto 0) := (others => '0'); signal MaCycxSN, MaCycxSP : std_logic := '0'; signal MaStbxSN, MaStbxSP : std_logic := '0'; begin -- Behavioral WbSlInPrcs : process (DmaBusyxSP, FlushCorexSP, FlushxSP, IECoreDonexSP, IEDmaErrxSP, IEInFIFOEmptyxSP, IEInFIFOFullxSP, IEOutFIFOEmptyxSP, IEOutFIFOFullxSP, InFIFOEmptyThrxDP, InFIFOFullThrxDP, IncDestAdrFlgxSP, OutFIFOEmptyThrxDP, OutFIFOFullThrxDP, SlAdrxDI, SlCycxSI, SlDatxDI, SlStbxSI, SlWexSI) begin WeInFIFOxS <= '0'; RstCorexSN <= '0'; FlushxSN <= FlushxSP and not FlushCorexSP; -- clear flush flag when core is flushed ClearInFIFOFlagsxS <= '0'; ClearOutFIFOFlagsxS <= '0'; ClearIntFlagsxSN <= '0'; IEInFIFOEmptyxSN <= IEInFIFOEmptyxSP; IEInFIFOFullxSN <= IEInFIFOFullxSP; IEOutFIFOEmptyxSN <= IEOutFIFOEmptyxSP; IEOutFIFOFullxSN <= IEOutFIFOFullxSP; IEDmaErrxSN <= IEDmaErrxSP; IECoreDonexSN <= IECoreDonexSP; IncDestAdrFlgxSN <= IncDestAdrFlgxSP; InFIFOEmptyThrxDN <= InFIFOEmptyThrxDP; InFIFOFullThrxDN <= InFIFOFullThrxDP; OutFIFOFullThrxDN <= OutFIFOFullThrxDP; OutFIFOEmptyThrxDN <= OutFIFOEmptyThrxDP; WrDmaDestAdrxS <= '0'; WrDmaLenxS <= '0'; -- decode write commands if SlCycxSI = '1' and SlStbxSI = '1' and SlWexSI = '1' then case SlAdrxDI is when "000" => -- data input register if FlushxSP = '0' then -- ignore all data after flush command was sent WeInFIFOxS <= '1'; end if; when "001" => -- config flags if DmaBusyxSP = '0' then IncDestAdrFlgxSN <= SlDatxDI(8); end if; IEInFIFOEmptyxSN <= SlDatxDI(16); IEInFIFOFullxSN <= SlDatxDI(17); IEOutFIFOEmptyxSN <= SlDatxDI(18); IEOutFIFOFullxSN <= SlDatxDI(19); IEDmaErrxSN <= SlDatxDI(20); IECoreDonexSN <= SlDatxDI(21); ClearIntFlagsxSN <= '1'; when "010" => InFIFOFullThrxDN <= SlDatxDI(31 downto 16); InFIFOEmptyThrxDN <= SlDatxDI(15 downto 0); ClearInFIFOFlagsxS <= '1'; when "011" => OutFIFOFullThrxDN <= SlDatxDI(31 downto 16); OutFIFOEmptyThrxDN <= SlDatxDI(15 downto 0); ClearOutFIFOFlagsxS <= '1'; when "100" => -- may only be written if dma unit is not busy if DmaBusyxSP = '0' then WrDmaDestAdrxS <= '1'; end if; when "101" => if DmaBusyxSP = '0' then WrDmaLenxS <= '1'; end if; when "111" => -- command register if SlDatxDI(0) = '1' then -- reset command RstCorexSN <= SlDatxDI(0); ClearInFIFOFlagsxS <= '1'; ClearOutFIFOFlagsxS <= '1'; end if; FlushxSN <= SlDatxDI(1) or FlushxSP; when others => null; end case; end if; end process WbSlInPrcs; -- we flush the core if a flush was requested and the intput fifo is empty FlushCorexSN <= '1' when FlushxSP = '1' and InFIFOLenxD = 0 else '0'; process (CoreDonexS, DmaBusyxSP, DmaDestAdrxDP, DmaErrFlgxSP, DmaLenxDP, IECoreDonexSP, IEDmaErrxSP, IEInFIFOEmptyxSP, IEInFIFOFullxSP, IEOutFIFOEmptyxSP, IEOutFIFOFullxSP, InFIFOEmptyFlgxSP, InFIFOEmptyThrxDP, InFIFOFullFlgxSP, InFIFOFullThrxDP, InFIFOLenxD, IncDestAdrFlgxSP, OutFIFOEmptyFlgxSP, OutFIFOEmptyThrxDP, OutFIFOFullFlgxSP, OutFIFOFullThrxDN, OutFIFOLenxD, SlAdrxDI, SlCycxSI, SlStbxSI, SlWexSI, XferByteCntxDP) begin -- SlDatxDO <= x"00000000"; -- decode read commands if SlCycxSI = '1' and SlStbxSI = '1' and SlWexSI = '0' then case SlAdrxDI is when "000" => null; -- data input, no read access when "001" => -- config and status reg SlDatxDO(3) <= DmaBusyxSP; SlDatxDO(8) <= IncDestAdrFlgxSP; -- config flags SlDatxDO(16) <= IEInFIFOEmptyxSP; -- interrupt enables SlDatxDO(17) <= IEInFIFOFullxSP; SlDatxDO(18) <= IEOutFIFOEmptyxSP; SlDatxDO(19) <= IEOutFIFOFullxSP; SlDatxDO(20) <= IEDmaErrxSP; SlDatxDO(21) <= IECoreDonexSP; SlDatxDO(24) <= InFIFOEmptyFlgxSP; -- interrupt flags SlDatxDO(25) <= InFIFOFullFlgxSP; SlDatxDO(26) <= OutFIFOEmptyFlgxSP; SlDatxDO(27) <= OutFIFOFullFlgxSP; SlDatxDO(28) <= DmaErrFlgxSP; SlDatxDO(29) <= CoreDonexS; --ClearIntFlagsxSN <= '1'; when "010" => SlDatxDO <= InFIFOFullThrxDP & InFIFOEmptyThrxDP; when "011" => SlDatxDO <= OutFIFOFullThrxDN & OutFIFOEmptyThrxDP; when "100" => SlDatxDO <= DmaDestAdrxDP(31 downto 2) & std_logic_vector(to_unsigned(XferByteCntxDP, 2)); when "101" => SlDatxDO <= x"0000" & std_logic_vector(to_unsigned(DmaLenxDP, DMA_LEN_SIZE)); when "110" => SlDatxDO <= std_logic_vector(to_unsigned(OutFIFOLenxD, 16)) & std_logic_vector(to_unsigned(InFIFOLenxD, 16)); when others => null; end case; end if; end process; -- create an ACK on slave bus for all 32bits accesses. Other types of -- accesses are not possible -> terminate with error signal SlAckxSO <= SlCycxSI and SlStbxSI when SlSelxDI = "1111" else '0'; SlErrxSO <= SlCycxSI and SlStbxSI when SlSelxDI /= "1111" else '0'; InterruptsPrcs : process (ClearInFIFOFlagsxS, ClearIntFlagsxSP, ClearOutFIFOFlagsxS, CoreDonexS, DmaErrFlgxSP, IECoreDonexSP, IEDmaErrxSP, IEInFIFOEmptyxSP, IEInFIFOFullxSP, IEOutFIFOEmptyxSP, IEOutFIFOFullxSP, InFIFOEmptyFlgxSP, InFIFOEmptyThrxDP, InFIFOFullFlgxSP, InFIFOFullThrxDP, InFIFOLenxD, OutFIFOEmptyFlgxSP, OutFIFOEmptyThrxDP, OutFIFOFullFlgxSP, OutFIFOFullThrxDP, OutFIFOLenxD) begin InFIFOEmptyFlgxSN <= InFIFOEmptyFlgxSP; InFIFOFullFlgxSN <= InFIFOFullFlgxSP; OutFIFOEmptyFlgxSN <= OutFIFOEmptyFlgxSP; OutFIFOFullFlgxSN <= OutFIFOFullFlgxSP; if ClearInFIFOFlagsxS = '0' then if InFIFOLenxD < to_integer(unsigned(InFIFOEmptyThrxDP)) then InFIFOEmptyFlgxSN <= '1'; end if; if InFIFOLenxD >= to_integer(unsigned(InFIFOFullThrxDP)) then InFIFOFullFlgxSN <= '1'; end if; else InFIFOEmptyFlgxSN <= '0'; InFIFOFullFlgxSN <= '0'; end if; if ClearOutFIFOFlagsxS = '0' then if OutFIFOLenxD < to_integer(unsigned(OutFIFOEmptyThrxDP)) then OutFIFOEmptyFlgxSN <= '1'; end if; if OutFIFOLenxD >= to_integer(unsigned(OutFIFOFullThrxDP)) then OutFIFOFullFlgxSN <= '1'; end if; else OutFIFOEmptyFlgxSN <= '0'; OutFIFOFullFlgxSN <= '0'; end if; if ClearIntFlagsxSP = '1' then InFIFOEmptyFlgxSN <= '0'; InFIFOFullFlgxSN <= '0'; OutFIFOEmptyFlgxSN <= '0'; OutFIFOFullFlgxSN <= '0'; end if; IRQxSN <= (InFIFOEmptyFlgxSP and IEInFIFOEmptyxSP) or (InFIFOFullFlgxSP and IEInFIFOFullxSP) or (OutFIFOEmptyFlgxSP and IEOutFIFOEmptyxSP) or (OutFIFOFullFlgxSP and IEOutFIFOFullxSP) or (DmaErrFlgxSP and IEDmaErrxSP) or (CoreDonexS and IECoreDonexSP); end process InterruptsPrcs; IntxSO <= IRQxSP; DmaPrcs : process (ClearIntFlagsxSP, CoreDatOutxD, CoreOutValidxS, DmaDataOutxDP, DmaDestAdrxDP, DmaErrFlgxSP, DmaLenxDP, DmaSelxSP, IncDestAdrFlgxSP, MaAckxSI, MaCycxSP, MaErrxSI, MaStbxSP, OutFIFOLenxD, RstCorexSP, SlDatxDI, WrDmaDestAdrxS, WrDmaLenxS, XferByteCntxDP) begin DmaLenxDN <= DmaLenxDP; DmaDestAdrxDN <= DmaDestAdrxDP; XferByteCntxDN <= XferByteCntxDP; DmaDataOutxDN <= DmaDataOutxDP; DmaSelxSN <= DmaSelxSP; CoreRdStbxS <= '0'; MaCycxSN <= MaCycxSP; MaStbxSN <= MaStbxSP; DmaErrFlgxSN <= DmaErrFlgxSP; -- if len is not zero dma unit is busy with a transfer if DmaLenxDP = 0 then DmaBusyxSN <= '0'; if WrDmaDestAdrxS = '1' then -- the last two bits specify at which byte within the 4 byte wide bus -- we start -> load them into the transfer byte counter DmaDestAdrxDN <= SlDatxDI(31 downto 2) & "00"; XferByteCntxDN <= to_integer(unsigned(SlDatxDI(1 downto 0))); DmaSelxSN <= (others => '0'); end if; if WrDmaLenxS = '1' then DmaLenxDN <= to_integer(unsigned(SlDatxDI(DMA_LEN_SIZE-1 downto 0))); end if; else if RstCorexSP = '1' then -- abort the dma operation DmaLenxDN <= 0; MaCycxSN <= '0'; MaStbxSN <= '0'; DmaBusyxSN <= '0'; else DmaBusyxSN <= '1'; -- wait until the last wishbone transfer is done if MaCycxSP = '0' then -- read data from output fifo when it becomes available if OutFIFOLenxD > 0 then -- output a read strobe if there is room for more than one byte -- (check dma length counter and transfer byte counter). This condition is -- loosened if there is no byte comming in this cycle if (XferByteCntxDP < 3 and DmaLenxDP > 1) or CoreOutValidxS = '0' then -- send read request to core CoreRdStbxS <= '1'; end if; end if; if CoreOutValidxS = '1' then -- copy byte from core into output buffer DmaLenxDN <= DmaLenxDP - 1; if IncDestAdrFlgxSP = '1' and XferByteCntxDP < 4 then XferByteCntxDN <= XferByteCntxDP + 1; end if; DmaDataOutxDN((XferByteCntxDP+1)*8-1 downto XferByteCntxDP*8) <= CoreDatOutxD; DmaSelxSN(XferByteCntxDP) <= '1'; -- if we write the last byte (end of buffer or end of fifo or end of dma len) address or we have a don't inc -- transfer we create a whishbone cycle if XferByteCntxDP = 3 or IncDestAdrFlgxSP = '0' or DmaLenxDP = 1 or OutFIFOLenxD = 0 then MaCycxSN <= '1'; MaStbxSN <= '1'; end if; end if; end if; end if; end if; -- wait for an ack or err from the slave if MaAckxSI = '1' then -- transfer is done, deassert signals MaCycxSN <= '0'; MaStbxSN <= '0'; DmaSelxSN <= (others => '0'); -- reset sel signals for next transfer if XferByteCntxDP = 4 then XferByteCntxDN <= 0; -- inc destination address to the next word if IncDestAdrFlgxSP = '1' then DmaDestAdrxDN <= std_logic_vector(to_unsigned(to_integer(unsigned(DmaDestAdrxDP))+4, 32)); end if; end if; end if; if MaErrxSI = '1' then -- transfer is done, deassert signals MaCycxSN <= '0'; MaStbxSN <= '0'; -- an whishbone error occured, abort dma transfer DmaLenxDN <= 0; DmaErrFlgxSN <= '1'; end if; if ClearIntFlagsxSP = '1' then DmaErrFlgxSN <= '0'; end if; end process DmaPrcs; MaCycxSO <= MaCycxSP; MaStbxSO <= MaStbxSP; MaSelxDO <= DmaSelxSP; MaDatxDO <= DmaDataOutxDP; MaAdrxDO <= DmaDestAdrxDP; MaWexSO <= '1'; -- we don't do any reads on the dma interface -- registers process (ClkxCI) begin if ClkxCI'event and ClkxCI = '1' then -- rising clock edge if RstxRI = '1' then RstCorexSP <= '1'; FlushxSP <= '0'; FlushCorexSP <= '0'; ClearIntFlagsxSP <= '0'; InFIFOEmptyFlgxSP <= '0'; InFIFOFullFlgxSP <= '0'; OutFIFOEmptyFlgxSP <= '0'; OutFIFOFullFlgxSP <= '0'; IEInFIFOEmptyxSP <= '0'; IEInFIFOFullxSP <= '0'; IEOutFIFOEmptyxSP <= '0'; IEOutFIFOFullxSP <= '0'; IEDmaErrxSP <= '0'; IECoreDonexSP <= '0'; IRQxSP <= '0'; InFIFOEmptyThrxDP <= (others => '0'); InFIFOFullThrxDP <= (others => '1'); OutFIFOEmptyThrxDP <= (others => '0'); OutFIFOFullThrxDP <= (others => '1'); IncDestAdrFlgxSP <= '0'; DmaErrFlgxSP <= '0'; DmaBusyxSP <= '0'; DmaDestAdrxDP <= (others => '0'); XferByteCntxDP <= 0; DmaLenxDP <= 0; DmaDataOutxDP <= (others => '0'); DmaSelxSP <= (others => '0'); MaCycxSP <= '0'; MaStbxSP <= '0'; else RstCorexSP <= RstCorexSN; FlushxSP <= FlushxSN; FlushCorexSP <= FlushCorexSN; ClearIntFlagsxSP <= ClearIntFlagsxSN; InFIFOEmptyFlgxSP <= InFIFOEmptyFlgxSN; InFIFOFullFlgxSP <= InFIFOFullFlgxSN; OutFIFOEmptyFlgxSP <= OutFIFOEmptyFlgxSN; OutFIFOFullFlgxSP <= OutFIFOFullFlgxSN; IEInFIFOEmptyxSP <= IEInFIFOEmptyxSN; IEInFIFOFullxSP <= IEInFIFOFullxSN; IEOutFIFOEmptyxSP <= IEOutFIFOEmptyxSN; IEOutFIFOFullxSP <= IEOutFIFOFullxSN; IEDmaErrxSP <= IEDmaErrxSN; IECoreDonexSP <= IECoreDonexSN; IRQxSP <= IRQxSN; InFIFOEmptyThrxDP <= InFIFOEmptyThrxDN; InFIFOFullThrxDP <= InFIFOFullThrxDN; OutFIFOEmptyThrxDP <= OutFIFOEmptyThrxDN; OutFIFOFullThrxDP <= OutFIFOFullThrxDN; IncDestAdrFlgxSP <= IncDestAdrFlgxSN; DmaErrFlgxSP <= DmaErrFlgxSN; DmaBusyxSP <= DmaBusyxSP; DmaDestAdrxDP <= DmaDestAdrxDN; XferByteCntxDP <= XferByteCntxDN; DmaLenxDP <= DmaLenxDN; DmaDataOutxDP <= DmaDataOutxDN; DmaSelxSP <= DmaSelxSN; MaCycxSP <= MaCycxSN; MaStbxSP <= MaStbxSN; end if; end if; end process; -- input data FIFO buffer InputFIFOInst : InputFIFO port map ( ClkxCI => ClkxCI, RstxRI => RstCorexSP, DInxDI => SlDatxDI, WExSI => WeInFIFOxS, StopOutputxSI => CoreBusyxS, BusyxSO => FIFOBusyxS, DOutxDO => CoreDatInxD, OutStrobexSO => CoreStbxS, LengthxDO => InFIFOLenxD); LZRWcompressorInst : LZRWcompressor port map ( ClkxCI => ClkxCI, RstxRI => RstCorexSP, DataInxDI => CoreDatInxD, StrobexSI => CoreStbxS, FlushBufxSI => FlushCorexSP, BusyxSO => CoreBusyxS, DonexSO => CoreDonexS, BufOutxDO => CoreDatOutxD, OutputValidxSO => CoreOutValidxS, RdStrobexSI => CoreRdStbxS, LengthxDO => OutFIFOLenxD); end Behavioral;
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd) -- Written by Gandhi Puvvada -- date of last rivision: 7/23/2008 -- -- A package file to define the instruction stream to be placed in the instr_cache. -- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module. -- We will use several files similar to this containining different instruction streams. -- The package name will remain the same, namely instr_stream_pkg. -- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd -- to say mult_test_stream_instr_stream_pkg.vhd. -- Depending on which instr_stream_pkg file was analysed/compiled most recently, -- that stream will be used for simulation/synthesis. ---------------------------------------------------------- library std, ieee; use ieee.std_logic_1164.all; package instr_stream_pkg is constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache -- type declarations type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0); --------------------------------------------------- --------------------------------------------------- -- $0 : 0 -- $1 : 1 -- $2 : 2 -- $3 : 3 -- $4 : 4 -- $5 : 5 -- $6 : F0 -- $29: contains fixed bottom of stack for $31 values -- The program calculates factorial of the number n -- addi $4, $0, n ---put factorial candidate in $4 -- addi $3, $0, n ---put factorial candidate in $3 -- slt $5, $4, $2 ---check if no. is zero or one -- bne $5, $1, skiptwo ---go ahead if no. is not 0 or 1 -- add $5, $1, $0 ---no. is 0 or 1, ans is 1 -- jump exit1 --- exit the code. $5 has final ans. -- skiptwo: jal subroutine ---calculate factorial. goto function. -- add $5, $3, $0 ---store final ans. in $5 -- exit1: jr $6 ---jump to exit -- subroutine: -- addi $29, $29, -4 --decrement address -- sw $31,0($29) --put contents of $31 into location pointed by $29 -- sub $4, $4, $1 ---$4=$4 - 1 -- mul $3, $3, $4 ---$3=$3 * $4 -- beq $1, $4, outofloop ---check if $4 has reached 1 -- jal subroutine; --- if $4 /= 1, do 1 more iteration -- outofloop: lw $31,0($29) -- addi $29, $29, 4 -- jr $31 ---start exiting the loop --($6): -- sw $5, 0($29) -- this sw stores final ans to mem -- add $4,$2,$2 -- load 4 into $4 -- lw $4, 0($4) -- add large latency in order to stop completion -- add $4, $4, $4 -- add $4, $4, $4 -- add $4, $4, $4 -- add $4, $4, $4 -- jr $4 --($4): -- exit --- EXPECTED RESULT---- -- the stream calculates factorial 8 and puts it in $5 -- $5 is mapped to physical reg 37 -- Physical register 37 should be 40320 (d) = 9D80 (H) --------------------------------------------------- --------------------------------------------------- signal mem : mem_type := ( X"14A10002_0082282A_20030008_20040008", -- Loc 0C, 08, 04, 00 bne_slt_addi_addi X"00602820_0C000009_08000008_00202820", -- Loc 1C, 18, 14, 10 add_jal_jump_add X"00812022_AFBF0000_23BDFFFC_08000020", -- Loc 2C, 28, 24, 20 sub_sw_addi_jump X"00000020_00000020_10240005_00641819", -- Loc 3C, 38, 34, 30 nop_nop_beq_mul X"00000020_0C000009_00000020_00000020", -- Loc 4C, 48, 44, 40 nop_jal_nop_nop X"8FBF0000_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50 lw_nop_nop_nop X"00000020_AC0C0020_03E00008_23BD0004", -- Loc 6C, 68, 64, 60 jr_addi X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70 X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80 X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90 X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0 X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0 X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0 X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0 X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0 X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0 X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100 X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110 X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120 X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130 X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140 X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150 X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160 X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170 X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180 X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190 X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0 X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0 X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0 X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0 X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0 X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0 X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200 X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221 X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220 X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230 X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240 X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250 X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260 X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270 X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280 X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290 X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0 X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0 X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0 X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0 X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0 X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0 X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300 X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331 X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320 X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330 X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340 X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350 X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360 X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370 X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380 X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390 X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0 X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0 -- the last 16 instructions are looping ump instructions X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0 X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0 X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0 X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0 ) ; -- the last 16 instructions are looping jump instructions -- of the type: loop: j loop -- This is to make sure that neither instruction fetching -- nor instruction execution proceeds beyond the end of this memory. -- Loc 3C0 -- 080000F0 => J 240 -- Loc 3C4 -- 080000F1 => J 241 -- Loc 3C8 -- 080000F2 => J 242 -- Loc 3CC -- 080000F3 => J 243 -- -- Loc 3D0 -- 080000F4 => J 244 -- Loc 3D4 -- 080000F5 => J 245 -- Loc 3D8 -- 080000F6 => J 246 -- Loc 3DC -- 080000F7 => J 247 -- -- Loc 3E0 -- 080000F8 => J 248 -- Loc 3E4 -- 080000F9 => J 249 -- Loc 3E8 -- 080000FA => J 250 -- Loc 3EC -- 080000FB => J 251 -- -- Loc 3F0 -- 080000FC => J 252 -- Loc 3F4 -- 080000FD => J 253 -- Loc 3F8 -- 080000FE => J 254 -- Loc 3FC -- 080000FF => J 255 end package instr_stream_pkg; -- -- No need for s package body here -- package body instr_stream_pkg is -- -- end package body instr_stream_pkg;
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd) -- Written by Gandhi Puvvada -- date of last rivision: 7/23/2008 -- -- A package file to define the instruction stream to be placed in the instr_cache. -- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module. -- We will use several files similar to this containining different instruction streams. -- The package name will remain the same, namely instr_stream_pkg. -- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd -- to say mult_test_stream_instr_stream_pkg.vhd. -- Depending on which instr_stream_pkg file was analysed/compiled most recently, -- that stream will be used for simulation/synthesis. ---------------------------------------------------------- library std, ieee; use ieee.std_logic_1164.all; package instr_stream_pkg is constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache -- type declarations type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0); --------------------------------------------------- --------------------------------------------------- -- $0 : 0 -- $1 : 1 -- $2 : 2 -- $3 : 3 -- $4 : 4 -- $5 : 5 -- $6 : F0 -- $29: contains fixed bottom of stack for $31 values -- The program calculates factorial of the number n -- addi $4, $0, n ---put factorial candidate in $4 -- addi $3, $0, n ---put factorial candidate in $3 -- slt $5, $4, $2 ---check if no. is zero or one -- bne $5, $1, skiptwo ---go ahead if no. is not 0 or 1 -- add $5, $1, $0 ---no. is 0 or 1, ans is 1 -- jump exit1 --- exit the code. $5 has final ans. -- skiptwo: jal subroutine ---calculate factorial. goto function. -- add $5, $3, $0 ---store final ans. in $5 -- exit1: jr $6 ---jump to exit -- subroutine: -- addi $29, $29, -4 --decrement address -- sw $31,0($29) --put contents of $31 into location pointed by $29 -- sub $4, $4, $1 ---$4=$4 - 1 -- mul $3, $3, $4 ---$3=$3 * $4 -- beq $1, $4, outofloop ---check if $4 has reached 1 -- jal subroutine; --- if $4 /= 1, do 1 more iteration -- outofloop: lw $31,0($29) -- addi $29, $29, 4 -- jr $31 ---start exiting the loop --($6): -- sw $5, 0($29) -- this sw stores final ans to mem -- add $4,$2,$2 -- load 4 into $4 -- lw $4, 0($4) -- add large latency in order to stop completion -- add $4, $4, $4 -- add $4, $4, $4 -- add $4, $4, $4 -- add $4, $4, $4 -- jr $4 --($4): -- exit --- EXPECTED RESULT---- -- the stream calculates factorial 8 and puts it in $5 -- $5 is mapped to physical reg 37 -- Physical register 37 should be 40320 (d) = 9D80 (H) --------------------------------------------------- --------------------------------------------------- signal mem : mem_type := ( X"14A10002_0082282A_20030008_20040008", -- Loc 0C, 08, 04, 00 bne_slt_addi_addi X"00602820_0C000009_08000008_00202820", -- Loc 1C, 18, 14, 10 add_jal_jump_add X"00812022_AFBF0000_23BDFFFC_08000020", -- Loc 2C, 28, 24, 20 sub_sw_addi_jump X"00000020_00000020_10240005_00641819", -- Loc 3C, 38, 34, 30 nop_nop_beq_mul X"00000020_0C000009_00000020_00000020", -- Loc 4C, 48, 44, 40 nop_jal_nop_nop X"8FBF0000_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50 lw_nop_nop_nop X"00000020_AC0C0020_03E00008_23BD0004", -- Loc 6C, 68, 64, 60 jr_addi X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70 X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80 X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90 X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0 X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0 X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0 X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0 X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0 X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0 X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100 X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110 X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120 X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130 X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140 X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150 X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160 X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170 X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180 X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190 X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0 X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0 X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0 X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0 X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0 X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0 X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200 X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221 X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220 X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230 X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240 X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250 X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260 X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270 X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280 X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290 X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0 X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0 X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0 X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0 X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0 X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0 X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300 X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331 X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320 X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330 X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340 X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350 X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360 X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370 X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380 X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390 X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0 X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0 -- the last 16 instructions are looping ump instructions X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0 X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0 X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0 X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0 ) ; -- the last 16 instructions are looping jump instructions -- of the type: loop: j loop -- This is to make sure that neither instruction fetching -- nor instruction execution proceeds beyond the end of this memory. -- Loc 3C0 -- 080000F0 => J 240 -- Loc 3C4 -- 080000F1 => J 241 -- Loc 3C8 -- 080000F2 => J 242 -- Loc 3CC -- 080000F3 => J 243 -- -- Loc 3D0 -- 080000F4 => J 244 -- Loc 3D4 -- 080000F5 => J 245 -- Loc 3D8 -- 080000F6 => J 246 -- Loc 3DC -- 080000F7 => J 247 -- -- Loc 3E0 -- 080000F8 => J 248 -- Loc 3E4 -- 080000F9 => J 249 -- Loc 3E8 -- 080000FA => J 250 -- Loc 3EC -- 080000FB => J 251 -- -- Loc 3F0 -- 080000FC => J 252 -- Loc 3F4 -- 080000FD => J 253 -- Loc 3F8 -- 080000FE => J 254 -- Loc 3FC -- 080000FF => J 255 end package instr_stream_pkg; -- -- No need for s package body here -- package body instr_stream_pkg is -- -- end package body instr_stream_pkg;
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd) -- Written by Gandhi Puvvada -- date of last rivision: 7/23/2008 -- -- A package file to define the instruction stream to be placed in the instr_cache. -- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module. -- We will use several files similar to this containining different instruction streams. -- The package name will remain the same, namely instr_stream_pkg. -- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd -- to say mult_test_stream_instr_stream_pkg.vhd. -- Depending on which instr_stream_pkg file was analysed/compiled most recently, -- that stream will be used for simulation/synthesis. ---------------------------------------------------------- library std, ieee; use ieee.std_logic_1164.all; package instr_stream_pkg is constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache -- type declarations type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0); --------------------------------------------------- --------------------------------------------------- -- $0 : 0 -- $1 : 1 -- $2 : 2 -- $3 : 3 -- $4 : 4 -- $5 : 5 -- $6 : F0 -- $29: contains fixed bottom of stack for $31 values -- The program calculates factorial of the number n -- addi $4, $0, n ---put factorial candidate in $4 -- addi $3, $0, n ---put factorial candidate in $3 -- slt $5, $4, $2 ---check if no. is zero or one -- bne $5, $1, skiptwo ---go ahead if no. is not 0 or 1 -- add $5, $1, $0 ---no. is 0 or 1, ans is 1 -- jump exit1 --- exit the code. $5 has final ans. -- skiptwo: jal subroutine ---calculate factorial. goto function. -- add $5, $3, $0 ---store final ans. in $5 -- exit1: jr $6 ---jump to exit -- subroutine: -- addi $29, $29, -4 --decrement address -- sw $31,0($29) --put contents of $31 into location pointed by $29 -- sub $4, $4, $1 ---$4=$4 - 1 -- mul $3, $3, $4 ---$3=$3 * $4 -- beq $1, $4, outofloop ---check if $4 has reached 1 -- jal subroutine; --- if $4 /= 1, do 1 more iteration -- outofloop: lw $31,0($29) -- addi $29, $29, 4 -- jr $31 ---start exiting the loop --($6): -- sw $5, 0($29) -- this sw stores final ans to mem -- add $4,$2,$2 -- load 4 into $4 -- lw $4, 0($4) -- add large latency in order to stop completion -- add $4, $4, $4 -- add $4, $4, $4 -- add $4, $4, $4 -- add $4, $4, $4 -- jr $4 --($4): -- exit --- EXPECTED RESULT---- -- the stream calculates factorial 8 and puts it in $5 -- $5 is mapped to physical reg 37 -- Physical register 37 should be 40320 (d) = 9D80 (H) --------------------------------------------------- --------------------------------------------------- signal mem : mem_type := ( X"14A10002_0082282A_20030008_20040008", -- Loc 0C, 08, 04, 00 bne_slt_addi_addi X"00602820_0C000009_08000008_00202820", -- Loc 1C, 18, 14, 10 add_jal_jump_add X"00812022_AFBF0000_23BDFFFC_08000020", -- Loc 2C, 28, 24, 20 sub_sw_addi_jump X"00000020_00000020_10240005_00641819", -- Loc 3C, 38, 34, 30 nop_nop_beq_mul X"00000020_0C000009_00000020_00000020", -- Loc 4C, 48, 44, 40 nop_jal_nop_nop X"8FBF0000_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50 lw_nop_nop_nop X"00000020_AC0C0020_03E00008_23BD0004", -- Loc 6C, 68, 64, 60 jr_addi X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70 X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80 X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90 X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0 X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0 X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0 X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0 X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0 X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0 X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100 X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110 X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120 X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130 X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140 X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150 X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160 X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170 X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180 X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190 X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0 X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0 X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0 X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0 X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0 X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0 X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200 X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221 X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220 X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230 X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240 X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250 X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260 X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270 X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280 X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290 X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0 X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0 X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0 X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0 X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0 X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0 X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300 X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331 X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320 X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330 X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340 X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350 X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360 X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370 X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380 X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390 X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0 X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0 -- the last 16 instructions are looping ump instructions X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0 X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0 X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0 X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0 ) ; -- the last 16 instructions are looping jump instructions -- of the type: loop: j loop -- This is to make sure that neither instruction fetching -- nor instruction execution proceeds beyond the end of this memory. -- Loc 3C0 -- 080000F0 => J 240 -- Loc 3C4 -- 080000F1 => J 241 -- Loc 3C8 -- 080000F2 => J 242 -- Loc 3CC -- 080000F3 => J 243 -- -- Loc 3D0 -- 080000F4 => J 244 -- Loc 3D4 -- 080000F5 => J 245 -- Loc 3D8 -- 080000F6 => J 246 -- Loc 3DC -- 080000F7 => J 247 -- -- Loc 3E0 -- 080000F8 => J 248 -- Loc 3E4 -- 080000F9 => J 249 -- Loc 3E8 -- 080000FA => J 250 -- Loc 3EC -- 080000FB => J 251 -- -- Loc 3F0 -- 080000FC => J 252 -- Loc 3F4 -- 080000FD => J 253 -- Loc 3F8 -- 080000FE => J 254 -- Loc 3FC -- 080000FF => J 255 end package instr_stream_pkg; -- -- No need for s package body here -- package body instr_stream_pkg is -- -- end package body instr_stream_pkg;
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:31:40) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.NUMERIC_STD.all; ENTITY ewf_spea2_entity IS PORT ( reset, clk: IN std_logic; input1, input2: IN unsigned(0 TO 30); output1, output2, output3, output4, output5: OUT unsigned(0 TO 31)); END ewf_spea2_entity; ARCHITECTURE ewf_spea2_description OF ewf_spea2_entity IS SIGNAL current_state : unsigned(0 TO 7) := "00000000"; SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000"; SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000"; SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000"; SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000"; SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000"; SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000"; BEGIN moore_machine: PROCESS(clk, reset) BEGIN IF reset = '0' THEN current_state <= "00000000"; ELSIF clk = '1' AND clk'event THEN IF current_state < 4 THEN current_state <= current_state + 1; END IF; END IF; END PROCESS moore_machine; operations: PROCESS(current_state) BEGIN CASE current_state IS WHEN "00000001" => register1 := input1 + 1; register2 := input2 + 2; WHEN "00000010" => register3 := register1 + 4; WHEN "00000011" => register4 := register3 + 6; WHEN "00000100" => register4 := register2 + register4; WHEN "00000101" => register5 := register4 * 8; WHEN "00000110" => register5 := register3 + register5; WHEN "00000111" => register3 := register3 + register5; register6 := register4 * 10; WHEN "00001000" => register3 := register3 * 12; register6 := register2 + register6; register4 := register4 + register5; WHEN "00001001" => output1 <= register6 + register4; register2 := register2 + register6; WHEN "00001010" => register2 := register2 * 15; register3 := register1 + register3; WHEN "00001011" => register1 := register1 + register3; WHEN "00001100" => register1 := register1 * 17; WHEN "00001101" => register1 := register1 + 19; register4 := register5 + register3; WHEN "00001110" => output2 <= register3 + register1; register1 := register4 + 22; WHEN "00001111" => register3 := register1 * 24; WHEN "00010000" => register3 := register3 + 26; WHEN "00010001" => output3 <= register1 + register3; register1 := register2 + 29; WHEN "00010010" => register2 := register1 + 31; WHEN "00010011" => register2 := register2 * 33; WHEN "00010100" => output4 <= register1 + register2; register1 := register6 + register1; WHEN "00010101" => register1 := register1 + 36; WHEN "00010110" => register2 := register1 * 38; WHEN "00010111" => register2 := register2 + 40; WHEN "00011000" => output5 <= register1 + register2; WHEN OTHERS => NULL; END CASE; END PROCESS operations; END ewf_spea2_description;
-- EMACS settings: -*- tab-width:2 -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ------------------------------------------------------------------------------- -- Authors: Patrick Lehmann -- -- Description: Testbench for stat_Maximum. -- ------------------------------------------------------------------------------- -- Copyright 2007-2015 Technische Universität Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library PoC; use poC.utils.all; use poC.vectors.all; entity stat_Maximum_tb is end entity; architecture tb of stat_Maximum_tb is -- component generics constant VALUES : T_NATVEC := ( 113, 106, 126, 239, 146, 72, 51, 210, 44, 56, 10, 126, 7, 7, 22, 18, 128, 217, 106, 210, 58, 71, 213, 206, 169, 213, 90, 27, 166, 159, 83, 116, 246, 208, 105, 64, 112, 12, 110, 10, 5, 100, 12, 231, 191, 235, 27, 143, 162, 178, 136, 149, 92, 221, 122, 44, 143, 169, 72, 182, 232, 26, 46, 135, 223, 144, 129, 48, 148, 208, 156, 119, 109, 98, 207, 208, 62, 232, 17, 183, 189, 197, 115, 237, 25, 183, 27, 27, 89, 64, 170, 192, 189, 177, 28, 228, 56, 127, 10, 49, 108, 229, 244, 204, 25, 20, 42, 243, 16, 163, 232, 161, 154, 139, 243, 38, 160, 59, 113, 42, 120, 104, 208, 87, 40, 213, 179, 181, 73, 228, 155, 184, 224, 218, 77, 210, 202, 161, 215, 7, 143, 34, 13, 175, 81, 12, 40, 53, 184, 240, 71, 247, 17, 218, 179, 7, 23, 159, 166, 61, 90, 111, 172, 37, 11, 50, 186, 186, 64, 36, 85, 249, 93, 108, 148, 89, 93, 35, 7, 30, 175, 129, 247, 83, 160, 157, 170, 9, 41, 73, 189, 45, 244, 157, 166, 35, 111, 226, 167, 34, 76, 104, 239, 151, 157, 71, 156, 159, 72, 93, 163, 237, 153, 139, 135, 211, 113, 92, 126, 103, 130, 180, 147, 240, 96, 42, 7, 185, 191, 115, 227, 117, 118, 224, 204, 74, 140, 98, 176, 92, 3, 13, 187, 198, 160, 201, 141, 108, 24, 205, 171, 22, 102, 66, 153, 146, 206, 248, 58, 117, 67, 220, 217, 206, 115, 48, 122, 179, 184, 63, 74, 18, 166, 37, 103, 119, 242, 198, 82, 144, 151, 149, 164, 235, 193, 207, 18, 55, 74, 61, 118, 141, 42, 61, 28, 32, 46, 230, 85, 114, 82, 212, 173, 210, 134, 156, 106, 67, 212, 36, 153, 10, 168, 164, 216, 168, 59, 231, 15, 157, 33, 69, 107, 126, 195, 182, 225, 107, 12, 73, 76, 15, 116, 218, 64, 188, 225, 203, 104, 40, 104, 200, 92, 40, 158, 110, 222, 128, 95, 110, 223, 64, 218, 178, 84, 16, 108, 50, 18, 202, 180, 249, 58, 142, 210, 141, 144, 200, 102, 30, 192, 106, 130, 224, 56, 82, 226, 69, 218, 88, 209, 100, 15, 152, 100, 14, 46, 188, 136, 51, 83, 178, 188, 152, 110, 105, 145, 199, 80, 19, 215, 25, 29, 67, 167, 119, 184, 243, 124, 5, 39, 41, 81, 179, 242, 83, 236, 155, 45, 198, 97, 206, 67, 54, 197, 17, 168, 227, 117, 200, 186, 29, 239, 201, 122, 187, 74, 197, 234, 230, 80, 53, 66, 133, 14, 44, 99, 11, 160, 29, 118, 239, 157, 131, 172, 12, 207, 224, 119, 153, 201, 206, 128, 173, 69, 12, 51, 129, 60, 57, 12, 42, 171, 64, 121, 46, 143, 184, 42, 156, 167, 160, 70, 91, 85, 196, 122, 110, 32, 113, 229, 99, 81, 84, 32, 123, 174, 142, 66, 5, 242, 220, 200, 105, 20, 79, 71, 95, 13, 128, 119, 26 ); type T_RESULT is record Maximum : NATURAL; Count : POSITIVE; end record; type T_RESULT_VECTOR is array(NATURAL range <>) of T_RESULT; constant RESULT : T_RESULT_VECTOR := ( (Maximum => 249, Count => 2), (Maximum => 248, Count => 1), (Maximum => 247, Count => 2), (Maximum => 246, Count => 1), (Maximum => 244, Count => 2), (Maximum => 243, Count => 3), (Maximum => 242, Count => 3), (Maximum => 240, Count => 2) ); constant DEPTH : POSITIVE := RESULT'length; constant DATA_BITS : POSITIVE := 8; constant COUNTER_BITS : POSITIVE := 4; -- component ports signal Clock : STD_LOGIC := '1'; signal Reset : STD_LOGIC := '0'; signal Enable : STD_LOGIC := '0'; signal DataIn : STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); signal Valids : STD_LOGIC_VECTOR(DEPTH - 1 downto 0); signal Maximums : T_SLM(DEPTH - 1 downto 0, DATA_BITS - 1 downto 0); signal Counts : T_SLM(DEPTH - 1 downto 0, COUNTER_BITS - 1 downto 0); signal Maximums_slvv : T_SLVV_8(DEPTH - 1 downto 0); signal Counts_slvv : T_SLVV_4(DEPTH - 1 downto 0); begin -- component instantiation DUT: entity PoC.stat_Maximum generic map ( DEPTH => DEPTH, DATA_BITS => DATA_BITS, COUNTER_BITS => COUNTER_BITS ) port map ( Clock => Clock, Reset => Reset, Enable => Enable, DataIn => DataIn, Valids => Valids, Maximums => Maximums, Counts => Counts ); Maximums_slvv <= to_slvv_8(Maximums); Counts_slvv <= to_slvv_4(Counts); process procedure cycle is begin Clock <= '1'; wait for 5 ns; Clock <= '0'; wait for 5 ns; end cycle; variable good : BOOLEAN; begin cycle; Reset <= '1'; cycle; Reset <= '0'; cycle; cycle; Enable <= '1'; for i in VALUES'range loop --Enable <= to_sl(VALUES(i) /= 35); DataIn <= to_slv(VALUES(i), DataIn'length); cycle; end loop; cycle; -- test result after all cycles good := (slv_and(Valids) = '1'); for i in RESULT'range loop good := good and (RESULT(i).Maximum = unsigned(Maximums_slvv(i))) and (RESULT(i).Count = unsigned(Counts_slvv(i))); end loop; assert (good = TRUE) report "Test failed." severity note; assert (good = FALSE) report "Test passed." severity note; wait; end process; end;
-- EMACS settings: -*- tab-width:2 -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ------------------------------------------------------------------------------- -- Authors: Patrick Lehmann -- -- Description: Testbench for stat_Maximum. -- ------------------------------------------------------------------------------- -- Copyright 2007-2015 Technische Universität Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library PoC; use poC.utils.all; use poC.vectors.all; entity stat_Maximum_tb is end entity; architecture tb of stat_Maximum_tb is -- component generics constant VALUES : T_NATVEC := ( 113, 106, 126, 239, 146, 72, 51, 210, 44, 56, 10, 126, 7, 7, 22, 18, 128, 217, 106, 210, 58, 71, 213, 206, 169, 213, 90, 27, 166, 159, 83, 116, 246, 208, 105, 64, 112, 12, 110, 10, 5, 100, 12, 231, 191, 235, 27, 143, 162, 178, 136, 149, 92, 221, 122, 44, 143, 169, 72, 182, 232, 26, 46, 135, 223, 144, 129, 48, 148, 208, 156, 119, 109, 98, 207, 208, 62, 232, 17, 183, 189, 197, 115, 237, 25, 183, 27, 27, 89, 64, 170, 192, 189, 177, 28, 228, 56, 127, 10, 49, 108, 229, 244, 204, 25, 20, 42, 243, 16, 163, 232, 161, 154, 139, 243, 38, 160, 59, 113, 42, 120, 104, 208, 87, 40, 213, 179, 181, 73, 228, 155, 184, 224, 218, 77, 210, 202, 161, 215, 7, 143, 34, 13, 175, 81, 12, 40, 53, 184, 240, 71, 247, 17, 218, 179, 7, 23, 159, 166, 61, 90, 111, 172, 37, 11, 50, 186, 186, 64, 36, 85, 249, 93, 108, 148, 89, 93, 35, 7, 30, 175, 129, 247, 83, 160, 157, 170, 9, 41, 73, 189, 45, 244, 157, 166, 35, 111, 226, 167, 34, 76, 104, 239, 151, 157, 71, 156, 159, 72, 93, 163, 237, 153, 139, 135, 211, 113, 92, 126, 103, 130, 180, 147, 240, 96, 42, 7, 185, 191, 115, 227, 117, 118, 224, 204, 74, 140, 98, 176, 92, 3, 13, 187, 198, 160, 201, 141, 108, 24, 205, 171, 22, 102, 66, 153, 146, 206, 248, 58, 117, 67, 220, 217, 206, 115, 48, 122, 179, 184, 63, 74, 18, 166, 37, 103, 119, 242, 198, 82, 144, 151, 149, 164, 235, 193, 207, 18, 55, 74, 61, 118, 141, 42, 61, 28, 32, 46, 230, 85, 114, 82, 212, 173, 210, 134, 156, 106, 67, 212, 36, 153, 10, 168, 164, 216, 168, 59, 231, 15, 157, 33, 69, 107, 126, 195, 182, 225, 107, 12, 73, 76, 15, 116, 218, 64, 188, 225, 203, 104, 40, 104, 200, 92, 40, 158, 110, 222, 128, 95, 110, 223, 64, 218, 178, 84, 16, 108, 50, 18, 202, 180, 249, 58, 142, 210, 141, 144, 200, 102, 30, 192, 106, 130, 224, 56, 82, 226, 69, 218, 88, 209, 100, 15, 152, 100, 14, 46, 188, 136, 51, 83, 178, 188, 152, 110, 105, 145, 199, 80, 19, 215, 25, 29, 67, 167, 119, 184, 243, 124, 5, 39, 41, 81, 179, 242, 83, 236, 155, 45, 198, 97, 206, 67, 54, 197, 17, 168, 227, 117, 200, 186, 29, 239, 201, 122, 187, 74, 197, 234, 230, 80, 53, 66, 133, 14, 44, 99, 11, 160, 29, 118, 239, 157, 131, 172, 12, 207, 224, 119, 153, 201, 206, 128, 173, 69, 12, 51, 129, 60, 57, 12, 42, 171, 64, 121, 46, 143, 184, 42, 156, 167, 160, 70, 91, 85, 196, 122, 110, 32, 113, 229, 99, 81, 84, 32, 123, 174, 142, 66, 5, 242, 220, 200, 105, 20, 79, 71, 95, 13, 128, 119, 26 ); type T_RESULT is record Maximum : NATURAL; Count : POSITIVE; end record; type T_RESULT_VECTOR is array(NATURAL range <>) of T_RESULT; constant RESULT : T_RESULT_VECTOR := ( (Maximum => 249, Count => 2), (Maximum => 248, Count => 1), (Maximum => 247, Count => 2), (Maximum => 246, Count => 1), (Maximum => 244, Count => 2), (Maximum => 243, Count => 3), (Maximum => 242, Count => 3), (Maximum => 240, Count => 2) ); constant DEPTH : POSITIVE := RESULT'length; constant DATA_BITS : POSITIVE := 8; constant COUNTER_BITS : POSITIVE := 4; -- component ports signal Clock : STD_LOGIC := '1'; signal Reset : STD_LOGIC := '0'; signal Enable : STD_LOGIC := '0'; signal DataIn : STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); signal Valids : STD_LOGIC_VECTOR(DEPTH - 1 downto 0); signal Maximums : T_SLM(DEPTH - 1 downto 0, DATA_BITS - 1 downto 0); signal Counts : T_SLM(DEPTH - 1 downto 0, COUNTER_BITS - 1 downto 0); signal Maximums_slvv : T_SLVV_8(DEPTH - 1 downto 0); signal Counts_slvv : T_SLVV_4(DEPTH - 1 downto 0); begin -- component instantiation DUT: entity PoC.stat_Maximum generic map ( DEPTH => DEPTH, DATA_BITS => DATA_BITS, COUNTER_BITS => COUNTER_BITS ) port map ( Clock => Clock, Reset => Reset, Enable => Enable, DataIn => DataIn, Valids => Valids, Maximums => Maximums, Counts => Counts ); Maximums_slvv <= to_slvv_8(Maximums); Counts_slvv <= to_slvv_4(Counts); process procedure cycle is begin Clock <= '1'; wait for 5 ns; Clock <= '0'; wait for 5 ns; end cycle; variable good : BOOLEAN; begin cycle; Reset <= '1'; cycle; Reset <= '0'; cycle; cycle; Enable <= '1'; for i in VALUES'range loop --Enable <= to_sl(VALUES(i) /= 35); DataIn <= to_slv(VALUES(i), DataIn'length); cycle; end loop; cycle; -- test result after all cycles good := (slv_and(Valids) = '1'); for i in RESULT'range loop good := good and (RESULT(i).Maximum = unsigned(Maximums_slvv(i))) and (RESULT(i).Count = unsigned(Counts_slvv(i))); end loop; assert (good = TRUE) report "Test failed." severity note; assert (good = FALSE) report "Test passed." severity note; wait; end process; end;
entity sub is port ( x : in integer; y : out integer ); end entity; architecture test of sub is begin process is begin if x'active then -- NULL nets array here y <= x + 1; end if; wait; end process; end architecture; ------------------------------------------------------------------------------- entity elab23 is end entity; architecture test of elab23 is signal y : integer; begin sub_i: entity work.sub port map ( x => 0, y => y ); process is begin wait for 1 ns; assert y = integer'low; wait; end process; end architecture;
entity sub is port ( x : in integer; y : out integer ); end entity; architecture test of sub is begin process is begin if x'active then -- NULL nets array here y <= x + 1; end if; wait; end process; end architecture; ------------------------------------------------------------------------------- entity elab23 is end entity; architecture test of elab23 is signal y : integer; begin sub_i: entity work.sub port map ( x => 0, y => y ); process is begin wait for 1 ns; assert y = integer'low; wait; end process; end architecture;
entity sub is port ( x : in integer; y : out integer ); end entity; architecture test of sub is begin process is begin if x'active then -- NULL nets array here y <= x + 1; end if; wait; end process; end architecture; ------------------------------------------------------------------------------- entity elab23 is end entity; architecture test of elab23 is signal y : integer; begin sub_i: entity work.sub port map ( x => 0, y => y ); process is begin wait for 1 ns; assert y = integer'low; wait; end process; end architecture;
entity sub is port ( x : in integer; y : out integer ); end entity; architecture test of sub is begin process is begin if x'active then -- NULL nets array here y <= x + 1; end if; wait; end process; end architecture; ------------------------------------------------------------------------------- entity elab23 is end entity; architecture test of elab23 is signal y : integer; begin sub_i: entity work.sub port map ( x => 0, y => y ); process is begin wait for 1 ns; assert y = integer'low; wait; end process; end architecture;
entity sub is port ( x : in integer; y : out integer ); end entity; architecture test of sub is begin process is begin if x'active then -- NULL nets array here y <= x + 1; end if; wait; end process; end architecture; ------------------------------------------------------------------------------- entity elab23 is end entity; architecture test of elab23 is signal y : integer; begin sub_i: entity work.sub port map ( x => 0, y => y ); process is begin wait for 1 ns; assert y = integer'low; wait; end process; end architecture;
-- ************************************ -- Automatically Generated FSM -- Author :Alborz Sad. -- hw_acc_quicksort -- ************************************ -- request send 6bitOpcode,10bitReseved,16bitparam1 32bit param2(if opcode is push or write) -- response from mb 32bitMblaze_return --API ( User puts the appropirate values into Opcode, Param1, and param2 and return_state, then calls send_request. U can get the value -- returned by mblaze in mb_ret. For load and store into global memory, just simply update addr,data, wren,ren of brams and go to the -- next state. --Example : -- when Q4=> -- opcode_next <= OPCODE_WRITE; -- param1_next <= x"0002"; -- param2_next <= x"BEAF"; -- return_state_next <= Q5; -- next_state <= send_request; -- Request Opcode-6bit Parm1-16bit Param2-32bits Mblaze_ret32bits next_state --push 16 -- value -- return_state --pop 17 -- -- value return_state --Declare 3 num -- -- return_state --read(local variable) 4 addr -- value return_state --write((local variable) 5 addr value -- return_state --call 18 next_pc -- -- return_state --return 19 -- -- next_pc next_pc(mb_ret value) --done 0 ----------------------------------------------------------------- -- --Load(from BRAM) in_array_addr0 <= addr; array_rENA0 <= '1'; next_state <= QUICKSORT_WHILE; -- when QUICKSORT_WHILE => -- right_next <=array_dout0; --Store(into BRAM) in_array_addr0 <= addr; array_dIN0 <= value; array_wENA0 <= (others => '1'); array_rENA0 <= '1'; next_state <=QUICKSORT_SWAP_2; -- -- -- -- -- -- -- -- -- ********************** -- Library inclusions -- ********************** library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -- ********************** -- Entity Definition -- ********************** entity quicksort is port ( array_addr0 : out std_logic_vector(0 to 31); array_dIN0 : out std_logic_vector(0 to 31); array_dOUT0 : in std_logic_vector(0 to 31); array_rENA0 : out std_logic; array_wENA0 : out std_logic_vector( 0 to 3); chan1_channelDataIn : out std_logic_vector(0 to (32 - 1)); chan1_channelDataOut : in std_logic_vector(0 to (32 - 1)); chan1_exists : in std_logic; chan1_full : in std_logic; chan1_channelRead : out std_logic; chan1_channelWrite : out std_logic; clock_sig : in std_logic; reset_sig : in std_logic ); end entity quicksort; -- ************************************************* -- Architecture Definition -- ************************************************** architecture IMPLEMENTATION of quicksort is -- ********************************************************************************************************* -- Type definitions for state signals -- ********************************************************************************************************** type STATE_MACHINE_TYPE is ( reset, idle, decode, send_request, send_request2, wait_for_mblaze, extra1, extra2, --user defined states READ_SORTDATA_1, READ_SORTDATA_2, READ_SORTDATA_3, READ_SORTDATA_4, READ_SORTDATA_5, READ_SORTDATA_6, READ_SORTDATA_7, READ_SORTDATA_8, CALL_QSORT_1, CALL_QSORT_2, CALL_QSORT_3, READ_ARRAY_1, READ_ARRAY_2, READ_ARRAY_3, READ_ARRAY_4, READ_ARRAY_5, READ_ARRAY_6, EXIT_THREAD_1, EXIT_THREAD_2, QUICKSORT_1, QUICKSORT_2, QUICKSORT_3, QUICKSORT_4, QUICKSORT_5, QUICKSORT_6, QUICKSORT_7, QUICKSORT_8, QUICKSORT_9, QUICKSORT_A, QUICKSORT_B, QUICKSORT_DO, QUICKSORT_WHILE_LEFT_0, QUICKSORT_WHILE_LEFT_1, QUICKSORT_WHILE_LEFT_2, QUICKSORT_WHILE_LEFT_3, QUICKSORT_BREAK, QUICKSORT_WHILE_RIGHT_1, QUICKSORT_WHILE_RIGHT_2, QUICKSORT_WHILE_RIGHT_3, QUICKSORT_SWAP_1, QUICKSORT_SWAP_2, QUICKSORT_SWAP_3, QUICKSORT_SWAP_4, QUICKSORT_SWAP_5, QUICKSORT_WHILE, QUICKSORT_CALL_QS_0, QUICKSORT_CALL_QS_1, QUICKSORT_CALL_QS_2, QUICKSORT_CALL_QS_3, QUICKSORT_CALL_QS_4, QUICKSORT_CALL_QS_5, QUICKSORT_CALL_QS_6, QUICKSORT_CALL_QS_7, QUICKSORT_CALL_QS_8, QUICKSORT_CALL_QS_9, QUICKSORT_CALL_QS_A, QUICKSORT_RETURN,A,B,C,D,E,F,G,H,I,J,K ); signal current_state,next_state: STATE_MACHINE_TYPE :=reset; signal return_state, return_state_next : state_machine_type := reset; -- ********************************************************************************************************* -- Constant Definition -- ********************************************************************************************************** constant U_EXIT_THREAD_1 : std_logic_vector(0 to 15) := x"0021"; constant U_QUICKSORT_1 : std_logic_vector(0 to 15) := x"0101"; constant U_QUICKSORT_CALL_QS_6 : std_logic_vector(0 to 15) := x"0171"; constant U_QUICKSORT_RETURN : std_logic_vector(0 to 15) := x"0181"; -- Memory sub-interface specific opcodes constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001"; constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010"; constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011"; constant OPCODE_READ : std_logic_vector(0 to 5) := "000100"; constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101"; -- Function sub-interface specific opcodes constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000"; constant OPCODE_POP : std_logic_vector(0 to 5) := "010001"; constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010"; constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011"; constant Z32 : std_logic_vector(0 to 31) := (others => '0'); -- **************************************************** -- Type definitions for FSM signals -- **************************************************** signal startPtr, startPtr_next : std_logic_vector(0 to 31); signal endPtr, endPtr_next : std_logic_vector(0 to 31); signal leftPtr, leftPtr_next : std_logic_vector(0 to 31); signal rightPtr, rightPtr_next : std_logic_vector(0 to 31); signal left, left_next : std_logic_vector(0 to 31); signal right, right_next : std_logic_vector(0 to 31); signal pivot, pivot_next : std_logic_vector(0 to 31); signal data1, data1_next : std_logic_vector(0 to 31); signal data2, data2_next : std_logic_vector(0 to 31); signal arg1, arg1_next : std_logic_vector(0 to 31); signal arg2, arg2_next : std_logic_vector(0 to 31); signal param1,param1_next :std_logic_vector(0 to 15); signal param2,param2_next :std_logic_vector(0 to 31); signal opcode,opcode_next :std_logic_vector(0 to 5); signal mblaze_ret,mblaze_ret_next :std_logic_vector(0 to 31); -- **************************************************** -- User-defined VHDL Section -- **************************************************** signal in_array_addr0 : std_logic_vector(0 to (32 - 1)); -- Architecture Section begin -- ************************ -- Permanent Connections -- ************************ --array_addr0 <= in_array_addr0(2 to 31) & "00"; --The external memory is organized in this way. array_addr0 <= in_array_addr0; --the address is already adding /subtracting by four in vhdl code. -- ************************ -- BRAM implementations -- ************************ -- **************************************************** -- Process to handle the synchronous portion of an FSM -- **************************************************** FSM_SYNC_PROCESS : process( data1_next, data2_next, arg1_next, arg2_next, param1_next, param2_next, opcode_next, return_state_next, mblaze_ret_next, next_state, clock_sig, reset_sig) is begin if (clock_sig'event and clock_sig = '1') then if (reset_sig = '1') then -- Reset all FSM signals, and enter the initial state data1 <= (others => '0'); data2 <= (others => '0'); arg1 <= (others => '0'); arg2 <= (others => '0'); startPtr <= (others => '0'); endPtr <=(others => '0'); leftPtr <= (others => '0'); rightPtr <= (others => '0'); left <= (others => '0'); right <=(others => '0'); pivot <= (others => '0'); return_state <= reset; param1 <= (others => '0'); param2 <= (others => '0'); opcode <= (others => '0'); mblaze_ret <= (others => '0'); current_state <= reset; else -- Transition to next state data1 <= data1_next; data2 <= data2_next; arg1 <= arg1_next; arg2 <= arg2_next; startPtr <= startPtr_next; endPtr <= endPtr_next; leftPtr <= leftPtr_next; rightPtr <= rightPtr_next; left <= left_next; right <= right_next; pivot <= pivot_next; return_state <= return_state_next; param1 <= param1_next; param2 <= param2_next; opcode <= opcode_next; return_state <=return_state_next; mblaze_ret <= mblaze_ret_next; current_state <= next_state; end if; end if; end process FSM_SYNC_PROCESS; -- ************************************************************************ -- Process to handle the asynchronous (combinational) portion of an FSM -- ************************************************************************ FSM_COMB_PROCESS : process( array_dOUT0, chan1_channelDataOut, chan1_full, chan1_exists, data1, data2, arg1, arg2, param1, param2, opcode, return_state, mblaze_ret, current_state) is begin -- Default signal assignments data1_next <= data1; data2_next <= data2; arg1_next <= arg1; arg2_next <= arg2; return_state_next <= return_state; startPtr_next <= startPtr; endPtr_next <= endPtr; leftPtr_next <= leftPtr; rightPtr_next <= rightPtr; left_next <= left; right_next <= right; pivot_next <= pivot; param1_next <= param1; param2_next <= param2; opcode_next<=opcode; return_state_next <= return_state; mblaze_ret_next <=mblaze_ret; in_array_addr0 <= (others => '0'); array_dIN0 <= (others => '0'); array_rENA0 <= '0'; array_wENA0 <= (others => '0'); chan1_channelDataIn <= (others => '0'); chan1_channelRead <= '0'; chan1_channelWrite <= '0'; next_state <= current_state; -- FSM logic case (current_state) is when send_request=> chan1_channelWrite <= '1'; chan1_channelDataIn <= opcode & "0000000000" &param1; if chan1_full /= '0' then next_state <= send_request; elsif chan1_full = '0' then if (opcode = OPCODE_PUSH or opcode=OPCODE_WRITE) then --so we should send parameter2, which is the value next_state <= send_request2; else next_state <= wait_for_mblaze; end if; end if; when send_request2 => chan1_channelWrite <= '1'; chan1_channelDataIn <= param2; if chan1_full /= '0' then next_state <= send_request2; elsif chan1_full = '0' then next_state <= wait_for_mblaze; end if; when wait_for_mblaze => chan1_channelRead <= '1'; if chan1_exists = '0' then next_state <= wait_for_mblaze; elsif chan1_exists /= '0' then mblaze_ret_next <= chan1_channelDataOut; if (opcode /= OPCODE_RETURN) then next_state <= return_state; else case (chan1_channelDataOut(16 to 31)) is when U_QUICKSORT_CALL_QS_6 => next_state <= QUICKSORT_CALL_QS_6; when U_QUICKSORT_RETURN => next_state <= QUICKSORT_RETURN; when U_EXIT_THREAD_1 => next_state <= EXIT_THREAD_1; when others => next_state <= reset; end case; end if; end if; when reset => next_state <= idle; when idle => if chan1_exists = '0' then next_state <= idle; elsif chan1_exists /= '0' then data1_next <= chan1_channelDataOut; chan1_channelRead <= '1'; next_state <= decode; end if; when decode => arg2_next <= "00000000000000000" & data1(2 to 16); --end address arg1_next <= "00000000000000000" & data1(17 to 31); --start adderss next_state <= READ_SORTDATA_4 ; when READ_SORTDATA_4 => -- 0006 endPtr_next <= arg2; startPtr_next <= arg1; leftPtr_next <= arg1; rightPtr_next <= arg2; -- Declare four local variables to hold start, end, left, right pointers opcode_next <= OPCODE_DECLARE; param1_next <= x"0004"; return_state_next <= READ_SORTDATA_5; next_state <= send_request; when READ_SORTDATA_5 => -- 0007 -- Save the start pointer opcode_next <= OPCODE_WRITE; param1_next <= x"0000"; param2_next <= startPtr; return_state_next <= READ_SORTDATA_6; next_state <= send_request; when READ_SORTDATA_6 => -- 0008 -- Save the end pointer opcode_next <= OPCODE_WRITE; param1_next <= x"0001"; param2_next <= endPtr; return_state_next <= READ_SORTDATA_7; next_state <= send_request; when READ_SORTDATA_7 => -- 0009 -- Save the left pointer opcode_next <= OPCODE_WRITE; param1_next <= x"0002"; param2_next <= leftPtr; return_state_next <= READ_SORTDATA_8; next_state <= send_request; when READ_SORTDATA_8 => -- 000A -- Save the right pointer opcode_next <= OPCODE_WRITE; param1_next <= x"0003"; param2_next <= rightPtr; -- Sort the data! return_state_next <= CALL_QSORT_1; next_state <= send_request; when CALL_QSORT_1 => -- 0011 -- Push the second argument, endPtr; opcode_next <= OPCODE_PUSH; param2_next <= rightPtr; return_state_next <= CALL_QSORT_2; next_state <= send_request; when CALL_QSORT_2 => -- 0012 -- Push the first argument, startPtr; opcode_next <= OPCODE_PUSH; param2_next <= leftPtr; return_state_next <= CALL_QSORT_3; next_state <= send_request; when CALL_QSORT_3 => -- 0013 -- Call quicksort opcode_next <= OPCODE_CALL; param1_next <= U_EXIT_THREAD_1; return_state_next <= QUICKSORT_1; next_state <= send_request; when EXIT_THREAD_1 => -- 0021 opcode_next <= (others => '0'); --means I am done. param1_next <= (others => '0'); return_state_next <= idle; next_state <= send_request; ----------------------------------------------------------------------- -- Quicksort function -- argument 1 - start pointer -- argument 2 - end pointer ----------------------------------------------------------------------- when QUICKSORT_1 => -- 0101 -- Read the first argument opcode_next <= OPCODE_POP; return_state_next <= QUICKSORT_2; next_state <= send_request; when QUICKSORT_2 => -- 0102 startPtr_next <=mblaze_ret; -- Read the second argument opcode_next <= OPCODE_POP; return_state_next <= QUICKSORT_3; next_state <= send_request; when QUICKSORT_3 => -- 0103 endPtr_next <=mblaze_ret; next_state <= QUICKSORT_4; when QUICKSORT_4 => -- 0104 -- Declare 5 variables opcode_next <= OPCODE_DECLARE; param1_next <= x"0002"; return_state_next <= QUICKSORT_5; next_state <= send_request; when QUICKSORT_5 => -- 0105 -- Copy the start and end pointers leftPtr_next <= startPtr; rightPtr_next <= endPtr; next_state <= QUICKSORT_6; when QUICKSORT_6 => -- 0106 -- check to see if left and right pointers are equal if ( leftPtr >= rightPtr ) then -- Nothing to sort, return next_state <= QUICKSORT_RETURN; else next_state <= QUICKSORT_7; end if; when QUICKSORT_7 => -- 0107 -- Read the value of the leftPtr -- opcode_next <= OPCODE_LOAD; --param1_next <= leftPtr(16 to 31); --return_state_next <= QUICKSORT_8; --next_state <= send_request; in_array_addr0 <= leftPtr; array_rENA0 <= '1'; next_state <= QUICKSORT_8; when QUICKSORT_8 => -- 0108 left_next <= array_dOUT0; -- Read the value of the rightPtr -- opcode_next <= OPCODE_LOAD; -- param1_next <= rightPtr(16 to 31); -- return_state_next <= QUICKSORT_9; -- next_state <= send_request; in_array_addr0 <= rightptr; array_rENA0 <= '1'; next_state <= QUICKSORT_9; when QUICKSORT_9 => -- 0109 right_next <= array_dout0; next_state <= QUICKSORT_A; when QUICKSORT_A => -- 010A -- determine the pivot value by first taking sum of left and right pivot_next <= left + right; next_state <= QUICKSORT_B; when QUICKSORT_B => -- 010B -- next divide the sum of left and right by two (or shift) pivot_next <= '0' & pivot(0 to 30); next_state <= QUICKSORT_DO; when QUICKSORT_DO => -- 0111 -- This is a placeholder for my own sanity next_state <= QUICKSORT_WHILE_LEFT_0; when QUICKSORT_WHILE_LEFT_0 => -- 0121 -- check to see if leftPtr moved past rightPtr if ( leftPtr < rightPtr ) then next_state <= QUICKSORT_WHILE_LEFT_1; else leftPtr_next <= rightPtr; next_state <= QUICKSORT_BREAK; end if; when QUICKSORT_WHILE_LEFT_1 => -- 0121 -- check to see if left < pivot if ( left <= pivot ) then -- left does not have to be swapped, increment leftPtr leftPtr_next <= leftPtr + 4; next_state <= QUICKSORT_WHILE_LEFT_2; else -- left needs to be swapped, end the while loop next_state <= QUICKSORT_BREAK; end if; when QUICKSORT_WHILE_LEFT_2 => -- 0122 -- read value of leftPtr -- opcode_next <= OPCODE_LOAD; --param1_next <= leftPtr(16 to 31); -- return_state_next <= QUICKSORT_WHILE_LEFT_3; -- next_state <= send_request; in_array_addr0 <= leftPtr; array_rENA0 <= '1'; next_state <= QUICKSORT_WHILE_LEFT_3; when QUICKSORT_WHILE_LEFT_3 => -- 0123 left_next <=array_dout0; next_state <= QUICKSORT_WHILE_LEFT_0; when QUICKSORT_BREAK => -- 0131 -- Check that we did not move past right ptr if ( leftPtr >= rightPtr ) then -- we are done swapping next_state <= QUICKSORT_CALL_QS_0; else next_state <= QUICKSORT_WHILE_RIGHT_1; end if; when QUICKSORT_WHILE_RIGHT_1 => -- 0141 -- check to see if right < pivot if ( right > pivot ) then -- right does not have to be swapped, decrement rightPtr rightPtr_next <= rightPtr - 4; next_state <= QUICKSORT_WHILE_RIGHT_2; else -- right needs to be swapped, end the while loop next_state <= QUICKSORT_SWAP_1; end if; when QUICKSORT_WHILE_RIGHT_2 => -- 0142 -- read value of rightPtr --opcode_next <= OPCODE_LOAD; --param1_next <= rightPtr(16 to 31); --return_state_next <= QUICKSORT_WHILE_RIGHT_3; --next_state <= send_request; in_array_addr0 <= rightptr; array_rENA0 <= '1'; next_state <= QUICKSORT_WHILE_RIGHT_3; when QUICKSORT_WHILE_RIGHT_3 => -- 0143 right_next <=array_dout0; next_state <= QUICKSORT_BREAK; when QUICKSORT_SWAP_1 => -- 0151 -- write the value of rightPtr with left --opcode_next <= OPCODE_STORE; -- param1_next <= rightPtr(16 to 31); --param2_next <= left; --return_state_next <= QUICKSORT_SWAP_2; --next_state <= send_request; in_array_addr0 <= rightPtr; array_dIN0 <= left; array_wENA0 <= (others => '1'); array_rENA0 <= '1'; next_state <=QUICKSORT_SWAP_2; when QUICKSORT_SWAP_2 => -- 0152 -- write the value of leftPtr with right --opcode_next <= OPCODE_STORE; --param1_next <= leftPtr(16 to 31); -- param2_next <= right; -- return_state_next <= QUICKSORT_SWAP_3; --next_state <= send_request; in_array_addr0 <= leftPtr; array_dIN0 <= right; array_wENA0 <= (others => '1'); array_rENA0 <= '1'; next_state <=QUICKSORT_SWAP_3; when QUICKSORT_SWAP_3 => -- 0153 -- increment/decrement pointers leftPtr_next <= leftPtr + 4; rightPtr_next <= rightPtr - 4; next_state <= QUICKSORT_SWAP_4; when QUICKSORT_SWAP_4 => -- 0154 -- read new value of left --opcode_next <= OPCODE_LOAD; -- param1_next <= leftPtr(16 to 31); --return_state_next <= QUICKSORT_SWAP_5; --next_state <= send_request; in_array_addr0 <= leftPtr; array_rENA0 <= '1'; next_state <= QUICKSORT_SWAP_5; when QUICKSORT_SWAP_5 => -- 0155 left_next <=array_dout0; -- read new value of right --opcode_next <= OPCODE_LOAD; --param1_next <= rightPtr(16 to 31); --return_state_next <= QUICKSORT_WHILE; --next_state <= send_request; in_array_addr0 <= rightptr; array_rENA0 <= '1'; next_state <= QUICKSORT_WHILE; when QUICKSORT_WHILE => -- 0161 right_next <=array_dout0; -- check to make sure leftPtr < rightPtr if ( leftPtr < rightPtr ) then next_state <= QUICKSORT_DO; else next_state <= QUICKSORT_CALL_QS_0; end if; when QUICKSORT_CALL_QS_0 => -- 0170 -- Check to see if leftPtr == rightPtr if ( leftPtr = rightPtr ) then -- Check to see if right > pivot if ( right >= pivot ) then leftPtr_next <= rightPtr - 4; else rightPtr_next <= rightPtr + 4; end if; else if ( right > pivot ) then leftPtr_next <= rightPtr - 4; else leftPtr_next <= rightPtr; rightPtr_next <= leftPtr; end if; end if; next_state <= QUICKSORT_CALL_QS_1; when QUICKSORT_CALL_QS_1 => -- 0171 -- Before calling quicksort need to save rightPtr and endPtr -- Save the rightPtr opcode_next <= OPCODE_WRITE; param1_next <= x"0000"; param2_next <= rightPtr; return_state_next <= QUICKSORT_CALL_QS_2; next_state <= send_request; when QUICKSORT_CALL_QS_2 => -- 0172 -- Save the endPtr opcode_next <= OPCODE_WRITE; param1_next <= x"0001"; param2_next <= endPtr; return_state_next <= QUICKSORT_CALL_QS_3; next_state <= send_request; when QUICKSORT_CALL_QS_3 => -- 0173 -- Push the leftPtr opcode_next <= OPCODE_PUSH; param2_next <= leftPtr; return_state_next <= QUICKSORT_CALL_QS_4; next_state <= send_request; when QUICKSORT_CALL_QS_4 => -- 0174 -- Push the startPtr opcode_next <= OPCODE_PUSH; param2_next <= startPtr; return_state_next <= QUICKSORT_CALL_QS_5; next_state <= send_request; when QUICKSORT_CALL_QS_5 => -- 0175 -- Call quicksort opcode_next <= OPCODE_CALL; param1_next <= U_QUICKSORT_CALL_QS_6; return_state_next <= QUICKSORT_1; next_state <= send_request; when QUICKSORT_CALL_QS_6 => -- 0176 -- read the value of endPtr opcode_next <= OPCODE_READ; param1_next <= x"0001"; return_state_next <= QUICKSORT_CALL_QS_7; next_state <= send_request; when QUICKSORT_CALL_QS_7 => -- 0177 endPtr_next <=mblaze_ret; -- read the value of rightPtr opcode_next <= OPCODE_READ; param1_next <= x"0000"; return_state_next <= QUICKSORT_CALL_QS_8; next_state <= send_request; when QUICKSORT_CALL_QS_8 => -- 0178 rightPtr_next <=mblaze_ret; -- Push the rightPtr opcode_next <= OPCODE_PUSH; param2_next <= endPtr; return_state_next <= QUICKSORT_CALL_QS_9; next_state <= send_request; when QUICKSORT_CALL_QS_9 => -- 0179 -- push the endPtr opcode_next <= OPCODE_PUSH; param2_next <= rightPtr; return_state_next <= QUICKSORT_CALL_QS_A; next_state <= send_request; when QUICKSORT_CALL_QS_A => -- 017A -- Call quicksort opcode_next <= OPCODE_CALL; param1_next <= U_QUICKSORT_RETURN; return_state_next <= QUICKSORT_1; next_state <= send_request; when QUICKSORT_RETURN => -- 0181 -- Return opcode_next <= OPCODE_RETURN; next_state <= send_request; when others => next_state <= reset; end case; end process FSM_COMB_PROCESS; end architecture IMPLEMENTATION;
library IEEE; use IEEE.std_logic_1164.all; use work.types.all; package interfaces is -- ALU type alu_in_if is record op : alu_op_t; i0 : byte_t; i1 : byte_t; flags : byte_t; end record; type alu_out_if is record q : byte_t; flags : byte_t; end record; -- Memory type memory_in_if is record we : std_logic; address : word_t; data : byte_t; end record; type memory_out_if is record data : byte_t; valid : std_logic; end record; -- Registers type registers_in_if is record we : std_logic; wsel : register_t; rsel0 : register_t; rsel1 : register_t; data : word_t; end record; type registers_out_if is record d0 : word_t; d1 : word_t; a : byte_t; f : byte_t; hl : word_t; sp : word_t; pc : word_t; end record; -- Load Logic type load_logic_in_if is record en : std_logic; r0 : register_t; r1 : register_t; indirect : std_logic_vector(1 downto 0); inc_dec : std_logic_vector(1 downto 0); reg : registers_out_if; mem : memory_out_if; end record; type load_logic_out_if is record reg : registers_in_if; mem : memory_in_if; done : std_logic; i0 : word_t; i1 : word_t; end record; -- alu logic type alu_logic_in_if is record en : std_logic; mode : std_logic_vector(1 downto 0); -- 00 = register, 01 = immediate, 10 = indirect, 11 = cb op : alu_op_t; rsel : register_t; reg : registers_out_if; mem : memory_out_if; end record; type alu_logic_out_if is record reg : registers_in_if; mem : memory_in_if; done : std_logic; end record; type sdcard_hw_out_if is record ss : std_logic; -- slave select miso : std_logic; -- master in slave out sck : std_logic; -- serial clk end record; type sdcard_hw_in_if is record mosi : std_logic; -- master out slave in end record; end;
library ieee; use ieee.std_logic_1164.all; entity toplevel is port( -- input pins IN_clk_50 : in std_logic; IN_rst : in std_logic; IN_RotA : in std_logic; IN_RotB : in std_logic; IN_RotPush : in std_logic; -- output pins OUT_LED_ch0 : out std_logic := '0'; OUT_LED_ch1 : out std_logic := '0'; OUT_LED_ch2 : out std_logic := '0'; OUT_LED_ch3 : out std_logic := '0'; OUT_LED_ch4 : out std_logic := '0'; OUT_LED_ch5 : out std_logic := '0'; OUT_LED_ch6 : out std_logic := '0'; OUT_LED_ch7 : out std_logic := '0' ); end entity toplevel; architecture RTL of toplevel is -- component declarations component rotKey port(clk_50 : in std_logic; rotA : in std_logic; rotB : in std_logic; rotPush : in std_logic; rotRightEvent : out std_logic; rotLeftEvent : out std_logic; rotPushEvent : out std_logic); end component rotKey; component controller port(clk_50 : in std_logic; rst : in std_logic; leftEvent : in std_logic; rightEvent : in std_logic; pushEvent : in std_logic; pwm0 : out std_logic_vector(5 downto 0); pwm1 : out std_logic_vector(5 downto 0); pwm2 : out std_logic_vector(5 downto 0); pwm3 : out std_logic_vector(5 downto 0); pwm4 : out std_logic_vector(5 downto 0); pwm5 : out std_logic_vector(5 downto 0); pwm6 : out std_logic_vector(5 downto 0); pwm7 : out std_logic_vector(5 downto 0)); end component controller; component logDim port(pwmIn : in std_logic_vector(5 downto 0); logPwm : out std_logic_vector(7 downto 0)); end component logDim; component pwmUnit port(clk_10 : in std_logic; rst : in std_logic; duty : in std_logic_vector(7 downto 0); outSig : out std_logic := '0'); end component pwmUnit; -- signal declarations signal sig_rotRightEvent : std_logic; signal sig_rotLeftEvent : std_logic; signal sig_rotPushEvent : std_logic; signal sig_duty0 : std_logic_vector(5 downto 0); signal sig_duty1 : std_logic_vector(5 downto 0); signal sig_duty2 : std_logic_vector(5 downto 0); signal sig_duty3 : std_logic_vector(5 downto 0); signal sig_duty4 : std_logic_vector(5 downto 0); signal sig_duty5 : std_logic_vector(5 downto 0); signal sig_duty6 : std_logic_vector(5 downto 0); signal sig_duty7 : std_logic_vector(5 downto 0); signal sig_pwm0 : std_logic_vector(7 downto 0); signal sig_pwm1 : std_logic_vector(7 downto 0); signal sig_pwm2 : std_logic_vector(7 downto 0); signal sig_pwm3 : std_logic_vector(7 downto 0); signal sig_pwm4 : std_logic_vector(7 downto 0); signal sig_pwm5 : std_logic_vector(7 downto 0); signal sig_pwm6 : std_logic_vector(7 downto 0); signal sig_pwm7 : std_logic_vector(7 downto 0); begin -- create instances and route signals inst_rotKey : rotKey port map(clk_50 => IN_clk_50, rotA => IN_rotA, rotB => IN_rotB, rotPush => IN_rotPush, rotRightEvent => sig_rotRightEvent, rotLeftEvent => sig_rotLeftEvent, rotPushEvent => sig_rotPushEvent); inst_controller : controller port map(clk_50 => IN_clk_50, rst => IN_rst, leftEvent => sig_rotLeftEvent, rightEvent => sig_rotRightEvent, pushEvent => sig_rotPushEvent, pwm0 => sig_duty0, pwm1 => sig_duty1, pwm2 => sig_duty2, pwm3 => sig_duty3, pwm4 => sig_duty4, pwm5 => sig_duty5, pwm6 => sig_duty6, pwm7 => sig_duty7); inst_log0 : logDim port map(pwmIn => sig_duty0, logPwm => sig_pwm0); inst_pwm0 : pwmUnit port map(clk_10 => IN_clk_50, rst => IN_rst, duty => sig_pwm0, outSig => OUT_LED_ch0); inst_log1 : logDim port map(pwmIn => sig_duty1, logPwm => sig_pwm1); inst_pwm1 : pwmUnit port map(clk_10 => IN_clk_50, rst => IN_rst, duty => sig_pwm1, outSig => OUT_LED_ch1); inst_log2 : logDim port map(pwmIn => sig_duty2, logPwm => sig_pwm2); inst_pwm2 : pwmUnit port map(clk_10 => IN_clk_50, rst => IN_rst, duty => sig_pwm2, outSig => OUT_LED_ch2); inst_log3 : logDim port map(pwmIn => sig_duty3, logPwm => sig_pwm3); inst_pwm3 : pwmUnit port map(clk_10 => IN_clk_50, rst => IN_rst, duty => sig_pwm3, outSig => OUT_LED_ch3); inst_log4 : logDim port map(pwmIn => sig_duty4, logPwm => sig_pwm4); inst_pwm4 : pwmUnit port map(clk_10 => IN_clk_50, rst => IN_rst, duty => sig_pwm4, outSig => OUT_LED_ch4); inst_log5 : logDim port map(pwmIn => sig_duty5, logPwm => sig_pwm5); inst_pwm5 : pwmUnit port map(clk_10 => IN_clk_50, rst => IN_rst, duty => sig_pwm5, outSig => OUT_LED_ch5); inst_log6 : logDim port map(pwmIn => sig_duty6, logPwm => sig_pwm6); inst_pwm6 : pwmUnit port map(clk_10 => IN_clk_50, rst => IN_rst, duty => sig_pwm6, outSig => OUT_LED_ch6); inst_log7 : logDim port map(pwmIn => sig_duty7, logPwm => sig_pwm7); inst_pwm7 : pwmUnit port map(clk_10 => IN_clk_50, rst => IN_rst, duty => sig_pwm7, outSig => OUT_LED_ch7); end architecture RTL;
------------------------------------------------------------------------------- -- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------- -- -- Filename: BLK_MEM_GEN_v8_2.vhd -- -- Description: -- This file is the VHDL behvarial model for the -- Block Memory Generator Core. -- ------------------------------------------------------------------------------- -- Author: Xilinx -- -- History: January 11, 2006: Initial revision -- June 11, 2007 : Added independent register stages for -- Port A and Port B (IP1_Jm/v2.5) -- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6) -- April 07, 2009 : Added support for Spartan-6 and Virtex-6 -- features, including the following: -- (i) error injection, detection and/or correction -- (ii) reset priority -- (iii) special reset behavior -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.numeric_std.all; USE ieee.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_misc.all; LIBRARY STD; USE STD.TEXTIO.ALL; ENTITY blk_mem_axi_regs_fwd_v8_2 IS GENERIC( C_DATA_WIDTH : INTEGER := 8 ); PORT ( ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; S_VALID : IN STD_LOGIC; S_READY : OUT STD_LOGIC; S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); M_VALID : OUT STD_LOGIC; M_READY : IN STD_LOGIC; M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ); END ENTITY blk_mem_axi_regs_fwd_v8_2; ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_2 IS SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL S_READY_I : STD_LOGIC := '0'; SIGNAL M_VALID_I : STD_LOGIC := '0'; SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register BEGIN --assign local signal to its output signal S_READY <= S_READY_I; M_VALID <= M_VALID_I; PROCESS(ACLK) BEGIN IF(ACLK'event AND ACLK = '1') THEN ARESET_D <= ARESET_D(0) & ARESET; END IF; END PROCESS; --Save payload data whenever we have a transaction on the slave side PROCESS(ACLK, ARESET) BEGIN IF (ARESET = '1') THEN STORAGE_DATA <= (OTHERS => '0'); ELSIF(ACLK'event AND ACLK = '1') THEN IF(S_VALID = '1' AND S_READY_I = '1') THEN STORAGE_DATA <= S_PAYLOAD_DATA; END IF; END IF; END PROCESS; M_PAYLOAD_DATA <= STORAGE_DATA; -- M_Valid set to high when we have a completed transfer on slave side -- Is removed on a M_READY except if we have a new transfer on the slave side PROCESS(ACLK,ARESET) BEGIN IF (ARESET_D /= "00") THEN M_VALID_I <= '0'; ELSIF(ACLK'event AND ACLK = '1') THEN IF (S_VALID = '1') THEN --Always set M_VALID_I when slave side is valid M_VALID_I <= '1'; ELSIF (M_READY = '1') THEN --Clear (or keep) when no slave side is valid but master side is ready M_VALID_I <= '0'; END IF; END IF; END PROCESS; --Slave Ready is either when Master side drives M_READY or we have space in our storage data S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D)); END axi_regs_fwd_arch; ------------------------------------------------------------------------------- -- Description: -- This is the behavioral model of write_wrapper for the -- Block Memory Generator Core. ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY blk_mem_axi_write_wrapper_beh IS GENERIC ( -- AXI Interface related parameters start here C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full; C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE; C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM; C_WRITE_DEPTH_A : integer := 0; C_AXI_AWADDR_WIDTH : integer := 32; C_ADDRA_WIDTH : integer := 12; C_AXI_WDATA_WIDTH : integer := 32; C_HAS_AXI_ID : integer := 0; C_AXI_ID_WIDTH : integer := 4; -- AXI OUTSTANDING WRITES C_AXI_OS_WR : integer := 2 ); PORT ( -- AXI Global Signals S_ACLK : IN std_logic; S_ARESETN : IN std_logic; -- AXI Full/Lite Slave Write Channel (write side) S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWVALID : IN std_logic := '0'; S_AXI_AWREADY : OUT std_logic := '0'; S_AXI_WVALID : IN std_logic := '0'; S_AXI_WREADY : OUT std_logic := '0'; S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_BVALID : OUT std_logic := '0'; S_AXI_BREADY : IN std_logic := '0'; -- Signals for BMG interface S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0); S_AXI_WR_EN : OUT std_logic:= '0' ); END blk_mem_axi_write_wrapper_beh; ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS ------------------------------------------------------------------------------ -- FUNCTION: if_then_else -- This function is used to implement an IF..THEN when such a statement is not -- allowed. ------------------------------------------------------------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : INTEGER; false_case : INTEGER) RETURN INTEGER IS VARIABLE retval : INTEGER := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; FUNCTION if_then_else ( condition : BOOLEAN; true_case : STD_LOGIC_VECTOR; false_case : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS BEGIN IF NOT condition THEN RETURN false_case; ELSE RETURN true_case; END IF; END if_then_else; FUNCTION if_then_else ( condition : BOOLEAN; true_case : STRING; false_case : STRING) RETURN STRING IS BEGIN IF NOT condition THEN RETURN false_case; ELSE RETURN true_case; END IF; END if_then_else; CONSTANT FLOP_DELAY : TIME := 100 PS; CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001"); CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0, if_then_else((C_AXI_WDATA_WIDTH=16),1, if_then_else((C_AXI_WDATA_WIDTH=32),2, if_then_else((C_AXI_WDATA_WIDTH=64),3, if_then_else((C_AXI_WDATA_WIDTH=128),4, if_then_else((C_AXI_WDATA_WIDTH=256),5,0)))))); SIGNAL bvalid_c : std_logic := '0'; SIGNAL bready_timeout_c : std_logic := '0'; SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); SIGNAL bvalid_r : std_logic := '0'; SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0'); SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0), C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0); SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); SIGNAL w_last_c : std_logic := '0'; SIGNAL addr_en_c : std_logic := '0'; SIGNAL incr_addr_c : std_logic := '0'; SIGNAL aw_ready_r : std_logic := '0'; SIGNAL dec_alen_c : std_logic := '0'; SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1'); SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); SIGNAL total_bytes : integer := 0; SIGNAL wrap_boundary : integer := 0; SIGNAL wrap_base_addr : integer := 0; SIGNAL num_of_bytes_c : integer := 0; SIGNAL num_of_bytes_r : integer := 0; -- Array to store BIDs TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); SIGNAL axi_bid_array : id_array := (others => (others => '0')); COMPONENT write_netlist GENERIC( C_AXI_TYPE : integer ); PORT( S_ACLK : IN std_logic; S_ARESETN : IN std_logic; S_AXI_AWVALID : IN std_logic; aw_ready_r : OUT std_logic; S_AXI_WVALID : IN std_logic; S_AXI_WREADY : OUT std_logic; S_AXI_BVALID : OUT STD_LOGIC; S_AXI_BREADY : IN std_logic; S_AXI_WR_EN : OUT std_logic; w_last_c : IN std_logic; bready_timeout_c : IN std_logic; addr_en_c : OUT std_logic; incr_addr_c : OUT std_logic; bvalid_c : OUT std_logic ); END COMPONENT write_netlist; BEGIN --------------------------------------- --AXI WRITE FSM COMPONENT INSTANTIATION --------------------------------------- axi_wr_fsm : write_netlist GENERIC MAP ( C_AXI_TYPE => C_AXI_TYPE ) PORT MAP ( S_ACLK => S_ACLK, S_ARESETN => S_ARESETN, S_AXI_AWVALID => S_AXI_AWVALID, aw_ready_r => aw_ready_r, S_AXI_WVALID => S_AXI_WVALID, S_AXI_BVALID => OPEN, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BREADY => S_AXI_BREADY, S_AXI_WR_EN => S_AXI_WR_EN, w_last_c => w_last_c, bready_timeout_c => bready_timeout_c, addr_en_c => addr_en_c, incr_addr_c => incr_addr_c, bvalid_c => bvalid_c ); --Wrap Address boundary calculation num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000")); total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1); wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes); wrap_boundary <= wrap_base_addr+total_bytes; --------------------------------------------------------------------------- -- BMG address generation --------------------------------------------------------------------------- P_addr_reg: PROCESS (S_ACLK,S_ARESETN) BEGIN IF (S_ARESETN = '1') THEN awaddr_reg <= (OTHERS => '0'); num_of_bytes_r <= 0; awburst_int <= (OTHERS => '0'); ELSIF (S_ACLK'event AND S_ACLK = '1') THEN IF (addr_en_c = '1') THEN awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY; num_of_bytes_r <= num_of_bytes_c; awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01"); ELSIF (incr_addr_c = '1') THEN IF (awburst_int = "10") THEN IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH); ELSE awaddr_reg <= awaddr_reg + num_of_bytes_r; END IF; ELSIF (awburst_int = "01" OR awburst_int = "11") THEN awaddr_reg <= awaddr_reg + num_of_bytes_r; END IF; END IF; END IF; END PROCESS P_addr_reg; S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0), awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg); --------------------------------------------------------------------------- -- AXI wlast generation --------------------------------------------------------------------------- P_addr_cnt: PROCESS (S_ACLK, S_ARESETN) BEGIN IF (S_ARESETN = '1') THEN awlen_cntr_r <= (OTHERS => '1'); awlen_int <= (OTHERS => '0'); ELSIF (S_ACLK'event AND S_ACLK = '1') THEN IF (addr_en_c = '1') THEN awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY; awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY; ELSIF (dec_alen_c = '1') THEN awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY; END IF; END IF; END PROCESS P_addr_cnt; w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0'; dec_alen_c <= (incr_addr_c OR w_last_c); --------------------------------------------------------------------------- -- Generation of bvalid counter for outstanding transactions --------------------------------------------------------------------------- P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN) BEGIN IF (S_ARESETN = '1') THEN bvalid_count_r <= (OTHERS => '0'); ELSIF (S_ACLK'event AND S_ACLK='1') THEN -- bvalid_count_r generation IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY; ELSIF (bvalid_c = '1') THEN bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY; ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY; END IF; END IF; END PROCESS P_b_valid_os_r ; --------------------------------------------------------------------------- -- Generation of bvalid when BID is used --------------------------------------------------------------------------- gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE SIGNAL bvalid_d1_c : std_logic := '0'; BEGIN P_b_valid_r: PROCESS (S_ACLK, S_ARESETN) BEGIN IF (S_ARESETN = '1') THEN bvalid_r <= '0'; bvalid_d1_c <= '0'; ELSIF (S_ACLK'event AND S_ACLK='1') THEN -- Delay the generation o bvalid_r for generation for BID bvalid_d1_c <= bvalid_c; --external bvalid signal generation IF (bvalid_d1_c = '1') THEN bvalid_r <= '1' AFTER FLOP_DELAY; ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN bvalid_r <= '0' AFTER FLOP_DELAY; END IF; END IF; END PROCESS P_b_valid_r ; END GENERATE gaxi_bvalid_id_r; --------------------------------------------------------------------------- -- Generation of bvalid when BID is not used --------------------------------------------------------------------------- gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE P_b_valid_r: PROCESS (S_ACLK, S_ARESETN) BEGIN IF (S_ARESETN = '1') THEN bvalid_r <= '0'; ELSIF (S_ACLK'event AND S_ACLK='1') THEN --external bvalid signal generation IF (bvalid_c = '1') THEN bvalid_r <= '1' AFTER FLOP_DELAY; ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN bvalid_r <= '0' AFTER FLOP_DELAY; END IF; END IF; END PROCESS P_b_valid_r ; END GENERATE gaxi_bvalid_noid_r; --------------------------------------------------------------------------- -- Generation of Bready timeout --------------------------------------------------------------------------- P_brdy_tout_c: PROCESS (bvalid_count_r) BEGIN -- bready_timeout_c generation IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN bready_timeout_c <= '1'; ELSE bready_timeout_c <= '0'; END IF; END PROCESS P_brdy_tout_c; --------------------------------------------------------------------------- -- Generation of BID --------------------------------------------------------------------------- gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE P_bid_gen: PROCESS (S_ACLK,S_ARESETN) BEGIN IF (S_ARESETN='1') THEN bvalid_wr_cnt_r <= (OTHERS => '0'); bvalid_rd_cnt_r <= (OTHERS => '0'); ELSIF (S_ACLK'event AND S_ACLK='1') THEN -- STORE AWID IN AN ARRAY IF(bvalid_c = '1') THEN bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01"; END IF; -- GENERATE BID FROM AWID ARRAY bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY; S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c)); END IF; END PROCESS P_bid_gen; bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r; --------------------------------------------------------------------------- -- Storing AWID for generation of BID --------------------------------------------------------------------------- P_awid_reg:PROCESS (S_ACLK) BEGIN IF (S_ACLK'event AND S_ACLK='1') THEN IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID; END IF; END IF; END PROCESS P_awid_reg; END GENERATE gaxi_bid_gen; S_AXI_BVALID <= bvalid_r; S_AXI_AWREADY <= aw_ready_r; END axi_write_wrap_arch; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity write_netlist is GENERIC( C_AXI_TYPE : integer ); port ( S_ACLK : in STD_LOGIC := '0'; S_ARESETN : in STD_LOGIC := '0'; S_AXI_AWVALID : in STD_LOGIC := '0'; S_AXI_WVALID : in STD_LOGIC := '0'; S_AXI_BREADY : in STD_LOGIC := '0'; w_last_c : in STD_LOGIC := '0'; bready_timeout_c : in STD_LOGIC := '0'; aw_ready_r : out STD_LOGIC; S_AXI_WREADY : out STD_LOGIC; S_AXI_BVALID : out STD_LOGIC; S_AXI_WR_EN : out STD_LOGIC; addr_en_c : out STD_LOGIC; incr_addr_c : out STD_LOGIC; bvalid_c : out STD_LOGIC ); end write_netlist; architecture STRUCTURE of write_netlist is component beh_muxf7 port( O : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic; S : in std_ulogic ); end component; COMPONENT beh_ff_pre generic( INIT : std_logic := '1' ); port( Q : out std_logic; C : in std_logic; D : in std_logic; PRE : in std_logic ); end COMPONENT beh_ff_pre; COMPONENT beh_ff_ce generic( INIT : std_logic := '0' ); port( Q : out std_logic; C : in std_logic; CE : in std_logic; CLR : in std_logic; D : in std_logic ); end COMPONENT beh_ff_ce; COMPONENT beh_ff_clr generic( INIT : std_logic := '0' ); port( Q : out std_logic; C : in std_logic; CLR : in std_logic; D : in std_logic ); end COMPONENT beh_ff_clr; COMPONENT STATE_LOGIC generic( INIT : std_logic_vector(63 downto 0) := X"0000000000000000" ); port( O : out std_logic; I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; I4 : in std_logic; I5 : in std_logic ); end COMPONENT STATE_LOGIC; BEGIN --------------------------------------------------------------------------- -- AXI LITE --------------------------------------------------------------------------- gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE signal w_ready_r_7 : STD_LOGIC; signal w_ready_c : STD_LOGIC; signal aw_ready_c : STD_LOGIC; signal NlwRenamedSignal_bvalid_c : STD_LOGIC; signal NlwRenamedSignal_incr_addr_c : STD_LOGIC; signal present_state_FSM_FFd3_13 : STD_LOGIC; signal present_state_FSM_FFd2_14 : STD_LOGIC; signal present_state_FSM_FFd1_15 : STD_LOGIC; signal present_state_FSM_FFd4_16 : STD_LOGIC; signal present_state_FSM_FFd4_In : STD_LOGIC; signal present_state_FSM_FFd3_In : STD_LOGIC; signal present_state_FSM_FFd2_In : STD_LOGIC; signal present_state_FSM_FFd1_In : STD_LOGIC; signal present_state_FSM_FFd4_In1_21 : STD_LOGIC; signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 ); begin S_AXI_WREADY <= w_ready_r_7; S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c; S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c; incr_addr_c <= NlwRenamedSignal_incr_addr_c; bvalid_c <= NlwRenamedSignal_bvalid_c; NlwRenamedSignal_incr_addr_c <= '0'; aw_ready_r_2 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => aw_ready_c, Q => aw_ready_r ); w_ready_r : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => w_ready_c, Q => w_ready_r_7 ); present_state_FSM_FFd4 : beh_ff_pre generic map( INIT => '1' ) port map ( C => S_ACLK, D => present_state_FSM_FFd4_In, PRE => S_ARESETN, Q => present_state_FSM_FFd4_16 ); present_state_FSM_FFd3 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => present_state_FSM_FFd3_In, Q => present_state_FSM_FFd3_13 ); present_state_FSM_FFd2 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => present_state_FSM_FFd2_In, Q => present_state_FSM_FFd2_14 ); present_state_FSM_FFd1 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => present_state_FSM_FFd1_In, Q => present_state_FSM_FFd1_15 ); present_state_FSM_FFd3_In1 : STATE_LOGIC generic map( INIT => X"0000000055554440" ) port map ( I0 => S_AXI_WVALID, I1 => S_AXI_AWVALID, I2 => present_state_FSM_FFd2_14, I3 => present_state_FSM_FFd4_16, I4 => present_state_FSM_FFd3_13, I5 => '0', O => present_state_FSM_FFd3_In ); present_state_FSM_FFd2_In1 : STATE_LOGIC generic map( INIT => X"0000000088880800" ) port map ( I0 => S_AXI_AWVALID, I1 => S_AXI_WVALID, I2 => bready_timeout_c, I3 => present_state_FSM_FFd2_14, I4 => present_state_FSM_FFd4_16, I5 => '0', O => present_state_FSM_FFd2_In ); Mmux_addr_en_c_0_1 : STATE_LOGIC generic map( INIT => X"00000000AAAA2000" ) port map ( I0 => S_AXI_AWVALID, I1 => bready_timeout_c, I2 => present_state_FSM_FFd2_14, I3 => S_AXI_WVALID, I4 => present_state_FSM_FFd4_16, I5 => '0', O => addr_en_c ); Mmux_w_ready_c_0_1 : STATE_LOGIC generic map( INIT => X"F5F07570F5F05500" ) port map ( I0 => S_AXI_WVALID, I1 => bready_timeout_c, I2 => S_AXI_AWVALID, I3 => present_state_FSM_FFd3_13, I4 => present_state_FSM_FFd4_16, I5 => present_state_FSM_FFd2_14, O => w_ready_c ); present_state_FSM_FFd1_In1 : STATE_LOGIC generic map( INIT => X"88808880FFFF8880" ) port map ( I0 => S_AXI_WVALID, I1 => bready_timeout_c, I2 => present_state_FSM_FFd3_13, I3 => present_state_FSM_FFd2_14, I4 => present_state_FSM_FFd1_15, I5 => S_AXI_BREADY, O => present_state_FSM_FFd1_In ); Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC generic map( INIT => X"00000000000000A8" ) port map ( I0 => S_AXI_WVALID, I1 => present_state_FSM_FFd2_14, I2 => present_state_FSM_FFd3_13, I3 => '0', I4 => '0', I5 => '0', O => NlwRenamedSignal_bvalid_c ); present_state_FSM_FFd4_In1 : STATE_LOGIC generic map( INIT => X"2F0F27072F0F2200" ) port map ( I0 => S_AXI_WVALID, I1 => bready_timeout_c, I2 => S_AXI_AWVALID, I3 => present_state_FSM_FFd3_13, I4 => present_state_FSM_FFd4_16, I5 => present_state_FSM_FFd2_14, O => present_state_FSM_FFd4_In1_21 ); present_state_FSM_FFd4_In2 : STATE_LOGIC generic map( INIT => X"00000000000000F8" ) port map ( I0 => present_state_FSM_FFd1_15, I1 => S_AXI_BREADY, I2 => present_state_FSM_FFd4_In1_21, I3 => '0', I4 => '0', I5 => '0', O => present_state_FSM_FFd4_In ); Mmux_aw_ready_c_0_1 : STATE_LOGIC generic map( INIT => X"7535753575305500" ) port map ( I0 => S_AXI_AWVALID, I1 => bready_timeout_c, I2 => S_AXI_WVALID, I3 => present_state_FSM_FFd4_16, I4 => present_state_FSM_FFd3_13, I5 => present_state_FSM_FFd2_14, O => Mmux_aw_ready_c(0) ); Mmux_aw_ready_c_0_2 : STATE_LOGIC generic map( INIT => X"00000000000000F8" ) port map ( I0 => present_state_FSM_FFd1_15, I1 => S_AXI_BREADY, I2 => Mmux_aw_ready_c(0), I3 => '0', I4 => '0', I5 => '0', O => aw_ready_c ); END GENERATE gbeh_axi_lite_sm; --------------------------------------------------------------------------- -- AXI FULL --------------------------------------------------------------------------- gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE signal w_ready_r_8 : STD_LOGIC; signal w_ready_c : STD_LOGIC; signal aw_ready_c : STD_LOGIC; signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC; signal present_state_FSM_FFd1_16 : STD_LOGIC; signal present_state_FSM_FFd4_17 : STD_LOGIC; signal present_state_FSM_FFd3_18 : STD_LOGIC; signal present_state_FSM_FFd2_19 : STD_LOGIC; signal present_state_FSM_FFd4_In : STD_LOGIC; signal present_state_FSM_FFd3_In : STD_LOGIC; signal present_state_FSM_FFd2_In : STD_LOGIC; signal present_state_FSM_FFd1_In : STD_LOGIC; signal present_state_FSM_FFd2_In1_24 : STD_LOGIC; signal present_state_FSM_FFd4_In1_25 : STD_LOGIC; signal N2 : STD_LOGIC; signal N4 : STD_LOGIC; begin S_AXI_WREADY <= w_ready_r_8; bvalid_c <= NlwRenamedSig_OI_bvalid_c; S_AXI_BVALID <= '0'; aw_ready_r_2 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => aw_ready_c, Q => aw_ready_r ); w_ready_r : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => w_ready_c, Q => w_ready_r_8 ); present_state_FSM_FFd4 : beh_ff_pre generic map( INIT => '1' ) port map ( C => S_ACLK, D => present_state_FSM_FFd4_In, PRE => S_ARESETN, Q => present_state_FSM_FFd4_17 ); present_state_FSM_FFd3 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => present_state_FSM_FFd3_In, Q => present_state_FSM_FFd3_18 ); present_state_FSM_FFd2 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => present_state_FSM_FFd2_In, Q => present_state_FSM_FFd2_19 ); present_state_FSM_FFd1 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => present_state_FSM_FFd1_In, Q => present_state_FSM_FFd1_16 ); present_state_FSM_FFd3_In1 : STATE_LOGIC generic map( INIT => X"0000000000005540" ) port map ( I0 => S_AXI_WVALID, I1 => present_state_FSM_FFd4_17, I2 => S_AXI_AWVALID, I3 => present_state_FSM_FFd3_18, I4 => '0', I5 => '0', O => present_state_FSM_FFd3_In ); Mmux_aw_ready_c_0_2 : STATE_LOGIC generic map( INIT => X"BF3FBB33AF0FAA00" ) port map ( I0 => S_AXI_BREADY, I1 => bready_timeout_c, I2 => S_AXI_AWVALID, I3 => present_state_FSM_FFd1_16, I4 => present_state_FSM_FFd4_17, I5 => NlwRenamedSig_OI_bvalid_c, O => aw_ready_c ); Mmux_addr_en_c_0_1 : STATE_LOGIC generic map( INIT => X"AAAAAAAA20000000" ) port map ( I0 => S_AXI_AWVALID, I1 => bready_timeout_c, I2 => present_state_FSM_FFd2_19, I3 => S_AXI_WVALID, I4 => w_last_c, I5 => present_state_FSM_FFd4_17, O => addr_en_c ); Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC generic map( INIT => X"00000000000000A8" ) port map ( I0 => S_AXI_WVALID, I1 => present_state_FSM_FFd2_19, I2 => present_state_FSM_FFd3_18, I3 => '0', I4 => '0', I5 => '0', O => S_AXI_WR_EN ); Mmux_incr_addr_c_0_1 : STATE_LOGIC generic map( INIT => X"0000000000002220" ) port map ( I0 => S_AXI_WVALID, I1 => w_last_c, I2 => present_state_FSM_FFd2_19, I3 => present_state_FSM_FFd3_18, I4 => '0', I5 => '0', O => incr_addr_c ); Mmux_aw_ready_c_0_11 : STATE_LOGIC generic map( INIT => X"0000000000008880" ) port map ( I0 => S_AXI_WVALID, I1 => w_last_c, I2 => present_state_FSM_FFd2_19, I3 => present_state_FSM_FFd3_18, I4 => '0', I5 => '0', O => NlwRenamedSig_OI_bvalid_c ); present_state_FSM_FFd2_In1 : STATE_LOGIC generic map( INIT => X"000000000000D5C0" ) port map ( I0 => w_last_c, I1 => S_AXI_AWVALID, I2 => present_state_FSM_FFd4_17, I3 => present_state_FSM_FFd3_18, I4 => '0', I5 => '0', O => present_state_FSM_FFd2_In1_24 ); present_state_FSM_FFd2_In2 : STATE_LOGIC generic map( INIT => X"FFFFAAAA08AAAAAA" ) port map ( I0 => present_state_FSM_FFd2_19, I1 => S_AXI_AWVALID, I2 => bready_timeout_c, I3 => w_last_c, I4 => S_AXI_WVALID, I5 => present_state_FSM_FFd2_In1_24, O => present_state_FSM_FFd2_In ); present_state_FSM_FFd4_In1 : STATE_LOGIC generic map( INIT => X"00C0004000C00000" ) port map ( I0 => S_AXI_AWVALID, I1 => w_last_c, I2 => S_AXI_WVALID, I3 => bready_timeout_c, I4 => present_state_FSM_FFd3_18, I5 => present_state_FSM_FFd2_19, O => present_state_FSM_FFd4_In1_25 ); present_state_FSM_FFd4_In2 : STATE_LOGIC generic map( INIT => X"00000000FFFF88F8" ) port map ( I0 => present_state_FSM_FFd1_16, I1 => S_AXI_BREADY, I2 => present_state_FSM_FFd4_17, I3 => S_AXI_AWVALID, I4 => present_state_FSM_FFd4_In1_25, I5 => '0', O => present_state_FSM_FFd4_In ); Mmux_w_ready_c_0_SW0 : STATE_LOGIC generic map( INIT => X"0000000000000007" ) port map ( I0 => w_last_c, I1 => S_AXI_WVALID, I2 => '0', I3 => '0', I4 => '0', I5 => '0', O => N2 ); Mmux_w_ready_c_0_Q : STATE_LOGIC generic map( INIT => X"FABAFABAFAAAF000" ) port map ( I0 => N2, I1 => bready_timeout_c, I2 => S_AXI_AWVALID, I3 => present_state_FSM_FFd4_17, I4 => present_state_FSM_FFd3_18, I5 => present_state_FSM_FFd2_19, O => w_ready_c ); Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC generic map( INIT => X"0000000000000008" ) port map ( I0 => bready_timeout_c, I1 => S_AXI_WVALID, I2 => '0', I3 => '0', I4 => '0', I5 => '0', O => N4 ); present_state_FSM_FFd1_In1 : STATE_LOGIC generic map( INIT => X"88808880FFFF8880" ) port map ( I0 => w_last_c, I1 => N4, I2 => present_state_FSM_FFd2_19, I3 => present_state_FSM_FFd3_18, I4 => present_state_FSM_FFd1_16, I5 => S_AXI_BREADY, O => present_state_FSM_FFd1_In ); END GENERATE gbeh_axi_full_sm; end STRUCTURE; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; --AXI Behavioral Model entities ENTITY blk_mem_axi_read_wrapper_beh is GENERIC ( -- AXI Interface related parameters start here C_INTERFACE_TYPE : integer := 0; C_AXI_TYPE : integer := 0; C_AXI_SLAVE_TYPE : integer := 0; C_MEMORY_TYPE : integer := 0; C_WRITE_WIDTH_A : integer := 4; C_WRITE_DEPTH_A : integer := 32; C_ADDRA_WIDTH : integer := 12; C_AXI_PIPELINE_STAGES : integer := 0; C_AXI_ARADDR_WIDTH : integer := 12; C_HAS_AXI_ID : integer := 0; C_AXI_ID_WIDTH : integer := 4; C_ADDRB_WIDTH : integer := 12 ); port ( -- AXI Global Signals S_ACLK : IN std_logic; S_ARESETN : IN std_logic; -- AXI Full/Lite Slave Read (Read side) S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0'); S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0'); S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARVALID : IN std_logic := '0'; S_AXI_ARREADY : OUT std_logic; S_AXI_RLAST : OUT std_logic; S_AXI_RVALID : OUT std_logic; S_AXI_RREADY : IN std_logic := '0'; S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0'); S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0'); -- AXI Full/Lite Read Address Signals to BRAM S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0); S_AXI_RD_EN : OUT std_logic ); END blk_mem_axi_read_wrapper_beh; architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is ------------------------------------------------------------------------------ -- FUNCTION: if_then_else -- This function is used to implement an IF..THEN when such a statement is not -- allowed. ------------------------------------------------------------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : STRING; false_case : STRING) RETURN STRING IS BEGIN IF NOT condition THEN RETURN false_case; ELSE RETURN true_case; END IF; END if_then_else; FUNCTION if_then_else ( condition : BOOLEAN; true_case : INTEGER; false_case : INTEGER) RETURN INTEGER IS VARIABLE retval : INTEGER := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; FUNCTION if_then_else ( condition : BOOLEAN; true_case : STD_LOGIC_VECTOR; false_case : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS BEGIN IF NOT condition THEN RETURN false_case; ELSE RETURN true_case; END IF; END if_then_else; CONSTANT FLOP_DELAY : TIME := 100 PS; CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001"); CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0, if_then_else((C_WRITE_WIDTH_A=16),1, if_then_else((C_WRITE_WIDTH_A=32),2, if_then_else((C_WRITE_WIDTH_A=64),3, if_then_else((C_WRITE_WIDTH_A=128),4, if_then_else((C_WRITE_WIDTH_A=256),5,0)))))); SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0'); SIGNAL addr_en_c : std_logic := '0'; SIGNAL rd_en_c : std_logic := '0'; SIGNAL incr_addr_c : std_logic := '0'; SIGNAL single_trans_c : std_logic := '0'; SIGNAL dec_alen_c : std_logic := '0'; SIGNAL mux_sel_c : std_logic := '0'; SIGNAL r_last_c : std_logic := '0'; SIGNAL r_last_int_c : std_logic := '0'; SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE; SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0); SIGNAL num_of_bytes_c : integer := 0; SIGNAL total_bytes : integer := 0; SIGNAL num_of_bytes_r : integer := 0; SIGNAL wrap_base_addr_r : integer := 0; SIGNAL wrap_boundary_r : integer := 0; SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL total_bytes_c : integer := 0; SIGNAL wrap_base_addr_c : integer := 0; SIGNAL wrap_boundary_c : integer := 0; SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0'); COMPONENT read_netlist GENERIC ( -- AXI Interface related parameters start here C_AXI_TYPE : integer := 1; C_ADDRB_WIDTH : integer := 12 ); port ( S_AXI_INCR_ADDR : OUT std_logic := '0'; S_AXI_ADDR_EN : OUT std_logic := '0'; S_AXI_SINGLE_TRANS : OUT std_logic := '0'; S_AXI_MUX_SEL : OUT std_logic := '0'; S_AXI_R_LAST : OUT std_logic := '0'; S_AXI_R_LAST_INT : IN std_logic := '0'; -- AXI Global Signals S_ACLK : IN std_logic; S_ARESETN : IN std_logic; -- AXI Full/Lite Slave Read (Read side) S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0'); S_AXI_ARVALID : IN std_logic := '0'; S_AXI_ARREADY : OUT std_logic; S_AXI_RLAST : OUT std_logic; S_AXI_RVALID : OUT std_logic; S_AXI_RREADY : IN std_logic := '0'; -- AXI Full/Lite Read Address Signals to BRAM S_AXI_RD_EN : OUT std_logic ); END COMPONENT read_netlist; BEGIN dec_alen_c <= incr_addr_c OR r_last_int_c; axi_read_fsm : read_netlist GENERIC MAP( C_AXI_TYPE => 1, C_ADDRB_WIDTH => C_ADDRB_WIDTH ) PORT MAP( S_AXI_INCR_ADDR => incr_addr_c, S_AXI_ADDR_EN => addr_en_c, S_AXI_SINGLE_TRANS => single_trans_c, S_AXI_MUX_SEL => mux_sel_c, S_AXI_R_LAST => r_last_c, S_AXI_R_LAST_INT => r_last_int_c, -- AXI Global Signals S_ACLK => S_ACLK, S_ARESETN => S_ARESETN, -- AXI Full/Lite Slave Read (Read side) S_AXI_ARLEN => S_AXI_ARLEN, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RLAST => S_AXI_RLAST, S_AXI_RVALID => S_AXI_RVALID, S_AXI_RREADY => S_AXI_RREADY, -- AXI Full/Lite Read Address Signals to BRAM S_AXI_RD_EN => rd_en_c ); total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1); wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes); wrap_boundary_r <= wrap_base_addr_r+total_bytes; ---- combinatorial from interface num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000")); arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN); total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1); wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c); wrap_boundary_c <= wrap_base_addr_c+total_bytes_c; arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01"); --------------------------------------------------------------------------- -- BMG address generation --------------------------------------------------------------------------- P_addr_reg: PROCESS (S_ACLK,S_ARESETN) BEGIN IF (S_ARESETN = '1') THEN araddr_reg <= (OTHERS => '0'); arburst_int_r <= (OTHERS => '0'); num_of_bytes_r <= 0; ELSIF (S_ACLK'event AND S_ACLK = '1') THEN IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN arburst_int_r <= arburst_int_c; num_of_bytes_r <= num_of_bytes_c; IF (arburst_int_c = "10") THEN IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH); ELSE araddr_reg <= S_AXI_ARADDR + num_of_bytes_c; END IF; ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN araddr_reg <= S_AXI_ARADDR + num_of_bytes_c; END IF; ELSIF (addr_en_c = '1') THEN araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY; num_of_bytes_r <= num_of_bytes_c; arburst_int_r <= arburst_int_c; ELSIF (incr_addr_c = '1') THEN IF (arburst_int_r = "10") THEN IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH); ELSE araddr_reg <= araddr_reg + num_of_bytes_r; END IF; ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN araddr_reg <= araddr_reg + num_of_bytes_r; END IF; END IF; END IF; END PROCESS P_addr_reg; araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg); -------------------------------------------------------------------------- -- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM -------------------------------------------------------------------------- P_addr_cnt: PROCESS (S_ACLK, S_ARESETN) BEGIN IF S_ARESETN = '1' THEN arlen_cntr <= ONE; arlen_int_r <= (OTHERS => '0'); ELSIF S_ACLK'event AND S_ACLK = '1' THEN IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN); arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY; ELSIF addr_en_c = '1' THEN arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN); arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN); ELSIF dec_alen_c = '1' THEN arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY; ELSE arlen_cntr <= arlen_cntr AFTER FLOP_DELAY; END IF; END IF; END PROCESS P_addr_cnt; r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ; -------------------------------------------------------------------------- -- AXI FULL FSM -- Mux Selection of ARADDR -- ARADDR is driven out from the read fsm based on the mux_sel_c -- Based on mux_sel either ARADDR is given out or the latched ARADDR is -- given out to BRAM -------------------------------------------------------------------------- P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out) BEGIN IF (mux_sel_c = '0') THEN S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR); ELSE S_AXI_ARADDR_OUT <= araddr_out; END IF; END PROCESS P_araddr_mux; -------------------------------------------------------------------------- -- Assign output signals - AXI FULL FSM -------------------------------------------------------------------------- S_AXI_RD_EN <= rd_en_c; grid: IF (C_HAS_AXI_ID = 1) GENERATE P_rid_gen: PROCESS (S_ACLK,S_ARESETN) BEGIN IF (S_ARESETN='1') THEN S_AXI_RID <= (OTHERS => '0'); ar_id_r <= (OTHERS => '0'); ELSIF (S_ACLK'event AND S_ACLK='1') THEN IF (addr_en_c = '1' AND rd_en_c = '1') THEN S_AXI_RID <= S_AXI_ARID; ar_id_r <= S_AXI_ARID; ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN ar_id_r <= S_AXI_ARID; ELSIF (rd_en_c = '1') THEN S_AXI_RID <= ar_id_r; END IF; END IF; END PROCESS P_rid_gen; END GENERATE grid; END blk_mem_axi_read_wrapper_beh_arch; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity read_netlist is GENERIC ( -- AXI Interface related parameters start here C_AXI_TYPE : integer := 1; C_ADDRB_WIDTH : integer := 12 ); port ( S_AXI_R_LAST_INT : in STD_LOGIC := '0'; S_ACLK : in STD_LOGIC := '0'; S_ARESETN : in STD_LOGIC := '0'; S_AXI_ARVALID : in STD_LOGIC := '0'; S_AXI_RREADY : in STD_LOGIC := '0'; S_AXI_INCR_ADDR : out STD_LOGIC; S_AXI_ADDR_EN : out STD_LOGIC; S_AXI_SINGLE_TRANS : out STD_LOGIC; S_AXI_MUX_SEL : out STD_LOGIC; S_AXI_R_LAST : out STD_LOGIC; S_AXI_ARREADY : out STD_LOGIC; S_AXI_RLAST : out STD_LOGIC; S_AXI_RVALID : out STD_LOGIC; S_AXI_RD_EN : out STD_LOGIC; S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); end read_netlist; architecture STRUCTURE of read_netlist is component beh_muxf7 port( O : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic; S : in std_ulogic ); end component; COMPONENT beh_ff_pre generic( INIT : std_logic := '1' ); port( Q : out std_logic; C : in std_logic; D : in std_logic; PRE : in std_logic ); end COMPONENT beh_ff_pre; COMPONENT beh_ff_ce generic( INIT : std_logic := '0' ); port( Q : out std_logic; C : in std_logic; CE : in std_logic; CLR : in std_logic; D : in std_logic ); end COMPONENT beh_ff_ce; COMPONENT beh_ff_clr generic( INIT : std_logic := '0' ); port( Q : out std_logic; C : in std_logic; CLR : in std_logic; D : in std_logic ); end COMPONENT beh_ff_clr; COMPONENT STATE_LOGIC generic( INIT : std_logic_vector(63 downto 0) := X"0000000000000000" ); port( O : out std_logic; I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; I4 : in std_logic; I5 : in std_logic ); end COMPONENT STATE_LOGIC; signal present_state_FSM_FFd1_13 : STD_LOGIC; signal present_state_FSM_FFd2_14 : STD_LOGIC; signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC; signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC; signal gaxi_full_sm_r_last_r_17 : STD_LOGIC; signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC; signal gaxi_full_sm_r_valid_c : STD_LOGIC; signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC; signal gaxi_full_sm_ar_ready_c : STD_LOGIC; signal gaxi_full_sm_outstanding_read_c : STD_LOGIC; signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC; signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC; signal present_state_FSM_FFd2_In : STD_LOGIC; signal present_state_FSM_FFd1_In : STD_LOGIC; signal Mmux_S_AXI_R_LAST13 : STD_LOGIC; signal N01 : STD_LOGIC; signal N2 : STD_LOGIC; signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC; signal N4 : STD_LOGIC; signal N8 : STD_LOGIC; signal N9 : STD_LOGIC; signal N10 : STD_LOGIC; signal N11 : STD_LOGIC; signal N12 : STD_LOGIC; signal N13 : STD_LOGIC; begin S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST; S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16; S_AXI_RLAST <= gaxi_full_sm_r_last_r_17; S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r; gaxi_full_sm_outstanding_read_r : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => gaxi_full_sm_outstanding_read_c, Q => gaxi_full_sm_outstanding_read_r_15 ); gaxi_full_sm_r_valid_r : beh_ff_ce generic map( INIT => '0' ) port map ( C => S_ACLK, CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o, CLR => S_ARESETN, D => gaxi_full_sm_r_valid_c, Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ); gaxi_full_sm_ar_ready_r : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => gaxi_full_sm_ar_ready_c, Q => gaxi_full_sm_ar_ready_r_16 ); gaxi_full_sm_r_last_r : beh_ff_ce generic map( INIT => '0' ) port map ( C => S_ACLK, CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o, CLR => S_ARESETN, D => NlwRenamedSig_OI_S_AXI_R_LAST, Q => gaxi_full_sm_r_last_r_17 ); present_state_FSM_FFd2 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => present_state_FSM_FFd2_In, Q => present_state_FSM_FFd2_14 ); present_state_FSM_FFd1 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => present_state_FSM_FFd1_In, Q => present_state_FSM_FFd1_13 ); S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC generic map( INIT => X"000000000000000B" ) port map ( I0 => S_AXI_RREADY, I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I2 => '0', I3 => '0', I4 => '0', I5 => '0', O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ); Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC generic map( INIT => X"0000000000000008" ) port map ( I0 => S_AXI_ARVALID, I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o, I2 => '0', I3 => '0', I4 => '0', I5 => '0', O => S_AXI_SINGLE_TRANS ); Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC generic map( INIT => X"0000000000000004" ) port map ( I0 => present_state_FSM_FFd1_13, I1 => S_AXI_ARVALID, I2 => '0', I3 => '0', I4 => '0', I5 => '0', O => S_AXI_ADDR_EN ); present_state_FSM_FFd2_In1 : STATE_LOGIC generic map( INIT => X"ECEE2022EEEE2022" ) port map ( I0 => S_AXI_ARVALID, I1 => present_state_FSM_FFd1_13, I2 => S_AXI_RREADY, I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o, I4 => present_state_FSM_FFd2_14, I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, O => present_state_FSM_FFd2_In ); Mmux_S_AXI_R_LAST131 : STATE_LOGIC generic map( INIT => X"0000000044440444" ) port map ( I0 => present_state_FSM_FFd1_13, I1 => S_AXI_ARVALID, I2 => present_state_FSM_FFd2_14, I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I4 => S_AXI_RREADY, I5 => '0', O => Mmux_S_AXI_R_LAST13 ); Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC generic map( INIT => X"4000FFFF40004000" ) port map ( I0 => S_AXI_R_LAST_INT, I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o, I2 => present_state_FSM_FFd2_14, I3 => present_state_FSM_FFd1_13, I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o, I5 => Mmux_S_AXI_R_LAST13, O => S_AXI_INCR_ADDR ); S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC generic map( INIT => X"00000000000000FE" ) port map ( I0 => S_AXI_ARLEN(2), I1 => S_AXI_ARLEN(1), I2 => S_AXI_ARLEN(0), I3 => '0', I4 => '0', I5 => '0', O => N01 ); S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC generic map( INIT => X"0000000000000001" ) port map ( I0 => S_AXI_ARLEN(7), I1 => S_AXI_ARLEN(6), I2 => S_AXI_ARLEN(5), I3 => S_AXI_ARLEN(4), I4 => S_AXI_ARLEN(3), I5 => N01, O => S_AXI_ARLEN_7_GND_8_o_equal_1_o ); Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC generic map( INIT => X"0000000000000007" ) port map ( I0 => S_AXI_ARVALID, I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o, I2 => '0', I3 => '0', I4 => '0', I5 => '0', O => N2 ); Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC generic map( INIT => X"0020000002200200" ) port map ( I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I1 => S_AXI_RREADY, I2 => present_state_FSM_FFd1_13, I3 => present_state_FSM_FFd2_14, I4 => gaxi_full_sm_outstanding_read_r_15, I5 => N2, O => gaxi_full_sm_outstanding_read_c ); Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC generic map( INIT => X"0000000000004555" ) port map ( I0 => S_AXI_ARVALID, I1 => S_AXI_RREADY, I2 => present_state_FSM_FFd2_14, I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I4 => '0', I5 => '0', O => Mmux_gaxi_full_sm_ar_ready_c11 ); Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC generic map( INIT => X"00000000000000EF" ) port map ( I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o, I1 => S_AXI_RREADY, I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I3 => '0', I4 => '0', I5 => '0', O => N4 ); Mmux_S_AXI_R_LAST11 : STATE_LOGIC generic map( INIT => X"FCAAFC0A00AA000A" ) port map ( I0 => S_AXI_ARVALID, I1 => gaxi_full_sm_outstanding_read_r_15, I2 => present_state_FSM_FFd2_14, I3 => present_state_FSM_FFd1_13, I4 => N4, I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o, O => gaxi_full_sm_r_valid_c ); S_AXI_MUX_SEL1 : STATE_LOGIC generic map( INIT => X"00000000AAAAAA08" ) port map ( I0 => present_state_FSM_FFd1_13, I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I2 => S_AXI_RREADY, I3 => present_state_FSM_FFd2_14, I4 => gaxi_full_sm_outstanding_read_r_15, I5 => '0', O => S_AXI_MUX_SEL ); Mmux_S_AXI_RD_EN11 : STATE_LOGIC generic map( INIT => X"F3F3F755A2A2A200" ) port map ( I0 => present_state_FSM_FFd1_13, I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I2 => S_AXI_RREADY, I3 => gaxi_full_sm_outstanding_read_r_15, I4 => present_state_FSM_FFd2_14, I5 => S_AXI_ARVALID, O => S_AXI_RD_EN ); present_state_FSM_FFd1_In3 : beh_muxf7 port map ( I0 => N8, I1 => N9, S => present_state_FSM_FFd1_13, O => present_state_FSM_FFd1_In ); present_state_FSM_FFd1_In3_F : STATE_LOGIC generic map( INIT => X"000000005410F4F0" ) port map ( I0 => S_AXI_RREADY, I1 => present_state_FSM_FFd2_14, I2 => S_AXI_ARVALID, I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o, I5 => '0', O => N8 ); present_state_FSM_FFd1_In3_G : STATE_LOGIC generic map( INIT => X"0000000072FF7272" ) port map ( I0 => present_state_FSM_FFd2_14, I1 => S_AXI_R_LAST_INT, I2 => gaxi_full_sm_outstanding_read_r_15, I3 => S_AXI_RREADY, I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I5 => '0', O => N9 ); Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7 port map ( I0 => N10, I1 => N11, S => present_state_FSM_FFd1_13, O => gaxi_full_sm_ar_ready_c ); Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC generic map( INIT => X"00000000FFFF88A8" ) port map ( I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o, I1 => S_AXI_RREADY, I2 => present_state_FSM_FFd2_14, I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I4 => Mmux_gaxi_full_sm_ar_ready_c11, I5 => '0', O => N10 ); Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC generic map( INIT => X"000000008D008D8D" ) port map ( I0 => present_state_FSM_FFd2_14, I1 => S_AXI_R_LAST_INT, I2 => gaxi_full_sm_outstanding_read_r_15, I3 => S_AXI_RREADY, I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I5 => '0', O => N11 ); Mmux_S_AXI_R_LAST1 : beh_muxf7 port map ( I0 => N12, I1 => N13, S => present_state_FSM_FFd1_13, O => NlwRenamedSig_OI_S_AXI_R_LAST ); Mmux_S_AXI_R_LAST1_F : STATE_LOGIC generic map( INIT => X"0000000088088888" ) port map ( I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o, I1 => S_AXI_ARVALID, I2 => present_state_FSM_FFd2_14, I3 => S_AXI_RREADY, I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I5 => '0', O => N12 ); Mmux_S_AXI_R_LAST1_G : STATE_LOGIC generic map( INIT => X"00000000E400E4E4" ) port map ( I0 => present_state_FSM_FFd2_14, I1 => gaxi_full_sm_outstanding_read_r_15, I2 => S_AXI_R_LAST_INT, I3 => S_AXI_RREADY, I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I5 => '0', O => N13 ); end STRUCTURE; ------------------------------------------------------------------------------- -- Output Register Stage Entity -- -- This module builds the output register stages of the memory. This module is -- instantiated in the main memory module (BLK_MEM_GEN_v8_2) which is -- declared/implemented further down in this file. ------------------------------------------------------------------------------- LIBRARY STD; USE STD.TEXTIO.ALL; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY BLK_MEM_GEN_v8_2_output_stage IS GENERIC ( C_FAMILY : STRING := "virtex7"; C_XDEVICEFAMILY : STRING := "virtex7"; C_RST_TYPE : STRING := "SYNC"; C_HAS_RST : INTEGER := 0; C_RSTRAM : INTEGER := 0; C_RST_PRIORITY : STRING := "CE"; init_val : STD_LOGIC_VECTOR; C_HAS_EN : INTEGER := 0; C_HAS_REGCE : INTEGER := 0; C_DATA_WIDTH : INTEGER := 32; C_ADDRB_WIDTH : INTEGER := 10; C_HAS_MEM_OUTPUT_REGS : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; C_USE_ECC : INTEGER := 0; NUM_STAGES : INTEGER := 1; C_EN_ECC_PIPE : INTEGER := 0; FLOP_DELAY : TIME := 100 ps ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; REGCE : IN STD_LOGIC; DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); SBITERR_IN_I : IN STD_LOGIC; DBITERR_IN_I : IN STD_LOGIC; SBITERR : OUT STD_LOGIC; DBITERR : OUT STD_LOGIC; RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); eccpipece : IN STD_LOGIC; RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ); END BLK_MEM_GEN_v8_2_output_stage; --****************************** -- Port and Generic Definitions --****************************** --------------------------------------------------------------------------- -- Generic Definitions --------------------------------------------------------------------------- -- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following -- options are available - "spartan3", "spartan6", -- "virtex4", "virtex5", "virtex6" and "virtex6l". -- C_RST_TYPE : Type of reset - Synchronous or Asynchronous -- C_HAS_RST : Determines the presence of the RST port -- C_RSTRAM : Determines if special reset behavior is used -- C_RST_PRIORITY : Determines the priority between CE and SR -- C_INIT_VAL : Initialization value -- C_HAS_EN : Determines the presence of the EN port -- C_HAS_REGCE : Determines the presence of the REGCE port -- C_DATA_WIDTH : Memory write/read width -- C_ADDRB_WIDTH : Width of the ADDRB input port -- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output -- of the RAM primitive -- C_USE_SOFTECC : Determines if the Soft ECC feature is used or -- not. Only applicable Spartan-6 -- C_USE_ECC : Determines if the ECC feature is used or -- not. Only applicable for V5 and V6 -- NUM_STAGES : Determines the number of output stages -- FLOP_DELAY : Constant delay for register assignments --------------------------------------------------------------------------- -- Port Definitions --------------------------------------------------------------------------- -- CLK : Clock to synchronize all read and write operations -- RST : Reset input to reset memory outputs to a user-defined -- reset state -- EN : Enable all read and write operations -- REGCE : Register Clock Enable to control each pipeline output -- register stages -- DIN : Data input to the Output stage. -- DOUT : Final Data output -- SBITERR_IN : SBITERR input signal to the Output stage. -- SBITERR : Final SBITERR Output signal. -- DBITERR_IN : DBITERR input signal to the Output stage. -- DBITERR : Final DBITERR Output signal. -- RDADDRECC_IN : RDADDRECC input signal to the Output stage. -- RDADDRECC : Final RDADDRECC Output signal. --------------------------------------------------------------------------- ARCHITECTURE output_stage_behavioral OF BLK_MEM_GEN_v8_2_output_stage IS --******************************************************* -- Functions used in the output stage ARCHITECTURE --******************************************************* -- Calculate num_reg_stages FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS VARIABLE num_reg_stages : INTEGER := 0; BEGIN IF (NUM_STAGES = 0) THEN num_reg_stages := 0; ELSE num_reg_stages := NUM_STAGES - 1; END IF; RETURN num_reg_stages; END get_num_reg_stages; -- Check if the INTEGER is zero or non-zero FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS VARIABLE temp_return : STD_LOGIC; BEGIN IF (input = 0) THEN temp_return := '0'; ELSE temp_return := '1'; END IF; RETURN temp_return; END int_to_bit; -- Constants CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN); CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE); CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST); CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES); -- Pipeline array TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC; TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val); SIGNAL out_regs : reg_data_array := REG_INIT; SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0'); SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0'); SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0')); -- Internal signals SIGNAL en_i : STD_LOGIC; SIGNAL regce_i : STD_LOGIC; SIGNAL rst_i : STD_LOGIC; SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val; SIGNAL sbiterr_i: STD_LOGIC := '0'; SIGNAL dbiterr_i: STD_LOGIC := '0'; SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ; SIGNAL SBITERR_IN : STD_LOGIC := '0'; SIGNAL DBITERR_IN : STD_LOGIC := '0'; BEGIN --*********************************************************************** -- Assign internal signals. This effectively wires off optional inputs. --*********************************************************************** -- Internal enable for output registers is tied to user EN or '1' depending -- on parameters en_i <= EN OR (NOT HAS_EN); -- Internal register enable for output registers is tied to user REGCE, EN -- or '1' depending on parameters regce_i <= (HAS_REGCE AND REGCE) OR ((NOT HAS_REGCE) AND en_i); -- Internal SRR is tied to user RST or '0' depending on parameters rst_i <= RST AND HAS_RST; --*************************************************************************** -- NUM_STAGES = 0 (No output registers. RAM only) --*************************************************************************** zero_stages: IF (NUM_STAGES = 0) GENERATE DOUT <= DIN; SBITERR <= SBITERR_IN; DBITERR <= DBITERR_IN; RDADDRECC <= RDADDRECC_IN; END GENERATE zero_stages; NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE DIN <= DIN_I; RDADDRECC_IN <= RDADDRECC_IN_I; SBITERR_IN <= SBITERR_IN_I; DBITERR_IN <= DBITERR_IN_I; END GENERATE NO_ECC_PIPE_REG; WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE PROCESS (CLK) BEGIN IF (CLK'EVENT AND CLK = '1') THEN IF(ECCPIPECE = '1') THEN DIN <= DIN_I AFTER FLOP_DELAY; RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY; SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY; DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY; END IF; END IF; END PROCESS; END GENERATE WITH_ECC_PIPE_REG; --*************************************************************************** -- NUM_STAGES = 1 -- (Mem Output Reg only or Mux Output Reg only) --*************************************************************************** -- Possible valid combinations: -- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1) -- +-----------------------------------------+ -- | C_RSTRAM_* | Reset Behavior | -- +----------------+------------------------+ -- | 0 | Normal Behavior | -- +----------------+------------------------+ -- | 1 | Special Behavior | -- +----------------+------------------------+ -- -- Normal = REGCE gates reset, as in the case of all Virtex families and all -- spartan families with the exception of S3ADSP and S6. -- Special = EN gates reset, as in the case of S3ADSP and S6. one_stage_norm: IF (NUM_STAGES = 1 AND (C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE DOUT <= dout_i; SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0'; DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0'; RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0'); PROCESS (CLK,rst_i,regce_i) BEGIN IF (CLK'EVENT AND CLK = '1') THEN IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset IF (rst_i = '1' AND regce_i='1') THEN dout_i <= init_val AFTER FLOP_DELAY; sbiterr_i <= '0' AFTER FLOP_DELAY; dbiterr_i <= '0' AFTER FLOP_DELAY; rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY; ELSIF (regce_i='1') THEN dout_i <= DIN AFTER FLOP_DELAY; sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY; dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY; rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY; END IF; ELSE --RSTA has priority and is independent of REGCE IF (rst_i = '1') THEN dout_i <= init_val AFTER FLOP_DELAY; sbiterr_i <= '0' AFTER FLOP_DELAY; dbiterr_i <= '0' AFTER FLOP_DELAY; rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY; ELSIF (regce_i='1') THEN dout_i <= DIN AFTER FLOP_DELAY; sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY; dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY; rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY; END IF; END IF;--Priority conditions END IF;--CLK END PROCESS; END GENERATE one_stage_norm; -- Special Reset Behavior for S6 and S3ADSP one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp")) GENERATE DOUT <= dout_i; SBITERR <= '0'; DBITERR <= '0'; RDADDRECC <= (OTHERS => '0'); PROCESS (CLK) BEGIN IF (CLK'EVENT AND CLK = '1') THEN IF (rst_i='1' AND en_i='1') THEN dout_i <= init_val AFTER FLOP_DELAY; ELSIF (regce_i='1' AND rst_i/='1') THEN dout_i <= DIN AFTER FLOP_DELAY; END IF; END IF;--CLK END PROCESS; END GENERATE one_stage_splbhv; --**************************************************************************** -- NUM_STAGES > 1 -- Mem Output Reg + Mux Output Reg -- or -- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg -- or -- Mux Pipeline Stages (>0) + Mux Output Reg --**************************************************************************** multi_stage: IF (NUM_STAGES > 1) GENERATE DOUT <= dout_i; SBITERR <= sbiterr_i; DBITERR <= dbiterr_i; RDADDRECC <= rdaddrecc_i; PROCESS (CLK,rst_i,regce_i) BEGIN IF (CLK'EVENT AND CLK = '1') THEN IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset IF (rst_i='1'AND regce_i='1') THEN dout_i <= init_val AFTER FLOP_DELAY; sbiterr_i <= '0' AFTER FLOP_DELAY; dbiterr_i <= '0' AFTER FLOP_DELAY; rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY; ELSIF (regce_i='1') THEN dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY; sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY; dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY; rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY; END IF; ELSE --RSTA has priority and is independent of REGCE IF (rst_i = '1') THEN dout_i <= init_val AFTER FLOP_DELAY; sbiterr_i <= '0' AFTER FLOP_DELAY; dbiterr_i <= '0' AFTER FLOP_DELAY; rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY; ELSIF (regce_i='1') THEN dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY; sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY; dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY; rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY; END IF; END IF;--Priority conditions IF (en_i='1') THEN -- Shift the data through the output stages FOR i IN 1 TO REG_STAGES-1 LOOP out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY; sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY; dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY; rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY; END LOOP; out_regs(0) <= DIN; sbiterr_regs(0) <= SBITERR_IN; dbiterr_regs(0) <= DBITERR_IN; rdaddrecc_regs(0) <= RDADDRECC_IN; END IF; END IF;--CLK END PROCESS; END GENERATE multi_stage; END output_stage_behavioral; ------------------------------------------------------------------------------- -- SoftECC Output Register Stage Entity -- This module builds the softecc output register stages. This module is -- instantiated in the memory module (BLK_MEM_GEN_v8_2_mem_module) which is -- declared/implemented further down in this file. ------------------------------------------------------------------------------- LIBRARY STD; USE STD.TEXTIO.ALL; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY BLK_MEM_GEN_v8_2_softecc_output_reg_stage IS GENERIC ( C_DATA_WIDTH : INTEGER := 32; C_ADDRB_WIDTH : INTEGER := 10; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; FLOP_DELAY : TIME := 100 ps ); PORT ( CLK : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ; DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); SBITERR_IN : IN STD_LOGIC; DBITERR_IN : IN STD_LOGIC; SBITERR : OUT STD_LOGIC; DBITERR : OUT STD_LOGIC; RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ; RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ); END BLK_MEM_GEN_v8_2_softecc_output_reg_stage; --****************************** -- Port and Generic Definitions --****************************** --------------------------------------------------------------------------- -- Generic Definitions --------------------------------------------------------------------------- -- C_DATA_WIDTH : Memory write/read width -- C_ADDRB_WIDTH : Width of the ADDRB input port -- of the RAM primitive -- FLOP_DELAY : Constant delay for register assignments --------------------------------------------------------------------------- -- Port Definitions --------------------------------------------------------------------------- -- CLK : Clock to synchronize all read and write operations -- RST : Reset input to reset memory outputs to a user-defined -- reset state -- EN : Enable all read and write operations -- REGCE : Register Clock Enable to control each pipeline output -- register stages -- DIN : Data input to the Output stage. -- DOUT : Final Data output -- SBITERR_IN : SBITERR input signal to the Output stage. -- SBITERR : Final SBITERR Output signal. -- DBITERR_IN : DBITERR input signal to the Output stage. -- DBITERR : Final DBITERR Output signal. -- RDADDRECC_IN : RDADDRECC input signal to the Output stage. -- RDADDRECC : Final RDADDRECC Output signal. --------------------------------------------------------------------------- ARCHITECTURE softecc_output_reg_stage_behavioral OF BLK_MEM_GEN_v8_2_softecc_output_reg_stage IS -- Internal signals SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL sbiterr_i: STD_LOGIC := '0'; SIGNAL dbiterr_i: STD_LOGIC := '0'; SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); BEGIN --*************************************************************************** -- NO OUTPUT STAGES --*************************************************************************** no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE DOUT <= DIN; SBITERR <= SBITERR_IN; DBITERR <= DBITERR_IN; RDADDRECC <= RDADDRECC_IN; END GENERATE no_output_stage; --**************************************************************************** -- WITH OUTPUT STAGE --**************************************************************************** has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE PROCESS (CLK) BEGIN IF (CLK'EVENT AND CLK = '1') THEN dout_i <= DIN AFTER FLOP_DELAY; sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY; dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY; rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY; END IF; END PROCESS; DOUT <= dout_i; SBITERR <= sbiterr_i; DBITERR <= dbiterr_i; RDADDRECC <= rdaddrecc_i; END GENERATE has_output_stage; END softecc_output_reg_stage_behavioral; --****************************************************************************** -- Main Memory module -- -- This module is the behavioral model which implements the RAM --****************************************************************************** LIBRARY STD; USE STD.TEXTIO.ALL; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_MISC.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.std_logic_textio.all; ENTITY BLK_MEM_GEN_v8_2_mem_module IS GENERIC ( C_CORENAME : STRING := "blk_mem_gen_v8_2"; C_FAMILY : STRING := "virtex7"; C_XDEVICEFAMILY : STRING := "virtex7"; C_USE_BRAM_BLOCK : INTEGER := 0; C_ENABLE_32BIT_ADDRESS : INTEGER := 0; C_MEM_TYPE : INTEGER := 2; C_BYTE_SIZE : INTEGER := 8; C_ALGORITHM : INTEGER := 2; C_PRIM_TYPE : INTEGER := 3; C_LOAD_INIT_FILE : INTEGER := 0; C_INIT_FILE_NAME : STRING := ""; C_INIT_FILE : STRING := ""; C_USE_DEFAULT_DATA : INTEGER := 0; C_DEFAULT_DATA : STRING := ""; C_RST_TYPE : STRING := "SYNC"; C_HAS_RSTA : INTEGER := 0; C_RST_PRIORITY_A : STRING := "CE"; C_RSTRAM_A : INTEGER := 0; C_INITA_VAL : STRING := ""; C_HAS_ENA : INTEGER := 1; C_HAS_REGCEA : INTEGER := 0; C_USE_BYTE_WEA : INTEGER := 0; C_WEA_WIDTH : INTEGER := 1; C_WRITE_MODE_A : STRING := "WRITE_FIRST"; C_WRITE_WIDTH_A : INTEGER := 32; C_READ_WIDTH_A : INTEGER := 32; C_WRITE_DEPTH_A : INTEGER := 64; C_READ_DEPTH_A : INTEGER := 64; C_ADDRA_WIDTH : INTEGER := 6; C_HAS_RSTB : INTEGER := 0; C_RST_PRIORITY_B : STRING := "CE"; C_RSTRAM_B : INTEGER := 0; C_INITB_VAL : STRING := ""; C_HAS_ENB : INTEGER := 1; C_HAS_REGCEB : INTEGER := 0; C_USE_BYTE_WEB : INTEGER := 0; C_WEB_WIDTH : INTEGER := 1; C_WRITE_MODE_B : STRING := "WRITE_FIRST"; C_WRITE_WIDTH_B : INTEGER := 32; C_READ_WIDTH_B : INTEGER := 32; C_WRITE_DEPTH_B : INTEGER := 64; C_READ_DEPTH_B : INTEGER := 64; C_ADDRB_WIDTH : INTEGER := 6; C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0; C_MUX_PIPELINE_STAGES : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; C_USE_ECC : INTEGER := 0; C_HAS_INJECTERR : INTEGER := 0; C_SIM_COLLISION_CHECK : STRING := "NONE"; C_COMMON_CLK : INTEGER := 1; FLOP_DELAY : TIME := 100 ps; C_DISABLE_WARN_BHV_COLL : INTEGER := 0; C_EN_ECC_PIPE : INTEGER := 0; C_DISABLE_WARN_BHV_RANGE : INTEGER := 0 ); PORT ( CLKA : IN STD_LOGIC := '0'; RSTA : IN STD_LOGIC := '0'; ENA : IN STD_LOGIC := '1'; REGCEA : IN STD_LOGIC := '1'; WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0'); DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0); CLKB : IN STD_LOGIC := '0'; RSTB : IN STD_LOGIC := '0'; ENB : IN STD_LOGIC := '1'; REGCEB : IN STD_LOGIC := '1'; WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0'); DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0); INJECTSBITERR : IN STD_LOGIC := '0'; INJECTDBITERR : IN STD_LOGIC := '0'; SBITERR : OUT STD_LOGIC; DBITERR : OUT STD_LOGIC; ECCPIPECE : IN STD_LOGIC; SLEEP : IN STD_LOGIC; RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ); END BLK_MEM_GEN_v8_2_mem_module; --****************************** -- Port and Generic Definitions --****************************** --------------------------------------------------------------------------- -- Generic Definitions --------------------------------------------------------------------------- -- C_CORENAME : Instance name of the Block Memory Generator core -- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following -- options are available - "spartan3", "spartan6", -- "virtex4", "virtex5", "virtex6l" and "virtex6". -- C_MEM_TYPE : Designates memory type. -- It can be -- 0 - Single Port Memory -- 1 - Simple Dual Port Memory -- 2 - True Dual Port Memory -- 3 - Single Port Read Only Memory -- 4 - Dual Port Read Only Memory -- C_BYTE_SIZE : Size of a byte (8 or 9 bits) -- C_ALGORITHM : Designates the algorithm method used -- for constructing the memory. -- It can be Fixed_Primitives, Minimum_Area or -- Low_Power -- C_PRIM_TYPE : Designates the user selected primitive used to -- construct the memory. -- -- C_LOAD_INIT_FILE : Designates the use of an initialization file to -- initialize memory contents. -- C_INIT_FILE_NAME : Memory initialization file name. -- C_USE_DEFAULT_DATA : Designates whether to fill remaining -- initialization space with default data -- C_DEFAULT_DATA : Default value of all memory locations -- not initialized by the memory -- initialization file. -- C_RST_TYPE : Type of reset - Synchronous or Asynchronous -- -- C_HAS_RSTA : Determines the presence of the RSTA port -- C_RST_PRIORITY_A : Determines the priority between CE and SR for -- Port A. -- C_RSTRAM_A : Determines if special reset behavior is used for -- Port A -- C_INITA_VAL : The initialization value for Port A -- C_HAS_ENA : Determines the presence of the ENA port -- C_HAS_REGCEA : Determines the presence of the REGCEA port -- C_USE_BYTE_WEA : Determines if the Byte Write is used or not. -- C_WEA_WIDTH : The width of the WEA port -- C_WRITE_MODE_A : Configurable write mode for Port A. It can be -- WRITE_FIRST, READ_FIRST or NO_CHANGE. -- C_WRITE_WIDTH_A : Memory write width for Port A. -- C_READ_WIDTH_A : Memory read width for Port A. -- C_WRITE_DEPTH_A : Memory write depth for Port A. -- C_READ_DEPTH_A : Memory read depth for Port A. -- C_ADDRA_WIDTH : Width of the ADDRA input port -- C_HAS_RSTB : Determines the presence of the RSTB port -- C_RST_PRIORITY_B : Determines the priority between CE and SR for -- Port B. -- C_RSTRAM_B : Determines if special reset behavior is used for -- Port B -- C_INITB_VAL : The initialization value for Port B -- C_HAS_ENB : Determines the presence of the ENB port -- C_HAS_REGCEB : Determines the presence of the REGCEB port -- C_USE_BYTE_WEB : Determines if the Byte Write is used or not. -- C_WEB_WIDTH : The width of the WEB port -- C_WRITE_MODE_B : Configurable write mode for Port B. It can be -- WRITE_FIRST, READ_FIRST or NO_CHANGE. -- C_WRITE_WIDTH_B : Memory write width for Port B. -- C_READ_WIDTH_B : Memory read width for Port B. -- C_WRITE_DEPTH_B : Memory write depth for Port B. -- C_READ_DEPTH_B : Memory read depth for Port B. -- C_ADDRB_WIDTH : Width of the ADDRB input port -- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output -- of the RAM primitive for Port A. -- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output -- of the RAM primitive for Port B. -- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output -- of the MUX for Port A. -- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output -- of the MUX for Port B. -- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in -- between the muxes. -- C_USE_SOFTECC : Determines if the Soft ECC feature is used or -- not. Only applicable Spartan-6 -- C_USE_ECC : Determines if the ECC feature is used or -- not. Only applicable for V5 and V6 -- C_HAS_INJECTERR : Determines if the error injection pins -- are present or not. If the ECC feature -- is not used, this value is defaulted to -- 0, else the following are the allowed -- values: -- 0 : No INJECTSBITERR or INJECTDBITERR pins -- 1 : Only INJECTSBITERR pin exists -- 2 : Only INJECTDBITERR pin exists -- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist -- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision -- warnings. It can be "ALL", "NONE", -- "Warnings_Only" or "Generate_X_Only". -- C_COMMON_CLK : Determins if the core has a single CLK input. -- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings -- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range -- warnings --------------------------------------------------------------------------- -- Port Definitions --------------------------------------------------------------------------- -- CLKA : Clock to synchronize all read and write operations of Port A. -- RSTA : Reset input to reset memory outputs to a user-defined -- reset state for Port A. -- ENA : Enable all read and write operations of Port A. -- REGCEA : Register Clock Enable to control each pipeline output -- register stages for Port A. -- WEA : Write Enable to enable all write operations of Port A. -- ADDRA : Address of Port A. -- DINA : Data input of Port A. -- DOUTA : Data output of Port A. -- CLKB : Clock to synchronize all read and write operations of Port B. -- RSTB : Reset input to reset memory outputs to a user-defined -- reset state for Port B. -- ENB : Enable all read and write operations of Port B. -- REGCEB : Register Clock Enable to control each pipeline output -- register stages for Port B. -- WEB : Write Enable to enable all write operations of Port B. -- ADDRB : Address of Port B. -- DINB : Data input of Port B. -- DOUTB : Data output of Port B. -- INJECTSBITERR : Single Bit ECC Error Injection Pin. -- INJECTDBITERR : Double Bit ECC Error Injection Pin. -- SBITERR : Output signal indicating that a Single Bit ECC Error has been -- detected and corrected. -- DBITERR : Output signal indicating that a Double Bit ECC Error has been -- detected. -- RDADDRECC : Read Address Output signal indicating address at which an -- ECC error has occurred. --------------------------------------------------------------------------- ARCHITECTURE mem_module_behavioral OF BLK_MEM_GEN_v8_2_mem_module IS --**************************************** -- min/max constant functions --**************************************** -- get_max ---------- function SLV_TO_INT(SLV: in std_logic_vector ) return integer is variable int : integer; begin int := 0; for i in SLV'high downto SLV'low loop int := int * 2; if SLV(i) = '1' then int := int + 1; end if; end loop; return int; end; FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS BEGIN IF (a > b) THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION; -- get_min ---------- FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS BEGIN IF (a < b) THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION; --*************************************************************** -- convert write_mode from STRING type for use in case statement --*************************************************************** FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS BEGIN IF (mode = "NO_CHANGE") THEN RETURN "10"; ELSIF (mode = "READ_FIRST") THEN RETURN "01"; ELSE RETURN "00"; -- WRITE_FIRST END IF; END FUNCTION; --*************************************************************** -- convert hex STRING to STD_LOGIC_VECTOR --*************************************************************** FUNCTION hex_to_std_logic_vector( hex_str : STRING; return_width : INTEGER) RETURN STD_LOGIC_VECTOR IS VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1 DOWNTO 0); BEGIN tmp := (OTHERS => '0'); FOR i IN 1 TO hex_str'LENGTH LOOP CASE hex_str((hex_str'LENGTH+1)-i) IS WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000"; WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001"; WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010"; WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011"; WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100"; WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101"; WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110"; WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111"; WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000"; WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001"; WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010"; WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011"; WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100"; WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101"; WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110"; WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111"; WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111"; END CASE; END LOOP; RETURN tmp(return_width-1 DOWNTO 0); END hex_to_std_logic_vector; --*************************************************************** -- convert bit to STD_LOGIC --*************************************************************** FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS VARIABLE temp_return : STD_LOGIC; BEGIN IF (input = '0') THEN temp_return := '0'; ELSE temp_return := '1'; END IF; RETURN temp_return; END bit_to_sl; --*************************************************************** -- locally derived constants to determine memory shape --*************************************************************** CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A); CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B); CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B); CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A); CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B); CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B); TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0); TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0); TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC; TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC; --*************************************************************** -- memory initialization function --*************************************************************** IMPURE FUNCTION init_memory(DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0); write_width_a : INTEGER; depth : INTEGER; width : INTEGER) RETURN mem_array IS VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0')); FILE init_file : TEXT; VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0); VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0')); VARIABLE file_buffer : LINE; VARIABLE i : INTEGER := 0; VARIABLE j : INTEGER; VARIABLE k : INTEGER; VARIABLE ignore_line : BOOLEAN := false; VARIABLE good_data : BOOLEAN := false; VARIABLE char_tmp : CHARACTER; VARIABLE index : INTEGER; variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0'); variable data : std_logic_vector(255 downto 0) := (others => '0'); variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0'); variable k_slv : std_logic_vector(31 downto 0) := (others => '0'); variable i_slv : std_logic_vector(31 downto 0) := (others => '0'); VARIABLE disp_line : line := null; variable open_status : file_open_status; variable input_initf_tmp : mem_array ; variable input_initf : mem_array := (others => (others => '0')); file int_infile : text; variable data_line, data_line_tmp, out_data_line : line; variable slv_width : integer; VARIABLE d_l : LINE; BEGIN --Display output message indicating that the behavioral model is being --initialized -- Setup the default data -- Default data is with respect to write_port_A and may be wider -- or narrower than init_return width. The following loops map -- default data into the memory IF (C_USE_DEFAULT_DATA=1) THEN index := 0; FOR i IN 0 TO depth-1 LOOP FOR j IN 0 TO width-1 LOOP init_return(i)(j) := DEFAULT_DATA(index); index := (index + 1) MOD C_WRITE_WIDTH_A; END LOOP; END LOOP; END IF; -- Read in the .mif file -- The init data is formatted with respect to write port A dimensions. -- The init_return vector is formatted with respect to minimum width and -- maximum depth; the following loops map the .mif file into the memory IF (C_LOAD_INIT_FILE=1) THEN file_open(init_file, C_INIT_FILE_NAME, read_mode); i := 0; WHILE (i < depth AND NOT endfile(init_file)) LOOP mem_vector := (OTHERS => '0'); readline(init_file, file_buffer); read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0)); FOR j IN 0 TO write_width_a-1 LOOP IF (j MOD width = 0 AND j /= 0) THEN i := i + 1; END IF; init_return(i)(j MOD width) := bit_to_sl(mem_vector(j)); END LOOP; i := i + 1; END LOOP; file_close(init_file); END IF; --Display output message indicating that the behavioral model is done --initializing ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE; if (C_USE_BRAM_BLOCK = 1) then --Display output message indicating that the behavioral model is being --initialized -- Read in the .mem file -- The init data is formatted with respect to write port A dimensions. -- The init_return vector is formatted with respect to minimum width and -- maximum depth; the following loops map the .mif file into the memory IF (C_INIT_FILE /= "NONE") then file_open(open_status, int_infile, C_INIT_FILE, read_mode); while not endfile(int_infile) loop readline(int_infile, data_line); while (data_line /= null and data_line'length > 0) loop if (data_line(data_line'low to data_line'low + 1) = "//") then deallocate(data_line); elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then deallocate(data_line); elsif (data_line(data_line'low to data_line'low + 1) = "/*") then deallocate(data_line); ignore_line := true; elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then deallocate(data_line); ignore_line := false; elsif (ignore_line = false and data_line(data_line'low) = '@') then read(data_line, char_tmp); hread(data_line, init_addr_slv, good_data); i := SLV_TO_INT(init_addr_slv); elsif (ignore_line = false) then hread(data_line, input_initf_tmp(i), good_data); init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0); if (good_data = true) then i := i + 1; end if; else deallocate(data_line); end if; end loop; end loop; file_close(int_infile); END IF; END IF; RETURN init_return; END FUNCTION; --*************************************************************** -- memory type constants --*************************************************************** CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0; CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1; CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2; CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3; CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4; --*************************************************************** -- memory configuration constant functions --*************************************************************** --get_single_port ----------------- FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS BEGIN IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN RETURN 1; ELSE RETURN 0; END IF; END get_single_port; --get_is_rom -------------- FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS BEGIN IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN RETURN 1; ELSE RETURN 0; END IF; END get_is_rom; --get_has_a_write ------------------ FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS BEGIN IF (IS_ROM=0) THEN RETURN 1; ELSE RETURN 0; END IF; END get_has_a_write; --get_has_b_write ------------------ FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS BEGIN IF (mem_type=MEM_TYPE_TDP_RAM) THEN RETURN 1; ELSE RETURN 0; END IF; END get_has_b_write; --get_has_a_read ------------------ FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS BEGIN IF (mem_type=MEM_TYPE_SDP_RAM) THEN RETURN 0; ELSE RETURN 1; END IF; END get_has_a_read; --get_has_b_read ------------------ FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS BEGIN IF (SINGLE_PORT=1) THEN RETURN 0; ELSE RETURN 1; END IF; END get_has_b_read; --get_has_b_port ------------------ FUNCTION get_has_b_port(HAS_B_READ : INTEGER; HAS_B_WRITE : INTEGER) RETURN INTEGER IS BEGIN IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN RETURN 1; ELSE RETURN 0; END IF; END get_has_b_port; --get_num_output_stages ----------------------- FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER; has_mux_output_regs : INTEGER; mux_pipeline_stages : INTEGER) RETURN INTEGER IS VARIABLE actual_mux_pipeline_stages : INTEGER; BEGIN -- Mux pipeline stages can be non-zero only when there is a mux -- output register. IF (has_mux_output_regs=1) THEN actual_mux_pipeline_stages := mux_pipeline_stages; ELSE actual_mux_pipeline_stages := 0; END IF; RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs; END get_num_output_stages; --*************************************************************************** -- Component declaration of the VARIABLE depth output register stage --*************************************************************************** COMPONENT BLK_MEM_GEN_v8_2_output_stage GENERIC ( C_FAMILY : STRING := "virtex7"; C_XDEVICEFAMILY : STRING := "virtex7"; C_RST_TYPE : STRING := "SYNC"; C_HAS_RST : INTEGER := 0; C_RSTRAM : INTEGER := 0; C_RST_PRIORITY : STRING := "CE"; init_val : STD_LOGIC_VECTOR; C_HAS_EN : INTEGER := 0; C_HAS_REGCE : INTEGER := 0; C_DATA_WIDTH : INTEGER := 32; C_ADDRB_WIDTH : INTEGER := 10; C_HAS_MEM_OUTPUT_REGS : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; C_USE_ECC : INTEGER := 0; NUM_STAGES : INTEGER := 1; C_EN_ECC_PIPE : INTEGER := 0; FLOP_DELAY : TIME := 100 ps); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; REGCE : IN STD_LOGIC; EN : IN STD_LOGIC; DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); SBITERR_IN_I : IN STD_LOGIC; DBITERR_IN_I : IN STD_LOGIC; SBITERR : OUT STD_LOGIC; DBITERR : OUT STD_LOGIC; RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); ECCPIPECE : IN STD_LOGIC; RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ); END COMPONENT BLK_MEM_GEN_v8_2_output_stage; COMPONENT BLK_MEM_GEN_v8_2_softecc_output_reg_stage GENERIC ( C_DATA_WIDTH : INTEGER := 32; C_ADDRB_WIDTH : INTEGER := 10; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; FLOP_DELAY : TIME := 100 ps ); PORT ( CLK : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); SBITERR_IN : IN STD_LOGIC; DBITERR_IN : IN STD_LOGIC; SBITERR : OUT STD_LOGIC; DBITERR : OUT STD_LOGIC; RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ); END COMPONENT BLK_MEM_GEN_v8_2_softecc_output_reg_stage; --****************************************************** -- locally derived constants to assist memory access --****************************************************** CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH; CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH; CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH; CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH; --****************************************************** -- To modify the LSBs of the 'wider' data to the actual -- address value --****************************************************** CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A; CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A; CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B; CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B; --****************************************************** -- FUNCTION : log2roundup --****************************************************** FUNCTION log2roundup ( data_value : INTEGER) RETURN INTEGER IS VARIABLE width : INTEGER := 0; VARIABLE cnt : INTEGER := 1; BEGIN IF (data_value <= 1) THEN width := 0; ELSE WHILE (cnt < data_value) LOOP width := width + 1; cnt := cnt *2; END LOOP; END IF; RETURN width; END log2roundup; ----------------------------------------------------------------------------- -- FUNCTION : log2int ----------------------------------------------------------------------------- FUNCTION log2int ( data_value : INTEGER) RETURN INTEGER IS VARIABLE width : INTEGER := 0; VARIABLE cnt : INTEGER := data_value; BEGIN WHILE (cnt >1) LOOP width := width + 1; cnt := cnt/2; END LOOP; RETURN width; END log2int; ------------------------------------------------------------------------------ -- FUNCTION: if_then_else -- This function is used to implement an IF..THEN when such a statement is not -- allowed. ------------------------------------------------------------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : INTEGER; false_case : INTEGER) RETURN INTEGER IS VARIABLE retval : INTEGER := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; --****************************************************** -- Other constants and signals --****************************************************** CONSTANT COLL_DELAY : TIME := 100 ps; -- default data vector CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := hex_to_std_logic_vector(C_DEFAULT_DATA, C_WRITE_WIDTH_A); CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0))))); -- the init memory SIGNAL SIGNAL memory_i : mem_array; SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0); SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0); -- write mode constants CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) := write_mode_to_vector(C_WRITE_MODE_A); CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) := write_mode_to_vector(C_WRITE_MODE_B); CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) := WRITE_MODE_A & WRITE_MODE_B; -- reset values CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) := hex_to_std_logic_vector(C_INITA_VAL, C_READ_WIDTH_A); CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := hex_to_std_logic_vector(C_INITB_VAL, C_READ_WIDTH_B); -- memory output 'latches' SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) := INITA_VAL; SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := INITB_VAL; SIGNAL sbiterr_in : STD_LOGIC := '0'; SIGNAL sbiterr_sdp : STD_LOGIC := '0'; SIGNAL dbiterr_in : STD_LOGIC := '0'; SIGNAL dbiterr_sdp : STD_LOGIC := '0'; SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL sbiterr_i : STD_LOGIC := '0'; SIGNAL dbiterr_i : STD_LOGIC := '0'; -- memory configuration constants ----------------------------------------------- CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE); CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE); CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM); CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE); CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE); CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT); CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE); CONSTANT NUM_OUTPUT_STAGES_A : INTEGER := get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A, C_MUX_PIPELINE_STAGES); CONSTANT NUM_OUTPUT_STAGES_B : INTEGER := get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B, C_MUX_PIPELINE_STAGES); CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ----------------------------------------------------------------------------- -- DEBUG CONTROL -- DEBUG=0 : Debug output OFF -- DEBUG=1 : Some debug info printed ----------------------------------------------------------------------------- CONSTANT DEBUG : INTEGER := 0; -- internal signals ----------------------------------------------- SIGNAL ena_i : STD_LOGIC; SIGNAL enb_i : STD_LOGIC; SIGNAL reseta_i : STD_LOGIC; SIGNAL resetb_i : STD_LOGIC; SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0); SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0); SIGNAL rea_i : STD_LOGIC; SIGNAL reb_i : STD_LOGIC; SIGNAL message_complete : BOOLEAN := false; SIGNAL rsta_outp_stage : STD_LOGIC := '0'; SIGNAL rstb_outp_stage : STD_LOGIC := '0'; --********************************************************* --FUNCTION : Collision check --********************************************************* FUNCTION collision_check (addr_a : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0); iswrite_a : BOOLEAN; addr_b : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); iswrite_b : BOOLEAN) RETURN BOOLEAN IS VARIABLE c_aw_bw : INTEGER; VARIABLE c_aw_br : INTEGER; VARIABLE c_ar_bw : INTEGER; VARIABLE write_addr_a_width : INTEGER; VARIABLE read_addr_a_width : INTEGER; VARIABLE write_addr_b_width : INTEGER; VARIABLE read_addr_b_width : INTEGER; BEGIN c_aw_bw := 0; c_aw_br := 0; c_ar_bw := 0; -- Determine the effective address widths FOR each of the 4 ports write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV); read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV); write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV); read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV); --Look FOR a write-write collision. In order FOR a write-write --collision to exist, both ports must have a write transaction. IF (iswrite_a AND iswrite_b) THEN IF (write_addr_a_width > write_addr_b_width) THEN --write_addr_b_width is smaller, so scale both addresses to that -- width FOR comparing write_addr_a and write_addr_b --addr_a starts as C_ADDRA_WIDTH, -- scale it down to write_addr_b_width --addr_b starts as C_ADDRB_WIDTH, -- scale it down to write_addr_b_width --Once both are scaled to write_addr_b_width, compare. IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) = (conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN c_aw_bw := 1; ELSE c_aw_bw := 0; END IF; ELSE --write_addr_a_width is smaller, so scale both addresses to that -- width FOR comparing write_addr_a and write_addr_b --addr_a starts as C_ADDRA_WIDTH, -- scale it down to write_addr_a_width --addr_b starts as C_ADDRB_WIDTH, -- scale it down to write_addr_a_width --Once both are scaled to write_addr_a_width, compare. IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) = (conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN c_aw_bw := 1; ELSE c_aw_bw := 0; END IF; END IF; --width END IF; --iswrite_a and iswrite_b --If the B port is reading (which means it is enabled - so could be -- a TX_WRITE or TX_READ), then check FOR a write-read collision). --This could happen whether or not a write-write collision exists due -- to asymmetric write/read ports. IF (iswrite_a) THEN IF (write_addr_a_width > read_addr_b_width) THEN --read_addr_b_width is smaller, so scale both addresses to that -- width FOR comparing write_addr_a and read_addr_b --addr_a starts as C_ADDRA_WIDTH, -- scale it down to read_addr_b_width --addr_b starts as C_ADDRB_WIDTH, -- scale it down to read_addr_b_width --Once both are scaled to read_addr_b_width, compare. IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) = (conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN c_aw_br := 1; ELSE c_aw_br := 0; END IF; ELSE --write_addr_a_width is smaller, so scale both addresses to that -- width FOR comparing write_addr_a and read_addr_b --addr_a starts as C_ADDRA_WIDTH, -- scale it down to write_addr_a_width --addr_b starts as C_ADDRB_WIDTH, -- scale it down to write_addr_a_width --Once both are scaled to write_addr_a_width, compare. IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) = (conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN c_aw_br := 1; ELSE c_aw_br := 0; END IF; END IF; --width END IF; --iswrite_a --If the A port is reading (which means it is enabled - so could be -- a TX_WRITE or TX_READ), then check FOR a write-read collision). --This could happen whether or not a write-write collision exists due -- to asymmetric write/read ports. IF (iswrite_b) THEN IF (read_addr_a_width > write_addr_b_width) THEN --write_addr_b_width is smaller, so scale both addresses to that -- width FOR comparing read_addr_a and write_addr_b --addr_a starts as C_ADDRA_WIDTH, -- scale it down to write_addr_b_width --addr_b starts as C_ADDRB_WIDTH, -- scale it down to write_addr_b_width --Once both are scaled to write_addr_b_width, compare. IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) = (conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN c_ar_bw := 1; ELSE c_ar_bw := 0; END IF; ELSE --read_addr_a_width is smaller, so scale both addresses to that -- width FOR comparing read_addr_a and write_addr_b --addr_a starts as C_ADDRA_WIDTH, -- scale it down to read_addr_a_width --addr_b starts as C_ADDRB_WIDTH, -- scale it down to read_addr_a_width --Once both are scaled to read_addr_a_width, compare. IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) = (conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN c_ar_bw := 1; ELSE c_ar_bw := 0; END IF; END IF; --width END IF; --iswrite_b RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1); END FUNCTION collision_check; BEGIN -- Architecture ----------------------------------------------------------------------------- -- SOFTECC and ECC SBITERR/DBITERR Outputs -- The ECC Behavior is modeled by the behavioral models only for Virtex-6. -- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6. -- For Virtex-5, these outputs will be tied to 0. ----------------------------------------------------------------------------- SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0'; DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0'; RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0'); ----------------------------------------------- -- This effectively wires off optional inputs ----------------------------------------------- ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1'; enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1'; wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0; web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0; rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0'; reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0'; -- these signals reset the memory latches -- For the special reset behaviors in some of the families, the C_RSTRAM -- attribute of the corresponding port is used to indicate if the latch is -- reset or not. reseta_i <= RSTA WHEN ((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR (C_HAS_RSTA=1 AND C_RSTRAM_A=1)) ELSE '0'; resetb_i <= RSTB WHEN ((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR (C_HAS_RSTB=1 AND C_RSTRAM_B=1) ) ELSE '0'; --*************************************************************************** -- This is the main PROCESS which includes the memory VARIABLE and the read -- and write procedures. It also schedules read and write operations --*************************************************************************** PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i) -- Initialize the init memory array ------------------------------------ VARIABLE memory : mem_array := init_memory(DEFAULT_DATA, C_WRITE_WIDTH_A, MAX_DEPTH, MIN_WIDTH); -- Initialize the mem memory array ------------------------------------ VARIABLE softecc_sbiterr_arr : softecc_err_array; VARIABLE softecc_dbiterr_arr : softecc_err_array; VARIABLE sbiterr_arr : ecc_err_array; VARIABLE dbiterr_arr : ecc_err_array; CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11"; CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0'); VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ; VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0); --*********************************** -- procedures to access the memory --*********************************** -- write_a ---------- PROCEDURE write_a (addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0); byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0); data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0); inj_sbiterr : IN STD_LOGIC; inj_dbiterr : IN STD_LOGIC) IS VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0); VARIABLE address_i : INTEGER; VARIABLE i : INTEGER; VARIABLE message : LINE; VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN -- Block Memory Generator non-cycle-accurate message ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior." SEVERITY NOTE; message_complete <= true; -- Shift the address by the ratio address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV); IF (address_i >= C_WRITE_DEPTH_A) THEN IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN ASSERT FALSE REPORT C_CORENAME & " WARNING: Address " & INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write" SEVERITY WARNING; END IF; -- valid address ELSE -- Combine w/ byte writes IF (C_USE_BYTE_WEA = 1) THEN -- Get the current memory contents FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) := memory(address_i*WRITE_WIDTH_RATIO_A + i); END LOOP; -- Apply incoming bytes FOR i IN 0 TO C_WEA_WIDTH-1 LOOP IF (byte_en(i) = '1') THEN current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i) := data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i); END IF; END LOOP; -- No byte-writes, overwrite the whole word ELSE current_contents := data; END IF; -- Insert double bit errors: IF (C_USE_ECC = 1) THEN IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN current_contents(0) := NOT(current_contents(0)); current_contents(1) := NOT(current_contents(1)); END IF; END IF; -- Insert double bit errors: IF (C_USE_SOFTECC=1) THEN IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0); doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1); doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2); current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0); END IF; END IF; IF(DEBUG=1) THEN current_contents_var := current_contents; --for debugging current END IF; -- Write data to memory FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP memory(address_i*WRITE_WIDTH_RATIO_A + i) := current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i); END LOOP; -- Store address at which error is injected: IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN sbiterr_arr(address_i) := '1'; ELSE sbiterr_arr(address_i) := '0'; END IF; IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN dbiterr_arr(address_i) := '1'; ELSE dbiterr_arr(address_i) := '0'; END IF; END IF; -- Store address at which softecc error is injected: IF (C_USE_SOFTECC = 1) THEN IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN softecc_sbiterr_arr(address_i) := '1'; ELSE softecc_sbiterr_arr(address_i) := '0'; END IF; IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN softecc_dbiterr_arr(address_i) := '1'; ELSE softecc_dbiterr_arr(address_i) := '0'; END IF; END IF; END IF; END PROCEDURE; -- write_b ---------- PROCEDURE write_b (addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0); data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); VARIABLE address_i : INTEGER; VARIABLE i : INTEGER; BEGIN -- Shift the address by the ratio address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV); IF (address_i >= C_WRITE_DEPTH_B) THEN IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN ASSERT FALSE REPORT C_CORENAME & " WARNING: Address " & INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write" SEVERITY WARNING; END IF; -- valid address ELSE -- Combine w/ byte writes IF (C_USE_BYTE_WEB = 1) THEN -- Get the current memory contents FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) := memory(address_i*WRITE_WIDTH_RATIO_B + i); END LOOP; -- Apply incoming bytes FOR i IN 0 TO C_WEB_WIDTH-1 LOOP IF (byte_en(i) = '1') THEN current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i) := data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i); END IF; END LOOP; -- No byte-writes, overwrite the whole word ELSE current_contents := data; END IF; -- Write data to memory FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP memory(address_i*WRITE_WIDTH_RATIO_B + i) := current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i); END LOOP; END IF; END PROCEDURE; -- read_a ---------- PROCEDURE read_a (addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0); reset : IN STD_LOGIC) IS VARIABLE address_i : INTEGER; VARIABLE i : INTEGER; BEGIN IF (reset = '1') THEN memory_out_a <= INITA_VAL AFTER FLOP_DELAY; ELSE -- Shift the address by the ratio address_i := (conv_integer(addr)/READ_ADDR_A_DIV); IF (address_i >= C_READ_DEPTH_A) THEN IF (C_DISABLE_WARN_BHV_RANGE=0) THEN ASSERT FALSE REPORT C_CORENAME & " WARNING: Address " & INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read" SEVERITY WARNING; END IF; memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY; -- valid address ELSE -- Increment through the 'partial' words in the memory FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <= memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY; END LOOP; END IF; END IF; END PROCEDURE; -- read_b ---------- PROCEDURE read_b (addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); reset : IN STD_LOGIC) IS VARIABLE address_i : INTEGER; VARIABLE i : INTEGER; BEGIN IF (reset = '1') THEN memory_out_b <= INITB_VAL AFTER FLOP_DELAY; sbiterr_in <= '0' AFTER FLOP_DELAY; dbiterr_in <= '0' AFTER FLOP_DELAY; rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY; ELSE -- Shift the address by the ratio address_i := (conv_integer(addr)/READ_ADDR_B_DIV); IF (address_i >= C_READ_DEPTH_B) THEN IF (C_DISABLE_WARN_BHV_RANGE=0) THEN ASSERT FALSE REPORT C_CORENAME & " WARNING: Address " & INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read" SEVERITY WARNING; END IF; memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY; sbiterr_in <= 'X' AFTER FLOP_DELAY; dbiterr_in <= 'X' AFTER FLOP_DELAY; rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY; -- valid address ELSE -- Increment through the 'partial' words in the memory FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <= memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY; END LOOP; --assert sbiterr and dbiterr signals IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN rdaddrecc_in <= addr AFTER FLOP_DELAY; IF (sbiterr_arr(address_i) = '1') THEN sbiterr_in <= '1' AFTER FLOP_DELAY; ELSE sbiterr_in <= '0' AFTER FLOP_DELAY; END IF; IF (dbiterr_arr(address_i) = '1') THEN dbiterr_in <= '1' AFTER FLOP_DELAY; ELSE dbiterr_in <= '0' AFTER FLOP_DELAY; END IF; --assert softecc sbiterr and dbiterr signals ELSIF (C_USE_SOFTECC = 1) THEN rdaddrecc_in <= addr AFTER FLOP_DELAY; IF (softecc_sbiterr_arr(address_i) = '1') THEN sbiterr_in <= '1' AFTER FLOP_DELAY; ELSE sbiterr_in <= '0' AFTER FLOP_DELAY; END IF; IF (softecc_dbiterr_arr(address_i) = '1') THEN dbiterr_in <= '1' AFTER FLOP_DELAY; ELSE dbiterr_in <= '0' AFTER FLOP_DELAY; END IF; ELSE sbiterr_in <= '0' AFTER FLOP_DELAY; dbiterr_in <= '0' AFTER FLOP_DELAY; rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY; END IF; END IF; END IF; END PROCEDURE; -- reset_a ---------- PROCEDURE reset_a (reset : IN STD_LOGIC) IS BEGIN IF (reset = '1') THEN memory_out_a <= INITA_VAL AFTER FLOP_DELAY; END IF; END PROCEDURE; -- reset_b ---------- PROCEDURE reset_b (reset : IN STD_LOGIC) IS BEGIN IF (reset = '1') THEN memory_out_b <= INITB_VAL AFTER FLOP_DELAY; END IF; END PROCEDURE; BEGIN -- begin the main PROCESS --*************************************************************************** -- These are the main blocks which schedule read and write operations -- Note that the reset priority feature at the latch stage is only supported -- for Spartan-6. For other families, the default priority at the latch stage -- is "CE" --*************************************************************************** -- Synchronous clocks: schedule port operations with respect to both -- write operating modes IF (C_COMMON_CLK=1) THEN IF (CLKA='1' AND CLKA'EVENT) THEN CASE WRITE_MODES IS WHEN "0000" => -- write_first write_first --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; --Read A IF (rea_i='1') THEN read_a(ADDRA, reseta_i); END IF; --Read B IF (reb_i='1') THEN read_b(ADDRB, resetb_i); END IF; WHEN "0100" => -- read_first write_first --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; --Read B IF (reb_i='1') THEN read_b(ADDRB, resetb_i); END IF; --Read A IF (rea_i='1') THEN read_a(ADDRA, reseta_i); END IF; --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; WHEN "0001" => -- write_first read_first --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Read A IF (rea_i='1') THEN read_a(ADDRA, reseta_i); END IF; --Read B IF (reb_i='1') THEN read_b(ADDRB, resetb_i); END IF; --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; WHEN "0101" => --read_first read_first --Read A IF (rea_i='1') THEN read_a(ADDRA, reseta_i); END IF; --Read B IF (reb_i='1') THEN read_b(ADDRB, resetb_i); END IF; --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; WHEN "0010" => -- write_first no_change --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Read A IF (rea_i='1') THEN read_a(ADDRA, reseta_i); END IF; --Read B IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN read_b(ADDRB, resetb_i); END IF; --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; WHEN "0110" => -- read_first no_change --Read A IF (rea_i='1') THEN read_a(ADDRA, reseta_i); END IF; --Read B IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN read_b(ADDRB, resetb_i); END IF; --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; WHEN "1000" => -- no_change write_first --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; --Read A IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN read_a(ADDRA, reseta_i); END IF; --Read B IF (reb_i='1') THEN read_b(ADDRB, resetb_i); END IF; WHEN "1001" => -- no_change read_first --Read B IF (reb_i='1') THEN read_b(ADDRB, resetb_i); END IF; --Read A IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN read_a(ADDRA, reseta_i); END IF; --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; WHEN "1010" => -- no_change no_change --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; --Read A IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN read_a(ADDRA, reseta_i); END IF; --Read B IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN read_b(ADDRB, resetb_i); END IF; WHEN OTHERS => ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR; END CASE; END IF; END IF; -- Synchronous clocks -- Asynchronous clocks: port operation is independent IF (C_COMMON_CLK=0) THEN IF (CLKA='1' AND CLKA'EVENT) THEN CASE WRITE_MODE_A IS WHEN "00" => -- write_first --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Read A IF (rea_i='1') THEN read_a(ADDRA, reseta_i); END IF; WHEN "01" => -- read_first --Read A IF (rea_i='1') THEN read_a(ADDRA, reseta_i); END IF; --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; WHEN "10" => -- no_change --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Read A IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN read_a(ADDRA, reseta_i); END IF; WHEN OTHERS => ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR; END CASE; END IF; IF (CLKB='1' AND CLKB'EVENT) THEN CASE WRITE_MODE_B IS WHEN "00" => -- write_first --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; --Read B IF (reb_i='1') THEN read_b(ADDRB, resetb_i); END IF; WHEN "01" => -- read_first --Read B IF (reb_i='1') THEN read_b(ADDRB, resetb_i); END IF; --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; WHEN "10" => -- no_change --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; --Read B IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN read_b(ADDRB, resetb_i); END IF; WHEN OTHERS => ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR; END CASE; END IF; END IF; -- Asynchronous clocks -- Assign the memory VARIABLE to the user_visible memory_i SIGNAL IF(DEBUG=1) THEN memory_i <= memory; doublebit_error_i <= doublebit_error; current_contents_i <= current_contents_var; END IF; END PROCESS; --******************************************************************** -- Instantiate the VARIABLE depth output stage --******************************************************************** -- Port A rsta_outp_stage <= RSTA and not sleep; rstb_outp_stage <= RSTB and not sleep; reg_a : BLK_MEM_GEN_v8_2_output_stage GENERIC MAP( C_FAMILY => C_FAMILY, C_XDEVICEFAMILY => C_XDEVICEFAMILY, C_RST_TYPE => "SYNC", C_HAS_RST => C_HAS_RSTA, C_RSTRAM => C_RSTRAM_A, C_RST_PRIORITY => C_RST_PRIORITY_A, init_val => INITA_VAL, C_HAS_EN => C_HAS_ENA, C_HAS_REGCE => C_HAS_REGCEA, C_DATA_WIDTH => C_READ_WIDTH_A, C_ADDRB_WIDTH => C_ADDRB_WIDTH, C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A, C_USE_SOFTECC => C_USE_SOFTECC, C_USE_ECC => C_USE_ECC, NUM_STAGES => NUM_OUTPUT_STAGES_A, C_EN_ECC_PIPE => C_EN_ECC_PIPE, FLOP_DELAY => FLOP_DELAY ) PORT MAP ( CLK => CLKA, RST => rsta_outp_stage, --RSTA, EN => ENA, REGCE => REGCEA, DIN_I => memory_out_a, DOUT => DOUTA, SBITERR_IN_I => '0', DBITERR_IN_I => '0', SBITERR => OPEN, DBITERR => OPEN, RDADDRECC_IN_I => (OTHERS => '0'), ECCPIPECE => '0', RDADDRECC => OPEN ); -- Port B reg_b : BLK_MEM_GEN_v8_2_output_stage GENERIC MAP( C_FAMILY => C_FAMILY, C_XDEVICEFAMILY => C_XDEVICEFAMILY, C_RST_TYPE => "SYNC", C_HAS_RST => C_HAS_RSTB, C_RSTRAM => C_RSTRAM_B, C_RST_PRIORITY => C_RST_PRIORITY_B, init_val => INITB_VAL, C_HAS_EN => C_HAS_ENB, C_HAS_REGCE => C_HAS_REGCEB, C_DATA_WIDTH => C_READ_WIDTH_B, C_ADDRB_WIDTH => C_ADDRB_WIDTH, C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B, C_USE_SOFTECC => C_USE_SOFTECC, C_USE_ECC => C_USE_ECC, NUM_STAGES => NUM_OUTPUT_STAGES_B, C_EN_ECC_PIPE => C_EN_ECC_PIPE, FLOP_DELAY => FLOP_DELAY ) PORT MAP ( CLK => CLKB, RST => rstb_outp_stage,--RSTB, EN => ENB, REGCE => REGCEB, DIN_I => memory_out_b, DOUT => doutb_i, SBITERR_IN_I => sbiterr_in, DBITERR_IN_I => dbiterr_in, SBITERR => sbiterr_i, DBITERR => dbiterr_i, RDADDRECC_IN_I => rdaddrecc_in, ECCPIPECE => ECCPIPECE, RDADDRECC => rdaddrecc_i ); --******************************************************************** -- Instantiate the input / Output Register stages --******************************************************************** output_reg_stage: BLK_MEM_GEN_v8_2_softecc_output_reg_stage GENERIC MAP( C_DATA_WIDTH => C_READ_WIDTH_B, C_ADDRB_WIDTH => C_ADDRB_WIDTH, C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B, C_USE_SOFTECC => C_USE_SOFTECC, FLOP_DELAY => FLOP_DELAY ) PORT MAP( CLK => CLKB, DIN => doutb_i, DOUT => DOUTB, SBITERR_IN => sbiterr_i, DBITERR_IN => dbiterr_i, SBITERR => sbiterr_sdp, DBITERR => dbiterr_sdp, RDADDRECC_IN => rdaddrecc_i, RDADDRECC => rdaddrecc_sdp ); --********************************* -- Synchronous collision checks --********************************* sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE PROCESS (CLKA) use IEEE.STD_LOGIC_TEXTIO.ALL; -- collision detect VARIABLE is_collision : BOOLEAN; VARIABLE message : LINE; BEGIN IF (CLKA='1' AND CLKA'EVENT) THEN -- Possible collision if both are enabled and the addresses match -- Not checking the collision condition when there is an 'x' on the Addr bus IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN is_collision := collision_check(ADDRA, wea_i/=WEA0, ADDRB, web_i/=WEB0); ELSE is_collision := false; END IF; -- If the write port is in READ_FIRST mode, there is no collision IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN is_collision := false; END IF; IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN is_collision := false; END IF; -- Only flag if one of the accesses is a write IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN write(message, C_CORENAME); write(message, STRING'(" WARNING: collision detected: ")); IF (wea_i/=WEA0) THEN write(message, STRING'("A write address: ")); ELSE write(message, STRING'("A read address: ")); END IF; write(message, ADDRA); IF (web_i/=WEB0) THEN write(message, STRING'(", B write address: ")); ELSE write(message, STRING'(", B read address: ")); END IF; write(message, ADDRB); write(message, LF); ASSERT false REPORT message.ALL SEVERITY WARNING; deallocate(message); END IF; END IF; END PROCESS; END GENERATE; --********************************* -- Asynchronous collision checks --********************************* async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0); SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0); SIGNAL ena_delay : STD_LOGIC; SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0); SIGNAL enb_delay : STD_LOGIC; BEGIN -- Delay A and B addresses in order to mimic setup/hold times PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i) BEGIN addra_delay <= ADDRA AFTER COLL_DELAY; wea_delay <= wea_i AFTER COLL_DELAY; ena_delay <= ena_i AFTER COLL_DELAY; addrb_delay <= ADDRB AFTER COLL_DELAY; web_delay <= web_i AFTER COLL_DELAY; enb_delay <= enb_i AFTER COLL_DELAY; END PROCESS; -- Do the checks w/rt A PROCESS (CLKA) use IEEE.STD_LOGIC_TEXTIO.ALL; VARIABLE is_collision_a : BOOLEAN; VARIABLE is_collision_delay_a : BOOLEAN; VARIABLE message : LINE; BEGIN -- Possible collision if both are enabled and the addresses match -- Not checking the collision condition when there is an 'x' on the Addr bus IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN is_collision_a := collision_check(ADDRA, wea_i/=WEA0, ADDRB, web_i/=WEB0); ELSE is_collision_a := false; END IF; IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN is_collision_delay_a := collision_check(ADDRA, wea_i/=WEA0, addrb_delay, web_delay/=WEB0); ELSE is_collision_delay_a := false; END IF; -- Only flag if B access is a write IF (is_collision_a AND web_i/=WEB0) THEN write(message, C_CORENAME); write(message, STRING'(" WARNING: collision detected: ")); IF (wea_i/=WEA0) THEN write(message, STRING'("A write address: ")); ELSE write(message, STRING'("A read address: ")); END IF; write(message, ADDRA); write(message, STRING'(", B write address: ")); write(message, ADDRB); write(message, LF); ASSERT false REPORT message.ALL SEVERITY WARNING; deallocate(message); ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN write(message, C_CORENAME); write(message, STRING'(" WARNING: collision detected: ")); IF (wea_i/=WEA0) THEN write(message, STRING'("A write address: ")); ELSE write(message, STRING'("A read address: ")); END IF; write(message, ADDRA); write(message, STRING'(", B write address: ")); write(message, addrb_delay); write(message, LF); ASSERT false REPORT message.ALL SEVERITY WARNING; deallocate(message); END IF; END PROCESS; -- Do the checks w/rt B PROCESS (CLKB) use IEEE.STD_LOGIC_TEXTIO.ALL; VARIABLE is_collision_b : BOOLEAN; VARIABLE is_collision_delay_b : BOOLEAN; VARIABLE message : LINE; BEGIN -- Possible collision if both are enabled and the addresses match -- Not checking the collision condition when there is an 'x' on the Addr bus IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN is_collision_b := collision_check(ADDRA, wea_i/=WEA0, ADDRB, web_i/=WEB0); ELSE is_collision_b := false; END IF; IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN is_collision_delay_b := collision_check(addra_delay, wea_delay/=WEA0, ADDRB, web_i/=WEB0); ELSE is_collision_delay_b := false; END IF; -- Only flag if A access is a write -- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228 IF (is_collision_b AND wea_i/=WEA0) THEN write(message, C_CORENAME); write(message, STRING'(" WARNING: collision detected: ")); write(message, STRING'("A write address: ")); write(message, ADDRA); IF (web_i/=WEB0) THEN write(message, STRING'(", B write address: ")); ELSE write(message, STRING'(", B read address: ")); END IF; write(message, ADDRB); write(message, LF); ASSERT false REPORT message.ALL SEVERITY WARNING; deallocate(message); ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN write(message, C_CORENAME); write(message, STRING'(" WARNING: collision detected: ")); write(message, STRING'("A write address: ")); write(message, addra_delay); IF (web_i/=WEB0) THEN write(message, STRING'(", B write address: ")); ELSE write(message, STRING'(", B read address: ")); END IF; write(message, ADDRB); write(message, LF); ASSERT false REPORT message.ALL SEVERITY WARNING; deallocate(message); END IF; END PROCESS; END GENERATE; END mem_module_behavioral; --****************************************************************************** -- Top module that wraps SoftECC Input register stage and the main memory module -- -- This module is the top-level of behavioral model --****************************************************************************** LIBRARY STD; USE STD.TEXTIO.ALL; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY blk_mem_gen_v8_2 IS GENERIC ( C_CORENAME : STRING := "blk_mem_gen_v8_2"; C_FAMILY : STRING := "virtex7"; C_XDEVICEFAMILY : STRING := "virtex7"; C_ELABORATION_DIR : STRING := ""; C_INTERFACE_TYPE : INTEGER := 0; C_USE_BRAM_BLOCK : INTEGER := 0; C_ENABLE_32BIT_ADDRESS : INTEGER := 0; C_CTRL_ECC_ALGO : STRING := "NONE"; C_AXI_TYPE : INTEGER := 0; C_AXI_SLAVE_TYPE : INTEGER := 0; C_HAS_AXI_ID : INTEGER := 0; C_AXI_ID_WIDTH : INTEGER := 4; C_MEM_TYPE : INTEGER := 2; C_BYTE_SIZE : INTEGER := 8; C_ALGORITHM : INTEGER := 2; C_PRIM_TYPE : INTEGER := 3; C_LOAD_INIT_FILE : INTEGER := 0; C_INIT_FILE_NAME : STRING := ""; C_INIT_FILE : STRING := ""; C_USE_DEFAULT_DATA : INTEGER := 0; C_DEFAULT_DATA : STRING := ""; --C_RST_TYPE : STRING := "SYNC"; C_HAS_RSTA : INTEGER := 0; C_RST_PRIORITY_A : STRING := "CE"; C_RSTRAM_A : INTEGER := 0; C_INITA_VAL : STRING := ""; C_HAS_ENA : INTEGER := 1; C_HAS_REGCEA : INTEGER := 0; C_USE_BYTE_WEA : INTEGER := 0; C_WEA_WIDTH : INTEGER := 1; C_WRITE_MODE_A : STRING := "WRITE_FIRST"; C_WRITE_WIDTH_A : INTEGER := 32; C_READ_WIDTH_A : INTEGER := 32; C_WRITE_DEPTH_A : INTEGER := 64; C_READ_DEPTH_A : INTEGER := 64; C_ADDRA_WIDTH : INTEGER := 6; C_HAS_RSTB : INTEGER := 0; C_RST_PRIORITY_B : STRING := "CE"; C_RSTRAM_B : INTEGER := 0; C_INITB_VAL : STRING := ""; C_HAS_ENB : INTEGER := 1; C_HAS_REGCEB : INTEGER := 0; C_USE_BYTE_WEB : INTEGER := 0; C_WEB_WIDTH : INTEGER := 1; C_WRITE_MODE_B : STRING := "WRITE_FIRST"; C_WRITE_WIDTH_B : INTEGER := 32; C_READ_WIDTH_B : INTEGER := 32; C_WRITE_DEPTH_B : INTEGER := 64; C_READ_DEPTH_B : INTEGER := 64; C_ADDRB_WIDTH : INTEGER := 6; C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0; C_MUX_PIPELINE_STAGES : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; C_USE_ECC : INTEGER := 0; C_EN_ECC_PIPE : INTEGER := 0; C_HAS_INJECTERR : INTEGER := 0; C_SIM_COLLISION_CHECK : STRING := "NONE"; C_COMMON_CLK : INTEGER := 1; C_DISABLE_WARN_BHV_COLL : INTEGER := 0; C_EN_SLEEP_PIN : INTEGER := 0; C_USE_URAM : integer := 0; C_EN_RDADDRA_CHG : integer := 0; C_EN_RDADDRB_CHG : integer := 0; C_EN_DEEPSLEEP_PIN : integer := 0; C_EN_SHUTDOWN_PIN : integer := 0; C_DISABLE_WARN_BHV_RANGE : INTEGER := 0; C_COUNT_36K_BRAM : string := ""; C_COUNT_18K_BRAM : string := ""; C_EST_POWER_SUMMARY : string := "" ); PORT ( clka : IN STD_LOGIC := '0'; rsta : IN STD_LOGIC := '0'; ena : IN STD_LOGIC := '1'; regcea : IN STD_LOGIC := '1'; wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0'); dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0); clkb : IN STD_LOGIC := '0'; rstb : IN STD_LOGIC := '0'; enb : IN STD_LOGIC := '1'; regceb : IN STD_LOGIC := '1'; web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0'); doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0); injectsbiterr : IN STD_LOGIC := '0'; injectdbiterr : IN STD_LOGIC := '0'; sbiterr : OUT STD_LOGIC := '0'; dbiterr : OUT STD_LOGIC := '0'; rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); eccpipece : in std_logic := '0'; sleep : in std_logic := '0'; deepsleep : in std_logic := '0'; shutdown : in std_logic := '0'; -- AXI BMG Input and Output Port Declarations -- AXI Global Signals s_aclk : IN STD_LOGIC := '0'; s_aresetn : IN STD_LOGIC := '0'; -- axi full/lite slave Write (write side) s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); s_axi_awvalid : IN STD_LOGIC := '0'; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wlast : IN STD_LOGIC := '0'; s_axi_wvalid : IN STD_LOGIC := '0'; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC := '0'; -- axi full/lite slave Read (Write side) s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); s_axi_arvalid : IN STD_LOGIC := '0'; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC := '0'; -- axi full/lite sideband Signals s_axi_injectsbiterr : IN STD_LOGIC := '0'; s_axi_injectdbiterr : IN STD_LOGIC := '0'; s_axi_sbiterr : OUT STD_LOGIC := '0'; s_axi_dbiterr : OUT STD_LOGIC := '0'; s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ); END blk_mem_gen_v8_2; --****************************** -- Port and Generic Definitions --****************************** --------------------------------------------------------------------------- -- Generic Definitions --------------------------------------------------------------------------- -- C_CORENAME : Instance name of the Block Memory Generator core -- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following -- options are available - "spartan3", "spartan6", -- "virtex4", "virtex5", "virtex6l" and "virtex6". -- C_MEM_TYPE : Designates memory type. -- It can be -- 0 - Single Port Memory -- 1 - Simple Dual Port Memory -- 2 - True Dual Port Memory -- 3 - Single Port Read Only Memory -- 4 - Dual Port Read Only Memory -- C_BYTE_SIZE : Size of a byte (8 or 9 bits) -- C_ALGORITHM : Designates the algorithm method used -- for constructing the memory. -- It can be Fixed_Primitives, Minimum_Area or -- Low_Power -- C_PRIM_TYPE : Designates the user selected primitive used to -- construct the memory. -- -- C_LOAD_INIT_FILE : Designates the use of an initialization file to -- initialize memory contents. -- C_INIT_FILE_NAME : Memory initialization file name. -- C_USE_DEFAULT_DATA : Designates whether to fill remaining -- initialization space with default data -- C_DEFAULT_DATA : Default value of all memory locations -- not initialized by the memory -- initialization file. -- C_RST_TYPE : Type of reset - Synchronous or Asynchronous -- -- C_HAS_RSTA : Determines the presence of the RSTA port -- C_RST_PRIORITY_A : Determines the priority between CE and SR for -- Port A. -- C_RSTRAM_A : Determines if special reset behavior is used for -- Port A -- C_INITA_VAL : The initialization value for Port A -- C_HAS_ENA : Determines the presence of the ENA port -- C_HAS_REGCEA : Determines the presence of the REGCEA port -- C_USE_BYTE_WEA : Determines if the Byte Write is used or not. -- C_WEA_WIDTH : The width of the WEA port -- C_WRITE_MODE_A : Configurable write mode for Port A. It can be -- WRITE_FIRST, READ_FIRST or NO_CHANGE. -- C_WRITE_WIDTH_A : Memory write width for Port A. -- C_READ_WIDTH_A : Memory read width for Port A. -- C_WRITE_DEPTH_A : Memory write depth for Port A. -- C_READ_DEPTH_A : Memory read depth for Port A. -- C_ADDRA_WIDTH : Width of the ADDRA input port -- C_HAS_RSTB : Determines the presence of the RSTB port -- C_RST_PRIORITY_B : Determines the priority between CE and SR for -- Port B. -- C_RSTRAM_B : Determines if special reset behavior is used for -- Port B -- C_INITB_VAL : The initialization value for Port B -- C_HAS_ENB : Determines the presence of the ENB port -- C_HAS_REGCEB : Determines the presence of the REGCEB port -- C_USE_BYTE_WEB : Determines if the Byte Write is used or not. -- C_WEB_WIDTH : The width of the WEB port -- C_WRITE_MODE_B : Configurable write mode for Port B. It can be -- WRITE_FIRST, READ_FIRST or NO_CHANGE. -- C_WRITE_WIDTH_B : Memory write width for Port B. -- C_READ_WIDTH_B : Memory read width for Port B. -- C_WRITE_DEPTH_B : Memory write depth for Port B. -- C_READ_DEPTH_B : Memory read depth for Port B. -- C_ADDRB_WIDTH : Width of the ADDRB input port -- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output -- of the RAM primitive for Port A. -- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output -- of the RAM primitive for Port B. -- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output -- of the MUX for Port A. -- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output -- of the MUX for Port B. -- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in -- between the muxes. -- C_USE_SOFTECC : Determines if the Soft ECC feature is used or -- not. Only applicable Spartan-6 -- C_USE_ECC : Determines if the ECC feature is used or -- not. Only applicable for V5 and V6 -- C_HAS_INJECTERR : Determines if the error injection pins -- are present or not. If the ECC feature -- is not used, this value is defaulted to -- 0, else the following are the allowed -- values: -- 0 : No INJECTSBITERR or INJECTDBITERR pins -- 1 : Only INJECTSBITERR pin exists -- 2 : Only INJECTDBITERR pin exists -- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist -- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision -- warnings. It can be "ALL", "NONE", -- "Warnings_Only" or "Generate_X_Only". -- C_COMMON_CLK : Determins if the core has a single CLK input. -- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings -- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range -- warnings --------------------------------------------------------------------------- -- Port Definitions --------------------------------------------------------------------------- -- CLKA : Clock to synchronize all read and write operations of Port A. -- RSTA : Reset input to reset memory outputs to a user-defined -- reset state for Port A. -- ENA : Enable all read and write operations of Port A. -- REGCEA : Register Clock Enable to control each pipeline output -- register stages for Port A. -- WEA : Write Enable to enable all write operations of Port A. -- ADDRA : Address of Port A. -- DINA : Data input of Port A. -- DOUTA : Data output of Port A. -- CLKB : Clock to synchronize all read and write operations of Port B. -- RSTB : Reset input to reset memory outputs to a user-defined -- reset state for Port B. -- ENB : Enable all read and write operations of Port B. -- REGCEB : Register Clock Enable to control each pipeline output -- register stages for Port B. -- WEB : Write Enable to enable all write operations of Port B. -- ADDRB : Address of Port B. -- DINB : Data input of Port B. -- DOUTB : Data output of Port B. -- INJECTSBITERR : Single Bit ECC Error Injection Pin. -- INJECTDBITERR : Double Bit ECC Error Injection Pin. -- SBITERR : Output signal indicating that a Single Bit ECC Error has been -- detected and corrected. -- DBITERR : Output signal indicating that a Double Bit ECC Error has been -- detected. -- RDADDRECC : Read Address Output signal indicating address at which an -- ECC error has occurred. --------------------------------------------------------------------------- ARCHITECTURE behavioral OF BLK_MEM_GEN_v8_2 IS COMPONENT BLK_MEM_GEN_v8_2_mem_module GENERIC ( C_CORENAME : STRING := "blk_mem_gen_v8_2"; C_FAMILY : STRING := "virtex7"; C_XDEVICEFAMILY : STRING := "virtex7"; C_USE_BRAM_BLOCK : INTEGER := 0; C_ENABLE_32BIT_ADDRESS : INTEGER := 0; C_MEM_TYPE : INTEGER := 2; C_BYTE_SIZE : INTEGER := 8; C_ALGORITHM : INTEGER := 2; C_PRIM_TYPE : INTEGER := 3; C_LOAD_INIT_FILE : INTEGER := 0; C_INIT_FILE_NAME : STRING := ""; C_INIT_FILE : STRING := ""; C_USE_DEFAULT_DATA : INTEGER := 0; C_DEFAULT_DATA : STRING := ""; C_RST_TYPE : STRING := "SYNC"; C_HAS_RSTA : INTEGER := 0; C_RST_PRIORITY_A : STRING := "CE"; C_RSTRAM_A : INTEGER := 0; C_INITA_VAL : STRING := ""; C_HAS_ENA : INTEGER := 1; C_HAS_REGCEA : INTEGER := 0; C_USE_BYTE_WEA : INTEGER := 0; C_WEA_WIDTH : INTEGER := 1; C_WRITE_MODE_A : STRING := "WRITE_FIRST"; C_WRITE_WIDTH_A : INTEGER := 32; C_READ_WIDTH_A : INTEGER := 32; C_WRITE_DEPTH_A : INTEGER := 64; C_READ_DEPTH_A : INTEGER := 64; C_ADDRA_WIDTH : INTEGER := 6; C_HAS_RSTB : INTEGER := 0; C_RST_PRIORITY_B : STRING := "CE"; C_RSTRAM_B : INTEGER := 0; C_INITB_VAL : STRING := ""; C_HAS_ENB : INTEGER := 1; C_HAS_REGCEB : INTEGER := 0; C_USE_BYTE_WEB : INTEGER := 0; C_WEB_WIDTH : INTEGER := 1; C_WRITE_MODE_B : STRING := "WRITE_FIRST"; C_WRITE_WIDTH_B : INTEGER := 32; C_READ_WIDTH_B : INTEGER := 32; C_WRITE_DEPTH_B : INTEGER := 64; C_READ_DEPTH_B : INTEGER := 64; C_ADDRB_WIDTH : INTEGER := 6; C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0; C_MUX_PIPELINE_STAGES : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; C_USE_ECC : INTEGER := 0; C_HAS_INJECTERR : INTEGER := 0; C_SIM_COLLISION_CHECK : STRING := "NONE"; C_COMMON_CLK : INTEGER := 1; FLOP_DELAY : TIME := 100 ps; C_DISABLE_WARN_BHV_COLL : INTEGER := 0; C_EN_ECC_PIPE : INTEGER := 0; C_DISABLE_WARN_BHV_RANGE : INTEGER := 0 ); PORT ( CLKA : IN STD_LOGIC := '0'; RSTA : IN STD_LOGIC := '0'; ENA : IN STD_LOGIC := '1'; REGCEA : IN STD_LOGIC := '1'; WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0'); DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0); CLKB : IN STD_LOGIC := '0'; RSTB : IN STD_LOGIC := '0'; ENB : IN STD_LOGIC := '1'; REGCEB : IN STD_LOGIC := '1'; WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0'); DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0); INJECTSBITERR : IN STD_LOGIC := '0'; INJECTDBITERR : IN STD_LOGIC := '0'; ECCPIPECE : IN STD_LOGIC; SLEEP : IN STD_LOGIC; SBITERR : OUT STD_LOGIC; DBITERR : OUT STD_LOGIC; RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ); END COMPONENT BLK_MEM_GEN_v8_2_mem_module; COMPONENT blk_mem_axi_regs_fwd_v8_2 IS GENERIC( C_DATA_WIDTH : INTEGER := 8 ); PORT ( ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; S_VALID : IN STD_LOGIC; S_READY : OUT STD_LOGIC; S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); M_VALID : OUT STD_LOGIC; M_READY : IN STD_LOGIC; M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ); END COMPONENT blk_mem_axi_regs_fwd_v8_2; COMPONENT blk_mem_axi_read_wrapper_beh GENERIC ( -- AXI Interface related parameters start here C_INTERFACE_TYPE : integer := 0; C_AXI_TYPE : integer := 0; C_AXI_SLAVE_TYPE : integer := 0; C_MEMORY_TYPE : integer := 0; C_WRITE_WIDTH_A : integer := 4; C_WRITE_DEPTH_A : integer := 32; C_ADDRA_WIDTH : integer := 12; C_AXI_PIPELINE_STAGES : integer := 0; C_AXI_ARADDR_WIDTH : integer := 12; C_HAS_AXI_ID : integer := 0; C_AXI_ID_WIDTH : integer := 4; C_ADDRB_WIDTH : integer := 12 ); PORT ( -- AXI Global Signals S_ACLK : IN std_logic; S_ARESETN : IN std_logic; -- AXI Full/Lite Slave Read (Read side) S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0'); S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0'); S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARVALID : IN std_logic := '0'; S_AXI_ARREADY : OUT std_logic; S_AXI_RLAST : OUT std_logic; S_AXI_RVALID : OUT std_logic; S_AXI_RREADY : IN std_logic := '0'; S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0'); S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0'); -- AXI Full/Lite Read Address Signals to BRAM S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0); S_AXI_RD_EN : OUT std_logic ); END COMPONENT blk_mem_axi_read_wrapper_beh; COMPONENT blk_mem_axi_write_wrapper_beh GENERIC ( -- AXI Interface related parameters start here C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full; C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE; C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM; C_WRITE_DEPTH_A : integer := 0; C_AXI_AWADDR_WIDTH : integer := 32; C_ADDRA_WIDTH : integer := 12; C_AXI_WDATA_WIDTH : integer := 32; C_HAS_AXI_ID : integer := 0; C_AXI_ID_WIDTH : integer := 4; -- AXI OUTSTANDING WRITES C_AXI_OS_WR : integer := 2 ); PORT ( -- AXI Global Signals S_ACLK : IN std_logic; S_ARESETN : IN std_logic; -- AXI Full/Lite Slave Write Channel (write side) S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWVALID : IN std_logic := '0'; S_AXI_AWREADY : OUT std_logic := '0'; S_AXI_WVALID : IN std_logic := '0'; S_AXI_WREADY : OUT std_logic := '0'; S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_BVALID : OUT std_logic := '0'; S_AXI_BREADY : IN std_logic := '0'; -- Signals for BMG interface S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0); S_AXI_WR_EN : OUT std_logic:= '0' ); END COMPONENT blk_mem_axi_write_wrapper_beh; CONSTANT FLOP_DELAY : TIME := 100 ps; SIGNAL rsta_in : STD_LOGIC := '1'; SIGNAL ena_in : STD_LOGIC := '1'; SIGNAL regcea_in : STD_LOGIC := '1'; SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0'); SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0); SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0'); SIGNAL injectsbiterr_in : STD_LOGIC := '0'; SIGNAL injectdbiterr_in : STD_LOGIC := '0'; ----------------------------------------------------------------------------- -- FUNCTION: toLowerCaseChar -- Returns the lower case form of char if char is an upper case letter. -- Otherwise char is returned. ----------------------------------------------------------------------------- FUNCTION toLowerCaseChar( char : character ) RETURN character IS BEGIN -- If char is not an upper case letter then return char IF char<'A' OR char>'Z' THEN RETURN char; END IF; -- Otherwise map char to its corresponding lower case character and -- RETURN that CASE char IS WHEN 'A' => RETURN 'a'; WHEN 'B' => RETURN 'b'; WHEN 'C' => RETURN 'c'; WHEN 'D' => RETURN 'd'; WHEN 'E' => RETURN 'e'; WHEN 'F' => RETURN 'f'; WHEN 'G' => RETURN 'g'; WHEN 'H' => RETURN 'h'; WHEN 'I' => RETURN 'i'; WHEN 'J' => RETURN 'j'; WHEN 'K' => RETURN 'k'; WHEN 'L' => RETURN 'l'; WHEN 'M' => RETURN 'm'; WHEN 'N' => RETURN 'n'; WHEN 'O' => RETURN 'o'; WHEN 'P' => RETURN 'p'; WHEN 'Q' => RETURN 'q'; WHEN 'R' => RETURN 'r'; WHEN 'S' => RETURN 's'; WHEN 'T' => RETURN 't'; WHEN 'U' => RETURN 'u'; WHEN 'V' => RETURN 'v'; WHEN 'W' => RETURN 'w'; WHEN 'X' => RETURN 'x'; WHEN 'Y' => RETURN 'y'; WHEN 'Z' => RETURN 'z'; WHEN OTHERS => RETURN char; END CASE; END toLowerCaseChar; -- Returns true if case insensitive string comparison determines that -- str1 and str2 are equal FUNCTION equalIgnoreCase( str1 : STRING; str2 : STRING ) RETURN BOOLEAN IS CONSTANT len1 : INTEGER := str1'length; CONSTANT len2 : INTEGER := str2'length; VARIABLE equal : BOOLEAN := TRUE; BEGIN IF NOT (len1=len2) THEN equal := FALSE; ELSE FOR i IN str2'left TO str1'right LOOP IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN equal := FALSE; END IF; END LOOP; END IF; RETURN equal; END equalIgnoreCase; ----------------------------------------------------------------------------- -- FUNCTION: if_then_else -- This function is used to implement an IF..THEN when such a statement is not -- allowed. ---------------------------------------------------------------------------- FUNCTION if_then_else ( condition : BOOLEAN; true_case : STRING; false_case : STRING) RETURN STRING IS BEGIN IF NOT condition THEN RETURN false_case; ELSE RETURN true_case; END IF; END if_then_else; FUNCTION if_then_else ( condition : BOOLEAN; true_case : INTEGER; false_case : INTEGER) RETURN INTEGER IS BEGIN IF NOT condition THEN RETURN false_case; ELSE RETURN true_case; END IF; END if_then_else; FUNCTION if_then_else ( condition : BOOLEAN; true_case : STD_LOGIC_VECTOR; false_case : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS BEGIN IF NOT condition THEN RETURN false_case; ELSE RETURN true_case; END IF; END if_then_else; ---------------------------------------------------------------------------- -- FUNCTION : log2roundup ---------------------------------------------------------------------------- FUNCTION log2roundup ( data_value : INTEGER) RETURN INTEGER IS VARIABLE width : INTEGER := 0; VARIABLE cnt : INTEGER := 1; CONSTANT lower_limit : INTEGER := 1; CONSTANT upper_limit : INTEGER := 8; BEGIN IF (data_value <= 1) THEN width := 0; ELSE WHILE (cnt < data_value) LOOP width := width + 1; cnt := cnt *2; END LOOP; END IF; RETURN width; END log2roundup; ----------------------------------------------------------------------------- -- FUNCTION : log2int ----------------------------------------------------------------------------- FUNCTION log2int ( data_value : INTEGER) RETURN INTEGER IS VARIABLE width : INTEGER := 0; VARIABLE cnt : INTEGER := data_value; BEGIN WHILE (cnt >1) LOOP width := width + 1; cnt := cnt/2; END LOOP; RETURN width; END log2int; ----------------------------------------------------------------------------- -- FUNCTION : divroundup -- Returns the ceiling value of the division -- Data_value - the quantity to be divided, dividend -- Divisor - the value to divide the data_value by ----------------------------------------------------------------------------- FUNCTION divroundup ( data_value : INTEGER; divisor : INTEGER) RETURN INTEGER IS VARIABLE div : INTEGER; BEGIN div := data_value/divisor; IF ( (data_value MOD divisor) /= 0) THEN div := div+1; END IF; RETURN div; END divroundup; SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL s_axi_wr_en_c : STD_LOGIC := '0'; SIGNAL s_axi_rd_en_c : STD_LOGIC := '0'; SIGNAL s_aresetn_a_c : STD_LOGIC := '0'; --************************************************************************** -- AXI PARAMETERS CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0); CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8); CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB; -- Data Width Number of LSB address bits to be discarded -- 1 to 16 1 -- 17 to 32 2 -- 33 to 64 3 -- 65 to 128 4 -- 129 to 256 5 -- 257 to 512 6 -- 513 to 1024 7 -- The following two constants determine this. CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8))); CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL); CONSTANT C_AXI_OS_WR : integer := 2; --************************************************************************** BEGIN -- Architecture --************************************************************************* -- NO INPUT STAGE --************************************************************************* no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE rsta_in <= RSTA; ena_in <= ENA; regcea_in <= REGCEA; wea_in <= WEA; addra_in <= ADDRA; dina_in <= DINA; injectsbiterr_in <= INJECTSBITERR; injectdbiterr_in <= INJECTDBITERR; END GENERATE no_input_stage; --************************************************************************** -- WITH INPUT STAGE --************************************************************************** has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE PROCESS (CLKA) BEGIN IF (CLKA'EVENT AND CLKA = '1') THEN rsta_in <= RSTA AFTER FLOP_DELAY; ena_in <= ENA AFTER FLOP_DELAY; regcea_in <= REGCEA AFTER FLOP_DELAY; wea_in <= WEA AFTER FLOP_DELAY; addra_in <= ADDRA AFTER FLOP_DELAY; dina_in <= DINA AFTER FLOP_DELAY; injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY; injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY; END IF; END PROCESS; END GENERATE has_input_stage; --************************************************************************** -- NATIVE MEMORY MODULE INSTANCE --************************************************************************** native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE mem_module: BLK_MEM_GEN_v8_2_mem_module GENERIC MAP( C_CORENAME => C_CORENAME, C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY)))))))))))))))))), C_XDEVICEFAMILY => C_XDEVICEFAMILY, C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK, C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS, C_MEM_TYPE => C_MEM_TYPE, C_BYTE_SIZE => C_BYTE_SIZE, C_ALGORITHM => C_ALGORITHM, C_PRIM_TYPE => C_PRIM_TYPE, C_LOAD_INIT_FILE => C_LOAD_INIT_FILE, C_INIT_FILE_NAME => C_INIT_FILE_NAME, C_INIT_FILE => C_INIT_FILE, C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA, C_DEFAULT_DATA => C_DEFAULT_DATA, C_RST_TYPE => "SYNC", C_HAS_RSTA => C_HAS_RSTA, C_RST_PRIORITY_A => C_RST_PRIORITY_A, C_RSTRAM_A => C_RSTRAM_A, C_INITA_VAL => C_INITA_VAL, C_HAS_ENA => C_HAS_ENA, C_HAS_REGCEA => C_HAS_REGCEA, C_USE_BYTE_WEA => C_USE_BYTE_WEA, C_WEA_WIDTH => C_WEA_WIDTH, C_WRITE_MODE_A => C_WRITE_MODE_A, C_WRITE_WIDTH_A => C_WRITE_WIDTH_A, C_READ_WIDTH_A => C_READ_WIDTH_A, C_WRITE_DEPTH_A => C_WRITE_DEPTH_A, C_READ_DEPTH_A => C_READ_DEPTH_A, C_ADDRA_WIDTH => C_ADDRA_WIDTH, C_HAS_RSTB => C_HAS_RSTB, C_RST_PRIORITY_B => C_RST_PRIORITY_B, C_RSTRAM_B => C_RSTRAM_B, C_INITB_VAL => C_INITB_VAL, C_HAS_ENB => C_HAS_ENB, C_HAS_REGCEB => C_HAS_REGCEB, C_USE_BYTE_WEB => C_USE_BYTE_WEB, C_WEB_WIDTH => C_WEB_WIDTH, C_WRITE_MODE_B => C_WRITE_MODE_B, C_WRITE_WIDTH_B => C_WRITE_WIDTH_B, C_READ_WIDTH_B => C_READ_WIDTH_B, C_WRITE_DEPTH_B => C_WRITE_DEPTH_B, C_READ_DEPTH_B => C_READ_DEPTH_B, C_ADDRB_WIDTH => C_ADDRB_WIDTH, C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B, C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A, C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B, C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES, C_USE_SOFTECC => C_USE_SOFTECC, C_USE_ECC => C_USE_ECC, C_HAS_INJECTERR => C_HAS_INJECTERR, C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK, C_COMMON_CLK => C_COMMON_CLK, FLOP_DELAY => FLOP_DELAY, C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL, C_EN_ECC_PIPE => C_EN_ECC_PIPE, C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE ) PORT MAP( CLKA => CLKA, RSTA => rsta_in, ENA => ena_in, REGCEA => regcea_in, WEA => wea_in, ADDRA => addra_in, DINA => dina_in, DOUTA => DOUTA, CLKB => CLKB, RSTB => RSTB, ENB => ENB, REGCEB => REGCEB, WEB => WEB, ADDRB => ADDRB, DINB => DINB, DOUTB => DOUTB, INJECTSBITERR => injectsbiterr_in, INJECTDBITERR => injectdbiterr_in, SBITERR => SBITERR, DBITERR => DBITERR, ECCPIPECE => ECCPIPECE, SLEEP => SLEEP, RDADDRECC => RDADDRECC ); END GENERATE native_mem_module; --************************************************************************** -- NATIVE MEMORY MAPPED MODULE INSTANCE --************************************************************************** native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE --************************************************************************** -- NATIVE MEMORY MAPPED PARAMETERS CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A); CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B); CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8); CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8); CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB; CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB; -- Data Width Number of LSB address bits to be discarded -- 1 to 16 1 -- 17 to 32 2 -- 33 to 64 3 -- 65 to 128 4 -- 129 to 256 5 -- 257 to 512 6 -- 513 to 1024 7 -- The following two constants determine this. CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8))); CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8))); CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A; CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B; SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0'); --************************************************************************** BEGIN RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0'); RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i; RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0'); mem_map_module: BLK_MEM_GEN_v8_2_mem_module GENERIC MAP( C_CORENAME => C_CORENAME, C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))), C_XDEVICEFAMILY => C_XDEVICEFAMILY, C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK, C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS, C_MEM_TYPE => C_MEM_TYPE, C_BYTE_SIZE => C_BYTE_SIZE, C_ALGORITHM => C_ALGORITHM, C_PRIM_TYPE => C_PRIM_TYPE, C_LOAD_INIT_FILE => C_LOAD_INIT_FILE, C_INIT_FILE_NAME => C_INIT_FILE_NAME, C_INIT_FILE => C_INIT_FILE, C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA, C_DEFAULT_DATA => C_DEFAULT_DATA, C_RST_TYPE => "SYNC", C_HAS_RSTA => C_HAS_RSTA, C_RST_PRIORITY_A => C_RST_PRIORITY_A, C_RSTRAM_A => C_RSTRAM_A, C_INITA_VAL => C_INITA_VAL, C_HAS_ENA => C_HAS_ENA, C_HAS_REGCEA => C_HAS_REGCEA, C_USE_BYTE_WEA => C_USE_BYTE_WEA, C_WEA_WIDTH => C_WEA_WIDTH, C_WRITE_MODE_A => C_WRITE_MODE_A, C_WRITE_WIDTH_A => C_WRITE_WIDTH_A, C_READ_WIDTH_A => C_READ_WIDTH_A, C_WRITE_DEPTH_A => C_WRITE_DEPTH_A, C_READ_DEPTH_A => C_READ_DEPTH_A, C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL, C_HAS_RSTB => C_HAS_RSTB, C_RST_PRIORITY_B => C_RST_PRIORITY_B, C_RSTRAM_B => C_RSTRAM_B, C_INITB_VAL => C_INITB_VAL, C_HAS_ENB => C_HAS_ENB, C_HAS_REGCEB => C_HAS_REGCEB, C_USE_BYTE_WEB => C_USE_BYTE_WEB, C_WEB_WIDTH => C_WEB_WIDTH, C_WRITE_MODE_B => C_WRITE_MODE_B, C_WRITE_WIDTH_B => C_WRITE_WIDTH_B, C_READ_WIDTH_B => C_READ_WIDTH_B, C_WRITE_DEPTH_B => C_WRITE_DEPTH_B, C_READ_DEPTH_B => C_READ_DEPTH_B, C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL, C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B, C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A, C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B, C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES, C_USE_SOFTECC => C_USE_SOFTECC, C_USE_ECC => C_USE_ECC, C_HAS_INJECTERR => C_HAS_INJECTERR, C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK, C_COMMON_CLK => C_COMMON_CLK, FLOP_DELAY => FLOP_DELAY, C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL, C_EN_ECC_PIPE => C_EN_ECC_PIPE, C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE ) PORT MAP( CLKA => CLKA, RSTA => rsta_in, ENA => ena_in, REGCEA => regcea_in, WEA => wea_in, ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB), DINA => dina_in, DOUTA => DOUTA, CLKB => CLKB, RSTB => RSTB, ENB => ENB, REGCEB => REGCEB, WEB => WEB, ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB), DINB => DINB, DOUTB => DOUTB, INJECTSBITERR => injectsbiterr_in, INJECTDBITERR => injectdbiterr_in, SBITERR => SBITERR, DBITERR => DBITERR, ECCPIPECE => ECCPIPECE, SLEEP => SLEEP, RDADDRECC => rdaddrecc_i ); END GENERATE native_mem_map_module; --**************************************************************************** -- AXI MEMORY MODULE INSTANCE --**************************************************************************** axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL s_axi_rlast_c : STD_LOGIC := '0'; SIGNAL s_axi_rvalid_c : STD_LOGIC := '0'; SIGNAL s_axi_rready_c : STD_LOGIC := '0'; SIGNAL regceb_c : STD_LOGIC := '0'; BEGIN s_aresetn_a_c <= NOT S_ARESETN; S_AXI_BRESP <= (OTHERS => '0'); s_axi_rresp_c <= (OTHERS => '0'); no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE S_AXI_RDATA <= s_axi_rdata_c; S_AXI_RLAST <= s_axi_rlast_c; S_AXI_RVALID <= s_axi_rvalid_c; S_AXI_RID <= s_axi_rid_c; S_AXI_RRESP <= s_axi_rresp_c; s_axi_rready_c <= S_AXI_RREADY; END GENERATE no_regs; has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3); SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0'); BEGIN has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE regceb_c <= s_axi_rvalid_c AND s_axi_rready_c; END GENERATE has_regceb; no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE regceb_c <= REGCEB; END GENERATE no_regceb; only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c; S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH); S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B); S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1); S_AXI_RLAST <= m_axi_payload_c(0); END GENERATE only_core_op_regs; only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c; S_AXI_RDATA <= s_axi_rdata_c; S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH); S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1); S_AXI_RLAST <= m_axi_payload_c(0); END GENERATE only_emb_op_regs; axi_regs_inst : blk_mem_axi_regs_fwd_v8_2 GENERIC MAP( C_DATA_WIDTH => C_AXI_PAYLOAD ) PORT MAP ( ACLK => S_ACLK, ARESET => s_aresetn_a_c, S_VALID => s_axi_rvalid_c, S_READY => s_axi_rready_c, S_PAYLOAD_DATA => s_axi_payload_c, M_VALID => S_AXI_RVALID, M_READY => S_AXI_RREADY, M_PAYLOAD_DATA => m_axi_payload_c ); END GENERATE has_regs_fwd; axi_wr_fsm : blk_mem_axi_write_wrapper_beh GENERIC MAP( -- AXI Interface related parameters start here C_INTERFACE_TYPE => C_INTERFACE_TYPE, C_AXI_TYPE => C_AXI_TYPE, C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE, C_MEMORY_TYPE => C_MEM_TYPE, C_WRITE_DEPTH_A => C_WRITE_DEPTH_A, C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), C_HAS_AXI_ID => C_HAS_AXI_ID, C_AXI_ID_WIDTH => C_AXI_ID_WIDTH, C_ADDRA_WIDTH => C_ADDRA_WIDTH, C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A, C_AXI_OS_WR => C_AXI_OS_WR ) PORT MAP( -- AXI Global Signals S_ACLK => S_ACLK, S_ARESETN => s_aresetn_a_c, -- AXI Full/Lite Slave Write Interface S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB), S_AXI_AWLEN => S_AXI_AWLEN, S_AXI_AWID => S_AXI_AWID, S_AXI_AWSIZE => S_AXI_AWSIZE, S_AXI_AWBURST => S_AXI_AWBURST, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_AWREADY => S_AXI_AWREADY, S_AXI_WVALID => S_AXI_WVALID, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BVALID => S_AXI_BVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_BID => S_AXI_BID, -- Signals for BRAM interface S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c, S_AXI_WR_EN =>s_axi_wr_en_c ); mem_module: BLK_MEM_GEN_v8_2_mem_module GENERIC MAP( C_CORENAME => C_CORENAME, C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))), C_XDEVICEFAMILY => C_XDEVICEFAMILY, C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK, C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS, C_MEM_TYPE => C_MEM_TYPE, C_BYTE_SIZE => C_BYTE_SIZE, C_ALGORITHM => C_ALGORITHM, C_PRIM_TYPE => C_PRIM_TYPE, C_LOAD_INIT_FILE => C_LOAD_INIT_FILE, C_INIT_FILE_NAME => C_INIT_FILE_NAME, C_INIT_FILE => C_INIT_FILE, C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA, C_DEFAULT_DATA => C_DEFAULT_DATA, C_RST_TYPE => "SYNC", C_HAS_RSTA => C_HAS_RSTA, C_RST_PRIORITY_A => C_RST_PRIORITY_A, C_RSTRAM_A => C_RSTRAM_A, C_INITA_VAL => C_INITA_VAL, C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA, C_HAS_REGCEA => C_HAS_REGCEA, C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1, C_WEA_WIDTH => C_WEA_WIDTH, C_WRITE_MODE_A => C_WRITE_MODE_A, C_WRITE_WIDTH_A => C_WRITE_WIDTH_A, C_READ_WIDTH_A => C_READ_WIDTH_A, C_WRITE_DEPTH_A => C_WRITE_DEPTH_A, C_READ_DEPTH_A => C_READ_DEPTH_A, C_ADDRA_WIDTH => C_ADDRA_WIDTH, C_HAS_RSTB => C_HAS_RSTB, C_RST_PRIORITY_B => C_RST_PRIORITY_B, C_RSTRAM_B => C_RSTRAM_B, C_INITB_VAL => C_INITB_VAL, C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB, C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B, C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1, C_WEB_WIDTH => C_WEB_WIDTH, C_WRITE_MODE_B => C_WRITE_MODE_B, C_WRITE_WIDTH_B => C_WRITE_WIDTH_B, C_READ_WIDTH_B => C_READ_WIDTH_B, C_WRITE_DEPTH_B => C_WRITE_DEPTH_B, C_READ_DEPTH_B => C_READ_DEPTH_B, C_ADDRB_WIDTH => C_ADDRB_WIDTH, C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_A => 0, C_HAS_MUX_OUTPUT_REGS_B => 0, C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A, C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B, C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES, C_USE_SOFTECC => C_USE_SOFTECC, C_USE_ECC => C_USE_ECC, C_HAS_INJECTERR => C_HAS_INJECTERR, C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK, C_COMMON_CLK => C_COMMON_CLK, FLOP_DELAY => FLOP_DELAY, C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL, C_EN_ECC_PIPE => 0, C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE ) PORT MAP( --Port A: CLKA => S_AClk, RSTA => s_aresetn_a_c, ENA => s_axi_wr_en_c, REGCEA => regcea_in, WEA => S_AXI_WSTRB, ADDRA => s_axi_awaddr_out_c, DINA => S_AXI_WDATA, DOUTA => DOUTA, --Port B: CLKB => S_AClk, RSTB => s_aresetn_a_c, ENB => s_axi_rd_en_c, REGCEB => regceb_c, WEB => (OTHERS => '0'), ADDRB => s_axi_araddr_out_c, DINB => DINB, DOUTB => s_axi_rdata_c, INJECTSBITERR => injectsbiterr_in, INJECTDBITERR => injectdbiterr_in, SBITERR => SBITERR, DBITERR => DBITERR, ECCPIPECE => '0', SLEEP => '0', RDADDRECC => RDADDRECC ); axi_rd_sm : blk_mem_axi_read_wrapper_beh GENERIC MAP ( -- AXI Interface related parameters start here C_INTERFACE_TYPE => C_INTERFACE_TYPE, C_AXI_TYPE => C_AXI_TYPE, C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE, C_MEMORY_TYPE => C_MEM_TYPE, C_WRITE_WIDTH_A => C_WRITE_WIDTH_A, C_ADDRA_WIDTH => C_ADDRA_WIDTH, C_AXI_PIPELINE_STAGES => 1, C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), C_HAS_AXI_ID => C_HAS_AXI_ID, C_AXI_ID_WIDTH => C_AXI_ID_WIDTH, C_ADDRB_WIDTH => C_ADDRB_WIDTH ) PORT MAP( -- AXI Global Signals S_ACLK => S_AClk, S_ARESETN => s_aresetn_a_c, -- AXI Full/Lite Read Side S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB), S_AXI_ARLEN => S_AXI_ARLEN, S_AXI_ARSIZE => S_AXI_ARSIZE, S_AXI_ARBURST => S_AXI_ARBURST, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RLAST => s_axi_rlast_c, S_AXI_RVALID => s_axi_rvalid_c, S_AXI_RREADY => s_axi_rready_c, S_AXI_ARID => S_AXI_ARID, S_AXI_RID => s_axi_rid_c, -- AXI Full/Lite Read FSM Outputs S_AXI_ARADDR_OUT => s_axi_araddr_out_c, S_AXI_RD_EN => s_axi_rd_en_c ); END GENERATE axi_mem_module; END behavioral; library IEEE; use IEEE.STD_LOGIC_1164.all; entity beh_ff_clr is generic( INIT : std_logic := '0' ); port( Q : out std_logic; C : in std_logic; CLR : in std_logic; D : in std_logic ); end beh_ff_clr; architecture beh_ff_clr_arch of beh_ff_clr is signal q_o : std_logic := INIT; begin Q <= q_o; VITALBehavior : process(CLR, C) begin if (CLR = '1') then q_o <= '0'; elsif (rising_edge(C)) then q_o <= D after 100 ps; end if; end process; end beh_ff_clr_arch; library IEEE; use IEEE.STD_LOGIC_1164.all; entity beh_ff_ce is generic( INIT : std_logic := '0' ); port( Q : out std_logic; C : in std_logic; CE : in std_logic; CLR : in std_logic; D : in std_logic ); end beh_ff_ce; architecture beh_ff_ce_arch of beh_ff_ce is signal q_o : std_logic := INIT; begin Q <= q_o; VITALBehavior : process(C, CLR) begin if (CLR = '1') then q_o <= '0'; elsif (rising_edge(C)) then if (CE = '1') then q_o <= D after 100 ps; end if; end if; end process; end beh_ff_ce_arch; library IEEE; use IEEE.STD_LOGIC_1164.all; entity beh_ff_pre is generic( INIT : std_logic := '1' ); port( Q : out std_logic; C : in std_logic; D : in std_logic; PRE : in std_logic ); end beh_ff_pre; architecture beh_ff_pre_arch of beh_ff_pre is signal q_o : std_logic := INIT; begin Q <= q_o; VITALBehavior : process(C, PRE) begin if (PRE = '1') then q_o <= '1'; elsif (C' event and C = '1') then q_o <= D after 100 ps; end if; end process; end beh_ff_pre_arch; library IEEE; use IEEE.STD_LOGIC_1164.all; entity beh_muxf7 is port( O : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic; S : in std_ulogic ); end beh_muxf7; architecture beh_muxf7_arch of beh_muxf7 is begin VITALBehavior : process (I0, I1, S) begin if (S = '0') then O <= I0; else O <= I1; end if; end process; end beh_muxf7_arch; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity STATE_LOGIC is generic( INIT : std_logic_vector(63 downto 0) := X"0000000000000000" ); port( O : out std_logic := '0'; I0 : in std_logic := '0'; I1 : in std_logic := '0'; I2 : in std_logic := '0'; I3 : in std_logic := '0'; I4 : in std_logic := '0'; I5 : in std_logic := '0' ); end STATE_LOGIC; architecture STATE_LOGIC_arch of STATE_LOGIC is constant INIT_reg : std_logic_vector(63 downto 0) := INIT; begin LUT_beh:process (I0, I1, I2, I3, I4, I5) variable I_reg : std_logic_vector(5 downto 0); begin I_reg := I5 & I4 & I3 & I2 & I1 & I0; O <= INIT_reg(conv_integer(I_reg)); end process; end STATE_LOGIC_arch;
------------------------------------------------------------------------------- -- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------- -- -- Filename: BLK_MEM_GEN_v8_2.vhd -- -- Description: -- This file is the VHDL behvarial model for the -- Block Memory Generator Core. -- ------------------------------------------------------------------------------- -- Author: Xilinx -- -- History: January 11, 2006: Initial revision -- June 11, 2007 : Added independent register stages for -- Port A and Port B (IP1_Jm/v2.5) -- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6) -- April 07, 2009 : Added support for Spartan-6 and Virtex-6 -- features, including the following: -- (i) error injection, detection and/or correction -- (ii) reset priority -- (iii) special reset behavior -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.numeric_std.all; USE ieee.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_misc.all; LIBRARY STD; USE STD.TEXTIO.ALL; ENTITY blk_mem_axi_regs_fwd_v8_2 IS GENERIC( C_DATA_WIDTH : INTEGER := 8 ); PORT ( ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; S_VALID : IN STD_LOGIC; S_READY : OUT STD_LOGIC; S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); M_VALID : OUT STD_LOGIC; M_READY : IN STD_LOGIC; M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ); END ENTITY blk_mem_axi_regs_fwd_v8_2; ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_2 IS SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL S_READY_I : STD_LOGIC := '0'; SIGNAL M_VALID_I : STD_LOGIC := '0'; SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register BEGIN --assign local signal to its output signal S_READY <= S_READY_I; M_VALID <= M_VALID_I; PROCESS(ACLK) BEGIN IF(ACLK'event AND ACLK = '1') THEN ARESET_D <= ARESET_D(0) & ARESET; END IF; END PROCESS; --Save payload data whenever we have a transaction on the slave side PROCESS(ACLK, ARESET) BEGIN IF (ARESET = '1') THEN STORAGE_DATA <= (OTHERS => '0'); ELSIF(ACLK'event AND ACLK = '1') THEN IF(S_VALID = '1' AND S_READY_I = '1') THEN STORAGE_DATA <= S_PAYLOAD_DATA; END IF; END IF; END PROCESS; M_PAYLOAD_DATA <= STORAGE_DATA; -- M_Valid set to high when we have a completed transfer on slave side -- Is removed on a M_READY except if we have a new transfer on the slave side PROCESS(ACLK,ARESET) BEGIN IF (ARESET_D /= "00") THEN M_VALID_I <= '0'; ELSIF(ACLK'event AND ACLK = '1') THEN IF (S_VALID = '1') THEN --Always set M_VALID_I when slave side is valid M_VALID_I <= '1'; ELSIF (M_READY = '1') THEN --Clear (or keep) when no slave side is valid but master side is ready M_VALID_I <= '0'; END IF; END IF; END PROCESS; --Slave Ready is either when Master side drives M_READY or we have space in our storage data S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D)); END axi_regs_fwd_arch; ------------------------------------------------------------------------------- -- Description: -- This is the behavioral model of write_wrapper for the -- Block Memory Generator Core. ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY blk_mem_axi_write_wrapper_beh IS GENERIC ( -- AXI Interface related parameters start here C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full; C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE; C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM; C_WRITE_DEPTH_A : integer := 0; C_AXI_AWADDR_WIDTH : integer := 32; C_ADDRA_WIDTH : integer := 12; C_AXI_WDATA_WIDTH : integer := 32; C_HAS_AXI_ID : integer := 0; C_AXI_ID_WIDTH : integer := 4; -- AXI OUTSTANDING WRITES C_AXI_OS_WR : integer := 2 ); PORT ( -- AXI Global Signals S_ACLK : IN std_logic; S_ARESETN : IN std_logic; -- AXI Full/Lite Slave Write Channel (write side) S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWVALID : IN std_logic := '0'; S_AXI_AWREADY : OUT std_logic := '0'; S_AXI_WVALID : IN std_logic := '0'; S_AXI_WREADY : OUT std_logic := '0'; S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_BVALID : OUT std_logic := '0'; S_AXI_BREADY : IN std_logic := '0'; -- Signals for BMG interface S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0); S_AXI_WR_EN : OUT std_logic:= '0' ); END blk_mem_axi_write_wrapper_beh; ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS ------------------------------------------------------------------------------ -- FUNCTION: if_then_else -- This function is used to implement an IF..THEN when such a statement is not -- allowed. ------------------------------------------------------------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : INTEGER; false_case : INTEGER) RETURN INTEGER IS VARIABLE retval : INTEGER := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; FUNCTION if_then_else ( condition : BOOLEAN; true_case : STD_LOGIC_VECTOR; false_case : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS BEGIN IF NOT condition THEN RETURN false_case; ELSE RETURN true_case; END IF; END if_then_else; FUNCTION if_then_else ( condition : BOOLEAN; true_case : STRING; false_case : STRING) RETURN STRING IS BEGIN IF NOT condition THEN RETURN false_case; ELSE RETURN true_case; END IF; END if_then_else; CONSTANT FLOP_DELAY : TIME := 100 PS; CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001"); CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0, if_then_else((C_AXI_WDATA_WIDTH=16),1, if_then_else((C_AXI_WDATA_WIDTH=32),2, if_then_else((C_AXI_WDATA_WIDTH=64),3, if_then_else((C_AXI_WDATA_WIDTH=128),4, if_then_else((C_AXI_WDATA_WIDTH=256),5,0)))))); SIGNAL bvalid_c : std_logic := '0'; SIGNAL bready_timeout_c : std_logic := '0'; SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); SIGNAL bvalid_r : std_logic := '0'; SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0'); SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0), C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0); SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); SIGNAL w_last_c : std_logic := '0'; SIGNAL addr_en_c : std_logic := '0'; SIGNAL incr_addr_c : std_logic := '0'; SIGNAL aw_ready_r : std_logic := '0'; SIGNAL dec_alen_c : std_logic := '0'; SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1'); SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); SIGNAL total_bytes : integer := 0; SIGNAL wrap_boundary : integer := 0; SIGNAL wrap_base_addr : integer := 0; SIGNAL num_of_bytes_c : integer := 0; SIGNAL num_of_bytes_r : integer := 0; -- Array to store BIDs TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); SIGNAL axi_bid_array : id_array := (others => (others => '0')); COMPONENT write_netlist GENERIC( C_AXI_TYPE : integer ); PORT( S_ACLK : IN std_logic; S_ARESETN : IN std_logic; S_AXI_AWVALID : IN std_logic; aw_ready_r : OUT std_logic; S_AXI_WVALID : IN std_logic; S_AXI_WREADY : OUT std_logic; S_AXI_BVALID : OUT STD_LOGIC; S_AXI_BREADY : IN std_logic; S_AXI_WR_EN : OUT std_logic; w_last_c : IN std_logic; bready_timeout_c : IN std_logic; addr_en_c : OUT std_logic; incr_addr_c : OUT std_logic; bvalid_c : OUT std_logic ); END COMPONENT write_netlist; BEGIN --------------------------------------- --AXI WRITE FSM COMPONENT INSTANTIATION --------------------------------------- axi_wr_fsm : write_netlist GENERIC MAP ( C_AXI_TYPE => C_AXI_TYPE ) PORT MAP ( S_ACLK => S_ACLK, S_ARESETN => S_ARESETN, S_AXI_AWVALID => S_AXI_AWVALID, aw_ready_r => aw_ready_r, S_AXI_WVALID => S_AXI_WVALID, S_AXI_BVALID => OPEN, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BREADY => S_AXI_BREADY, S_AXI_WR_EN => S_AXI_WR_EN, w_last_c => w_last_c, bready_timeout_c => bready_timeout_c, addr_en_c => addr_en_c, incr_addr_c => incr_addr_c, bvalid_c => bvalid_c ); --Wrap Address boundary calculation num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000")); total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1); wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes); wrap_boundary <= wrap_base_addr+total_bytes; --------------------------------------------------------------------------- -- BMG address generation --------------------------------------------------------------------------- P_addr_reg: PROCESS (S_ACLK,S_ARESETN) BEGIN IF (S_ARESETN = '1') THEN awaddr_reg <= (OTHERS => '0'); num_of_bytes_r <= 0; awburst_int <= (OTHERS => '0'); ELSIF (S_ACLK'event AND S_ACLK = '1') THEN IF (addr_en_c = '1') THEN awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY; num_of_bytes_r <= num_of_bytes_c; awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01"); ELSIF (incr_addr_c = '1') THEN IF (awburst_int = "10") THEN IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH); ELSE awaddr_reg <= awaddr_reg + num_of_bytes_r; END IF; ELSIF (awburst_int = "01" OR awburst_int = "11") THEN awaddr_reg <= awaddr_reg + num_of_bytes_r; END IF; END IF; END IF; END PROCESS P_addr_reg; S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0), awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg); --------------------------------------------------------------------------- -- AXI wlast generation --------------------------------------------------------------------------- P_addr_cnt: PROCESS (S_ACLK, S_ARESETN) BEGIN IF (S_ARESETN = '1') THEN awlen_cntr_r <= (OTHERS => '1'); awlen_int <= (OTHERS => '0'); ELSIF (S_ACLK'event AND S_ACLK = '1') THEN IF (addr_en_c = '1') THEN awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY; awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY; ELSIF (dec_alen_c = '1') THEN awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY; END IF; END IF; END PROCESS P_addr_cnt; w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0'; dec_alen_c <= (incr_addr_c OR w_last_c); --------------------------------------------------------------------------- -- Generation of bvalid counter for outstanding transactions --------------------------------------------------------------------------- P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN) BEGIN IF (S_ARESETN = '1') THEN bvalid_count_r <= (OTHERS => '0'); ELSIF (S_ACLK'event AND S_ACLK='1') THEN -- bvalid_count_r generation IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY; ELSIF (bvalid_c = '1') THEN bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY; ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY; END IF; END IF; END PROCESS P_b_valid_os_r ; --------------------------------------------------------------------------- -- Generation of bvalid when BID is used --------------------------------------------------------------------------- gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE SIGNAL bvalid_d1_c : std_logic := '0'; BEGIN P_b_valid_r: PROCESS (S_ACLK, S_ARESETN) BEGIN IF (S_ARESETN = '1') THEN bvalid_r <= '0'; bvalid_d1_c <= '0'; ELSIF (S_ACLK'event AND S_ACLK='1') THEN -- Delay the generation o bvalid_r for generation for BID bvalid_d1_c <= bvalid_c; --external bvalid signal generation IF (bvalid_d1_c = '1') THEN bvalid_r <= '1' AFTER FLOP_DELAY; ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN bvalid_r <= '0' AFTER FLOP_DELAY; END IF; END IF; END PROCESS P_b_valid_r ; END GENERATE gaxi_bvalid_id_r; --------------------------------------------------------------------------- -- Generation of bvalid when BID is not used --------------------------------------------------------------------------- gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE P_b_valid_r: PROCESS (S_ACLK, S_ARESETN) BEGIN IF (S_ARESETN = '1') THEN bvalid_r <= '0'; ELSIF (S_ACLK'event AND S_ACLK='1') THEN --external bvalid signal generation IF (bvalid_c = '1') THEN bvalid_r <= '1' AFTER FLOP_DELAY; ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN bvalid_r <= '0' AFTER FLOP_DELAY; END IF; END IF; END PROCESS P_b_valid_r ; END GENERATE gaxi_bvalid_noid_r; --------------------------------------------------------------------------- -- Generation of Bready timeout --------------------------------------------------------------------------- P_brdy_tout_c: PROCESS (bvalid_count_r) BEGIN -- bready_timeout_c generation IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN bready_timeout_c <= '1'; ELSE bready_timeout_c <= '0'; END IF; END PROCESS P_brdy_tout_c; --------------------------------------------------------------------------- -- Generation of BID --------------------------------------------------------------------------- gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE P_bid_gen: PROCESS (S_ACLK,S_ARESETN) BEGIN IF (S_ARESETN='1') THEN bvalid_wr_cnt_r <= (OTHERS => '0'); bvalid_rd_cnt_r <= (OTHERS => '0'); ELSIF (S_ACLK'event AND S_ACLK='1') THEN -- STORE AWID IN AN ARRAY IF(bvalid_c = '1') THEN bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01"; END IF; -- GENERATE BID FROM AWID ARRAY bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY; S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c)); END IF; END PROCESS P_bid_gen; bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r; --------------------------------------------------------------------------- -- Storing AWID for generation of BID --------------------------------------------------------------------------- P_awid_reg:PROCESS (S_ACLK) BEGIN IF (S_ACLK'event AND S_ACLK='1') THEN IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID; END IF; END IF; END PROCESS P_awid_reg; END GENERATE gaxi_bid_gen; S_AXI_BVALID <= bvalid_r; S_AXI_AWREADY <= aw_ready_r; END axi_write_wrap_arch; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity write_netlist is GENERIC( C_AXI_TYPE : integer ); port ( S_ACLK : in STD_LOGIC := '0'; S_ARESETN : in STD_LOGIC := '0'; S_AXI_AWVALID : in STD_LOGIC := '0'; S_AXI_WVALID : in STD_LOGIC := '0'; S_AXI_BREADY : in STD_LOGIC := '0'; w_last_c : in STD_LOGIC := '0'; bready_timeout_c : in STD_LOGIC := '0'; aw_ready_r : out STD_LOGIC; S_AXI_WREADY : out STD_LOGIC; S_AXI_BVALID : out STD_LOGIC; S_AXI_WR_EN : out STD_LOGIC; addr_en_c : out STD_LOGIC; incr_addr_c : out STD_LOGIC; bvalid_c : out STD_LOGIC ); end write_netlist; architecture STRUCTURE of write_netlist is component beh_muxf7 port( O : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic; S : in std_ulogic ); end component; COMPONENT beh_ff_pre generic( INIT : std_logic := '1' ); port( Q : out std_logic; C : in std_logic; D : in std_logic; PRE : in std_logic ); end COMPONENT beh_ff_pre; COMPONENT beh_ff_ce generic( INIT : std_logic := '0' ); port( Q : out std_logic; C : in std_logic; CE : in std_logic; CLR : in std_logic; D : in std_logic ); end COMPONENT beh_ff_ce; COMPONENT beh_ff_clr generic( INIT : std_logic := '0' ); port( Q : out std_logic; C : in std_logic; CLR : in std_logic; D : in std_logic ); end COMPONENT beh_ff_clr; COMPONENT STATE_LOGIC generic( INIT : std_logic_vector(63 downto 0) := X"0000000000000000" ); port( O : out std_logic; I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; I4 : in std_logic; I5 : in std_logic ); end COMPONENT STATE_LOGIC; BEGIN --------------------------------------------------------------------------- -- AXI LITE --------------------------------------------------------------------------- gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE signal w_ready_r_7 : STD_LOGIC; signal w_ready_c : STD_LOGIC; signal aw_ready_c : STD_LOGIC; signal NlwRenamedSignal_bvalid_c : STD_LOGIC; signal NlwRenamedSignal_incr_addr_c : STD_LOGIC; signal present_state_FSM_FFd3_13 : STD_LOGIC; signal present_state_FSM_FFd2_14 : STD_LOGIC; signal present_state_FSM_FFd1_15 : STD_LOGIC; signal present_state_FSM_FFd4_16 : STD_LOGIC; signal present_state_FSM_FFd4_In : STD_LOGIC; signal present_state_FSM_FFd3_In : STD_LOGIC; signal present_state_FSM_FFd2_In : STD_LOGIC; signal present_state_FSM_FFd1_In : STD_LOGIC; signal present_state_FSM_FFd4_In1_21 : STD_LOGIC; signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 ); begin S_AXI_WREADY <= w_ready_r_7; S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c; S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c; incr_addr_c <= NlwRenamedSignal_incr_addr_c; bvalid_c <= NlwRenamedSignal_bvalid_c; NlwRenamedSignal_incr_addr_c <= '0'; aw_ready_r_2 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => aw_ready_c, Q => aw_ready_r ); w_ready_r : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => w_ready_c, Q => w_ready_r_7 ); present_state_FSM_FFd4 : beh_ff_pre generic map( INIT => '1' ) port map ( C => S_ACLK, D => present_state_FSM_FFd4_In, PRE => S_ARESETN, Q => present_state_FSM_FFd4_16 ); present_state_FSM_FFd3 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => present_state_FSM_FFd3_In, Q => present_state_FSM_FFd3_13 ); present_state_FSM_FFd2 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => present_state_FSM_FFd2_In, Q => present_state_FSM_FFd2_14 ); present_state_FSM_FFd1 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => present_state_FSM_FFd1_In, Q => present_state_FSM_FFd1_15 ); present_state_FSM_FFd3_In1 : STATE_LOGIC generic map( INIT => X"0000000055554440" ) port map ( I0 => S_AXI_WVALID, I1 => S_AXI_AWVALID, I2 => present_state_FSM_FFd2_14, I3 => present_state_FSM_FFd4_16, I4 => present_state_FSM_FFd3_13, I5 => '0', O => present_state_FSM_FFd3_In ); present_state_FSM_FFd2_In1 : STATE_LOGIC generic map( INIT => X"0000000088880800" ) port map ( I0 => S_AXI_AWVALID, I1 => S_AXI_WVALID, I2 => bready_timeout_c, I3 => present_state_FSM_FFd2_14, I4 => present_state_FSM_FFd4_16, I5 => '0', O => present_state_FSM_FFd2_In ); Mmux_addr_en_c_0_1 : STATE_LOGIC generic map( INIT => X"00000000AAAA2000" ) port map ( I0 => S_AXI_AWVALID, I1 => bready_timeout_c, I2 => present_state_FSM_FFd2_14, I3 => S_AXI_WVALID, I4 => present_state_FSM_FFd4_16, I5 => '0', O => addr_en_c ); Mmux_w_ready_c_0_1 : STATE_LOGIC generic map( INIT => X"F5F07570F5F05500" ) port map ( I0 => S_AXI_WVALID, I1 => bready_timeout_c, I2 => S_AXI_AWVALID, I3 => present_state_FSM_FFd3_13, I4 => present_state_FSM_FFd4_16, I5 => present_state_FSM_FFd2_14, O => w_ready_c ); present_state_FSM_FFd1_In1 : STATE_LOGIC generic map( INIT => X"88808880FFFF8880" ) port map ( I0 => S_AXI_WVALID, I1 => bready_timeout_c, I2 => present_state_FSM_FFd3_13, I3 => present_state_FSM_FFd2_14, I4 => present_state_FSM_FFd1_15, I5 => S_AXI_BREADY, O => present_state_FSM_FFd1_In ); Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC generic map( INIT => X"00000000000000A8" ) port map ( I0 => S_AXI_WVALID, I1 => present_state_FSM_FFd2_14, I2 => present_state_FSM_FFd3_13, I3 => '0', I4 => '0', I5 => '0', O => NlwRenamedSignal_bvalid_c ); present_state_FSM_FFd4_In1 : STATE_LOGIC generic map( INIT => X"2F0F27072F0F2200" ) port map ( I0 => S_AXI_WVALID, I1 => bready_timeout_c, I2 => S_AXI_AWVALID, I3 => present_state_FSM_FFd3_13, I4 => present_state_FSM_FFd4_16, I5 => present_state_FSM_FFd2_14, O => present_state_FSM_FFd4_In1_21 ); present_state_FSM_FFd4_In2 : STATE_LOGIC generic map( INIT => X"00000000000000F8" ) port map ( I0 => present_state_FSM_FFd1_15, I1 => S_AXI_BREADY, I2 => present_state_FSM_FFd4_In1_21, I3 => '0', I4 => '0', I5 => '0', O => present_state_FSM_FFd4_In ); Mmux_aw_ready_c_0_1 : STATE_LOGIC generic map( INIT => X"7535753575305500" ) port map ( I0 => S_AXI_AWVALID, I1 => bready_timeout_c, I2 => S_AXI_WVALID, I3 => present_state_FSM_FFd4_16, I4 => present_state_FSM_FFd3_13, I5 => present_state_FSM_FFd2_14, O => Mmux_aw_ready_c(0) ); Mmux_aw_ready_c_0_2 : STATE_LOGIC generic map( INIT => X"00000000000000F8" ) port map ( I0 => present_state_FSM_FFd1_15, I1 => S_AXI_BREADY, I2 => Mmux_aw_ready_c(0), I3 => '0', I4 => '0', I5 => '0', O => aw_ready_c ); END GENERATE gbeh_axi_lite_sm; --------------------------------------------------------------------------- -- AXI FULL --------------------------------------------------------------------------- gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE signal w_ready_r_8 : STD_LOGIC; signal w_ready_c : STD_LOGIC; signal aw_ready_c : STD_LOGIC; signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC; signal present_state_FSM_FFd1_16 : STD_LOGIC; signal present_state_FSM_FFd4_17 : STD_LOGIC; signal present_state_FSM_FFd3_18 : STD_LOGIC; signal present_state_FSM_FFd2_19 : STD_LOGIC; signal present_state_FSM_FFd4_In : STD_LOGIC; signal present_state_FSM_FFd3_In : STD_LOGIC; signal present_state_FSM_FFd2_In : STD_LOGIC; signal present_state_FSM_FFd1_In : STD_LOGIC; signal present_state_FSM_FFd2_In1_24 : STD_LOGIC; signal present_state_FSM_FFd4_In1_25 : STD_LOGIC; signal N2 : STD_LOGIC; signal N4 : STD_LOGIC; begin S_AXI_WREADY <= w_ready_r_8; bvalid_c <= NlwRenamedSig_OI_bvalid_c; S_AXI_BVALID <= '0'; aw_ready_r_2 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => aw_ready_c, Q => aw_ready_r ); w_ready_r : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => w_ready_c, Q => w_ready_r_8 ); present_state_FSM_FFd4 : beh_ff_pre generic map( INIT => '1' ) port map ( C => S_ACLK, D => present_state_FSM_FFd4_In, PRE => S_ARESETN, Q => present_state_FSM_FFd4_17 ); present_state_FSM_FFd3 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => present_state_FSM_FFd3_In, Q => present_state_FSM_FFd3_18 ); present_state_FSM_FFd2 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => present_state_FSM_FFd2_In, Q => present_state_FSM_FFd2_19 ); present_state_FSM_FFd1 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => present_state_FSM_FFd1_In, Q => present_state_FSM_FFd1_16 ); present_state_FSM_FFd3_In1 : STATE_LOGIC generic map( INIT => X"0000000000005540" ) port map ( I0 => S_AXI_WVALID, I1 => present_state_FSM_FFd4_17, I2 => S_AXI_AWVALID, I3 => present_state_FSM_FFd3_18, I4 => '0', I5 => '0', O => present_state_FSM_FFd3_In ); Mmux_aw_ready_c_0_2 : STATE_LOGIC generic map( INIT => X"BF3FBB33AF0FAA00" ) port map ( I0 => S_AXI_BREADY, I1 => bready_timeout_c, I2 => S_AXI_AWVALID, I3 => present_state_FSM_FFd1_16, I4 => present_state_FSM_FFd4_17, I5 => NlwRenamedSig_OI_bvalid_c, O => aw_ready_c ); Mmux_addr_en_c_0_1 : STATE_LOGIC generic map( INIT => X"AAAAAAAA20000000" ) port map ( I0 => S_AXI_AWVALID, I1 => bready_timeout_c, I2 => present_state_FSM_FFd2_19, I3 => S_AXI_WVALID, I4 => w_last_c, I5 => present_state_FSM_FFd4_17, O => addr_en_c ); Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC generic map( INIT => X"00000000000000A8" ) port map ( I0 => S_AXI_WVALID, I1 => present_state_FSM_FFd2_19, I2 => present_state_FSM_FFd3_18, I3 => '0', I4 => '0', I5 => '0', O => S_AXI_WR_EN ); Mmux_incr_addr_c_0_1 : STATE_LOGIC generic map( INIT => X"0000000000002220" ) port map ( I0 => S_AXI_WVALID, I1 => w_last_c, I2 => present_state_FSM_FFd2_19, I3 => present_state_FSM_FFd3_18, I4 => '0', I5 => '0', O => incr_addr_c ); Mmux_aw_ready_c_0_11 : STATE_LOGIC generic map( INIT => X"0000000000008880" ) port map ( I0 => S_AXI_WVALID, I1 => w_last_c, I2 => present_state_FSM_FFd2_19, I3 => present_state_FSM_FFd3_18, I4 => '0', I5 => '0', O => NlwRenamedSig_OI_bvalid_c ); present_state_FSM_FFd2_In1 : STATE_LOGIC generic map( INIT => X"000000000000D5C0" ) port map ( I0 => w_last_c, I1 => S_AXI_AWVALID, I2 => present_state_FSM_FFd4_17, I3 => present_state_FSM_FFd3_18, I4 => '0', I5 => '0', O => present_state_FSM_FFd2_In1_24 ); present_state_FSM_FFd2_In2 : STATE_LOGIC generic map( INIT => X"FFFFAAAA08AAAAAA" ) port map ( I0 => present_state_FSM_FFd2_19, I1 => S_AXI_AWVALID, I2 => bready_timeout_c, I3 => w_last_c, I4 => S_AXI_WVALID, I5 => present_state_FSM_FFd2_In1_24, O => present_state_FSM_FFd2_In ); present_state_FSM_FFd4_In1 : STATE_LOGIC generic map( INIT => X"00C0004000C00000" ) port map ( I0 => S_AXI_AWVALID, I1 => w_last_c, I2 => S_AXI_WVALID, I3 => bready_timeout_c, I4 => present_state_FSM_FFd3_18, I5 => present_state_FSM_FFd2_19, O => present_state_FSM_FFd4_In1_25 ); present_state_FSM_FFd4_In2 : STATE_LOGIC generic map( INIT => X"00000000FFFF88F8" ) port map ( I0 => present_state_FSM_FFd1_16, I1 => S_AXI_BREADY, I2 => present_state_FSM_FFd4_17, I3 => S_AXI_AWVALID, I4 => present_state_FSM_FFd4_In1_25, I5 => '0', O => present_state_FSM_FFd4_In ); Mmux_w_ready_c_0_SW0 : STATE_LOGIC generic map( INIT => X"0000000000000007" ) port map ( I0 => w_last_c, I1 => S_AXI_WVALID, I2 => '0', I3 => '0', I4 => '0', I5 => '0', O => N2 ); Mmux_w_ready_c_0_Q : STATE_LOGIC generic map( INIT => X"FABAFABAFAAAF000" ) port map ( I0 => N2, I1 => bready_timeout_c, I2 => S_AXI_AWVALID, I3 => present_state_FSM_FFd4_17, I4 => present_state_FSM_FFd3_18, I5 => present_state_FSM_FFd2_19, O => w_ready_c ); Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC generic map( INIT => X"0000000000000008" ) port map ( I0 => bready_timeout_c, I1 => S_AXI_WVALID, I2 => '0', I3 => '0', I4 => '0', I5 => '0', O => N4 ); present_state_FSM_FFd1_In1 : STATE_LOGIC generic map( INIT => X"88808880FFFF8880" ) port map ( I0 => w_last_c, I1 => N4, I2 => present_state_FSM_FFd2_19, I3 => present_state_FSM_FFd3_18, I4 => present_state_FSM_FFd1_16, I5 => S_AXI_BREADY, O => present_state_FSM_FFd1_In ); END GENERATE gbeh_axi_full_sm; end STRUCTURE; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; --AXI Behavioral Model entities ENTITY blk_mem_axi_read_wrapper_beh is GENERIC ( -- AXI Interface related parameters start here C_INTERFACE_TYPE : integer := 0; C_AXI_TYPE : integer := 0; C_AXI_SLAVE_TYPE : integer := 0; C_MEMORY_TYPE : integer := 0; C_WRITE_WIDTH_A : integer := 4; C_WRITE_DEPTH_A : integer := 32; C_ADDRA_WIDTH : integer := 12; C_AXI_PIPELINE_STAGES : integer := 0; C_AXI_ARADDR_WIDTH : integer := 12; C_HAS_AXI_ID : integer := 0; C_AXI_ID_WIDTH : integer := 4; C_ADDRB_WIDTH : integer := 12 ); port ( -- AXI Global Signals S_ACLK : IN std_logic; S_ARESETN : IN std_logic; -- AXI Full/Lite Slave Read (Read side) S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0'); S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0'); S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARVALID : IN std_logic := '0'; S_AXI_ARREADY : OUT std_logic; S_AXI_RLAST : OUT std_logic; S_AXI_RVALID : OUT std_logic; S_AXI_RREADY : IN std_logic := '0'; S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0'); S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0'); -- AXI Full/Lite Read Address Signals to BRAM S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0); S_AXI_RD_EN : OUT std_logic ); END blk_mem_axi_read_wrapper_beh; architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is ------------------------------------------------------------------------------ -- FUNCTION: if_then_else -- This function is used to implement an IF..THEN when such a statement is not -- allowed. ------------------------------------------------------------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : STRING; false_case : STRING) RETURN STRING IS BEGIN IF NOT condition THEN RETURN false_case; ELSE RETURN true_case; END IF; END if_then_else; FUNCTION if_then_else ( condition : BOOLEAN; true_case : INTEGER; false_case : INTEGER) RETURN INTEGER IS VARIABLE retval : INTEGER := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; FUNCTION if_then_else ( condition : BOOLEAN; true_case : STD_LOGIC_VECTOR; false_case : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS BEGIN IF NOT condition THEN RETURN false_case; ELSE RETURN true_case; END IF; END if_then_else; CONSTANT FLOP_DELAY : TIME := 100 PS; CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001"); CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0, if_then_else((C_WRITE_WIDTH_A=16),1, if_then_else((C_WRITE_WIDTH_A=32),2, if_then_else((C_WRITE_WIDTH_A=64),3, if_then_else((C_WRITE_WIDTH_A=128),4, if_then_else((C_WRITE_WIDTH_A=256),5,0)))))); SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0'); SIGNAL addr_en_c : std_logic := '0'; SIGNAL rd_en_c : std_logic := '0'; SIGNAL incr_addr_c : std_logic := '0'; SIGNAL single_trans_c : std_logic := '0'; SIGNAL dec_alen_c : std_logic := '0'; SIGNAL mux_sel_c : std_logic := '0'; SIGNAL r_last_c : std_logic := '0'; SIGNAL r_last_int_c : std_logic := '0'; SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE; SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0); SIGNAL num_of_bytes_c : integer := 0; SIGNAL total_bytes : integer := 0; SIGNAL num_of_bytes_r : integer := 0; SIGNAL wrap_base_addr_r : integer := 0; SIGNAL wrap_boundary_r : integer := 0; SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL total_bytes_c : integer := 0; SIGNAL wrap_base_addr_c : integer := 0; SIGNAL wrap_boundary_c : integer := 0; SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0'); COMPONENT read_netlist GENERIC ( -- AXI Interface related parameters start here C_AXI_TYPE : integer := 1; C_ADDRB_WIDTH : integer := 12 ); port ( S_AXI_INCR_ADDR : OUT std_logic := '0'; S_AXI_ADDR_EN : OUT std_logic := '0'; S_AXI_SINGLE_TRANS : OUT std_logic := '0'; S_AXI_MUX_SEL : OUT std_logic := '0'; S_AXI_R_LAST : OUT std_logic := '0'; S_AXI_R_LAST_INT : IN std_logic := '0'; -- AXI Global Signals S_ACLK : IN std_logic; S_ARESETN : IN std_logic; -- AXI Full/Lite Slave Read (Read side) S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0'); S_AXI_ARVALID : IN std_logic := '0'; S_AXI_ARREADY : OUT std_logic; S_AXI_RLAST : OUT std_logic; S_AXI_RVALID : OUT std_logic; S_AXI_RREADY : IN std_logic := '0'; -- AXI Full/Lite Read Address Signals to BRAM S_AXI_RD_EN : OUT std_logic ); END COMPONENT read_netlist; BEGIN dec_alen_c <= incr_addr_c OR r_last_int_c; axi_read_fsm : read_netlist GENERIC MAP( C_AXI_TYPE => 1, C_ADDRB_WIDTH => C_ADDRB_WIDTH ) PORT MAP( S_AXI_INCR_ADDR => incr_addr_c, S_AXI_ADDR_EN => addr_en_c, S_AXI_SINGLE_TRANS => single_trans_c, S_AXI_MUX_SEL => mux_sel_c, S_AXI_R_LAST => r_last_c, S_AXI_R_LAST_INT => r_last_int_c, -- AXI Global Signals S_ACLK => S_ACLK, S_ARESETN => S_ARESETN, -- AXI Full/Lite Slave Read (Read side) S_AXI_ARLEN => S_AXI_ARLEN, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RLAST => S_AXI_RLAST, S_AXI_RVALID => S_AXI_RVALID, S_AXI_RREADY => S_AXI_RREADY, -- AXI Full/Lite Read Address Signals to BRAM S_AXI_RD_EN => rd_en_c ); total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1); wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes); wrap_boundary_r <= wrap_base_addr_r+total_bytes; ---- combinatorial from interface num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000")); arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN); total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1); wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c); wrap_boundary_c <= wrap_base_addr_c+total_bytes_c; arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01"); --------------------------------------------------------------------------- -- BMG address generation --------------------------------------------------------------------------- P_addr_reg: PROCESS (S_ACLK,S_ARESETN) BEGIN IF (S_ARESETN = '1') THEN araddr_reg <= (OTHERS => '0'); arburst_int_r <= (OTHERS => '0'); num_of_bytes_r <= 0; ELSIF (S_ACLK'event AND S_ACLK = '1') THEN IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN arburst_int_r <= arburst_int_c; num_of_bytes_r <= num_of_bytes_c; IF (arburst_int_c = "10") THEN IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH); ELSE araddr_reg <= S_AXI_ARADDR + num_of_bytes_c; END IF; ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN araddr_reg <= S_AXI_ARADDR + num_of_bytes_c; END IF; ELSIF (addr_en_c = '1') THEN araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY; num_of_bytes_r <= num_of_bytes_c; arburst_int_r <= arburst_int_c; ELSIF (incr_addr_c = '1') THEN IF (arburst_int_r = "10") THEN IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH); ELSE araddr_reg <= araddr_reg + num_of_bytes_r; END IF; ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN araddr_reg <= araddr_reg + num_of_bytes_r; END IF; END IF; END IF; END PROCESS P_addr_reg; araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg); -------------------------------------------------------------------------- -- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM -------------------------------------------------------------------------- P_addr_cnt: PROCESS (S_ACLK, S_ARESETN) BEGIN IF S_ARESETN = '1' THEN arlen_cntr <= ONE; arlen_int_r <= (OTHERS => '0'); ELSIF S_ACLK'event AND S_ACLK = '1' THEN IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN); arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY; ELSIF addr_en_c = '1' THEN arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN); arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN); ELSIF dec_alen_c = '1' THEN arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY; ELSE arlen_cntr <= arlen_cntr AFTER FLOP_DELAY; END IF; END IF; END PROCESS P_addr_cnt; r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ; -------------------------------------------------------------------------- -- AXI FULL FSM -- Mux Selection of ARADDR -- ARADDR is driven out from the read fsm based on the mux_sel_c -- Based on mux_sel either ARADDR is given out or the latched ARADDR is -- given out to BRAM -------------------------------------------------------------------------- P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out) BEGIN IF (mux_sel_c = '0') THEN S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR); ELSE S_AXI_ARADDR_OUT <= araddr_out; END IF; END PROCESS P_araddr_mux; -------------------------------------------------------------------------- -- Assign output signals - AXI FULL FSM -------------------------------------------------------------------------- S_AXI_RD_EN <= rd_en_c; grid: IF (C_HAS_AXI_ID = 1) GENERATE P_rid_gen: PROCESS (S_ACLK,S_ARESETN) BEGIN IF (S_ARESETN='1') THEN S_AXI_RID <= (OTHERS => '0'); ar_id_r <= (OTHERS => '0'); ELSIF (S_ACLK'event AND S_ACLK='1') THEN IF (addr_en_c = '1' AND rd_en_c = '1') THEN S_AXI_RID <= S_AXI_ARID; ar_id_r <= S_AXI_ARID; ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN ar_id_r <= S_AXI_ARID; ELSIF (rd_en_c = '1') THEN S_AXI_RID <= ar_id_r; END IF; END IF; END PROCESS P_rid_gen; END GENERATE grid; END blk_mem_axi_read_wrapper_beh_arch; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity read_netlist is GENERIC ( -- AXI Interface related parameters start here C_AXI_TYPE : integer := 1; C_ADDRB_WIDTH : integer := 12 ); port ( S_AXI_R_LAST_INT : in STD_LOGIC := '0'; S_ACLK : in STD_LOGIC := '0'; S_ARESETN : in STD_LOGIC := '0'; S_AXI_ARVALID : in STD_LOGIC := '0'; S_AXI_RREADY : in STD_LOGIC := '0'; S_AXI_INCR_ADDR : out STD_LOGIC; S_AXI_ADDR_EN : out STD_LOGIC; S_AXI_SINGLE_TRANS : out STD_LOGIC; S_AXI_MUX_SEL : out STD_LOGIC; S_AXI_R_LAST : out STD_LOGIC; S_AXI_ARREADY : out STD_LOGIC; S_AXI_RLAST : out STD_LOGIC; S_AXI_RVALID : out STD_LOGIC; S_AXI_RD_EN : out STD_LOGIC; S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); end read_netlist; architecture STRUCTURE of read_netlist is component beh_muxf7 port( O : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic; S : in std_ulogic ); end component; COMPONENT beh_ff_pre generic( INIT : std_logic := '1' ); port( Q : out std_logic; C : in std_logic; D : in std_logic; PRE : in std_logic ); end COMPONENT beh_ff_pre; COMPONENT beh_ff_ce generic( INIT : std_logic := '0' ); port( Q : out std_logic; C : in std_logic; CE : in std_logic; CLR : in std_logic; D : in std_logic ); end COMPONENT beh_ff_ce; COMPONENT beh_ff_clr generic( INIT : std_logic := '0' ); port( Q : out std_logic; C : in std_logic; CLR : in std_logic; D : in std_logic ); end COMPONENT beh_ff_clr; COMPONENT STATE_LOGIC generic( INIT : std_logic_vector(63 downto 0) := X"0000000000000000" ); port( O : out std_logic; I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; I4 : in std_logic; I5 : in std_logic ); end COMPONENT STATE_LOGIC; signal present_state_FSM_FFd1_13 : STD_LOGIC; signal present_state_FSM_FFd2_14 : STD_LOGIC; signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC; signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC; signal gaxi_full_sm_r_last_r_17 : STD_LOGIC; signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC; signal gaxi_full_sm_r_valid_c : STD_LOGIC; signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC; signal gaxi_full_sm_ar_ready_c : STD_LOGIC; signal gaxi_full_sm_outstanding_read_c : STD_LOGIC; signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC; signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC; signal present_state_FSM_FFd2_In : STD_LOGIC; signal present_state_FSM_FFd1_In : STD_LOGIC; signal Mmux_S_AXI_R_LAST13 : STD_LOGIC; signal N01 : STD_LOGIC; signal N2 : STD_LOGIC; signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC; signal N4 : STD_LOGIC; signal N8 : STD_LOGIC; signal N9 : STD_LOGIC; signal N10 : STD_LOGIC; signal N11 : STD_LOGIC; signal N12 : STD_LOGIC; signal N13 : STD_LOGIC; begin S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST; S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16; S_AXI_RLAST <= gaxi_full_sm_r_last_r_17; S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r; gaxi_full_sm_outstanding_read_r : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => gaxi_full_sm_outstanding_read_c, Q => gaxi_full_sm_outstanding_read_r_15 ); gaxi_full_sm_r_valid_r : beh_ff_ce generic map( INIT => '0' ) port map ( C => S_ACLK, CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o, CLR => S_ARESETN, D => gaxi_full_sm_r_valid_c, Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ); gaxi_full_sm_ar_ready_r : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => gaxi_full_sm_ar_ready_c, Q => gaxi_full_sm_ar_ready_r_16 ); gaxi_full_sm_r_last_r : beh_ff_ce generic map( INIT => '0' ) port map ( C => S_ACLK, CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o, CLR => S_ARESETN, D => NlwRenamedSig_OI_S_AXI_R_LAST, Q => gaxi_full_sm_r_last_r_17 ); present_state_FSM_FFd2 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => present_state_FSM_FFd2_In, Q => present_state_FSM_FFd2_14 ); present_state_FSM_FFd1 : beh_ff_clr generic map( INIT => '0' ) port map ( C => S_ACLK, CLR => S_ARESETN, D => present_state_FSM_FFd1_In, Q => present_state_FSM_FFd1_13 ); S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC generic map( INIT => X"000000000000000B" ) port map ( I0 => S_AXI_RREADY, I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I2 => '0', I3 => '0', I4 => '0', I5 => '0', O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ); Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC generic map( INIT => X"0000000000000008" ) port map ( I0 => S_AXI_ARVALID, I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o, I2 => '0', I3 => '0', I4 => '0', I5 => '0', O => S_AXI_SINGLE_TRANS ); Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC generic map( INIT => X"0000000000000004" ) port map ( I0 => present_state_FSM_FFd1_13, I1 => S_AXI_ARVALID, I2 => '0', I3 => '0', I4 => '0', I5 => '0', O => S_AXI_ADDR_EN ); present_state_FSM_FFd2_In1 : STATE_LOGIC generic map( INIT => X"ECEE2022EEEE2022" ) port map ( I0 => S_AXI_ARVALID, I1 => present_state_FSM_FFd1_13, I2 => S_AXI_RREADY, I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o, I4 => present_state_FSM_FFd2_14, I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, O => present_state_FSM_FFd2_In ); Mmux_S_AXI_R_LAST131 : STATE_LOGIC generic map( INIT => X"0000000044440444" ) port map ( I0 => present_state_FSM_FFd1_13, I1 => S_AXI_ARVALID, I2 => present_state_FSM_FFd2_14, I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I4 => S_AXI_RREADY, I5 => '0', O => Mmux_S_AXI_R_LAST13 ); Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC generic map( INIT => X"4000FFFF40004000" ) port map ( I0 => S_AXI_R_LAST_INT, I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o, I2 => present_state_FSM_FFd2_14, I3 => present_state_FSM_FFd1_13, I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o, I5 => Mmux_S_AXI_R_LAST13, O => S_AXI_INCR_ADDR ); S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC generic map( INIT => X"00000000000000FE" ) port map ( I0 => S_AXI_ARLEN(2), I1 => S_AXI_ARLEN(1), I2 => S_AXI_ARLEN(0), I3 => '0', I4 => '0', I5 => '0', O => N01 ); S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC generic map( INIT => X"0000000000000001" ) port map ( I0 => S_AXI_ARLEN(7), I1 => S_AXI_ARLEN(6), I2 => S_AXI_ARLEN(5), I3 => S_AXI_ARLEN(4), I4 => S_AXI_ARLEN(3), I5 => N01, O => S_AXI_ARLEN_7_GND_8_o_equal_1_o ); Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC generic map( INIT => X"0000000000000007" ) port map ( I0 => S_AXI_ARVALID, I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o, I2 => '0', I3 => '0', I4 => '0', I5 => '0', O => N2 ); Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC generic map( INIT => X"0020000002200200" ) port map ( I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I1 => S_AXI_RREADY, I2 => present_state_FSM_FFd1_13, I3 => present_state_FSM_FFd2_14, I4 => gaxi_full_sm_outstanding_read_r_15, I5 => N2, O => gaxi_full_sm_outstanding_read_c ); Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC generic map( INIT => X"0000000000004555" ) port map ( I0 => S_AXI_ARVALID, I1 => S_AXI_RREADY, I2 => present_state_FSM_FFd2_14, I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I4 => '0', I5 => '0', O => Mmux_gaxi_full_sm_ar_ready_c11 ); Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC generic map( INIT => X"00000000000000EF" ) port map ( I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o, I1 => S_AXI_RREADY, I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I3 => '0', I4 => '0', I5 => '0', O => N4 ); Mmux_S_AXI_R_LAST11 : STATE_LOGIC generic map( INIT => X"FCAAFC0A00AA000A" ) port map ( I0 => S_AXI_ARVALID, I1 => gaxi_full_sm_outstanding_read_r_15, I2 => present_state_FSM_FFd2_14, I3 => present_state_FSM_FFd1_13, I4 => N4, I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o, O => gaxi_full_sm_r_valid_c ); S_AXI_MUX_SEL1 : STATE_LOGIC generic map( INIT => X"00000000AAAAAA08" ) port map ( I0 => present_state_FSM_FFd1_13, I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I2 => S_AXI_RREADY, I3 => present_state_FSM_FFd2_14, I4 => gaxi_full_sm_outstanding_read_r_15, I5 => '0', O => S_AXI_MUX_SEL ); Mmux_S_AXI_RD_EN11 : STATE_LOGIC generic map( INIT => X"F3F3F755A2A2A200" ) port map ( I0 => present_state_FSM_FFd1_13, I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I2 => S_AXI_RREADY, I3 => gaxi_full_sm_outstanding_read_r_15, I4 => present_state_FSM_FFd2_14, I5 => S_AXI_ARVALID, O => S_AXI_RD_EN ); present_state_FSM_FFd1_In3 : beh_muxf7 port map ( I0 => N8, I1 => N9, S => present_state_FSM_FFd1_13, O => present_state_FSM_FFd1_In ); present_state_FSM_FFd1_In3_F : STATE_LOGIC generic map( INIT => X"000000005410F4F0" ) port map ( I0 => S_AXI_RREADY, I1 => present_state_FSM_FFd2_14, I2 => S_AXI_ARVALID, I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o, I5 => '0', O => N8 ); present_state_FSM_FFd1_In3_G : STATE_LOGIC generic map( INIT => X"0000000072FF7272" ) port map ( I0 => present_state_FSM_FFd2_14, I1 => S_AXI_R_LAST_INT, I2 => gaxi_full_sm_outstanding_read_r_15, I3 => S_AXI_RREADY, I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I5 => '0', O => N9 ); Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7 port map ( I0 => N10, I1 => N11, S => present_state_FSM_FFd1_13, O => gaxi_full_sm_ar_ready_c ); Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC generic map( INIT => X"00000000FFFF88A8" ) port map ( I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o, I1 => S_AXI_RREADY, I2 => present_state_FSM_FFd2_14, I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I4 => Mmux_gaxi_full_sm_ar_ready_c11, I5 => '0', O => N10 ); Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC generic map( INIT => X"000000008D008D8D" ) port map ( I0 => present_state_FSM_FFd2_14, I1 => S_AXI_R_LAST_INT, I2 => gaxi_full_sm_outstanding_read_r_15, I3 => S_AXI_RREADY, I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I5 => '0', O => N11 ); Mmux_S_AXI_R_LAST1 : beh_muxf7 port map ( I0 => N12, I1 => N13, S => present_state_FSM_FFd1_13, O => NlwRenamedSig_OI_S_AXI_R_LAST ); Mmux_S_AXI_R_LAST1_F : STATE_LOGIC generic map( INIT => X"0000000088088888" ) port map ( I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o, I1 => S_AXI_ARVALID, I2 => present_state_FSM_FFd2_14, I3 => S_AXI_RREADY, I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I5 => '0', O => N12 ); Mmux_S_AXI_R_LAST1_G : STATE_LOGIC generic map( INIT => X"00000000E400E4E4" ) port map ( I0 => present_state_FSM_FFd2_14, I1 => gaxi_full_sm_outstanding_read_r_15, I2 => S_AXI_R_LAST_INT, I3 => S_AXI_RREADY, I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r, I5 => '0', O => N13 ); end STRUCTURE; ------------------------------------------------------------------------------- -- Output Register Stage Entity -- -- This module builds the output register stages of the memory. This module is -- instantiated in the main memory module (BLK_MEM_GEN_v8_2) which is -- declared/implemented further down in this file. ------------------------------------------------------------------------------- LIBRARY STD; USE STD.TEXTIO.ALL; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY BLK_MEM_GEN_v8_2_output_stage IS GENERIC ( C_FAMILY : STRING := "virtex7"; C_XDEVICEFAMILY : STRING := "virtex7"; C_RST_TYPE : STRING := "SYNC"; C_HAS_RST : INTEGER := 0; C_RSTRAM : INTEGER := 0; C_RST_PRIORITY : STRING := "CE"; init_val : STD_LOGIC_VECTOR; C_HAS_EN : INTEGER := 0; C_HAS_REGCE : INTEGER := 0; C_DATA_WIDTH : INTEGER := 32; C_ADDRB_WIDTH : INTEGER := 10; C_HAS_MEM_OUTPUT_REGS : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; C_USE_ECC : INTEGER := 0; NUM_STAGES : INTEGER := 1; C_EN_ECC_PIPE : INTEGER := 0; FLOP_DELAY : TIME := 100 ps ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; REGCE : IN STD_LOGIC; DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); SBITERR_IN_I : IN STD_LOGIC; DBITERR_IN_I : IN STD_LOGIC; SBITERR : OUT STD_LOGIC; DBITERR : OUT STD_LOGIC; RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); eccpipece : IN STD_LOGIC; RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ); END BLK_MEM_GEN_v8_2_output_stage; --****************************** -- Port and Generic Definitions --****************************** --------------------------------------------------------------------------- -- Generic Definitions --------------------------------------------------------------------------- -- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following -- options are available - "spartan3", "spartan6", -- "virtex4", "virtex5", "virtex6" and "virtex6l". -- C_RST_TYPE : Type of reset - Synchronous or Asynchronous -- C_HAS_RST : Determines the presence of the RST port -- C_RSTRAM : Determines if special reset behavior is used -- C_RST_PRIORITY : Determines the priority between CE and SR -- C_INIT_VAL : Initialization value -- C_HAS_EN : Determines the presence of the EN port -- C_HAS_REGCE : Determines the presence of the REGCE port -- C_DATA_WIDTH : Memory write/read width -- C_ADDRB_WIDTH : Width of the ADDRB input port -- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output -- of the RAM primitive -- C_USE_SOFTECC : Determines if the Soft ECC feature is used or -- not. Only applicable Spartan-6 -- C_USE_ECC : Determines if the ECC feature is used or -- not. Only applicable for V5 and V6 -- NUM_STAGES : Determines the number of output stages -- FLOP_DELAY : Constant delay for register assignments --------------------------------------------------------------------------- -- Port Definitions --------------------------------------------------------------------------- -- CLK : Clock to synchronize all read and write operations -- RST : Reset input to reset memory outputs to a user-defined -- reset state -- EN : Enable all read and write operations -- REGCE : Register Clock Enable to control each pipeline output -- register stages -- DIN : Data input to the Output stage. -- DOUT : Final Data output -- SBITERR_IN : SBITERR input signal to the Output stage. -- SBITERR : Final SBITERR Output signal. -- DBITERR_IN : DBITERR input signal to the Output stage. -- DBITERR : Final DBITERR Output signal. -- RDADDRECC_IN : RDADDRECC input signal to the Output stage. -- RDADDRECC : Final RDADDRECC Output signal. --------------------------------------------------------------------------- ARCHITECTURE output_stage_behavioral OF BLK_MEM_GEN_v8_2_output_stage IS --******************************************************* -- Functions used in the output stage ARCHITECTURE --******************************************************* -- Calculate num_reg_stages FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS VARIABLE num_reg_stages : INTEGER := 0; BEGIN IF (NUM_STAGES = 0) THEN num_reg_stages := 0; ELSE num_reg_stages := NUM_STAGES - 1; END IF; RETURN num_reg_stages; END get_num_reg_stages; -- Check if the INTEGER is zero or non-zero FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS VARIABLE temp_return : STD_LOGIC; BEGIN IF (input = 0) THEN temp_return := '0'; ELSE temp_return := '1'; END IF; RETURN temp_return; END int_to_bit; -- Constants CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN); CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE); CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST); CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES); -- Pipeline array TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC; TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val); SIGNAL out_regs : reg_data_array := REG_INIT; SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0'); SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0'); SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0')); -- Internal signals SIGNAL en_i : STD_LOGIC; SIGNAL regce_i : STD_LOGIC; SIGNAL rst_i : STD_LOGIC; SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val; SIGNAL sbiterr_i: STD_LOGIC := '0'; SIGNAL dbiterr_i: STD_LOGIC := '0'; SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ; SIGNAL SBITERR_IN : STD_LOGIC := '0'; SIGNAL DBITERR_IN : STD_LOGIC := '0'; BEGIN --*********************************************************************** -- Assign internal signals. This effectively wires off optional inputs. --*********************************************************************** -- Internal enable for output registers is tied to user EN or '1' depending -- on parameters en_i <= EN OR (NOT HAS_EN); -- Internal register enable for output registers is tied to user REGCE, EN -- or '1' depending on parameters regce_i <= (HAS_REGCE AND REGCE) OR ((NOT HAS_REGCE) AND en_i); -- Internal SRR is tied to user RST or '0' depending on parameters rst_i <= RST AND HAS_RST; --*************************************************************************** -- NUM_STAGES = 0 (No output registers. RAM only) --*************************************************************************** zero_stages: IF (NUM_STAGES = 0) GENERATE DOUT <= DIN; SBITERR <= SBITERR_IN; DBITERR <= DBITERR_IN; RDADDRECC <= RDADDRECC_IN; END GENERATE zero_stages; NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE DIN <= DIN_I; RDADDRECC_IN <= RDADDRECC_IN_I; SBITERR_IN <= SBITERR_IN_I; DBITERR_IN <= DBITERR_IN_I; END GENERATE NO_ECC_PIPE_REG; WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE PROCESS (CLK) BEGIN IF (CLK'EVENT AND CLK = '1') THEN IF(ECCPIPECE = '1') THEN DIN <= DIN_I AFTER FLOP_DELAY; RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY; SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY; DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY; END IF; END IF; END PROCESS; END GENERATE WITH_ECC_PIPE_REG; --*************************************************************************** -- NUM_STAGES = 1 -- (Mem Output Reg only or Mux Output Reg only) --*************************************************************************** -- Possible valid combinations: -- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1) -- +-----------------------------------------+ -- | C_RSTRAM_* | Reset Behavior | -- +----------------+------------------------+ -- | 0 | Normal Behavior | -- +----------------+------------------------+ -- | 1 | Special Behavior | -- +----------------+------------------------+ -- -- Normal = REGCE gates reset, as in the case of all Virtex families and all -- spartan families with the exception of S3ADSP and S6. -- Special = EN gates reset, as in the case of S3ADSP and S6. one_stage_norm: IF (NUM_STAGES = 1 AND (C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE DOUT <= dout_i; SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0'; DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0'; RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0'); PROCESS (CLK,rst_i,regce_i) BEGIN IF (CLK'EVENT AND CLK = '1') THEN IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset IF (rst_i = '1' AND regce_i='1') THEN dout_i <= init_val AFTER FLOP_DELAY; sbiterr_i <= '0' AFTER FLOP_DELAY; dbiterr_i <= '0' AFTER FLOP_DELAY; rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY; ELSIF (regce_i='1') THEN dout_i <= DIN AFTER FLOP_DELAY; sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY; dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY; rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY; END IF; ELSE --RSTA has priority and is independent of REGCE IF (rst_i = '1') THEN dout_i <= init_val AFTER FLOP_DELAY; sbiterr_i <= '0' AFTER FLOP_DELAY; dbiterr_i <= '0' AFTER FLOP_DELAY; rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY; ELSIF (regce_i='1') THEN dout_i <= DIN AFTER FLOP_DELAY; sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY; dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY; rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY; END IF; END IF;--Priority conditions END IF;--CLK END PROCESS; END GENERATE one_stage_norm; -- Special Reset Behavior for S6 and S3ADSP one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp")) GENERATE DOUT <= dout_i; SBITERR <= '0'; DBITERR <= '0'; RDADDRECC <= (OTHERS => '0'); PROCESS (CLK) BEGIN IF (CLK'EVENT AND CLK = '1') THEN IF (rst_i='1' AND en_i='1') THEN dout_i <= init_val AFTER FLOP_DELAY; ELSIF (regce_i='1' AND rst_i/='1') THEN dout_i <= DIN AFTER FLOP_DELAY; END IF; END IF;--CLK END PROCESS; END GENERATE one_stage_splbhv; --**************************************************************************** -- NUM_STAGES > 1 -- Mem Output Reg + Mux Output Reg -- or -- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg -- or -- Mux Pipeline Stages (>0) + Mux Output Reg --**************************************************************************** multi_stage: IF (NUM_STAGES > 1) GENERATE DOUT <= dout_i; SBITERR <= sbiterr_i; DBITERR <= dbiterr_i; RDADDRECC <= rdaddrecc_i; PROCESS (CLK,rst_i,regce_i) BEGIN IF (CLK'EVENT AND CLK = '1') THEN IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset IF (rst_i='1'AND regce_i='1') THEN dout_i <= init_val AFTER FLOP_DELAY; sbiterr_i <= '0' AFTER FLOP_DELAY; dbiterr_i <= '0' AFTER FLOP_DELAY; rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY; ELSIF (regce_i='1') THEN dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY; sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY; dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY; rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY; END IF; ELSE --RSTA has priority and is independent of REGCE IF (rst_i = '1') THEN dout_i <= init_val AFTER FLOP_DELAY; sbiterr_i <= '0' AFTER FLOP_DELAY; dbiterr_i <= '0' AFTER FLOP_DELAY; rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY; ELSIF (regce_i='1') THEN dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY; sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY; dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY; rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY; END IF; END IF;--Priority conditions IF (en_i='1') THEN -- Shift the data through the output stages FOR i IN 1 TO REG_STAGES-1 LOOP out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY; sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY; dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY; rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY; END LOOP; out_regs(0) <= DIN; sbiterr_regs(0) <= SBITERR_IN; dbiterr_regs(0) <= DBITERR_IN; rdaddrecc_regs(0) <= RDADDRECC_IN; END IF; END IF;--CLK END PROCESS; END GENERATE multi_stage; END output_stage_behavioral; ------------------------------------------------------------------------------- -- SoftECC Output Register Stage Entity -- This module builds the softecc output register stages. This module is -- instantiated in the memory module (BLK_MEM_GEN_v8_2_mem_module) which is -- declared/implemented further down in this file. ------------------------------------------------------------------------------- LIBRARY STD; USE STD.TEXTIO.ALL; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY BLK_MEM_GEN_v8_2_softecc_output_reg_stage IS GENERIC ( C_DATA_WIDTH : INTEGER := 32; C_ADDRB_WIDTH : INTEGER := 10; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; FLOP_DELAY : TIME := 100 ps ); PORT ( CLK : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ; DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); SBITERR_IN : IN STD_LOGIC; DBITERR_IN : IN STD_LOGIC; SBITERR : OUT STD_LOGIC; DBITERR : OUT STD_LOGIC; RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ; RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ); END BLK_MEM_GEN_v8_2_softecc_output_reg_stage; --****************************** -- Port and Generic Definitions --****************************** --------------------------------------------------------------------------- -- Generic Definitions --------------------------------------------------------------------------- -- C_DATA_WIDTH : Memory write/read width -- C_ADDRB_WIDTH : Width of the ADDRB input port -- of the RAM primitive -- FLOP_DELAY : Constant delay for register assignments --------------------------------------------------------------------------- -- Port Definitions --------------------------------------------------------------------------- -- CLK : Clock to synchronize all read and write operations -- RST : Reset input to reset memory outputs to a user-defined -- reset state -- EN : Enable all read and write operations -- REGCE : Register Clock Enable to control each pipeline output -- register stages -- DIN : Data input to the Output stage. -- DOUT : Final Data output -- SBITERR_IN : SBITERR input signal to the Output stage. -- SBITERR : Final SBITERR Output signal. -- DBITERR_IN : DBITERR input signal to the Output stage. -- DBITERR : Final DBITERR Output signal. -- RDADDRECC_IN : RDADDRECC input signal to the Output stage. -- RDADDRECC : Final RDADDRECC Output signal. --------------------------------------------------------------------------- ARCHITECTURE softecc_output_reg_stage_behavioral OF BLK_MEM_GEN_v8_2_softecc_output_reg_stage IS -- Internal signals SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL sbiterr_i: STD_LOGIC := '0'; SIGNAL dbiterr_i: STD_LOGIC := '0'; SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); BEGIN --*************************************************************************** -- NO OUTPUT STAGES --*************************************************************************** no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE DOUT <= DIN; SBITERR <= SBITERR_IN; DBITERR <= DBITERR_IN; RDADDRECC <= RDADDRECC_IN; END GENERATE no_output_stage; --**************************************************************************** -- WITH OUTPUT STAGE --**************************************************************************** has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE PROCESS (CLK) BEGIN IF (CLK'EVENT AND CLK = '1') THEN dout_i <= DIN AFTER FLOP_DELAY; sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY; dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY; rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY; END IF; END PROCESS; DOUT <= dout_i; SBITERR <= sbiterr_i; DBITERR <= dbiterr_i; RDADDRECC <= rdaddrecc_i; END GENERATE has_output_stage; END softecc_output_reg_stage_behavioral; --****************************************************************************** -- Main Memory module -- -- This module is the behavioral model which implements the RAM --****************************************************************************** LIBRARY STD; USE STD.TEXTIO.ALL; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_MISC.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.std_logic_textio.all; ENTITY BLK_MEM_GEN_v8_2_mem_module IS GENERIC ( C_CORENAME : STRING := "blk_mem_gen_v8_2"; C_FAMILY : STRING := "virtex7"; C_XDEVICEFAMILY : STRING := "virtex7"; C_USE_BRAM_BLOCK : INTEGER := 0; C_ENABLE_32BIT_ADDRESS : INTEGER := 0; C_MEM_TYPE : INTEGER := 2; C_BYTE_SIZE : INTEGER := 8; C_ALGORITHM : INTEGER := 2; C_PRIM_TYPE : INTEGER := 3; C_LOAD_INIT_FILE : INTEGER := 0; C_INIT_FILE_NAME : STRING := ""; C_INIT_FILE : STRING := ""; C_USE_DEFAULT_DATA : INTEGER := 0; C_DEFAULT_DATA : STRING := ""; C_RST_TYPE : STRING := "SYNC"; C_HAS_RSTA : INTEGER := 0; C_RST_PRIORITY_A : STRING := "CE"; C_RSTRAM_A : INTEGER := 0; C_INITA_VAL : STRING := ""; C_HAS_ENA : INTEGER := 1; C_HAS_REGCEA : INTEGER := 0; C_USE_BYTE_WEA : INTEGER := 0; C_WEA_WIDTH : INTEGER := 1; C_WRITE_MODE_A : STRING := "WRITE_FIRST"; C_WRITE_WIDTH_A : INTEGER := 32; C_READ_WIDTH_A : INTEGER := 32; C_WRITE_DEPTH_A : INTEGER := 64; C_READ_DEPTH_A : INTEGER := 64; C_ADDRA_WIDTH : INTEGER := 6; C_HAS_RSTB : INTEGER := 0; C_RST_PRIORITY_B : STRING := "CE"; C_RSTRAM_B : INTEGER := 0; C_INITB_VAL : STRING := ""; C_HAS_ENB : INTEGER := 1; C_HAS_REGCEB : INTEGER := 0; C_USE_BYTE_WEB : INTEGER := 0; C_WEB_WIDTH : INTEGER := 1; C_WRITE_MODE_B : STRING := "WRITE_FIRST"; C_WRITE_WIDTH_B : INTEGER := 32; C_READ_WIDTH_B : INTEGER := 32; C_WRITE_DEPTH_B : INTEGER := 64; C_READ_DEPTH_B : INTEGER := 64; C_ADDRB_WIDTH : INTEGER := 6; C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0; C_MUX_PIPELINE_STAGES : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; C_USE_ECC : INTEGER := 0; C_HAS_INJECTERR : INTEGER := 0; C_SIM_COLLISION_CHECK : STRING := "NONE"; C_COMMON_CLK : INTEGER := 1; FLOP_DELAY : TIME := 100 ps; C_DISABLE_WARN_BHV_COLL : INTEGER := 0; C_EN_ECC_PIPE : INTEGER := 0; C_DISABLE_WARN_BHV_RANGE : INTEGER := 0 ); PORT ( CLKA : IN STD_LOGIC := '0'; RSTA : IN STD_LOGIC := '0'; ENA : IN STD_LOGIC := '1'; REGCEA : IN STD_LOGIC := '1'; WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0'); DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0); CLKB : IN STD_LOGIC := '0'; RSTB : IN STD_LOGIC := '0'; ENB : IN STD_LOGIC := '1'; REGCEB : IN STD_LOGIC := '1'; WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0'); DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0); INJECTSBITERR : IN STD_LOGIC := '0'; INJECTDBITERR : IN STD_LOGIC := '0'; SBITERR : OUT STD_LOGIC; DBITERR : OUT STD_LOGIC; ECCPIPECE : IN STD_LOGIC; SLEEP : IN STD_LOGIC; RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ); END BLK_MEM_GEN_v8_2_mem_module; --****************************** -- Port and Generic Definitions --****************************** --------------------------------------------------------------------------- -- Generic Definitions --------------------------------------------------------------------------- -- C_CORENAME : Instance name of the Block Memory Generator core -- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following -- options are available - "spartan3", "spartan6", -- "virtex4", "virtex5", "virtex6l" and "virtex6". -- C_MEM_TYPE : Designates memory type. -- It can be -- 0 - Single Port Memory -- 1 - Simple Dual Port Memory -- 2 - True Dual Port Memory -- 3 - Single Port Read Only Memory -- 4 - Dual Port Read Only Memory -- C_BYTE_SIZE : Size of a byte (8 or 9 bits) -- C_ALGORITHM : Designates the algorithm method used -- for constructing the memory. -- It can be Fixed_Primitives, Minimum_Area or -- Low_Power -- C_PRIM_TYPE : Designates the user selected primitive used to -- construct the memory. -- -- C_LOAD_INIT_FILE : Designates the use of an initialization file to -- initialize memory contents. -- C_INIT_FILE_NAME : Memory initialization file name. -- C_USE_DEFAULT_DATA : Designates whether to fill remaining -- initialization space with default data -- C_DEFAULT_DATA : Default value of all memory locations -- not initialized by the memory -- initialization file. -- C_RST_TYPE : Type of reset - Synchronous or Asynchronous -- -- C_HAS_RSTA : Determines the presence of the RSTA port -- C_RST_PRIORITY_A : Determines the priority between CE and SR for -- Port A. -- C_RSTRAM_A : Determines if special reset behavior is used for -- Port A -- C_INITA_VAL : The initialization value for Port A -- C_HAS_ENA : Determines the presence of the ENA port -- C_HAS_REGCEA : Determines the presence of the REGCEA port -- C_USE_BYTE_WEA : Determines if the Byte Write is used or not. -- C_WEA_WIDTH : The width of the WEA port -- C_WRITE_MODE_A : Configurable write mode for Port A. It can be -- WRITE_FIRST, READ_FIRST or NO_CHANGE. -- C_WRITE_WIDTH_A : Memory write width for Port A. -- C_READ_WIDTH_A : Memory read width for Port A. -- C_WRITE_DEPTH_A : Memory write depth for Port A. -- C_READ_DEPTH_A : Memory read depth for Port A. -- C_ADDRA_WIDTH : Width of the ADDRA input port -- C_HAS_RSTB : Determines the presence of the RSTB port -- C_RST_PRIORITY_B : Determines the priority between CE and SR for -- Port B. -- C_RSTRAM_B : Determines if special reset behavior is used for -- Port B -- C_INITB_VAL : The initialization value for Port B -- C_HAS_ENB : Determines the presence of the ENB port -- C_HAS_REGCEB : Determines the presence of the REGCEB port -- C_USE_BYTE_WEB : Determines if the Byte Write is used or not. -- C_WEB_WIDTH : The width of the WEB port -- C_WRITE_MODE_B : Configurable write mode for Port B. It can be -- WRITE_FIRST, READ_FIRST or NO_CHANGE. -- C_WRITE_WIDTH_B : Memory write width for Port B. -- C_READ_WIDTH_B : Memory read width for Port B. -- C_WRITE_DEPTH_B : Memory write depth for Port B. -- C_READ_DEPTH_B : Memory read depth for Port B. -- C_ADDRB_WIDTH : Width of the ADDRB input port -- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output -- of the RAM primitive for Port A. -- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output -- of the RAM primitive for Port B. -- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output -- of the MUX for Port A. -- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output -- of the MUX for Port B. -- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in -- between the muxes. -- C_USE_SOFTECC : Determines if the Soft ECC feature is used or -- not. Only applicable Spartan-6 -- C_USE_ECC : Determines if the ECC feature is used or -- not. Only applicable for V5 and V6 -- C_HAS_INJECTERR : Determines if the error injection pins -- are present or not. If the ECC feature -- is not used, this value is defaulted to -- 0, else the following are the allowed -- values: -- 0 : No INJECTSBITERR or INJECTDBITERR pins -- 1 : Only INJECTSBITERR pin exists -- 2 : Only INJECTDBITERR pin exists -- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist -- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision -- warnings. It can be "ALL", "NONE", -- "Warnings_Only" or "Generate_X_Only". -- C_COMMON_CLK : Determins if the core has a single CLK input. -- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings -- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range -- warnings --------------------------------------------------------------------------- -- Port Definitions --------------------------------------------------------------------------- -- CLKA : Clock to synchronize all read and write operations of Port A. -- RSTA : Reset input to reset memory outputs to a user-defined -- reset state for Port A. -- ENA : Enable all read and write operations of Port A. -- REGCEA : Register Clock Enable to control each pipeline output -- register stages for Port A. -- WEA : Write Enable to enable all write operations of Port A. -- ADDRA : Address of Port A. -- DINA : Data input of Port A. -- DOUTA : Data output of Port A. -- CLKB : Clock to synchronize all read and write operations of Port B. -- RSTB : Reset input to reset memory outputs to a user-defined -- reset state for Port B. -- ENB : Enable all read and write operations of Port B. -- REGCEB : Register Clock Enable to control each pipeline output -- register stages for Port B. -- WEB : Write Enable to enable all write operations of Port B. -- ADDRB : Address of Port B. -- DINB : Data input of Port B. -- DOUTB : Data output of Port B. -- INJECTSBITERR : Single Bit ECC Error Injection Pin. -- INJECTDBITERR : Double Bit ECC Error Injection Pin. -- SBITERR : Output signal indicating that a Single Bit ECC Error has been -- detected and corrected. -- DBITERR : Output signal indicating that a Double Bit ECC Error has been -- detected. -- RDADDRECC : Read Address Output signal indicating address at which an -- ECC error has occurred. --------------------------------------------------------------------------- ARCHITECTURE mem_module_behavioral OF BLK_MEM_GEN_v8_2_mem_module IS --**************************************** -- min/max constant functions --**************************************** -- get_max ---------- function SLV_TO_INT(SLV: in std_logic_vector ) return integer is variable int : integer; begin int := 0; for i in SLV'high downto SLV'low loop int := int * 2; if SLV(i) = '1' then int := int + 1; end if; end loop; return int; end; FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS BEGIN IF (a > b) THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION; -- get_min ---------- FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS BEGIN IF (a < b) THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION; --*************************************************************** -- convert write_mode from STRING type for use in case statement --*************************************************************** FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS BEGIN IF (mode = "NO_CHANGE") THEN RETURN "10"; ELSIF (mode = "READ_FIRST") THEN RETURN "01"; ELSE RETURN "00"; -- WRITE_FIRST END IF; END FUNCTION; --*************************************************************** -- convert hex STRING to STD_LOGIC_VECTOR --*************************************************************** FUNCTION hex_to_std_logic_vector( hex_str : STRING; return_width : INTEGER) RETURN STD_LOGIC_VECTOR IS VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1 DOWNTO 0); BEGIN tmp := (OTHERS => '0'); FOR i IN 1 TO hex_str'LENGTH LOOP CASE hex_str((hex_str'LENGTH+1)-i) IS WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000"; WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001"; WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010"; WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011"; WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100"; WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101"; WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110"; WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111"; WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000"; WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001"; WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010"; WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011"; WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100"; WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101"; WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110"; WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111"; WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111"; END CASE; END LOOP; RETURN tmp(return_width-1 DOWNTO 0); END hex_to_std_logic_vector; --*************************************************************** -- convert bit to STD_LOGIC --*************************************************************** FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS VARIABLE temp_return : STD_LOGIC; BEGIN IF (input = '0') THEN temp_return := '0'; ELSE temp_return := '1'; END IF; RETURN temp_return; END bit_to_sl; --*************************************************************** -- locally derived constants to determine memory shape --*************************************************************** CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A); CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B); CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B); CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A); CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B); CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B); TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0); TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0); TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC; TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC; --*************************************************************** -- memory initialization function --*************************************************************** IMPURE FUNCTION init_memory(DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0); write_width_a : INTEGER; depth : INTEGER; width : INTEGER) RETURN mem_array IS VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0')); FILE init_file : TEXT; VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0); VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0')); VARIABLE file_buffer : LINE; VARIABLE i : INTEGER := 0; VARIABLE j : INTEGER; VARIABLE k : INTEGER; VARIABLE ignore_line : BOOLEAN := false; VARIABLE good_data : BOOLEAN := false; VARIABLE char_tmp : CHARACTER; VARIABLE index : INTEGER; variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0'); variable data : std_logic_vector(255 downto 0) := (others => '0'); variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0'); variable k_slv : std_logic_vector(31 downto 0) := (others => '0'); variable i_slv : std_logic_vector(31 downto 0) := (others => '0'); VARIABLE disp_line : line := null; variable open_status : file_open_status; variable input_initf_tmp : mem_array ; variable input_initf : mem_array := (others => (others => '0')); file int_infile : text; variable data_line, data_line_tmp, out_data_line : line; variable slv_width : integer; VARIABLE d_l : LINE; BEGIN --Display output message indicating that the behavioral model is being --initialized -- Setup the default data -- Default data is with respect to write_port_A and may be wider -- or narrower than init_return width. The following loops map -- default data into the memory IF (C_USE_DEFAULT_DATA=1) THEN index := 0; FOR i IN 0 TO depth-1 LOOP FOR j IN 0 TO width-1 LOOP init_return(i)(j) := DEFAULT_DATA(index); index := (index + 1) MOD C_WRITE_WIDTH_A; END LOOP; END LOOP; END IF; -- Read in the .mif file -- The init data is formatted with respect to write port A dimensions. -- The init_return vector is formatted with respect to minimum width and -- maximum depth; the following loops map the .mif file into the memory IF (C_LOAD_INIT_FILE=1) THEN file_open(init_file, C_INIT_FILE_NAME, read_mode); i := 0; WHILE (i < depth AND NOT endfile(init_file)) LOOP mem_vector := (OTHERS => '0'); readline(init_file, file_buffer); read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0)); FOR j IN 0 TO write_width_a-1 LOOP IF (j MOD width = 0 AND j /= 0) THEN i := i + 1; END IF; init_return(i)(j MOD width) := bit_to_sl(mem_vector(j)); END LOOP; i := i + 1; END LOOP; file_close(init_file); END IF; --Display output message indicating that the behavioral model is done --initializing ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE; if (C_USE_BRAM_BLOCK = 1) then --Display output message indicating that the behavioral model is being --initialized -- Read in the .mem file -- The init data is formatted with respect to write port A dimensions. -- The init_return vector is formatted with respect to minimum width and -- maximum depth; the following loops map the .mif file into the memory IF (C_INIT_FILE /= "NONE") then file_open(open_status, int_infile, C_INIT_FILE, read_mode); while not endfile(int_infile) loop readline(int_infile, data_line); while (data_line /= null and data_line'length > 0) loop if (data_line(data_line'low to data_line'low + 1) = "//") then deallocate(data_line); elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then deallocate(data_line); elsif (data_line(data_line'low to data_line'low + 1) = "/*") then deallocate(data_line); ignore_line := true; elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then deallocate(data_line); ignore_line := false; elsif (ignore_line = false and data_line(data_line'low) = '@') then read(data_line, char_tmp); hread(data_line, init_addr_slv, good_data); i := SLV_TO_INT(init_addr_slv); elsif (ignore_line = false) then hread(data_line, input_initf_tmp(i), good_data); init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0); if (good_data = true) then i := i + 1; end if; else deallocate(data_line); end if; end loop; end loop; file_close(int_infile); END IF; END IF; RETURN init_return; END FUNCTION; --*************************************************************** -- memory type constants --*************************************************************** CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0; CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1; CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2; CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3; CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4; --*************************************************************** -- memory configuration constant functions --*************************************************************** --get_single_port ----------------- FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS BEGIN IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN RETURN 1; ELSE RETURN 0; END IF; END get_single_port; --get_is_rom -------------- FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS BEGIN IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN RETURN 1; ELSE RETURN 0; END IF; END get_is_rom; --get_has_a_write ------------------ FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS BEGIN IF (IS_ROM=0) THEN RETURN 1; ELSE RETURN 0; END IF; END get_has_a_write; --get_has_b_write ------------------ FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS BEGIN IF (mem_type=MEM_TYPE_TDP_RAM) THEN RETURN 1; ELSE RETURN 0; END IF; END get_has_b_write; --get_has_a_read ------------------ FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS BEGIN IF (mem_type=MEM_TYPE_SDP_RAM) THEN RETURN 0; ELSE RETURN 1; END IF; END get_has_a_read; --get_has_b_read ------------------ FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS BEGIN IF (SINGLE_PORT=1) THEN RETURN 0; ELSE RETURN 1; END IF; END get_has_b_read; --get_has_b_port ------------------ FUNCTION get_has_b_port(HAS_B_READ : INTEGER; HAS_B_WRITE : INTEGER) RETURN INTEGER IS BEGIN IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN RETURN 1; ELSE RETURN 0; END IF; END get_has_b_port; --get_num_output_stages ----------------------- FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER; has_mux_output_regs : INTEGER; mux_pipeline_stages : INTEGER) RETURN INTEGER IS VARIABLE actual_mux_pipeline_stages : INTEGER; BEGIN -- Mux pipeline stages can be non-zero only when there is a mux -- output register. IF (has_mux_output_regs=1) THEN actual_mux_pipeline_stages := mux_pipeline_stages; ELSE actual_mux_pipeline_stages := 0; END IF; RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs; END get_num_output_stages; --*************************************************************************** -- Component declaration of the VARIABLE depth output register stage --*************************************************************************** COMPONENT BLK_MEM_GEN_v8_2_output_stage GENERIC ( C_FAMILY : STRING := "virtex7"; C_XDEVICEFAMILY : STRING := "virtex7"; C_RST_TYPE : STRING := "SYNC"; C_HAS_RST : INTEGER := 0; C_RSTRAM : INTEGER := 0; C_RST_PRIORITY : STRING := "CE"; init_val : STD_LOGIC_VECTOR; C_HAS_EN : INTEGER := 0; C_HAS_REGCE : INTEGER := 0; C_DATA_WIDTH : INTEGER := 32; C_ADDRB_WIDTH : INTEGER := 10; C_HAS_MEM_OUTPUT_REGS : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; C_USE_ECC : INTEGER := 0; NUM_STAGES : INTEGER := 1; C_EN_ECC_PIPE : INTEGER := 0; FLOP_DELAY : TIME := 100 ps); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; REGCE : IN STD_LOGIC; EN : IN STD_LOGIC; DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); SBITERR_IN_I : IN STD_LOGIC; DBITERR_IN_I : IN STD_LOGIC; SBITERR : OUT STD_LOGIC; DBITERR : OUT STD_LOGIC; RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); ECCPIPECE : IN STD_LOGIC; RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ); END COMPONENT BLK_MEM_GEN_v8_2_output_stage; COMPONENT BLK_MEM_GEN_v8_2_softecc_output_reg_stage GENERIC ( C_DATA_WIDTH : INTEGER := 32; C_ADDRB_WIDTH : INTEGER := 10; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; FLOP_DELAY : TIME := 100 ps ); PORT ( CLK : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); SBITERR_IN : IN STD_LOGIC; DBITERR_IN : IN STD_LOGIC; SBITERR : OUT STD_LOGIC; DBITERR : OUT STD_LOGIC; RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ); END COMPONENT BLK_MEM_GEN_v8_2_softecc_output_reg_stage; --****************************************************** -- locally derived constants to assist memory access --****************************************************** CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH; CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH; CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH; CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH; --****************************************************** -- To modify the LSBs of the 'wider' data to the actual -- address value --****************************************************** CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A; CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A; CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B; CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B; --****************************************************** -- FUNCTION : log2roundup --****************************************************** FUNCTION log2roundup ( data_value : INTEGER) RETURN INTEGER IS VARIABLE width : INTEGER := 0; VARIABLE cnt : INTEGER := 1; BEGIN IF (data_value <= 1) THEN width := 0; ELSE WHILE (cnt < data_value) LOOP width := width + 1; cnt := cnt *2; END LOOP; END IF; RETURN width; END log2roundup; ----------------------------------------------------------------------------- -- FUNCTION : log2int ----------------------------------------------------------------------------- FUNCTION log2int ( data_value : INTEGER) RETURN INTEGER IS VARIABLE width : INTEGER := 0; VARIABLE cnt : INTEGER := data_value; BEGIN WHILE (cnt >1) LOOP width := width + 1; cnt := cnt/2; END LOOP; RETURN width; END log2int; ------------------------------------------------------------------------------ -- FUNCTION: if_then_else -- This function is used to implement an IF..THEN when such a statement is not -- allowed. ------------------------------------------------------------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : INTEGER; false_case : INTEGER) RETURN INTEGER IS VARIABLE retval : INTEGER := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; --****************************************************** -- Other constants and signals --****************************************************** CONSTANT COLL_DELAY : TIME := 100 ps; -- default data vector CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := hex_to_std_logic_vector(C_DEFAULT_DATA, C_WRITE_WIDTH_A); CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0))))); -- the init memory SIGNAL SIGNAL memory_i : mem_array; SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0); SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0); -- write mode constants CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) := write_mode_to_vector(C_WRITE_MODE_A); CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) := write_mode_to_vector(C_WRITE_MODE_B); CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) := WRITE_MODE_A & WRITE_MODE_B; -- reset values CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) := hex_to_std_logic_vector(C_INITA_VAL, C_READ_WIDTH_A); CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := hex_to_std_logic_vector(C_INITB_VAL, C_READ_WIDTH_B); -- memory output 'latches' SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) := INITA_VAL; SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := INITB_VAL; SIGNAL sbiterr_in : STD_LOGIC := '0'; SIGNAL sbiterr_sdp : STD_LOGIC := '0'; SIGNAL dbiterr_in : STD_LOGIC := '0'; SIGNAL dbiterr_sdp : STD_LOGIC := '0'; SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL sbiterr_i : STD_LOGIC := '0'; SIGNAL dbiterr_i : STD_LOGIC := '0'; -- memory configuration constants ----------------------------------------------- CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE); CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE); CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM); CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE); CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE); CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT); CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE); CONSTANT NUM_OUTPUT_STAGES_A : INTEGER := get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A, C_MUX_PIPELINE_STAGES); CONSTANT NUM_OUTPUT_STAGES_B : INTEGER := get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B, C_MUX_PIPELINE_STAGES); CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ----------------------------------------------------------------------------- -- DEBUG CONTROL -- DEBUG=0 : Debug output OFF -- DEBUG=1 : Some debug info printed ----------------------------------------------------------------------------- CONSTANT DEBUG : INTEGER := 0; -- internal signals ----------------------------------------------- SIGNAL ena_i : STD_LOGIC; SIGNAL enb_i : STD_LOGIC; SIGNAL reseta_i : STD_LOGIC; SIGNAL resetb_i : STD_LOGIC; SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0); SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0); SIGNAL rea_i : STD_LOGIC; SIGNAL reb_i : STD_LOGIC; SIGNAL message_complete : BOOLEAN := false; SIGNAL rsta_outp_stage : STD_LOGIC := '0'; SIGNAL rstb_outp_stage : STD_LOGIC := '0'; --********************************************************* --FUNCTION : Collision check --********************************************************* FUNCTION collision_check (addr_a : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0); iswrite_a : BOOLEAN; addr_b : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); iswrite_b : BOOLEAN) RETURN BOOLEAN IS VARIABLE c_aw_bw : INTEGER; VARIABLE c_aw_br : INTEGER; VARIABLE c_ar_bw : INTEGER; VARIABLE write_addr_a_width : INTEGER; VARIABLE read_addr_a_width : INTEGER; VARIABLE write_addr_b_width : INTEGER; VARIABLE read_addr_b_width : INTEGER; BEGIN c_aw_bw := 0; c_aw_br := 0; c_ar_bw := 0; -- Determine the effective address widths FOR each of the 4 ports write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV); read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV); write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV); read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV); --Look FOR a write-write collision. In order FOR a write-write --collision to exist, both ports must have a write transaction. IF (iswrite_a AND iswrite_b) THEN IF (write_addr_a_width > write_addr_b_width) THEN --write_addr_b_width is smaller, so scale both addresses to that -- width FOR comparing write_addr_a and write_addr_b --addr_a starts as C_ADDRA_WIDTH, -- scale it down to write_addr_b_width --addr_b starts as C_ADDRB_WIDTH, -- scale it down to write_addr_b_width --Once both are scaled to write_addr_b_width, compare. IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) = (conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN c_aw_bw := 1; ELSE c_aw_bw := 0; END IF; ELSE --write_addr_a_width is smaller, so scale both addresses to that -- width FOR comparing write_addr_a and write_addr_b --addr_a starts as C_ADDRA_WIDTH, -- scale it down to write_addr_a_width --addr_b starts as C_ADDRB_WIDTH, -- scale it down to write_addr_a_width --Once both are scaled to write_addr_a_width, compare. IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) = (conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN c_aw_bw := 1; ELSE c_aw_bw := 0; END IF; END IF; --width END IF; --iswrite_a and iswrite_b --If the B port is reading (which means it is enabled - so could be -- a TX_WRITE or TX_READ), then check FOR a write-read collision). --This could happen whether or not a write-write collision exists due -- to asymmetric write/read ports. IF (iswrite_a) THEN IF (write_addr_a_width > read_addr_b_width) THEN --read_addr_b_width is smaller, so scale both addresses to that -- width FOR comparing write_addr_a and read_addr_b --addr_a starts as C_ADDRA_WIDTH, -- scale it down to read_addr_b_width --addr_b starts as C_ADDRB_WIDTH, -- scale it down to read_addr_b_width --Once both are scaled to read_addr_b_width, compare. IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) = (conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN c_aw_br := 1; ELSE c_aw_br := 0; END IF; ELSE --write_addr_a_width is smaller, so scale both addresses to that -- width FOR comparing write_addr_a and read_addr_b --addr_a starts as C_ADDRA_WIDTH, -- scale it down to write_addr_a_width --addr_b starts as C_ADDRB_WIDTH, -- scale it down to write_addr_a_width --Once both are scaled to write_addr_a_width, compare. IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) = (conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN c_aw_br := 1; ELSE c_aw_br := 0; END IF; END IF; --width END IF; --iswrite_a --If the A port is reading (which means it is enabled - so could be -- a TX_WRITE or TX_READ), then check FOR a write-read collision). --This could happen whether or not a write-write collision exists due -- to asymmetric write/read ports. IF (iswrite_b) THEN IF (read_addr_a_width > write_addr_b_width) THEN --write_addr_b_width is smaller, so scale both addresses to that -- width FOR comparing read_addr_a and write_addr_b --addr_a starts as C_ADDRA_WIDTH, -- scale it down to write_addr_b_width --addr_b starts as C_ADDRB_WIDTH, -- scale it down to write_addr_b_width --Once both are scaled to write_addr_b_width, compare. IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) = (conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN c_ar_bw := 1; ELSE c_ar_bw := 0; END IF; ELSE --read_addr_a_width is smaller, so scale both addresses to that -- width FOR comparing read_addr_a and write_addr_b --addr_a starts as C_ADDRA_WIDTH, -- scale it down to read_addr_a_width --addr_b starts as C_ADDRB_WIDTH, -- scale it down to read_addr_a_width --Once both are scaled to read_addr_a_width, compare. IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) = (conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN c_ar_bw := 1; ELSE c_ar_bw := 0; END IF; END IF; --width END IF; --iswrite_b RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1); END FUNCTION collision_check; BEGIN -- Architecture ----------------------------------------------------------------------------- -- SOFTECC and ECC SBITERR/DBITERR Outputs -- The ECC Behavior is modeled by the behavioral models only for Virtex-6. -- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6. -- For Virtex-5, these outputs will be tied to 0. ----------------------------------------------------------------------------- SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0'; DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0'; RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0'); ----------------------------------------------- -- This effectively wires off optional inputs ----------------------------------------------- ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1'; enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1'; wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0; web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0; rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0'; reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0'; -- these signals reset the memory latches -- For the special reset behaviors in some of the families, the C_RSTRAM -- attribute of the corresponding port is used to indicate if the latch is -- reset or not. reseta_i <= RSTA WHEN ((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR (C_HAS_RSTA=1 AND C_RSTRAM_A=1)) ELSE '0'; resetb_i <= RSTB WHEN ((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR (C_HAS_RSTB=1 AND C_RSTRAM_B=1) ) ELSE '0'; --*************************************************************************** -- This is the main PROCESS which includes the memory VARIABLE and the read -- and write procedures. It also schedules read and write operations --*************************************************************************** PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i) -- Initialize the init memory array ------------------------------------ VARIABLE memory : mem_array := init_memory(DEFAULT_DATA, C_WRITE_WIDTH_A, MAX_DEPTH, MIN_WIDTH); -- Initialize the mem memory array ------------------------------------ VARIABLE softecc_sbiterr_arr : softecc_err_array; VARIABLE softecc_dbiterr_arr : softecc_err_array; VARIABLE sbiterr_arr : ecc_err_array; VARIABLE dbiterr_arr : ecc_err_array; CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11"; CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0'); VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ; VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0); --*********************************** -- procedures to access the memory --*********************************** -- write_a ---------- PROCEDURE write_a (addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0); byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0); data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0); inj_sbiterr : IN STD_LOGIC; inj_dbiterr : IN STD_LOGIC) IS VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0); VARIABLE address_i : INTEGER; VARIABLE i : INTEGER; VARIABLE message : LINE; VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN -- Block Memory Generator non-cycle-accurate message ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior." SEVERITY NOTE; message_complete <= true; -- Shift the address by the ratio address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV); IF (address_i >= C_WRITE_DEPTH_A) THEN IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN ASSERT FALSE REPORT C_CORENAME & " WARNING: Address " & INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write" SEVERITY WARNING; END IF; -- valid address ELSE -- Combine w/ byte writes IF (C_USE_BYTE_WEA = 1) THEN -- Get the current memory contents FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) := memory(address_i*WRITE_WIDTH_RATIO_A + i); END LOOP; -- Apply incoming bytes FOR i IN 0 TO C_WEA_WIDTH-1 LOOP IF (byte_en(i) = '1') THEN current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i) := data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i); END IF; END LOOP; -- No byte-writes, overwrite the whole word ELSE current_contents := data; END IF; -- Insert double bit errors: IF (C_USE_ECC = 1) THEN IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN current_contents(0) := NOT(current_contents(0)); current_contents(1) := NOT(current_contents(1)); END IF; END IF; -- Insert double bit errors: IF (C_USE_SOFTECC=1) THEN IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0); doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1); doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2); current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0); END IF; END IF; IF(DEBUG=1) THEN current_contents_var := current_contents; --for debugging current END IF; -- Write data to memory FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP memory(address_i*WRITE_WIDTH_RATIO_A + i) := current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i); END LOOP; -- Store address at which error is injected: IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN sbiterr_arr(address_i) := '1'; ELSE sbiterr_arr(address_i) := '0'; END IF; IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN dbiterr_arr(address_i) := '1'; ELSE dbiterr_arr(address_i) := '0'; END IF; END IF; -- Store address at which softecc error is injected: IF (C_USE_SOFTECC = 1) THEN IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN softecc_sbiterr_arr(address_i) := '1'; ELSE softecc_sbiterr_arr(address_i) := '0'; END IF; IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN softecc_dbiterr_arr(address_i) := '1'; ELSE softecc_dbiterr_arr(address_i) := '0'; END IF; END IF; END IF; END PROCEDURE; -- write_b ---------- PROCEDURE write_b (addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0); data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); VARIABLE address_i : INTEGER; VARIABLE i : INTEGER; BEGIN -- Shift the address by the ratio address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV); IF (address_i >= C_WRITE_DEPTH_B) THEN IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN ASSERT FALSE REPORT C_CORENAME & " WARNING: Address " & INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write" SEVERITY WARNING; END IF; -- valid address ELSE -- Combine w/ byte writes IF (C_USE_BYTE_WEB = 1) THEN -- Get the current memory contents FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) := memory(address_i*WRITE_WIDTH_RATIO_B + i); END LOOP; -- Apply incoming bytes FOR i IN 0 TO C_WEB_WIDTH-1 LOOP IF (byte_en(i) = '1') THEN current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i) := data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i); END IF; END LOOP; -- No byte-writes, overwrite the whole word ELSE current_contents := data; END IF; -- Write data to memory FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP memory(address_i*WRITE_WIDTH_RATIO_B + i) := current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i); END LOOP; END IF; END PROCEDURE; -- read_a ---------- PROCEDURE read_a (addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0); reset : IN STD_LOGIC) IS VARIABLE address_i : INTEGER; VARIABLE i : INTEGER; BEGIN IF (reset = '1') THEN memory_out_a <= INITA_VAL AFTER FLOP_DELAY; ELSE -- Shift the address by the ratio address_i := (conv_integer(addr)/READ_ADDR_A_DIV); IF (address_i >= C_READ_DEPTH_A) THEN IF (C_DISABLE_WARN_BHV_RANGE=0) THEN ASSERT FALSE REPORT C_CORENAME & " WARNING: Address " & INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read" SEVERITY WARNING; END IF; memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY; -- valid address ELSE -- Increment through the 'partial' words in the memory FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <= memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY; END LOOP; END IF; END IF; END PROCEDURE; -- read_b ---------- PROCEDURE read_b (addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); reset : IN STD_LOGIC) IS VARIABLE address_i : INTEGER; VARIABLE i : INTEGER; BEGIN IF (reset = '1') THEN memory_out_b <= INITB_VAL AFTER FLOP_DELAY; sbiterr_in <= '0' AFTER FLOP_DELAY; dbiterr_in <= '0' AFTER FLOP_DELAY; rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY; ELSE -- Shift the address by the ratio address_i := (conv_integer(addr)/READ_ADDR_B_DIV); IF (address_i >= C_READ_DEPTH_B) THEN IF (C_DISABLE_WARN_BHV_RANGE=0) THEN ASSERT FALSE REPORT C_CORENAME & " WARNING: Address " & INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read" SEVERITY WARNING; END IF; memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY; sbiterr_in <= 'X' AFTER FLOP_DELAY; dbiterr_in <= 'X' AFTER FLOP_DELAY; rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY; -- valid address ELSE -- Increment through the 'partial' words in the memory FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <= memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY; END LOOP; --assert sbiterr and dbiterr signals IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN rdaddrecc_in <= addr AFTER FLOP_DELAY; IF (sbiterr_arr(address_i) = '1') THEN sbiterr_in <= '1' AFTER FLOP_DELAY; ELSE sbiterr_in <= '0' AFTER FLOP_DELAY; END IF; IF (dbiterr_arr(address_i) = '1') THEN dbiterr_in <= '1' AFTER FLOP_DELAY; ELSE dbiterr_in <= '0' AFTER FLOP_DELAY; END IF; --assert softecc sbiterr and dbiterr signals ELSIF (C_USE_SOFTECC = 1) THEN rdaddrecc_in <= addr AFTER FLOP_DELAY; IF (softecc_sbiterr_arr(address_i) = '1') THEN sbiterr_in <= '1' AFTER FLOP_DELAY; ELSE sbiterr_in <= '0' AFTER FLOP_DELAY; END IF; IF (softecc_dbiterr_arr(address_i) = '1') THEN dbiterr_in <= '1' AFTER FLOP_DELAY; ELSE dbiterr_in <= '0' AFTER FLOP_DELAY; END IF; ELSE sbiterr_in <= '0' AFTER FLOP_DELAY; dbiterr_in <= '0' AFTER FLOP_DELAY; rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY; END IF; END IF; END IF; END PROCEDURE; -- reset_a ---------- PROCEDURE reset_a (reset : IN STD_LOGIC) IS BEGIN IF (reset = '1') THEN memory_out_a <= INITA_VAL AFTER FLOP_DELAY; END IF; END PROCEDURE; -- reset_b ---------- PROCEDURE reset_b (reset : IN STD_LOGIC) IS BEGIN IF (reset = '1') THEN memory_out_b <= INITB_VAL AFTER FLOP_DELAY; END IF; END PROCEDURE; BEGIN -- begin the main PROCESS --*************************************************************************** -- These are the main blocks which schedule read and write operations -- Note that the reset priority feature at the latch stage is only supported -- for Spartan-6. For other families, the default priority at the latch stage -- is "CE" --*************************************************************************** -- Synchronous clocks: schedule port operations with respect to both -- write operating modes IF (C_COMMON_CLK=1) THEN IF (CLKA='1' AND CLKA'EVENT) THEN CASE WRITE_MODES IS WHEN "0000" => -- write_first write_first --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; --Read A IF (rea_i='1') THEN read_a(ADDRA, reseta_i); END IF; --Read B IF (reb_i='1') THEN read_b(ADDRB, resetb_i); END IF; WHEN "0100" => -- read_first write_first --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; --Read B IF (reb_i='1') THEN read_b(ADDRB, resetb_i); END IF; --Read A IF (rea_i='1') THEN read_a(ADDRA, reseta_i); END IF; --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; WHEN "0001" => -- write_first read_first --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Read A IF (rea_i='1') THEN read_a(ADDRA, reseta_i); END IF; --Read B IF (reb_i='1') THEN read_b(ADDRB, resetb_i); END IF; --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; WHEN "0101" => --read_first read_first --Read A IF (rea_i='1') THEN read_a(ADDRA, reseta_i); END IF; --Read B IF (reb_i='1') THEN read_b(ADDRB, resetb_i); END IF; --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; WHEN "0010" => -- write_first no_change --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Read A IF (rea_i='1') THEN read_a(ADDRA, reseta_i); END IF; --Read B IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN read_b(ADDRB, resetb_i); END IF; --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; WHEN "0110" => -- read_first no_change --Read A IF (rea_i='1') THEN read_a(ADDRA, reseta_i); END IF; --Read B IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN read_b(ADDRB, resetb_i); END IF; --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; WHEN "1000" => -- no_change write_first --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; --Read A IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN read_a(ADDRA, reseta_i); END IF; --Read B IF (reb_i='1') THEN read_b(ADDRB, resetb_i); END IF; WHEN "1001" => -- no_change read_first --Read B IF (reb_i='1') THEN read_b(ADDRB, resetb_i); END IF; --Read A IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN read_a(ADDRA, reseta_i); END IF; --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; WHEN "1010" => -- no_change no_change --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; --Read A IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN read_a(ADDRA, reseta_i); END IF; --Read B IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN read_b(ADDRB, resetb_i); END IF; WHEN OTHERS => ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR; END CASE; END IF; END IF; -- Synchronous clocks -- Asynchronous clocks: port operation is independent IF (C_COMMON_CLK=0) THEN IF (CLKA='1' AND CLKA'EVENT) THEN CASE WRITE_MODE_A IS WHEN "00" => -- write_first --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Read A IF (rea_i='1') THEN read_a(ADDRA, reseta_i); END IF; WHEN "01" => -- read_first --Read A IF (rea_i='1') THEN read_a(ADDRA, reseta_i); END IF; --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; WHEN "10" => -- no_change --Write A IF (wea_i/=WEA0) THEN write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR); END IF; --Read A IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN read_a(ADDRA, reseta_i); END IF; WHEN OTHERS => ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR; END CASE; END IF; IF (CLKB='1' AND CLKB'EVENT) THEN CASE WRITE_MODE_B IS WHEN "00" => -- write_first --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; --Read B IF (reb_i='1') THEN read_b(ADDRB, resetb_i); END IF; WHEN "01" => -- read_first --Read B IF (reb_i='1') THEN read_b(ADDRB, resetb_i); END IF; --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; WHEN "10" => -- no_change --Write B IF (web_i/=WEB0) THEN write_b(ADDRB, web_i, DINB); END IF; --Read B IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN read_b(ADDRB, resetb_i); END IF; WHEN OTHERS => ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR; END CASE; END IF; END IF; -- Asynchronous clocks -- Assign the memory VARIABLE to the user_visible memory_i SIGNAL IF(DEBUG=1) THEN memory_i <= memory; doublebit_error_i <= doublebit_error; current_contents_i <= current_contents_var; END IF; END PROCESS; --******************************************************************** -- Instantiate the VARIABLE depth output stage --******************************************************************** -- Port A rsta_outp_stage <= RSTA and not sleep; rstb_outp_stage <= RSTB and not sleep; reg_a : BLK_MEM_GEN_v8_2_output_stage GENERIC MAP( C_FAMILY => C_FAMILY, C_XDEVICEFAMILY => C_XDEVICEFAMILY, C_RST_TYPE => "SYNC", C_HAS_RST => C_HAS_RSTA, C_RSTRAM => C_RSTRAM_A, C_RST_PRIORITY => C_RST_PRIORITY_A, init_val => INITA_VAL, C_HAS_EN => C_HAS_ENA, C_HAS_REGCE => C_HAS_REGCEA, C_DATA_WIDTH => C_READ_WIDTH_A, C_ADDRB_WIDTH => C_ADDRB_WIDTH, C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A, C_USE_SOFTECC => C_USE_SOFTECC, C_USE_ECC => C_USE_ECC, NUM_STAGES => NUM_OUTPUT_STAGES_A, C_EN_ECC_PIPE => C_EN_ECC_PIPE, FLOP_DELAY => FLOP_DELAY ) PORT MAP ( CLK => CLKA, RST => rsta_outp_stage, --RSTA, EN => ENA, REGCE => REGCEA, DIN_I => memory_out_a, DOUT => DOUTA, SBITERR_IN_I => '0', DBITERR_IN_I => '0', SBITERR => OPEN, DBITERR => OPEN, RDADDRECC_IN_I => (OTHERS => '0'), ECCPIPECE => '0', RDADDRECC => OPEN ); -- Port B reg_b : BLK_MEM_GEN_v8_2_output_stage GENERIC MAP( C_FAMILY => C_FAMILY, C_XDEVICEFAMILY => C_XDEVICEFAMILY, C_RST_TYPE => "SYNC", C_HAS_RST => C_HAS_RSTB, C_RSTRAM => C_RSTRAM_B, C_RST_PRIORITY => C_RST_PRIORITY_B, init_val => INITB_VAL, C_HAS_EN => C_HAS_ENB, C_HAS_REGCE => C_HAS_REGCEB, C_DATA_WIDTH => C_READ_WIDTH_B, C_ADDRB_WIDTH => C_ADDRB_WIDTH, C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B, C_USE_SOFTECC => C_USE_SOFTECC, C_USE_ECC => C_USE_ECC, NUM_STAGES => NUM_OUTPUT_STAGES_B, C_EN_ECC_PIPE => C_EN_ECC_PIPE, FLOP_DELAY => FLOP_DELAY ) PORT MAP ( CLK => CLKB, RST => rstb_outp_stage,--RSTB, EN => ENB, REGCE => REGCEB, DIN_I => memory_out_b, DOUT => doutb_i, SBITERR_IN_I => sbiterr_in, DBITERR_IN_I => dbiterr_in, SBITERR => sbiterr_i, DBITERR => dbiterr_i, RDADDRECC_IN_I => rdaddrecc_in, ECCPIPECE => ECCPIPECE, RDADDRECC => rdaddrecc_i ); --******************************************************************** -- Instantiate the input / Output Register stages --******************************************************************** output_reg_stage: BLK_MEM_GEN_v8_2_softecc_output_reg_stage GENERIC MAP( C_DATA_WIDTH => C_READ_WIDTH_B, C_ADDRB_WIDTH => C_ADDRB_WIDTH, C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B, C_USE_SOFTECC => C_USE_SOFTECC, FLOP_DELAY => FLOP_DELAY ) PORT MAP( CLK => CLKB, DIN => doutb_i, DOUT => DOUTB, SBITERR_IN => sbiterr_i, DBITERR_IN => dbiterr_i, SBITERR => sbiterr_sdp, DBITERR => dbiterr_sdp, RDADDRECC_IN => rdaddrecc_i, RDADDRECC => rdaddrecc_sdp ); --********************************* -- Synchronous collision checks --********************************* sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE PROCESS (CLKA) use IEEE.STD_LOGIC_TEXTIO.ALL; -- collision detect VARIABLE is_collision : BOOLEAN; VARIABLE message : LINE; BEGIN IF (CLKA='1' AND CLKA'EVENT) THEN -- Possible collision if both are enabled and the addresses match -- Not checking the collision condition when there is an 'x' on the Addr bus IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN is_collision := collision_check(ADDRA, wea_i/=WEA0, ADDRB, web_i/=WEB0); ELSE is_collision := false; END IF; -- If the write port is in READ_FIRST mode, there is no collision IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN is_collision := false; END IF; IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN is_collision := false; END IF; -- Only flag if one of the accesses is a write IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN write(message, C_CORENAME); write(message, STRING'(" WARNING: collision detected: ")); IF (wea_i/=WEA0) THEN write(message, STRING'("A write address: ")); ELSE write(message, STRING'("A read address: ")); END IF; write(message, ADDRA); IF (web_i/=WEB0) THEN write(message, STRING'(", B write address: ")); ELSE write(message, STRING'(", B read address: ")); END IF; write(message, ADDRB); write(message, LF); ASSERT false REPORT message.ALL SEVERITY WARNING; deallocate(message); END IF; END IF; END PROCESS; END GENERATE; --********************************* -- Asynchronous collision checks --********************************* async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0); SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0); SIGNAL ena_delay : STD_LOGIC; SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0); SIGNAL enb_delay : STD_LOGIC; BEGIN -- Delay A and B addresses in order to mimic setup/hold times PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i) BEGIN addra_delay <= ADDRA AFTER COLL_DELAY; wea_delay <= wea_i AFTER COLL_DELAY; ena_delay <= ena_i AFTER COLL_DELAY; addrb_delay <= ADDRB AFTER COLL_DELAY; web_delay <= web_i AFTER COLL_DELAY; enb_delay <= enb_i AFTER COLL_DELAY; END PROCESS; -- Do the checks w/rt A PROCESS (CLKA) use IEEE.STD_LOGIC_TEXTIO.ALL; VARIABLE is_collision_a : BOOLEAN; VARIABLE is_collision_delay_a : BOOLEAN; VARIABLE message : LINE; BEGIN -- Possible collision if both are enabled and the addresses match -- Not checking the collision condition when there is an 'x' on the Addr bus IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN is_collision_a := collision_check(ADDRA, wea_i/=WEA0, ADDRB, web_i/=WEB0); ELSE is_collision_a := false; END IF; IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN is_collision_delay_a := collision_check(ADDRA, wea_i/=WEA0, addrb_delay, web_delay/=WEB0); ELSE is_collision_delay_a := false; END IF; -- Only flag if B access is a write IF (is_collision_a AND web_i/=WEB0) THEN write(message, C_CORENAME); write(message, STRING'(" WARNING: collision detected: ")); IF (wea_i/=WEA0) THEN write(message, STRING'("A write address: ")); ELSE write(message, STRING'("A read address: ")); END IF; write(message, ADDRA); write(message, STRING'(", B write address: ")); write(message, ADDRB); write(message, LF); ASSERT false REPORT message.ALL SEVERITY WARNING; deallocate(message); ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN write(message, C_CORENAME); write(message, STRING'(" WARNING: collision detected: ")); IF (wea_i/=WEA0) THEN write(message, STRING'("A write address: ")); ELSE write(message, STRING'("A read address: ")); END IF; write(message, ADDRA); write(message, STRING'(", B write address: ")); write(message, addrb_delay); write(message, LF); ASSERT false REPORT message.ALL SEVERITY WARNING; deallocate(message); END IF; END PROCESS; -- Do the checks w/rt B PROCESS (CLKB) use IEEE.STD_LOGIC_TEXTIO.ALL; VARIABLE is_collision_b : BOOLEAN; VARIABLE is_collision_delay_b : BOOLEAN; VARIABLE message : LINE; BEGIN -- Possible collision if both are enabled and the addresses match -- Not checking the collision condition when there is an 'x' on the Addr bus IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN is_collision_b := collision_check(ADDRA, wea_i/=WEA0, ADDRB, web_i/=WEB0); ELSE is_collision_b := false; END IF; IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN is_collision_delay_b := collision_check(addra_delay, wea_delay/=WEA0, ADDRB, web_i/=WEB0); ELSE is_collision_delay_b := false; END IF; -- Only flag if A access is a write -- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228 IF (is_collision_b AND wea_i/=WEA0) THEN write(message, C_CORENAME); write(message, STRING'(" WARNING: collision detected: ")); write(message, STRING'("A write address: ")); write(message, ADDRA); IF (web_i/=WEB0) THEN write(message, STRING'(", B write address: ")); ELSE write(message, STRING'(", B read address: ")); END IF; write(message, ADDRB); write(message, LF); ASSERT false REPORT message.ALL SEVERITY WARNING; deallocate(message); ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN write(message, C_CORENAME); write(message, STRING'(" WARNING: collision detected: ")); write(message, STRING'("A write address: ")); write(message, addra_delay); IF (web_i/=WEB0) THEN write(message, STRING'(", B write address: ")); ELSE write(message, STRING'(", B read address: ")); END IF; write(message, ADDRB); write(message, LF); ASSERT false REPORT message.ALL SEVERITY WARNING; deallocate(message); END IF; END PROCESS; END GENERATE; END mem_module_behavioral; --****************************************************************************** -- Top module that wraps SoftECC Input register stage and the main memory module -- -- This module is the top-level of behavioral model --****************************************************************************** LIBRARY STD; USE STD.TEXTIO.ALL; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY blk_mem_gen_v8_2 IS GENERIC ( C_CORENAME : STRING := "blk_mem_gen_v8_2"; C_FAMILY : STRING := "virtex7"; C_XDEVICEFAMILY : STRING := "virtex7"; C_ELABORATION_DIR : STRING := ""; C_INTERFACE_TYPE : INTEGER := 0; C_USE_BRAM_BLOCK : INTEGER := 0; C_ENABLE_32BIT_ADDRESS : INTEGER := 0; C_CTRL_ECC_ALGO : STRING := "NONE"; C_AXI_TYPE : INTEGER := 0; C_AXI_SLAVE_TYPE : INTEGER := 0; C_HAS_AXI_ID : INTEGER := 0; C_AXI_ID_WIDTH : INTEGER := 4; C_MEM_TYPE : INTEGER := 2; C_BYTE_SIZE : INTEGER := 8; C_ALGORITHM : INTEGER := 2; C_PRIM_TYPE : INTEGER := 3; C_LOAD_INIT_FILE : INTEGER := 0; C_INIT_FILE_NAME : STRING := ""; C_INIT_FILE : STRING := ""; C_USE_DEFAULT_DATA : INTEGER := 0; C_DEFAULT_DATA : STRING := ""; --C_RST_TYPE : STRING := "SYNC"; C_HAS_RSTA : INTEGER := 0; C_RST_PRIORITY_A : STRING := "CE"; C_RSTRAM_A : INTEGER := 0; C_INITA_VAL : STRING := ""; C_HAS_ENA : INTEGER := 1; C_HAS_REGCEA : INTEGER := 0; C_USE_BYTE_WEA : INTEGER := 0; C_WEA_WIDTH : INTEGER := 1; C_WRITE_MODE_A : STRING := "WRITE_FIRST"; C_WRITE_WIDTH_A : INTEGER := 32; C_READ_WIDTH_A : INTEGER := 32; C_WRITE_DEPTH_A : INTEGER := 64; C_READ_DEPTH_A : INTEGER := 64; C_ADDRA_WIDTH : INTEGER := 6; C_HAS_RSTB : INTEGER := 0; C_RST_PRIORITY_B : STRING := "CE"; C_RSTRAM_B : INTEGER := 0; C_INITB_VAL : STRING := ""; C_HAS_ENB : INTEGER := 1; C_HAS_REGCEB : INTEGER := 0; C_USE_BYTE_WEB : INTEGER := 0; C_WEB_WIDTH : INTEGER := 1; C_WRITE_MODE_B : STRING := "WRITE_FIRST"; C_WRITE_WIDTH_B : INTEGER := 32; C_READ_WIDTH_B : INTEGER := 32; C_WRITE_DEPTH_B : INTEGER := 64; C_READ_DEPTH_B : INTEGER := 64; C_ADDRB_WIDTH : INTEGER := 6; C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0; C_MUX_PIPELINE_STAGES : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; C_USE_ECC : INTEGER := 0; C_EN_ECC_PIPE : INTEGER := 0; C_HAS_INJECTERR : INTEGER := 0; C_SIM_COLLISION_CHECK : STRING := "NONE"; C_COMMON_CLK : INTEGER := 1; C_DISABLE_WARN_BHV_COLL : INTEGER := 0; C_EN_SLEEP_PIN : INTEGER := 0; C_USE_URAM : integer := 0; C_EN_RDADDRA_CHG : integer := 0; C_EN_RDADDRB_CHG : integer := 0; C_EN_DEEPSLEEP_PIN : integer := 0; C_EN_SHUTDOWN_PIN : integer := 0; C_DISABLE_WARN_BHV_RANGE : INTEGER := 0; C_COUNT_36K_BRAM : string := ""; C_COUNT_18K_BRAM : string := ""; C_EST_POWER_SUMMARY : string := "" ); PORT ( clka : IN STD_LOGIC := '0'; rsta : IN STD_LOGIC := '0'; ena : IN STD_LOGIC := '1'; regcea : IN STD_LOGIC := '1'; wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0'); dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0); clkb : IN STD_LOGIC := '0'; rstb : IN STD_LOGIC := '0'; enb : IN STD_LOGIC := '1'; regceb : IN STD_LOGIC := '1'; web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0'); doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0); injectsbiterr : IN STD_LOGIC := '0'; injectdbiterr : IN STD_LOGIC := '0'; sbiterr : OUT STD_LOGIC := '0'; dbiterr : OUT STD_LOGIC := '0'; rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); eccpipece : in std_logic := '0'; sleep : in std_logic := '0'; deepsleep : in std_logic := '0'; shutdown : in std_logic := '0'; -- AXI BMG Input and Output Port Declarations -- AXI Global Signals s_aclk : IN STD_LOGIC := '0'; s_aresetn : IN STD_LOGIC := '0'; -- axi full/lite slave Write (write side) s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); s_axi_awvalid : IN STD_LOGIC := '0'; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wlast : IN STD_LOGIC := '0'; s_axi_wvalid : IN STD_LOGIC := '0'; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC := '0'; -- axi full/lite slave Read (Write side) s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); s_axi_arvalid : IN STD_LOGIC := '0'; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC := '0'; -- axi full/lite sideband Signals s_axi_injectsbiterr : IN STD_LOGIC := '0'; s_axi_injectdbiterr : IN STD_LOGIC := '0'; s_axi_sbiterr : OUT STD_LOGIC := '0'; s_axi_dbiterr : OUT STD_LOGIC := '0'; s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ); END blk_mem_gen_v8_2; --****************************** -- Port and Generic Definitions --****************************** --------------------------------------------------------------------------- -- Generic Definitions --------------------------------------------------------------------------- -- C_CORENAME : Instance name of the Block Memory Generator core -- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following -- options are available - "spartan3", "spartan6", -- "virtex4", "virtex5", "virtex6l" and "virtex6". -- C_MEM_TYPE : Designates memory type. -- It can be -- 0 - Single Port Memory -- 1 - Simple Dual Port Memory -- 2 - True Dual Port Memory -- 3 - Single Port Read Only Memory -- 4 - Dual Port Read Only Memory -- C_BYTE_SIZE : Size of a byte (8 or 9 bits) -- C_ALGORITHM : Designates the algorithm method used -- for constructing the memory. -- It can be Fixed_Primitives, Minimum_Area or -- Low_Power -- C_PRIM_TYPE : Designates the user selected primitive used to -- construct the memory. -- -- C_LOAD_INIT_FILE : Designates the use of an initialization file to -- initialize memory contents. -- C_INIT_FILE_NAME : Memory initialization file name. -- C_USE_DEFAULT_DATA : Designates whether to fill remaining -- initialization space with default data -- C_DEFAULT_DATA : Default value of all memory locations -- not initialized by the memory -- initialization file. -- C_RST_TYPE : Type of reset - Synchronous or Asynchronous -- -- C_HAS_RSTA : Determines the presence of the RSTA port -- C_RST_PRIORITY_A : Determines the priority between CE and SR for -- Port A. -- C_RSTRAM_A : Determines if special reset behavior is used for -- Port A -- C_INITA_VAL : The initialization value for Port A -- C_HAS_ENA : Determines the presence of the ENA port -- C_HAS_REGCEA : Determines the presence of the REGCEA port -- C_USE_BYTE_WEA : Determines if the Byte Write is used or not. -- C_WEA_WIDTH : The width of the WEA port -- C_WRITE_MODE_A : Configurable write mode for Port A. It can be -- WRITE_FIRST, READ_FIRST or NO_CHANGE. -- C_WRITE_WIDTH_A : Memory write width for Port A. -- C_READ_WIDTH_A : Memory read width for Port A. -- C_WRITE_DEPTH_A : Memory write depth for Port A. -- C_READ_DEPTH_A : Memory read depth for Port A. -- C_ADDRA_WIDTH : Width of the ADDRA input port -- C_HAS_RSTB : Determines the presence of the RSTB port -- C_RST_PRIORITY_B : Determines the priority between CE and SR for -- Port B. -- C_RSTRAM_B : Determines if special reset behavior is used for -- Port B -- C_INITB_VAL : The initialization value for Port B -- C_HAS_ENB : Determines the presence of the ENB port -- C_HAS_REGCEB : Determines the presence of the REGCEB port -- C_USE_BYTE_WEB : Determines if the Byte Write is used or not. -- C_WEB_WIDTH : The width of the WEB port -- C_WRITE_MODE_B : Configurable write mode for Port B. It can be -- WRITE_FIRST, READ_FIRST or NO_CHANGE. -- C_WRITE_WIDTH_B : Memory write width for Port B. -- C_READ_WIDTH_B : Memory read width for Port B. -- C_WRITE_DEPTH_B : Memory write depth for Port B. -- C_READ_DEPTH_B : Memory read depth for Port B. -- C_ADDRB_WIDTH : Width of the ADDRB input port -- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output -- of the RAM primitive for Port A. -- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output -- of the RAM primitive for Port B. -- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output -- of the MUX for Port A. -- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output -- of the MUX for Port B. -- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in -- between the muxes. -- C_USE_SOFTECC : Determines if the Soft ECC feature is used or -- not. Only applicable Spartan-6 -- C_USE_ECC : Determines if the ECC feature is used or -- not. Only applicable for V5 and V6 -- C_HAS_INJECTERR : Determines if the error injection pins -- are present or not. If the ECC feature -- is not used, this value is defaulted to -- 0, else the following are the allowed -- values: -- 0 : No INJECTSBITERR or INJECTDBITERR pins -- 1 : Only INJECTSBITERR pin exists -- 2 : Only INJECTDBITERR pin exists -- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist -- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision -- warnings. It can be "ALL", "NONE", -- "Warnings_Only" or "Generate_X_Only". -- C_COMMON_CLK : Determins if the core has a single CLK input. -- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings -- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range -- warnings --------------------------------------------------------------------------- -- Port Definitions --------------------------------------------------------------------------- -- CLKA : Clock to synchronize all read and write operations of Port A. -- RSTA : Reset input to reset memory outputs to a user-defined -- reset state for Port A. -- ENA : Enable all read and write operations of Port A. -- REGCEA : Register Clock Enable to control each pipeline output -- register stages for Port A. -- WEA : Write Enable to enable all write operations of Port A. -- ADDRA : Address of Port A. -- DINA : Data input of Port A. -- DOUTA : Data output of Port A. -- CLKB : Clock to synchronize all read and write operations of Port B. -- RSTB : Reset input to reset memory outputs to a user-defined -- reset state for Port B. -- ENB : Enable all read and write operations of Port B. -- REGCEB : Register Clock Enable to control each pipeline output -- register stages for Port B. -- WEB : Write Enable to enable all write operations of Port B. -- ADDRB : Address of Port B. -- DINB : Data input of Port B. -- DOUTB : Data output of Port B. -- INJECTSBITERR : Single Bit ECC Error Injection Pin. -- INJECTDBITERR : Double Bit ECC Error Injection Pin. -- SBITERR : Output signal indicating that a Single Bit ECC Error has been -- detected and corrected. -- DBITERR : Output signal indicating that a Double Bit ECC Error has been -- detected. -- RDADDRECC : Read Address Output signal indicating address at which an -- ECC error has occurred. --------------------------------------------------------------------------- ARCHITECTURE behavioral OF BLK_MEM_GEN_v8_2 IS COMPONENT BLK_MEM_GEN_v8_2_mem_module GENERIC ( C_CORENAME : STRING := "blk_mem_gen_v8_2"; C_FAMILY : STRING := "virtex7"; C_XDEVICEFAMILY : STRING := "virtex7"; C_USE_BRAM_BLOCK : INTEGER := 0; C_ENABLE_32BIT_ADDRESS : INTEGER := 0; C_MEM_TYPE : INTEGER := 2; C_BYTE_SIZE : INTEGER := 8; C_ALGORITHM : INTEGER := 2; C_PRIM_TYPE : INTEGER := 3; C_LOAD_INIT_FILE : INTEGER := 0; C_INIT_FILE_NAME : STRING := ""; C_INIT_FILE : STRING := ""; C_USE_DEFAULT_DATA : INTEGER := 0; C_DEFAULT_DATA : STRING := ""; C_RST_TYPE : STRING := "SYNC"; C_HAS_RSTA : INTEGER := 0; C_RST_PRIORITY_A : STRING := "CE"; C_RSTRAM_A : INTEGER := 0; C_INITA_VAL : STRING := ""; C_HAS_ENA : INTEGER := 1; C_HAS_REGCEA : INTEGER := 0; C_USE_BYTE_WEA : INTEGER := 0; C_WEA_WIDTH : INTEGER := 1; C_WRITE_MODE_A : STRING := "WRITE_FIRST"; C_WRITE_WIDTH_A : INTEGER := 32; C_READ_WIDTH_A : INTEGER := 32; C_WRITE_DEPTH_A : INTEGER := 64; C_READ_DEPTH_A : INTEGER := 64; C_ADDRA_WIDTH : INTEGER := 6; C_HAS_RSTB : INTEGER := 0; C_RST_PRIORITY_B : STRING := "CE"; C_RSTRAM_B : INTEGER := 0; C_INITB_VAL : STRING := ""; C_HAS_ENB : INTEGER := 1; C_HAS_REGCEB : INTEGER := 0; C_USE_BYTE_WEB : INTEGER := 0; C_WEB_WIDTH : INTEGER := 1; C_WRITE_MODE_B : STRING := "WRITE_FIRST"; C_WRITE_WIDTH_B : INTEGER := 32; C_READ_WIDTH_B : INTEGER := 32; C_WRITE_DEPTH_B : INTEGER := 64; C_READ_DEPTH_B : INTEGER := 64; C_ADDRB_WIDTH : INTEGER := 6; C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0; C_MUX_PIPELINE_STAGES : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; C_USE_ECC : INTEGER := 0; C_HAS_INJECTERR : INTEGER := 0; C_SIM_COLLISION_CHECK : STRING := "NONE"; C_COMMON_CLK : INTEGER := 1; FLOP_DELAY : TIME := 100 ps; C_DISABLE_WARN_BHV_COLL : INTEGER := 0; C_EN_ECC_PIPE : INTEGER := 0; C_DISABLE_WARN_BHV_RANGE : INTEGER := 0 ); PORT ( CLKA : IN STD_LOGIC := '0'; RSTA : IN STD_LOGIC := '0'; ENA : IN STD_LOGIC := '1'; REGCEA : IN STD_LOGIC := '1'; WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0'); DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0); CLKB : IN STD_LOGIC := '0'; RSTB : IN STD_LOGIC := '0'; ENB : IN STD_LOGIC := '1'; REGCEB : IN STD_LOGIC := '1'; WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0'); DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0); INJECTSBITERR : IN STD_LOGIC := '0'; INJECTDBITERR : IN STD_LOGIC := '0'; ECCPIPECE : IN STD_LOGIC; SLEEP : IN STD_LOGIC; SBITERR : OUT STD_LOGIC; DBITERR : OUT STD_LOGIC; RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ); END COMPONENT BLK_MEM_GEN_v8_2_mem_module; COMPONENT blk_mem_axi_regs_fwd_v8_2 IS GENERIC( C_DATA_WIDTH : INTEGER := 8 ); PORT ( ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; S_VALID : IN STD_LOGIC; S_READY : OUT STD_LOGIC; S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); M_VALID : OUT STD_LOGIC; M_READY : IN STD_LOGIC; M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ); END COMPONENT blk_mem_axi_regs_fwd_v8_2; COMPONENT blk_mem_axi_read_wrapper_beh GENERIC ( -- AXI Interface related parameters start here C_INTERFACE_TYPE : integer := 0; C_AXI_TYPE : integer := 0; C_AXI_SLAVE_TYPE : integer := 0; C_MEMORY_TYPE : integer := 0; C_WRITE_WIDTH_A : integer := 4; C_WRITE_DEPTH_A : integer := 32; C_ADDRA_WIDTH : integer := 12; C_AXI_PIPELINE_STAGES : integer := 0; C_AXI_ARADDR_WIDTH : integer := 12; C_HAS_AXI_ID : integer := 0; C_AXI_ID_WIDTH : integer := 4; C_ADDRB_WIDTH : integer := 12 ); PORT ( -- AXI Global Signals S_ACLK : IN std_logic; S_ARESETN : IN std_logic; -- AXI Full/Lite Slave Read (Read side) S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0'); S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0'); S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARVALID : IN std_logic := '0'; S_AXI_ARREADY : OUT std_logic; S_AXI_RLAST : OUT std_logic; S_AXI_RVALID : OUT std_logic; S_AXI_RREADY : IN std_logic := '0'; S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0'); S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0'); -- AXI Full/Lite Read Address Signals to BRAM S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0); S_AXI_RD_EN : OUT std_logic ); END COMPONENT blk_mem_axi_read_wrapper_beh; COMPONENT blk_mem_axi_write_wrapper_beh GENERIC ( -- AXI Interface related parameters start here C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full; C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE; C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM; C_WRITE_DEPTH_A : integer := 0; C_AXI_AWADDR_WIDTH : integer := 32; C_ADDRA_WIDTH : integer := 12; C_AXI_WDATA_WIDTH : integer := 32; C_HAS_AXI_ID : integer := 0; C_AXI_ID_WIDTH : integer := 4; -- AXI OUTSTANDING WRITES C_AXI_OS_WR : integer := 2 ); PORT ( -- AXI Global Signals S_ACLK : IN std_logic; S_ARESETN : IN std_logic; -- AXI Full/Lite Slave Write Channel (write side) S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWVALID : IN std_logic := '0'; S_AXI_AWREADY : OUT std_logic := '0'; S_AXI_WVALID : IN std_logic := '0'; S_AXI_WREADY : OUT std_logic := '0'; S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_BVALID : OUT std_logic := '0'; S_AXI_BREADY : IN std_logic := '0'; -- Signals for BMG interface S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0); S_AXI_WR_EN : OUT std_logic:= '0' ); END COMPONENT blk_mem_axi_write_wrapper_beh; CONSTANT FLOP_DELAY : TIME := 100 ps; SIGNAL rsta_in : STD_LOGIC := '1'; SIGNAL ena_in : STD_LOGIC := '1'; SIGNAL regcea_in : STD_LOGIC := '1'; SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0'); SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0); SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0'); SIGNAL injectsbiterr_in : STD_LOGIC := '0'; SIGNAL injectdbiterr_in : STD_LOGIC := '0'; ----------------------------------------------------------------------------- -- FUNCTION: toLowerCaseChar -- Returns the lower case form of char if char is an upper case letter. -- Otherwise char is returned. ----------------------------------------------------------------------------- FUNCTION toLowerCaseChar( char : character ) RETURN character IS BEGIN -- If char is not an upper case letter then return char IF char<'A' OR char>'Z' THEN RETURN char; END IF; -- Otherwise map char to its corresponding lower case character and -- RETURN that CASE char IS WHEN 'A' => RETURN 'a'; WHEN 'B' => RETURN 'b'; WHEN 'C' => RETURN 'c'; WHEN 'D' => RETURN 'd'; WHEN 'E' => RETURN 'e'; WHEN 'F' => RETURN 'f'; WHEN 'G' => RETURN 'g'; WHEN 'H' => RETURN 'h'; WHEN 'I' => RETURN 'i'; WHEN 'J' => RETURN 'j'; WHEN 'K' => RETURN 'k'; WHEN 'L' => RETURN 'l'; WHEN 'M' => RETURN 'm'; WHEN 'N' => RETURN 'n'; WHEN 'O' => RETURN 'o'; WHEN 'P' => RETURN 'p'; WHEN 'Q' => RETURN 'q'; WHEN 'R' => RETURN 'r'; WHEN 'S' => RETURN 's'; WHEN 'T' => RETURN 't'; WHEN 'U' => RETURN 'u'; WHEN 'V' => RETURN 'v'; WHEN 'W' => RETURN 'w'; WHEN 'X' => RETURN 'x'; WHEN 'Y' => RETURN 'y'; WHEN 'Z' => RETURN 'z'; WHEN OTHERS => RETURN char; END CASE; END toLowerCaseChar; -- Returns true if case insensitive string comparison determines that -- str1 and str2 are equal FUNCTION equalIgnoreCase( str1 : STRING; str2 : STRING ) RETURN BOOLEAN IS CONSTANT len1 : INTEGER := str1'length; CONSTANT len2 : INTEGER := str2'length; VARIABLE equal : BOOLEAN := TRUE; BEGIN IF NOT (len1=len2) THEN equal := FALSE; ELSE FOR i IN str2'left TO str1'right LOOP IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN equal := FALSE; END IF; END LOOP; END IF; RETURN equal; END equalIgnoreCase; ----------------------------------------------------------------------------- -- FUNCTION: if_then_else -- This function is used to implement an IF..THEN when such a statement is not -- allowed. ---------------------------------------------------------------------------- FUNCTION if_then_else ( condition : BOOLEAN; true_case : STRING; false_case : STRING) RETURN STRING IS BEGIN IF NOT condition THEN RETURN false_case; ELSE RETURN true_case; END IF; END if_then_else; FUNCTION if_then_else ( condition : BOOLEAN; true_case : INTEGER; false_case : INTEGER) RETURN INTEGER IS BEGIN IF NOT condition THEN RETURN false_case; ELSE RETURN true_case; END IF; END if_then_else; FUNCTION if_then_else ( condition : BOOLEAN; true_case : STD_LOGIC_VECTOR; false_case : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS BEGIN IF NOT condition THEN RETURN false_case; ELSE RETURN true_case; END IF; END if_then_else; ---------------------------------------------------------------------------- -- FUNCTION : log2roundup ---------------------------------------------------------------------------- FUNCTION log2roundup ( data_value : INTEGER) RETURN INTEGER IS VARIABLE width : INTEGER := 0; VARIABLE cnt : INTEGER := 1; CONSTANT lower_limit : INTEGER := 1; CONSTANT upper_limit : INTEGER := 8; BEGIN IF (data_value <= 1) THEN width := 0; ELSE WHILE (cnt < data_value) LOOP width := width + 1; cnt := cnt *2; END LOOP; END IF; RETURN width; END log2roundup; ----------------------------------------------------------------------------- -- FUNCTION : log2int ----------------------------------------------------------------------------- FUNCTION log2int ( data_value : INTEGER) RETURN INTEGER IS VARIABLE width : INTEGER := 0; VARIABLE cnt : INTEGER := data_value; BEGIN WHILE (cnt >1) LOOP width := width + 1; cnt := cnt/2; END LOOP; RETURN width; END log2int; ----------------------------------------------------------------------------- -- FUNCTION : divroundup -- Returns the ceiling value of the division -- Data_value - the quantity to be divided, dividend -- Divisor - the value to divide the data_value by ----------------------------------------------------------------------------- FUNCTION divroundup ( data_value : INTEGER; divisor : INTEGER) RETURN INTEGER IS VARIABLE div : INTEGER; BEGIN div := data_value/divisor; IF ( (data_value MOD divisor) /= 0) THEN div := div+1; END IF; RETURN div; END divroundup; SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL s_axi_wr_en_c : STD_LOGIC := '0'; SIGNAL s_axi_rd_en_c : STD_LOGIC := '0'; SIGNAL s_aresetn_a_c : STD_LOGIC := '0'; --************************************************************************** -- AXI PARAMETERS CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0); CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8); CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB; -- Data Width Number of LSB address bits to be discarded -- 1 to 16 1 -- 17 to 32 2 -- 33 to 64 3 -- 65 to 128 4 -- 129 to 256 5 -- 257 to 512 6 -- 513 to 1024 7 -- The following two constants determine this. CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8))); CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL); CONSTANT C_AXI_OS_WR : integer := 2; --************************************************************************** BEGIN -- Architecture --************************************************************************* -- NO INPUT STAGE --************************************************************************* no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE rsta_in <= RSTA; ena_in <= ENA; regcea_in <= REGCEA; wea_in <= WEA; addra_in <= ADDRA; dina_in <= DINA; injectsbiterr_in <= INJECTSBITERR; injectdbiterr_in <= INJECTDBITERR; END GENERATE no_input_stage; --************************************************************************** -- WITH INPUT STAGE --************************************************************************** has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE PROCESS (CLKA) BEGIN IF (CLKA'EVENT AND CLKA = '1') THEN rsta_in <= RSTA AFTER FLOP_DELAY; ena_in <= ENA AFTER FLOP_DELAY; regcea_in <= REGCEA AFTER FLOP_DELAY; wea_in <= WEA AFTER FLOP_DELAY; addra_in <= ADDRA AFTER FLOP_DELAY; dina_in <= DINA AFTER FLOP_DELAY; injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY; injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY; END IF; END PROCESS; END GENERATE has_input_stage; --************************************************************************** -- NATIVE MEMORY MODULE INSTANCE --************************************************************************** native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE mem_module: BLK_MEM_GEN_v8_2_mem_module GENERIC MAP( C_CORENAME => C_CORENAME, C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY)))))))))))))))))), C_XDEVICEFAMILY => C_XDEVICEFAMILY, C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK, C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS, C_MEM_TYPE => C_MEM_TYPE, C_BYTE_SIZE => C_BYTE_SIZE, C_ALGORITHM => C_ALGORITHM, C_PRIM_TYPE => C_PRIM_TYPE, C_LOAD_INIT_FILE => C_LOAD_INIT_FILE, C_INIT_FILE_NAME => C_INIT_FILE_NAME, C_INIT_FILE => C_INIT_FILE, C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA, C_DEFAULT_DATA => C_DEFAULT_DATA, C_RST_TYPE => "SYNC", C_HAS_RSTA => C_HAS_RSTA, C_RST_PRIORITY_A => C_RST_PRIORITY_A, C_RSTRAM_A => C_RSTRAM_A, C_INITA_VAL => C_INITA_VAL, C_HAS_ENA => C_HAS_ENA, C_HAS_REGCEA => C_HAS_REGCEA, C_USE_BYTE_WEA => C_USE_BYTE_WEA, C_WEA_WIDTH => C_WEA_WIDTH, C_WRITE_MODE_A => C_WRITE_MODE_A, C_WRITE_WIDTH_A => C_WRITE_WIDTH_A, C_READ_WIDTH_A => C_READ_WIDTH_A, C_WRITE_DEPTH_A => C_WRITE_DEPTH_A, C_READ_DEPTH_A => C_READ_DEPTH_A, C_ADDRA_WIDTH => C_ADDRA_WIDTH, C_HAS_RSTB => C_HAS_RSTB, C_RST_PRIORITY_B => C_RST_PRIORITY_B, C_RSTRAM_B => C_RSTRAM_B, C_INITB_VAL => C_INITB_VAL, C_HAS_ENB => C_HAS_ENB, C_HAS_REGCEB => C_HAS_REGCEB, C_USE_BYTE_WEB => C_USE_BYTE_WEB, C_WEB_WIDTH => C_WEB_WIDTH, C_WRITE_MODE_B => C_WRITE_MODE_B, C_WRITE_WIDTH_B => C_WRITE_WIDTH_B, C_READ_WIDTH_B => C_READ_WIDTH_B, C_WRITE_DEPTH_B => C_WRITE_DEPTH_B, C_READ_DEPTH_B => C_READ_DEPTH_B, C_ADDRB_WIDTH => C_ADDRB_WIDTH, C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B, C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A, C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B, C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES, C_USE_SOFTECC => C_USE_SOFTECC, C_USE_ECC => C_USE_ECC, C_HAS_INJECTERR => C_HAS_INJECTERR, C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK, C_COMMON_CLK => C_COMMON_CLK, FLOP_DELAY => FLOP_DELAY, C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL, C_EN_ECC_PIPE => C_EN_ECC_PIPE, C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE ) PORT MAP( CLKA => CLKA, RSTA => rsta_in, ENA => ena_in, REGCEA => regcea_in, WEA => wea_in, ADDRA => addra_in, DINA => dina_in, DOUTA => DOUTA, CLKB => CLKB, RSTB => RSTB, ENB => ENB, REGCEB => REGCEB, WEB => WEB, ADDRB => ADDRB, DINB => DINB, DOUTB => DOUTB, INJECTSBITERR => injectsbiterr_in, INJECTDBITERR => injectdbiterr_in, SBITERR => SBITERR, DBITERR => DBITERR, ECCPIPECE => ECCPIPECE, SLEEP => SLEEP, RDADDRECC => RDADDRECC ); END GENERATE native_mem_module; --************************************************************************** -- NATIVE MEMORY MAPPED MODULE INSTANCE --************************************************************************** native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE --************************************************************************** -- NATIVE MEMORY MAPPED PARAMETERS CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A); CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B); CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8); CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8); CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB; CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB; -- Data Width Number of LSB address bits to be discarded -- 1 to 16 1 -- 17 to 32 2 -- 33 to 64 3 -- 65 to 128 4 -- 129 to 256 5 -- 257 to 512 6 -- 513 to 1024 7 -- The following two constants determine this. CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8))); CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8))); CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A; CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B; SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0'); --************************************************************************** BEGIN RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0'); RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i; RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0'); mem_map_module: BLK_MEM_GEN_v8_2_mem_module GENERIC MAP( C_CORENAME => C_CORENAME, C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))), C_XDEVICEFAMILY => C_XDEVICEFAMILY, C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK, C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS, C_MEM_TYPE => C_MEM_TYPE, C_BYTE_SIZE => C_BYTE_SIZE, C_ALGORITHM => C_ALGORITHM, C_PRIM_TYPE => C_PRIM_TYPE, C_LOAD_INIT_FILE => C_LOAD_INIT_FILE, C_INIT_FILE_NAME => C_INIT_FILE_NAME, C_INIT_FILE => C_INIT_FILE, C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA, C_DEFAULT_DATA => C_DEFAULT_DATA, C_RST_TYPE => "SYNC", C_HAS_RSTA => C_HAS_RSTA, C_RST_PRIORITY_A => C_RST_PRIORITY_A, C_RSTRAM_A => C_RSTRAM_A, C_INITA_VAL => C_INITA_VAL, C_HAS_ENA => C_HAS_ENA, C_HAS_REGCEA => C_HAS_REGCEA, C_USE_BYTE_WEA => C_USE_BYTE_WEA, C_WEA_WIDTH => C_WEA_WIDTH, C_WRITE_MODE_A => C_WRITE_MODE_A, C_WRITE_WIDTH_A => C_WRITE_WIDTH_A, C_READ_WIDTH_A => C_READ_WIDTH_A, C_WRITE_DEPTH_A => C_WRITE_DEPTH_A, C_READ_DEPTH_A => C_READ_DEPTH_A, C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL, C_HAS_RSTB => C_HAS_RSTB, C_RST_PRIORITY_B => C_RST_PRIORITY_B, C_RSTRAM_B => C_RSTRAM_B, C_INITB_VAL => C_INITB_VAL, C_HAS_ENB => C_HAS_ENB, C_HAS_REGCEB => C_HAS_REGCEB, C_USE_BYTE_WEB => C_USE_BYTE_WEB, C_WEB_WIDTH => C_WEB_WIDTH, C_WRITE_MODE_B => C_WRITE_MODE_B, C_WRITE_WIDTH_B => C_WRITE_WIDTH_B, C_READ_WIDTH_B => C_READ_WIDTH_B, C_WRITE_DEPTH_B => C_WRITE_DEPTH_B, C_READ_DEPTH_B => C_READ_DEPTH_B, C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL, C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B, C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A, C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B, C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES, C_USE_SOFTECC => C_USE_SOFTECC, C_USE_ECC => C_USE_ECC, C_HAS_INJECTERR => C_HAS_INJECTERR, C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK, C_COMMON_CLK => C_COMMON_CLK, FLOP_DELAY => FLOP_DELAY, C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL, C_EN_ECC_PIPE => C_EN_ECC_PIPE, C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE ) PORT MAP( CLKA => CLKA, RSTA => rsta_in, ENA => ena_in, REGCEA => regcea_in, WEA => wea_in, ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB), DINA => dina_in, DOUTA => DOUTA, CLKB => CLKB, RSTB => RSTB, ENB => ENB, REGCEB => REGCEB, WEB => WEB, ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB), DINB => DINB, DOUTB => DOUTB, INJECTSBITERR => injectsbiterr_in, INJECTDBITERR => injectdbiterr_in, SBITERR => SBITERR, DBITERR => DBITERR, ECCPIPECE => ECCPIPECE, SLEEP => SLEEP, RDADDRECC => rdaddrecc_i ); END GENERATE native_mem_map_module; --**************************************************************************** -- AXI MEMORY MODULE INSTANCE --**************************************************************************** axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL s_axi_rlast_c : STD_LOGIC := '0'; SIGNAL s_axi_rvalid_c : STD_LOGIC := '0'; SIGNAL s_axi_rready_c : STD_LOGIC := '0'; SIGNAL regceb_c : STD_LOGIC := '0'; BEGIN s_aresetn_a_c <= NOT S_ARESETN; S_AXI_BRESP <= (OTHERS => '0'); s_axi_rresp_c <= (OTHERS => '0'); no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE S_AXI_RDATA <= s_axi_rdata_c; S_AXI_RLAST <= s_axi_rlast_c; S_AXI_RVALID <= s_axi_rvalid_c; S_AXI_RID <= s_axi_rid_c; S_AXI_RRESP <= s_axi_rresp_c; s_axi_rready_c <= S_AXI_RREADY; END GENERATE no_regs; has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3); SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0'); BEGIN has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE regceb_c <= s_axi_rvalid_c AND s_axi_rready_c; END GENERATE has_regceb; no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE regceb_c <= REGCEB; END GENERATE no_regceb; only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c; S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH); S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B); S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1); S_AXI_RLAST <= m_axi_payload_c(0); END GENERATE only_core_op_regs; only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c; S_AXI_RDATA <= s_axi_rdata_c; S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH); S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1); S_AXI_RLAST <= m_axi_payload_c(0); END GENERATE only_emb_op_regs; axi_regs_inst : blk_mem_axi_regs_fwd_v8_2 GENERIC MAP( C_DATA_WIDTH => C_AXI_PAYLOAD ) PORT MAP ( ACLK => S_ACLK, ARESET => s_aresetn_a_c, S_VALID => s_axi_rvalid_c, S_READY => s_axi_rready_c, S_PAYLOAD_DATA => s_axi_payload_c, M_VALID => S_AXI_RVALID, M_READY => S_AXI_RREADY, M_PAYLOAD_DATA => m_axi_payload_c ); END GENERATE has_regs_fwd; axi_wr_fsm : blk_mem_axi_write_wrapper_beh GENERIC MAP( -- AXI Interface related parameters start here C_INTERFACE_TYPE => C_INTERFACE_TYPE, C_AXI_TYPE => C_AXI_TYPE, C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE, C_MEMORY_TYPE => C_MEM_TYPE, C_WRITE_DEPTH_A => C_WRITE_DEPTH_A, C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), C_HAS_AXI_ID => C_HAS_AXI_ID, C_AXI_ID_WIDTH => C_AXI_ID_WIDTH, C_ADDRA_WIDTH => C_ADDRA_WIDTH, C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A, C_AXI_OS_WR => C_AXI_OS_WR ) PORT MAP( -- AXI Global Signals S_ACLK => S_ACLK, S_ARESETN => s_aresetn_a_c, -- AXI Full/Lite Slave Write Interface S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB), S_AXI_AWLEN => S_AXI_AWLEN, S_AXI_AWID => S_AXI_AWID, S_AXI_AWSIZE => S_AXI_AWSIZE, S_AXI_AWBURST => S_AXI_AWBURST, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_AWREADY => S_AXI_AWREADY, S_AXI_WVALID => S_AXI_WVALID, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BVALID => S_AXI_BVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_BID => S_AXI_BID, -- Signals for BRAM interface S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c, S_AXI_WR_EN =>s_axi_wr_en_c ); mem_module: BLK_MEM_GEN_v8_2_mem_module GENERIC MAP( C_CORENAME => C_CORENAME, C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))), C_XDEVICEFAMILY => C_XDEVICEFAMILY, C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK, C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS, C_MEM_TYPE => C_MEM_TYPE, C_BYTE_SIZE => C_BYTE_SIZE, C_ALGORITHM => C_ALGORITHM, C_PRIM_TYPE => C_PRIM_TYPE, C_LOAD_INIT_FILE => C_LOAD_INIT_FILE, C_INIT_FILE_NAME => C_INIT_FILE_NAME, C_INIT_FILE => C_INIT_FILE, C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA, C_DEFAULT_DATA => C_DEFAULT_DATA, C_RST_TYPE => "SYNC", C_HAS_RSTA => C_HAS_RSTA, C_RST_PRIORITY_A => C_RST_PRIORITY_A, C_RSTRAM_A => C_RSTRAM_A, C_INITA_VAL => C_INITA_VAL, C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA, C_HAS_REGCEA => C_HAS_REGCEA, C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1, C_WEA_WIDTH => C_WEA_WIDTH, C_WRITE_MODE_A => C_WRITE_MODE_A, C_WRITE_WIDTH_A => C_WRITE_WIDTH_A, C_READ_WIDTH_A => C_READ_WIDTH_A, C_WRITE_DEPTH_A => C_WRITE_DEPTH_A, C_READ_DEPTH_A => C_READ_DEPTH_A, C_ADDRA_WIDTH => C_ADDRA_WIDTH, C_HAS_RSTB => C_HAS_RSTB, C_RST_PRIORITY_B => C_RST_PRIORITY_B, C_RSTRAM_B => C_RSTRAM_B, C_INITB_VAL => C_INITB_VAL, C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB, C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B, C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1, C_WEB_WIDTH => C_WEB_WIDTH, C_WRITE_MODE_B => C_WRITE_MODE_B, C_WRITE_WIDTH_B => C_WRITE_WIDTH_B, C_READ_WIDTH_B => C_READ_WIDTH_B, C_WRITE_DEPTH_B => C_WRITE_DEPTH_B, C_READ_DEPTH_B => C_READ_DEPTH_B, C_ADDRB_WIDTH => C_ADDRB_WIDTH, C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_A => 0, C_HAS_MUX_OUTPUT_REGS_B => 0, C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A, C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B, C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES, C_USE_SOFTECC => C_USE_SOFTECC, C_USE_ECC => C_USE_ECC, C_HAS_INJECTERR => C_HAS_INJECTERR, C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK, C_COMMON_CLK => C_COMMON_CLK, FLOP_DELAY => FLOP_DELAY, C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL, C_EN_ECC_PIPE => 0, C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE ) PORT MAP( --Port A: CLKA => S_AClk, RSTA => s_aresetn_a_c, ENA => s_axi_wr_en_c, REGCEA => regcea_in, WEA => S_AXI_WSTRB, ADDRA => s_axi_awaddr_out_c, DINA => S_AXI_WDATA, DOUTA => DOUTA, --Port B: CLKB => S_AClk, RSTB => s_aresetn_a_c, ENB => s_axi_rd_en_c, REGCEB => regceb_c, WEB => (OTHERS => '0'), ADDRB => s_axi_araddr_out_c, DINB => DINB, DOUTB => s_axi_rdata_c, INJECTSBITERR => injectsbiterr_in, INJECTDBITERR => injectdbiterr_in, SBITERR => SBITERR, DBITERR => DBITERR, ECCPIPECE => '0', SLEEP => '0', RDADDRECC => RDADDRECC ); axi_rd_sm : blk_mem_axi_read_wrapper_beh GENERIC MAP ( -- AXI Interface related parameters start here C_INTERFACE_TYPE => C_INTERFACE_TYPE, C_AXI_TYPE => C_AXI_TYPE, C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE, C_MEMORY_TYPE => C_MEM_TYPE, C_WRITE_WIDTH_A => C_WRITE_WIDTH_A, C_ADDRA_WIDTH => C_ADDRA_WIDTH, C_AXI_PIPELINE_STAGES => 1, C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), C_HAS_AXI_ID => C_HAS_AXI_ID, C_AXI_ID_WIDTH => C_AXI_ID_WIDTH, C_ADDRB_WIDTH => C_ADDRB_WIDTH ) PORT MAP( -- AXI Global Signals S_ACLK => S_AClk, S_ARESETN => s_aresetn_a_c, -- AXI Full/Lite Read Side S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB), S_AXI_ARLEN => S_AXI_ARLEN, S_AXI_ARSIZE => S_AXI_ARSIZE, S_AXI_ARBURST => S_AXI_ARBURST, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RLAST => s_axi_rlast_c, S_AXI_RVALID => s_axi_rvalid_c, S_AXI_RREADY => s_axi_rready_c, S_AXI_ARID => S_AXI_ARID, S_AXI_RID => s_axi_rid_c, -- AXI Full/Lite Read FSM Outputs S_AXI_ARADDR_OUT => s_axi_araddr_out_c, S_AXI_RD_EN => s_axi_rd_en_c ); END GENERATE axi_mem_module; END behavioral; library IEEE; use IEEE.STD_LOGIC_1164.all; entity beh_ff_clr is generic( INIT : std_logic := '0' ); port( Q : out std_logic; C : in std_logic; CLR : in std_logic; D : in std_logic ); end beh_ff_clr; architecture beh_ff_clr_arch of beh_ff_clr is signal q_o : std_logic := INIT; begin Q <= q_o; VITALBehavior : process(CLR, C) begin if (CLR = '1') then q_o <= '0'; elsif (rising_edge(C)) then q_o <= D after 100 ps; end if; end process; end beh_ff_clr_arch; library IEEE; use IEEE.STD_LOGIC_1164.all; entity beh_ff_ce is generic( INIT : std_logic := '0' ); port( Q : out std_logic; C : in std_logic; CE : in std_logic; CLR : in std_logic; D : in std_logic ); end beh_ff_ce; architecture beh_ff_ce_arch of beh_ff_ce is signal q_o : std_logic := INIT; begin Q <= q_o; VITALBehavior : process(C, CLR) begin if (CLR = '1') then q_o <= '0'; elsif (rising_edge(C)) then if (CE = '1') then q_o <= D after 100 ps; end if; end if; end process; end beh_ff_ce_arch; library IEEE; use IEEE.STD_LOGIC_1164.all; entity beh_ff_pre is generic( INIT : std_logic := '1' ); port( Q : out std_logic; C : in std_logic; D : in std_logic; PRE : in std_logic ); end beh_ff_pre; architecture beh_ff_pre_arch of beh_ff_pre is signal q_o : std_logic := INIT; begin Q <= q_o; VITALBehavior : process(C, PRE) begin if (PRE = '1') then q_o <= '1'; elsif (C' event and C = '1') then q_o <= D after 100 ps; end if; end process; end beh_ff_pre_arch; library IEEE; use IEEE.STD_LOGIC_1164.all; entity beh_muxf7 is port( O : out std_ulogic; I0 : in std_ulogic; I1 : in std_ulogic; S : in std_ulogic ); end beh_muxf7; architecture beh_muxf7_arch of beh_muxf7 is begin VITALBehavior : process (I0, I1, S) begin if (S = '0') then O <= I0; else O <= I1; end if; end process; end beh_muxf7_arch; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity STATE_LOGIC is generic( INIT : std_logic_vector(63 downto 0) := X"0000000000000000" ); port( O : out std_logic := '0'; I0 : in std_logic := '0'; I1 : in std_logic := '0'; I2 : in std_logic := '0'; I3 : in std_logic := '0'; I4 : in std_logic := '0'; I5 : in std_logic := '0' ); end STATE_LOGIC; architecture STATE_LOGIC_arch of STATE_LOGIC is constant INIT_reg : std_logic_vector(63 downto 0) := INIT; begin LUT_beh:process (I0, I1, I2, I3, I4, I5) variable I_reg : std_logic_vector(5 downto 0); begin I_reg := I5 & I4 & I3 & I2 & I1 & I0; O <= INIT_reg(conv_integer(I_reg)); end process; end STATE_LOGIC_arch;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity testbench is end testbench; architecture behv of testbench is component ledc8x8 is port ( SMCLK, RESET: in std_logic; ROW, LED: out std_logic_vector(0 to 7) ); end component; signal smclk: std_logic := '0'; signal reset: std_logic; signal row, led: std_logic_vector(0 to 7); constant period: time := 135.6 ns; -- odvozeno od f(SMCLK) = 7.3728 MHz begin uut: ledc8x8 port map(smclk, reset, row, led); smclk <= not smclk after period / 2; test: process begin reset <= '1'; wait until smclk'event and smclk = '1'; reset <= '0'; wait; end process; end behv;
-- CDR with SERDES library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; entity cdr_serdes is port ( -- clocks clk160 : in std_logic; clk640 : in std_logic; -- reset reset : in std_logic; -- data input din : in std_logic; -- data output data_value : out std_logic_vector(1 downto 0); data_valid : out std_logic_vector(1 downto 0); data_lock : out std_logic ); end cdr_serdes; architecture rtl of cdr_serdes is signal AZ : std_logic_vector(4 downto 0) := (others => '0'); signal BZ : std_logic_vector(4 downto 0) := (others => '0'); signal CZ : std_logic_vector(4 downto 0) := (others => '0'); signal DZ : std_logic_vector(4 downto 0) := (others => '0'); signal AAP, AAN : std_logic := '0'; signal BBP, BBN : std_logic := '0'; signal CCP, CCN : std_logic := '0'; signal DDP, DDN : std_logic := '0'; signal use_A : std_logic := '0'; signal use_B : std_logic := '0'; signal use_C : std_logic := '0'; signal use_D : std_logic := '0'; signal use_A1, use_A2 : std_logic := '0'; signal use_B1, use_B2 : std_logic := '0'; signal use_C1, use_C2 : std_logic := '0'; signal use_D1, use_D2 : std_logic := '0'; signal use_A_reg : std_logic := '0'; signal use_B_reg : std_logic := '0'; signal use_C_reg : std_logic := '0'; signal use_D_reg : std_logic := '0'; signal use_A_reg2 : std_logic := '0'; signal use_B_reg2 : std_logic := '0'; signal use_C_reg2 : std_logic := '0'; signal use_D_reg2 : std_logic := '0'; signal sdata_A : std_logic_vector(1 downto 0) := "00"; signal sdata_B : std_logic_vector(1 downto 0) := "00"; signal sdata_C : std_logic_vector(1 downto 0) := "00"; signal sdata_D : std_logic_vector(1 downto 0) := "00"; signal pipe_ce0 : std_logic := '0'; signal pipe_ce1 : std_logic := '0'; signal valid_int : std_logic_vector(1 downto 0) := "00"; signal lockcnt : integer range 0 to 31 := 0; begin serdes: ISERDES2 generic map ( BITSLIP_ENABLE => FALSE, -- Enable Bitslip Functionality (TRUE/FALSE) DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR") DATA_WIDTH => 4, -- Parallel data width selection (2-8) INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE" ) port map ( CFB0 => open, -- 1-bit output: Clock feed-through route output CFB1 => open, -- 1-bit output: Clock feed-through route output DFB => open, -- 1-bit output: Feed-through clock output FABRICOUT => open, -- 1-bit output: Unsynchrnonized data output INCDEC => open, -- 1-bit output: Phase detector output -- Q1 - Q4: 1-bit (each) output: Registered outputs to FPGA logic Q1 => AZ(0), Q2 => BZ(0), Q3 => CZ(0), Q4 => DZ(0), SHIFTOUT => open, -- 1-bit output: Cascade output signal for master/slave I/O VALID => open, -- 1-bit output: Output status of the phase detector BITSLIP => '0', -- 1-bit input: Bitslip enable input CE0 => '1', -- 1-bit input: Clock enable input CLK0 => clk640, -- 1-bit input: I/O clock network input CLK1 => '0', -- 1-bit input: Secondary I/O clock network input CLKDIV => clk160, -- 1-bit input: FPGA logic domain clock input D => din, -- 1-bit input: Input data IOCE => '1', -- 1-bit input: Data strobe input RST => reset, -- 1-bit input: Asynchronous reset input SHIFTIN => '0' -- 1-bit input: Cascade input signal for master/slave I/O ); process begin wait until rising_edge(clk160); if reset = '1' then AZ(4 downto 1) <= (others => '0'); BZ(4 downto 1) <= (others => '0'); CZ(4 downto 1) <= (others => '0'); DZ(4 downto 1) <= (others => '0'); AAP <= '0'; AAN <= '0'; BBP <= '0'; BBN <= '0'; CCP <= '0'; CCN <= '0'; DDP <= '0'; DDN <= '0'; use_A1 <= '0'; use_A2 <= '0'; use_A <= '0'; use_B1 <= '0'; use_B2 <= '0'; use_B <= '0'; use_C1 <= '0'; use_C2 <= '0'; use_C <= '0'; use_D1 <= '0'; use_D2 <= '0'; use_D <= '0'; use_A_reg <= '0'; use_A_reg2 <= '0'; use_B_reg <= '0'; use_B_reg2 <= '0'; use_C_reg <= '0'; use_C_reg2 <= '0'; use_D_reg <= '0'; use_D_reg2 <= '0'; sdata_A <= "00"; sdata_B <= "00"; sdata_C <= "00"; sdata_D <= "00"; valid_int <= "00"; data_value <= "00"; data_valid <= "00"; data_lock <= '0'; lockcnt <= 0; pipe_ce0 <= '0'; pipe_ce1 <= '0'; else -- clock in the data AZ(4 downto 1) <= AZ(3 downto 0); BZ(4 downto 1) <= BZ(3 downto 0); CZ(4 downto 1) <= CZ(3 downto 0); DZ(4 downto 1) <= DZ(3 downto 0); -- find positive edges AAP <= (AZ(2) xor AZ(3)) and not AZ(2); BBP <= (BZ(2) xor BZ(3)) and not BZ(2); CCP <= (CZ(2) xor CZ(3)) and not CZ(2); DDP <= (DZ(2) xor DZ(3)) and not DZ(2); -- find negative edges AAN <= (AZ(2) xor AZ(3)) and AZ(2); BBN <= (BZ(2) xor BZ(3)) and BZ(2); CCN <= (CZ(2) xor CZ(3)) and CZ(2); DDN <= (DZ(2) xor DZ(3)) and DZ(2); -- decision of sampling point use_A1 <= (BBP and not CCP and not DDP and AAP); use_A2 <= (BBN and not CCN and not DDN and AAN); use_B1 <= (CCP and not DDP and AAP and BBP); use_B2 <= (CCN and not DDN and AAN and BBN); use_C1 <= (DDP and AAP and BBP and CCP); use_C2 <= (DDN and AAN and BBN and CCN); use_D1 <= (AAP and not BBP and not CCP and not DDP); use_D2 <= (AAN and not BBN and not CCN and not DDN); use_A <= use_A1 or use_A2; use_B <= use_B1 or use_B2; use_C <= use_C1 or use_C2; use_D <= use_D1 or use_D2; -- if we found an edge if (use_A or use_B or use_C or use_D) = '1' then lockcnt <= 31; pipe_ce0 <= '1'; -- sync marker pipe_ce1 <= '1'; else if lockcnt = 0 then pipe_ce0 <= '0'; else lockcnt <= lockcnt - 1; end if; pipe_ce1 <= '0'; end if; -- register use_A_reg <= use_A; use_B_reg <= use_B; use_C_reg <= use_C; use_D_reg <= use_D; if pipe_ce1 = '1' then use_A_reg2 <= use_A_reg; use_B_reg2 <= use_B_reg; use_C_reg2 <= use_C_reg; use_D_reg2 <= use_D_reg; end if; -- collect output data sdata_A(0) <= AZ(4) and use_A_reg2; sdata_A(1) <= AZ(4) and use_D_reg2; sdata_B(0) <= BZ(4) and use_B_reg2; sdata_B(1) <= '0'; sdata_C(0) <= CZ(4) and use_C_reg2; sdata_C(1) <= '0'; sdata_D(0) <= DZ(4) and use_D_reg2; sdata_D(1) <= DZ(4) and use_A_reg2; -- ouput data if we have seen an edge if pipe_ce0 = '1' then data_value <= sdata_A or sdata_B or sdata_C or sdata_D; end if; -- data valid output if use_D_reg2 = '1' and use_A_reg = '1' then valid_int <= "00"; -- move from A to D: no valid data elsif use_A_reg2 = '1' and use_D_reg = '1' then valid_int <= "11"; -- move from D to A: 2 bits valid else valid_int <= "01"; -- only one bit is valid end if; if pipe_ce0 = '1' then data_valid <= valid_int; else data_valid <= "00"; end if; data_lock <= pipe_ce0; end if; end process; end architecture;
-- CDR with SERDES library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; entity cdr_serdes is port ( -- clocks clk160 : in std_logic; clk640 : in std_logic; -- reset reset : in std_logic; -- data input din : in std_logic; -- data output data_value : out std_logic_vector(1 downto 0); data_valid : out std_logic_vector(1 downto 0); data_lock : out std_logic ); end cdr_serdes; architecture rtl of cdr_serdes is signal AZ : std_logic_vector(4 downto 0) := (others => '0'); signal BZ : std_logic_vector(4 downto 0) := (others => '0'); signal CZ : std_logic_vector(4 downto 0) := (others => '0'); signal DZ : std_logic_vector(4 downto 0) := (others => '0'); signal AAP, AAN : std_logic := '0'; signal BBP, BBN : std_logic := '0'; signal CCP, CCN : std_logic := '0'; signal DDP, DDN : std_logic := '0'; signal use_A : std_logic := '0'; signal use_B : std_logic := '0'; signal use_C : std_logic := '0'; signal use_D : std_logic := '0'; signal use_A1, use_A2 : std_logic := '0'; signal use_B1, use_B2 : std_logic := '0'; signal use_C1, use_C2 : std_logic := '0'; signal use_D1, use_D2 : std_logic := '0'; signal use_A_reg : std_logic := '0'; signal use_B_reg : std_logic := '0'; signal use_C_reg : std_logic := '0'; signal use_D_reg : std_logic := '0'; signal use_A_reg2 : std_logic := '0'; signal use_B_reg2 : std_logic := '0'; signal use_C_reg2 : std_logic := '0'; signal use_D_reg2 : std_logic := '0'; signal sdata_A : std_logic_vector(1 downto 0) := "00"; signal sdata_B : std_logic_vector(1 downto 0) := "00"; signal sdata_C : std_logic_vector(1 downto 0) := "00"; signal sdata_D : std_logic_vector(1 downto 0) := "00"; signal pipe_ce0 : std_logic := '0'; signal pipe_ce1 : std_logic := '0'; signal valid_int : std_logic_vector(1 downto 0) := "00"; signal lockcnt : integer range 0 to 31 := 0; begin serdes: ISERDES2 generic map ( BITSLIP_ENABLE => FALSE, -- Enable Bitslip Functionality (TRUE/FALSE) DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR") DATA_WIDTH => 4, -- Parallel data width selection (2-8) INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE" ) port map ( CFB0 => open, -- 1-bit output: Clock feed-through route output CFB1 => open, -- 1-bit output: Clock feed-through route output DFB => open, -- 1-bit output: Feed-through clock output FABRICOUT => open, -- 1-bit output: Unsynchrnonized data output INCDEC => open, -- 1-bit output: Phase detector output -- Q1 - Q4: 1-bit (each) output: Registered outputs to FPGA logic Q1 => AZ(0), Q2 => BZ(0), Q3 => CZ(0), Q4 => DZ(0), SHIFTOUT => open, -- 1-bit output: Cascade output signal for master/slave I/O VALID => open, -- 1-bit output: Output status of the phase detector BITSLIP => '0', -- 1-bit input: Bitslip enable input CE0 => '1', -- 1-bit input: Clock enable input CLK0 => clk640, -- 1-bit input: I/O clock network input CLK1 => '0', -- 1-bit input: Secondary I/O clock network input CLKDIV => clk160, -- 1-bit input: FPGA logic domain clock input D => din, -- 1-bit input: Input data IOCE => '1', -- 1-bit input: Data strobe input RST => reset, -- 1-bit input: Asynchronous reset input SHIFTIN => '0' -- 1-bit input: Cascade input signal for master/slave I/O ); process begin wait until rising_edge(clk160); if reset = '1' then AZ(4 downto 1) <= (others => '0'); BZ(4 downto 1) <= (others => '0'); CZ(4 downto 1) <= (others => '0'); DZ(4 downto 1) <= (others => '0'); AAP <= '0'; AAN <= '0'; BBP <= '0'; BBN <= '0'; CCP <= '0'; CCN <= '0'; DDP <= '0'; DDN <= '0'; use_A1 <= '0'; use_A2 <= '0'; use_A <= '0'; use_B1 <= '0'; use_B2 <= '0'; use_B <= '0'; use_C1 <= '0'; use_C2 <= '0'; use_C <= '0'; use_D1 <= '0'; use_D2 <= '0'; use_D <= '0'; use_A_reg <= '0'; use_A_reg2 <= '0'; use_B_reg <= '0'; use_B_reg2 <= '0'; use_C_reg <= '0'; use_C_reg2 <= '0'; use_D_reg <= '0'; use_D_reg2 <= '0'; sdata_A <= "00"; sdata_B <= "00"; sdata_C <= "00"; sdata_D <= "00"; valid_int <= "00"; data_value <= "00"; data_valid <= "00"; data_lock <= '0'; lockcnt <= 0; pipe_ce0 <= '0'; pipe_ce1 <= '0'; else -- clock in the data AZ(4 downto 1) <= AZ(3 downto 0); BZ(4 downto 1) <= BZ(3 downto 0); CZ(4 downto 1) <= CZ(3 downto 0); DZ(4 downto 1) <= DZ(3 downto 0); -- find positive edges AAP <= (AZ(2) xor AZ(3)) and not AZ(2); BBP <= (BZ(2) xor BZ(3)) and not BZ(2); CCP <= (CZ(2) xor CZ(3)) and not CZ(2); DDP <= (DZ(2) xor DZ(3)) and not DZ(2); -- find negative edges AAN <= (AZ(2) xor AZ(3)) and AZ(2); BBN <= (BZ(2) xor BZ(3)) and BZ(2); CCN <= (CZ(2) xor CZ(3)) and CZ(2); DDN <= (DZ(2) xor DZ(3)) and DZ(2); -- decision of sampling point use_A1 <= (BBP and not CCP and not DDP and AAP); use_A2 <= (BBN and not CCN and not DDN and AAN); use_B1 <= (CCP and not DDP and AAP and BBP); use_B2 <= (CCN and not DDN and AAN and BBN); use_C1 <= (DDP and AAP and BBP and CCP); use_C2 <= (DDN and AAN and BBN and CCN); use_D1 <= (AAP and not BBP and not CCP and not DDP); use_D2 <= (AAN and not BBN and not CCN and not DDN); use_A <= use_A1 or use_A2; use_B <= use_B1 or use_B2; use_C <= use_C1 or use_C2; use_D <= use_D1 or use_D2; -- if we found an edge if (use_A or use_B or use_C or use_D) = '1' then lockcnt <= 31; pipe_ce0 <= '1'; -- sync marker pipe_ce1 <= '1'; else if lockcnt = 0 then pipe_ce0 <= '0'; else lockcnt <= lockcnt - 1; end if; pipe_ce1 <= '0'; end if; -- register use_A_reg <= use_A; use_B_reg <= use_B; use_C_reg <= use_C; use_D_reg <= use_D; if pipe_ce1 = '1' then use_A_reg2 <= use_A_reg; use_B_reg2 <= use_B_reg; use_C_reg2 <= use_C_reg; use_D_reg2 <= use_D_reg; end if; -- collect output data sdata_A(0) <= AZ(4) and use_A_reg2; sdata_A(1) <= AZ(4) and use_D_reg2; sdata_B(0) <= BZ(4) and use_B_reg2; sdata_B(1) <= '0'; sdata_C(0) <= CZ(4) and use_C_reg2; sdata_C(1) <= '0'; sdata_D(0) <= DZ(4) and use_D_reg2; sdata_D(1) <= DZ(4) and use_A_reg2; -- ouput data if we have seen an edge if pipe_ce0 = '1' then data_value <= sdata_A or sdata_B or sdata_C or sdata_D; end if; -- data valid output if use_D_reg2 = '1' and use_A_reg = '1' then valid_int <= "00"; -- move from A to D: no valid data elsif use_A_reg2 = '1' and use_D_reg = '1' then valid_int <= "11"; -- move from D to A: 2 bits valid else valid_int <= "01"; -- only one bit is valid end if; if pipe_ce0 = '1' then data_valid <= valid_int; else data_valid <= "00"; end if; data_lock <= pipe_ce0; end if; end process; end architecture;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_17_fg_17_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity fg_17_05 is end entity fg_17_05; ---------------------------------------------------------------- architecture test of fg_17_05 is signal s : bit_vector(0 to 3); begin process is type value_cell; type value_ptr is access value_cell; type value_cell is record value : bit_vector(0 to 3); next_cell : value_ptr; end record value_cell; variable value_list, current_cell : value_ptr; begin value_list := new value_cell'( B"1000", value_list ); value_list := new value_cell'( B"0010", value_list ); value_list := new value_cell'( B"0000", value_list ); -- code from book: current_cell := value_list; while current_cell /= null loop s <= current_cell.value; wait for 10 ns; current_cell := current_cell.next_cell; end loop; -- end of code from book wait; end process; end architecture test;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_17_fg_17_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity fg_17_05 is end entity fg_17_05; ---------------------------------------------------------------- architecture test of fg_17_05 is signal s : bit_vector(0 to 3); begin process is type value_cell; type value_ptr is access value_cell; type value_cell is record value : bit_vector(0 to 3); next_cell : value_ptr; end record value_cell; variable value_list, current_cell : value_ptr; begin value_list := new value_cell'( B"1000", value_list ); value_list := new value_cell'( B"0010", value_list ); value_list := new value_cell'( B"0000", value_list ); -- code from book: current_cell := value_list; while current_cell /= null loop s <= current_cell.value; wait for 10 ns; current_cell := current_cell.next_cell; end loop; -- end of code from book wait; end process; end architecture test;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_17_fg_17_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity fg_17_05 is end entity fg_17_05; ---------------------------------------------------------------- architecture test of fg_17_05 is signal s : bit_vector(0 to 3); begin process is type value_cell; type value_ptr is access value_cell; type value_cell is record value : bit_vector(0 to 3); next_cell : value_ptr; end record value_cell; variable value_list, current_cell : value_ptr; begin value_list := new value_cell'( B"1000", value_list ); value_list := new value_cell'( B"0010", value_list ); value_list := new value_cell'( B"0000", value_list ); -- code from book: current_cell := value_list; while current_cell /= null loop s <= current_cell.value; wait for 10 ns; current_cell := current_cell.next_cell; end loop; -- end of code from book wait; end process; end architecture test;
-- -*- vhdl -*- ------------------------------------------------------------------------------- -- Copyright (c) 2012, The CARPE Project, All rights reserved. -- -- See the AUTHORS file for individual contributors. -- -- -- -- Copyright and related rights are licensed under the Solderpad -- -- Hardware License, Version 0.51 (the "License"); you may not use this -- -- file except in compliance with the License. You may obtain a copy of -- -- the License at http://solderpad.org/licenses/SHL-0.51. -- -- -- -- Unless required by applicable law or agreed to in writing, software, -- -- hardware and materials distributed under this License is distributed -- -- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -- -- either express or implied. See the License for the specific language -- -- governing permissions and limitations under the License. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity addsub is generic ( src_bits : natural := 32 ); port ( sub : in std_ulogic; carryin : in std_ulogic; src1 : in std_ulogic_vector(src_bits-1 downto 0); src2 : in std_ulogic_vector(src_bits-1 downto 0); result : out std_ulogic_vector(src_bits-1 downto 0); carryout : out std_ulogic; overflow : out std_ulogic ); end;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sparcv8_v4 is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; alurs : out STD_LOGIC_VECTOR (31 downto 0) ); end sparcv8_v4; architecture Behavioral of sparcv8_v4 is component ADD Port ( add : in STD_LOGIC_VECTOR (31 downto 0); input : in STD_LOGIC_VECTOR (31 downto 0); output : out STD_LOGIC_VECTOR (31 downto 0) ); end component; component ALU Port ( ope1 : in STD_LOGIC_VECTOR (31 downto 0); ope2 : in STD_LOGIC_VECTOR (31 downto 0); aluop : in STD_LOGIC_VECTOR (5 downto 0); C : in STD_LOGIC; alurs : out STD_LOGIC_VECTOR (31 downto 0) ); end component; component CU Port ( --clk : in STD_LOGIC; op : in STD_LOGIC_VECTOR (1 downto 0); op3 : in STD_LOGIC_VECTOR (5 downto 0); aluop : out STD_LOGIC_VECTOR (5 downto 0) ); end component; component IM Port ( --clk : in STD_LOGIC; reset : in STD_LOGIC; address : in STD_LOGIC_VECTOR (31 downto 0); inst_out : out STD_LOGIC_VECTOR (31 downto 0) ); end component; component MUX Port ( crs2 : in STD_LOGIC_VECTOR (31 downto 0); immSE : in STD_LOGIC_VECTOR (31 downto 0); i : in STD_LOGIC; ope2 : out STD_LOGIC_VECTOR (31 downto 0) ); end component; component PC Port ( CLK : in STD_LOGIC; RESET : in STD_LOGIC; PC_IN : in STD_LOGIC_VECTOR(31 DOWNTO 0); PC_OUT : out STD_LOGIC_VECTOR(31 DOWNTO 0) ); end component; component RF Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; rs1 : in STD_LOGIC_VECTOR (5 downto 0); rs2 : in STD_LOGIC_VECTOR (5 downto 0); rd : in STD_LOGIC_VECTOR (5 downto 0); we : in STD_LOGIC; dwr : in STD_LOGIC_VECTOR (31 downto 0); crs1 : out STD_LOGIC_VECTOR (31 downto 0); crs2 : out STD_LOGIC_VECTOR (31 downto 0) ); end component; component SEU Port ( imm13 : in STD_LOGIC_VECTOR (12 downto 0); sign_ext : out STD_LOGIC_VECTOR (31 downto 0) ); end component; component WM Port ( op : in STD_LOGIC_VECTOR (1 downto 0); op3 : in STD_LOGIC_VECTOR (5 downto 0); cwp : in STD_LOGIC_VECTOR (1 downto 0); rs1 : in STD_LOGIC_VECTOR (4 downto 0); rs2 : in STD_LOGIC_VECTOR (4 downto 0); rd : in STD_LOGIC_VECTOR (4 downto 0); ncwp : out STD_LOGIC_VECTOR (1 downto 0); nrs1 : out STD_LOGIC_VECTOR (5 downto 0); nrs2 : out STD_LOGIC_VECTOR (5 downto 0); nrd : out STD_LOGIC_VECTOR (5 downto 0) ); end component; component PSR Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; nzvc : in STD_LOGIC_VECTOR (3 downto 0); ncwp : in STD_LOGIC_VECTOR (1 downto 0); cwp : out STD_LOGIC_VECTOR (1 downto 0); carry : out STD_LOGIC ); end component; component PSR_MOD Port ( alurs : in STD_LOGIC_VECTOR (31 downto 0); ope1 : in STD_LOGIC; ope2 : in STD_LOGIC; aluop : in STD_LOGIC_VECTOR (5 downto 0); nzvc : out std_logic_vector(3 downto 0) ); end component; --internal out signals ADD, nPC and PC signal addi : std_logic_vector(31 downto 0); signal npci : std_logic_vector(31 downto 0); signal pci : std_logic_vector(31 downto 0); --internal out signal CU signal aluop : std_logic_vector(5 downto 0); --internal out signals RF signal crs1 : std_logic_vector(31 downto 0); signal crs2 : std_logic_vector(31 downto 0); --internal out signal SEU signal imm31 : std_logic_vector(31 downto 0); --internal out signal MUX signal ope2 : std_logic_vector(31 downto 0); --internal out signal ALU signal alursi : std_logic_vector(31 downto 0); --internal out signal PSR_MOD signal nzvc : std_logic_vector(3 downto 0); --internal out signals PSR signal cwp : STD_LOGIC_VECTOR (1 downto 0); signal carry : STD_LOGIC; --internal out signal IM signal im_o : std_logic_vector(31 downto 0); --instruction format signal op : STD_LOGIC_VECTOR (1 downto 0); signal op3 : STD_LOGIC_VECTOR (5 downto 0); signal rd : STD_LOGIC_VECTOR (4 downto 0); signal rs1 : STD_LOGIC_VECTOR (4 downto 0); signal i : STD_LOGIC; signal imm13: STD_LOGIC_VECTOR (12 downto 0); signal rs2 : STD_LOGIC_VECTOR (4 downto 0); --internal out signals WM signal ncwp : STD_LOGIC_VECTOR (1 downto 0); signal nrs1 : STD_LOGIC_VECTOR (5 downto 0); signal nrs2 : STD_LOGIC_VECTOR (5 downto 0); signal nrd : STD_LOGIC_VECTOR (5 downto 0); begin add_map : ADD port map( x"00000001", npci, addi ); npc_map : PC port map( clk, reset, addi, npci ); pc_map : PC port map( clk, reset, npci, pci ); im_map : IM port map( reset, pci, im_o ); op <= im_o(31 downto 30); op3 <= im_o(24 downto 19); rd <= im_o(29 downto 25); rs1 <= im_o(18 downto 14); i <= im_o(13); imm13 <= im_o(12 downto 0); rs2 <= im_o(4 downto 0); cu_map : CU port map( op, op3, aluop ); rf_map : RF port map( clk, reset, nrs1, nrs2, nrd, '1', alursi, crs1, crs2 ); seu_map : SEU port map( imm13, imm31 ); mux_map : MUX port map( crs2, imm31, i, ope2 ); wm_map : WM port map( op, op3, cwp, rs1, rs2, rd, ncwp, nrs1, nrs2, nrd ); psr_map : PSR port map( clk, reset, nzvc, ncwp, cwp, carry ); psrmod_map : PSR_MOD port map( alursi, crs1(31), ope2(31), aluop, nzvc ); alu_map : ALU port map( crs1, ope2, aluop, carry, alursi ); alurs <= alursi; end Behavioral;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:user:affine_rotation_generator:1.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY system_affine_rotation_generator_0_0 IS PORT ( clk_25 : IN STD_LOGIC; reset : IN STD_LOGIC; a00 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); a01 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); a10 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); a11 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END system_affine_rotation_generator_0_0; ARCHITECTURE system_affine_rotation_generator_0_0_arch OF system_affine_rotation_generator_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_affine_rotation_generator_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT affine_rotation_generator IS PORT ( clk_25 : IN STD_LOGIC; reset : IN STD_LOGIC; a00 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); a01 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); a10 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); a11 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT affine_rotation_generator; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST"; BEGIN U0 : affine_rotation_generator PORT MAP ( clk_25 => clk_25, reset => reset, a00 => a00, a01 => a01, a10 => a10, a11 => a11 ); END system_affine_rotation_generator_0_0_arch;
-------------------------------------------------------------------------------- -- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- Description: -- This is an example testbench for the FIR Compiler IP core. -- The testbench has been generated by Vivado to accompany the IP core -- instance you have generated. -- -- This testbench is for demonstration purposes only. See note below for -- instructions on how to use it with your core. -- -- See the FIR Compiler product guide for further information -- about this core. -- -------------------------------------------------------------------------------- -- Using this testbench -- -- This testbench instantiates your generated FIR Compiler core -- instance named "fir_lp_54kHz". -- -- Use Vivado's Run Simulation flow to run this testbench. See the Vivado -- documentation for details. -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity tb_fir_lp_54kHz is end tb_fir_lp_54kHz; architecture tb of tb_fir_lp_54kHz is ----------------------------------------------------------------------- -- Timing constants ----------------------------------------------------------------------- constant CLOCK_PERIOD : time := 100 ns; constant T_HOLD : time := 10 ns; constant T_STROBE : time := CLOCK_PERIOD - (1 ns); ----------------------------------------------------------------------- -- DUT signals ----------------------------------------------------------------------- -- General signals signal aclk : std_logic := '0'; -- the master clock -- Data slave channel signals signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid signal s_axis_data_tready : std_logic := '1'; -- slave is ready signal s_axis_data_tdata : std_logic_vector(31 downto 0) := (others => '0'); -- data payload -- Data master channel signals signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid signal m_axis_data_tdata : std_logic_vector(95 downto 0) := (others => '0'); -- data payload ----------------------------------------------------------------------- -- Aliases for AXI channel TDATA and TUSER fields -- These are a convenience for viewing data in a simulator waveform viewer. -- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command -- to prevent the simulator optimizing away these signals. ----------------------------------------------------------------------- -- Data slave channel alias signals signal s_axis_data_tdata_path0 : std_logic_vector(15 downto 0) := (others => '0'); signal s_axis_data_tdata_path1 : std_logic_vector(15 downto 0) := (others => '0'); -- Data master channel alias signals signal m_axis_data_tdata_path0 : std_logic_vector(44 downto 0) := (others => '0'); signal m_axis_data_tdata_path1 : std_logic_vector(44 downto 0) := (others => '0'); begin ----------------------------------------------------------------------- -- Instantiate the DUT ----------------------------------------------------------------------- dut : entity work.fir_lp_54kHz port map ( aclk => aclk, s_axis_data_tvalid => s_axis_data_tvalid, s_axis_data_tready => s_axis_data_tready, s_axis_data_tdata => s_axis_data_tdata, m_axis_data_tvalid => m_axis_data_tvalid, m_axis_data_tdata => m_axis_data_tdata ); ----------------------------------------------------------------------- -- Generate clock ----------------------------------------------------------------------- clock_gen : process begin aclk <= '0'; wait for CLOCK_PERIOD; loop aclk <= '0'; wait for CLOCK_PERIOD/2; aclk <= '1'; wait for CLOCK_PERIOD/2; end loop; end process clock_gen; ----------------------------------------------------------------------- -- Generate inputs ----------------------------------------------------------------------- stimuli : process -- Procedure to drive a number of input samples with specific data -- data is the data value to drive on the tdata signal -- samples is the number of zero-data input samples to drive procedure drive_data ( data : std_logic_vector(31 downto 0); samples : natural := 1 ) is variable ip_count : integer := 0; begin ip_count := 0; loop s_axis_data_tvalid <= '1'; s_axis_data_tdata <= data; loop wait until rising_edge(aclk); exit when s_axis_data_tready = '1'; end loop; ip_count := ip_count + 1; wait for T_HOLD; exit when ip_count >= samples; end loop; end procedure drive_data; -- Procedure to drive a number of zero-data input samples -- samples is the number of zero-data input samples to drive procedure drive_zeros ( samples : natural := 1 ) is begin drive_data((others => '0'), samples); end procedure drive_zeros; -- Procedure to drive an impulse and let the impulse response emerge on the data master channel -- samples is the number of input samples to drive; default is enough for impulse response output to emerge procedure drive_impulse ( samples : natural := 2131 ) is variable impulse : std_logic_vector(31 downto 0); begin impulse := (others => '0'); -- initialize unused bits to zero impulse(15 downto 0) := "0100000000000000"; drive_data(impulse); if samples > 1 then drive_zeros(samples-1); end if; end procedure drive_impulse; -- Local variables variable data : std_logic_vector(31 downto 0); begin -- Drive inputs T_HOLD time after rising edge of clock wait until rising_edge(aclk); wait for T_HOLD; -- Drive a single impulse and let the impulse response emerge drive_impulse; -- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals drive_impulse(2); -- start of impulse; data is now zero s_axis_data_tvalid <= '0'; wait for CLOCK_PERIOD * 5; -- provide no data for 5 input samples worth drive_zeros(2129); -- back to normal operation -- Drive a set of impulses of different magnitudes on each path -- Path inputs are provided in parallel, in different fields of s_axis_data_tdata data := (others => '0'); -- initialize unused bits to zero data(15 downto 0) := "0100000000000000"; -- path 0: impulse >> 0 data(31 downto 16) := "0010000000000000"; -- path 1: impulse >> 1 drive_data(data); drive_zeros(2130); -- End of test report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure; wait; end process stimuli; ----------------------------------------------------------------------- -- Check outputs ----------------------------------------------------------------------- check_outputs : process variable check_ok : boolean := true; begin -- Check outputs T_STROBE time after rising edge of clock wait until rising_edge(aclk); wait for T_STROBE; -- Do not check the output payload values, as this requires the behavioral model -- which would make this demonstration testbench unwieldy. -- Instead, check the protocol of the master DATA channel: -- check that the payload is valid (not X) when TVALID is high if m_axis_data_tvalid = '1' then if is_x(m_axis_data_tdata) then report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error; check_ok := false; end if; end if; assert check_ok report "ERROR: terminating test with failures." severity failure; end process check_outputs; ----------------------------------------------------------------------- -- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing ----------------------------------------------------------------------- -- Data slave channel alias signals s_axis_data_tdata_path0 <= s_axis_data_tdata(15 downto 0); s_axis_data_tdata_path1 <= s_axis_data_tdata(31 downto 16); -- Data master channel alias signals: update these only when they are valid m_axis_data_tdata_path0 <= m_axis_data_tdata(44 downto 0) when m_axis_data_tvalid = '1'; m_axis_data_tdata_path1 <= m_axis_data_tdata(92 downto 48) when m_axis_data_tvalid = '1'; end tb;
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:floating_point:7.1 -- IP Revision: 2 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_1_2; USE floating_point_v7_1_2.floating_point_v7_1_2; ENTITY doHistStretch_ap_sitofp_4_no_dsp_32 IS PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END doHistStretch_ap_sitofp_4_no_dsp_32; ARCHITECTURE doHistStretch_ap_sitofp_4_no_dsp_32_arch OF doHistStretch_ap_sitofp_4_no_dsp_32 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF doHistStretch_ap_sitofp_4_no_dsp_32_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_1_2 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER; C_FIXED_DATA_UNSIGNED : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_1_2; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_1_2 GENERIC MAP ( C_XDEVICEFAMILY => "virtex7", C_HAS_ADD => 0, C_HAS_SUBTRACT => 0, C_HAS_MULTIPLY => 0, C_HAS_DIVIDE => 0, C_HAS_SQRT => 0, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 1, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 0, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 32, C_A_FRACTION_WIDTH => 0, C_B_WIDTH => 32, C_B_FRACTION_WIDTH => 0, C_C_WIDTH => 32, C_C_FRACTION_WIDTH => 0, C_RESULT_WIDTH => 32, C_RESULT_FRACTION_WIDTH => 24, C_COMPARE_OPERATION => 8, C_LATENCY => 4, C_OPTIMIZATION => 1, C_MULT_USAGE => 0, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 1, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 0, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 0, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 32, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 32, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 32, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 32, C_RESULT_TUSER_WIDTH => 1, C_FIXED_DATA_UNSIGNED => 0 ) PORT MAP ( aclk => aclk, aclken => aclken, aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => '0', s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => '0', s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END doHistStretch_ap_sitofp_4_no_dsp_32_arch;
-------------------------------------------------------------------------- -- -- Copyright (C) 1993, Peter J. Ashenden -- Mail: Dept. Computer Science -- University of Adelaide, SA 5005, Australia -- e-mail: petera@cs.adelaide.edu.au -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 1, or (at your option) -- any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -- -------------------------------------------------------------------------- -- -- $RCSfile: reg_file.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 19:16:43 $ -- -------------------------------------------------------------------------- -- -- Entity declaration for register file. -- use work.dlx_types.all, work.dlx_instr.all; entity reg_file is generic (Tac : Time; tag : string := ""; origin_x, origin_y : real := 0.0); port (a1 : in dlx_reg_addr; q1 : out dlx_word; a2 : in dlx_reg_addr; q2 : out dlx_word; a3 : in dlx_reg_addr; d3 : in dlx_word; write_en : in bit); end reg_file;
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:30:59) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.NUMERIC_STD.all; ENTITY ewf_nsga2_entity IS PORT ( reset, clk: IN std_logic; input1, input2: IN unsigned(0 TO 3); output1, output2, output3, output4, output5: OUT unsigned(0 TO 4)); END ewf_nsga2_entity; ARCHITECTURE ewf_nsga2_description OF ewf_nsga2_entity IS SIGNAL current_state : unsigned(0 TO 7) := "00000000"; SHARED VARIABLE register1: unsigned(0 TO 4) := "00000"; SHARED VARIABLE register2: unsigned(0 TO 4) := "00000"; SHARED VARIABLE register3: unsigned(0 TO 4) := "00000"; SHARED VARIABLE register4: unsigned(0 TO 4) := "00000"; SHARED VARIABLE register5: unsigned(0 TO 4) := "00000"; SHARED VARIABLE register6: unsigned(0 TO 4) := "00000"; BEGIN moore_machine: PROCESS(clk, reset) BEGIN IF reset = '0' THEN current_state <= "00000000"; ELSIF clk = '1' AND clk'event THEN IF current_state < 4 THEN current_state <= current_state + 1; END IF; END IF; END PROCESS moore_machine; operations: PROCESS(current_state) BEGIN CASE current_state IS WHEN "00000001" => register1 := input1 + 1; register2 := input2 + 2; WHEN "00000010" => register3 := register2 + 4; WHEN "00000011" => register4 := register3 + 6; WHEN "00000100" => register4 := register1 + register4; WHEN "00000101" => register5 := register4 * 8; WHEN "00000110" => register5 := register3 + register5; register6 := register4 * 10; WHEN "00000111" => register3 := register3 + register5; WHEN "00001000" => register3 := register3 * 12; register4 := register4 + register5; register6 := register1 + register6; WHEN "00001001" => register1 := register1 + register6; output1 <= register6 + register4; WHEN "00001010" => register1 := register1 * 15; register3 := register2 + register3; WHEN "00001011" => register2 := register2 + register3; WHEN "00001100" => register2 := register2 * 17; WHEN "00001101" => register2 := register2 + 19; WHEN "00001110" => output2 <= register3 + register2; register2 := register5 + register3; WHEN "00001111" => register2 := register2 + 22; WHEN "00010000" => register3 := register2 * 24; WHEN "00010001" => register3 := register3 + 26; WHEN "00010010" => output3 <= register2 + register3; register1 := register1 + 29; WHEN "00010011" => register2 := register1 + 31; WHEN "00010100" => register2 := register2 * 33; WHEN "00010101" => output4 <= register1 + register2; register1 := register6 + register1; WHEN "00010110" => register1 := register1 + 36; WHEN "00010111" => register2 := register1 * 38; WHEN "00011000" => register2 := register2 + 40; WHEN "00011001" => output5 <= register1 + register2; WHEN OTHERS => NULL; END CASE; END PROCESS operations; END ewf_nsga2_description;
---------------------------------------------------------------------------- -- This file is a part of the LEON VHDL model -- Copyright (C) 1999 European Space Agency (ESA) -- -- This library is free software; you can redistribute it and/or -- modify it under the terms of the GNU Lesser General Public -- License as published by the Free Software Foundation; either -- version 2 of the License, or (at your option) any later version. -- -- See the file COPYING.LGPL for the full details of the license. ----------------------------------------------------------------------------- -- Entity: device -- File: device.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: package to select current device configuration ------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use work.target.all; package device is ---------------------------------------------------------------------- -- This is the current device configuration ---------------------------------------------------------------------- constant conf : config_type := fpga_2k2k; -- constant conf : config_type := fpga_2k2k_v8; -- constant conf : config_type := fpga_2k2k_irq2; -- constant conf : config_type := fpga_2k2k_softprom; -- constant conf : config_type := fpga_2k2k_v8_softprom; -- constant conf : config_type := fpga_4k4k_v8_fpu; -- constant conf : config_type := fpga_4k4k_v8_fpu_softprom; -- constant conf : config_type := fpga_2k2k_v8_mac_softprom; -- constant conf : config_type := virtex_2k2k_blockprom; -- constant conf : config_type := virtex_2k1k_rdbmon; -- constant conf : config_type := virtex_2k2k_v8_blockprom; -- constant conf : config_type := gen_atc25; -- constant conf : config_type := gen_atc25_meiko; -- constant conf : config_type := gen_atc25_fpc; -- constant conf : config_type := gen_atc25_insilicon_pci; -- constant conf : config_type := gen_atc35; -- constant conf : config_type := systel_fpga; -- constant conf : config_type := systel_asic; -- constant conf : config_type := gen_fs90; -- constant conf : config_type := gen_umc18; end;
library IEEE; use IEEE.STD_LOGIC_1164.all; entity liaison is port( clk : in STD_LOGIC; reset : in STD_LOGIC; di_ready : in STD_LOGIC; mp_data : in STD_LOGIC_VECTOR(3 downto 0); do_ready : out STD_LOGIC; voted_data : out STD_LOGIC ); end liaison; architecture liaison of liaison is signal voted_data_bit: STD_LOGIC; signal status: STD_LOGIC_VECTOR (2 downto 0); signal control_signals: STD_LOGIC_VECTOR (9 downto 0); signal ECC_signal: STD_LOGIC_VECTOR(3 downto 0); signal voted_data_out: STD_LOGIC_VECTOR (7 downto 0); signal status_out: STD_LOGIC_VECTOR (2 downto 0); signal ECC_out: STD_LOGIC_VECTOR (3 downto 0); signal voted_data_selector: STD_LOGIC_VECTOR (3 downto 0); -- Declare aliases for the input votes alias a is mp_data(0); alias b is mp_data(1); alias c is mp_data(2); alias d is mp_data(3); begin -- Add all entities to the top level onebitvoter: entity work.onebitvoter port map( clk => clk, reset => reset, a => a, b => b, c => c, d => d, y => voted_data_bit, status => status ); controller: entity work.controller port map( clk => clk, reset => reset, di_ready => di_ready, do_ready => do_ready, control_signals => control_signals, voted_data_selector => voted_data_selector ); registers: entity work.registers port map( clk => clk, reset => reset, voted_data_bit => voted_data_bit, status => status, control_signals => control_signals, ECC_signal => ECC_signal, voted_data_out => voted_data_out, status_out => status_out, ECC_out => ECC_out ); ECC: entity work.ECC port map( voted_data_out => voted_data_out, status_out => status_out, ECC_signal => ECC_signal ); -- End of entity declarations -- Add a process for the mux that will control the serial output from liaison process(voted_data_selector, voted_data_out, status_out, ECC_out) begin case voted_data_selector is when "0000" => -- 00 voted_data <= voted_data_out(0); when "0001" => -- 01 voted_data <= voted_data_out(1); when "0010" => -- 02 voted_data <= voted_data_out(2); when "0011" => -- 03 voted_data <= voted_data_out(3); when "0100" => -- 04 voted_data <= voted_data_out(4); when "0101" => -- 05 voted_data <= voted_data_out(5); when "0110" => -- 06 voted_data <= voted_data_out(6); when "0111" => -- 07 voted_data <= voted_data_out(7); when "1000" => -- 08 voted_data <= status_out(0); when "1001" => -- 09 voted_data <= status_out(1); when "1010" => -- 10 voted_data <= status_out(2); when "1011" => -- 11 voted_data <= ECC_out(0); when "1100" => -- 12 voted_data <= ECC_out(1); when "1101" => -- 13 voted_data <= ECC_out(2); when "1110" => -- 14 voted_data <= ECC_out(3); when others => voted_data <= '-'; -- should not be reached, but useful to detect glitches end case; -- when implementing and perfecting output throughput end process; end liaison;
------------------------------------------------------------------------------- -- Copyright 2013-2014 Jonathon Pendlum -- -- This is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- -- File: zc706.vhd -- Author: Jonathon Pendlum (jon.pendlum@gmail.com) -- Description: Toplevel file for ZC702. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity zc702 is port ( -- ARM Connections MIO : inout std_logic_vector(53 downto 0); PS_SRSTB : in std_logic; PS_CLK : in std_logic; PS_PORB : in std_logic; DDR_Clk : inout std_logic; DDR_Clk_n : inout std_logic; DDR_CKE : inout std_logic; DDR_CS_n : inout std_logic; DDR_RAS_n : inout std_logic; DDR_CAS_n : inout std_logic; DDR_WEB_pin : out std_logic; DDR_BankAddr : inout std_logic_vector(2 downto 0); DDR_Addr : inout std_logic_vector(14 downto 0); DDR_ODT : inout std_logic; DDR_DRSTB : inout std_logic; DDR_DQ : inout std_logic_vector(31 downto 0); DDR_DM : inout std_logic_vector(3 downto 0); DDR_DQS : inout std_logic_vector(3 downto 0); DDR_DQS_n : inout std_logic_vector(3 downto 0); DDR_VRP : inout std_logic; DDR_VRN : inout std_logic; -- USRP DDR Interface RX_DATA_CLK_N : in std_logic; RX_DATA_CLK_P : in std_logic; RX_DATA_N : in std_logic_vector(6 downto 0); RX_DATA_P : in std_logic_vector(6 downto 0); TX_DATA_N : out std_logic_vector(7 downto 0); TX_DATA_P : out std_logic_vector(7 downto 0); SPARE : out std_logic; UART_TX : out std_logic); end entity; architecture RTL of zc702 is ------------------------------------------------------------------------------- -- Component Declaration ------------------------------------------------------------------------------- component zc702_ps is port ( processing_system7_0_MIO : inout std_logic_vector(53 downto 0); processing_system7_0_PS_SRSTB_pin : in std_logic; processing_system7_0_PS_CLK_pin : in std_logic; processing_system7_0_PS_PORB_pin : in std_logic; processing_system7_0_DDR_Clk : inout std_logic; processing_system7_0_DDR_Clk_n : inout std_logic; processing_system7_0_DDR_CKE : inout std_logic; processing_system7_0_DDR_CS_n : inout std_logic; processing_system7_0_DDR_RAS_n : inout std_logic; processing_system7_0_DDR_CAS_n : inout std_logic; processing_system7_0_DDR_WEB_pin : out std_logic; processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0); processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0); processing_system7_0_DDR_ODT : inout std_logic; processing_system7_0_DDR_DRSTB : inout std_logic; processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0); processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0); processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0); processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0); processing_system7_0_DDR_VRN : inout std_logic; processing_system7_0_DDR_VRP : inout std_logic; axi_ext_slave_conn_0_M_AXI_AWADDR_pin : out std_logic_vector(31 downto 0); axi_ext_slave_conn_0_M_AXI_AWVALID_pin : out std_logic; axi_ext_slave_conn_0_M_AXI_AWREADY_pin : in std_logic; axi_ext_slave_conn_0_M_AXI_WDATA_pin : out std_logic_vector(31 downto 0); axi_ext_slave_conn_0_M_AXI_WSTRB_pin : out std_logic_vector(3 downto 0); axi_ext_slave_conn_0_M_AXI_WVALID_pin : out std_logic; axi_ext_slave_conn_0_M_AXI_WREADY_pin : in std_logic; axi_ext_slave_conn_0_M_AXI_BRESP_pin : in std_logic_vector(1 downto 0); axi_ext_slave_conn_0_M_AXI_BVALID_pin : in std_logic; axi_ext_slave_conn_0_M_AXI_BREADY_pin : out std_logic; axi_ext_slave_conn_0_M_AXI_ARADDR_pin : out std_logic_vector(31 downto 0); axi_ext_slave_conn_0_M_AXI_ARVALID_pin : out std_logic; axi_ext_slave_conn_0_M_AXI_ARREADY_pin : in std_logic; axi_ext_slave_conn_0_M_AXI_RDATA_pin : in std_logic_vector(31 downto 0); axi_ext_slave_conn_0_M_AXI_RRESP_pin : in std_logic_vector(1 downto 0); axi_ext_slave_conn_0_M_AXI_RVALID_pin : in std_logic; axi_ext_slave_conn_0_M_AXI_RREADY_pin : out std_logic; processing_system7_0_IRQ_F2P_pin : in std_logic_vector(15 downto 0); processing_system7_0_FCLK_CLK0_pin : out std_logic; processing_system7_0_FCLK_RESET0_N_pin : out std_logic; axi_ext_master_conn_0_S_AXI_AWADDR_pin : in std_logic_vector(31 downto 0); axi_ext_master_conn_0_S_AXI_AWLEN_pin : in std_logic_vector(7 downto 0); axi_ext_master_conn_0_S_AXI_AWSIZE_pin : in std_logic_vector(2 downto 0); axi_ext_master_conn_0_S_AXI_AWBURST_pin : in std_logic_vector(1 downto 0); axi_ext_master_conn_0_S_AXI_AWCACHE_pin : in std_logic_vector(3 downto 0); axi_ext_master_conn_0_S_AXI_AWPROT_pin : in std_logic_vector(2 downto 0); axi_ext_master_conn_0_S_AXI_AWVALID_pin : in std_logic; axi_ext_master_conn_0_S_AXI_AWREADY_pin : out std_logic; axi_ext_master_conn_0_S_AXI_WDATA_pin : in std_logic_vector(63 downto 0); axi_ext_master_conn_0_S_AXI_WSTRB_pin : in std_logic_vector(7 downto 0); axi_ext_master_conn_0_S_AXI_WLAST_pin : in std_logic; axi_ext_master_conn_0_S_AXI_WVALID_pin : in std_logic; axi_ext_master_conn_0_S_AXI_WREADY_pin : out std_logic; axi_ext_master_conn_0_S_AXI_BRESP_pin : out std_logic_vector(1 downto 0); axi_ext_master_conn_0_S_AXI_BVALID_pin : out std_logic; axi_ext_master_conn_0_S_AXI_BREADY_pin : in std_logic; axi_ext_master_conn_0_S_AXI_ARADDR_pin : in std_logic_vector(31 downto 0); axi_ext_master_conn_0_S_AXI_ARLEN_pin : in std_logic_vector(7 downto 0); axi_ext_master_conn_0_S_AXI_ARSIZE_pin : in std_logic_vector(2 downto 0); axi_ext_master_conn_0_S_AXI_ARBURST_pin : in std_logic_vector(1 downto 0); axi_ext_master_conn_0_S_AXI_ARCACHE_pin : in std_logic_vector(3 downto 0); axi_ext_master_conn_0_S_AXI_ARPROT_pin : in std_logic_vector(2 downto 0); axi_ext_master_conn_0_S_AXI_ARVALID_pin : in std_logic; axi_ext_master_conn_0_S_AXI_ARREADY_pin : out std_logic; axi_ext_master_conn_0_S_AXI_RDATA_pin : out std_logic_vector(63 downto 0); axi_ext_master_conn_0_S_AXI_RRESP_pin : out std_logic_vector(1 downto 0); axi_ext_master_conn_0_S_AXI_RLAST_pin : out std_logic; axi_ext_master_conn_0_S_AXI_RVALID_pin : out std_logic; axi_ext_master_conn_0_S_AXI_RREADY_pin : in std_logic; axi_ext_master_conn_0_S_AXI_AWUSER_pin : in std_logic_vector(4 downto 0); axi_ext_master_conn_0_S_AXI_ARUSER_pin : in std_logic_vector(4 downto 0)); end component; component ps_pl_interface is generic ( C_BASEADDR : std_logic_vector(31 downto 0) := x"40000000"; C_HIGHADDR : std_logic_vector(31 downto 0) := x"4001ffff"); port ( -- AXIS Stream Clock and Reset clk : in std_logic; rst_n : in std_logic; -- AXI-Lite Slave bus for access to control & status registers S_AXI_AWADDR : in std_logic_vector(31 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(31 downto 0); S_AXI_WSTRB : in std_logic_vector(3 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(31 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(31 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; -- AXI ACP Bus to interface with processor system M_AXI_AWADDR : out std_logic_vector(31 downto 0); M_AXI_AWPROT : out std_logic_vector(2 downto 0); M_AXI_AWVALID : out std_logic; M_AXI_AWREADY : in std_logic; M_AXI_WDATA : out std_logic_vector(63 downto 0); M_AXI_WSTRB : out std_logic_vector(7 downto 0); M_AXI_WVALID : out std_logic; M_AXI_WREADY : in std_logic; M_AXI_BRESP : in std_logic_vector(1 downto 0); M_AXI_BVALID : in std_logic; M_AXI_BREADY : out std_logic; M_AXI_AWLEN : out std_logic_vector(7 downto 0); M_AXI_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_AWBURST : out std_logic_vector(1 downto 0); M_AXI_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_AWUSER : out std_logic_vector(4 downto 0); M_AXI_WLAST : out std_logic; M_AXI_ARADDR : out std_logic_vector(31 downto 0); M_AXI_ARPROT : out std_logic_vector(2 downto 0); M_AXI_ARVALID : out std_logic; M_AXI_ARREADY : in std_logic; M_AXI_RDATA : in std_logic_vector(63 downto 0); M_AXI_RRESP : in std_logic_vector(1 downto 0); M_AXI_RVALID : in std_logic; M_AXI_RREADY : out std_logic; M_AXI_RLAST : in std_logic; M_AXI_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_ARUSER : out std_logic_vector(4 downto 0); M_AXI_ARLEN : out std_logic_vector(7 downto 0); M_AXI_ARBURST : out std_logic_vector(1 downto 0); M_AXI_ARSIZE : out std_logic_vector(2 downto 0); -- Interrupt on successfully completed AXI ACP writes irq : out std_logic; -- Global reset for all accelerators rst_glb_n : out std_logic; -- Accelerator interfaces -- Note: Master & Slave 0 are not listed as the Datamover componeent -- uses both. -- Accelerator 1 -- Accelerator 1 axis_master_1_tvalid : in std_logic; axis_master_1_tready : out std_logic; axis_master_1_tdata : in std_logic_vector(63 downto 0); axis_master_1_tdest : in std_logic_vector(2 downto 0); axis_master_1_tlast : in std_logic; axis_master_1_irq : in std_logic; axis_slave_1_tvalid : out std_logic; axis_slave_1_tready : in std_logic; axis_slave_1_tdata : out std_logic_vector(63 downto 0); axis_slave_1_tid : out std_logic_vector(2 downto 0); axis_slave_1_tlast : out std_logic; axis_slave_1_irq : in std_logic; status_1_addr : out std_logic_vector(7 downto 0); status_1_data : in std_logic_vector(31 downto 0); status_1_stb : out std_logic; ctrl_1_addr : out std_logic_vector(7 downto 0); ctrl_1_data : out std_logic_vector(31 downto 0); ctrl_1_stb : out std_logic; -- Accelerator 2 axis_master_2_tvalid : in std_logic; axis_master_2_tready : out std_logic; axis_master_2_tdata : in std_logic_vector(63 downto 0); axis_master_2_tdest : in std_logic_vector(2 downto 0); axis_master_2_tlast : in std_logic; axis_master_2_irq : in std_logic; axis_slave_2_tvalid : out std_logic; axis_slave_2_tready : in std_logic; axis_slave_2_tdata : out std_logic_vector(63 downto 0); axis_slave_2_tid : out std_logic_vector(2 downto 0); axis_slave_2_tlast : out std_logic; axis_slave_2_irq : in std_logic; status_2_addr : out std_logic_vector(7 downto 0); status_2_data : in std_logic_vector(31 downto 0); status_2_stb : out std_logic; ctrl_2_addr : out std_logic_vector(7 downto 0); ctrl_2_data : out std_logic_vector(31 downto 0); ctrl_2_stb : out std_logic; -- Accelerator 3 axis_master_3_tvalid : in std_logic; axis_master_3_tready : out std_logic; axis_master_3_tdata : in std_logic_vector(63 downto 0); axis_master_3_tdest : in std_logic_vector(2 downto 0); axis_master_3_tlast : in std_logic; axis_master_3_irq : in std_logic; axis_slave_3_tvalid : out std_logic; axis_slave_3_tready : in std_logic; axis_slave_3_tdata : out std_logic_vector(63 downto 0); axis_slave_3_tid : out std_logic_vector(2 downto 0); axis_slave_3_tlast : out std_logic; axis_slave_3_irq : in std_logic; status_3_addr : out std_logic_vector(7 downto 0); status_3_data : in std_logic_vector(31 downto 0); status_3_stb : out std_logic; ctrl_3_addr : out std_logic_vector(7 downto 0); ctrl_3_data : out std_logic_vector(31 downto 0); ctrl_3_stb : out std_logic; -- Accelerator 4 axis_master_4_tvalid : in std_logic; axis_master_4_tready : out std_logic; axis_master_4_tdata : in std_logic_vector(63 downto 0); axis_master_4_tdest : in std_logic_vector(2 downto 0); axis_master_4_tlast : in std_logic; axis_master_4_irq : in std_logic; axis_slave_4_tvalid : out std_logic; axis_slave_4_tready : in std_logic; axis_slave_4_tdata : out std_logic_vector(63 downto 0); axis_slave_4_tid : out std_logic_vector(2 downto 0); axis_slave_4_tlast : out std_logic; axis_slave_4_irq : in std_logic; status_4_addr : out std_logic_vector(7 downto 0); status_4_data : in std_logic_vector(31 downto 0); status_4_stb : out std_logic; ctrl_4_addr : out std_logic_vector(7 downto 0); ctrl_4_data : out std_logic_vector(31 downto 0); ctrl_4_stb : out std_logic; -- Accelerator 5 axis_master_5_tvalid : in std_logic; axis_master_5_tready : out std_logic; axis_master_5_tdata : in std_logic_vector(63 downto 0); axis_master_5_tdest : in std_logic_vector(2 downto 0); axis_master_5_tlast : in std_logic; axis_master_5_irq : in std_logic; axis_slave_5_tvalid : out std_logic; axis_slave_5_tready : in std_logic; axis_slave_5_tdata : out std_logic_vector(63 downto 0); axis_slave_5_tid : out std_logic_vector(2 downto 0); axis_slave_5_tlast : out std_logic; axis_slave_5_irq : in std_logic; status_5_addr : out std_logic_vector(7 downto 0); status_5_data : in std_logic_vector(31 downto 0); status_5_stb : out std_logic; ctrl_5_addr : out std_logic_vector(7 downto 0); ctrl_5_data : out std_logic_vector(31 downto 0); ctrl_5_stb : out std_logic; -- Accelerator 6 axis_master_6_tvalid : in std_logic; axis_master_6_tready : out std_logic; axis_master_6_tdata : in std_logic_vector(63 downto 0); axis_master_6_tdest : in std_logic_vector(2 downto 0); axis_master_6_tlast : in std_logic; axis_master_6_irq : in std_logic; axis_slave_6_tvalid : out std_logic; axis_slave_6_tready : in std_logic; axis_slave_6_tdata : out std_logic_vector(63 downto 0); axis_slave_6_tid : out std_logic_vector(2 downto 0); axis_slave_6_tlast : out std_logic; axis_slave_6_irq : in std_logic; status_6_addr : out std_logic_vector(7 downto 0); status_6_data : in std_logic_vector(31 downto 0); status_6_stb : out std_logic; ctrl_6_addr : out std_logic_vector(7 downto 0); ctrl_6_data : out std_logic_vector(31 downto 0); ctrl_6_stb : out std_logic; -- Accelerator 7 axis_master_7_tvalid : in std_logic; axis_master_7_tready : out std_logic; axis_master_7_tdata : in std_logic_vector(63 downto 0); axis_master_7_tdest : in std_logic_vector(2 downto 0); axis_master_7_tlast : in std_logic; axis_master_7_irq : in std_logic; axis_slave_7_tvalid : out std_logic; axis_slave_7_tready : in std_logic; axis_slave_7_tdata : out std_logic_vector(63 downto 0); axis_slave_7_tid : out std_logic_vector(2 downto 0); axis_slave_7_tlast : out std_logic; axis_slave_7_irq : in std_logic; status_7_addr : out std_logic_vector(7 downto 0); status_7_data : in std_logic_vector(31 downto 0); status_7_stb : out std_logic; ctrl_7_addr : out std_logic_vector(7 downto 0); ctrl_7_data : out std_logic_vector(31 downto 0); ctrl_7_stb : out std_logic); end component; component usrp_ddr_intf_axis is generic ( DDR_CLOCK_FREQ : integer := 100e6; -- Clock rate of DDR interface BAUD : integer := 115200); -- UART baud rate port ( -- USRP Interface UART_TX : out std_logic; -- UART RX_DATA_CLK_N : in std_logic; -- Receive data clock (N) RX_DATA_CLK_P : in std_logic; -- Receive data clock (P) RX_DATA_N : in std_logic_vector(6 downto 0); -- Receive data (N) RX_DATA_P : in std_logic_vector(6 downto 0); -- Receive data (N) TX_DATA_N : out std_logic_vector(7 downto 0); -- Transmit data (N) TX_DATA_P : out std_logic_vector(7 downto 0); -- Transmit data (P) -- Clock and Reset clk : in std_logic; rst_n : in std_logic; -- Control and Status Registers status_addr : in std_logic_vector(7 downto 0); status_data : out std_logic_vector(31 downto 0); status_stb : in std_logic; ctrl_addr : in std_logic_vector(7 downto 0); ctrl_data : in std_logic_vector(31 downto 0); ctrl_stb : in std_logic; -- AXIS Stream Slave Interface (DAC / TX Data) axis_slave_tvalid : in std_logic; axis_slave_tready : out std_logic; axis_slave_tdata : in std_logic_vector(63 downto 0); axis_slave_tid : in std_logic_vector(2 downto 0); axis_slave_tlast : in std_logic; axis_slave_irq : out std_logic; -- Not used -- AXIS Stream Master Interface (ADC / RX Data) axis_master_tvalid : out std_logic; axis_master_tready : in std_logic; axis_master_tdata : out std_logic_vector(63 downto 0); axis_master_tdest : out std_logic_vector(2 downto 0); axis_master_tlast : out std_logic; axis_master_irq : out std_logic; -- Not used -- Sideband signals rx_enable_aux : in std_logic; tx_enable_aux : in std_logic); end component; component spectrum_sense is port ( -- Clock and Reset clk : in std_logic; rst_n : in std_logic; -- Control and Status Registers status_addr : in std_logic_vector(7 downto 0); status_data : out std_logic_vector(31 downto 0); status_stb : in std_logic; ctrl_addr : in std_logic_vector(7 downto 0); ctrl_data : in std_logic_vector(31 downto 0); ctrl_stb : in std_logic; -- AXIS Stream Slave Interface (Time Domain / FFT Input) axis_slave_tvalid : in std_logic; axis_slave_tready : out std_logic; axis_slave_tdata : in std_logic_vector(63 downto 0); axis_slave_tid : in std_logic_vector(2 downto 0); axis_slave_tlast : in std_logic; axis_slave_irq : out std_logic; -- Not used -- AXIS Stream Master Interface (Frequency Domain / FFT Output) axis_master_tvalid : out std_logic; axis_master_tready : in std_logic; axis_master_tdata : out std_logic_vector(63 downto 0); axis_master_tdest : out std_logic_vector(2 downto 0); axis_master_tlast : out std_logic; axis_master_irq : out std_logic; -- Strobes when threshold exceeded -- Sideband signals threshold_not_exceeded : out std_logic; threshold_not_exceeded_stb : out std_logic; threshold_exceeded : out std_logic; threshold_exceeded_stb : out std_logic); end component; component bpsk_mod is port ( -- Clock and Reset clk : in std_logic; rst_n : in std_logic; -- Control and Status Registers status_addr : in std_logic_vector(7 downto 0); status_data : out std_logic_vector(31 downto 0); status_stb : in std_logic; ctrl_addr : in std_logic_vector(7 downto 0); ctrl_data : in std_logic_vector(31 downto 0); ctrl_stb : in std_logic; -- AXIS Stream Slave Interface (Binary Data) axis_slave_tvalid : in std_logic; axis_slave_tready : out std_logic; axis_slave_tdata : in std_logic_vector(63 downto 0); axis_slave_tid : in std_logic_vector(2 downto 0); axis_slave_tlast : in std_logic; axis_slave_irq : out std_logic; -- Not used (TODO: maybe use for near empty input FIFO?) -- AXIS Stream Master Interface (Modulated complex samples) axis_master_tvalid : out std_logic; axis_master_tready : in std_logic; axis_master_tdata : out std_logic_vector(63 downto 0); axis_master_tdest : out std_logic_vector(2 downto 0); axis_master_tlast : out std_logic; axis_master_irq : out std_logic; -- Not used -- Sideband signals trigger_stb : in std_logic); end component; ----------------------------------------------------------------------------- -- Signals Declaration ----------------------------------------------------------------------------- signal clk : std_logic; signal rst_n : std_logic; signal S_AXI_AWADDR : std_logic_vector(31 downto 0); signal S_AXI_AWVALID : std_logic; signal S_AXI_AWREADY : std_logic; signal S_AXI_WDATA : std_logic_vector(31 downto 0); signal S_AXI_WSTRB : std_logic_vector(3 downto 0); signal S_AXI_WVALID : std_logic; signal S_AXI_WREADY : std_logic; signal S_AXI_BRESP : std_logic_vector(1 downto 0); signal S_AXI_BVALID : std_logic; signal S_AXI_BREADY : std_logic; signal S_AXI_ARADDR : std_logic_vector(31 downto 0); signal S_AXI_ARVALID : std_logic; signal S_AXI_ARREADY : std_logic; signal S_AXI_RDATA : std_logic_vector(31 downto 0); signal S_AXI_RRESP : std_logic_vector(1 downto 0); signal S_AXI_RVALID : std_logic; signal S_AXI_RREADY : std_logic; signal M_AXI_AWADDR : std_logic_vector(31 downto 0); signal M_AXI_AWPROT : std_logic_vector(2 downto 0); signal M_AXI_AWVALID : std_logic; signal M_AXI_AWREADY : std_logic; signal M_AXI_WDATA : std_logic_vector(63 downto 0); signal M_AXI_WSTRB : std_logic_vector(7 downto 0); signal M_AXI_WVALID : std_logic; signal M_AXI_WREADY : std_logic; signal M_AXI_BRESP : std_logic_vector(1 downto 0); signal M_AXI_BVALID : std_logic; signal M_AXI_BREADY : std_logic; signal M_AXI_AWLEN : std_logic_vector(7 downto 0); signal M_AXI_AWSIZE : std_logic_vector(2 downto 0); signal M_AXI_AWBURST : std_logic_vector(1 downto 0); signal M_AXI_AWCACHE : std_logic_vector(3 downto 0); signal M_AXI_AWUSER : std_logic_vector(4 downto 0); signal M_AXI_WLAST : std_logic; signal M_AXI_ARADDR : std_logic_vector(31 downto 0); signal M_AXI_ARPROT : std_logic_vector(2 downto 0); signal M_AXI_ARVALID : std_logic; signal M_AXI_ARREADY : std_logic; signal M_AXI_RDATA : std_logic_vector(63 downto 0); signal M_AXI_RRESP : std_logic_vector(1 downto 0); signal M_AXI_RVALID : std_logic; signal M_AXI_RREADY : std_logic; signal M_AXI_RLAST : std_logic; signal M_AXI_ARCACHE : std_logic_vector(3 downto 0); signal M_AXI_ARUSER : std_logic_vector(4 downto 0); signal M_AXI_ARLEN : std_logic_vector(7 downto 0); signal M_AXI_ARBURST : std_logic_vector(1 downto 0); signal M_AXI_ARSIZE : std_logic_vector(2 downto 0); signal processing_system7_0_IRQ_F2P_pin : std_logic_vector(15 downto 0); signal irq : std_logic; signal rst_glb_n : std_logic; signal axis_master_1_tvalid : std_logic; signal axis_master_1_tready : std_logic; signal axis_master_1_tdata : std_logic_vector(63 downto 0); signal axis_master_1_tdest : std_logic_vector(2 downto 0); signal axis_master_1_tlast : std_logic; signal axis_master_1_irq : std_logic; signal axis_slave_1_tvalid : std_logic; signal axis_slave_1_tready : std_logic; signal axis_slave_1_tdata : std_logic_vector(63 downto 0); signal axis_slave_1_tid : std_logic_vector(2 downto 0); signal axis_slave_1_tlast : std_logic; signal axis_slave_1_irq : std_logic; signal status_1_addr : std_logic_vector(7 downto 0); signal status_1_data : std_logic_vector(31 downto 0); signal status_1_stb : std_logic; signal ctrl_1_addr : std_logic_vector(7 downto 0); signal ctrl_1_data : std_logic_vector(31 downto 0); signal ctrl_1_stb : std_logic; signal axis_master_2_tvalid : std_logic; signal axis_master_2_tready : std_logic; signal axis_master_2_tdata : std_logic_vector(63 downto 0); signal axis_master_2_tdest : std_logic_vector(2 downto 0); signal axis_master_2_tlast : std_logic; signal axis_master_2_irq : std_logic; signal axis_slave_2_tvalid : std_logic; signal axis_slave_2_tready : std_logic; signal axis_slave_2_tdata : std_logic_vector(63 downto 0); signal axis_slave_2_tid : std_logic_vector(2 downto 0); signal axis_slave_2_tlast : std_logic; signal axis_slave_2_irq : std_logic; signal status_2_addr : std_logic_vector(7 downto 0); signal status_2_data : std_logic_vector(31 downto 0); signal status_2_stb : std_logic; signal ctrl_2_addr : std_logic_vector(7 downto 0); signal ctrl_2_data : std_logic_vector(31 downto 0); signal ctrl_2_stb : std_logic; signal axis_master_3_tvalid : std_logic; signal axis_master_3_tready : std_logic; signal axis_master_3_tdata : std_logic_vector(63 downto 0); signal axis_master_3_tdest : std_logic_vector(2 downto 0); signal axis_master_3_tlast : std_logic; signal axis_master_3_irq : std_logic; signal axis_slave_3_tvalid : std_logic; signal axis_slave_3_tready : std_logic; signal axis_slave_3_tdata : std_logic_vector(63 downto 0); signal axis_slave_3_tid : std_logic_vector(2 downto 0); signal axis_slave_3_tlast : std_logic; signal axis_slave_3_irq : std_logic; signal status_3_addr : std_logic_vector(7 downto 0); signal status_3_data : std_logic_vector(31 downto 0); signal status_3_stb : std_logic; signal ctrl_3_addr : std_logic_vector(7 downto 0); signal ctrl_3_data : std_logic_vector(31 downto 0); signal ctrl_3_stb : std_logic; signal axis_master_4_tvalid : std_logic; signal axis_master_4_tready : std_logic; signal axis_master_4_tdata : std_logic_vector(63 downto 0); signal axis_master_4_tdest : std_logic_vector(2 downto 0); signal axis_master_4_tlast : std_logic; signal axis_master_4_irq : std_logic; signal axis_slave_4_tvalid : std_logic; signal axis_slave_4_tready : std_logic; signal axis_slave_4_tdata : std_logic_vector(63 downto 0); signal axis_slave_4_tid : std_logic_vector(2 downto 0); signal axis_slave_4_tlast : std_logic; signal axis_slave_4_irq : std_logic; signal status_4_addr : std_logic_vector(7 downto 0); signal status_4_data : std_logic_vector(31 downto 0); signal status_4_stb : std_logic; signal ctrl_4_addr : std_logic_vector(7 downto 0); signal ctrl_4_data : std_logic_vector(31 downto 0); signal ctrl_4_stb : std_logic; signal axis_master_5_tvalid : std_logic; signal axis_master_5_tready : std_logic; signal axis_master_5_tdata : std_logic_vector(63 downto 0); signal axis_master_5_tdest : std_logic_vector(2 downto 0); signal axis_master_5_tlast : std_logic; signal axis_master_5_irq : std_logic; signal axis_slave_5_tvalid : std_logic; signal axis_slave_5_tready : std_logic; signal axis_slave_5_tdata : std_logic_vector(63 downto 0); signal axis_slave_5_tid : std_logic_vector(2 downto 0); signal axis_slave_5_tlast : std_logic; signal axis_slave_5_irq : std_logic; signal status_5_addr : std_logic_vector(7 downto 0); signal status_5_data : std_logic_vector(31 downto 0); signal status_5_stb : std_logic; signal ctrl_5_addr : std_logic_vector(7 downto 0); signal ctrl_5_data : std_logic_vector(31 downto 0); signal ctrl_5_stb : std_logic; signal axis_master_6_tvalid : std_logic; signal axis_master_6_tready : std_logic; signal axis_master_6_tdata : std_logic_vector(63 downto 0); signal axis_master_6_tdest : std_logic_vector(2 downto 0); signal axis_master_6_tlast : std_logic; signal axis_master_6_irq : std_logic; signal axis_slave_6_tvalid : std_logic; signal axis_slave_6_tready : std_logic; signal axis_slave_6_tdata : std_logic_vector(63 downto 0); signal axis_slave_6_tid : std_logic_vector(2 downto 0); signal axis_slave_6_tlast : std_logic; signal axis_slave_6_irq : std_logic; signal status_6_addr : std_logic_vector(7 downto 0); signal status_6_data : std_logic_vector(31 downto 0); signal status_6_stb : std_logic; signal ctrl_6_addr : std_logic_vector(7 downto 0); signal ctrl_6_data : std_logic_vector(31 downto 0); signal ctrl_6_stb : std_logic; signal axis_master_7_tvalid : std_logic; signal axis_master_7_tready : std_logic; signal axis_master_7_tdata : std_logic_vector(63 downto 0); signal axis_master_7_tdest : std_logic_vector(2 downto 0); signal axis_master_7_tlast : std_logic; signal axis_master_7_irq : std_logic; signal axis_slave_7_tvalid : std_logic; signal axis_slave_7_tready : std_logic; signal axis_slave_7_tdata : std_logic_vector(63 downto 0); signal axis_slave_7_tid : std_logic_vector(2 downto 0); signal axis_slave_7_tlast : std_logic; signal axis_slave_7_irq : std_logic; signal status_7_addr : std_logic_vector(7 downto 0); signal status_7_data : std_logic_vector(31 downto 0); signal status_7_stb : std_logic; signal ctrl_7_addr : std_logic_vector(7 downto 0); signal ctrl_7_data : std_logic_vector(31 downto 0); signal ctrl_7_stb : std_logic; signal rx_enable_aux : std_logic; signal tx_enable_aux : std_logic; signal threshold_not_exceeded : std_logic; signal threshold_not_exceeded_stb : std_logic; signal threshold_exceeded : std_logic; signal threshold_exceeded_stb : std_logic; signal trigger_stb : std_logic; begin inst_zc702_ps : zc702_ps port map ( processing_system7_0_MIO => MIO, processing_system7_0_PS_SRSTB_pin => PS_SRSTB, processing_system7_0_PS_CLK_pin => PS_CLK, processing_system7_0_PS_PORB_pin => PS_PORB, processing_system7_0_DDR_Clk => DDR_Clk, processing_system7_0_DDR_Clk_n => DDR_Clk_n, processing_system7_0_DDR_CKE => DDR_CKE, processing_system7_0_DDR_CS_n => DDR_CS_n, processing_system7_0_DDR_RAS_n => DDR_RAS_n, processing_system7_0_DDR_CAS_n => DDR_CAS_n, processing_system7_0_DDR_WEB_pin => DDR_WEB_pin, processing_system7_0_DDR_BankAddr => DDR_BankAddr, processing_system7_0_DDR_Addr => DDR_Addr, processing_system7_0_DDR_ODT => DDR_ODT, processing_system7_0_DDR_DRSTB => DDR_DRSTB, processing_system7_0_DDR_DQ => DDR_DQ, processing_system7_0_DDR_DM => DDR_DM, processing_system7_0_DDR_DQS => DDR_DQS, processing_system7_0_DDR_DQS_n => DDR_DQS_n, processing_system7_0_DDR_VRN => DDR_VRN, processing_system7_0_DDR_VRP => DDR_VRP, axi_ext_slave_conn_0_M_AXI_AWADDR_pin => S_AXI_AWADDR, axi_ext_slave_conn_0_M_AXI_AWVALID_pin => S_AXI_AWVALID, axi_ext_slave_conn_0_M_AXI_AWREADY_pin => S_AXI_AWREADY, axi_ext_slave_conn_0_M_AXI_WDATA_pin => S_AXI_WDATA, axi_ext_slave_conn_0_M_AXI_WSTRB_pin => S_AXI_WSTRB, axi_ext_slave_conn_0_M_AXI_WVALID_pin => S_AXI_WVALID, axi_ext_slave_conn_0_M_AXI_WREADY_pin => S_AXI_WREADY, axi_ext_slave_conn_0_M_AXI_BRESP_pin => S_AXI_BRESP, axi_ext_slave_conn_0_M_AXI_BVALID_pin => S_AXI_BVALID, axi_ext_slave_conn_0_M_AXI_BREADY_pin => S_AXI_BREADY, axi_ext_slave_conn_0_M_AXI_ARADDR_pin => S_AXI_ARADDR, axi_ext_slave_conn_0_M_AXI_ARVALID_pin => S_AXI_ARVALID, axi_ext_slave_conn_0_M_AXI_ARREADY_pin => S_AXI_ARREADY, axi_ext_slave_conn_0_M_AXI_RDATA_pin => S_AXI_RDATA, axi_ext_slave_conn_0_M_AXI_RRESP_pin => S_AXI_RRESP, axi_ext_slave_conn_0_M_AXI_RVALID_pin => S_AXI_RVALID, axi_ext_slave_conn_0_M_AXI_RREADY_pin => S_AXI_RREADY, processing_system7_0_IRQ_F2P_pin => processing_system7_0_IRQ_F2P_pin, processing_system7_0_FCLK_CLK0_pin => clk, processing_system7_0_FCLK_RESET0_N_pin => rst_n, axi_ext_master_conn_0_S_AXI_AWADDR_pin => M_AXI_AWADDR, axi_ext_master_conn_0_S_AXI_AWLEN_pin => M_AXI_AWLEN, axi_ext_master_conn_0_S_AXI_AWSIZE_pin => M_AXI_AWSIZE, axi_ext_master_conn_0_S_AXI_AWBURST_pin => M_AXI_AWBURST, axi_ext_master_conn_0_S_AXI_AWCACHE_pin => M_AXI_AWCACHE, axi_ext_master_conn_0_S_AXI_AWPROT_pin => M_AXI_AWPROT, axi_ext_master_conn_0_S_AXI_AWVALID_pin => M_AXI_AWVALID, axi_ext_master_conn_0_S_AXI_AWREADY_pin => M_AXI_AWREADY, axi_ext_master_conn_0_S_AXI_WDATA_pin => M_AXI_WDATA, axi_ext_master_conn_0_S_AXI_WSTRB_pin => M_AXI_WSTRB, axi_ext_master_conn_0_S_AXI_WLAST_pin => M_AXI_WLAST, axi_ext_master_conn_0_S_AXI_WVALID_pin => M_AXI_WVALID, axi_ext_master_conn_0_S_AXI_WREADY_pin => M_AXI_WREADY, axi_ext_master_conn_0_S_AXI_BRESP_pin => M_AXI_BRESP, axi_ext_master_conn_0_S_AXI_BVALID_pin => M_AXI_BVALID, axi_ext_master_conn_0_S_AXI_BREADY_pin => M_AXI_BREADY, axi_ext_master_conn_0_S_AXI_ARADDR_pin => M_AXI_ARADDR, axi_ext_master_conn_0_S_AXI_ARLEN_pin => M_AXI_ARLEN, axi_ext_master_conn_0_S_AXI_ARSIZE_pin => M_AXI_ARSIZE, axi_ext_master_conn_0_S_AXI_ARBURST_pin => M_AXI_ARBURST, axi_ext_master_conn_0_S_AXI_ARCACHE_pin => M_AXI_ARCACHE, axi_ext_master_conn_0_S_AXI_ARPROT_pin => M_AXI_ARPROT, axi_ext_master_conn_0_S_AXI_ARVALID_pin => M_AXI_ARVALID, axi_ext_master_conn_0_S_AXI_ARREADY_pin => M_AXI_ARREADY, axi_ext_master_conn_0_S_AXI_RDATA_pin => M_AXI_RDATA, axi_ext_master_conn_0_S_AXI_RRESP_pin => M_AXI_RRESP, axi_ext_master_conn_0_S_AXI_RLAST_pin => M_AXI_RLAST, axi_ext_master_conn_0_S_AXI_RVALID_pin => M_AXI_RVALID, axi_ext_master_conn_0_S_AXI_RREADY_pin => M_AXI_RREADY, axi_ext_master_conn_0_S_AXI_AWUSER_pin => M_AXI_AWUSER, axi_ext_master_conn_0_S_AXI_ARUSER_pin => M_AXI_ARUSER); processing_system7_0_IRQ_F2P_pin(15) <= irq; inst_ps_pl_interface : ps_pl_interface generic map ( C_BASEADDR => x"40000000", C_HIGHADDR => x"4001ffff") port map ( clk => clk, rst_n => rst_n, S_AXI_AWADDR => S_AXI_AWADDR, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_AWREADY => S_AXI_AWREADY, S_AXI_WDATA => S_AXI_WDATA, S_AXI_WSTRB => S_AXI_WSTRB, S_AXI_WVALID => S_AXI_WVALID, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BRESP => S_AXI_BRESP, S_AXI_BVALID => S_AXI_BVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_ARADDR => S_AXI_ARADDR, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RDATA => S_AXI_RDATA, S_AXI_RRESP => S_AXI_RRESP, S_AXI_RVALID => S_AXI_RVALID, S_AXI_RREADY => S_AXI_RREADY, M_AXI_AWADDR => M_AXI_AWADDR, M_AXI_AWPROT => M_AXI_AWPROT, M_AXI_AWVALID => M_AXI_AWVALID, M_AXI_AWREADY => M_AXI_AWREADY, M_AXI_WDATA => M_AXI_WDATA, M_AXI_WSTRB => M_AXI_WSTRB, M_AXI_WVALID => M_AXI_WVALID, M_AXI_WREADY => M_AXI_WREADY, M_AXI_BRESP => M_AXI_BRESP, M_AXI_BVALID => M_AXI_BVALID, M_AXI_BREADY => M_AXI_BREADY, M_AXI_AWLEN => M_AXI_AWLEN, M_AXI_AWSIZE => M_AXI_AWSIZE, M_AXI_AWBURST => M_AXI_AWBURST, M_AXI_AWCACHE => M_AXI_AWCACHE, M_AXI_AWUSER => M_AXI_AWUSER, M_AXI_WLAST => M_AXI_WLAST, M_AXI_ARADDR => M_AXI_ARADDR, M_AXI_ARPROT => M_AXI_ARPROT, M_AXI_ARVALID => M_AXI_ARVALID, M_AXI_ARREADY => M_AXI_ARREADY, M_AXI_RDATA => M_AXI_RDATA, M_AXI_RRESP => M_AXI_RRESP, M_AXI_RVALID => M_AXI_RVALID, M_AXI_RREADY => M_AXI_RREADY, M_AXI_RLAST => M_AXI_RLAST, M_AXI_ARCACHE => M_AXI_ARCACHE, M_AXI_ARUSER => M_AXI_ARUSER, M_AXI_ARLEN => M_AXI_ARLEN, M_AXI_ARBURST => M_AXI_ARBURST, M_AXI_ARSIZE => M_AXI_ARSIZE, irq => irq, rst_glb_n => rst_glb_n, -- Note: Master 0 & Slave 0 interfaces are occupied by the -- datamover component internally. axis_master_1_tvalid => axis_master_1_tvalid, axis_master_1_tready => axis_master_1_tready, axis_master_1_tdata => axis_master_1_tdata, axis_master_1_tdest => axis_master_1_tdest, axis_master_1_tlast => axis_master_1_tlast, axis_master_1_irq => axis_master_1_irq, axis_slave_1_tvalid => axis_slave_1_tvalid, axis_slave_1_tready => axis_slave_1_tready, axis_slave_1_tdata => axis_slave_1_tdata, axis_slave_1_tid => axis_slave_1_tid, axis_slave_1_tlast => axis_slave_1_tlast, axis_slave_1_irq => axis_slave_1_irq, status_1_addr => status_1_addr, status_1_data => status_1_data, status_1_stb => status_1_stb, ctrl_1_addr => ctrl_1_addr, ctrl_1_data => ctrl_1_data, ctrl_1_stb => ctrl_1_stb, axis_master_2_tvalid => axis_master_2_tvalid, axis_master_2_tready => axis_master_2_tready, axis_master_2_tdata => axis_master_2_tdata, axis_master_2_tdest => axis_master_2_tdest, axis_master_2_tlast => axis_master_2_tlast, axis_master_2_irq => axis_master_2_irq, axis_slave_2_tvalid => axis_slave_2_tvalid, axis_slave_2_tready => axis_slave_2_tready, axis_slave_2_tdata => axis_slave_2_tdata, axis_slave_2_tid => axis_slave_2_tid, axis_slave_2_tlast => axis_slave_2_tlast, axis_slave_2_irq => axis_slave_2_irq, status_2_addr => status_2_addr, status_2_data => status_2_data, status_2_stb => status_2_stb, ctrl_2_addr => ctrl_2_addr, ctrl_2_data => ctrl_2_data, ctrl_2_stb => ctrl_2_stb, axis_master_3_tvalid => axis_master_3_tvalid, axis_master_3_tready => axis_master_3_tready, axis_master_3_tdata => axis_master_3_tdata, axis_master_3_tdest => axis_master_3_tdest, axis_master_3_tlast => axis_master_3_tlast, axis_master_3_irq => axis_master_3_irq, axis_slave_3_tvalid => axis_slave_3_tvalid, axis_slave_3_tready => axis_slave_3_tready, axis_slave_3_tdata => axis_slave_3_tdata, axis_slave_3_tid => axis_slave_3_tid, axis_slave_3_tlast => axis_slave_3_tlast, axis_slave_3_irq => axis_slave_3_irq, status_3_addr => status_3_addr, status_3_data => status_3_data, status_3_stb => status_3_stb, ctrl_3_addr => ctrl_3_addr, ctrl_3_data => ctrl_3_data, ctrl_3_stb => ctrl_3_stb, axis_master_4_tvalid => axis_master_4_tvalid, axis_master_4_tready => axis_master_4_tready, axis_master_4_tdata => axis_master_4_tdata, axis_master_4_tdest => axis_master_4_tdest, axis_master_4_tlast => axis_master_4_tlast, axis_master_4_irq => axis_master_4_irq, axis_slave_4_tvalid => axis_slave_4_tvalid, axis_slave_4_tready => axis_slave_4_tready, axis_slave_4_tdata => axis_slave_4_tdata, axis_slave_4_tid => axis_slave_4_tid, axis_slave_4_tlast => axis_slave_4_tlast, axis_slave_4_irq => axis_slave_4_irq, status_4_addr => status_4_addr, status_4_data => status_4_data, status_4_stb => status_4_stb, ctrl_4_addr => ctrl_4_addr, ctrl_4_data => ctrl_4_data, ctrl_4_stb => ctrl_4_stb, axis_master_5_tvalid => axis_master_5_tvalid, axis_master_5_tready => axis_master_5_tready, axis_master_5_tdata => axis_master_5_tdata, axis_master_5_tdest => axis_master_5_tdest, axis_master_5_tlast => axis_master_5_tlast, axis_master_5_irq => axis_master_5_irq, axis_slave_5_tvalid => axis_slave_5_tvalid, axis_slave_5_tready => axis_slave_5_tready, axis_slave_5_tdata => axis_slave_5_tdata, axis_slave_5_tid => axis_slave_5_tid, axis_slave_5_tlast => axis_slave_5_tlast, axis_slave_5_irq => axis_slave_5_irq, status_5_addr => status_5_addr, status_5_data => status_5_data, status_5_stb => status_5_stb, ctrl_5_addr => ctrl_5_addr, ctrl_5_data => ctrl_5_data, ctrl_5_stb => ctrl_5_stb, axis_master_6_tvalid => axis_master_6_tvalid, axis_master_6_tready => axis_master_6_tready, axis_master_6_tdata => axis_master_6_tdata, axis_master_6_tdest => axis_master_6_tdest, axis_master_6_tlast => axis_master_6_tlast, axis_master_6_irq => axis_master_6_irq, axis_slave_6_tvalid => axis_slave_6_tvalid, axis_slave_6_tready => axis_slave_6_tready, axis_slave_6_tdata => axis_slave_6_tdata, axis_slave_6_tid => axis_slave_6_tid, axis_slave_6_tlast => axis_slave_6_tlast, axis_slave_6_irq => axis_slave_6_irq, status_6_addr => status_6_addr, status_6_data => status_6_data, status_6_stb => status_6_stb, ctrl_6_addr => ctrl_6_addr, ctrl_6_data => ctrl_6_data, ctrl_6_stb => ctrl_6_stb, axis_master_7_tvalid => axis_master_7_tvalid, axis_master_7_tready => axis_master_7_tready, axis_master_7_tdata => axis_master_7_tdata, axis_master_7_tdest => axis_master_7_tdest, axis_master_7_tlast => axis_master_7_tlast, axis_master_7_irq => axis_master_7_irq, axis_slave_7_tvalid => axis_slave_7_tvalid, axis_slave_7_tready => axis_slave_7_tready, axis_slave_7_tdata => axis_slave_7_tdata, axis_slave_7_tid => axis_slave_7_tid, axis_slave_7_tlast => axis_slave_7_tlast, axis_slave_7_irq => axis_slave_7_irq, status_7_addr => status_7_addr, status_7_data => status_7_data, status_7_stb => status_7_stb, ctrl_7_addr => ctrl_7_addr, ctrl_7_data => ctrl_7_data, ctrl_7_stb => ctrl_7_stb); -- Accelerator 1 inst_usrp_ddr_intf_axis : usrp_ddr_intf_axis generic map ( DDR_CLOCK_FREQ => 100e6, BAUD => 115200) port map ( UART_TX => UART_TX, RX_DATA_CLK_N => RX_DATA_CLK_N, RX_DATA_CLK_P => RX_DATA_CLK_P, RX_DATA_N => RX_DATA_N, RX_DATA_P => RX_DATA_P, TX_DATA_N => TX_DATA_N, TX_DATA_P => TX_DATA_P, clk => clk, rst_n => rst_glb_n, status_addr => status_1_addr, status_data => status_1_data, status_stb => status_1_stb, ctrl_addr => ctrl_1_addr, ctrl_data => ctrl_1_data, ctrl_stb => ctrl_1_stb, axis_slave_tvalid => axis_slave_1_tvalid, axis_slave_tready => axis_slave_1_tready, axis_slave_tdata => axis_slave_1_tdata, axis_slave_tid => axis_slave_1_tid, axis_slave_tlast => axis_slave_1_tlast, axis_slave_irq => axis_slave_1_irq, axis_master_tvalid => axis_master_1_tvalid, axis_master_tready => axis_master_1_tready, axis_master_tdata => axis_master_1_tdata, axis_master_tdest => axis_master_1_tdest, axis_master_tlast => axis_master_1_tlast, axis_master_irq => axis_master_1_irq, rx_enable_aux => rx_enable_aux, tx_enable_aux => tx_enable_aux); rx_enable_aux <= '0'; tx_enable_aux <= threshold_exceeded OR threshold_not_exceeded; -- Accelerator 2 inst_spectrum_sense : spectrum_sense port map ( clk => clk, rst_n => rst_glb_n, status_addr => status_2_addr, status_data => status_2_data, status_stb => status_2_stb, ctrl_addr => ctrl_2_addr, ctrl_data => ctrl_2_data, ctrl_stb => ctrl_2_stb, axis_slave_tvalid => axis_slave_2_tvalid, axis_slave_tready => axis_slave_2_tready, axis_slave_tdata => axis_slave_2_tdata, axis_slave_tid => axis_slave_2_tid, axis_slave_tlast => axis_slave_2_tlast, axis_slave_irq => axis_slave_2_irq, axis_master_tvalid => axis_master_2_tvalid, axis_master_tready => axis_master_2_tready, axis_master_tdata => axis_master_2_tdata, axis_master_tdest => axis_master_2_tdest, axis_master_tlast => axis_master_2_tlast, axis_master_irq => axis_master_2_irq, threshold_not_exceeded => threshold_not_exceeded, threshold_not_exceeded_stb => threshold_not_exceeded_stb, threshold_exceeded => threshold_exceeded, threshold_exceeded_stb => threshold_exceeded_stb); -- Accelerator 3 inst_bpsk_mod : bpsk_mod port map ( clk => clk, rst_n => rst_glb_n, status_addr => status_3_addr, status_data => status_3_data, status_stb => status_3_stb, ctrl_addr => ctrl_3_addr, ctrl_data => ctrl_3_data, ctrl_stb => ctrl_3_stb, axis_slave_tvalid => axis_slave_3_tvalid, axis_slave_tready => axis_slave_3_tready, axis_slave_tdata => axis_slave_3_tdata, axis_slave_tid => axis_slave_3_tid, axis_slave_tlast => axis_slave_3_tlast, axis_slave_irq => axis_slave_3_irq, axis_master_tvalid => axis_master_3_tvalid, axis_master_tready => axis_master_3_tready, axis_master_tdata => axis_master_3_tdata, axis_master_tdest => axis_master_3_tdest, axis_master_tlast => axis_master_3_tlast, axis_master_irq => axis_master_3_irq, trigger_stb => trigger_stb); -- The output of either threshold trigger is controlled by control registers, so ORing them is -- not an issue as only one should be active at a time. trigger_stb <= threshold_exceeded_stb OR threshold_not_exceeded_stb; -- Unused Accelerators axis_slave_4_tready <= '0'; axis_slave_4_irq <= '0'; axis_master_4_tvalid <= '0'; axis_master_4_tdata <= x"0000000000000000"; axis_master_4_tdest <= "000"; axis_master_4_tlast <= '0'; axis_master_4_irq <= '0'; status_4_data <= x"00000000"; axis_slave_5_tready <= '0'; axis_slave_5_irq <= '0'; axis_master_5_tvalid <= '0'; axis_master_5_tdata <= x"0000000000000000"; axis_master_5_tdest <= "000"; axis_master_5_tlast <= '0'; axis_master_5_irq <= '0'; status_5_data <= x"00000000"; axis_slave_6_tready <= '0'; axis_slave_6_irq <= '0'; axis_master_6_tvalid <= '0'; axis_master_6_tdata <= x"0000000000000000"; axis_master_6_tdest <= "000"; axis_master_6_tlast <= '0'; axis_master_6_irq <= '0'; status_6_data <= x"00000000"; axis_slave_7_tready <= '0'; axis_slave_7_irq <= '0'; axis_master_7_tvalid <= '0'; axis_master_7_tdata <= x"0000000000000000"; axis_master_7_tdest <= "000"; axis_master_7_tlast <= '0'; axis_master_7_irq <= '0'; status_7_data <= x"00000000"; SPARE <= 'Z'; end architecture;
------------------------------------------------------------------------------- -- Copyright 2013-2014 Jonathon Pendlum -- -- This is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- -- File: zc706.vhd -- Author: Jonathon Pendlum (jon.pendlum@gmail.com) -- Description: Toplevel file for ZC702. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity zc702 is port ( -- ARM Connections MIO : inout std_logic_vector(53 downto 0); PS_SRSTB : in std_logic; PS_CLK : in std_logic; PS_PORB : in std_logic; DDR_Clk : inout std_logic; DDR_Clk_n : inout std_logic; DDR_CKE : inout std_logic; DDR_CS_n : inout std_logic; DDR_RAS_n : inout std_logic; DDR_CAS_n : inout std_logic; DDR_WEB_pin : out std_logic; DDR_BankAddr : inout std_logic_vector(2 downto 0); DDR_Addr : inout std_logic_vector(14 downto 0); DDR_ODT : inout std_logic; DDR_DRSTB : inout std_logic; DDR_DQ : inout std_logic_vector(31 downto 0); DDR_DM : inout std_logic_vector(3 downto 0); DDR_DQS : inout std_logic_vector(3 downto 0); DDR_DQS_n : inout std_logic_vector(3 downto 0); DDR_VRP : inout std_logic; DDR_VRN : inout std_logic; -- USRP DDR Interface RX_DATA_CLK_N : in std_logic; RX_DATA_CLK_P : in std_logic; RX_DATA_N : in std_logic_vector(6 downto 0); RX_DATA_P : in std_logic_vector(6 downto 0); TX_DATA_N : out std_logic_vector(7 downto 0); TX_DATA_P : out std_logic_vector(7 downto 0); SPARE : out std_logic; UART_TX : out std_logic); end entity; architecture RTL of zc702 is ------------------------------------------------------------------------------- -- Component Declaration ------------------------------------------------------------------------------- component zc702_ps is port ( processing_system7_0_MIO : inout std_logic_vector(53 downto 0); processing_system7_0_PS_SRSTB_pin : in std_logic; processing_system7_0_PS_CLK_pin : in std_logic; processing_system7_0_PS_PORB_pin : in std_logic; processing_system7_0_DDR_Clk : inout std_logic; processing_system7_0_DDR_Clk_n : inout std_logic; processing_system7_0_DDR_CKE : inout std_logic; processing_system7_0_DDR_CS_n : inout std_logic; processing_system7_0_DDR_RAS_n : inout std_logic; processing_system7_0_DDR_CAS_n : inout std_logic; processing_system7_0_DDR_WEB_pin : out std_logic; processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0); processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0); processing_system7_0_DDR_ODT : inout std_logic; processing_system7_0_DDR_DRSTB : inout std_logic; processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0); processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0); processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0); processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0); processing_system7_0_DDR_VRN : inout std_logic; processing_system7_0_DDR_VRP : inout std_logic; axi_ext_slave_conn_0_M_AXI_AWADDR_pin : out std_logic_vector(31 downto 0); axi_ext_slave_conn_0_M_AXI_AWVALID_pin : out std_logic; axi_ext_slave_conn_0_M_AXI_AWREADY_pin : in std_logic; axi_ext_slave_conn_0_M_AXI_WDATA_pin : out std_logic_vector(31 downto 0); axi_ext_slave_conn_0_M_AXI_WSTRB_pin : out std_logic_vector(3 downto 0); axi_ext_slave_conn_0_M_AXI_WVALID_pin : out std_logic; axi_ext_slave_conn_0_M_AXI_WREADY_pin : in std_logic; axi_ext_slave_conn_0_M_AXI_BRESP_pin : in std_logic_vector(1 downto 0); axi_ext_slave_conn_0_M_AXI_BVALID_pin : in std_logic; axi_ext_slave_conn_0_M_AXI_BREADY_pin : out std_logic; axi_ext_slave_conn_0_M_AXI_ARADDR_pin : out std_logic_vector(31 downto 0); axi_ext_slave_conn_0_M_AXI_ARVALID_pin : out std_logic; axi_ext_slave_conn_0_M_AXI_ARREADY_pin : in std_logic; axi_ext_slave_conn_0_M_AXI_RDATA_pin : in std_logic_vector(31 downto 0); axi_ext_slave_conn_0_M_AXI_RRESP_pin : in std_logic_vector(1 downto 0); axi_ext_slave_conn_0_M_AXI_RVALID_pin : in std_logic; axi_ext_slave_conn_0_M_AXI_RREADY_pin : out std_logic; processing_system7_0_IRQ_F2P_pin : in std_logic_vector(15 downto 0); processing_system7_0_FCLK_CLK0_pin : out std_logic; processing_system7_0_FCLK_RESET0_N_pin : out std_logic; axi_ext_master_conn_0_S_AXI_AWADDR_pin : in std_logic_vector(31 downto 0); axi_ext_master_conn_0_S_AXI_AWLEN_pin : in std_logic_vector(7 downto 0); axi_ext_master_conn_0_S_AXI_AWSIZE_pin : in std_logic_vector(2 downto 0); axi_ext_master_conn_0_S_AXI_AWBURST_pin : in std_logic_vector(1 downto 0); axi_ext_master_conn_0_S_AXI_AWCACHE_pin : in std_logic_vector(3 downto 0); axi_ext_master_conn_0_S_AXI_AWPROT_pin : in std_logic_vector(2 downto 0); axi_ext_master_conn_0_S_AXI_AWVALID_pin : in std_logic; axi_ext_master_conn_0_S_AXI_AWREADY_pin : out std_logic; axi_ext_master_conn_0_S_AXI_WDATA_pin : in std_logic_vector(63 downto 0); axi_ext_master_conn_0_S_AXI_WSTRB_pin : in std_logic_vector(7 downto 0); axi_ext_master_conn_0_S_AXI_WLAST_pin : in std_logic; axi_ext_master_conn_0_S_AXI_WVALID_pin : in std_logic; axi_ext_master_conn_0_S_AXI_WREADY_pin : out std_logic; axi_ext_master_conn_0_S_AXI_BRESP_pin : out std_logic_vector(1 downto 0); axi_ext_master_conn_0_S_AXI_BVALID_pin : out std_logic; axi_ext_master_conn_0_S_AXI_BREADY_pin : in std_logic; axi_ext_master_conn_0_S_AXI_ARADDR_pin : in std_logic_vector(31 downto 0); axi_ext_master_conn_0_S_AXI_ARLEN_pin : in std_logic_vector(7 downto 0); axi_ext_master_conn_0_S_AXI_ARSIZE_pin : in std_logic_vector(2 downto 0); axi_ext_master_conn_0_S_AXI_ARBURST_pin : in std_logic_vector(1 downto 0); axi_ext_master_conn_0_S_AXI_ARCACHE_pin : in std_logic_vector(3 downto 0); axi_ext_master_conn_0_S_AXI_ARPROT_pin : in std_logic_vector(2 downto 0); axi_ext_master_conn_0_S_AXI_ARVALID_pin : in std_logic; axi_ext_master_conn_0_S_AXI_ARREADY_pin : out std_logic; axi_ext_master_conn_0_S_AXI_RDATA_pin : out std_logic_vector(63 downto 0); axi_ext_master_conn_0_S_AXI_RRESP_pin : out std_logic_vector(1 downto 0); axi_ext_master_conn_0_S_AXI_RLAST_pin : out std_logic; axi_ext_master_conn_0_S_AXI_RVALID_pin : out std_logic; axi_ext_master_conn_0_S_AXI_RREADY_pin : in std_logic; axi_ext_master_conn_0_S_AXI_AWUSER_pin : in std_logic_vector(4 downto 0); axi_ext_master_conn_0_S_AXI_ARUSER_pin : in std_logic_vector(4 downto 0)); end component; component ps_pl_interface is generic ( C_BASEADDR : std_logic_vector(31 downto 0) := x"40000000"; C_HIGHADDR : std_logic_vector(31 downto 0) := x"4001ffff"); port ( -- AXIS Stream Clock and Reset clk : in std_logic; rst_n : in std_logic; -- AXI-Lite Slave bus for access to control & status registers S_AXI_AWADDR : in std_logic_vector(31 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(31 downto 0); S_AXI_WSTRB : in std_logic_vector(3 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(31 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(31 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; -- AXI ACP Bus to interface with processor system M_AXI_AWADDR : out std_logic_vector(31 downto 0); M_AXI_AWPROT : out std_logic_vector(2 downto 0); M_AXI_AWVALID : out std_logic; M_AXI_AWREADY : in std_logic; M_AXI_WDATA : out std_logic_vector(63 downto 0); M_AXI_WSTRB : out std_logic_vector(7 downto 0); M_AXI_WVALID : out std_logic; M_AXI_WREADY : in std_logic; M_AXI_BRESP : in std_logic_vector(1 downto 0); M_AXI_BVALID : in std_logic; M_AXI_BREADY : out std_logic; M_AXI_AWLEN : out std_logic_vector(7 downto 0); M_AXI_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_AWBURST : out std_logic_vector(1 downto 0); M_AXI_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_AWUSER : out std_logic_vector(4 downto 0); M_AXI_WLAST : out std_logic; M_AXI_ARADDR : out std_logic_vector(31 downto 0); M_AXI_ARPROT : out std_logic_vector(2 downto 0); M_AXI_ARVALID : out std_logic; M_AXI_ARREADY : in std_logic; M_AXI_RDATA : in std_logic_vector(63 downto 0); M_AXI_RRESP : in std_logic_vector(1 downto 0); M_AXI_RVALID : in std_logic; M_AXI_RREADY : out std_logic; M_AXI_RLAST : in std_logic; M_AXI_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_ARUSER : out std_logic_vector(4 downto 0); M_AXI_ARLEN : out std_logic_vector(7 downto 0); M_AXI_ARBURST : out std_logic_vector(1 downto 0); M_AXI_ARSIZE : out std_logic_vector(2 downto 0); -- Interrupt on successfully completed AXI ACP writes irq : out std_logic; -- Global reset for all accelerators rst_glb_n : out std_logic; -- Accelerator interfaces -- Note: Master & Slave 0 are not listed as the Datamover componeent -- uses both. -- Accelerator 1 -- Accelerator 1 axis_master_1_tvalid : in std_logic; axis_master_1_tready : out std_logic; axis_master_1_tdata : in std_logic_vector(63 downto 0); axis_master_1_tdest : in std_logic_vector(2 downto 0); axis_master_1_tlast : in std_logic; axis_master_1_irq : in std_logic; axis_slave_1_tvalid : out std_logic; axis_slave_1_tready : in std_logic; axis_slave_1_tdata : out std_logic_vector(63 downto 0); axis_slave_1_tid : out std_logic_vector(2 downto 0); axis_slave_1_tlast : out std_logic; axis_slave_1_irq : in std_logic; status_1_addr : out std_logic_vector(7 downto 0); status_1_data : in std_logic_vector(31 downto 0); status_1_stb : out std_logic; ctrl_1_addr : out std_logic_vector(7 downto 0); ctrl_1_data : out std_logic_vector(31 downto 0); ctrl_1_stb : out std_logic; -- Accelerator 2 axis_master_2_tvalid : in std_logic; axis_master_2_tready : out std_logic; axis_master_2_tdata : in std_logic_vector(63 downto 0); axis_master_2_tdest : in std_logic_vector(2 downto 0); axis_master_2_tlast : in std_logic; axis_master_2_irq : in std_logic; axis_slave_2_tvalid : out std_logic; axis_slave_2_tready : in std_logic; axis_slave_2_tdata : out std_logic_vector(63 downto 0); axis_slave_2_tid : out std_logic_vector(2 downto 0); axis_slave_2_tlast : out std_logic; axis_slave_2_irq : in std_logic; status_2_addr : out std_logic_vector(7 downto 0); status_2_data : in std_logic_vector(31 downto 0); status_2_stb : out std_logic; ctrl_2_addr : out std_logic_vector(7 downto 0); ctrl_2_data : out std_logic_vector(31 downto 0); ctrl_2_stb : out std_logic; -- Accelerator 3 axis_master_3_tvalid : in std_logic; axis_master_3_tready : out std_logic; axis_master_3_tdata : in std_logic_vector(63 downto 0); axis_master_3_tdest : in std_logic_vector(2 downto 0); axis_master_3_tlast : in std_logic; axis_master_3_irq : in std_logic; axis_slave_3_tvalid : out std_logic; axis_slave_3_tready : in std_logic; axis_slave_3_tdata : out std_logic_vector(63 downto 0); axis_slave_3_tid : out std_logic_vector(2 downto 0); axis_slave_3_tlast : out std_logic; axis_slave_3_irq : in std_logic; status_3_addr : out std_logic_vector(7 downto 0); status_3_data : in std_logic_vector(31 downto 0); status_3_stb : out std_logic; ctrl_3_addr : out std_logic_vector(7 downto 0); ctrl_3_data : out std_logic_vector(31 downto 0); ctrl_3_stb : out std_logic; -- Accelerator 4 axis_master_4_tvalid : in std_logic; axis_master_4_tready : out std_logic; axis_master_4_tdata : in std_logic_vector(63 downto 0); axis_master_4_tdest : in std_logic_vector(2 downto 0); axis_master_4_tlast : in std_logic; axis_master_4_irq : in std_logic; axis_slave_4_tvalid : out std_logic; axis_slave_4_tready : in std_logic; axis_slave_4_tdata : out std_logic_vector(63 downto 0); axis_slave_4_tid : out std_logic_vector(2 downto 0); axis_slave_4_tlast : out std_logic; axis_slave_4_irq : in std_logic; status_4_addr : out std_logic_vector(7 downto 0); status_4_data : in std_logic_vector(31 downto 0); status_4_stb : out std_logic; ctrl_4_addr : out std_logic_vector(7 downto 0); ctrl_4_data : out std_logic_vector(31 downto 0); ctrl_4_stb : out std_logic; -- Accelerator 5 axis_master_5_tvalid : in std_logic; axis_master_5_tready : out std_logic; axis_master_5_tdata : in std_logic_vector(63 downto 0); axis_master_5_tdest : in std_logic_vector(2 downto 0); axis_master_5_tlast : in std_logic; axis_master_5_irq : in std_logic; axis_slave_5_tvalid : out std_logic; axis_slave_5_tready : in std_logic; axis_slave_5_tdata : out std_logic_vector(63 downto 0); axis_slave_5_tid : out std_logic_vector(2 downto 0); axis_slave_5_tlast : out std_logic; axis_slave_5_irq : in std_logic; status_5_addr : out std_logic_vector(7 downto 0); status_5_data : in std_logic_vector(31 downto 0); status_5_stb : out std_logic; ctrl_5_addr : out std_logic_vector(7 downto 0); ctrl_5_data : out std_logic_vector(31 downto 0); ctrl_5_stb : out std_logic; -- Accelerator 6 axis_master_6_tvalid : in std_logic; axis_master_6_tready : out std_logic; axis_master_6_tdata : in std_logic_vector(63 downto 0); axis_master_6_tdest : in std_logic_vector(2 downto 0); axis_master_6_tlast : in std_logic; axis_master_6_irq : in std_logic; axis_slave_6_tvalid : out std_logic; axis_slave_6_tready : in std_logic; axis_slave_6_tdata : out std_logic_vector(63 downto 0); axis_slave_6_tid : out std_logic_vector(2 downto 0); axis_slave_6_tlast : out std_logic; axis_slave_6_irq : in std_logic; status_6_addr : out std_logic_vector(7 downto 0); status_6_data : in std_logic_vector(31 downto 0); status_6_stb : out std_logic; ctrl_6_addr : out std_logic_vector(7 downto 0); ctrl_6_data : out std_logic_vector(31 downto 0); ctrl_6_stb : out std_logic; -- Accelerator 7 axis_master_7_tvalid : in std_logic; axis_master_7_tready : out std_logic; axis_master_7_tdata : in std_logic_vector(63 downto 0); axis_master_7_tdest : in std_logic_vector(2 downto 0); axis_master_7_tlast : in std_logic; axis_master_7_irq : in std_logic; axis_slave_7_tvalid : out std_logic; axis_slave_7_tready : in std_logic; axis_slave_7_tdata : out std_logic_vector(63 downto 0); axis_slave_7_tid : out std_logic_vector(2 downto 0); axis_slave_7_tlast : out std_logic; axis_slave_7_irq : in std_logic; status_7_addr : out std_logic_vector(7 downto 0); status_7_data : in std_logic_vector(31 downto 0); status_7_stb : out std_logic; ctrl_7_addr : out std_logic_vector(7 downto 0); ctrl_7_data : out std_logic_vector(31 downto 0); ctrl_7_stb : out std_logic); end component; component usrp_ddr_intf_axis is generic ( DDR_CLOCK_FREQ : integer := 100e6; -- Clock rate of DDR interface BAUD : integer := 115200); -- UART baud rate port ( -- USRP Interface UART_TX : out std_logic; -- UART RX_DATA_CLK_N : in std_logic; -- Receive data clock (N) RX_DATA_CLK_P : in std_logic; -- Receive data clock (P) RX_DATA_N : in std_logic_vector(6 downto 0); -- Receive data (N) RX_DATA_P : in std_logic_vector(6 downto 0); -- Receive data (N) TX_DATA_N : out std_logic_vector(7 downto 0); -- Transmit data (N) TX_DATA_P : out std_logic_vector(7 downto 0); -- Transmit data (P) -- Clock and Reset clk : in std_logic; rst_n : in std_logic; -- Control and Status Registers status_addr : in std_logic_vector(7 downto 0); status_data : out std_logic_vector(31 downto 0); status_stb : in std_logic; ctrl_addr : in std_logic_vector(7 downto 0); ctrl_data : in std_logic_vector(31 downto 0); ctrl_stb : in std_logic; -- AXIS Stream Slave Interface (DAC / TX Data) axis_slave_tvalid : in std_logic; axis_slave_tready : out std_logic; axis_slave_tdata : in std_logic_vector(63 downto 0); axis_slave_tid : in std_logic_vector(2 downto 0); axis_slave_tlast : in std_logic; axis_slave_irq : out std_logic; -- Not used -- AXIS Stream Master Interface (ADC / RX Data) axis_master_tvalid : out std_logic; axis_master_tready : in std_logic; axis_master_tdata : out std_logic_vector(63 downto 0); axis_master_tdest : out std_logic_vector(2 downto 0); axis_master_tlast : out std_logic; axis_master_irq : out std_logic; -- Not used -- Sideband signals rx_enable_aux : in std_logic; tx_enable_aux : in std_logic); end component; component spectrum_sense is port ( -- Clock and Reset clk : in std_logic; rst_n : in std_logic; -- Control and Status Registers status_addr : in std_logic_vector(7 downto 0); status_data : out std_logic_vector(31 downto 0); status_stb : in std_logic; ctrl_addr : in std_logic_vector(7 downto 0); ctrl_data : in std_logic_vector(31 downto 0); ctrl_stb : in std_logic; -- AXIS Stream Slave Interface (Time Domain / FFT Input) axis_slave_tvalid : in std_logic; axis_slave_tready : out std_logic; axis_slave_tdata : in std_logic_vector(63 downto 0); axis_slave_tid : in std_logic_vector(2 downto 0); axis_slave_tlast : in std_logic; axis_slave_irq : out std_logic; -- Not used -- AXIS Stream Master Interface (Frequency Domain / FFT Output) axis_master_tvalid : out std_logic; axis_master_tready : in std_logic; axis_master_tdata : out std_logic_vector(63 downto 0); axis_master_tdest : out std_logic_vector(2 downto 0); axis_master_tlast : out std_logic; axis_master_irq : out std_logic; -- Strobes when threshold exceeded -- Sideband signals threshold_not_exceeded : out std_logic; threshold_not_exceeded_stb : out std_logic; threshold_exceeded : out std_logic; threshold_exceeded_stb : out std_logic); end component; component bpsk_mod is port ( -- Clock and Reset clk : in std_logic; rst_n : in std_logic; -- Control and Status Registers status_addr : in std_logic_vector(7 downto 0); status_data : out std_logic_vector(31 downto 0); status_stb : in std_logic; ctrl_addr : in std_logic_vector(7 downto 0); ctrl_data : in std_logic_vector(31 downto 0); ctrl_stb : in std_logic; -- AXIS Stream Slave Interface (Binary Data) axis_slave_tvalid : in std_logic; axis_slave_tready : out std_logic; axis_slave_tdata : in std_logic_vector(63 downto 0); axis_slave_tid : in std_logic_vector(2 downto 0); axis_slave_tlast : in std_logic; axis_slave_irq : out std_logic; -- Not used (TODO: maybe use for near empty input FIFO?) -- AXIS Stream Master Interface (Modulated complex samples) axis_master_tvalid : out std_logic; axis_master_tready : in std_logic; axis_master_tdata : out std_logic_vector(63 downto 0); axis_master_tdest : out std_logic_vector(2 downto 0); axis_master_tlast : out std_logic; axis_master_irq : out std_logic; -- Not used -- Sideband signals trigger_stb : in std_logic); end component; ----------------------------------------------------------------------------- -- Signals Declaration ----------------------------------------------------------------------------- signal clk : std_logic; signal rst_n : std_logic; signal S_AXI_AWADDR : std_logic_vector(31 downto 0); signal S_AXI_AWVALID : std_logic; signal S_AXI_AWREADY : std_logic; signal S_AXI_WDATA : std_logic_vector(31 downto 0); signal S_AXI_WSTRB : std_logic_vector(3 downto 0); signal S_AXI_WVALID : std_logic; signal S_AXI_WREADY : std_logic; signal S_AXI_BRESP : std_logic_vector(1 downto 0); signal S_AXI_BVALID : std_logic; signal S_AXI_BREADY : std_logic; signal S_AXI_ARADDR : std_logic_vector(31 downto 0); signal S_AXI_ARVALID : std_logic; signal S_AXI_ARREADY : std_logic; signal S_AXI_RDATA : std_logic_vector(31 downto 0); signal S_AXI_RRESP : std_logic_vector(1 downto 0); signal S_AXI_RVALID : std_logic; signal S_AXI_RREADY : std_logic; signal M_AXI_AWADDR : std_logic_vector(31 downto 0); signal M_AXI_AWPROT : std_logic_vector(2 downto 0); signal M_AXI_AWVALID : std_logic; signal M_AXI_AWREADY : std_logic; signal M_AXI_WDATA : std_logic_vector(63 downto 0); signal M_AXI_WSTRB : std_logic_vector(7 downto 0); signal M_AXI_WVALID : std_logic; signal M_AXI_WREADY : std_logic; signal M_AXI_BRESP : std_logic_vector(1 downto 0); signal M_AXI_BVALID : std_logic; signal M_AXI_BREADY : std_logic; signal M_AXI_AWLEN : std_logic_vector(7 downto 0); signal M_AXI_AWSIZE : std_logic_vector(2 downto 0); signal M_AXI_AWBURST : std_logic_vector(1 downto 0); signal M_AXI_AWCACHE : std_logic_vector(3 downto 0); signal M_AXI_AWUSER : std_logic_vector(4 downto 0); signal M_AXI_WLAST : std_logic; signal M_AXI_ARADDR : std_logic_vector(31 downto 0); signal M_AXI_ARPROT : std_logic_vector(2 downto 0); signal M_AXI_ARVALID : std_logic; signal M_AXI_ARREADY : std_logic; signal M_AXI_RDATA : std_logic_vector(63 downto 0); signal M_AXI_RRESP : std_logic_vector(1 downto 0); signal M_AXI_RVALID : std_logic; signal M_AXI_RREADY : std_logic; signal M_AXI_RLAST : std_logic; signal M_AXI_ARCACHE : std_logic_vector(3 downto 0); signal M_AXI_ARUSER : std_logic_vector(4 downto 0); signal M_AXI_ARLEN : std_logic_vector(7 downto 0); signal M_AXI_ARBURST : std_logic_vector(1 downto 0); signal M_AXI_ARSIZE : std_logic_vector(2 downto 0); signal processing_system7_0_IRQ_F2P_pin : std_logic_vector(15 downto 0); signal irq : std_logic; signal rst_glb_n : std_logic; signal axis_master_1_tvalid : std_logic; signal axis_master_1_tready : std_logic; signal axis_master_1_tdata : std_logic_vector(63 downto 0); signal axis_master_1_tdest : std_logic_vector(2 downto 0); signal axis_master_1_tlast : std_logic; signal axis_master_1_irq : std_logic; signal axis_slave_1_tvalid : std_logic; signal axis_slave_1_tready : std_logic; signal axis_slave_1_tdata : std_logic_vector(63 downto 0); signal axis_slave_1_tid : std_logic_vector(2 downto 0); signal axis_slave_1_tlast : std_logic; signal axis_slave_1_irq : std_logic; signal status_1_addr : std_logic_vector(7 downto 0); signal status_1_data : std_logic_vector(31 downto 0); signal status_1_stb : std_logic; signal ctrl_1_addr : std_logic_vector(7 downto 0); signal ctrl_1_data : std_logic_vector(31 downto 0); signal ctrl_1_stb : std_logic; signal axis_master_2_tvalid : std_logic; signal axis_master_2_tready : std_logic; signal axis_master_2_tdata : std_logic_vector(63 downto 0); signal axis_master_2_tdest : std_logic_vector(2 downto 0); signal axis_master_2_tlast : std_logic; signal axis_master_2_irq : std_logic; signal axis_slave_2_tvalid : std_logic; signal axis_slave_2_tready : std_logic; signal axis_slave_2_tdata : std_logic_vector(63 downto 0); signal axis_slave_2_tid : std_logic_vector(2 downto 0); signal axis_slave_2_tlast : std_logic; signal axis_slave_2_irq : std_logic; signal status_2_addr : std_logic_vector(7 downto 0); signal status_2_data : std_logic_vector(31 downto 0); signal status_2_stb : std_logic; signal ctrl_2_addr : std_logic_vector(7 downto 0); signal ctrl_2_data : std_logic_vector(31 downto 0); signal ctrl_2_stb : std_logic; signal axis_master_3_tvalid : std_logic; signal axis_master_3_tready : std_logic; signal axis_master_3_tdata : std_logic_vector(63 downto 0); signal axis_master_3_tdest : std_logic_vector(2 downto 0); signal axis_master_3_tlast : std_logic; signal axis_master_3_irq : std_logic; signal axis_slave_3_tvalid : std_logic; signal axis_slave_3_tready : std_logic; signal axis_slave_3_tdata : std_logic_vector(63 downto 0); signal axis_slave_3_tid : std_logic_vector(2 downto 0); signal axis_slave_3_tlast : std_logic; signal axis_slave_3_irq : std_logic; signal status_3_addr : std_logic_vector(7 downto 0); signal status_3_data : std_logic_vector(31 downto 0); signal status_3_stb : std_logic; signal ctrl_3_addr : std_logic_vector(7 downto 0); signal ctrl_3_data : std_logic_vector(31 downto 0); signal ctrl_3_stb : std_logic; signal axis_master_4_tvalid : std_logic; signal axis_master_4_tready : std_logic; signal axis_master_4_tdata : std_logic_vector(63 downto 0); signal axis_master_4_tdest : std_logic_vector(2 downto 0); signal axis_master_4_tlast : std_logic; signal axis_master_4_irq : std_logic; signal axis_slave_4_tvalid : std_logic; signal axis_slave_4_tready : std_logic; signal axis_slave_4_tdata : std_logic_vector(63 downto 0); signal axis_slave_4_tid : std_logic_vector(2 downto 0); signal axis_slave_4_tlast : std_logic; signal axis_slave_4_irq : std_logic; signal status_4_addr : std_logic_vector(7 downto 0); signal status_4_data : std_logic_vector(31 downto 0); signal status_4_stb : std_logic; signal ctrl_4_addr : std_logic_vector(7 downto 0); signal ctrl_4_data : std_logic_vector(31 downto 0); signal ctrl_4_stb : std_logic; signal axis_master_5_tvalid : std_logic; signal axis_master_5_tready : std_logic; signal axis_master_5_tdata : std_logic_vector(63 downto 0); signal axis_master_5_tdest : std_logic_vector(2 downto 0); signal axis_master_5_tlast : std_logic; signal axis_master_5_irq : std_logic; signal axis_slave_5_tvalid : std_logic; signal axis_slave_5_tready : std_logic; signal axis_slave_5_tdata : std_logic_vector(63 downto 0); signal axis_slave_5_tid : std_logic_vector(2 downto 0); signal axis_slave_5_tlast : std_logic; signal axis_slave_5_irq : std_logic; signal status_5_addr : std_logic_vector(7 downto 0); signal status_5_data : std_logic_vector(31 downto 0); signal status_5_stb : std_logic; signal ctrl_5_addr : std_logic_vector(7 downto 0); signal ctrl_5_data : std_logic_vector(31 downto 0); signal ctrl_5_stb : std_logic; signal axis_master_6_tvalid : std_logic; signal axis_master_6_tready : std_logic; signal axis_master_6_tdata : std_logic_vector(63 downto 0); signal axis_master_6_tdest : std_logic_vector(2 downto 0); signal axis_master_6_tlast : std_logic; signal axis_master_6_irq : std_logic; signal axis_slave_6_tvalid : std_logic; signal axis_slave_6_tready : std_logic; signal axis_slave_6_tdata : std_logic_vector(63 downto 0); signal axis_slave_6_tid : std_logic_vector(2 downto 0); signal axis_slave_6_tlast : std_logic; signal axis_slave_6_irq : std_logic; signal status_6_addr : std_logic_vector(7 downto 0); signal status_6_data : std_logic_vector(31 downto 0); signal status_6_stb : std_logic; signal ctrl_6_addr : std_logic_vector(7 downto 0); signal ctrl_6_data : std_logic_vector(31 downto 0); signal ctrl_6_stb : std_logic; signal axis_master_7_tvalid : std_logic; signal axis_master_7_tready : std_logic; signal axis_master_7_tdata : std_logic_vector(63 downto 0); signal axis_master_7_tdest : std_logic_vector(2 downto 0); signal axis_master_7_tlast : std_logic; signal axis_master_7_irq : std_logic; signal axis_slave_7_tvalid : std_logic; signal axis_slave_7_tready : std_logic; signal axis_slave_7_tdata : std_logic_vector(63 downto 0); signal axis_slave_7_tid : std_logic_vector(2 downto 0); signal axis_slave_7_tlast : std_logic; signal axis_slave_7_irq : std_logic; signal status_7_addr : std_logic_vector(7 downto 0); signal status_7_data : std_logic_vector(31 downto 0); signal status_7_stb : std_logic; signal ctrl_7_addr : std_logic_vector(7 downto 0); signal ctrl_7_data : std_logic_vector(31 downto 0); signal ctrl_7_stb : std_logic; signal rx_enable_aux : std_logic; signal tx_enable_aux : std_logic; signal threshold_not_exceeded : std_logic; signal threshold_not_exceeded_stb : std_logic; signal threshold_exceeded : std_logic; signal threshold_exceeded_stb : std_logic; signal trigger_stb : std_logic; begin inst_zc702_ps : zc702_ps port map ( processing_system7_0_MIO => MIO, processing_system7_0_PS_SRSTB_pin => PS_SRSTB, processing_system7_0_PS_CLK_pin => PS_CLK, processing_system7_0_PS_PORB_pin => PS_PORB, processing_system7_0_DDR_Clk => DDR_Clk, processing_system7_0_DDR_Clk_n => DDR_Clk_n, processing_system7_0_DDR_CKE => DDR_CKE, processing_system7_0_DDR_CS_n => DDR_CS_n, processing_system7_0_DDR_RAS_n => DDR_RAS_n, processing_system7_0_DDR_CAS_n => DDR_CAS_n, processing_system7_0_DDR_WEB_pin => DDR_WEB_pin, processing_system7_0_DDR_BankAddr => DDR_BankAddr, processing_system7_0_DDR_Addr => DDR_Addr, processing_system7_0_DDR_ODT => DDR_ODT, processing_system7_0_DDR_DRSTB => DDR_DRSTB, processing_system7_0_DDR_DQ => DDR_DQ, processing_system7_0_DDR_DM => DDR_DM, processing_system7_0_DDR_DQS => DDR_DQS, processing_system7_0_DDR_DQS_n => DDR_DQS_n, processing_system7_0_DDR_VRN => DDR_VRN, processing_system7_0_DDR_VRP => DDR_VRP, axi_ext_slave_conn_0_M_AXI_AWADDR_pin => S_AXI_AWADDR, axi_ext_slave_conn_0_M_AXI_AWVALID_pin => S_AXI_AWVALID, axi_ext_slave_conn_0_M_AXI_AWREADY_pin => S_AXI_AWREADY, axi_ext_slave_conn_0_M_AXI_WDATA_pin => S_AXI_WDATA, axi_ext_slave_conn_0_M_AXI_WSTRB_pin => S_AXI_WSTRB, axi_ext_slave_conn_0_M_AXI_WVALID_pin => S_AXI_WVALID, axi_ext_slave_conn_0_M_AXI_WREADY_pin => S_AXI_WREADY, axi_ext_slave_conn_0_M_AXI_BRESP_pin => S_AXI_BRESP, axi_ext_slave_conn_0_M_AXI_BVALID_pin => S_AXI_BVALID, axi_ext_slave_conn_0_M_AXI_BREADY_pin => S_AXI_BREADY, axi_ext_slave_conn_0_M_AXI_ARADDR_pin => S_AXI_ARADDR, axi_ext_slave_conn_0_M_AXI_ARVALID_pin => S_AXI_ARVALID, axi_ext_slave_conn_0_M_AXI_ARREADY_pin => S_AXI_ARREADY, axi_ext_slave_conn_0_M_AXI_RDATA_pin => S_AXI_RDATA, axi_ext_slave_conn_0_M_AXI_RRESP_pin => S_AXI_RRESP, axi_ext_slave_conn_0_M_AXI_RVALID_pin => S_AXI_RVALID, axi_ext_slave_conn_0_M_AXI_RREADY_pin => S_AXI_RREADY, processing_system7_0_IRQ_F2P_pin => processing_system7_0_IRQ_F2P_pin, processing_system7_0_FCLK_CLK0_pin => clk, processing_system7_0_FCLK_RESET0_N_pin => rst_n, axi_ext_master_conn_0_S_AXI_AWADDR_pin => M_AXI_AWADDR, axi_ext_master_conn_0_S_AXI_AWLEN_pin => M_AXI_AWLEN, axi_ext_master_conn_0_S_AXI_AWSIZE_pin => M_AXI_AWSIZE, axi_ext_master_conn_0_S_AXI_AWBURST_pin => M_AXI_AWBURST, axi_ext_master_conn_0_S_AXI_AWCACHE_pin => M_AXI_AWCACHE, axi_ext_master_conn_0_S_AXI_AWPROT_pin => M_AXI_AWPROT, axi_ext_master_conn_0_S_AXI_AWVALID_pin => M_AXI_AWVALID, axi_ext_master_conn_0_S_AXI_AWREADY_pin => M_AXI_AWREADY, axi_ext_master_conn_0_S_AXI_WDATA_pin => M_AXI_WDATA, axi_ext_master_conn_0_S_AXI_WSTRB_pin => M_AXI_WSTRB, axi_ext_master_conn_0_S_AXI_WLAST_pin => M_AXI_WLAST, axi_ext_master_conn_0_S_AXI_WVALID_pin => M_AXI_WVALID, axi_ext_master_conn_0_S_AXI_WREADY_pin => M_AXI_WREADY, axi_ext_master_conn_0_S_AXI_BRESP_pin => M_AXI_BRESP, axi_ext_master_conn_0_S_AXI_BVALID_pin => M_AXI_BVALID, axi_ext_master_conn_0_S_AXI_BREADY_pin => M_AXI_BREADY, axi_ext_master_conn_0_S_AXI_ARADDR_pin => M_AXI_ARADDR, axi_ext_master_conn_0_S_AXI_ARLEN_pin => M_AXI_ARLEN, axi_ext_master_conn_0_S_AXI_ARSIZE_pin => M_AXI_ARSIZE, axi_ext_master_conn_0_S_AXI_ARBURST_pin => M_AXI_ARBURST, axi_ext_master_conn_0_S_AXI_ARCACHE_pin => M_AXI_ARCACHE, axi_ext_master_conn_0_S_AXI_ARPROT_pin => M_AXI_ARPROT, axi_ext_master_conn_0_S_AXI_ARVALID_pin => M_AXI_ARVALID, axi_ext_master_conn_0_S_AXI_ARREADY_pin => M_AXI_ARREADY, axi_ext_master_conn_0_S_AXI_RDATA_pin => M_AXI_RDATA, axi_ext_master_conn_0_S_AXI_RRESP_pin => M_AXI_RRESP, axi_ext_master_conn_0_S_AXI_RLAST_pin => M_AXI_RLAST, axi_ext_master_conn_0_S_AXI_RVALID_pin => M_AXI_RVALID, axi_ext_master_conn_0_S_AXI_RREADY_pin => M_AXI_RREADY, axi_ext_master_conn_0_S_AXI_AWUSER_pin => M_AXI_AWUSER, axi_ext_master_conn_0_S_AXI_ARUSER_pin => M_AXI_ARUSER); processing_system7_0_IRQ_F2P_pin(15) <= irq; inst_ps_pl_interface : ps_pl_interface generic map ( C_BASEADDR => x"40000000", C_HIGHADDR => x"4001ffff") port map ( clk => clk, rst_n => rst_n, S_AXI_AWADDR => S_AXI_AWADDR, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_AWREADY => S_AXI_AWREADY, S_AXI_WDATA => S_AXI_WDATA, S_AXI_WSTRB => S_AXI_WSTRB, S_AXI_WVALID => S_AXI_WVALID, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BRESP => S_AXI_BRESP, S_AXI_BVALID => S_AXI_BVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_ARADDR => S_AXI_ARADDR, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RDATA => S_AXI_RDATA, S_AXI_RRESP => S_AXI_RRESP, S_AXI_RVALID => S_AXI_RVALID, S_AXI_RREADY => S_AXI_RREADY, M_AXI_AWADDR => M_AXI_AWADDR, M_AXI_AWPROT => M_AXI_AWPROT, M_AXI_AWVALID => M_AXI_AWVALID, M_AXI_AWREADY => M_AXI_AWREADY, M_AXI_WDATA => M_AXI_WDATA, M_AXI_WSTRB => M_AXI_WSTRB, M_AXI_WVALID => M_AXI_WVALID, M_AXI_WREADY => M_AXI_WREADY, M_AXI_BRESP => M_AXI_BRESP, M_AXI_BVALID => M_AXI_BVALID, M_AXI_BREADY => M_AXI_BREADY, M_AXI_AWLEN => M_AXI_AWLEN, M_AXI_AWSIZE => M_AXI_AWSIZE, M_AXI_AWBURST => M_AXI_AWBURST, M_AXI_AWCACHE => M_AXI_AWCACHE, M_AXI_AWUSER => M_AXI_AWUSER, M_AXI_WLAST => M_AXI_WLAST, M_AXI_ARADDR => M_AXI_ARADDR, M_AXI_ARPROT => M_AXI_ARPROT, M_AXI_ARVALID => M_AXI_ARVALID, M_AXI_ARREADY => M_AXI_ARREADY, M_AXI_RDATA => M_AXI_RDATA, M_AXI_RRESP => M_AXI_RRESP, M_AXI_RVALID => M_AXI_RVALID, M_AXI_RREADY => M_AXI_RREADY, M_AXI_RLAST => M_AXI_RLAST, M_AXI_ARCACHE => M_AXI_ARCACHE, M_AXI_ARUSER => M_AXI_ARUSER, M_AXI_ARLEN => M_AXI_ARLEN, M_AXI_ARBURST => M_AXI_ARBURST, M_AXI_ARSIZE => M_AXI_ARSIZE, irq => irq, rst_glb_n => rst_glb_n, -- Note: Master 0 & Slave 0 interfaces are occupied by the -- datamover component internally. axis_master_1_tvalid => axis_master_1_tvalid, axis_master_1_tready => axis_master_1_tready, axis_master_1_tdata => axis_master_1_tdata, axis_master_1_tdest => axis_master_1_tdest, axis_master_1_tlast => axis_master_1_tlast, axis_master_1_irq => axis_master_1_irq, axis_slave_1_tvalid => axis_slave_1_tvalid, axis_slave_1_tready => axis_slave_1_tready, axis_slave_1_tdata => axis_slave_1_tdata, axis_slave_1_tid => axis_slave_1_tid, axis_slave_1_tlast => axis_slave_1_tlast, axis_slave_1_irq => axis_slave_1_irq, status_1_addr => status_1_addr, status_1_data => status_1_data, status_1_stb => status_1_stb, ctrl_1_addr => ctrl_1_addr, ctrl_1_data => ctrl_1_data, ctrl_1_stb => ctrl_1_stb, axis_master_2_tvalid => axis_master_2_tvalid, axis_master_2_tready => axis_master_2_tready, axis_master_2_tdata => axis_master_2_tdata, axis_master_2_tdest => axis_master_2_tdest, axis_master_2_tlast => axis_master_2_tlast, axis_master_2_irq => axis_master_2_irq, axis_slave_2_tvalid => axis_slave_2_tvalid, axis_slave_2_tready => axis_slave_2_tready, axis_slave_2_tdata => axis_slave_2_tdata, axis_slave_2_tid => axis_slave_2_tid, axis_slave_2_tlast => axis_slave_2_tlast, axis_slave_2_irq => axis_slave_2_irq, status_2_addr => status_2_addr, status_2_data => status_2_data, status_2_stb => status_2_stb, ctrl_2_addr => ctrl_2_addr, ctrl_2_data => ctrl_2_data, ctrl_2_stb => ctrl_2_stb, axis_master_3_tvalid => axis_master_3_tvalid, axis_master_3_tready => axis_master_3_tready, axis_master_3_tdata => axis_master_3_tdata, axis_master_3_tdest => axis_master_3_tdest, axis_master_3_tlast => axis_master_3_tlast, axis_master_3_irq => axis_master_3_irq, axis_slave_3_tvalid => axis_slave_3_tvalid, axis_slave_3_tready => axis_slave_3_tready, axis_slave_3_tdata => axis_slave_3_tdata, axis_slave_3_tid => axis_slave_3_tid, axis_slave_3_tlast => axis_slave_3_tlast, axis_slave_3_irq => axis_slave_3_irq, status_3_addr => status_3_addr, status_3_data => status_3_data, status_3_stb => status_3_stb, ctrl_3_addr => ctrl_3_addr, ctrl_3_data => ctrl_3_data, ctrl_3_stb => ctrl_3_stb, axis_master_4_tvalid => axis_master_4_tvalid, axis_master_4_tready => axis_master_4_tready, axis_master_4_tdata => axis_master_4_tdata, axis_master_4_tdest => axis_master_4_tdest, axis_master_4_tlast => axis_master_4_tlast, axis_master_4_irq => axis_master_4_irq, axis_slave_4_tvalid => axis_slave_4_tvalid, axis_slave_4_tready => axis_slave_4_tready, axis_slave_4_tdata => axis_slave_4_tdata, axis_slave_4_tid => axis_slave_4_tid, axis_slave_4_tlast => axis_slave_4_tlast, axis_slave_4_irq => axis_slave_4_irq, status_4_addr => status_4_addr, status_4_data => status_4_data, status_4_stb => status_4_stb, ctrl_4_addr => ctrl_4_addr, ctrl_4_data => ctrl_4_data, ctrl_4_stb => ctrl_4_stb, axis_master_5_tvalid => axis_master_5_tvalid, axis_master_5_tready => axis_master_5_tready, axis_master_5_tdata => axis_master_5_tdata, axis_master_5_tdest => axis_master_5_tdest, axis_master_5_tlast => axis_master_5_tlast, axis_master_5_irq => axis_master_5_irq, axis_slave_5_tvalid => axis_slave_5_tvalid, axis_slave_5_tready => axis_slave_5_tready, axis_slave_5_tdata => axis_slave_5_tdata, axis_slave_5_tid => axis_slave_5_tid, axis_slave_5_tlast => axis_slave_5_tlast, axis_slave_5_irq => axis_slave_5_irq, status_5_addr => status_5_addr, status_5_data => status_5_data, status_5_stb => status_5_stb, ctrl_5_addr => ctrl_5_addr, ctrl_5_data => ctrl_5_data, ctrl_5_stb => ctrl_5_stb, axis_master_6_tvalid => axis_master_6_tvalid, axis_master_6_tready => axis_master_6_tready, axis_master_6_tdata => axis_master_6_tdata, axis_master_6_tdest => axis_master_6_tdest, axis_master_6_tlast => axis_master_6_tlast, axis_master_6_irq => axis_master_6_irq, axis_slave_6_tvalid => axis_slave_6_tvalid, axis_slave_6_tready => axis_slave_6_tready, axis_slave_6_tdata => axis_slave_6_tdata, axis_slave_6_tid => axis_slave_6_tid, axis_slave_6_tlast => axis_slave_6_tlast, axis_slave_6_irq => axis_slave_6_irq, status_6_addr => status_6_addr, status_6_data => status_6_data, status_6_stb => status_6_stb, ctrl_6_addr => ctrl_6_addr, ctrl_6_data => ctrl_6_data, ctrl_6_stb => ctrl_6_stb, axis_master_7_tvalid => axis_master_7_tvalid, axis_master_7_tready => axis_master_7_tready, axis_master_7_tdata => axis_master_7_tdata, axis_master_7_tdest => axis_master_7_tdest, axis_master_7_tlast => axis_master_7_tlast, axis_master_7_irq => axis_master_7_irq, axis_slave_7_tvalid => axis_slave_7_tvalid, axis_slave_7_tready => axis_slave_7_tready, axis_slave_7_tdata => axis_slave_7_tdata, axis_slave_7_tid => axis_slave_7_tid, axis_slave_7_tlast => axis_slave_7_tlast, axis_slave_7_irq => axis_slave_7_irq, status_7_addr => status_7_addr, status_7_data => status_7_data, status_7_stb => status_7_stb, ctrl_7_addr => ctrl_7_addr, ctrl_7_data => ctrl_7_data, ctrl_7_stb => ctrl_7_stb); -- Accelerator 1 inst_usrp_ddr_intf_axis : usrp_ddr_intf_axis generic map ( DDR_CLOCK_FREQ => 100e6, BAUD => 115200) port map ( UART_TX => UART_TX, RX_DATA_CLK_N => RX_DATA_CLK_N, RX_DATA_CLK_P => RX_DATA_CLK_P, RX_DATA_N => RX_DATA_N, RX_DATA_P => RX_DATA_P, TX_DATA_N => TX_DATA_N, TX_DATA_P => TX_DATA_P, clk => clk, rst_n => rst_glb_n, status_addr => status_1_addr, status_data => status_1_data, status_stb => status_1_stb, ctrl_addr => ctrl_1_addr, ctrl_data => ctrl_1_data, ctrl_stb => ctrl_1_stb, axis_slave_tvalid => axis_slave_1_tvalid, axis_slave_tready => axis_slave_1_tready, axis_slave_tdata => axis_slave_1_tdata, axis_slave_tid => axis_slave_1_tid, axis_slave_tlast => axis_slave_1_tlast, axis_slave_irq => axis_slave_1_irq, axis_master_tvalid => axis_master_1_tvalid, axis_master_tready => axis_master_1_tready, axis_master_tdata => axis_master_1_tdata, axis_master_tdest => axis_master_1_tdest, axis_master_tlast => axis_master_1_tlast, axis_master_irq => axis_master_1_irq, rx_enable_aux => rx_enable_aux, tx_enable_aux => tx_enable_aux); rx_enable_aux <= '0'; tx_enable_aux <= threshold_exceeded OR threshold_not_exceeded; -- Accelerator 2 inst_spectrum_sense : spectrum_sense port map ( clk => clk, rst_n => rst_glb_n, status_addr => status_2_addr, status_data => status_2_data, status_stb => status_2_stb, ctrl_addr => ctrl_2_addr, ctrl_data => ctrl_2_data, ctrl_stb => ctrl_2_stb, axis_slave_tvalid => axis_slave_2_tvalid, axis_slave_tready => axis_slave_2_tready, axis_slave_tdata => axis_slave_2_tdata, axis_slave_tid => axis_slave_2_tid, axis_slave_tlast => axis_slave_2_tlast, axis_slave_irq => axis_slave_2_irq, axis_master_tvalid => axis_master_2_tvalid, axis_master_tready => axis_master_2_tready, axis_master_tdata => axis_master_2_tdata, axis_master_tdest => axis_master_2_tdest, axis_master_tlast => axis_master_2_tlast, axis_master_irq => axis_master_2_irq, threshold_not_exceeded => threshold_not_exceeded, threshold_not_exceeded_stb => threshold_not_exceeded_stb, threshold_exceeded => threshold_exceeded, threshold_exceeded_stb => threshold_exceeded_stb); -- Accelerator 3 inst_bpsk_mod : bpsk_mod port map ( clk => clk, rst_n => rst_glb_n, status_addr => status_3_addr, status_data => status_3_data, status_stb => status_3_stb, ctrl_addr => ctrl_3_addr, ctrl_data => ctrl_3_data, ctrl_stb => ctrl_3_stb, axis_slave_tvalid => axis_slave_3_tvalid, axis_slave_tready => axis_slave_3_tready, axis_slave_tdata => axis_slave_3_tdata, axis_slave_tid => axis_slave_3_tid, axis_slave_tlast => axis_slave_3_tlast, axis_slave_irq => axis_slave_3_irq, axis_master_tvalid => axis_master_3_tvalid, axis_master_tready => axis_master_3_tready, axis_master_tdata => axis_master_3_tdata, axis_master_tdest => axis_master_3_tdest, axis_master_tlast => axis_master_3_tlast, axis_master_irq => axis_master_3_irq, trigger_stb => trigger_stb); -- The output of either threshold trigger is controlled by control registers, so ORing them is -- not an issue as only one should be active at a time. trigger_stb <= threshold_exceeded_stb OR threshold_not_exceeded_stb; -- Unused Accelerators axis_slave_4_tready <= '0'; axis_slave_4_irq <= '0'; axis_master_4_tvalid <= '0'; axis_master_4_tdata <= x"0000000000000000"; axis_master_4_tdest <= "000"; axis_master_4_tlast <= '0'; axis_master_4_irq <= '0'; status_4_data <= x"00000000"; axis_slave_5_tready <= '0'; axis_slave_5_irq <= '0'; axis_master_5_tvalid <= '0'; axis_master_5_tdata <= x"0000000000000000"; axis_master_5_tdest <= "000"; axis_master_5_tlast <= '0'; axis_master_5_irq <= '0'; status_5_data <= x"00000000"; axis_slave_6_tready <= '0'; axis_slave_6_irq <= '0'; axis_master_6_tvalid <= '0'; axis_master_6_tdata <= x"0000000000000000"; axis_master_6_tdest <= "000"; axis_master_6_tlast <= '0'; axis_master_6_irq <= '0'; status_6_data <= x"00000000"; axis_slave_7_tready <= '0'; axis_slave_7_irq <= '0'; axis_master_7_tvalid <= '0'; axis_master_7_tdata <= x"0000000000000000"; axis_master_7_tdest <= "000"; axis_master_7_tlast <= '0'; axis_master_7_irq <= '0'; status_7_data <= x"00000000"; SPARE <= 'Z'; end architecture;
---------------------------------------------------------------------------------- -- Company: LARC - Escola Politecnica - University of Sao Paulo -- Engineer: Pedro Maat C. Massolino -- -- Create Date: 05/12/2012 -- Design Name: Codeword Generator 1 -- Module Name: Codeword_Generator_1 -- Project Name: McEliece QD-Goppa Encoder -- Target Devices: Any -- Tool versions: Xilinx ISE 13.3 WebPack -- -- Description: -- -- The first and only step in QD-Goppa Code encoding. -- This circuit transforms an k-bit message into a valid n-bit codeword. -- The transformation is an multiplication of a message of k-bits by the -- Generator matrix G. The Generator matrix is composed of Identity Matrix and -- another matrix A. For this reason the first k bits of the codeword are equal -- to the message, only the last n-k bits are computed. This circuit works only -- only for QD-Goppa codes, where matrix A is composed of dyadic matrices and -- can be stored only by the first row of each dyadic matrix. -- Matrix A is supposed to be stored with a word of 1 bit and each dyadic matrix row -- followed by each one, in a row-wise pattern. -- -- This circuit process one bit at time, each is more than 1 cycle. -- This circuit is inefficient and only a proof of concept for n_m version. -- -- The circuits parameters -- -- length_message : -- -- Length in bits of message size and also part of matrix size. -- -- size_message : -- -- The number of bits necessary to store the message. The ceil(log2(lenght_message)) -- -- length_codeword : -- -- Length in bits of codeword size and also part of matrix size. -- -- size_codeword : -- -- The number of bits necessary to store the codeword. The ceil(log2(length_codeword)) -- -- size_dyadic_matrix : -- -- The number of bits necessary to store one row of the dyadic matrix. -- It is also the ceil(log2(number of errors in the code)) -- -- number_dyadic_matrices : -- -- The number of dyadic matrices present in matrix A. -- -- size_number_dyadic_matrices : -- -- The number of bits necessary to store the number of dyadic matrices. -- The ceil(log2(number_dyadic_matrices)) -- -- Dependencies: -- -- VHDL-93 -- IEEE.NUMERIC_STD_ALL; -- -- controller_codeword_generator_1 Rev 1.0 -- register_nbits Rev 1.0 -- register_rst_nbits Rev 1.0 -- counter_rst_nbits Rev 1.0 -- counter_rst_set_nbits Rev 1.0 -- -- Revision: -- Revision 1.00 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity codeword_generator_1 is Generic( -- QD-GOPPA [2528, 2144, 32, 12] -- length_message : integer := 2144; size_message : integer := 12; length_codeword : integer := 2528; size_codeword : integer := 12; size_dyadic_matrix : integer := 5; number_dyadic_matrices : integer := 804; size_number_dyadic_matrices : integer := 10 -- QD-GOPPA [2816, 2048, 64, 12] -- -- length_message : integer := 2048; -- size_message : integer := 12; -- length_codeword : integer := 2816; -- size_codeword : integer := 12; -- size_dyadic_matrix : integer := 6; -- number_dyadic_matrices : integer := 384; -- size_number_dyadic_matrices : integer := 9 -- QD-GOPPA [3328, 2560, 64, 12] -- -- length_message : integer := 2560; -- size_message : integer := 12; -- length_codeword : integer := 3328; -- size_codeword : integer := 12; -- size_dyadic_matrix : integer := 6; -- number_dyadic_matrices : integer := 480; -- size_number_dyadic_matrices : integer := 9 -- QD-GOPPA [7296, 5632, 128, 13] -- -- length_message : integer := 5632; -- size_message : integer := 13; -- length_codeword : integer := 7296; -- size_codeword : integer := 13; -- size_dyadic_matrix : integer := 7; -- number_dyadic_matrices : integer := 572; -- size_number_dyadic_matrices : integer := 10 ); Port( codeword : in STD_LOGIC; matrix : in STD_LOGIC; message : in STD_LOGIC; clk : in STD_LOGIC; rst : in STD_LOGIC; new_codeword : out STD_LOGIC; write_enable_new_codeword : out STD_LOGIC; codeword_finalized : out STD_LOGIC; address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0); address_message : out STD_LOGIC_VECTOR((size_message - 1) downto 0); address_matrix : out STD_LOGIC_VECTOR((size_dyadic_matrix + size_number_dyadic_matrices - 1) downto 0) ); end codeword_generator_1; architecture Behavioral of codeword_generator_1 is component controller_codeword_generator_1 Port( clk : in STD_LOGIC; rst : in STD_LOGIC; limit_ctr_dyadic_column_q : in STD_LOGIC; limit_ctr_dyadic_row_q : in STD_LOGIC; limit_ctr_address_message_q : in STD_LOGIC; limit_ctr_address_codeword_q : in STD_LOGIC; write_enable_new_codeword : out STD_LOGIC; message_into_new_codeword : out STD_LOGIC; reg_codeword_ce : out STD_LOGIC; reg_codeword_rst : out STD_LOGIC; reg_message_ce : out STD_LOGIC; reg_matrix_ce : out STD_LOGIC; ctr_dyadic_column_ce : out STD_LOGIC; ctr_dyadic_column_rst : out STD_LOGIC; ctr_dyadic_row_ce : out STD_LOGIC; ctr_dyadic_row_rst : out STD_LOGIC; ctr_dyadic_matrices_ce : out STD_LOGIC; ctr_dyadic_matrices_rst : out STD_LOGIC; ctr_address_base_message_ce : out STD_LOGIC; ctr_address_base_message_rst : out STD_LOGIC; ctr_address_base_codeword_ce : out STD_LOGIC; ctr_address_base_codeword_rst : out STD_LOGIC; ctr_address_base_codeword_set : out STD_LOGIC; internal_codeword : out STD_LOGIC; codeword_finalized : out STD_LOGIC ); end component; component register_nbits Generic (size : integer); Port ( d : in STD_LOGIC_VECTOR ((size - 1) downto 0); clk : in STD_LOGIC; ce : in STD_LOGIC; q : out STD_LOGIC_VECTOR ((size - 1) downto 0) ); end component; component register_rst_nbits Generic (size : integer); Port ( d : in STD_LOGIC_VECTOR ((size - 1) downto 0); clk : in STD_LOGIC; ce : in STD_LOGIC; rst : in STD_LOGIC; rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0); q : out STD_LOGIC_VECTOR ((size - 1) downto 0) ); end component; component counter_rst_nbits Generic ( size : integer; increment_value : integer ); Port ( clk : in STD_LOGIC; ce : in STD_LOGIC; rst : in STD_LOGIC; rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0); q : out STD_LOGIC_VECTOR ((size - 1) downto 0) ); end component; component counter_rst_set_nbits Generic ( size : integer; increment_value : integer ); Port ( clk : in STD_LOGIC; ce : in STD_LOGIC; rst : in STD_LOGIC; set : in STD_LOGIC; rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0); set_value : in STD_LOGIC_VECTOR ((size - 1) downto 0); q : out STD_LOGIC_VECTOR ((size - 1) downto 0) ); end component; signal reg_codeword_d : STD_LOGIC; signal reg_codeword_ce : STD_LOGIC; signal reg_codeword_rst : STD_LOGIC; constant reg_codeword_rst_value : STD_LOGIC := '0'; signal reg_codeword_q : STD_LOGIC; signal reg_message_d : STD_LOGIC; signal reg_message_ce : STD_LOGIC; signal reg_message_q : STD_LOGIC; signal reg_matrix_d : STD_LOGIC; signal reg_matrix_ce : STD_LOGIC; signal reg_matrix_q : STD_LOGIC; signal ctr_dyadic_column_ce : STD_LOGIC; signal ctr_dyadic_column_rst : STD_LOGIC; constant ctr_dyadic_column_rst_value : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0) := (others => '0'); signal ctr_dyadic_column_q : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0); signal limit_ctr_dyadic_column_q : STD_LOGIC; signal ctr_dyadic_row_ce : STD_LOGIC; signal ctr_dyadic_row_rst : STD_LOGIC; constant ctr_dyadic_row_rst_value : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0) := (others => '0'); signal ctr_dyadic_row_q : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0); signal limit_ctr_dyadic_row_q : STD_LOGIC; signal ctr_dyadic_matrices_ce : STD_LOGIC; signal ctr_dyadic_matrices_rst : STD_LOGIC; constant ctr_dyadic_matrices_rst_value : STD_LOGIC_VECTOR((size_number_dyadic_matrices - 1) downto 0) := (others => '0'); signal ctr_dyadic_matrices_q : STD_LOGIC_VECTOR((size_number_dyadic_matrices - 1) downto 0); signal limit_ctr_dyadic_matrices_q : STD_LOGIC; signal ctr_address_base_message_ce : STD_LOGIC; signal ctr_address_base_message_rst : STD_LOGIC; constant ctr_address_base_message_rst_value : STD_LOGIC_VECTOR((size_message - size_dyadic_matrix - 1) downto 0) := (others => '0'); signal ctr_address_base_message_q : STD_LOGIC_VECTOR((size_message - size_dyadic_matrix - 1) downto 0); signal limit_ctr_address_message_q : STD_LOGIC; signal ctr_address_base_codeword_ce : STD_LOGIC; signal ctr_address_base_codeword_rst : STD_LOGIC; signal ctr_address_base_codeword_set : STD_LOGIC; constant ctr_address_base_codeword_rst_value : STD_LOGIC_VECTOR((size_codeword - size_dyadic_matrix - 1) downto 0) := (others => '0'); constant ctr_address_base_codeword_set_value : STD_LOGIC_VECTOR((size_codeword - size_dyadic_matrix - 1) downto 0) := std_logic_vector(to_unsigned(length_message/2**size_dyadic_matrix, size_codeword - size_dyadic_matrix)); signal ctr_address_base_codeword_q : STD_LOGIC_VECTOR((size_codeword - size_dyadic_matrix - 1) downto 0); signal limit_ctr_address_codeword_q : STD_LOGIC; signal internal_address_codeword : STD_LOGIC_VECTOR((size_codeword - 1) downto 0); signal internal_address_message : STD_LOGIC_VECTOR((size_message - 1) downto 0); signal internal_codeword : STD_LOGIC; signal internal_new_codeword : STD_LOGIC; signal message_into_new_codeword : STD_LOGIC; begin controller : controller_codeword_generator_1 Port Map( clk => clk, rst => rst, limit_ctr_dyadic_column_q => limit_ctr_dyadic_column_q, limit_ctr_dyadic_row_q => limit_ctr_dyadic_row_q, limit_ctr_address_message_q => limit_ctr_address_message_q, limit_ctr_address_codeword_q => limit_ctr_address_codeword_q, write_enable_new_codeword => write_enable_new_codeword, message_into_new_codeword => message_into_new_codeword, reg_codeword_ce => reg_codeword_ce, reg_codeword_rst => reg_codeword_rst, reg_message_ce => reg_message_ce, reg_matrix_ce => reg_matrix_ce, ctr_dyadic_column_ce => ctr_dyadic_column_ce, ctr_dyadic_column_rst => ctr_dyadic_column_rst, ctr_dyadic_row_ce => ctr_dyadic_row_ce, ctr_dyadic_row_rst => ctr_dyadic_row_rst, ctr_dyadic_matrices_ce => ctr_dyadic_matrices_ce, ctr_dyadic_matrices_rst => ctr_dyadic_matrices_rst, ctr_address_base_message_ce => ctr_address_base_message_ce, ctr_address_base_message_rst => ctr_address_base_message_rst, ctr_address_base_codeword_ce => ctr_address_base_codeword_ce, ctr_address_base_codeword_rst => ctr_address_base_codeword_rst, ctr_address_base_codeword_set => ctr_address_base_codeword_set, internal_codeword => internal_codeword, codeword_finalized => codeword_finalized ); reg_acc : register_rst_nbits Generic Map( size => 1 ) Port Map( d(0) => reg_codeword_d, clk => clk, ce => reg_codeword_ce, rst => reg_codeword_rst, rst_value(0) => reg_codeword_rst_value, q(0) => reg_codeword_q ); reg_vector : register_nbits Generic Map( size => 1 ) Port Map( d(0) => reg_message_d, clk => clk, ce => reg_message_ce, q(0) => reg_message_q ); reg_matrix : register_nbits Generic Map( size => 1 ) Port Map( d(0) => reg_matrix_d, clk => clk, ce => reg_matrix_ce, q(0) => reg_matrix_q ); ctr_dyadic_column : counter_rst_nbits Generic Map( size => size_dyadic_matrix, increment_value => 1 ) Port Map( clk => clk, ce => ctr_dyadic_column_ce, rst => ctr_dyadic_column_rst, rst_value => ctr_dyadic_column_rst_value, q => ctr_dyadic_column_q ); ctr_dyadic_row : counter_rst_nbits Generic Map( size => size_dyadic_matrix, increment_value => 1 ) Port Map( clk => clk, ce => ctr_dyadic_row_ce, rst => ctr_dyadic_row_rst, rst_value => ctr_dyadic_row_rst_value, q => ctr_dyadic_row_q ); ctr_dyadic_matrices : counter_rst_nbits Generic Map( size => size_number_dyadic_matrices, increment_value => 1 ) Port Map( clk => clk, ce => ctr_dyadic_matrices_ce, rst => ctr_dyadic_matrices_rst, rst_value => ctr_dyadic_matrices_rst_value, q => ctr_dyadic_matrices_q ); ctr_address_base_vector : counter_rst_nbits Generic Map( size => size_message - size_dyadic_matrix, increment_value => 1 ) Port Map( clk => clk, ce => ctr_address_base_message_ce, rst => ctr_address_base_message_rst, rst_value => ctr_address_base_message_rst_value, q => ctr_address_base_message_q ); ctr_address_base_acc : counter_rst_set_nbits Generic Map( size => size_codeword - size_dyadic_matrix, increment_value => 1 ) Port Map( clk => clk, ce => ctr_address_base_codeword_ce, set => ctr_address_base_codeword_set, rst => ctr_address_base_codeword_rst, set_value => ctr_address_base_codeword_set_value, rst_value => ctr_address_base_codeword_rst_value, q => ctr_address_base_codeword_q ); internal_new_codeword <= (reg_message_q and reg_matrix_q) xor reg_codeword_q; new_codeword <= reg_message_q when message_into_new_codeword = '1' else internal_new_codeword; reg_codeword_d <= internal_new_codeword when internal_codeword = '1' else codeword; reg_message_d <= message; reg_matrix_d <= matrix; internal_address_codeword <= ctr_address_base_codeword_q & ctr_dyadic_column_q; internal_address_message <= ctr_address_base_message_q & ctr_dyadic_row_q; address_codeword <= internal_address_codeword; address_message <= internal_address_message; address_matrix <= ctr_dyadic_matrices_q & (ctr_dyadic_column_q xor ctr_dyadic_row_q); limit_ctr_dyadic_column_q <= '1' when ctr_dyadic_column_q = std_logic_vector(to_unsigned(2**size_dyadic_matrix - 1, ctr_dyadic_column_q'length)) else '0'; limit_ctr_dyadic_row_q <= '1' when ctr_dyadic_row_q = std_logic_vector(to_unsigned(2**size_dyadic_matrix - 1, ctr_dyadic_row_q'length)) else '0'; limit_ctr_address_message_q <= '1' when internal_address_message = std_logic_vector(to_unsigned(length_message - 1, internal_address_message'length)) else '0'; limit_ctr_address_codeword_q <= '1' when internal_address_codeword = std_logic_vector(to_unsigned(length_codeword - 1, internal_address_codeword'length)) else '0'; end Behavioral;
-- NEED RESULT: ARCH00698: Formal parameters of mode in may be left unspecified in association list if they have default expressions passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00698 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.3.3.2 (7) -- -- DESIGN UNIT ORDERING: -- -- ENT00698(ARCH00698) -- ENT00698_Test_Bench(ARCH00698_Test_Bench) -- -- REVISION HISTORY: -- -- 09-SEP-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; entity ENT00698 is port ( p_integer : integer := 5 ; p_boolean : boolean := true ; p_st_arr3 : st_arr3 := c_st_arr3_1 ) ; end ENT00698 ; -- architecture ARCH00698 of ENT00698 is procedure p1 ( pc_integer : integer := -4 ; pc_boolean : boolean := false ; pc_st_arr3 : st_arr3 := c_st_arr3_2 ; pv_integer : integer := 3 ; pv_boolean : boolean := true ; pv_st_arr3 : st_arr3 := c_st_arr3_1 ; signal ps_integer : integer ; signal ps_boolean : boolean ; signal ps_st_arr3 : st_arr3 ) is variable correct : boolean := true ; begin correct := correct and pc_integer = -4 ; correct := correct and not pc_boolean ; correct := correct and pc_st_arr3 = c_st_arr3_2 ; correct := correct and pv_integer = 0 ; correct := correct and pv_boolean ; correct := correct and pv_st_arr3 = c_st_arr3_1 ; correct := correct and ps_integer = 5 ; correct := correct and ps_boolean ; correct := correct and ps_st_arr3 = c_st_arr3_1 ; test_report ( "ARCH00698" , "Formal parameters of mode in may be left unspecified" & " in association list if they have default expressions" , correct ) ; end p1 ; begin process variable v_integer : integer := 0 ; variable v_boolean : boolean := true ; variable v_st_arr3 : st_arr3 := c_st_arr3_1 ; begin p1 ( ps_integer => p_integer , ps_boolean => p_boolean , ps_st_arr3 => p_st_arr3 , pv_integer => 0 ) ; wait ; end process ; end ARCH00698 ; -- use WORK.STANDARD_TYPES.all ; entity ENT00698_Test_Bench is end ENT00698_Test_Bench ; -- architecture ARCH00698_Test_Bench of ENT00698_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.ENT00698 ( ARCH00698 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00698_Test_Bench ; --
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.dsp_cores_pkg.all; entity position_calc is generic ( g_pipeline_regs : integer := 8 ); port( adc_ch0_i : in std_logic_vector(15 downto 0); adc_ch1_i : in std_logic_vector(15 downto 0); adc_ch2_i : in std_logic_vector(15 downto 0); adc_ch3_i : in std_logic_vector(15 downto 0); clk : in std_logic; -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz) clr : in std_logic; -- clear signal del_sig_div_fofb_thres_i : in std_logic_vector(25 downto 0); del_sig_div_monit_thres_i : in std_logic_vector(25 downto 0); del_sig_div_tbt_thres_i : in std_logic_vector(25 downto 0); ksum_i : in std_logic_vector(24 downto 0); kx_i : in std_logic_vector(24 downto 0); ky_i : in std_logic_vector(24 downto 0); dds_config_valid_ch0_i : in std_logic; dds_config_valid_ch1_i : in std_logic; dds_config_valid_ch2_i : in std_logic; dds_config_valid_ch3_i : in std_logic; dds_pinc_ch0_i : in std_logic_vector(29 downto 0); dds_pinc_ch1_i : in std_logic_vector(29 downto 0); dds_pinc_ch2_i : in std_logic_vector(29 downto 0); dds_pinc_ch3_i : in std_logic_vector(29 downto 0); dds_poff_ch0_i : in std_logic_vector(29 downto 0); dds_poff_ch1_i : in std_logic_vector(29 downto 0); dds_poff_ch2_i : in std_logic_vector(29 downto 0); dds_poff_ch3_i : in std_logic_vector(29 downto 0); adc_ch0_dbg_data_o : out std_logic_vector(15 downto 0); adc_ch1_dbg_data_o : out std_logic_vector(15 downto 0); adc_ch2_dbg_data_o : out std_logic_vector(15 downto 0); adc_ch3_dbg_data_o : out std_logic_vector(15 downto 0); bpf_ch0_o : out std_logic_vector(23 downto 0); bpf_ch1_o : out std_logic_vector(23 downto 0); bpf_ch2_o : out std_logic_vector(23 downto 0); bpf_ch3_o : out std_logic_vector(23 downto 0); mix_ch0_i_o : out std_logic_vector(23 downto 0); mix_ch0_q_o : out std_logic_vector(23 downto 0); mix_ch1_i_o : out std_logic_vector(23 downto 0); mix_ch1_q_o : out std_logic_vector(23 downto 0); mix_ch2_i_o : out std_logic_vector(23 downto 0); mix_ch2_q_o : out std_logic_vector(23 downto 0); mix_ch3_i_o : out std_logic_vector(23 downto 0); mix_ch3_q_o : out std_logic_vector(23 downto 0); tbt_decim_ch0_i_o : out std_logic_vector(23 downto 0); tbt_decim_ch0_q_o : out std_logic_vector(23 downto 0); tbt_decim_ch1_i_o : out std_logic_vector(23 downto 0); tbt_decim_ch1_q_o : out std_logic_vector(23 downto 0); tbt_decim_ch2_i_o : out std_logic_vector(23 downto 0); tbt_decim_ch2_q_o : out std_logic_vector(23 downto 0); tbt_decim_ch3_i_o : out std_logic_vector(23 downto 0); tbt_decim_ch3_q_o : out std_logic_vector(23 downto 0); tbt_decim_q_ch01_incorrect_o : out std_logic; tbt_decim_q_ch23_incorrect_o : out std_logic; tbt_amp_ch0_o : out std_logic_vector(23 downto 0); tbt_amp_ch1_o : out std_logic_vector(23 downto 0); tbt_amp_ch2_o : out std_logic_vector(23 downto 0); tbt_amp_ch3_o : out std_logic_vector(23 downto 0); tbt_pha_ch0_o : out std_logic_vector(23 downto 0); tbt_pha_ch1_o : out std_logic_vector(23 downto 0); tbt_pha_ch2_o : out std_logic_vector(23 downto 0); tbt_pha_ch3_o : out std_logic_vector(23 downto 0); fofb_decim_ch0_i_o : out std_logic_vector(23 downto 0); fofb_decim_ch0_q_o : out std_logic_vector(23 downto 0); fofb_decim_ch1_i_o : out std_logic_vector(23 downto 0); fofb_decim_ch1_q_o : out std_logic_vector(23 downto 0); fofb_decim_ch2_i_o : out std_logic_vector(23 downto 0); fofb_decim_ch2_q_o : out std_logic_vector(23 downto 0); fofb_decim_ch3_i_o : out std_logic_vector(23 downto 0); fofb_decim_ch3_q_o : out std_logic_vector(23 downto 0); fofb_decim_q_01_missing_o : out std_logic; fofb_decim_q_23_missing_o : out std_logic; fofb_amp_ch0_o : out std_logic_vector(23 downto 0); fofb_amp_ch1_o : out std_logic_vector(23 downto 0); fofb_amp_ch2_o : out std_logic_vector(23 downto 0); fofb_amp_ch3_o : out std_logic_vector(23 downto 0); fofb_pha_ch0_o : out std_logic_vector(23 downto 0); fofb_pha_ch1_o : out std_logic_vector(23 downto 0); fofb_pha_ch2_o : out std_logic_vector(23 downto 0); fofb_pha_ch3_o : out std_logic_vector(23 downto 0); monit_amp_ch0_o : out std_logic_vector(23 downto 0); monit_amp_ch1_o : out std_logic_vector(23 downto 0); monit_amp_ch2_o : out std_logic_vector(23 downto 0); monit_amp_ch3_o : out std_logic_vector(23 downto 0); monit_cic_unexpected_o : out std_logic; monit_cfir_incorrect_o : out std_logic; monit_pfir_incorrect_o : out std_logic; x_tbt_o : out std_logic_vector(25 downto 0); x_tbt_valid_o : out std_logic; y_tbt_o : out std_logic_vector(25 downto 0); y_tbt_valid_o : out std_logic; q_tbt_o : out std_logic_vector(25 downto 0); q_tbt_valid_o : out std_logic; sum_tbt_o : out std_logic_vector(25 downto 0); sum_tbt_valid_o : out std_logic; x_fofb_o : out std_logic_vector(25 downto 0); x_fofb_valid_o : out std_logic; y_fofb_o : out std_logic_vector(25 downto 0); y_fofb_valid_o : out std_logic; q_fofb_o : out std_logic_vector(25 downto 0); q_fofb_valid_o : out std_logic; sum_fofb_o : out std_logic_vector(25 downto 0); sum_fofb_valid_o : out std_logic; x_monit_o : out std_logic_vector(25 downto 0); x_monit_valid_o : out std_logic; y_monit_o : out std_logic_vector(25 downto 0); y_monit_valid_o : out std_logic; q_monit_o : out std_logic_vector(25 downto 0); q_monit_valid_o : out std_logic; sum_monit_o : out std_logic_vector(25 downto 0); sum_monit_valid_o : out std_logic; x_monit_1_o : out std_logic_vector(25 downto 0); x_monit_1_valid_o : out std_logic; y_monit_1_o : out std_logic_vector(25 downto 0); y_monit_1_valid_o : out std_logic; q_monit_1_o : out std_logic_vector(25 downto 0); q_monit_1_valid_o : out std_logic; sum_monit_1_o : out std_logic_vector(25 downto 0); sum_monit_1_valid_o : out std_logic; monit_pos_1_incorrect_o : out std_logic; -- Clock drivers for various rates clk_ce_1_o : out std_logic; clk_ce_1112_o : out std_logic; clk_ce_1390000_o : out std_logic; clk_ce_2_o : out std_logic; clk_ce_2224_o : out std_logic; clk_ce_22240000_o : out std_logic; clk_ce_222400000_o : out std_logic; clk_ce_2780000_o : out std_logic; clk_ce_35_o : out std_logic; clk_ce_5000_o : out std_logic; clk_ce_556_o : out std_logic; clk_ce_5560000_o : out std_logic; clk_ce_70_o : out std_logic ); end position_calc; architecture rtl of position_calc is signal ce : std_logic; signal ce_clr : std_logic; signal clk_ce_1 : std_logic; signal clk_ce_1112 : std_logic; signal clk_ce_1390000 : std_logic; signal clk_ce_2 : std_logic; signal clk_ce_2224 : std_logic; signal clk_ce_22240000 : std_logic; signal clk_ce_2780000 : std_logic; signal clk_ce_35 : std_logic; signal clk_ce_5000 : std_logic; signal clk_ce_556 : std_logic; signal clk_ce_5560000 : std_logic; signal clk_ce_70 : std_logic; begin ce <= '1'; --ce_clr <= '0'; ce_clr <= clr; -- FIXME: fix CE names. They don't match the correct ones! cmp_default_clock_driver : default_clock_driver generic map( pipeline_regs => g_pipeline_regs ) port map( sysce => ce, sysce_clr => ce_clr, sysclk => clk, ce_1 => clk_ce_1_o, ce_10000 => open, ce_1120 => clk_ce_1112_o, ce_1400000 => clk_ce_1390000_o, ce_2 => clk_ce_2_o, ce_2240 => clk_ce_2224_o, ce_22400000 => clk_ce_22240000_o, ce_224000000 => clk_ce_222400000_o, ce_2500 => open, ce_2800000 => clk_ce_2780000_o, ce_35 => clk_ce_35_o, ce_4480 => open, ce_44800000 => open, ce_5000 => clk_ce_5000_o, ce_560 => clk_ce_556_o, ce_5600000 => clk_ce_5560000_o, ce_56000000 => open, ce_70 => clk_ce_70_o, ce_logic_1 => open, ce_logic_1400000 => open, ce_logic_2240 => open, ce_logic_22400000 => open, ce_logic_2800000 => open, ce_logic_560 => open, ce_logic_5600000 => open, ce_logic_70 => open, clk_1 => open, clk_10000 => open, clk_1120 => open, clk_1400000 => open, clk_2 => open, clk_2240 => open, clk_22400000 => open, clk_224000000 => open, clk_2500 => open, clk_2800000 => open, clk_35 => open, clk_4480 => open, clk_44800000 => open, clk_5000 => open, clk_560 => open, clk_5600000 => open, clk_56000000 => open, clk_70 => open ); cmp_ddc_bpm_476_066_cw : ddc_bpm_476_066_cw generic map ( pipeline_regs => g_pipeline_regs ) port map ( adc_ch0_i => adc_ch0_i, adc_ch1_i => adc_ch1_i, adc_ch2_i => adc_ch2_i, adc_ch3_i => adc_ch3_i, ce => ce, ce_clr => ce_clr, clk => clk, del_sig_div_fofb_thres_i => del_sig_div_fofb_thres_i, del_sig_div_monit_thres_i => del_sig_div_monit_thres_i, del_sig_div_tbt_thres_i => del_sig_div_tbt_thres_i, ksum_i => ksum_i, kx_i => kx_i, ky_i => ky_i, dds_config_valid_ch0_i => dds_config_valid_ch0_i, dds_config_valid_ch1_i => dds_config_valid_ch1_i, dds_config_valid_ch2_i => dds_config_valid_ch2_i, dds_config_valid_ch3_i => dds_config_valid_ch3_i, dds_pinc_ch0_i => dds_pinc_ch0_i, dds_pinc_ch1_i => dds_pinc_ch1_i, dds_pinc_ch2_i => dds_pinc_ch2_i, dds_pinc_ch3_i => dds_pinc_ch3_i, dds_poff_ch0_i => dds_poff_ch0_i, dds_poff_ch1_i => dds_poff_ch1_i, dds_poff_ch2_i => dds_poff_ch2_i, dds_poff_ch3_i => dds_poff_ch3_i, adc_ch0_dbg_data_o => adc_ch0_dbg_data_o, adc_ch1_dbg_data_o => adc_ch1_dbg_data_o, adc_ch2_dbg_data_o => adc_ch2_dbg_data_o, adc_ch3_dbg_data_o => adc_ch3_dbg_data_o, bpf_ch0_o => bpf_ch0_o, bpf_ch1_o => bpf_ch1_o, bpf_ch2_o => bpf_ch2_o, bpf_ch3_o => bpf_ch3_o, mix_ch0_i_o => mix_ch0_i_o, mix_ch0_q_o => mix_ch0_q_o, mix_ch1_i_o => mix_ch1_i_o, mix_ch1_q_o => mix_ch1_q_o, mix_ch2_i_o => mix_ch2_i_o, mix_ch2_q_o => mix_ch2_q_o, mix_ch3_i_o => mix_ch3_i_o, mix_ch3_q_o => mix_ch3_q_o, tbt_decim_ch0_i_o => tbt_decim_ch0_i_o, tbt_decim_ch0_q_o => tbt_decim_ch0_q_o, tbt_decim_ch1_i_o => tbt_decim_ch1_i_o, tbt_decim_ch1_q_o => tbt_decim_ch1_q_o, tbt_decim_ch2_i_o => tbt_decim_ch2_i_o, tbt_decim_ch2_q_o => tbt_decim_ch2_q_o, tbt_decim_ch3_i_o => tbt_decim_ch3_i_o, tbt_decim_ch3_q_o => tbt_decim_ch3_q_o, tbt_decim_ch01_incorrect_o => tbt_decim_q_ch01_incorrect_o, tbt_decim_ch23_incorrect_o => tbt_decim_q_ch23_incorrect_o, tbt_amp_ch0_o => tbt_amp_ch0_o, tbt_amp_ch1_o => tbt_amp_ch1_o, tbt_amp_ch2_o => tbt_amp_ch2_o, tbt_amp_ch3_o => tbt_amp_ch3_o, tbt_pha_ch0_o => tbt_pha_ch0_o, tbt_pha_ch1_o => tbt_pha_ch1_o, tbt_pha_ch2_o => tbt_pha_ch2_o, tbt_pha_ch3_o => tbt_pha_ch3_o, fofb_decim_ch0_i_o => fofb_decim_ch0_i_o, fofb_decim_ch0_q_o => fofb_decim_ch0_q_o, fofb_decim_ch1_i_o => fofb_decim_ch1_i_o, fofb_decim_ch1_q_o => fofb_decim_ch1_q_o, fofb_decim_ch2_i_o => fofb_decim_ch2_i_o, fofb_decim_ch2_q_o => fofb_decim_ch2_q_o, fofb_decim_ch3_i_o => fofb_decim_ch3_i_o, fofb_decim_ch3_q_o => fofb_decim_ch3_q_o, cic_fofb_q_01_missing_o => fofb_decim_q_01_missing_o, cic_fofb_q_23_missing_o => fofb_decim_q_23_missing_o, fofb_amp_ch0_o => fofb_amp_ch0_o, fofb_amp_ch1_o => fofb_amp_ch1_o, fofb_amp_ch2_o => fofb_amp_ch2_o, fofb_amp_ch3_o => fofb_amp_ch3_o, fofb_pha_ch0_o => fofb_pha_ch0_o, fofb_pha_ch1_o => fofb_pha_ch1_o, fofb_pha_ch2_o => fofb_pha_ch2_o, fofb_pha_ch3_o => fofb_pha_ch3_o, monit_amp_ch0_o => monit_amp_ch0_o, monit_amp_ch1_o => monit_amp_ch1_o, monit_amp_ch2_o => monit_amp_ch2_o, monit_amp_ch3_o => monit_amp_ch3_o, monit_cic_unexpected_o => monit_cic_unexpected_o, monit_cfir_incorrect_o => monit_cfir_incorrect_o, monit_pfir_incorrect_o => monit_pfir_incorrect_o, x_tbt_o => x_tbt_o, x_tbt_valid_o => x_tbt_valid_o, y_tbt_o => y_tbt_o, y_tbt_valid_o => y_tbt_valid_o, q_tbt_o => q_tbt_o, q_tbt_valid_o => q_tbt_valid_o, sum_tbt_o => sum_tbt_o, sum_tbt_valid_o => sum_tbt_valid_o, x_fofb_o => x_fofb_o, x_fofb_valid_o => x_fofb_valid_o, y_fofb_o => y_fofb_o, y_fofb_valid_o => y_fofb_valid_o, q_fofb_o => q_fofb_o, q_fofb_valid_o => q_fofb_valid_o, sum_fofb_o => sum_fofb_o, sum_fofb_valid_o => sum_fofb_valid_o, x_monit_o => x_monit_o, x_monit_valid_o => x_monit_valid_o, y_monit_o => y_monit_o, y_monit_valid_o => y_monit_valid_o, q_monit_o => q_monit_o, q_monit_valid_o => q_monit_valid_o, sum_monit_o => sum_monit_o, sum_monit_valid_o => sum_monit_valid_o, x_monit_1_o => x_monit_1_o, x_monit_1_valid_o => x_monit_1_valid_o, y_monit_1_o => y_monit_1_o, y_monit_1_valid_o => y_monit_1_valid_o, q_monit_1_o => q_monit_1_o, q_monit_1_valid_o => q_monit_1_valid_o, sum_monit_1_o => sum_monit_1_o, sum_monit_1_valid_o => sum_monit_1_valid_o, monit_pos_1_incorrect_o => monit_pos_1_incorrect_o ); end rtl;
-- -- SineTable.vhd -- -- Copyright (c) 2006 Mitsutaka Okazaki (brezza@pokipoki.org) -- All rights reserved. -- -- Redistribution and use of this source code or any derivative works, are -- permitted provided that the following conditions are met: -- -- 1. Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- 3. Redistributions may not be sold, nor may they be used in a commercial -- product or activity without specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; -- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR -- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- -- -- modified by t.hara -- -- ---------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; -- conv_integer() entity SineTable is port ( clk : in std_logic; clkena : in std_logic; wf : in std_logic; addr : in std_logic_vector( 17 downto 0 ); -- ®”•” 9bit, ¬”•” 9bit data : out std_logic_vector( 13 downto 0 ) -- ®”•” 8bit, ¬”•” 6bit ); end SineTable; architecture rtl of sinetable is type sin_type is array (0 to 127) of std_logic_vector( 10 downto 0 ); -- ®”•” 7bit, ¬”•” 4bit constant sin_data : sin_type := ( "11111111111", "11001010000", "10101010001", "10010111100", "10001010011", "10000000001", "01110111110", "01110000101", "01101010101", "01100101001", "01100000011", "01011100000", "01011000000", "01010100011", "01010001000", "01001101111", "01001011000", "01001000010", "01000101101", "01000011010", "01000000111", "00111110110", "00111100101", "00111010101", "00111000110", "00110110111", "00110101001", "00110011100", "00110001111", "00110000011", "00101110111", "00101101011", "00101100000", "00101010110", "00101001011", "00101000001", "00100111000", "00100101110", "00100100101", "00100011100", "00100010100", "00100001011", "00100000011", "00011111011", "00011110100", "00011101100", "00011100101", "00011011110", "00011010111", "00011010001", "00011001010", "00011000100", "00010111110", "00010111000", "00010110010", "00010101100", "00010100111", "00010100001", "00010011100", "00010010111", "00010010010", "00010001101", "00010001000", "00010000011", "00001111111", "00001111010", "00001110110", "00001110010", "00001101110", "00001101010", "00001100110", "00001100010", "00001011110", "00001011010", "00001010111", "00001010011", "00001010000", "00001001101", "00001001001", "00001000110", "00001000011", "00001000000", "00000111101", "00000111011", "00000111000", "00000110101", "00000110011", "00000110000", "00000101110", "00000101011", "00000101001", "00000100111", "00000100101", "00000100010", "00000100000", "00000011110", "00000011101", "00000011011", "00000011001", "00000010111", "00000010110", "00000010100", "00000010011", "00000010001", "00000010000", "00000001110", "00000001101", "00000001100", "00000001011", "00000001010", "00000001001", "00000001000", "00000000111", "00000000110", "00000000101", "00000000100", "00000000011", "00000000011", "00000000010", "00000000010", "00000000001", "00000000001", "00000000000", "00000000000", "00000000000", "00000000000", "00000000000", "00000000000" ); signal ff_data0 : std_logic_vector( 10 downto 0 ); -- •„†ƒiƒV®”•” 7bit, ¬”•” 4bit signal ff_data1 : std_logic_vector( 10 downto 0 ); -- •„†ƒiƒV®”•” 7bit, ¬”•” 4bit signal w_wf : std_logic_vector( 13 downto 0 ); signal w_xor : std_logic_vector( 6 downto 0 ); signal w_addr0 : std_logic_vector( 6 downto 0 ); signal w_addr1 : std_logic_vector( 6 downto 0 ); signal w_xaddr : std_logic_vector( 6 downto 0 ); signal ff_sign : std_logic; signal ff_wf : std_logic; signal ff_weight : std_logic_vector( 8 downto 0 ); signal w_sub : std_logic_vector( 11 downto 0 ); -- •„†•t‚«®”•” 8bit, ¬”•” 4bit signal w_mul : std_logic_vector( 13 downto 0 ); -- •„†•t‚«®”•” 8bit, ¬”•” 6bit signal w_inter : std_logic_vector( 13 downto 0 ); signal ff_data : std_logic_vector( 13 downto 0 ); begin w_xor <= (others => addr(16)); w_xaddr <= addr( 15 downto 9 ) xor w_xor; w_addr0 <= w_xaddr; w_addr1 <= "1111111" xor w_xor when(addr( 15 downto 9 ) = "1111111" )else -- ”gŒ`‚ªzŠÂ‚·‚é•”•ª‚̑Ώˆ (addr( 15 downto 9 ) + 1) xor w_xor; -- ”gŒ`ƒƒ‚ƒŠ process( clk ) begin if( clk'event and clk = '1' )then if( clkena = '1' )then ff_data0 <= sin_data( conv_integer( w_addr0 ) ); ff_data1 <= sin_data( conv_integer( w_addr1 ) ); end if; end if; end process; -- Cüî•ñ‚Ì’x‰„i”gŒ`ƒƒ‚ƒŠ‚̓ǂݏo‚µ’x‰„‚É‚ ‚킹‚éj process( clk ) begin if( clk'event and clk = '1' )then if( clkena = '1' )then ff_sign <= addr(17); ff_wf <= wf and addr(17); ff_weight <= addr( 8 downto 0 ); end if; end if; end process; -- •âŠÔ (¦•„†‚ð‚Ü‚½‚ª‚éêŠ‚Å‚Í 0 ‚É‚È‚é‚©‚ç ff_sign ‚Í‹C‚É‚µ‚È‚¢j -- o = i0 * (1 - k) + i1 * w = i0 - w * i0 + w * i1 = i0 + w * (i1 - i0) w_sub <= ('0' & ff_data1) - ('0' & ff_data0); u_interpolate_mul: entity work.InterpolateMul port map ( i0 => ff_weight, i1 => w_sub, o => w_mul ); -- ‰ºˆÊ 6bit i¬”•”j‚ð‰‰ŽZ¸“xˆÛŽ‚Ì‚½‚ß‚ÉŽc‚· w_inter <= (ff_data0 & "00") + w_mul; -- "00" ‚ÍŒ…‚ ‚킹 w_wf <= (others => ff_wf); process( clk ) begin if( clk'event and clk = '1' )then if( clkena = '1' )then -- •âŠÔ‰‰ŽZ‚ÌŒ‹‰Ê‚ð‚¢‚Á‚½‚ñ FF ‚É“ü‚ê‚ĉ‰ŽZ’x‰„‚ð‹zŽû ff_data <= (ff_sign & w_inter(12 downto 0)) or w_wf; end if; end if; end process; data <= ff_data; -------------------------------------------------------------------------- -- addr X addr“ü—Í X -- w_addr0 X Šm’è X -- w_addr1 X Šm’è X -- ff_data0 X Šm’è X -- ff_data1 X Šm’è X -- ff_sign X Šm’è X -- ff_wf X Šm’è X -- ff_weight X Šm’è X -- w_sub X Šm’è X -- w_mul X Šm’è X -- w_inter X Šm’è X -- w_wf X Šm’è X -- ff_data X Šm’è X -- data X Šm’è X -- Operator -- stage X 01 X 10 X 11 X 00 X -- -- Operator ‚́Astage = 01 ‚Ì‚Æ‚«‚É“Š“ü‚µ‚½“ü—Í’l‚ÉŠî‚­o—͂𓾂éê‡‚É -- stage = 11 ‚Ŏ󂯎æ‚ç‚È‚¯‚ê‚΂Ȃç‚È‚¢B -- -- ƒAƒhƒŒƒXŽw’肳‚ê‚Ä‚©‚çA‚»‚ê‚ɑΉž‚·‚é’l‚ª“¾‚ç‚ê‚é‚Ü‚Å 2cycle ‚Ì’x‰„ -- end architecture;
architecture RTL of FIFO is function func1 return integer; pure function func1 return integer; impure function func1 return integer; function func1 return integer is begin end function func1; -- Violations follow function func1 return integer; function func1 return integer; pure function func1 return integer; pure function func1 return integer; impure function func1 return integer; impure function func1 return integer; begin end architecture RTL;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity RAM is port ( clock : in std_logic; write_enable : in std_logic; address : in std_logic_vector; data_in : in std_logic_vector; data_out : out std_logic_vector ); end entity RAM; architecture behavioural of RAM is type memory is array(integer range 0 to (2**address'length-1)) of std_logic_vector(data_in'range); signal storage : memory := (others => (others => '0')); begin process(clock) begin if rising_edge(clock) then data_out <= storage(to_integer(unsigned(address))); if write_enable = '1' then storage(to_integer(unsigned(address))) <= data_in; end if; end if; end process; end behavioural;
------------------------------------------------------------------------------- -- epc_core.vhd - entity/architecture pair ------------------------------------------------------------------------------- -- ************************************************************************ -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This file contains proprietary and confidential information of ** -- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** -- ** from Xilinx, and may be used, copied and/or disclosed only ** -- ** pursuant to the terms of a valid license agreement with Xilinx. ** -- ** ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** -- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** -- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** -- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** -- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** -- ** does not warrant that functions included in the Materials will ** -- ** meet the requirements of Licensee, or that the operation of the ** -- ** Materials will be uninterrupted or error-free, or that defects ** -- ** in the Materials will be corrected. Furthermore, Xilinx does ** -- ** not warrant or make any representations regarding use, or the ** -- ** results of the use, of the Materials in terms of correctness, ** -- ** accuracy, reliability or otherwise. ** -- ** ** -- ** Xilinx products are not designed or intended to be fail-safe, ** -- ** or for use in any application requiring fail-safe performance, ** -- ** such as life-support or safety devices or systems, Class III ** -- ** medical devices, nuclear facilities, applications related to ** -- ** the deployment of airbags, or any other applications that could ** -- ** lead to death, personal injury or severe property or ** -- ** environmental damage (individually and collectively, "critical ** -- ** applications"). Customer assumes the sole risk and liability ** -- ** of any use of Xilinx products in critical applications, ** -- ** subject only to applicable laws and regulations governing ** -- ** limitations on product liability. ** -- ** ** -- ** Copyright 2005, 2006, 2008, 2009 Xilinx, Inc. ** -- ** All rights reserved. ** -- ** ** -- ** This disclaimer and copyright notice must be retained as part ** -- ** of this file at all times. ** -- ************************************************************************ -- ------------------------------------------------------------------------------- -- File : epc_core.vhd -- Company : Xilinx -- Version : v1.00.a -- Description : External Peripheral Controller for AXI epc core interface -- Standard : VHDL-93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Structure: -- axi_epc.vhd -- -axi_lite_ipif -- -epc_core.vhd -- -ipic_if_decode.vhd -- -sync_cntl.vhd -- -async_cntl.vhd -- -- async_counters.vhd -- -- async_statemachine.vhd -- -address_gen.vhd -- -data_steer.vhd -- -access_mux.vhd ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Author : VB -- History : -- -- VB 08-24-2010 -- v2_0 version for AXI -- ^^^^^^ -- The core updated for AXI based on xps_epc_v1_02_a -- ~~~~~~ ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.conv_std_logic_vector; library axi_lite_ipif_v3_0; use axi_lite_ipif_v3_0.ipif_pkg.INTEGER_ARRAY_TYPE; library axi_epc_v2_0; ------------------------------------------------------------------------------- -- Definition of Generics : -- ------------------------------------------------------------------------------- -- C_SPLB_CLK_PERIOD_PS - The clock period of PLB Clock in picoseconds -- C_SPLB_AWIDTH - Address width of PLB BUS. -- C_SPLB_DWIDTH - Data width of PLB BUS. -- C_FAMILY - FPGA Family for which the external peripheral -- controller is targeted -- C_NUM_PERIPHERALS - Number of external devices connected to XPS EPC -- C_PRH_MAX_AWIDTH - Maximum of address bus width of all peripherals -- C_PRH_MAX_DWIDTH - Maximum of data bus width of all peripherals -- C_PRH_MAX_ADWIDTH - Maximum of data bus width of all peripherals -- and address bus width of peripherals employing -- multiplexed address/data bus -- C_PRH_CLK_SUPPORT - Indication of whether the synchronous interface -- operates on peripheral clock or on XPSclock -- C_PRH_BURST_SUPPORT - Indicates if the XPS EPC supports burst -- C_PRH(0:3)_FIFO_ACCESS - Indicates if the support for accessing FIFO -- like structure within external device is -- required -- C_PRH(0:3)_FIFO_OFFSET - Byte offset of FIFO from the base address -- assigned to peripheral -- C_PRH(0:3)_AWIDTH - External peripheral (0:3) address bus width -- C_PRH(0:3)_DWIDTH - External peripheral (0:3) data bus width -- C_PRH(0:3)_DWIDTH_MATCH - Indication of whether external peripheral (0:3) -- supports multiple access cycle on the -- peripheral interface for a single XPScycle -- when the peripheral data bus width is less than -- that of XPSbus data width -- C_PRH(0:3)_SYNC - Indicates if the external device (0:3) uses -- synchronous or asynchronous interface -- C_PRH(0:3)_BUS_MULTIPLEX - Indicates if the external device (0:3) uses a -- multiplexed or non-multiplexed device -- C_PRH(0:3)_ADDR_TSU - External device (0:3) address setup time with -- respect to rising edge of address strobe -- (multiplexed address and data bus) or falling -- edge of read/write signal (non-multiplexed -- address/data bus) -- C_PRH(0:3)_ADDR_TH - External device (0:3) address hold time with -- respect to rising edge of address strobe -- (multiplexed address and data bus) or rising -- edge of read/write signal (non-multiplexed -- address/data bus) -- C_PRH(0:3)_ADS_WIDTH - Minimum pulse width of address strobe -- C_PRH(0:3)_CSN_TSU - External device (0:3) chip select setup time -- with respect to falling edge of read/write -- signal -- C_PRH(0:3)_CSN_TH - External device (0:3) chip select hold time with -- respect to rising edge of read/write signal -- C_PRH(0:3)_WRN_WIDTH - External device (0:3) write signal minimum -- pulse width -- C_PRH(0:3)_WR_CYCLE - External device (0:3) write cycle time -- C_PRH(0:3)_DATA_TSU - External device (0:3) data bus setup with -- respect to rising edge of write signal -- C_PRH(0:3)_DATA_TH - External device (0:3) data bus hold with -- respect to rising edge of write signal -- C_PRH(0:3)_RDN_WIDTH - External device (0:3) read signal minimum -- pulse width -- C_PRH(0:3)_RD_CYCLE - External device (0:3) read cycle time -- C_PRH(0:3)_DATA_TOUT - External device (0:3) data bus validity with -- respect to falling edge of read signal -- C_PRH(0:3)_DATA_TINV - External device (0:3) data bus high impedence -- with respect to rising edge of read signal -- C_PRH(0:3)_RDY_TOUT - External device (0:3) device ready validity from -- falling edge of read/write signal -- C_PRH(0:3)_RDY_WIDTH - Maximimum wait period for external device (0:3) -- ready signal assertion -- LOCAL_CLK_PERIOD_PS - The clock period of operating clock for -- synchronous interface in picoseconds -- MAX_PERIPHERALS - Maximum number of peripherals supported by the -- external peripheral controller -- PRH(0:3)_FIFO_ADDRESS - The address of external peripheral device FIFO ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Ports -- ------------------------------------------------------------------------------- ---------------------------------------- -- IPIC INTERFACE ---------------------------------------- -- Bus2IP_Clk - IPIC clock -- Bus2IP_Rst - IPIC reset -- Bus2IP_CS - IPIC chip select signals -- Bus2IP_RdCE - IPIC read transaction chip enables -- Bus2IP_WrCE - IPIC write transaction chip enables -- Bus2IP_Addr - IPIC address -- Bus2IP_RNW - IPIC read/write indication -- Bus2IP_BE - IPIC byte enables -- Bus2IP_Data - IPIC write data -- IP2Bus_Data - Read data from IP to IPIC interface -- IP2Bus_WrAck - Write Data acknowledgment from IP to IPIC interface -- IP2Bus_RdAck - Read Data acknowledgment from IP to IPIC interface -- IP2Bus_Error - Error indication from IP to IPIC interface ---------------------------------------- -- PERIPHERAL INTERFACE ---------------------------------------- -- Local_Clk - Operational clock for peripheral interface -- Local_Rst - Reset for peripheral interface -- PRH_CS_n - Peripheral interface chip select -- PRH_Addr - Peripheral interface address bus -- PRH_ADS - Peripheral interface address strobe -- PRH_BE - Peripheral interface byte enables -- PRH_RNW - Peripheral interface read/write control for -- synchronous interface -- PRH_Rd_n - Peripheral interface read strobe for asynchronous -- interface -- PRH_Wr_n - Peripheral interface write strobe for asynchronous -- interface -- PRH_Burst - Peripheral interface burst indication signal -- PRH_Rdy - Peripheral interface device ready signal -- PRH_Data_I - Peripheral interface input data bus -- PRH_Data_O - Peripehral interface output data bus -- PRH_Data_T - 3-state control for peripheral interface output data -- bus ------------------------------------------------------------------------------- entity epc_core is generic ( C_SPLB_CLK_PERIOD_PS : integer; LOCAL_CLK_PERIOD_PS : integer; ---------------- ------------------------- C_SPLB_AWIDTH : integer; C_SPLB_DWIDTH : integer; C_SPLB_NATIVE_DWIDTH : integer; C_FAMILY : string; ---------------- ------------------------- C_NUM_PERIPHERALS : integer; C_PRH_MAX_AWIDTH : integer; C_PRH_MAX_DWIDTH : integer; C_PRH_MAX_ADWIDTH : integer; C_PRH_CLK_SUPPORT : integer; C_PRH_BURST_SUPPORT : integer; ---------------- ------------------------- C_PRH0_FIFO_ACCESS : integer; C_PRH0_AWIDTH : integer; C_PRH0_DWIDTH : integer; C_PRH0_DWIDTH_MATCH : integer; C_PRH0_SYNC : integer; C_PRH0_BUS_MULTIPLEX : integer; C_PRH0_ADDR_TSU : integer; C_PRH0_ADDR_TH : integer; C_PRH0_ADS_WIDTH : integer; C_PRH0_CSN_TSU : integer; C_PRH0_CSN_TH : integer; C_PRH0_WRN_WIDTH : integer; C_PRH0_WR_CYCLE : integer; C_PRH0_DATA_TSU : integer; C_PRH0_DATA_TH : integer; C_PRH0_RDN_WIDTH : integer; C_PRH0_RD_CYCLE : integer; C_PRH0_DATA_TOUT : integer; C_PRH0_DATA_TINV : integer; C_PRH0_RDY_TOUT : integer; C_PRH0_RDY_WIDTH : integer; ---------------- ------------------------- C_PRH1_FIFO_ACCESS : integer; C_PRH1_AWIDTH : integer; C_PRH1_DWIDTH : integer; C_PRH1_DWIDTH_MATCH : integer; C_PRH1_SYNC : integer; C_PRH1_BUS_MULTIPLEX : integer; C_PRH1_ADDR_TSU : integer; C_PRH1_ADDR_TH : integer; C_PRH1_ADS_WIDTH : integer; C_PRH1_CSN_TSU : integer; C_PRH1_CSN_TH : integer; C_PRH1_WRN_WIDTH : integer; C_PRH1_WR_CYCLE : integer; C_PRH1_DATA_TSU : integer; C_PRH1_DATA_TH : integer; C_PRH1_RDN_WIDTH : integer; C_PRH1_RD_CYCLE : integer; C_PRH1_DATA_TOUT : integer; C_PRH1_DATA_TINV : integer; C_PRH1_RDY_TOUT : integer; C_PRH1_RDY_WIDTH : integer; ---------------- ------------------------- C_PRH2_FIFO_ACCESS : integer; C_PRH2_AWIDTH : integer; C_PRH2_DWIDTH : integer; C_PRH2_DWIDTH_MATCH : integer; C_PRH2_SYNC : integer; C_PRH2_BUS_MULTIPLEX : integer; C_PRH2_ADDR_TSU : integer; C_PRH2_ADDR_TH : integer; C_PRH2_ADS_WIDTH : integer; C_PRH2_CSN_TSU : integer; C_PRH2_CSN_TH : integer; C_PRH2_WRN_WIDTH : integer; C_PRH2_WR_CYCLE : integer; C_PRH2_DATA_TSU : integer; C_PRH2_DATA_TH : integer; C_PRH2_RDN_WIDTH : integer; C_PRH2_RD_CYCLE : integer; C_PRH2_DATA_TOUT : integer; C_PRH2_DATA_TINV : integer; C_PRH2_RDY_TOUT : integer; C_PRH2_RDY_WIDTH : integer; ---------------- ------------------------- C_PRH3_FIFO_ACCESS : integer; C_PRH3_AWIDTH : integer; C_PRH3_DWIDTH : integer; C_PRH3_DWIDTH_MATCH : integer; C_PRH3_SYNC : integer; C_PRH3_BUS_MULTIPLEX : integer; C_PRH3_ADDR_TSU : integer; C_PRH3_ADDR_TH : integer; C_PRH3_ADS_WIDTH : integer; C_PRH3_CSN_TSU : integer; C_PRH3_CSN_TH : integer; C_PRH3_WRN_WIDTH : integer; C_PRH3_WR_CYCLE : integer; C_PRH3_DATA_TSU : integer; C_PRH3_DATA_TH : integer; C_PRH3_RDN_WIDTH : integer; C_PRH3_RD_CYCLE : integer; C_PRH3_DATA_TOUT : integer; C_PRH3_DATA_TINV : integer; C_PRH3_RDY_TOUT : integer; C_PRH3_RDY_WIDTH : integer; ---------------- ------------------------- MAX_PERIPHERALS : integer; PRH0_FIFO_ADDRESS : std_logic_vector; PRH1_FIFO_ADDRESS : std_logic_vector; PRH2_FIFO_ADDRESS : std_logic_vector; PRH3_FIFO_ADDRESS : std_logic_vector ---------------- ------------------------- ); port ( Bus2IP_Clk : in std_logic; Bus2IP_Rst : in std_logic; -- IPIC interface Bus2IP_CS : in std_logic_vector(0 to C_NUM_PERIPHERALS-1); Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_PERIPHERALS-1); Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_PERIPHERALS-1); Bus2IP_Addr : in std_logic_vector(0 to C_PRH_MAX_AWIDTH-1); Bus2IP_RNW : in std_logic; Bus2IP_BE : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8-1); Bus2IP_Data : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1); IP2Bus_Data : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1); IP2Bus_WrAck : out std_logic; IP2Bus_RdAck : out std_logic; IP2Bus_Error : out std_logic; -- Clock and Reset for peripheral interface Local_Clk : in std_logic; Local_Rst : in std_logic; -- Peripheral interface PRH_CS_n : out std_logic_vector(0 to C_NUM_PERIPHERALS-1); PRH_Addr : out std_logic_vector(0 to C_PRH_MAX_AWIDTH-1); PRH_ADS : out std_logic; PRH_BE : out std_logic_vector(0 to C_PRH_MAX_DWIDTH/8-1); PRH_RNW : out std_logic; PRH_Rd_n : out std_logic; PRH_Wr_n : out std_logic; PRH_Burst : out std_logic; PRH_Rdy : in std_logic_vector(0 to C_NUM_PERIPHERALS-1); PRH_Data_I : in std_logic_vector(0 to C_PRH_MAX_ADWIDTH-1); PRH_Data_O : out std_logic_vector(0 to C_PRH_MAX_ADWIDTH-1); PRH_Data_T : out std_logic_vector(0 to C_PRH_MAX_ADWIDTH-1) ); end entity epc_core; ------------------------------------------------------------------------------- -- Architecture section ------------------------------------------------------------------------------- architecture imp of epc_core is ------------------------------------------------------------------------------- -- Function Declaration ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- NAME: all_zeros ----------------------------------------------------------------------------- -- Description: Given an array returns an integer value of '1' if all elements -- of the array are zero. Returns '0' otherwise ----------------------------------------------------------------------------- function all_zeros ( array_size : integer; int_array : INTEGER_ARRAY_TYPE) return integer is variable temp : integer := 1; begin for i in 0 to (array_size-1) loop if int_array(i) = 1 then temp := 0; end if; end loop; return temp; end function all_zeros; ----------------------------------------------------------------------------- -- NAME: all_ones ----------------------------------------------------------------------------- -- Description: Given an array returns an integer value of '1' if all elements -- of the array are one. Returns '0' otherwise ----------------------------------------------------------------------------- function all_ones ( array_size : integer; int_array : INTEGER_ARRAY_TYPE) return integer is variable temp : integer := 1; begin for i in 0 to (array_size-1) loop if int_array(i) = 0 then temp := 0; end if; end loop; return temp; end function all_ones; ----------------------------------------------------------------------------- -- NAME: IntArray_to_StdLogicVec ----------------------------------------------------------------------------- -- Description: Given an array returns an std_logic_vector, where each -- element of the vector represents a value of '0' if the -- corresponding integer in the array is 0. Else, the vector -- value denotes a '1' ----------------------------------------------------------------------------- function IntArray_to_StdLogicVec ( array_size : integer; int_array : INTEGER_ARRAY_TYPE) return std_logic_vector is variable temp : std_logic_vector(0 to array_size-1); begin for i in 0 to (array_size - 1) loop if int_array(i) = 0 then temp(i) := '0'; else temp(i) := '1'; end if; end loop; return temp; end function IntArray_to_StdLogicVec; ------------------------------------------------------------------------------- -- Type Declarations ------------------------------------------------------------------------------- type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to C_SPLB_AWIDTH-1); ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- constant ADDRCNT_WIDTH : integer := 2; constant PRH_SYNC_ARRAY : INTEGER_ARRAY_TYPE(0 to MAX_PERIPHERALS-1) := ( C_PRH0_SYNC, C_PRH1_SYNC, C_PRH2_SYNC, C_PRH3_SYNC ); constant NO_PRH_SYNC : integer := all_zeros(C_NUM_PERIPHERALS, PRH_SYNC_ARRAY); constant NO_PRH_ASYNC : integer := all_ones(C_NUM_PERIPHERALS, PRH_SYNC_ARRAY); constant PRH_SYNC : std_logic_vector := IntArray_to_StdLogicVec(MAX_PERIPHERALS, PRH_SYNC_ARRAY); constant PRH_BUS_MULTIPLEX_ARRAY : INTEGER_ARRAY_TYPE(0 to MAX_PERIPHERALS-1) := ( C_PRH0_BUS_MULTIPLEX, C_PRH1_BUS_MULTIPLEX, C_PRH2_BUS_MULTIPLEX, C_PRH3_BUS_MULTIPLEX ); constant NO_PRH_BUS_MULTIPLEX : integer := all_zeros(C_NUM_PERIPHERALS, PRH_BUS_MULTIPLEX_ARRAY); constant PRH_BUS_MULTIPLEX : std_logic_vector := IntArray_to_StdLogicVec(MAX_PERIPHERALS, PRH_BUS_MULTIPLEX_ARRAY); constant PRH_DWIDTH_MATCH_ARRAY: INTEGER_ARRAY_TYPE(0 to MAX_PERIPHERALS-1) := ( C_PRH0_DWIDTH_MATCH, C_PRH1_DWIDTH_MATCH, C_PRH2_DWIDTH_MATCH, C_PRH3_DWIDTH_MATCH ); constant NO_PRH_DWIDTH_MATCH : integer := all_zeros(C_NUM_PERIPHERALS, PRH_DWIDTH_MATCH_ARRAY); constant ALL_PRH_DWIDTH_MATCH : integer := all_ones(C_NUM_PERIPHERALS, PRH_DWIDTH_MATCH_ARRAY); constant PRH_DWIDTH_MATCH : std_logic_vector := IntArray_to_StdLogicVec(MAX_PERIPHERALS, PRH_DWIDTH_MATCH_ARRAY); constant PRH_FIFO_ACCESS_ARRAY : INTEGER_ARRAY_TYPE(0 to MAX_PERIPHERALS-1) := ( C_PRH0_FIFO_ACCESS, C_PRH1_FIFO_ACCESS, C_PRH2_FIFO_ACCESS, C_PRH3_FIFO_ACCESS ); constant PRH_FIFO_ADDRESS_ARRAY : SLV32_ARRAY_TYPE(0 to MAX_PERIPHERALS-1) := ( PRH0_FIFO_ADDRESS, PRH1_FIFO_ADDRESS, PRH2_FIFO_ADDRESS, PRH3_FIFO_ADDRESS ); ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- signal ipic_sync_req : std_logic; signal ip_sync_req_rst : std_logic; signal ipic_async_req : std_logic; signal ip_sync_Wrack : std_logic; signal ip_sync_Rdack : std_logic; signal ipic_sync_ack_rst : std_logic; signal ip_async_Wrack : std_logic; signal ip_async_Rdack : std_logic; signal ip_sync_error : std_logic; signal ip_async_error : std_logic; signal dev_id : std_logic_vector(0 to C_NUM_PERIPHERALS-1); signal dev_in_access : std_logic; signal dev_sync_in_access : std_logic; signal dev_async_in_access : std_logic; signal dev_sync : std_logic; signal dev_rnw : std_logic; signal dev_bus_multiplex : std_logic; signal dev_dwidth_match : std_logic; signal dev_dbus_width : std_logic_vector(0 to 2); signal async_addr_cnt_ld : std_logic; signal async_addr_cnt_ce : std_logic; signal sync_addr_cnt_ld : std_logic; signal sync_addr_cnt_ce : std_logic; signal async_en : std_logic; signal async_ce : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8-1); signal sync_en : std_logic; signal sync_ce : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8-1); signal addr_suffix : std_logic_vector(0 to ADDRCNT_WIDTH-1); signal steer_index : std_logic_vector(0 to ADDRCNT_WIDTH-1); signal dev_rdy : std_logic; signal sync_ads : std_logic; signal sync_cs_n : std_logic_vector(0 to C_NUM_PERIPHERALS-1); signal sync_rnw : std_logic; signal sync_burst : std_logic; signal sync_addr_ph : std_logic; signal sync_data_oe : std_logic; signal async_ads : std_logic; signal async_cs_n : std_logic_vector(0 to C_NUM_PERIPHERALS-1); signal async_rd_n : std_logic; signal async_wr_n : std_logic; signal async_addr_ph : std_logic; signal async_data_oe : std_logic; signal addr_int : std_logic_vector(0 to C_PRH_MAX_AWIDTH-1); signal data_int : std_logic_vector(0 to C_PRH_MAX_DWIDTH-1); signal prh_data_in : std_logic_vector(0 to C_PRH_MAX_DWIDTH-1); signal fifo_access : std_logic := '0'; signal dev_fifo_access : std_logic := '0'; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- begin IPIC_DECODE_I : entity axi_epc_v2_0.ipic_if_decode generic map ( C_SPLB_DWIDTH => C_SPLB_DWIDTH, C_NUM_PERIPHERALS => C_NUM_PERIPHERALS, C_PRH_CLK_SUPPORT => C_PRH_CLK_SUPPORT, ----------------------------------------- C_PRH0_DWIDTH_MATCH => C_PRH0_DWIDTH_MATCH, C_PRH1_DWIDTH_MATCH => C_PRH1_DWIDTH_MATCH, C_PRH2_DWIDTH_MATCH => C_PRH2_DWIDTH_MATCH, C_PRH3_DWIDTH_MATCH => C_PRH3_DWIDTH_MATCH, ----------------------------------------- C_PRH0_DWIDTH => C_PRH0_DWIDTH, C_PRH1_DWIDTH => C_PRH1_DWIDTH, C_PRH2_DWIDTH => C_PRH2_DWIDTH, C_PRH3_DWIDTH => C_PRH3_DWIDTH, ----------------------------------------- MAX_PERIPHERALS => MAX_PERIPHERALS, NO_PRH_SYNC => NO_PRH_SYNC, NO_PRH_ASYNC => NO_PRH_ASYNC, PRH_SYNC => PRH_SYNC, ----------------------------------------- NO_PRH_BUS_MULTIPLEX => NO_PRH_BUS_MULTIPLEX, PRH_BUS_MULTIPLEX => PRH_BUS_MULTIPLEX, NO_PRH_DWIDTH_MATCH => NO_PRH_DWIDTH_MATCH, PRH_DWIDTH_MATCH => PRH_DWIDTH_MATCH ) port map ( Bus2IP_Clk => Bus2IP_Clk, Bus2IP_Rst => Bus2IP_Rst, ------------------------------------------ Local_Clk => Local_Clk, Local_Rst => Local_Rst, ------------------------------------------ Bus2IP_CS => Bus2IP_CS, Bus2IP_RNW => Bus2IP_RNW, ------------------------------------------ IP2Bus_WrAck => IP2Bus_WrAck, IP2Bus_RdAck => IP2Bus_RdAck, IP2Bus_Error => IP2Bus_Error, ------------------------------------------ FIFO_access => fifo_access, ------------------------------------------ Dev_id => dev_id, Dev_fifo_access => dev_fifo_access, Dev_in_access => dev_in_access, Dev_sync_in_access => dev_sync_in_access, Dev_async_in_access => dev_async_in_access, Dev_sync => dev_sync, Dev_rnw => dev_rnw, Dev_bus_multiplex => dev_bus_multiplex, Dev_dwidth_match => dev_dwidth_match, Dev_dbus_width => dev_dbus_width, ------------------------------------------ IPIC_sync_req => ipic_sync_req, IPIC_async_req => ipic_async_req, IP_sync_req_rst => ip_sync_req_rst, ------------------------------------------ IP_sync_Wrack => ip_sync_Wrack, IP_sync_Rdack => ip_sync_Rdack, IPIC_sync_ack_rst => ipic_sync_ack_rst, ------------------------------------------ IP_async_Wrack => ip_async_Wrack, IP_async_Rdack => ip_async_Rdack, ------------------------------------------ IP_sync_error => ip_sync_error, IP_async_error => ip_async_error ); SYNC_CNTL_I : entity axi_epc_v2_0.sync_cntl generic map ( C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH, C_NUM_PERIPHERALS => C_NUM_PERIPHERALS, C_PRH_CLK_SUPPORT => C_PRH_CLK_SUPPORT, ----------------------------------------- C_PRH0_ADDR_TSU => C_PRH0_ADDR_TSU, C_PRH1_ADDR_TSU => C_PRH1_ADDR_TSU, C_PRH2_ADDR_TSU => C_PRH2_ADDR_TSU, C_PRH3_ADDR_TSU => C_PRH3_ADDR_TSU, ----------------------------------------- C_PRH0_ADDR_TH => C_PRH0_ADDR_TH, C_PRH1_ADDR_TH => C_PRH1_ADDR_TH, C_PRH2_ADDR_TH => C_PRH2_ADDR_TH, C_PRH3_ADDR_TH => C_PRH3_ADDR_TH, ----------------------------------------- C_PRH0_ADS_WIDTH => C_PRH0_ADS_WIDTH, C_PRH1_ADS_WIDTH => C_PRH1_ADS_WIDTH, C_PRH2_ADS_WIDTH => C_PRH2_ADS_WIDTH, C_PRH3_ADS_WIDTH => C_PRH3_ADS_WIDTH, ----------------------------------------- C_PRH0_RDY_WIDTH => C_PRH0_RDY_WIDTH, C_PRH1_RDY_WIDTH => C_PRH1_RDY_WIDTH, C_PRH2_RDY_WIDTH => C_PRH2_RDY_WIDTH, C_PRH3_RDY_WIDTH => C_PRH3_RDY_WIDTH, ----------------------------------------- LOCAL_CLK_PERIOD_PS => LOCAL_CLK_PERIOD_PS, MAX_PERIPHERALS => MAX_PERIPHERALS, ADDRCNT_WIDTH => ADDRCNT_WIDTH, NO_PRH_SYNC => NO_PRH_SYNC, PRH_SYNC => PRH_SYNC, NO_PRH_DWIDTH_MATCH => NO_PRH_DWIDTH_MATCH ) port map ( Bus2IP_Clk => Bus2IP_Clk, Bus2IP_Rst => Bus2IP_Rst, ------------------------------------------ Local_Clk => Local_Clk, Local_Rst => Local_Rst, ------------------------------------------ Bus2IP_BE => Bus2IP_BE, ------------------------------------------ Dev_id => dev_id, Dev_fifo_access => dev_fifo_access, Dev_in_access => dev_sync_in_access, Dev_rnw => dev_rnw, Dev_bus_multiplex => dev_bus_multiplex, Dev_dwidth_match => dev_dwidth_match, Dev_dbus_width => dev_dbus_width, ------------------------------------------ IPIC_sync_req => ipic_sync_req, IP_sync_req_rst => ip_sync_req_rst, ------------------------------------------ IP_sync_Wrack => ip_sync_Wrack, IP_sync_Rdack => ip_sync_Rdack, IPIC_sync_ack_rst => ipic_sync_ack_rst, ------------------------------------------ IP_sync_errack => ip_sync_error, ------------------------------------------ Sync_addr_cnt_ld => sync_addr_cnt_ld, Sync_addr_cnt_ce => sync_addr_cnt_ce, ------------------------------------------ Sync_en => sync_en, Sync_ce => sync_ce, ------------------------------------------ Steer_index => steer_index, ------------------------------------------ Dev_Rdy => dev_rdy, ------------------------------------------ Sync_ADS => sync_ads, Sync_CS_n => sync_cs_n, Sync_RNW => sync_rnw, Sync_Burst => sync_burst, ------------------------------------------ Sync_addr_ph => sync_addr_ph, Sync_data_oe => sync_data_oe ); ASYNC_CNTL_I : entity axi_epc_v2_0.async_cntl generic map ( PRH_SYNC => PRH_SYNC, NO_PRH_ASYNC => NO_PRH_ASYNC, C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH, ------------------------------------------ C_PRH0_ADDR_TSU => C_PRH0_ADDR_TSU, C_PRH0_ADDR_TH => C_PRH0_ADDR_TH, C_PRH0_WRN_WIDTH => C_PRH0_WRN_WIDTH, C_PRH0_DATA_TSU => C_PRH0_DATA_TSU, C_PRH0_RDN_WIDTH => C_PRH0_RDN_WIDTH, C_PRH0_DATA_TOUT => C_PRH0_DATA_TOUT, C_PRH0_DATA_TH => C_PRH0_DATA_TH, C_PRH0_DATA_TINV => C_PRH0_DATA_TINV, C_PRH0_RDY_TOUT => C_PRH0_RDY_TOUT, C_PRH0_RDY_WIDTH => C_PRH0_RDY_WIDTH, C_PRH0_ADS_WIDTH => C_PRH0_ADS_WIDTH, C_PRH0_CSN_TSU => C_PRH0_CSN_TSU, C_PRH0_CSN_TH => C_PRH0_CSN_TH, C_PRH0_WR_CYCLE => C_PRH0_WR_CYCLE, C_PRH0_RD_CYCLE => C_PRH0_RD_CYCLE, ------------------------------------------ C_PRH1_ADDR_TSU => C_PRH1_ADDR_TSU, C_PRH1_ADDR_TH => C_PRH1_ADDR_TH, C_PRH1_WRN_WIDTH => C_PRH1_WRN_WIDTH, C_PRH1_DATA_TSU => C_PRH1_DATA_TSU, C_PRH1_RDN_WIDTH => C_PRH1_RDN_WIDTH, C_PRH1_DATA_TOUT => C_PRH1_DATA_TOUT, C_PRH1_DATA_TH => C_PRH1_DATA_TH, C_PRH1_DATA_TINV => C_PRH1_DATA_TINV, C_PRH1_RDY_TOUT => C_PRH1_RDY_TOUT, C_PRH1_RDY_WIDTH => C_PRH1_RDY_WIDTH, C_PRH1_ADS_WIDTH => C_PRH1_ADS_WIDTH, C_PRH1_CSN_TSU => C_PRH1_CSN_TSU, C_PRH1_CSN_TH => C_PRH1_CSN_TH, C_PRH1_WR_CYCLE => C_PRH1_WR_CYCLE, C_PRH1_RD_CYCLE => C_PRH1_RD_CYCLE, ------------------------------------------ C_PRH2_ADDR_TSU => C_PRH2_ADDR_TSU, C_PRH2_ADDR_TH => C_PRH2_ADDR_TH, C_PRH2_WRN_WIDTH => C_PRH2_WRN_WIDTH, C_PRH2_DATA_TSU => C_PRH2_DATA_TSU, C_PRH2_RDN_WIDTH => C_PRH2_RDN_WIDTH, C_PRH2_DATA_TOUT => C_PRH2_DATA_TOUT, C_PRH2_DATA_TH => C_PRH2_DATA_TH, C_PRH2_DATA_TINV => C_PRH2_DATA_TINV, C_PRH2_RDY_TOUT => C_PRH2_RDY_TOUT, C_PRH2_RDY_WIDTH => C_PRH2_RDY_WIDTH, C_PRH2_ADS_WIDTH => C_PRH2_ADS_WIDTH, C_PRH2_CSN_TSU => C_PRH2_CSN_TSU, C_PRH2_CSN_TH => C_PRH2_CSN_TH, C_PRH2_WR_CYCLE => C_PRH2_WR_CYCLE, C_PRH2_RD_CYCLE => C_PRH2_RD_CYCLE, ------------------------------------------ C_PRH3_ADDR_TSU => C_PRH3_ADDR_TSU, C_PRH3_ADDR_TH => C_PRH3_ADDR_TH, C_PRH3_WRN_WIDTH => C_PRH3_WRN_WIDTH, C_PRH3_DATA_TSU => C_PRH3_DATA_TSU, C_PRH3_RDN_WIDTH => C_PRH3_RDN_WIDTH, C_PRH3_DATA_TOUT => C_PRH3_DATA_TOUT, C_PRH3_DATA_TH => C_PRH3_DATA_TH, C_PRH3_DATA_TINV => C_PRH3_DATA_TINV, C_PRH3_RDY_TOUT => C_PRH3_RDY_TOUT, C_PRH3_RDY_WIDTH => C_PRH3_RDY_WIDTH, C_PRH3_ADS_WIDTH => C_PRH3_ADS_WIDTH, C_PRH3_CSN_TSU => C_PRH3_CSN_TSU, C_PRH3_CSN_TH => C_PRH3_CSN_TH, C_PRH3_WR_CYCLE => C_PRH3_WR_CYCLE, C_PRH3_RD_CYCLE => C_PRH3_RD_CYCLE, ------------------------------------------ C_BUS_CLOCK_PERIOD_PS => C_SPLB_CLK_PERIOD_PS, -- C_MAX_DWIDTH => C_PRH_MAX_DWIDTH, C_NUM_PERIPHERALS => C_NUM_PERIPHERALS, C_MAX_PERIPHERALS => MAX_PERIPHERALS ------------------------------------------ ) port map( Bus2IP_CS => Bus2IP_CS, Bus2IP_RdCE => Bus2IP_RdCE, Bus2IP_WrCE => Bus2IP_WrCE, Bus2IP_BE => Bus2IP_BE, Bus2IP_RNW => Bus2IP_RNW, ------------------------------------------ IPIC_Asynch_req => ipic_async_req, Dev_FIFO_access => dev_fifo_access, Dev_in_access => dev_async_in_access, ------------------------------------------ Asynch_prh_rdy => dev_rdy, Dev_dwidth_match => dev_dwidth_match, -- Dev_dbus_width => dev_dbus_width, Dev_bus_multiplexed => dev_bus_multiplex, Asynch_ce => async_ce, ------------------------------------------ Asynch_Wrack => ip_async_Wrack, Asynch_Rdack => ip_async_Rdack, Asynch_error => ip_async_error, ------------------------------------------ Asynch_Wr => async_wr_n, Asynch_Rd => async_rd_n, Asynch_en => async_en, ------------------------------------------ Asynch_addr_strobe => async_ads, Asynch_addr_data_sel => async_addr_ph, Asynch_data_sel => async_data_oe, Asynch_chip_select => async_cs_n, Asynch_addr_cnt_ld => async_addr_cnt_ld, Asynch_addr_cnt_en => async_addr_cnt_ce, ------------------------------------------ Clk => Bus2IP_Clk, Rst => Bus2IP_Rst ); ADDRESS_GEN_I: entity axi_epc_v2_0.address_gen generic map ( C_PRH_MAX_AWIDTH => C_PRH_MAX_AWIDTH, NO_PRH_DWIDTH_MATCH => NO_PRH_DWIDTH_MATCH, NO_PRH_SYNC => NO_PRH_SYNC, NO_PRH_ASYNC => NO_PRH_ASYNC, ADDRCNT_WIDTH => ADDRCNT_WIDTH ) port map ( Bus2IP_Clk => Bus2IP_Clk, Bus2IP_Rst => Bus2IP_Rst, ------------------------------------------ Local_Clk => Local_Clk, Local_Rst => Local_Rst, ------------------------------------------ Bus2IP_Addr => bus2ip_addr, ------------------------------------------ Dev_fifo_access => dev_fifo_access, Dev_sync => dev_sync, Dev_dwidth_match => dev_dwidth_match, Dev_dbus_width => dev_dbus_width, ------------------------------------------ Async_addr_cnt_ld => async_addr_cnt_ld, Async_addr_cnt_ce => async_addr_cnt_ce, ------------------------------------------ Sync_addr_cnt_ld => sync_addr_cnt_ld, Sync_addr_cnt_ce => sync_addr_cnt_ce, ------------------------------------------ Addr_Int => addr_int, Addr_suffix => addr_suffix ); DATA_STEER_I: entity axi_epc_v2_0.data_steer generic map ( C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH, C_PRH_MAX_DWIDTH => C_PRH_MAX_DWIDTH, ALL_PRH_DWIDTH_MATCH => ALL_PRH_DWIDTH_MATCH, NO_PRH_DWIDTH_MATCH => NO_PRH_DWIDTH_MATCH, NO_PRH_SYNC => NO_PRH_SYNC, NO_PRH_ASYNC => NO_PRH_ASYNC, ADDRCNT_WIDTH => ADDRCNT_WIDTH ) port map ( Bus2IP_Clk => Bus2IP_Clk, Bus2IP_Rst => Bus2IP_Rst, ------------------------------------------ Local_Clk => Local_Clk, Local_Rst => Local_Rst, ------------------------------------------ Bus2IP_RNW => Bus2IP_RNW, Bus2IP_BE => Bus2IP_BE, Bus2IP_Data => Bus2IP_Data, ------------------------------------------ Dev_in_access => dev_in_access, Dev_sync => dev_sync, Dev_rnw => dev_rnw, Dev_dwidth_match => dev_dwidth_match, Dev_dbus_width => dev_dbus_width, ------------------------------------------ Addr_suffix => addr_suffix, Steer_index => steer_index, ------------------------------------------ Async_en => async_en, Async_ce => async_ce, ------------------------------------------ Sync_en => sync_en, Sync_ce => sync_ce, ------------------------------------------ PRH_Data_In => prh_data_in, PRH_BE => PRH_BE, ------------------------------------------ Data_Int => data_int, IP2Bus_Data => IP2Bus_Data, Dev_bus_multiplex => Dev_bus_multiplex ); ACCESS_MUX_I : entity axi_epc_v2_0.access_mux generic map ( C_NUM_PERIPHERALS => C_NUM_PERIPHERALS, C_PRH_MAX_AWIDTH => C_PRH_MAX_AWIDTH, C_PRH_MAX_DWIDTH => C_PRH_MAX_DWIDTH, C_PRH_MAX_ADWIDTH => C_PRH_MAX_ADWIDTH, ------------------------------------------ C_PRH0_AWIDTH => C_PRH0_AWIDTH, C_PRH1_AWIDTH => C_PRH1_AWIDTH, C_PRH2_AWIDTH => C_PRH2_AWIDTH, C_PRH3_AWIDTH => C_PRH3_AWIDTH, ------------------------------------------ C_PRH0_DWIDTH => C_PRH0_DWIDTH, C_PRH1_DWIDTH => C_PRH1_DWIDTH, C_PRH2_DWIDTH => C_PRH2_DWIDTH, C_PRH3_DWIDTH => C_PRH3_DWIDTH, ------------------------------------------ C_PRH0_BUS_MULTIPLEX => C_PRH0_BUS_MULTIPLEX, C_PRH1_BUS_MULTIPLEX => C_PRH1_BUS_MULTIPLEX, C_PRH2_BUS_MULTIPLEX => C_PRH2_BUS_MULTIPLEX, C_PRH3_BUS_MULTIPLEX => C_PRH3_BUS_MULTIPLEX, ------------------------------------------ MAX_PERIPHERALS => MAX_PERIPHERALS, NO_PRH_SYNC => NO_PRH_SYNC, NO_PRH_ASYNC => NO_PRH_ASYNC, NO_PRH_BUS_MULTIPLEX => NO_PRH_BUS_MULTIPLEX ) port map ( Local_Clk => Local_Clk, Dev_id => dev_id, ------------------------------------------ Sync_CS_n => sync_cs_n, Sync_ADS => sync_ads, Sync_RNW => sync_rnw, Sync_Burst => sync_burst, Sync_addr_ph => sync_addr_ph, Sync_data_oe => sync_data_oe, ------------------------------------------ Async_CS_n => async_cs_n, Async_ADS => async_ads, Async_Rd_n => async_rd_n, Async_Wr_n => async_wr_n, Async_addr_ph => async_addr_ph, Async_data_oe => async_data_oe, ------------------------------------------ Addr_Int => addr_int, Data_Int => data_int, ------------------------------------------ PRH_CS_n => PRH_CS_n, PRH_ADS => PRH_ADS, PRH_RNW => PRH_RNW, PRH_Rd_n => PRH_Rd_n, PRH_Wr_n => PRH_Wr_n, PRH_Burst => PRH_Burst, ------------------------------------------ PRH_Rdy => PRH_Rdy, Dev_Rdy => dev_rdy, ------------------------------------------ PRH_Addr => PRH_Addr, PRH_Data_O => PRH_Data_O, PRH_Data_T => PRH_Data_T ); prh_data_in <= PRH_Data_I(0 to C_PRH_MAX_DWIDTH-1); ------------------------------------------------------------------------------- -- NAME: DEV_FIFO_ACCESS_PROCESS ------------------------------------------------------------------------------- -- Description: Generate an indication to the internal modules that the -- current transaction is to a FIFO like structure ------------------------------------------------------------------------------- DEV_FIFO_ACCESS_PROCESS: process (Bus2IP_CS, Bus2IP_Addr) is begin fifo_access <= '0'; for i in 0 to C_NUM_PERIPHERALS-1 loop if (Bus2IP_CS(i) = '1') then if ( (PRH_FIFO_ACCESS_ARRAY(i) = 1) and (Bus2IP_Addr = PRH_FIFO_ADDRESS_ARRAY(i) (C_SPLB_AWIDTH-C_PRH_MAX_AWIDTH to C_SPLB_AWIDTH-1)) ) then fifo_access <= '1'; end if; end if; end loop; end process DEV_FIFO_ACCESS_PROCESS; end architecture imp; --------------------------------end of file------------------------------------
--test bench written by Alban Bourge @ TIMA library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.pkg_tb.all; entity prog is port( clock : in std_logic; reset : in std_logic; step : in std_logic; instr_next : out instruction ); end prog; architecture rtl of prog is signal instr_n : instruction := instr_rst; --Table describing fsm behavior constant fsm_behavior : table_behavior := ( --##PROGRAM_GOES_DOWN_HERE##-- 0 => (state => Rst, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)), 1 => (state => Rst, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)), 2 => (state => Sig_start, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)), 3 => (state => Ack_data, context_uut => "01", arg => to_unsigned(64,ARG_WIDTH)), 4 => (state => Cp_search, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)), 5 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)), 6 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)), 7 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)), 8 => (state => Sig_start, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)), 9 => (state => Ack_data, context_uut => "10", arg => to_unsigned(64,ARG_WIDTH)), 10 => (state => Running, context_uut => "10", arg => to_unsigned(20,ARG_WIDTH)), 11 => (state => Cp_search, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)), 12 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)), 13 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)), 14 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)), 15 => (state => Rest_ini0, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)), 16 => (state => Waitfor, context_uut => "01", arg => to_unsigned(64,ARG_WIDTH)), 17 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)), 18 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)), 19 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)), 20 => (state => Rest_ini0, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)), 21 => (state => Waitfor, context_uut => "10", arg => to_unsigned(64,ARG_WIDTH)), 22 => (state => Stop, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)), --##PROGRAM_GOES_OVER_HERE##-- others => instr_rst); signal pc : unsigned(PC_SIZE - 1 downto 0) := (others => '0'); begin drive_state : process (reset,clock) is begin if reset = '1' then instr_n <= instr_rst; pc <= (others => '0'); elsif rising_edge(clock) then if (step = '1') then pc <= pc + 1; end if; instr_n <= fsm_behavior(to_integer(pc)); end if; end process drive_state; --instr_next <= instr_n; instr_next <= fsm_behavior(to_integer(pc)); end rtl;