content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.std_logic_1164.all;
-- Dummy sld_virtual_jtag - ModelSim crashes on default one
entity sld_virtual_jtag is
generic (
lpm_type : string := "SLD_VIRTUAL_JTAG";
-- required by coding standard
lpm_hint : string := "SLD_VIRTUAL_JTAG"; ... |
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
-- Test bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.ALL;
entity wasca_tb is
end entity wasca_tb;
architecture SIMULATE of wasca_tb is
-- Clock
signal clk_clk : std_logic ... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: wizpll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:41:42 12/26/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs2/tb_datapath.vhd
-- Project Name: idea_rcs2
-- Target Device:
-- Tool versions: ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:41:42 12/26/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs2/tb_datapath.vhd
-- Project Name: idea_rcs2
-- Target Device:
-- Tool versions: ... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: CLK4Hz
-- Project Name: CLOCK COUNTER
-- Target Devices: Spartan-3E
-- Tool versions: ... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:19:39 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Counter_rst_set_n_bits
-- Module Name: Counter_rst_set_n_bits
-- Project Name:... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity LX9CoProZ80 is
port (
-- GOP Signals
fastclk : in std_logic;
test : inout std_logic_vector(8 downto 1);
sw : in std_logic_vector(3 downto 0);
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity LX9CoProSPI is
port (
-- GOP Signals
fastclk : in std_logic;
sw : in std_logic_vector(3 downto 0);
-- Tube signals
h_phi2 : in ... |
---------------------------------------------------------------------------------
-- Title : ARP Packet TX
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : IPv4Tx.vhd
-- Author : Kurtis Nishimura
-----------------... |
-- ----------------------------------------------------------------
-- adder_tree.vhd
--
-- 4/28/2011 D. W. Hawkins (dwh@ovro.caltech.edu)
--
-- Adder tree.
--
-- This component calculates the pipelined sum of parallel input
-- arguments and generates a single output. The sums are
-- implemented in pairs. The width of ... |
----------------------------------------------------------------------
--- A synchronous memory
----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
entity memory256x8 is
port (
ck : in std_logic;
we : in std_l... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY tb_sqrt IS
END tb_sqrt;
ARCHITECTURE sqrt_arch OF tb_sqrt IS
-- constants
-- signals
SIGNAL btn : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL hex0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL hex1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL hex2 : STD_LO... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
----------------------------------------------------------------------------------------------------
--
-- FileName: DRAM.vhd
-- Description: MainBoard DRAM Controller CPLD Top Level.
--
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity fsm_163 is
port (
clock : in std_logic;
reset : in std_logic;
out91 : out std_logic;
out92 : out std_logic;
out93 : out std_logic;
in7 : in std_logic;
out94 : out std_logic;
out95 : out std_logic;
out98 : o... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity fsm_163 is
port (
clock : in std_logic;
reset : in std_logic;
out91 : out std_logic;
out92 : out std_logic;
out93 : out std_logic;
in7 : in std_logic;
out94 : out std_logic;
out95 : out std_logic;
out98 : o... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity fsm_163 is
port (
clock : in std_logic;
reset : in std_logic;
out91 : out std_logic;
out92 : out std_logic;
out93 : out std_logic;
in7 : in std_logic;
out94 : out std_logic;
out95 : out std_logic;
out98 : o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity debayer33 is
generic( CLK_PROC_FREQ : integer;
IM_WIDTH : integer := 1280;
IM_HEIGHT : integer := 960;
COLOR_CHANNELS : integer := 3;
DATA_SIZE : integer := 8
);
port(
clk_proc : in std... |
entity test is
end test;
architecture only of test is
procedure iterate (
input : in bit_vector) is
variable j : integer := input'range'left;
begin -- iterate
for i in input'range loop
assert i = j report "TEST FAILED" severity failure;
j := j + 1;
end loop; -- i in 1 to 10
assert... |
entity test is
end test;
architecture only of test is
procedure iterate (
input : in bit_vector) is
variable j : integer := input'range'left;
begin -- iterate
for i in input'range loop
assert i = j report "TEST FAILED" severity failure;
j := j + 1;
end loop; -- i in 1 to 10
assert... |
entity test is
end test;
architecture only of test is
procedure iterate (
input : in bit_vector) is
variable j : integer := input'range'left;
begin -- iterate
for i in input'range loop
assert i = j report "TEST FAILED" severity failure;
j := j + 1;
end loop; -- i in 1 to 10
assert... |
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_t
--
-- Generated
-- by: wig
-- on: Thu Oct 13 08:24:14 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../intra.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_172 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_172;
architecture augh of add_172 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_172 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_172;
architecture augh of add_172 is
signal carry_inA : std_l... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright... |
----------------------------------------------------------------------------------
-- Author: Osowski Marcin
--
-- Description:
-- o Entity generates impulses required for managing
-- vga port in 1280x1024@60hz mode
--
-- o It requires 108 Mhz input clock
--
-- o It generates vblank signal. Whenever i... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE is
port(
HCLK : in vl_logic;
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENA... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE is
port(
HCLK : in vl_logic;
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENA... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE is
port(
HCLK : in vl_logic;
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENA... |
------------------------------------------------------------------------------------------------------------------------
-- RMII to MII converter
-- ex: openMAC - openHUB - RMII2MII - MII PHY
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, ... |
------------------------------------------------------------------------------------------------------------------------
-- RMII to MII converter
-- ex: openMAC - openHUB - RMII2MII - MII PHY
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, ... |
------------------------------------------------------------------------------------------------------------------------
-- RMII to MII converter
-- ex: openMAC - openHUB - RMII2MII - MII PHY
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xil... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xil... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xil... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xil... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xil... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xil... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY apll IS
generic (
freq : integer := 200;
mult : integer := 8;
div : integer := 5;
rskew : integer := 0
);
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY apll IS
generic (
freq : integer := 200;
mult : integer := 8;
div : integer := 5;
rskew : integer := 0
);
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY apll IS
generic (
freq : integer := 200;
mult : integer := 8;
div : integer := 5;
rskew : integer := 0
);
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY apll IS
generic (
freq : integer := 200;
mult : integer := 8;
div : integer := 5;
rskew : integer := 0
);
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity shifter is
port (
--clk: in std_logic;
--rst: in std_logic;
a: in unsigned(31 downto 0);
b: in unsigned(4 downto 0);
o: out unsigned(31 downto 0);
left: in std_logic;
arith:i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:06:19 10/24/2009
-- Design Name:
-- Module Name: mROM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
constant I2CFSMLength : integer := 1295;
constant I2CFSMCfg : std_logic_vector(I2CFSMLength-1 downto 0) := "0001100000000100000000000001000101000000010000000000110011000000000000100000011100100000001000000000010000010100000000000001000000000010000100000000010000000000000000000100010001110000100000000000000100000... |
constant I2CFSMLength : integer := 1295;
constant I2CFSMCfg : std_logic_vector(I2CFSMLength-1 downto 0) := "0001100000000100000000000001000101000000010000000000110011000000000000100000011100100000001000000000010000010100000000000001000000000010000100000000010000000000000000000100010001110000100000000000000100000... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--
-- Author: Pawel Szostek (pawel.szostek@cern.ch)
-- Date: 27.07.2011
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity dummy is
port (o1: out std_logic_vector(7 downto 0);
o2: out std_logic_vector(7 downto 0);
o3: out std_logic_vect... |
--
-- Author: Pawel Szostek (pawel.szostek@cern.ch)
-- Date: 27.07.2011
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity dummy is
port (o1: out std_logic_vector(7 downto 0);
o2: out std_logic_vector(7 downto 0);
o3: out std_logic_vect... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
entity simple_car_alarm is
port (
clk, rst, remote, sensors: in std_logic;
siren: out std_logic);
end entity simple_car_alarm;
--------... |
--------------------------------------------------------------------------------
--
-- UART top module
--
-- 8 bit data, 1 stop bit, no parity. Intended for the Digilent Arty Artix-7
-- FPGA board, but can be easily used in other projects without modification.
--
-- Signals:
-- clk : Clock of frequ... |
entity reprook is
generic (
BUS_WIDTH : integer := 8;
ARRAY_WIDTH : integer := 2);
end entity reprook;
architecture behavioural of reprook is
type test_array_btype is array (integer range <>) of
bit_vector (BUS_WIDTH-1 downto 0);
subtype test_array_type is test_array_btype (ARRAY_WIDTH-1 downto 0)... |
entity reprook is
generic (
BUS_WIDTH : integer := 8;
ARRAY_WIDTH : integer := 2);
end entity reprook;
architecture behavioural of reprook is
type test_array_btype is array (integer range <>) of
bit_vector (BUS_WIDTH-1 downto 0);
subtype test_array_type is test_array_btype (ARRAY_WIDTH-1 downto 0)... |
entity reprook is
generic (
BUS_WIDTH : integer := 8;
ARRAY_WIDTH : integer := 2);
end entity reprook;
architecture behavioural of reprook is
type test_array_btype is array (integer range <>) of
bit_vector (BUS_WIDTH-1 downto 0);
subtype test_array_type is test_array_btype (ARRAY_WIDTH-1 downto 0)... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY grlib;
USE grlib.amba.all;
USE grlib.stdlib.all;
LIBRARY gaisler;
USE grlib.devices.all;
USE gaisler.memctrl.all;
LIBRARY techmap;
USE techmap.gencomp.all;
ENTITY ddrsp64a IS
GENERIC (
memtech : integer := 0;
hindex : intege... |
entity case4 is
end entity;
architecture test of case4 is
constant c1 : bit_vector(7 downto 0) := X"ab";
constant c2 : bit_vector(7 downto 0) := X"62";
signal s : bit_vector(7 downto 0);
signal x, y : natural;
begin
process (s) is
begin
case s is
when c1 =>
... |
entity case4 is
end entity;
architecture test of case4 is
constant c1 : bit_vector(7 downto 0) := X"ab";
constant c2 : bit_vector(7 downto 0) := X"62";
signal s : bit_vector(7 downto 0);
signal x, y : natural;
begin
process (s) is
begin
case s is
when c1 =>
... |
entity case4 is
end entity;
architecture test of case4 is
constant c1 : bit_vector(7 downto 0) := X"ab";
constant c2 : bit_vector(7 downto 0) := X"62";
signal s : bit_vector(7 downto 0);
signal x, y : natural;
begin
process (s) is
begin
case s is
when c1 =>
... |
entity case4 is
end entity;
architecture test of case4 is
constant c1 : bit_vector(7 downto 0) := X"ab";
constant c2 : bit_vector(7 downto 0) := X"62";
signal s : bit_vector(7 downto 0);
signal x, y : natural;
begin
process (s) is
begin
case s is
when c1 =>
... |
entity case4 is
end entity;
architecture test of case4 is
constant c1 : bit_vector(7 downto 0) := X"ab";
constant c2 : bit_vector(7 downto 0) := X"62";
signal s : bit_vector(7 downto 0);
signal x, y : natural;
begin
process (s) is
begin
case s is
when c1 =>
... |
library ieee;
use ieee.std_logic_1164.all;
entity ip is port
(
ct : in std_logic_vector(1 TO 64);
l0x : out std_logic_vector(1 TO 32);
r0x : out std_logic_vector(1 TO 32)
);
end ip;
architecture behavior of ip is
begin
l0x(1)<=ct(58); l0x(2)<=ct(50); l0x(3)<=ct(42); l0x(4)<=ct(34); l0x(5)<=ct(26); l0x(6)<=ct(18); l0x(7... |
library ieee;
use ieee.std_logic_1164.all;
entity ip is port
(
ct : in std_logic_vector(1 TO 64);
l0x : out std_logic_vector(1 TO 32);
r0x : out std_logic_vector(1 TO 32)
);
end ip;
architecture behavior of ip is
begin
l0x(1)<=ct(58); l0x(2)<=ct(50); l0x(3)<=ct(42); l0x(4)<=ct(34); l0x(5)<=ct(26); l0x(6)<=ct(18); l0x(7... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.types.all;
ENTITY test_types IS
END test_types;
ARCHITECTURE behavior OF test_types IS
signal tested_num : integer range 0 to 127;
signal tested_num2 : integer range 0 to 127;
signal tested_short_char : short_character;
... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_shadow_ok_8_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
library ieee;
use ieee.std_logic_1164.all;
entity ent is
generic (
g : natural := 8
);
port (
o1 : out std_logic;
o2 : out std_logic
);
end;
architecture a of ent is
constant x : real := real(g);
constant a : natural := g;
constant y : real := real(a);
begin
o1 <= '1' when integer(x) = 8 else '0';
o2 ... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License... |
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribu... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:51:42 01/14/2015
-- Design Name:
-- Module Name: sseg_4x - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:51:42 01/14/2015
-- Design Name:
-- Module Name: sseg_4x - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
component nios_design is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component nios_design;
u0 : component nios_design
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
reset_reset_n => CONNECTED_TO_reset_reset_n -- ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------------------------------------
entity Gate_XNOR is
Port
(
A : in STD_LOGIC;
B : in STD_LOGIC;
Z : out STD_LOGIC
);
end Gate_XNOR;
-------------------------------------------------------... |
-- SIMON 64/128
-- key scheduling function
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- r: round index
-- k_0..k_3: key
-- subkey_out: round subkey
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity key_schedule is
port (
k_in_0 ... |
-- SIMON 64/128
-- key scheduling function
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- r: round index
-- k_0..k_3: key
-- subkey_out: round subkey
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity key_schedule is
port (
k_in_0 ... |
----------------------------------------------------------------------------------------------------
-- ENTITY - Serial In Parallel Out Register
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 29.06.2017
----------------------------------------------------------------------------------------------------
LIBRARY I... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains con... |
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