content stringlengths 1 1.04M ⌀ |
|---|
-------------------------------------------------------------------------------
-- Title : Testbench for design "hall_sensor_decoder"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
----------------------------------------------... |
-------------------------------------------------------------------------------
-- --
-- Module : BRAM_S16_S144.vhd Last Update: --
-- --... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2008 Jiri Gaisler, Jan Andersson, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY... |
-- Inter-Prediction Interpolator Filter
-- see ITU Std. 8.4.2.2.1 and 8.4.2.2.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity inter_core is
generic(
x_len : integer := 4;
y_len : integer := 4;
sample_size : int... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:27:07 2017
-- Host : GILAMONSTER running 64-bit major rel... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity maxfinder is
port (
startaddr : in std_logic_vector(15 downto 0);
len : in std_logic_vector(15 downto 0);
start : in std_logic;
reset_n : in std_logic;
clk : in std_logic;
rddata : i... |
architecture RTL OF ENT is
begin
end RTL;
architecture RTL OF ent is
begin
end rtl;
architecture RTL OF Ent is
begin
end Rtl;
architecture RTL OF ENT is
begin
end;
architecture RTL OF ENT is
begin
end architecture;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:18:54 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit m... |
--------------------------------------------------------------------------------
---
--- CHIPS - 2.0 Simple Web App Demo
---
--- :Author: Jonathan P Dawson
--- :Date: 04/04/2014
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :
--- :Copyright: Copyright (C) Jonathan P Dawson 2014
--- :Modified by Amer... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
-- Date : Tue Jun 30 15:23:02 2015
-- Host : Vangelis-PC running 64-bit major rel... |
-- $Id: sys_tst_snhumanio_b3.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_snhumanio_b3 - syn
-- Descri... |
-- VHDL da interface de entrada e saida do jogo da velha
library ieee;
use ieee.std_logic_1164.all;
entity interface_jogo is
port(
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
jogador : in std_logic;
fim_recepcao ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
entity bug is
end entity;
architecture a of bug is
component cmp is
port(o :out bit_vector);
end component;
signal o:bit_vector(4 downto 0);
begin
i_exp: cmp port map(o);
process(o)
begin
report "o event" severity note;
end process;
end architecture;
entity cmp is
port(o :out bit_vector);
... |
entity bug is
end entity;
architecture a of bug is
component cmp is
port(o :out bit_vector);
end component;
signal o:bit_vector(4 downto 0);
begin
i_exp: cmp port map(o);
process(o)
begin
report "o event" severity note;
end process;
end architecture;
entity cmp is
port(o :out bit_vector);
... |
entity bug is
end entity;
architecture a of bug is
component cmp is
port(o :out bit_vector);
end component;
signal o:bit_vector(4 downto 0);
begin
i_exp: cmp port map(o);
process(o)
begin
report "o event" severity note;
end process;
end architecture;
entity cmp is
port(o :out bit_vector);
... |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' t... |
----------------------------------------------------------------------------------
-- Company: University of Genova
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 14:28:47 10/06/2011
-- Design Name:
-- Module Name: CaosAlAl - Behavioral
-- Project Name:
-- Target Devices:
-- ... |
----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Jan Dürre
-- Year : 2013
-- Description : This example uses adc-channel 0 as gain-control
-- for audio pass-through. Two independent FSMs are
-- required, since the lcd is too slow for 44,1kHz
-- ... |
-------------------------------------------------------------------------------
-- axi_emc_native_interface - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx,... |
-------------------------------------------------------------------------------
-- axi_emc_native_interface - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx,... |
-------------------------------------------------------------------------------
-- axi_emc_native_interface - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx,... |
-------------------------------------------------------------------------------
-- axi_emc_native_interface - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx,... |
-- cpu (EPF10K10TC144-3)
--
-- Copyright (C) 1991-1997 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Alte... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
entity forloop is
end forloop;
architecture behav of forloop is
signal clk : bit;
signal rst : bit := '1';
signal tx : bit;
signal data : bit_vector (7 downto 0);
signal valid : bit;
signal err : bit;
begin
process
procedure pulse is
begin
clk <= '0';
... |
library ieee;
use ieee.std_logic_1164.all;
entity asgn04 is
port (s0 : std_logic;
s1 : std_logic;
r : out std_logic_vector (2 downto 0));
end asgn04;
architecture behav of asgn04 is
begin
process (s0, s1) is
begin
r <= "000";
if s0 = '1' then
r (1) <= '1';
if s1 = '1' then
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--library DesignLab;
--use DesignLab.ALL;
entity Simulate_Your_CCL_Design is
end entity;
architecture sim of Simulate_Your_CCL_Design is
constant period: time := 10 ns;
signal clk: std_logic := '1';
signal ... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is d... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity typeTest is
port (
clk : in std_ulogic;
rst : in std_ulogic;
dataIn : in std_ulogic_vector(7 downto 0);
dataOut : out std_ulogic_vector(7 downto 0)
);
end entity typeTest;
architecture rtl of typeTest is
-- Scalar... |
-- This snippets reports that the specifications of test2 (line 17 and 26) are not identical.
-- Line 17 was generated by line duplication in my editor ... strange
-- Have I missed something?
--
-- PS H:\Austausch\PoC\temp\bugreport> C:\Tools\GHDL.new\bin\ghdl.exe -a -v .\2_SecondaryUnit.vhd
-- .\2_SecondaryUnit.... |
-- This snippets reports that the specifications of test2 (line 17 and 26) are not identical.
-- Line 17 was generated by line duplication in my editor ... strange
-- Have I missed something?
--
-- PS H:\Austausch\PoC\temp\bugreport> C:\Tools\GHDL.new\bin\ghdl.exe -a -v .\2_SecondaryUnit.vhd
-- .\2_SecondaryUnit.... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--- COMMAND
--- =======
---
--- Bits (7:0)
--- ----------
--- (For write byte only) data payload byte
---
--- Bit (8)
--- -------
--- 1 = read byte
--- 0 = write byte
---
--- Bit (9)
--- -------
--- 1 = SEND_START
---
--- Bit (10)
--- --------
--- 1 = SEND_STOP
---
--- Bit (11)
--- --------
--- (For read byte only) 1 =... |
--- COMMAND
--- =======
---
--- Bits (7:0)
--- ----------
--- (For write byte only) data payload byte
---
--- Bit (8)
--- -------
--- 1 = read byte
--- 0 = write byte
---
--- Bit (9)
--- -------
--- 1 = SEND_START
---
--- Bit (10)
--- --------
--- 1 = SEND_STOP
---
--- Bit (11)
--- --------
--- (For read byte only) 1 =... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
-- Date : Sun Mar 8 22:11:52 2015
-- Host : edinburgh running 64-bit Ubuntu 14.1... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
-- Date : Sun Mar 8 22:11:52 2015
-- Host : edinburgh running 64-bit Ubuntu 14.1... |
architecture RTL of FIFO is
constant c_width : integer := 16;
constant x_depth : integer := 512;
constant word : integer := 1024;
begin
end architecture RTL;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- file: patternClk.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not... |
-- file: patternClk.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not... |
-- file: patternClk.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package usb_pkg is
constant c_pid_out : std_logic_vector(3 downto 0) := X"1"; -- token
constant c_pid_in : std_logic_vector(3 downto 0) := X"9"; -- token
constant c_pid_sof : std_logic_vector(3 downt... |
library ieee;
use ieee.std_logic_1164.all;
entity spike_filter is
generic (
g_stable_time : integer := 8 );
port (
clock : in std_logic;
pin_in : in std_logic;
pin_out : out std_logic := '1' );
end spike_filter;
architecture gideon of spike_filter is
signa... |
library ieee;
use ieee.std_logic_1164.all;
entity spike_filter is
generic (
g_stable_time : integer := 8 );
port (
clock : in std_logic;
pin_in : in std_logic;
pin_out : out std_logic := '1' );
end spike_filter;
architecture gideon of spike_filter is
signa... |
library ieee;
use ieee.std_logic_1164.all;
entity spike_filter is
generic (
g_stable_time : integer := 8 );
port (
clock : in std_logic;
pin_in : in std_logic;
pin_out : out std_logic := '1' );
end spike_filter;
architecture gideon of spike_filter is
signa... |
library ieee;
use ieee.std_logic_1164.all;
entity spike_filter is
generic (
g_stable_time : integer := 8 );
port (
clock : in std_logic;
pin_in : in std_logic;
pin_out : out std_logic := '1' );
end spike_filter;
architecture gideon of spike_filter is
signa... |
library ieee;
use ieee.std_logic_1164.all;
entity spike_filter is
generic (
g_stable_time : integer := 8 );
port (
clock : in std_logic;
pin_in : in std_logic;
pin_out : out std_logic := '1' );
end spike_filter;
architecture gideon of spike_filter is
signa... |
library verilog;
use verilog.vl_types.all;
entity altlvds_tx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
registered_input: string := "ON";
multi_clock : string := "OFF";
inclock_period : integer := 10000;
outclock_divide_... |
--Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
--Date : Wed Aug 26 21:30:37 2015
--Host : localhost.localdomain running 64-bit Cent... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/24/2015 01:10:26 PM
-- Design Name:
-- Module Name: Register8Bit2WayOutput - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This fil... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
architecture RTL of FIFO is
begin
FOR_LABEL_GEN : for i in 0 to 7 generate
end generate FOR_LABEL_GEN;
IF_LABEL_GEN : if a = '1' generate
end generate IF_LABEL_GEN;
CASE_LABEL_GEN : case data generate
end generate CASE_LABEL_GEN;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
end ... |
-------------------------------------------------------------------------------
--
-- Module : BRAM_fifo.vhd
--
-- Version : 1.2
--
-- Last Update : 2005-06-29
--
-- Project : Parameterizable LocalLink FIFO
--
-- Descri... |
-- Generated by tools/generate-rom.pl
-- Template: https://www.xilinx.com/support/answers/8183.html
-- But changed manually afterwards
library ieee;
use ieee.std_logic_1164.all;
use work.txt_utils.all;
use work.arch_defs.all;
use work.utils.all;
entity rom_vga is
port ( a: in std_logic_vector(31 downto 0);
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- 0 1 2 3 4 5 6 7 8 9
-- input | | | | | | | | | | |
-- middle | | | | | | | | | | |
-- bottom | | | | | | | | | | |
-- output x| | | | | | | | |x
--
entity gol_processor is
port (
clock : in std_logic;
input : in std_logic_vect... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE is
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
HCLK : in vl_logic;
PSEL : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in ... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE is
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
HCLK : in vl_logic;
PSEL : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in ... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE is
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
HCLK : in vl_logic;
PSEL : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in ... |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
package nco_p is
type nco_input_t is record
dphase : signed(15 downto 0) ;
valid : std_logic ;
end record ;
type nco_output_t is record
re : signed(15 downto 0) ;
im ... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilin... |
-------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual pr... |
library verilog;
use verilog.vl_types.all;
entity gray_counter is
generic(
WIDTH : integer := 8
);
port(
clk : in vl_logic;
reset : in vl_logic;
gray_count : out vl_logic_vector
);
attribute mti_svvh_generic_type : integ... |
-- Descp. decode the 4 bits encoded score to two 4 bits score number, which is needed for the 7 segment display decoder
--4 bit number #### => (num_exact, num_color_matches)
--0000 (4,0)
--0001 (3,0)
--0010 (2,0)
--0011 (2,1)
--0100 (2,2)
--0101 (1,0)
--0110 (1,1)
--0111 (1,2)
--1000 (1,3)
--1001 (0,0)
--1010 (0,1)
--... |
-- abus_slave.vhd
library IEEE;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
-- Demuxed signals
-- Note : naming is Sat... |
-- abus_slave.vhd
library IEEE;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
-- Demuxed signals
-- Note : naming is Sat... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.usb_pkg.all;
entity nano_minimal_io is
generic (
g_support_suspend : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : in unsigned(7... |
entity t3 is
end;
architecture behav of t3 is
constant t1 : time := ps;
begin
assert time'pos(t1) = 1 severity failure;
end behav;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Technology specific Galileo PRN ROM codes
---------------------------------------------------... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Technology specific Galileo PRN ROM codes
---------------------------------------------------... |
--
-- UART transmitter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
package body fifo_pkg is
end fifo_pkg;
package body fifo_pkg is
end fifo_pkg;
package body fifo_pkg is
end;
package body fifo_pkg is
end ;
package body fifo_pkg is
end
;
package body fifo_pkg is
end--Comment
;
|
library IEEE;
use ieee.std_logic_1164.all;
entity test_bench_ripple_adder is
end test_bench_ripple_adder;
architecture behav of test_bench_ripple_adder is
component thirty_two_bit_alu
port(
a, b : in std_logic_vector(31 downto 0);
less, ainvert, binvert, cin : in std_logic;
ALUOp : in std_logic_vector(1 down... |
-- Twofish_ecb_tbl_testbench_128bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any lat... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
--
-- GCpad controller core
--
-- $Id: gcpad_sampler.vhd,v 1.3 2004-10-09 00:33:12 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised ... |
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Softw... |
---------------------------------------------------------------------------------
-- Engineer: Klimann Wendelin
--
-- Create Date: 07:25:11 11/Okt/2013
-- Design Name: clk_gen
--
-- Description:
--
-- This module is a simple clock divider which generates the BIT_CLK and the LR_CLK
-- signals for the I2S in... |
library ieee;
use ieee.std_logic_1164.all;
entity Lab7a is
port (
LEDR: out std_logic_vector(3 downto 0);
KEY: in std_logic_vector(1 downto 0);
HEX0: out std_logic_vector(6 downto 0)
);
end Lab7a;
architecture Lab7a_beh of Lab7a is
signal F: std_logic_vector(3 downto 0);
component FSM_Conta -- Esse e’ o compon... |
library ieee;
use ieee.std_logic_1164.all;
entity Lab7a is
port (
LEDR: out std_logic_vector(3 downto 0);
KEY: in std_logic_vector(1 downto 0);
HEX0: out std_logic_vector(6 downto 0)
);
end Lab7a;
architecture Lab7a_beh of Lab7a is
signal F: std_logic_vector(3 downto 0);
component FSM_Conta -- Esse e’ o compon... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 01:40:38 2017
-- Host : GILAMONSTER running 64-bit major rel... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: tcp_engine_add_data - Behavioral
--
-- Description: Add the data stream alongsude the packet header
--
-------------------------------------------------------------------... |
------------------------------------------------------------------------------
-- "numeric_std_additions" package contains the additions to the standard
-- "numeric_std" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic... |
------------------------------------------------------------------------------
-- "numeric_std_additions" package contains the additions to the standard
-- "numeric_std" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic... |
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- See list of changes in T65 top file (T65.vhd)...
--
-- ****
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65_Pack.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- ... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library verilog;
use verilog.vl_types.all;
entity simpleCPU is
port(
clk : in vl_logic;
rst : in vl_logic;
IMR : in vl_logic;
instr2load : in vl_logic_vector(31 downto 0);
loadAdx : in vl_logic_vector(6 down... |
----------------------------------------------------------------------------------
-- ------------------- --
-- | | --
-- | Z0 |--------- Z0 ... |
-------------------------------------------------------------------------------
--! @file PreProcessor.vhd
--! @brief Pre-processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptograp... |
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