content stringlengths 1 1.04M ⌀ |
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
-- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later v... |
----------------------------------------------------------------------------------------------
--
-- Input file : core_address_decoder.vhd
-- Design name : core_address_decoder
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- ... |
----------------------------------------------------------------------------------------------
--
-- Input file : core_address_decoder.vhd
-- Design name : core_address_decoder
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: buffer_count_and_checksum_data - Behavioral
--
-- Description: Count and checksum the data to be put into a UDP or TCP packet
--
----------------------------------------... |
---------------------------------------------------------------------------------------------
-- VIDEO DELAY - AD, DA Converter
--
-- Part of the Synkie Project: www.synkie.net
--
-- © 2013 Michael Egger, Licensed under GNU GPLv3
--
---------------------------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
fpga_0_DDR2_SDRAM_DDR2_Clk_... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:20 2017
-- Host : KLight-PC running 64-bit major relea... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- The MIT License (MIT)
-- Copyright (c) 2014 Shuo Li
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, c... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "comparator_module"
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Standard : VHDL'87
------------------------------... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "comparator_module"
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Standard : VHDL'87
------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Bug-Reproducer: Sorting Network: ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Bug-Reproducer: Sorting Network: ... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/TWDLMULT_SDNF1_3_block4.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ----------------------... |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.iec_bus_bfm_pkg.all;
use work.flat_memory_model.all;
entity testcase_format is
end testcase_format;
architecture tb of testcase_format is
begin
test: process
variable iec : p_iec_bus_bfm_object;
variable ram : h_m... |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.iec_bus_bfm_pkg.all;
use work.flat_memory_model.all;
entity testcase_format is
end testcase_format;
architecture tb of testcase_format is
begin
test: process
variable iec : p_iec_bus_bfm_object;
variable ram : h_m... |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.iec_bus_bfm_pkg.all;
use work.flat_memory_model.all;
entity testcase_format is
end testcase_format;
architecture tb of testcase_format is
begin
test: process
variable iec : p_iec_bus_bfm_object;
variable ram : h_m... |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.iec_bus_bfm_pkg.all;
use work.flat_memory_model.all;
entity testcase_format is
end testcase_format;
architecture tb of testcase_format is
begin
test: process
variable iec : p_iec_bus_bfm_object;
variable ram : h_m... |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.iec_bus_bfm_pkg.all;
use work.flat_memory_model.all;
entity testcase_format is
end testcase_format;
architecture tb of testcase_format is
begin
test: process
variable iec : p_iec_bus_bfm_object;
variable ram : h_m... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity rgb_buf is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(7 downto 0... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity rgb_buf is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(7 downto 0... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00126
--
-- AUTHOR:
--
-- G. Tomi... |
architecture RTL of FIFO is
type state_machine is (idle, write, read, done);
signal sig1 : std_logic;
-- Violations below
type state_machine is (idle, write, read, done);
signal sig1 : std_logic;
begin
end architecture RTL;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _ ... |
-- NEED RESULT: *** An assertion follows with severity level WARNING
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
---------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: compute_squared_sums - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
---------------------------------------... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_programCounterAdder IS
END tb_programCounterAdder;
ARCHITECTURE behavior OF tb_programCounterAdder IS
--Inputs
SIGNAL tb_programCounterIn : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
--Outputs
SIGNAL tb_programCounterOut : std_logic_vector(31 DOWNTO 0);
BE... |
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity bufr_test is
end entity;
architecture test of bufr_test is
component BUFR
generic ( BUFR_DIVIDE : string := "BYPASS";
SIM_DEVICE : string := "7SERIES");
port ( O : out STD... |
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity bufr_test is
end entity;
architecture test of bufr_test is
component BUFR
generic ( BUFR_DIVIDE : string := "BYPASS";
SIM_DEVICE : string := "7SERIES");
port ( O : out STD... |
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity bufr_test is
end entity;
architecture test of bufr_test is
component BUFR
generic ( BUFR_DIVIDE : string := "BYPASS";
SIM_DEVICE : string := "7SERIES");
port ( O : out STD... |
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity bufr_test is
end entity;
architecture test of bufr_test is
component BUFR
generic ( BUFR_DIVIDE : string := "BYPASS";
SIM_DEVICE : string := "7SERIES");
port ( O : out STD... |
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity bufr_test is
end entity;
architecture test of bufr_test is
component BUFR
generic ( BUFR_DIVIDE : string := "BYPASS";
SIM_DEVICE : string := "7SERIES");
port ( O : out STD... |
architecture rtl of fifo is
constant cons1 : t_type :=
(
1 => func1(std_logic_vector(G_GEN), G_GEN2),
2 => func1(std_logic_vector(G_GEN3), G_GEN4)
);
constant cons1 : t_type :=
(
1 => func1(std_logic_vector(G_GEN), G_GEN2),
2 => func1(
std_logic_vector(G_GEN3), G_GEN4)
);
constant cons1 : t... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use s... |
----------------------------------------------------
-- Vladi & Adi --
-- TAU EE Senior year project --
-- --
--************************************************--
--************* Distortion /Overdrive ************--
--... |
-- REG8
-- 8 bit register file
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity reg8 is
port(D: in std_logic_vector(7 downto 0);
EN: in std_logic;
CLK: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end reg8;
architecture logic of reg8 is
begin
process(CLK, EN)... |
-- REG8
-- 8 bit register file
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity reg8 is
port(D: in std_logic_vector(7 downto 0);
EN: in std_logic;
CLK: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end reg8;
architecture logic of reg8 is
begin
process(CLK, EN)... |
-- REG8
-- 8 bit register file
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity reg8 is
port(D: in std_logic_vector(7 downto 0);
EN: in std_logic;
CLK: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end reg8;
architecture logic of reg8 is
begin
process(CLK, EN)... |
-- REG8
-- 8 bit register file
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity reg8 is
port(D: in std_logic_vector(7 downto 0);
EN: in std_logic;
CLK: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end reg8;
architecture logic of reg8 is
begin
process(CLK, EN)... |
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
-- Revision 0.02 - Added type definitions (store and network) for arpv2
library IEEE;
use IEE... |
--
-- Copyright (C) 2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This progr... |
Library ieee;
Use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity control_entity is
port (
op_code: in std_logic_vector(4 downto 0);
nop_enable:in std_logic; --nop operation enable for load & store
pc_mux : out std_logic_vector(1 downto 0);
inport_en : out std_logic;
outport_en :... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity test is
package a is new b generic map(c => foo(0 to 2));
end;
|
-- file: pll_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_saturation_eneOg_DSP48_1 is
port (
a: in std_logic_vector(20 - 1 downto 0);
b: in std_logic_vector(8 - 1 downto 0);
p: out std_logic_vector(28 - 1 downto 0));
end entity;
architecture behav of hls_saturation_eneOg_DSP48_1 is... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Title : Sine Generator, only for simulation
-------------------------------------------------------------------------------
-- File : SinGen-Bhv-ea.vhd
-- Author : Franz Steinbacher
----------------------------------------... |
-------------------------------------------------------------------------------
-- Title : 8x1 Pixel Controller
-------------------------------------------------------------------------------
-- Author : cjt@users.sourceforge.net
-------------------------------------------------------------------------------
-... |
--accm
-- ************************************
-- Automatically Generated FSM
-- IDEA_chan
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
entity agg3 is
end entity;
architecture test of agg3 is
type int_array is array (integer range <>) of integer;
function get_array return int_array is
begin
return (4 => 4, 3 => 3, 5 => 5);
end function;
begin
process is
variable x : int_array(1 to 3) := (others => 5);
vari... |
entity agg3 is
end entity;
architecture test of agg3 is
type int_array is array (integer range <>) of integer;
function get_array return int_array is
begin
return (4 => 4, 3 => 3, 5 => 5);
end function;
begin
process is
variable x : int_array(1 to 3) := (others => 5);
vari... |
entity agg3 is
end entity;
architecture test of agg3 is
type int_array is array (integer range <>) of integer;
function get_array return int_array is
begin
return (4 => 4, 3 => 3, 5 => 5);
end function;
begin
process is
variable x : int_array(1 to 3) := (others => 5);
vari... |
entity agg3 is
end entity;
architecture test of agg3 is
type int_array is array (integer range <>) of integer;
function get_array return int_array is
begin
return (4 => 4, 3 => 3, 5 => 5);
end function;
begin
process is
variable x : int_array(1 to 3) := (others => 5);
vari... |
entity agg3 is
end entity;
architecture test of agg3 is
type int_array is array (integer range <>) of integer;
function get_array return int_array is
begin
return (4 => 4, 3 => 3, 5 => 5);
end function;
begin
process is
variable x : int_array(1 to 3) := (others => 5);
vari... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
------------------------------------------------------... |
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