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---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 21:11:48 12/23/2015 -- Design Name: -- Module Name: datapath - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revisi...
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 21:11:48 12/23/2015 -- Design Name: -- Module Name: datapath - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revisi...
use std.textio.all; entity top_ent is end entity; architecture default of top_ent is file fh : text; begin process begin if endfile(fh) then null; end if; end process; end architecture;
-- ------------------------------------------------------------- -- -- Generated Architecture Declaration for rtl of ent_t -- -- Generated -- by: wig -- on: Tue Jul 4 05:34:51 2006 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../configuration.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Auth...
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library basic_library; entity foo is generic ( DIVIDER_A : integer := 10; DIVIDER_B : integer := 20 ); port ( rst_a, clk_in_a : in std_logic; clk_out_a : out std_logic; rst_b, clk_in_b : ...
-- ------------------------------------------------------------- -- -- Generated Configuration for inst_a_e -- -- Generated -- by: wig -- on: Wed Jul 19 05:22:48 2006 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../logic.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_...
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify i...
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify i...
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify i...
library ieee; -- Commonly imported packages: -- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions use ieee.std_logic_1164.all; -- SIGNED and UNSIGNED types, and relevant functions use ieee.numeric_std.all; -- Basic sequential functions and concurrent procedures use ieee.VITAL_Primitives.all; package DE2...
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify i...
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify i...
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify i...
LIBRARY IEEE; USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all; entity test is generic( rst_val : std_logic := '0'; thing_size: integer := 201; bus_width : integer := 201 mod 32); port( clk, rstn : in std_logic; en, start_dec : in std_logic; addr : in std_logic_vector(2 d...
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your o...
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your o...
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your o...
---------------------------------------------------------------------------------- -- Company:LAAS-CNRS -- Author:Jonathan Piat <piat.jonathan@gmail.com> -- -- Create Date: 20:17:12 04/14/2012 -- Design Name: -- Module Name: generic_latch - Behavioral -- Project Name: -- Target Devices: Spartan 6 ...
---------------------------------------------------------------------------------- -- Company:LAAS-CNRS -- Author:Jonathan Piat <piat.jonathan@gmail.com> -- -- Create Date: 20:17:12 04/14/2012 -- Design Name: -- Module Name: generic_latch - Behavioral -- Project Name: -- Target Devices: Spartan 6 ...
-- CTRL_TELEGRAM_CHECK -- Profibus Telegramtyp ermitteln, aktuelle Laenge und Telegram komplett anzeigen -- Projekt: PROFIBUS MONITOR -- Ersteller: Martin Harndt -- Erstellt: 02.01.2013 -- Bearbeiter: mharndt -- Geaendert: 28.01.2013 -- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi...
-- CTRL_TELEGRAM_CHECK -- Profibus Telegramtyp ermitteln, aktuelle Laenge und Telegram komplett anzeigen -- Projekt: PROFIBUS MONITOR -- Ersteller: Martin Harndt -- Erstellt: 02.01.2013 -- Bearbeiter: mharndt -- Geaendert: 28.01.2013 -- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi...
-- CTRL_TELEGRAM_CHECK -- Profibus Telegramtyp ermitteln, aktuelle Laenge und Telegram komplett anzeigen -- Projekt: PROFIBUS MONITOR -- Ersteller: Martin Harndt -- Erstellt: 02.01.2013 -- Bearbeiter: mharndt -- Geaendert: 28.01.2013 -- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi...
-- CTRL_TELEGRAM_CHECK -- Profibus Telegramtyp ermitteln, aktuelle Laenge und Telegram komplett anzeigen -- Projekt: PROFIBUS MONITOR -- Ersteller: Martin Harndt -- Erstellt: 02.01.2013 -- Bearbeiter: mharndt -- Geaendert: 28.01.2013 -- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi...
------------------------------------------------------------------------------- --! @project Unrolled (factor 2) hardware implementation of Asconv128128 --! @author Michael Fivez --! @license This project is released under the GNU Public License. --! The license and distribution terms for this...
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant ...
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the...
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify i...
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify i...
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify i...
-- 500 variable assigns in 2 processes. GHC works here. entity main is end entity main; architecture arch of main is signal clk : integer := 0; constant CYCLES : integer := 1000; begin main: process(clk) --{{{ variable a0502 : integer; variable a0503 : integer; variable a0504 : integer; variable a0505 : i...
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:03:22 11/13/2015 -- Design Name: -- Module Name: C:/Users/Gham/Desktop/Actual files/IDE/IDE3_final/IDE_READ/read_tb.vhd -- Project Name: IDE_READ -- Target Device: -- Tool versions:...
-- megafunction wizard: %RAM: 2-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: RAM_1.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ====================...
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...
-- Copyright (C) 1991-2011 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated docume...
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015 - 2016, Cobham Gaisler -- -- This program is free software; you can ...
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library ftl; use ftl.ftlbase.all; use work.comp_tslink_ct.all; entity tslink is port ( clk : in std_ulogic; rst : in std_ulogic; LinkIn : in std_ulogic; IValid : in std_ulogic; QAck : in std_ulogic; IData : in std_logic_vec...
-- ------------------------------------------------------------- -- -- Generated Architecture Declaration for rtl of inst_eda_e -- -- Generated -- by: wig -- on: Mon Mar 22 13:27:43 2004 -- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls -- -- !!! Do not edit this file! Autogenerated by MIX !...
-- NEED RESULT: ARCH00367.P1: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00367: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00367: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: P1: Transport ...
library verilog; use verilog.vl_types.all; entity finalproject_cpu_nios2_oci_debug is port( clk : in vl_logic; dbrk_break : in vl_logic; debugreq : in vl_logic; hbreak_enabled : in vl_logic; jdo : in vl_logic_vector(37 ...
-- --ROMsUsingBlockRAMResources. --VHDLcodeforaROMwithregisteredoutput(template2) -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity os8 is port( clock:in std_logic; address:in std_logic_vector(12 downto 0); q:out std_logic_vector(7 downto 0) ); end os8; arc...
package STRSYN is attribute SigDir : string; attribute SigType : string; attribute SigBias : string; end STRSYN; entity op is port ( terminal in1: electrical; terminal in2: electrical; terminal out1: electrical; terminal vbias4: electrical; terminal gnd: electrical; termina...
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015 - 2016, Cobham Gaisler -- -- This program is free software; you can ...
-- Returns the sine of a value from 0 to 1 (scaled as - to sine_addr_max) -- -- The lookup table actually stores the first quarter of each sine wave, so -- this entity transforms the stored first quarter to be able to calculate the -- sine of any quarter of the wave. The following graph shoes the relation -- between i...
entity proc8 is end entity; architecture test of proc8 is type int_vec is array (integer range <>) of integer; subtype int_vec4 is int_vec(1 to 4); procedure p1(signal y : in int_vec) is begin for i in y'range loop report integer'image(y(i)); end loop; end procedure; ...
entity proc8 is end entity; architecture test of proc8 is type int_vec is array (integer range <>) of integer; subtype int_vec4 is int_vec(1 to 4); procedure p1(signal y : in int_vec) is begin for i in y'range loop report integer'image(y(i)); end loop; end procedure; ...
entity proc8 is end entity; architecture test of proc8 is type int_vec is array (integer range <>) of integer; subtype int_vec4 is int_vec(1 to 4); procedure p1(signal y : in int_vec) is begin for i in y'range loop report integer'image(y(i)); end loop; end procedure; ...
entity proc8 is end entity; architecture test of proc8 is type int_vec is array (integer range <>) of integer; subtype int_vec4 is int_vec(1 to 4); procedure p1(signal y : in int_vec) is begin for i in y'range loop report integer'image(y(i)); end loop; end procedure; ...
entity proc8 is end entity; architecture test of proc8 is type int_vec is array (integer range <>) of integer; subtype int_vec4 is int_vec(1 to 4); procedure p1(signal y : in int_vec) is begin for i in y'range loop report integer'image(y(i)); end loop; end procedure; ...
---------------------------------------------------------------------- ---- ---- ---- WISHBONE SPDIF IP Core ---- ---- ---- ---- This file is part of the SPDIF ...
-- NEED RESULT: ARCH00072.P1: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00072.P2: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00072.P3: Multi transport transactions occurred on signal asg with simpl...
-- ------------------------------------------------------------- -- -- Generated Architecture Declaration for rtl of a_clk -- -- Generated -- by: wig -- on: Mon Jul 18 15:46:40 2005 -- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Au...
------------------------------------------------------------------------------- --! @file hostInterface.vhd -- --! @brief toplevel of host interface -- --! @details The toplevel instantiates the necessary components for the --! host interface like the Dynamic Bridge and the Status-/Control Registers. -- ---------------...
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity tuberom_pdp11 is port ( CLK : in std_logic; ADDR : in std_logic_vector(9 downto 0); DATA : out std_logic_vector(15 downto 0) ); end; architecture RTL of tuberom_pdp11 is signal rom_addr : std_logic_...
-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; -----------------------------------------------------------------------------------------------...
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Tue May 30 11:58:28 2017 -- Host : GILAMONSTER running 64-bit major rel...
-- nios_dut_rst_controller.vhd -- Generated using ACDS version 15.1 185 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nios_dut_rst_controller is generic ( NUM_RESET_INPUTS : integer := 1; OUTPUT_RESET_SYNC_EDGES : string := "deassert"; SYNC_DEPTH : inte...
-- -- sort8k.vhd -- eCos hardware thread using the bubble_sort module and mailboxes to -- sort 8k-sized blocks of data in main memory. The incoming messages -- on C_MB_START contain the addresses of the blocks, and an arbitrary -- message sent to C_MB_DONE signals completion of the sorting process. -- -- Author: E...
architecture RTL of ENTITY_NAME is type T_FLAG_TYPE is protected body -- protected type declaration procedure init (foo : real); impure function myfunct return boolean; constant c_con1 : std_logic; variable v_var1 : integer; end protected body T_FLAG_TYPE; begin end architecture RTL;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.myTypes.all; entity mux41 is generic ( MUX_SIZE : integer := 32 ); port ( IN0 : in std_logic_vector(MUX_SIZE - 1 downto 0); IN1 : in std_logic_vector(MUX_SIZE - 1 downto 0); IN2 : in std_logic_vector(MUX_SIZE - 1 downto 0); IN3 : ...
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.myTypes.all; entity mux41 is generic ( MUX_SIZE : integer := 32 ); port ( IN0 : in std_logic_vector(MUX_SIZE - 1 downto 0); IN1 : in std_logic_vector(MUX_SIZE - 1 downto 0); IN2 : in std_logic_vector(MUX_SIZE - 1 downto 0); IN3 : ...
---------------------------------------------------------------------------------- -- Company: University of Queensland -- Engineer: MDS -- -- Create Date: 25/07/2014 -- Design Name: -- Module Name: pracTop - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -...
-- NEED RESULT: This should only come out once -- NEED RESULT: *** An assertion with report = 'This should only come out once' and severity level = 'Note' ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All right...
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity b is port( clk : in std_logic; din_enable : in std_logic; din_value : in unsigned(15 downto 0); dout_enable : out std_logic; dout_value : out unsigned(15 downto 0) ); end b; architecture b_archi1 of ...
-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and prop...
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cpu6502 is port ( cpu_clk : in std_logic; cpu_clk_en : in std_logic; cpu_reset : in std_logic; cpu_write : out std_logic; cpu_wdata : out std_logic_vector(7 downto 0); cpu_rda...
------------------------------------------------------------------------------- --! @file AEAD.vhd --! @brief Top-level template of authenticated encryption unit. --! --! @project CAESAR Candidate Evaluation --! @author Ekawat (ice) Homsirikamol --! @copyright Copyright (c) 2015 Cryptographic Enginee...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain t...