content stringlengths 1 1.04M ⌀ |
|---|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c)... |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c)... |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c)... |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c)... |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c)... |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c)... |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c)... |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c)... |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level of authenticated encryption unit containing logic and memory region.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c)... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright ... |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; top level ----
---- ----
---- ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
component wasca is
port (
abus_avalon_sdram_bridge_0_abus_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
abus_avalon_sdram_bridge_0_abus_read : in std_logic := 'X'; -- read
abus_avalon_sdram_bridge_0_abus_data ... |
-- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your opt... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - ... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 17, 2017
--! @brief Contains the package and component declaration of the
--! Plasma-SoC's UART Core. Please refer to the documentation
--! in plasoc_uart.vhd for more information.
----------------------------------------... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_a
--
-- Generated
-- by: wig
-- on: Fri Jun 9 05:15:53 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../highlow.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wi... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_bb_e
--
-- Generated
-- by: wig
-- on: Wed Apr 5 12:50:28 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id... |
architecture RTL of FIFO is
procedure proc1 is
begin
end procedure proc1;
signal wr_en : std_logic;
-- Violations follow
procedure proc1 is
begin
end procedure proc1;
signal wr_en : std_logic;
begin
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use work.init_funcs.all;
use std.textio.all;
entity test_vga_system is
end test_vga_system;
architecture behavioural of test_vga_system is
component VGA_system is
generic (
display_rows : natural := 480;
display_cols : natural := 640
);
port (
... |
library ieee;
use ieee.std_logic_1164.all;
use work.init_funcs.all;
use std.textio.all;
entity test_vga_system is
end test_vga_system;
architecture behavioural of test_vga_system is
component VGA_system is
generic (
display_rows : natural := 480;
display_cols : natural := 640
);
port (
... |
--------------------------------------------------------------------------------
-- Entity: dm_simple
-- Date: 2014-12-08
-- Author: Gideon
--
-- Description: Simple direct mapped cache controller, compatible with the
-- I/D buses of the mblite
------------------------------------------------------... |
entity loop2 is
end entity;
architecture test of loop2 is
procedure p3(t : in time) is
begin
loop
if t >= 1 ps then
return;
end if;
end loop;
end procedure;
begin
end architecture;
|
entity loop2 is
end entity;
architecture test of loop2 is
procedure p3(t : in time) is
begin
loop
if t >= 1 ps then
return;
end if;
end loop;
end procedure;
begin
end architecture;
|
entity loop2 is
end entity;
architecture test of loop2 is
procedure p3(t : in time) is
begin
loop
if t >= 1 ps then
return;
end if;
end loop;
end procedure;
begin
end architecture;
|
entity loop2 is
end entity;
architecture test of loop2 is
procedure p3(t : in time) is
begin
loop
if t >= 1 ps then
return;
end if;
end loop;
end procedure;
begin
end architecture;
|
entity loop2 is
end entity;
architecture test of loop2 is
procedure p3(t : in time) is
begin
loop
if t >= 1 ps then
return;
end if;
end loop;
end procedure;
begin
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity processor is
port ( address : out std_logic_vector (15 downto 0);
Pstrobe : out std_logic;
Prw : out std_logic;
Pready : in std_logic;
Pdata : inout std_logic_vector (32 downto 0));
end processor; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--===========================================================================--
-- --
-- Synthesizable Character Generator using Xilinx RAMB16_S9 Block RAM --
-- --
... |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' t... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20... |
-------------------------------------------------------------------------------
--! @file AEAD_pkg.vhd
--! @brief Package used for authenticated encyryption
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Resea... |
-- $Id: tb_tst_serloop.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either versio... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity REP is port(
a: in std_logic;
z: out std_logic
);
end REP;
--
architecture REP of REP is
begin
z <= a;
end REP; |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Tue Jun 06 02:30:20 2017
--Host : GILAMONSTER running 64-bit major release ... |
----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 13:41:21 06/19/2016
------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FLOW is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OPCODE : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
ROW_A : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_B : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_C : IN STD_LOGIC_VECTOR(9 downto ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FLOW is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OPCODE : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
ROW_A : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_B : IN STD_LOGIC_VECTOR(9 downto 0);
ROW_C : IN STD_LOGIC_VECTOR(9 downto ... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library ieee;
use ieee.std_logic_1164.all;
package eclipse_components is
component RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end co... |
library ieee;
use ieee.std_logic_1164.all;
package eclipse_components is
component RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end co... |
library ieee;
use ieee.std_logic_1164.all;
package eclipse_components is
component RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end co... |
library ieee;
use ieee.std_logic_1164.all;
package eclipse_components is
component RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end co... |
library ieee;
use ieee.std_logic_1164.all;
package eclipse_components is
component RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end co... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
use work.PIC_pkg.all;
use work.RS232_test.all;
entity PICtop_tb is
end PICtop_tb;
architecture TestBench of PICtop_tb is
component PICtop
port (
Reset : in std_logic;
Clk : in std_l... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:26:46 02/24/2015
-- Design Name:
-- Module Name: rc_shr - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
-... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/TWDLMULT_SDNF1_3_block6.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -----------------------------------... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:54:25 2017
-- Host : GILAMONSTER running 64-bit major rel... |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity uart is
port (
-- FPGA internal interface to the TX and RX FIFOs
clock : in std_logic ;
reset : in std_logic ;
enable : in std_logic ;
-- RS232 interface
rs232_rxd ... |
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectua... |
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectua... |
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectua... |
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectua... |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Elod Gyorgy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Dat... |
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implem... |
-------------------------------------------------------------------------------
-- Company : HSLU, Waj
-- Create Date: 20-Apr-12
-- Project : ECS, Uebung 2
-- Description: Testbench for enable gate with configuration selection
------------------------------------------------------------------------------... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (lin64) Build 1215546 Mon Apr 27 19:07:21 MDT 2015
-- Date : Fri Sep 18 12:15:17 2015
-- Host : parallella running 64-bit Ubuntu 14.... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2009 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler... |
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
entity tb is
end;
architecture rtl of tb is
component top is
port( clk : in std_logic;
reset : in std_logic;
red : out std_logic_vector(2 downto 0);
green : out std_logic_vector(2 downto 0)... |
package pkg is
procedure proc(length : integer);
end package;
package body pkg is
procedure proc(length : integer) is
-- Runtime error
variable bv : bit_vector(length-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
end procedure;
end package body;
use work.pkg.... |
package pkg is
procedure proc(length : integer);
end package;
package body pkg is
procedure proc(length : integer) is
-- Runtime error
variable bv : bit_vector(length-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
end procedure;
end package body;
use work.pkg.... |
package pkg is
procedure proc(length : integer);
end package;
package body pkg is
procedure proc(length : integer) is
-- Runtime error
variable bv : bit_vector(length-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
end procedure;
end package body;
use work.pkg.... |
package pkg is
procedure proc(length : integer);
end package;
package body pkg is
procedure proc(length : integer) is
-- Runtime error
variable bv : bit_vector(length-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
end procedure;
end package body;
use work.pkg.... |
package pkg is
procedure proc(length : integer);
end package;
package body pkg is
procedure proc(length : integer) is
-- Runtime error
variable bv : bit_vector(length-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
end procedure;
end package body;
use work.pkg.... |
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "... |
-------------------------------------------------------------------------------
--! @file nf_top.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-02-24
--! @brief FGClite NanoFIP FPGA (NF) top-level.
------------------------------------------------... |
--
-- SpaceWire Transmitter
--
-- This entity translates outgoing characters and tokens into
-- data-strobe signalling.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spwpkg.all;
entity spwxmit is
port (
-- System clock.
clk: in std_logic;
-- ... |
--
-- SpaceWire Transmitter
--
-- This entity translates outgoing characters and tokens into
-- data-strobe signalling.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spwpkg.all;
entity spwxmit is
port (
-- System clock.
clk: in std_logic;
-- ... |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Wed Aug 17 14:15:47 2016
--Host : andrewandrepowell2-desktop running 64-bit... |
entity Latch is
port (
Din: in Word;
Dout: out Word;
Load: in Bit;
Clk: in Bit);
constant Setup: Time := 12 ns;
constant PulseWidth: Time := 50 ns;
use Work.TimingMonitors.all;
begin
assert Clk='1' or Clk'Delayed'Stable (PulseWidth);
CheckTiming (Setup, Din, Load, Clk);
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:21:30 03/04/2017
-- Design Name:
-- Module Name: gal_progcounter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependen... |
-- megafunction wizard: %LPM_DIVIDE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_DIVIDE
-- ============================================================
-- File Name: Divider.vhd
-- Megafunction Name(s):
-- LPM_DIVIDE
--
-- Simulation Library Files(s):
-- lpm
-- =========================... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity SeqDetector is
port( CLOCK_50 : in std_logic;
SW : in std_logic_vector(0 downto 0);
LEDR : out std_logic_vector(0 downto 0);
LEDG : out std_logic_vector(0 downto 0));
end SeqDetector;
architecture Shell of SeqDetector is
signal s_clk : std_logic;
be... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:57:17 11/20/2014
-- Design Name:
-- Module Name: ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision: ... |
entity operator3 is
end entity;
architecture test of operator3 is
type int_array is array (integer range <>) of integer;
begin
process is
variable x : int_array(1 to 3);
variable y : bit_vector(1 to 3);
begin
x := (1, 2, 3);
assert x < (2, 2, 3);
assert x > (0, 0, 0... |
entity operator3 is
end entity;
architecture test of operator3 is
type int_array is array (integer range <>) of integer;
begin
process is
variable x : int_array(1 to 3);
variable y : bit_vector(1 to 3);
begin
x := (1, 2, 3);
assert x < (2, 2, 3);
assert x > (0, 0, 0... |
entity operator3 is
end entity;
architecture test of operator3 is
type int_array is array (integer range <>) of integer;
begin
process is
variable x : int_array(1 to 3);
variable y : bit_vector(1 to 3);
begin
x := (1, 2, 3);
assert x < (2, 2, 3);
assert x > (0, 0, 0... |
entity operator3 is
end entity;
architecture test of operator3 is
type int_array is array (integer range <>) of integer;
begin
process is
variable x : int_array(1 to 3);
variable y : bit_vector(1 to 3);
begin
x := (1, 2, 3);
assert x < (2, 2, 3);
assert x > (0, 0, 0... |
entity operator3 is
end entity;
architecture test of operator3 is
type int_array is array (integer range <>) of integer;
begin
process is
variable x : int_array(1 to 3);
variable y : bit_vector(1 to 3);
begin
x := (1, 2, 3);
assert x < (2, 2, 3);
assert x > (0, 0, 0... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file... |
------------------------------------------------------------------------------
---- ----
---- I2C Master Core (Byte Controller) ----
---- ----
----... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 14:57:12 07/30/2009
-- Design Name:
-- Module Name: Comp_ClockGen - Behavioral
-- Project Name: Clock Generator
-- Target Devices:
-- Tool versions:
-- Descript... |
--accm
-- ************************************
-- Automatically Generated FSM
-- IDEA_chan
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee... |
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