content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity train11_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end train11_jed;
architecture behaviour of train11_jed is
constant st0: std_logic_vector(3 downt... |
-- file: timer.vhd
--
-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
package real1 is
function approx(x, y : real; t : real := 0.001) return boolean;
end package;
package body real1 is
function approx(x, y : real; t : real := 0.001) return boolean is
begin
return abs(x - y) < t;
end function;
end package body;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
entity router_channel is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 5;
Rxy_rst : integer :=... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity noc_interface is
generic(
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8;
use_... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- Math Libraries
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY alu_component IS
PORT ( dataSource0, dataSource1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
opcode : IN STD_LOGIC;
dataOutput : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END alu_componen... |
-- $Id: ram_1swar_1ar_gen.vhd 422 2011-11-10 18:44:06Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, ... |
-- $Id: ram_1swar_1ar_gen.vhd 422 2011-11-10 18:44:06Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
entity test is
end entity test;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
architecture rtl of test is
FUNCTION test
RETURN std_ulogic_vector IS
SUBTYPE vector_t IS std_ulogic_vector(0 TO 3);
BEGIN
RETURN vector_t'(OTHERS => '0');
END test;
begin
end architecture r... |
entity test is
end entity test;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
architecture rtl of test is
FUNCTION test
RETURN std_ulogic_vector IS
SUBTYPE vector_t IS std_ulogic_vector(0 TO 3);
BEGIN
RETURN vector_t'(OTHERS => '0');
END test;
begin
end architecture r... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Library Clause(s) (optional)
-- Use Clause(s) (optional)
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.filter_shared_package.all;
entity filter_mac_datapath is
generic
(
-- Multiplier and Adder Pipeline Lengths
FPMULT_PIPE_LENGTH : P_T := PM;
... |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dqINST_lb.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ========================... |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dqINST_lb.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ========================... |
-- NEED RESULT: ARCH00573: Library unit is visible passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
DRTS: in std_logic; ... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test2 is
port(
d_in: in std_ulogic_vector(63 downto 0);
d_out: out std_ulogic_vector(63 downto 0)
);
end entity test2;
architecture behaviour of test2 is
begin
comb : process(all)
begin
d_out <= std... |
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_ab
--
-- Generated
-- by: wig
-- on: Wed Nov 2 10:48:49 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
--... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity neuron_hid is
port ( clk : in std_logic;
ce : in std_logic;
sclr : in std_logic;
bypass : in std_logic;
im : in std_logic_vector(7 downto 0);
weig_hid : in std_logic_vector( 7 downto 0);
hid_out : out std_logic_vector... |
-- $Id: nexys4lib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: nexys4lib
-- Description: Nexys 4 components... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =========================================================================================================================================================... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =========================================================================================================================================================... |
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.physical.all;
entity sdrc_queens_master is
generic (
-- Design Parameters
N : positive := 27;
L : positive := 2;
SOLVERS : positive := 90;
COUNT_CYCLES : boolean := false;
-- Local Clock Parameters
CLK_FREQ : FREQ :... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- $Id: tb_w11a_br_n4d.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_w11a_br_n4d
-- Description: Configuratio... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- Modular timer
constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
constant CFG_G... |
-- Modular timer
constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
constant CFG_G... |
-- Modular timer
constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
constant CFG_G... |
-- Modular timer
constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
constant CFG_G... |
-- Modular timer
constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
constant CFG_G... |
-- Modular timer
constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
constant CFG_G... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt";
uart_support : string := "yes"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
int_in: in std_logic;
uart_read: in std_log... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:11:18 2017
-- Host : EffulgentTome running 64-bit maj... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
--*****************************************************************************
-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... |
entity bounds18 is
end entity;
architecture test of bounds18 is
function func(x : bit_vector(1 to 5)) return bit is
begin
return x(1) and x(5);
end function;
procedure proc(n : positive) is
variable v : bit_vector(1 to n);
begin
assert func(v) = '0';
end procedure;
be... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/20/2015 05:54:19 PM
-- Design Name:
-- Module Name: SHL8Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
... |
architecture rtl of fifo is
constant sig8 : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0)
,
elementB(3 downto 0)),
element3(3 downto 0)(elementC(4 downto 1), elementD(1 downto 0)),
element5(
elementE
(3 downto
0)... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/05/2017 02:01:44 PM
-- Design Name:
-- Module Name: game_logic - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.all;
ENTITY cpu_branchtest_tb IS
END cpu_branchtest_tb;
ARCHITECTURE behavior OF cpu_branchtest_tb IS
signal clk, reset, tx, rx : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
... |
-- NEED RESULT: ARCH00580: Check involving overloading context rule 1 passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------... |
architecture RTL of FIFO is
function func1 return integer is
begin
return 99;
end func1;
-- Violations follow
function func1 return integer is
begin
return 99;
end func1;
function func1 return integer is
begin
return 99;
end func1;
begin
end architecture RTL;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___... |
entity func16 is
end entity func16;
architecture test of func16 is
constant STATE_WORD_SIZE : integer := 8;
type state_type is array (3 downto 0) of bit_vector(STATE_WORD_SIZE-1 downto 0);
function TestFunction (StateInxD : state_type) return state_type is
variable StateOutxD : state_type;
... |
entity func16 is
end entity func16;
architecture test of func16 is
constant STATE_WORD_SIZE : integer := 8;
type state_type is array (3 downto 0) of bit_vector(STATE_WORD_SIZE-1 downto 0);
function TestFunction (StateInxD : state_type) return state_type is
variable StateOutxD : state_type;
... |
entity func16 is
end entity func16;
architecture test of func16 is
constant STATE_WORD_SIZE : integer := 8;
type state_type is array (3 downto 0) of bit_vector(STATE_WORD_SIZE-1 downto 0);
function TestFunction (StateInxD : state_type) return state_type is
variable StateOutxD : state_type;
... |
entity func16 is
end entity func16;
architecture test of func16 is
constant STATE_WORD_SIZE : integer := 8;
type state_type is array (3 downto 0) of bit_vector(STATE_WORD_SIZE-1 downto 0);
function TestFunction (StateInxD : state_type) return state_type is
variable StateOutxD : state_type;
... |
entity func16 is
end entity func16;
architecture test of func16 is
constant STATE_WORD_SIZE : integer := 8;
type state_type is array (3 downto 0) of bit_vector(STATE_WORD_SIZE-1 downto 0);
function TestFunction (StateInxD : state_type) return state_type is
variable StateOutxD : state_type;
... |
--
-- Authors: Francisco Paiva Knebel
-- Gabriel Alexandre Zillmer
--
-- Universidade Federal do Rio Grande do Sul
-- Instituto de Informática
-- Sistemas Digitais
-- Prof. Fernanda Lima Kastensmidt
--
-- Create Date: 11:07:47 05/03/2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux is
port ... |
-------------------------------------------------------------------------------
-- axi_vdma_s2mm_linebuf
-------------------------------------------------------------------------------
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All righ... |
-------------------------------------------------------------------------------
-- axi_vdma_s2mm_linebuf
-------------------------------------------------------------------------------
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All righ... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_10_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_10_... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
-- Last modification date: 05 October 2022
--
----------------------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
-- Last modification date: 05 October 2022
--
----------------------------------------------------------------... |
--!
--! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
-- wasca_rst_controller_001.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : in... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ECO is
Port ( Rx : in STD_LOGIC;
Tx : out STD_LOGIC;
CLK : in STD_LOGIC);
end ECO;
architecture Behavioral of ECO is
COMPONENT ProtocoloRS232_v2
PORT(
Rx_entrada : IN std_logic;
CLK : IN std_logic;
CampanaTx : IN std_logic;
Dato... |
------------------------------------------------------------------------------------------------------------------------------------
--********************************************************************************************************************
-- Design : Return Address Stack
-- Project : EE560 Summer 20... |
--========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: cont255_V2.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms ... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
us... |
Library ieee;
Use ieee.std_logic_1164.all;
ENTITY my_nadder IS
PORT (a, b : in std_logic_vector(15 downto 0) ;
s : out std_logic_vector(15 downto 0);
cout : out std_logic);
END my_nadder;
Architecture a_my_nadder of my_nadder is
Component my_adder is
port( a,b,cin: in std_logic; s,cout : out std_logic);
end com... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:39:36 2017
-- Host : DarkCube running 64-bit major releas... |
-------------------------------------------------------------------------
-- Class: CPE233
-- Engineer: Jacob Hladky
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity uart_wrapper i... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Clock multiplexer with buffered output for Xilinx FPGA.
-------------------------------------------------------------... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Clock multiplexer with buffered output for Xilinx FPGA.
-------------------------------------------------------------... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- modulo
use IEEE.NUMERIC_STD.ALL;
--use work.fontRom.all;
entity sync_test is
Port ( clkExtOsc : in STD_LOGIC;
ledOut : out STD_LOGIC_VECTOR(7 downto 0);
sw : in STD_LOGIC_VECTOR (... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
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