content stringlengths 1 1.04M ⌀ |
|---|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dynroi is
generic (
CLK_PROC_FREQ : integer;
BINIMG_SIZE : integer;
IMG_SIZE : integer;
ROI_SIZE : integer;
COORD_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in... |
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity clk_slow_tb is
end;
architecture bench of clk_slow_tb is
component clk_slow
Port ( clk_in : in STD_LOGIC;
clk_190hz : out STD_LOGIC;
clk_380hz : out STD_LOGIC;
clk_95hz : out STD_LOGIC;
clk_48h... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2011-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-----... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use commands.all;
entity MicroROM is
port(
read_enable : in std_logic;
address : in std_logic_vector(7 downto 0);
data_output : out std_logic_vector(27 downto ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: McEliece_QD-Goppa_Decrypt_v3
-- Module Name: McEliece_QD-Goppa_Decrypt_v3
-- Pr... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
--
-- T8048 Microcontroller System
--
-- $Id: t8048-c.vhd,v 1.2 2004-12-01 23:09:47 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
---------------------------------------------------... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_bitcoin_miner
-- fsm.vhd is part of DS_bitcoin_miner.
-- DS_bitcoin_miner is free software: you can redistribute it and/or modify
-- it under the terms of t... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
-- Helper component to map My IO to FPGA IO-s
entity PORTER is
Port (
JA_P: in std_logic_vector(7 downto 0); --JA port input
JB_P: in std_logic_vector(7 downto 0); --JB port input
JC_P: in std_logic_vector(7 downto 0); --JC port ... |
library verilog;
use verilog.vl_types.all;
entity altera_mult_add is
generic(
extra_latency : integer := 0;
dedicated_multiplier_circuitry: string := "AUTO";
dsp_block_balancing: string := "AUTO";
selected_device_family: string := "Stratix V";
lpm_type : string :... |
library verilog;
use verilog.vl_types.all;
entity altera_mult_add is
generic(
extra_latency : integer := 0;
dedicated_multiplier_circuitry: string := "AUTO";
dsp_block_balancing: string := "AUTO";
selected_device_family: string := "Stratix V";
lpm_type : string :... |
library verilog;
use verilog.vl_types.all;
entity altera_mult_add is
generic(
extra_latency : integer := 0;
dedicated_multiplier_circuitry: string := "AUTO";
dsp_block_balancing: string := "AUTO";
selected_device_family: string := "Stratix V";
lpm_type : string :... |
library verilog;
use verilog.vl_types.all;
entity altera_mult_add is
generic(
extra_latency : integer := 0;
dedicated_multiplier_circuitry: string := "AUTO";
dsp_block_balancing: string := "AUTO";
selected_device_family: string := "Stratix V";
lpm_type : string :... |
library verilog;
use verilog.vl_types.all;
entity altera_mult_add is
generic(
extra_latency : integer := 0;
dedicated_multiplier_circuitry: string := "AUTO";
dsp_block_balancing: string := "AUTO";
selected_device_family: string := "Stratix V";
lpm_type : string :... |
---------------------------------------------------------
-- JAM CPU
-- Very simple SRAM model for simulation
--
-- Copyright © 2002:
-- Anders Lindström, Johan E. Thelin, Michael Nordseth
---------------------------------------------------------
-- This is free software; you can redistribute it and/or
-- modify it un... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package DW02_components is
component DW02_mult_2_stage
generic( A_width: POSITIVE; -- multiplier wordlength
B_width: POSITIVE); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in s... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package DW02_components is
component DW02_mult_2_stage
generic( A_width: POSITIVE; -- multiplier wordlength
B_width: POSITIVE); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in s... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package DW02_components is
component DW02_mult_2_stage
generic( A_width: POSITIVE; -- multiplier wordlength
B_width: POSITIVE); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in s... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package DW02_components is
component DW02_mult_2_stage
generic( A_width: POSITIVE; -- multiplier wordlength
B_width: POSITIVE); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in s... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package DW02_components is
component DW02_mult_2_stage
generic( A_width: POSITIVE; -- multiplier wordlength
B_width: POSITIVE); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in s... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package DW02_components is
component DW02_mult_2_stage
generic( A_width: POSITIVE; -- multiplier wordlength
B_width: POSITIVE); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in s... |
library verilog;
use verilog.vl_types.all;
entity SixToEightExtend is
port(
\In\ : in vl_logic_vector(5 downto 0);
\Out\ : out vl_logic_vector(7 downto 0)
);
end SixToEightExtend;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_159 is
port (
output : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_159;
architecture augh of add_159 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_159 is
port (
output : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_159;
architecture augh of add_159 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_159 is
port (
output : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_159;
architecture augh of add_159 is
signal carry_inA : std_l... |
---------------------------------------------------------------------
-- TITLE: Plamsa Interface (clock divider and interface to FPGA board)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 9/15/07
-- FILENAME: plasma_3e.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by... |
------------------------------------------------------------------------------
-- Title : Swapping Channel Pairs under Counter, Top entity
------------------------------------------------------------------------------
-- Author : José Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generi... |
-------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : clock_tb.vhd
-- Author : Daniel Sun <dcsun88osh@gmail.com>
-- Company :
-- Created : 2016-03-... |
------------------------------------------------------------------------------
-- Title : CDC FIFO for Position data
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-09-23
-- Platform : FPGA-gene... |
----------------------------------------------------------------------------------
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ctrl_in is
generic(NUM_PERIF: int... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package driveseg_comp is
component driveseg
Port(
data : in STD_LOGIC_VECTOR (15 downto 0);
seg_c : out STD_LOGIC_VECTOR (7 downto 0);
seg_a : out std_logic_vector (3 downto 0);
en : in std_logic_vector(3 downto 0);
clk : in std_logic;
rst : in std_lo... |
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_ae
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- ... |
-- Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:05:29
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE is
port (
Clock : in std_logic ... |
-- Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:05:29
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE is
port (
Clock : in std_logic ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: udp_test_sink - Behavioral
--
-- Description: Receive UDP packets for testing.
--
------------------------------------------------------------------------------------
--... |
-- A2601 Top Level Entity (Rev B Board with Flash Memory)
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version ... |
-- file: clk_193MHz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not... |
-- file: clk_193MHz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not... |
-- file: clk_193MHz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.bus_pkg.all;
entity bus_demux is
generic (
ADDRESS_MAP : addr_range_and_mapping_array;
OOR_FAULT_CODE : bus_data_type := (others => '1')
);
port (
rst : in std... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RS232top is
port (
Reset : in std_logic; -- Low_level-active asynchronous reset
Clk : in std_logic; -- System clock (20MHz), rising edge u... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_tb is
end entity;
architecture testbench of fifo_tb is
component fifo32x1K is
port (
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_... |
-- **********************************************************************************
-- Project : MiniBlaze
-- Author : Benjamin Lemoine
-- Module : tb_sequencer
-- Date : 08/05/2016
--
-- Description : Test bench for Sequencer unit
--
-- --------------... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RS232top_TB is
end RS232top_TB;
architecture Testbench of RS232top_TB is
component RS232top
port (
Reset : in std_logic;
Clk : in st... |
entity ENT00001_Test_Bench is
end entity ENT00001_Test_Bench;
architecture arch of ENT00001_Test_Bench is
constant CYCLES : integer := 1000;
signal clk : integer := 0;
signal n : integer := 0;
begin
main: process(clk)
begin
n <= 1 after 10 us;
end process;
terminator : process(clk)
begin
if clk >=... |
----------------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis (christos.bakalis@cern.ch)
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- ... |
package fifo_pkg is
end package;
package fifo_pkg is
end package;
package fifo_pkg is
end package;
package fifo_pkg is
end package;
|
entity arith3 is
end entity;
architecture test of arith3 is
begin
process is
variable t : time;
variable i : integer;
begin
t := 120 ns;
i := sec / t;
report integer'image(i);
assert i = 8333333;
wait;
end process;
end architecture;
|
entity arith3 is
end entity;
architecture test of arith3 is
begin
process is
variable t : time;
variable i : integer;
begin
t := 120 ns;
i := sec / t;
report integer'image(i);
assert i = 8333333;
wait;
end process;
end architecture;
|
entity arith3 is
end entity;
architecture test of arith3 is
begin
process is
variable t : time;
variable i : integer;
begin
t := 120 ns;
i := sec / t;
report integer'image(i);
assert i = 8333333;
wait;
end process;
end architecture;
|
entity arith3 is
end entity;
architecture test of arith3 is
begin
process is
variable t : time;
variable i : integer;
begin
t := 120 ns;
i := sec / t;
report integer'image(i);
assert i = 8333333;
wait;
end process;
end architecture;
|
entity arith3 is
end entity;
architecture test of arith3 is
begin
process is
variable t : time;
variable i : integer;
begin
t := 120 ns;
i := sec / t;
report integer'image(i);
assert i = 8333333;
wait;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 08-02-2016
-- Module Name: fulladdr.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164... |
library ieee;
use ieee.std_logic_1164.all;
entity shiftReg is
port(clock : in std_logic;
load : in std_logic;
shift : in std_logic;
e_s : in std_logic;
bit_out : out std_logic_vector(11 downto 0) := '0');
end shiftReg;
architecture exemp... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library IEEE;
use IEEE.std_logic_1164.All;
use IEEE.std_logic_unsigned.All;
entity testbench is end testbench;
architecture tb_jkff of testbench is
signal clk : std_logic := '0';
signal j : std_logic;
signal k : std_logic;
signal q_out : std_logic;
signal q_not_out : std_logic;
constant twent... |
-- NEED RESULT: ARCH00135.P1: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00135.P2: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00135.P3: Multi inertial transactions occurred on signal asg with simple n... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity si5351c_handler is
port (
clock_in : in std_logic;
reset_in : in std_logic;
done_out : out std_logic;
sda_inout : inout std_logic;
scl_inout : inout std_logic
);
end si5351c_handler;
architecture Behavioral of si5351c_handl... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_Flip_Flop is
port
(
rst : in std_logic;
pre : in std_logic;
ce : in std_logic;
d : in std_logic;
q : out std_logic
);
end entity D_Flip_Flop;
architecture Behavioral of D_Flip_Flop is
begin
process (ce, rst, pre) is
... |
-------------------------------------------------------------------------------
-- Title : Finite Impulse Response Filter
-- Author : Steiger Martin <martin.steiger@students.fh-hagenberg.at>
-------------------------------------------------------------------------------
-- Description : Simple FIR filter str... |
--------------------------------------------------------------------------------------------------
-- 3-stage Filter Bank
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
--------------------------------------------------... |
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