content stringlengths 1 1.04M ⌀ |
|---|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gais... |
library ieee;
use ieee.std_logic_1164.all;
-- Units present in this block (refer to DP schematic):
-- adder1
-- adder2
-- jreg_mux21
-- concatenate16
-- oprnd1_mux41
-- oprnd2_mux41
-- regaddr_mux21
-- forwarding unit
-- alusrc_mux21
-- ALU
-- plus4_adder
-- branch_circ
-- PSW
-- link_mux21... |
-------------------------------------------------------------------------------
--
-- The Decoder unit.
-- It decodes the instruction opcodes and executes them.
--
-- $Id: decoder-c.vhd,v 1.3 2008-04-29 21:19:21 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
---... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity piso_tb is
end entity;
architecture behav of piso_tb is
component piso is
port (
clk : in std_logic;
se : in std_logic_vector(1 downto 0);
D : in std_logic_vector(3 downto 0);
Din : in std_logic;
Q : out std_l... |
-------------------------------------------------------------------------------
-- dlmb_cntlr_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v2_10_b;
use lmb_br... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity intra_prediction_core is
port(
clk : in std_logic;
rst : in std_logic;
--interface to enable "set samples" command
sample_data : i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:15:00 11/12/2015
-- Design Name:
-- Module Name: reg_read - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets o... |
-------------------------------------------------------------------------------
-- $Id: lmb_bram_if_funcs.vhd,v 1.1.2.4 2010/09/28 11:56:10 rolandp Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2013 Xilinx, Inc. All rights reserved.
--
-- This file contai... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSR is
Port ( NZVC : in STD_LOGIC_VECTOR (3 downto 0);
Rst : in STD_LOGIC;
clk : in STD_LOGIC;
Ncwp : in STD_LOGIC;
Carry : out STD_LOGIC;
Cwp : out STD_LOGIC
);
end PSR;
architecture Behavioral of PSR is
begin
process(clk,... |
--------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : Elec... |
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... |
entity tb_dff08c is
end tb_dff08c;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff08c is
signal clk : std_logic;
signal rst : std_logic;
signal en : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
begin
dut: entity work.dff08c
... |
library ieee;
use ieee.std_logic_1164.all;
entity dut is
port (
sig_i : in std_logic_vector;
sig_o : out std_logic_vector
);
end entity;
architecture arch of dut is
begin
sig_o <= sig_i;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity tb is
end entity;
architecture bench of tb is
signal sin... |
-- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does no... |
-- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does no... |
-- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does no... |
-- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does no... |
-- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does no... |
-- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does no... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF1_1_block2.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- ------------------------... |
entity proc4 is
end entity;
architecture rtl of proc4 is
procedure test1(x : inout integer) is
begin
x := x + 1;
end procedure;
procedure test2(x : inout bit_vector) is
begin
for i in x'range loop
x(i) := not x(i);
end loop;
end procedure;
procedure te... |
entity proc4 is
end entity;
architecture rtl of proc4 is
procedure test1(x : inout integer) is
begin
x := x + 1;
end procedure;
procedure test2(x : inout bit_vector) is
begin
for i in x'range loop
x(i) := not x(i);
end loop;
end procedure;
procedure te... |
entity proc4 is
end entity;
architecture rtl of proc4 is
procedure test1(x : inout integer) is
begin
x := x + 1;
end procedure;
procedure test2(x : inout bit_vector) is
begin
for i in x'range loop
x(i) := not x(i);
end loop;
end procedure;
procedure te... |
entity proc4 is
end entity;
architecture rtl of proc4 is
procedure test1(x : inout integer) is
begin
x := x + 1;
end procedure;
procedure test2(x : inout bit_vector) is
begin
for i in x'range loop
x(i) := not x(i);
end loop;
end procedure;
procedure te... |
entity proc4 is
end entity;
architecture rtl of proc4 is
procedure test1(x : inout integer) is
begin
x := x + 1;
end procedure;
procedure test2(x : inout bit_vector) is
begin
for i in x'range loop
x(i) := not x(i);
end loop;
end procedure;
procedure te... |
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
... |
-------------------------------------------------------------------------------
-- Title : 8-bit Client-to-LocalLink Transmitter FIFO
-- Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
-- File : tx_client_fifo_8.vhd
-- Version : 1.4
------------------------------------------------------------... |
architecture rtl of fifo is
begin
block_label : block is
begin
end block block_label;
------------------------------<- 80 chars ->------------------------------
--! FPGA RX to Avalon-ST TX interface
--------------------------------------------------------------------------------
-----------... |
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC ADC 250MS/s core registers
---------------------------------------------------------------------------------------
-- File : wb_fmc516_regs_pkg.vhd
-- Author : auto-g... |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : if a = '1' generate
end generate;
CASE_LABEL : case data generate
end generate;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : if a = '1' generate
end ... |
use work.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu_testbench is
end;
architecture behavioral of alu_testbench is
constant TB_WIDTH : integer := 8;
signal a, b, q : std_logic_vector(TB_WIDTH-1 downto 0);
signal ctrl : std_logic_vector (1 DOWNTO 0);
... |
-------------------------------------------------------------------------------
-- mdio_if.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
-------------------------------------------------------------------------------
-- mdio_if.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
-------------------------------------------------------------------------------
-- mdio_if.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
-------------------------------------------------------------------------------
-- mdio_if.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
-- ============================================================
-- File Name: control_path.vhd
-- ============================================================
-- ************************************************************
-- THIS IS A AUTO-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 2.0 BUILD. GENERATED ON 2... |
library ieee;
use ieee.std_logic_1164.all;
use work.memory_types.all;
entity test_vga_rom is
end test_vga_rom;
architecture behavioural of test_vga_rom is
component VGA_ROM is
generic (
contents: vga_memory
);
port (
clock : in std_logic;
enable : in std_logic;
address : in nat... |
-------------------------------------------------------------------------------
-- Title : FSMC Slave, synchronous
-------------------------------------------------------------------------------
-- Author :
-------------------------------------------------------------------------------
-- Description: This is... |
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end PROCEDURE proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
var... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:18:22 07/06/2014
-- Design Name:
-- Module Name: triple_buffer_arbiter - triple_buffer_arbiter_arch
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-... |
--------------------------------------------------------------------------------
--
-- AM2901 Benchmark -- mem component
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Verification Informa... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_d_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity sigma_delta_dac is
generic (
g_divider : natural := 1;
g_width : positive := 12;
g_invert : boolean := false;
g_use_mid_only : boolean := true;
g_l... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_132 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_132;
architecture augh of cmp_132 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_132 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_132;
architecture augh of cmp_132 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
entity operator1 is
end entity;
architecture test of operator1 is
type t is (A, B);
function "and"(x, y : t) return t is
begin
if x = y then
return A;
else
return B;
end if;
end function;
begin
process is
variable x, y : t;
begin
... |
entity operator1 is
end entity;
architecture test of operator1 is
type t is (A, B);
function "and"(x, y : t) return t is
begin
if x = y then
return A;
else
return B;
end if;
end function;
begin
process is
variable x, y : t;
begin
... |
entity operator1 is
end entity;
architecture test of operator1 is
type t is (A, B);
function "and"(x, y : t) return t is
begin
if x = y then
return A;
else
return B;
end if;
end function;
begin
process is
variable x, y : t;
begin
... |
entity operator1 is
end entity;
architecture test of operator1 is
type t is (A, B);
function "and"(x, y : t) return t is
begin
if x = y then
return A;
else
return B;
end if;
end function;
begin
process is
variable x, y : t;
begin
... |
entity operator1 is
end entity;
architecture test of operator1 is
type t is (A, B);
function "and"(x, y : t) return t is
begin
if x = y then
return A;
else
return B;
end if;
end function;
begin
process is
variable x, y : t;
begin
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wrapper is
port(
clk : in std_logic;
reset : in std_logic;
write : in std_logic;
ack : out std_logic
);
end wrapper;
architecture a of wrapper is
-- compiling with std=93 produces an error here
component write is
port(
clk ... |
-------------------------------------------------------------------
-- FPGA Audio Project SoC IP
-- V0.1
-- Ultra-Embedded.com
--
-- This file was derived from the Plasma project by Steve Rhoads.
-- It has been modified to support dual port block RAM and... |
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ab_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 08:31:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Aut... |
library ieee;
use ieee.std_logic_1164.all;
entity unidade_controle_recepcao is
port(liga : in std_logic;
reset : in std_logic;
CD : in std_logic;
clock : in std_logic;
enable_recepcao : out std_logic;
DTR : out std_logic;
s_estado : out std_... |
------------------------------------------------------------------------
-- RS232RefCom.vhd
------------------------------------------------------------------------
-- Author: Dan Pederson
-- Copyright 2004 Digilent, Inc.
------------------------------------------------------------------------
-- Description... |
------------------------------------------------------------------------
-- RS232RefCom.vhd
------------------------------------------------------------------------
-- Author: Dan Pederson
-- Copyright 2004 Digilent, Inc.
------------------------------------------------------------------------
-- Description... |
------------------------------------------------------------------------
-- RS232RefCom.vhd
------------------------------------------------------------------------
-- Author: Dan Pederson
-- Copyright 2004 Digilent, Inc.
------------------------------------------------------------------------
-- Description... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity MAR is
port(
clk, lat: in std_logic;
busC : in std_logic_vector(15 downto 0);
M_ad16: out std_logic_vector(15 downto 0);
M_ad8: out std_logic_vector(7 downto 0)
);
end MAR;
a... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity MAR is
port(
clk, lat: in std_logic;
busC : in std_logic_vector(15 downto 0);
M_ad16: out std_logic_vector(15 downto 0);
M_ad8: out std_logic_vector(7 downto 0)
);
end MAR;
a... |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under ... |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:48:07 05/19/2016
-- Design Name:
-- Module Name: Komp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision: ... |
entity vecorder1 is
end entity;
architecture test of vecorder1 is
type int_array is array (integer range <>) of integer;
signal s : int_array(0 to 1) := ( 0 => 0, 1 => 1 );
begin
process is
variable x : int_array(0 to 1) := ( 0 => 0, 1 => 1 );
variable y : int_array(1 downto 0) := ( 0 => ... |
library ieee;
use ieee.std_logic_1164.all;
use work.types.all;
entity cipher_tb is
end cipher_tb;
architecture behavior of cipher_tb is
component cipher
port (
din : in state;
dout : out state
);
end component;
--Inputs
signal din : state;
--Outputs
signal dout : state;
begin
uut: cipher port map (
... |
-- Author: Ronaldo Dall'Agnol Veiga
-- @roniveiga
-- UFRGS - Instituto de Informática
-- Sistemas Digitais
-- Profa. Dra. Fernanda Gusmão de Lima Kastensmidt
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity control_unit is
Port (
-- inputs
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_grain128 is
generic (
DEBUG : boolean := false;
FAST : boolean := false
);
end entity;
architecture test of tb_grain128 is
-- some testvectors:
constant GRAIN_KEY1 : unsigned(127 downto 0) := (others => '0');
constant GRAIN_IV1 : un... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
use work.mem_pkg.all;
entity memory_stage is
port (mem_d : in mem_in;
mem_q : out mem_out);
end entity memory_stage;
architecture Behavioral of memory_stage is
begin -- architecture Behavioral
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
use work.mem_pkg.all;
entity memory_stage is
port (mem_d : in mem_in;
mem_q : out mem_out);
end entity memory_stage;
architecture Behavioral of memory_stage is
begin -- architecture Behavioral
... |
library ieee;
--Comment
use ieee.std_logic_1164.all;
--Comment
use ieee.numeric_std.all;
library ieee;
-- Comment
use ieee.std_logic_1164.all;
-- Comment
-- Comment 2
-- Comment 3
use ieee.numeric_std.all;
-- Comment
use ieee.std_logic_arith.all;
library ieee;
-- Comment
use ieee.std_logic_1164.al... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use i... |
----------------------------------------------------------------------
-- OscChpGat
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Blink some LEDs based only on OnChip resources.
-- Use the OnDie RC-Oscillator plus a bunch
-- of registers for the FlipFlip toggl... |
library IEEE;
use ieee.std_logic_1164.all;
entity recursive_stack is
generic ( size: natural := 4);
port (
data_in : in natural;
data_out : out natural;
enable : in std_logic;
push_pop: in std_logic;
clk : in std_logic
);
end recursive_stack;
architecture arch_recur... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versi... |
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: filtering_algorithm_pkg - Package
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
---------------------------------------... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity AudioIO_tl is
port (
sampleButton : in std_logic;
vauxn : in std_logic;
vauxp : in std_logic;
leds : out std_logic_vector(15 downto 0);
clk : in std_logic;
reset : in std_logic
) ;
end entity ; -- AudioIO_tl
architectur... |
-------------------------------------------------------------------------------
-- Copyright (C) 2022 Nick Gasson
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www... |
-- NEED RESULT: ARCH00437: comments passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NA... |
--------------------------------------------------------------------------------
--
-- AM2901 Benchmark output_shifter
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Verification Informati... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity VOICE_DELAY is
port
(
clk:in std_logic;
start:in std_logic:='0';
total:in std_logic_vector(7 downto 0);
finish:out std_logic:='1'
);
end entity;
architecture delayx ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity VOICE_DELAY is
port
(
clk:in std_logic;
start:in std_logic:='0';
total:in std_logic_vector(7 downto 0);
finish:out std_logic:='1'
);
end entity;
architecture delayx ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
---------------------------------------------------------------------------
-- Copyright 2012 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
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