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-- NEED RESULT: ARCH00338.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P4: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P5: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P6: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P7: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P8: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P9: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P10: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P11: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P12: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P13: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P14: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P15: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P16: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P17: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P17: Transport transactions completed entirely passed
-- NEED RESULT: P16: Transport transactions completed entirely passed
-- NEED RESULT: P15: Transport transactions completed entirely passed
-- NEED RESULT: P14: Transport transactions completed entirely passed
-- NEED RESULT: P13: Transport transactions completed entirely passed
-- NEED RESULT: P12: Transport transactions completed entirely passed
-- NEED RESULT: P11: Transport transactions completed entirely passed
-- NEED RESULT: P10: Transport transactions completed entirely passed
-- NEED RESULT: P9: Transport transactions completed entirely passed
-- NEED RESULT: P8: Transport transactions completed entirely passed
-- NEED RESULT: P7: Transport transactions completed entirely passed
-- NEED RESULT: P6: Transport transactions completed entirely passed
-- NEED RESULT: P5: Transport transactions completed entirely passed
-- NEED RESULT: P4: Transport transactions completed entirely passed
-- NEED RESULT: P3: Transport transactions completed entirely passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00338
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00338(ARCH00338)
-- ENT00338_Test_Bench(ARCH00338_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00338 is
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
end ENT00338 ;
--
--
architecture ARCH00338 of ENT00338 is
subtype chk_time_type is Time ;
signal s_boolean_savt : chk_time_type := 0 ns ;
signal s_bit_savt : chk_time_type := 0 ns ;
signal s_severity_level_savt : chk_time_type := 0 ns ;
signal s_character_savt : chk_time_type := 0 ns ;
signal s_st_enum1_savt : chk_time_type := 0 ns ;
signal s_integer_savt : chk_time_type := 0 ns ;
signal s_st_int1_savt : chk_time_type := 0 ns ;
signal s_time_savt : chk_time_type := 0 ns ;
signal s_st_phys1_savt : chk_time_type := 0 ns ;
signal s_real_savt : chk_time_type := 0 ns ;
signal s_st_real1_savt : chk_time_type := 0 ns ;
signal s_st_rec1_savt : chk_time_type := 0 ns ;
signal s_st_rec2_savt : chk_time_type := 0 ns ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
signal s_st_arr1_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
signal s_st_arr3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_boolean_cnt : chk_cnt_type := 0 ;
signal s_bit_cnt : chk_cnt_type := 0 ;
signal s_severity_level_cnt : chk_cnt_type := 0 ;
signal s_character_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_cnt : chk_cnt_type := 0 ;
signal s_integer_cnt : chk_cnt_type := 0 ;
signal s_st_int1_cnt : chk_cnt_type := 0 ;
signal s_time_cnt : chk_cnt_type := 0 ;
signal s_st_phys1_cnt : chk_cnt_type := 0 ;
signal s_real_cnt : chk_cnt_type := 0 ;
signal s_st_real1_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
signal s_st_arr1_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal boolean_select : select_type := 1 ;
signal bit_select : select_type := 1 ;
signal severity_level_select : select_type := 1 ;
signal character_select : select_type := 1 ;
signal st_enum1_select : select_type := 1 ;
signal integer_select : select_type := 1 ;
signal st_int1_select : select_type := 1 ;
signal time_select : select_type := 1 ;
signal st_phys1_select : select_type := 1 ;
signal real_select : select_type := 1 ;
signal st_real1_select : select_type := 1 ;
signal st_rec1_select : select_type := 1 ;
signal st_rec2_select : select_type := 1 ;
signal st_rec3_select : select_type := 1 ;
signal st_arr1_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
signal st_arr3_select : select_type := 1 ;
--
begin
CHG1 :
process ( s_boolean )
variable correct : boolean ;
begin
case s_boolean_cnt is
when 0
=> null ;
-- s_boolean <= transport
-- c_boolean_2 after 10 ns,
-- c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
boolean_select <= transport 2 ;
-- s_boolean <= transport
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
boolean_select <= transport 3 ;
-- s_boolean <= transport
-- c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_boolean_savt <= transport Std.Standard.Now ;
chk_boolean <= transport s_boolean_cnt
after (1 us - Std.Standard.Now) ;
s_boolean_cnt <= transport s_boolean_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_boolean = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with boolean_select select
s_boolean <= transport
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns
when 1,
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when 2,
--
c_boolean_1 after 5 ns when 3 ;
--
CHG2 :
process ( s_bit )
variable correct : boolean ;
begin
case s_bit_cnt is
when 0
=> null ;
-- s_bit <= transport
-- c_bit_2 after 10 ns,
-- c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
bit_select <= transport 2 ;
-- s_bit <= transport
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
bit_select <= transport 3 ;
-- s_bit <= transport
-- c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_bit_savt <= transport Std.Standard.Now ;
chk_bit <= transport s_bit_cnt
after (1 us - Std.Standard.Now) ;
s_bit_cnt <= transport s_bit_cnt + 1 ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_bit = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with bit_select select
s_bit <= transport
c_bit_2 after 10 ns,
c_bit_1 after 20 ns
when 1,
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when 2,
--
c_bit_1 after 5 ns when 3 ;
--
CHG3 :
process ( s_severity_level )
variable correct : boolean ;
begin
case s_severity_level_cnt is
when 0
=> null ;
-- s_severity_level <= transport
-- c_severity_level_2 after 10 ns,
-- c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P3" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
severity_level_select <= transport 2 ;
-- s_severity_level <= transport
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
severity_level_select <= transport 3 ;
-- s_severity_level <= transport
-- c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_severity_level_savt <= transport Std.Standard.Now ;
chk_severity_level <= transport s_severity_level_cnt
after (1 us - Std.Standard.Now) ;
s_severity_level_cnt <= transport s_severity_level_cnt + 1 ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions completed entirely",
chk_severity_level = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with severity_level_select select
s_severity_level <= transport
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns
when 1,
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when 2,
--
c_severity_level_1 after 5 ns when 3 ;
--
CHG4 :
process ( s_character )
variable correct : boolean ;
begin
case s_character_cnt is
when 0
=> null ;
-- s_character <= transport
-- c_character_2 after 10 ns,
-- c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P4" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
character_select <= transport 2 ;
-- s_character <= transport
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
character_select <= transport 3 ;
-- s_character <= transport
-- c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_character_savt <= transport Std.Standard.Now ;
chk_character <= transport s_character_cnt
after (1 us - Std.Standard.Now) ;
s_character_cnt <= transport s_character_cnt + 1 ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions completed entirely",
chk_character = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
with character_select select
s_character <= transport
c_character_2 after 10 ns,
c_character_1 after 20 ns
when 1,
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when 2,
--
c_character_1 after 5 ns when 3 ;
--
CHG5 :
process ( s_st_enum1 )
variable correct : boolean ;
begin
case s_st_enum1_cnt is
when 0
=> null ;
-- s_st_enum1 <= transport
-- c_st_enum1_2 after 10 ns,
-- c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P5" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_select <= transport 2 ;
-- s_st_enum1 <= transport
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
st_enum1_select <= transport 3 ;
-- s_st_enum1 <= transport
-- c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_enum1_savt <= transport Std.Standard.Now ;
chk_st_enum1 <= transport s_st_enum1_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_cnt <= transport s_st_enum1_cnt + 1 ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions completed entirely",
chk_st_enum1 = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
with st_enum1_select select
s_st_enum1 <= transport
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns
when 1,
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when 2,
--
c_st_enum1_1 after 5 ns when 3 ;
--
CHG6 :
process ( s_integer )
variable correct : boolean ;
begin
case s_integer_cnt is
when 0
=> null ;
-- s_integer <= transport
-- c_integer_2 after 10 ns,
-- c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P6" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
integer_select <= transport 2 ;
-- s_integer <= transport
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
integer_select <= transport 3 ;
-- s_integer <= transport
-- c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_integer_savt <= transport Std.Standard.Now ;
chk_integer <= transport s_integer_cnt
after (1 us - Std.Standard.Now) ;
s_integer_cnt <= transport s_integer_cnt + 1 ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions completed entirely",
chk_integer = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
with integer_select select
s_integer <= transport
c_integer_2 after 10 ns,
c_integer_1 after 20 ns
when 1,
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when 2,
--
c_integer_1 after 5 ns when 3 ;
--
CHG7 :
process ( s_st_int1 )
variable correct : boolean ;
begin
case s_st_int1_cnt is
when 0
=> null ;
-- s_st_int1 <= transport
-- c_st_int1_2 after 10 ns,
-- c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P7" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_int1_select <= transport 2 ;
-- s_st_int1 <= transport
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
st_int1_select <= transport 3 ;
-- s_st_int1 <= transport
-- c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_int1_savt <= transport Std.Standard.Now ;
chk_st_int1 <= transport s_st_int1_cnt
after (1 us - Std.Standard.Now) ;
s_st_int1_cnt <= transport s_st_int1_cnt + 1 ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions completed entirely",
chk_st_int1 = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
with st_int1_select select
s_st_int1 <= transport
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns
when 1,
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when 2,
--
c_st_int1_1 after 5 ns when 3 ;
--
CHG8 :
process ( s_time )
variable correct : boolean ;
begin
case s_time_cnt is
when 0
=> null ;
-- s_time <= transport
-- c_time_2 after 10 ns,
-- c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P8" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
time_select <= transport 2 ;
-- s_time <= transport
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
time_select <= transport 3 ;
-- s_time <= transport
-- c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_time_savt <= transport Std.Standard.Now ;
chk_time <= transport s_time_cnt
after (1 us - Std.Standard.Now) ;
s_time_cnt <= transport s_time_cnt + 1 ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions completed entirely",
chk_time = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
with time_select select
s_time <= transport
c_time_2 after 10 ns,
c_time_1 after 20 ns
when 1,
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when 2,
--
c_time_1 after 5 ns when 3 ;
--
CHG9 :
process ( s_st_phys1 )
variable correct : boolean ;
begin
case s_st_phys1_cnt is
when 0
=> null ;
-- s_st_phys1 <= transport
-- c_st_phys1_2 after 10 ns,
-- c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P9" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_phys1_select <= transport 2 ;
-- s_st_phys1 <= transport
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
st_phys1_select <= transport 3 ;
-- s_st_phys1 <= transport
-- c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_phys1_savt <= transport Std.Standard.Now ;
chk_st_phys1 <= transport s_st_phys1_cnt
after (1 us - Std.Standard.Now) ;
s_st_phys1_cnt <= transport s_st_phys1_cnt + 1 ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions completed entirely",
chk_st_phys1 = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
with st_phys1_select select
s_st_phys1 <= transport
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns
when 1,
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when 2,
--
c_st_phys1_1 after 5 ns when 3 ;
--
CHG10 :
process ( s_real )
variable correct : boolean ;
begin
case s_real_cnt is
when 0
=> null ;
-- s_real <= transport
-- c_real_2 after 10 ns,
-- c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P10" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
real_select <= transport 2 ;
-- s_real <= transport
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
real_select <= transport 3 ;
-- s_real <= transport
-- c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_real_savt <= transport Std.Standard.Now ;
chk_real <= transport s_real_cnt
after (1 us - Std.Standard.Now) ;
s_real_cnt <= transport s_real_cnt + 1 ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions completed entirely",
chk_real = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
with real_select select
s_real <= transport
c_real_2 after 10 ns,
c_real_1 after 20 ns
when 1,
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when 2,
--
c_real_1 after 5 ns when 3 ;
--
CHG11 :
process ( s_st_real1 )
variable correct : boolean ;
begin
case s_st_real1_cnt is
when 0
=> null ;
-- s_st_real1 <= transport
-- c_st_real1_2 after 10 ns,
-- c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P11" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real1_select <= transport 2 ;
-- s_st_real1 <= transport
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
st_real1_select <= transport 3 ;
-- s_st_real1 <= transport
-- c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_real1_savt <= transport Std.Standard.Now ;
chk_st_real1 <= transport s_st_real1_cnt
after (1 us - Std.Standard.Now) ;
s_st_real1_cnt <= transport s_st_real1_cnt + 1 ;
--
end process CHG11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Transport transactions completed entirely",
chk_st_real1 = 4 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
--
with st_real1_select select
s_st_real1 <= transport
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns
when 1,
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when 2,
--
c_st_real1_1 after 5 ns when 3 ;
--
CHG12 :
process ( s_st_rec1 )
variable correct : boolean ;
begin
case s_st_rec1_cnt is
when 0
=> null ;
-- s_st_rec1 <= transport
-- c_st_rec1_2 after 10 ns,
-- c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P12" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_select <= transport 2 ;
-- s_st_rec1 <= transport
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
st_rec1_select <= transport 3 ;
-- s_st_rec1 <= transport
-- c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec1_savt <= transport Std.Standard.Now ;
chk_st_rec1 <= transport s_st_rec1_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ;
--
end process CHG12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Transport transactions completed entirely",
chk_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
--
with st_rec1_select select
s_st_rec1 <= transport
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns
when 1,
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when 2,
--
c_st_rec1_1 after 5 ns when 3 ;
--
CHG13 :
process ( s_st_rec2 )
variable correct : boolean ;
begin
case s_st_rec2_cnt is
when 0
=> null ;
-- s_st_rec2 <= transport
-- c_st_rec2_2 after 10 ns,
-- c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P13" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_select <= transport 2 ;
-- s_st_rec2 <= transport
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
st_rec2_select <= transport 3 ;
-- s_st_rec2 <= transport
-- c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec2_savt <= transport Std.Standard.Now ;
chk_st_rec2 <= transport s_st_rec2_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ;
--
end process CHG13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Transport transactions completed entirely",
chk_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
--
with st_rec2_select select
s_st_rec2 <= transport
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns
when 1,
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when 2,
--
c_st_rec2_1 after 5 ns when 3 ;
--
CHG14 :
process ( s_st_rec3 )
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3 <= transport
-- c_st_rec3_2 after 10 ns,
-- c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P14" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3 <= transport
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3 <= transport
-- c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
--
end process CHG14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Transport transactions completed entirely",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
--
with st_rec3_select select
s_st_rec3 <= transport
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns
when 1,
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when 2,
--
c_st_rec3_1 after 5 ns when 3 ;
--
CHG15 :
process ( s_st_arr1 )
variable correct : boolean ;
begin
case s_st_arr1_cnt is
when 0
=> null ;
-- s_st_arr1 <= transport
-- c_st_arr1_2 after 10 ns,
-- c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P15" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr1_select <= transport 2 ;
-- s_st_arr1 <= transport
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
st_arr1_select <= transport 3 ;
-- s_st_arr1 <= transport
-- c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr1_savt <= transport Std.Standard.Now ;
chk_st_arr1 <= transport s_st_arr1_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr1_cnt <= transport s_st_arr1_cnt + 1 ;
--
end process CHG15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Transport transactions completed entirely",
chk_st_arr1 = 4 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
--
with st_arr1_select select
s_st_arr1 <= transport
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns
when 1,
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when 2,
--
c_st_arr1_1 after 5 ns when 3 ;
--
CHG16 :
process ( s_st_arr2 )
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2 <= transport
-- c_st_arr2_2 after 10 ns,
-- c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P16" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2 <= transport
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2 <= transport
-- c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
--
end process CHG16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Transport transactions completed entirely",
chk_st_arr2 = 4 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
--
with st_arr2_select select
s_st_arr2 <= transport
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns
when 1,
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when 2,
--
c_st_arr2_1 after 5 ns when 3 ;
--
CHG17 :
process ( s_st_arr3 )
variable correct : boolean ;
begin
case s_st_arr3_cnt is
when 0
=> null ;
-- s_st_arr3 <= transport
-- c_st_arr3_2 after 10 ns,
-- c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P17" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr3_select <= transport 2 ;
-- s_st_arr3 <= transport
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
st_arr3_select <= transport 3 ;
-- s_st_arr3 <= transport
-- c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr3_savt <= transport Std.Standard.Now ;
chk_st_arr3 <= transport s_st_arr3_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr3_cnt <= transport s_st_arr3_cnt + 1 ;
--
end process CHG17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Transport transactions completed entirely",
chk_st_arr3 = 4 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
with st_arr3_select select
s_st_arr3 <= transport
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns
when 1,
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when 2,
--
c_st_arr3_1 after 5 ns when 3 ;
--
end ARCH00338 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00338_Test_Bench is
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
end ENT00338_Test_Bench ;
--
--
architecture ARCH00338_Test_Bench of ENT00338_Test_Bench is
begin
L1:
block
component UUT
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00338 ( ARCH00338 ) ;
begin
CIS1 : UUT
port map (
s_boolean
, s_bit
, s_severity_level
, s_character
, s_st_enum1
, s_integer
, s_st_int1
, s_time
, s_st_phys1
, s_real
, s_st_real1
, s_st_rec1
, s_st_rec2
, s_st_rec3
, s_st_arr1
, s_st_arr2
, s_st_arr3
)
;
end block L1 ;
end ARCH00338_Test_Bench ;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity transmission_line_wa is
port ( quantity vin : in voltage;
quantity vout : out voltage);
end entity transmission_line_wa;
----------------------------------------------------------------
architecture abstract of transmission_line_wa is
constant propagation_time : real := 2.5E-9;
constant attenuation : real := 0.8;
quantity vin_temp : real;
begin
vin_temp == vin;
vout == attenuation * vin_temp'delayed(propagation_time);
end architecture abstract;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity transmission_line_wa is
port ( quantity vin : in voltage;
quantity vout : out voltage);
end entity transmission_line_wa;
----------------------------------------------------------------
architecture abstract of transmission_line_wa is
constant propagation_time : real := 2.5E-9;
constant attenuation : real := 0.8;
quantity vin_temp : real;
begin
vin_temp == vin;
vout == attenuation * vin_temp'delayed(propagation_time);
end architecture abstract;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity transmission_line_wa is
port ( quantity vin : in voltage;
quantity vout : out voltage);
end entity transmission_line_wa;
----------------------------------------------------------------
architecture abstract of transmission_line_wa is
constant propagation_time : real := 2.5E-9;
constant attenuation : real := 0.8;
quantity vin_temp : real;
begin
vin_temp == vin;
vout == attenuation * vin_temp'delayed(propagation_time);
end architecture abstract;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity wb_spi is
generic (
g_CLK_DIVIDER : positive := 10
);
port (
-- Sys Connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- SPI out
scl_o : out std_logic;
sda_o : out std_logic;
sdi_i : in std_logic;
latch_o : out std_logic
);
end wb_spi;
architecture rtl of wb_spi is
signal data_word : std_logic_vector(31 downto 0);
signal sreg : std_logic_vector(31 downto 0);
signal shift_cnt : unsigned(7 downto 0);
signal wait_cnt : unsigned(7 downto 0);
signal start : std_logic;
signal busy : std_logic;
signal data_in : std_logic_vector(31 downto 0);
begin
wb_proc: process(wb_clk_i, rst_n_i)
begin
if (rst_n_i ='0') then
data_word <= (others => '0');
start <= '0';
wb_ack_o <= '0';
wb_dat_o <= (others => '0');
elsif rising_edge(wb_clk_i) then
wb_ack_o <= '0';
start <= '0';
if (wb_cyc_i = '1' and wb_stb_i = '1') then
if (wb_we_i = '1') then
case (wb_adr_i(3 downto 0)) is
when x"0" =>
data_word <= wb_dat_i;
wb_ack_o <= '1';
when x"1" =>
start <= wb_dat_i(0);
wb_ack_o <= '1';
when others =>
wb_ack_o <= '1';
end case;
else
case (wb_adr_i(3 downto 0)) is
when x"1" =>
wb_dat_o(31 downto 1) <= (others => '0');
wb_dat_o(0) <= busy;
wb_ack_o <= '1';
when x"2" =>
wb_dat_o <= data_in;
wb_ack_o <= '1';
when others =>
wb_dat_o <= x"DEADBEEF";
wb_ack_o <= '1';
end case;
end if;
end if;
end if;
end process wb_proc;
spi_proc: process(wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
busy <= '0';
shift_cnt <= (others => '0');
wait_cnt <= (others => '0');
sreg <= (others => '0');
scl_o <= '0';
sda_o <= '0';
latch_o <= '0';
data_in <= (others => '0');
elsif rising_edge(wb_clk_i) then
if (start = '1') then
sreg <= data_word;
shift_cnt <= to_unsigned(34, 8);
busy <= '1';
end if;
sda_o <= sreg(31);
latch_o <= '0';
if (shift_cnt > 2) then
if (wait_cnt = to_unsigned(g_CLK_DIVIDER, 8)) then
wait_cnt <= (others => '0');
scl_o <= '0';
sreg <= sreg(30 downto 0) & '0';
shift_cnt <= shift_cnt - 1;
data_in <= data_in(30 downto 0) & sdi_i;
elsif (wait_cnt=to_unsigned(g_CLK_DIVIDER/2, 8)) then
scl_o <= '1';
wait_cnt <= wait_cnt + 1;
else
wait_cnt <= wait_cnt + 1;
end if;
elsif (shift_cnt > 1) then
if (wait_cnt = to_unsigned(g_CLK_DIVIDER, 8)) then
wait_cnt <= (others => '0');
shift_cnt <= shift_cnt - 1;
else
wait_cnt <= wait_cnt + 1;
end if;
elsif (shift_cnt > 0) then
if (wait_cnt = to_unsigned(g_CLK_DIVIDER, 8)) then
wait_cnt <= (others => '0');
shift_cnt <= shift_cnt - 1;
latch_o <= '1';
busy <= '0';
else
wait_cnt <= wait_cnt + 1;
latch_o <= '1';
end if;
end if;
end if;
end process;
end rtl;
|
-- Copyright (c) 2015 CERN
-- @author Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for variable initialization.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vhdl_var_init is
port(init : in std_logic;
slv : out std_logic_vector(7 downto 0);
bool : out boolean;
i : out integer
);
end vhdl_var_init;
architecture test of vhdl_var_init is
begin
process(init)
variable var_slv : std_logic_vector(7 downto 0) := "01000010";
variable var_bool : boolean := false;
variable var_int : integer := 42;
begin
if rising_edge(init) then
slv <= var_slv;
bool <= var_bool;
i <= var_int;
end if;
end process;
end test;
|
-- Copyright (c) 2015 CERN
-- @author Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for variable initialization.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vhdl_var_init is
port(init : in std_logic;
slv : out std_logic_vector(7 downto 0);
bool : out boolean;
i : out integer
);
end vhdl_var_init;
architecture test of vhdl_var_init is
begin
process(init)
variable var_slv : std_logic_vector(7 downto 0) := "01000010";
variable var_bool : boolean := false;
variable var_int : integer := 42;
begin
if rising_edge(init) then
slv <= var_slv;
bool <= var_bool;
i <= var_int;
end if;
end process;
end test;
|
-- Copyright (c) 2015 CERN
-- @author Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for variable initialization.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vhdl_var_init is
port(init : in std_logic;
slv : out std_logic_vector(7 downto 0);
bool : out boolean;
i : out integer
);
end vhdl_var_init;
architecture test of vhdl_var_init is
begin
process(init)
variable var_slv : std_logic_vector(7 downto 0) := "01000010";
variable var_bool : boolean := false;
variable var_int : integer := 42;
begin
if rising_edge(init) then
slv <= var_slv;
bool <= var_bool;
i <= var_int;
end if;
end process;
end test;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (4);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020765#;
constant CFG_ETH_ENL : integer := 16#003456#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 0;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (16);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (128);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 1;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 16;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 1;
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#03#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (1);
constant CFG_SPIMCTRL_ASCALER : integer := (8);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (30000);
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.cpu86pack.ALL;
ENTITY biu IS
PORT(
clk : IN std_logic;
csbus : IN std_logic_vector (15 DOWNTO 0);
dbus_in : IN std_logic_vector (7 DOWNTO 0);
dbusdp_in : IN std_logic_vector (15 DOWNTO 0);
decode_state : IN std_logic;
flush_coming : IN std_logic;
flush_req : IN std_logic;
intack : IN std_logic;
intr : IN std_logic;
iomem : IN std_logic;
ipbus : IN std_logic_vector (15 DOWNTO 0);
irq_block : IN std_logic;
nmi : IN std_logic;
opc_req : IN std_logic;
read_req : IN std_logic;
reset : IN std_logic;
status : IN status_out_type;
word : IN std_logic;
write_req : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
biu_error : OUT std_logic;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
flush_ack : OUT std_logic;
instr : OUT instruction_type;
inta : OUT std_logic;
inta1 : OUT std_logic;
iom : OUT std_logic;
irq_req : OUT std_logic;
latcho : OUT std_logic;
mdbus_out : OUT std_logic_vector (15 DOWNTO 0);
rdn : OUT std_logic;
rw_ack : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END biu ;
ARCHITECTURE struct OF biu IS
SIGNAL abus_s : std_logic_vector(19 DOWNTO 0);
SIGNAL abusdp_in : std_logic_vector(19 DOWNTO 0);
SIGNAL addrplus4 : std_logic;
SIGNAL biu_status : std_logic_vector(2 DOWNTO 0);
SIGNAL csbusbiu_s : std_logic_vector(15 DOWNTO 0);
SIGNAL halt_instr : std_logic;
SIGNAL inta2_s : std_logic; -- Second INTA pulse, used to latch 8 bist vector
SIGNAL ipbusbiu_s : std_logic_vector(15 DOWNTO 0);
SIGNAL ipbusp1_s : std_logic_vector(15 DOWNTO 0);
SIGNAL irq_ack : std_logic;
SIGNAL irq_clr : std_logic;
SIGNAL irq_type : std_logic_vector(1 DOWNTO 0);
SIGNAL latchabus : std_logic;
SIGNAL latchclr : std_logic;
SIGNAL latchm : std_logic;
SIGNAL latchrw : std_logic;
SIGNAL ldposplus1 : std_logic;
SIGNAL lutbus : std_logic_vector(15 DOWNTO 0);
SIGNAL mux_addr : std_logic_vector(2 DOWNTO 0);
SIGNAL mux_data : std_logic_vector(3 DOWNTO 0);
SIGNAL mux_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL muxabus : std_logic_vector(1 DOWNTO 0);
SIGNAL nbreq : std_logic_vector(2 DOWNTO 0);
SIGNAL rdcode_s : std_logic;
SIGNAL rddata_s : std_logic;
SIGNAL reg1freed : std_logic; -- Delayed version (1 clk) of reg1free
SIGNAL reg4free : std_logic;
SIGNAL regnbok : std_logic;
SIGNAL regplus1 : std_logic;
SIGNAL w_biufsm_s : std_logic;
SIGNAL wr_s : std_logic;
SIGNAL flush_ack_internal : std_logic;
SIGNAL inta1_internal : std_logic;
SIGNAL irq_req_internal : std_logic;
SIGNAL latcho_internal : std_logic;
signal nmi_s : std_logic;
signal nmipre_s : std_logic_vector(1 downto 0); -- metastability first FF for nmi
signal outbus_s : std_logic_vector(7 downto 0); -- used in out instr. bus streering
signal latchmd_s : std_logic; -- internal rdl_s signal
signal abusdp_inp1l_s: std_logic_vector(15 downto 0);
signal latchrw_d_s: std_logic; -- latchrw delayed 1 clk cycle
signal latchclr_d_s: std_logic; -- latchclr delayed 1 clk cycle
signal iom_s : std_logic;
signal instr_trace_s : std_logic; -- TF latched by exec_state pulse
signal irq_req_s : std_logic;
-- Component Declarations
COMPONENT biufsm
PORT (
clk : IN std_logic ;
flush_coming : IN std_logic ;
flush_req : IN std_logic ;
irq_req : IN std_logic ;
irq_type : IN std_logic_vector (1 DOWNTO 0);
opc_req : IN std_logic ;
read_req : IN std_logic ;
reg1freed : IN std_logic ;
reg4free : IN std_logic ;
regnbok : IN std_logic ;
reset : IN std_logic ;
w_biufsm_s : IN std_logic ;
write_req : IN std_logic ;
addrplus4 : OUT std_logic ;
biu_error : OUT std_logic ;
biu_status : OUT std_logic_vector (2 DOWNTO 0);
irq_ack : OUT std_logic ;
irq_clr : OUT std_logic ;
latchabus : OUT std_logic ;
latchclr : OUT std_logic ;
latchm : OUT std_logic ;
latcho : OUT std_logic ;
latchrw : OUT std_logic ;
ldposplus1 : OUT std_logic ;
muxabus : OUT std_logic_vector (1 DOWNTO 0);
rdcode_s : OUT std_logic ;
rddata_s : OUT std_logic ;
regplus1 : OUT std_logic ;
rw_ack : OUT std_logic ;
wr_s : OUT std_logic ;
flush_ack : BUFFER std_logic ;
inta1 : BUFFER std_logic
);
END COMPONENT;
COMPONENT formatter
PORT (
lutbus : IN std_logic_vector (15 DOWNTO 0);
mux_addr : OUT std_logic_vector (2 DOWNTO 0);
mux_data : OUT std_logic_vector (3 DOWNTO 0);
mux_reg : OUT std_logic_vector (2 DOWNTO 0);
nbreq : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
COMPONENT regshiftmux
PORT (
clk : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
flush_req : IN std_logic ;
latchm : IN std_logic ;
latcho : IN std_logic ;
mux_addr : IN std_logic_vector (2 DOWNTO 0);
mux_data : IN std_logic_vector (3 DOWNTO 0);
mux_reg : IN std_logic_vector (2 DOWNTO 0);
nbreq : IN std_logic_vector (2 DOWNTO 0);
regplus1 : IN std_logic ;
ldposplus1 : IN std_logic ;
reset : IN std_logic ;
irq : IN std_logic ;
inta1 : IN std_logic ; -- Added for ver 0.71
inta2_s : IN std_logic ;
irq_type : IN std_logic_vector (1 DOWNTO 0);
instr : OUT instruction_type ;
halt_instr : OUT std_logic ;
lutbus : OUT std_logic_vector (15 DOWNTO 0);
reg1free : BUFFER std_logic ;
reg1freed : BUFFER std_logic ; -- Delayed version (1 clk) of reg1free
regnbok : OUT std_logic
);
END COMPONENT;
BEGIN
-------------------------------------------------------------------------
-- Databus Latch
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
dbus_out <= DONTCARE(7 downto 0);
elsif rising_edge(clk) then
if latchrw='1' then -- Latch Data from DataPath
dbus_out <= outbus_s;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- OUT instruction bus steering
-- IO/~M & A[1:0]
---------------------------------------------------------------------------
process(dbusdp_in,abus_s)
begin
if abus_s(0)='0' then
outbus_s <= dbusdp_in(7 downto 0); -- D0
else
outbus_s <= dbusdp_in(15 downto 8); -- D1
end if;
end process;
---------------------------------------------------------------------------
-- Latch word for BIU FSM
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
w_biufsm_s<='0';
elsif rising_edge(clk) then
if latchrw='1' then
w_biufsm_s<=word;
end if;
end if;
end process;
-- metastability sync
process(reset,clk) -- ireg
begin
if reset='1' then
nmipre_s <= "00";
elsif rising_edge(clk) then
nmipre_s <= nmipre_s(0) & nmi;
end if;
end process;
-- set/reset FF
process(reset, clk) -- ireg
begin
if (reset='1') then
nmi_s <= '0';
elsif rising_edge(clk) then
if (irq_clr='1') then
nmi_s <= '0';
else
nmi_s <= nmi_s or ((not nmipre_s(1)) and nmipre_s(0));
end if;
end if;
end process;
-- Instruction trace flag, the trace flag is latched by the decode_state signal. This will
-- result in the instruction after setting the trace flag not being traced (required).
-- The instr_trace_s flag is not set if the current instruction is a HLT
process(reset, clk)
begin
if (reset='1') then
instr_trace_s <= '0';
elsif rising_edge(clk) then
if (decode_state='1' and halt_instr='0') then
instr_trace_s <= status.flag(8);
end if;
end if;
end process;
-- int0_req=Divider/0 error
-- status(8)=TF
-- status(9)=IF
irq_req_s <= '1' when ((status.div_err='1' or instr_trace_s='1' or nmi_s='1' or (status.flag(9)='1' and intr='1')) and irq_block='0') else '0';
-- set/reset FF
process(reset, clk) -- ireg
begin
if (reset='1') then
irq_req_internal <= '0';
elsif rising_edge(clk) then
if (irq_clr='1') then
irq_req_internal <= '0';
elsif irq_req_s='1' then
irq_req_internal <= '1';
end if;
end if;
end process;
--process (nmi_s,status,intr)
process (reset,clk)
begin
if reset='1' then
irq_type <= (others => '0'); -- Don't care value
elsif rising_edge(clk) then
if irq_req_internal='1' then
if nmi_s='1' then
irq_type <= "10"; -- NMI result in INT2
elsif status.flag(8)='1' then
irq_type <= "01"; -- TF result in INT1
else
irq_type <= "00"; -- INTR result in INT <DBUS>
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Delayed signals
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
latchrw_d_s <= '0';
latchclr_d_s <= '0';
elsif rising_edge(clk) then
latchrw_d_s <= latchrw;
latchclr_d_s <= latchclr;
end if;
end process;
---------------------------------------------------------------------------
-- IO/~M strobe latch
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
iom_s <= '0';
elsif rising_edge(clk) then
if latchrw='1' and muxabus/="00" then
iom_s <= iomem;
elsif latchrw='1' then
iom_s <= '0';
end if;
end if;
end process;
iom <= iom_s;
---------------------------------------------------------------------------
-- Shifted WR strobe latch, to add some address and data hold time the WR
-- strobe is negated .5 clock cycles before address and data changes. This
-- is implemented using the falling edge of the clock. Generally using
-- both edges of a clock is not recommended. If this is not desirable
-- use the latchclr signal with the rising edge of clk. This will result
-- in a full clk cycle for the data hold.
---------------------------------------------------------------------------
process(clk,reset) -- note wr should be 1 clk cycle after latchrw
begin
if reset='1' then
wran <= '1';
elsif falling_edge(clk) then -- wran is negated 0.5 cycle before data&address changes
if latchclr_d_s='1' then
wran <= '1';
elsif wr_s='1' then
wran<='0';
end if;
-- elsif rising_edge(clk) then -- wran negated 1 clk cycle before data&address changes
-- if latchclr='1' then
-- wran <= '1';
-- elsif wr_s='1' then
-- wran<='0';
-- end if;
end if;
end process;
---------------------------------------------------------------------------
-- WR strobe latch. This signal can be use to drive the tri-state drivers
-- and will result in a data hold time until the end of the write cycle.
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
wrn <= '1';
elsif rising_edge(clk) then
if latchclr_d_s='1' then -- Change wrn at the same time as addr changes
wrn <= '1';
elsif wr_s='1' then
wrn<='0';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- RD strobe latch
-- rd is active low and connected to top entity
-- Use 1 clk delayed latchrw_d_s signal
-- Original signals were rd_data_s and rd_code_s, new signals rddata_s and
-- rdcode_s.
-- Add flushreq_s, prevend rd signal from starting
---------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
rdn <= '1';
latchmd_s <= '0';
elsif rising_edge(clk) then
if latchclr_d_s='1' then
rdn <= '1';
latchmd_s <= '0';
elsif latchrw_d_s='1' then
latchmd_s <= rddata_s;
-- Bug reported by Rick Kilgore
-- ver 0.69, stops RD from being asserted during second inta
rdn <= not((rdcode_s or rddata_s) AND NOT intack);
-- The next second was added to create a updown pulse on the rd strobe
-- during a flush action. This will result in a dummy read cycle (unavoidable?)
elsif latchrw='1' then
latchmd_s <= rddata_s;
rdn <= not(rdcode_s or rddata_s);
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Second INTA strobe latch
---------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
inta2_s<= '0';
elsif rising_edge(clk) then
if latchclr_d_s='1' then
inta2_s <= '0';
elsif latchrw_d_s='1' then
inta2_s <= intack;
end if;
end if;
end process;
inta <= not (inta2_s OR inta1_internal);
---------------------------------------------------------------------------
-- Databus stearing for the datapath input
-- mdbus_out(31..16) is only used for "int x", the value si used to load
-- ipreg at the same time as loading cs.
-- Note mdbus must be valid (i.e. contain dbus value) before rising edge
-- of wrn/rdn
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
mdbus_out <= (others => '0');
elsif rising_edge(clk) then
if latchmd_s='1' then
if word='0' then -- byte read
mdbus_out <= X"00" & dbus_in;
else
if muxabus="00" then -- first cycle of word read
mdbus_out(15 downto 8) <= dbus_in;
else -- Second cycle
mdbus_out(7 downto 0) <= dbus_in;
end if;
end if;
end if;
end if;
end process;
process(reset,clk)
begin
if reset='1' then
ipbusbiu_s <= RESET_IP_C; -- start 0x0000, CS=FFFF
csbusbiu_s <= RESET_CS_C;
elsif rising_edge(clk) then
if latchabus='1' then
if (addrplus4='1') then
ipbusbiu_s <= ipbusbiu_s+'1';
else
ipbusbiu_s <= ipbus; -- get new address after flush
csbusbiu_s <= csbus;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- Latch datapath address+4 for mis-aligned R/W
-------------------------------------------------------------------------
ipbusp1_s <= ipbus+'1';
abusdp_inp1l_s <= ipbus when latchrw='0' else ipbusp1_s;
process(abusdp_inp1l_s,muxabus,csbusbiu_s,ipbusbiu_s,csbus,ipbus)
begin
case muxabus is
when "01" => abus_s <= (csbus&"0000") + ("0000"&ipbus); --abusdp_in;
when "10" => abus_s <= (csbus&"0000") + ("0000"&abusdp_inp1l_s); -- Add 1 if odd address and write word
when others => abus_s <= (csbusbiu_s&"0000") + ("0000"&ipbusbiu_s); -- default to BIU word address
end case;
end process;
-------------------------------------------------------------------------
-- Address/Databus Latch
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
abus <= RESET_VECTOR_C;
elsif rising_edge(clk) then
if latchrw='1' then -- Latch Address
abus <= abus_s;
end if;
end if;
end process;
-- Instance port mappings.
fsm : biufsm
PORT MAP (
clk => clk,
flush_coming => flush_coming,
flush_req => flush_req,
irq_req => irq_req_internal,
irq_type => irq_type,
opc_req => opc_req,
read_req => read_req,
reg1freed => reg1freed,
reg4free => reg4free,
regnbok => regnbok,
reset => reset,
w_biufsm_s => w_biufsm_s,
write_req => write_req,
addrplus4 => addrplus4,
biu_error => biu_error,
biu_status => biu_status,
irq_ack => irq_ack,
irq_clr => irq_clr,
latchabus => latchabus,
latchclr => latchclr,
latchm => latchm,
latcho => latcho_internal,
latchrw => latchrw,
ldposplus1 => ldposplus1,
muxabus => muxabus,
rdcode_s => rdcode_s,
rddata_s => rddata_s,
regplus1 => regplus1,
rw_ack => rw_ack,
wr_s => wr_s,
flush_ack => flush_ack_internal,
inta1 => inta1_internal
);
I4 : formatter
PORT MAP (
lutbus => lutbus,
mux_addr => mux_addr,
mux_data => mux_data,
mux_reg => mux_reg,
nbreq => nbreq
);
shift : regshiftmux
PORT MAP (
clk => clk,
dbus_in => dbus_in,
flush_req => flush_req,
latchm => latchm,
latcho => latcho_internal,
mux_addr => mux_addr,
mux_data => mux_data,
mux_reg => mux_reg,
nbreq => nbreq,
regplus1 => regplus1,
ldposplus1 => ldposplus1,
reset => reset,
irq => irq_ack,
inta1 => inta1_internal,
inta2_s => inta2_s,
irq_type => irq_type,
instr => instr,
halt_instr => halt_instr,
lutbus => lutbus,
reg1free => reg4free,
reg1freed => reg1freed,
regnbok => regnbok
);
flush_ack <= flush_ack_internal;
inta1 <= inta1_internal;
irq_req <= irq_req_internal;
latcho <= latcho_internal;
END struct;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.cpu86pack.ALL;
ENTITY biu IS
PORT(
clk : IN std_logic;
csbus : IN std_logic_vector (15 DOWNTO 0);
dbus_in : IN std_logic_vector (7 DOWNTO 0);
dbusdp_in : IN std_logic_vector (15 DOWNTO 0);
decode_state : IN std_logic;
flush_coming : IN std_logic;
flush_req : IN std_logic;
intack : IN std_logic;
intr : IN std_logic;
iomem : IN std_logic;
ipbus : IN std_logic_vector (15 DOWNTO 0);
irq_block : IN std_logic;
nmi : IN std_logic;
opc_req : IN std_logic;
read_req : IN std_logic;
reset : IN std_logic;
status : IN status_out_type;
word : IN std_logic;
write_req : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
biu_error : OUT std_logic;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
flush_ack : OUT std_logic;
instr : OUT instruction_type;
inta : OUT std_logic;
inta1 : OUT std_logic;
iom : OUT std_logic;
irq_req : OUT std_logic;
latcho : OUT std_logic;
mdbus_out : OUT std_logic_vector (15 DOWNTO 0);
rdn : OUT std_logic;
rw_ack : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END biu ;
ARCHITECTURE struct OF biu IS
SIGNAL abus_s : std_logic_vector(19 DOWNTO 0);
SIGNAL abusdp_in : std_logic_vector(19 DOWNTO 0);
SIGNAL addrplus4 : std_logic;
SIGNAL biu_status : std_logic_vector(2 DOWNTO 0);
SIGNAL csbusbiu_s : std_logic_vector(15 DOWNTO 0);
SIGNAL halt_instr : std_logic;
SIGNAL inta2_s : std_logic; -- Second INTA pulse, used to latch 8 bist vector
SIGNAL ipbusbiu_s : std_logic_vector(15 DOWNTO 0);
SIGNAL ipbusp1_s : std_logic_vector(15 DOWNTO 0);
SIGNAL irq_ack : std_logic;
SIGNAL irq_clr : std_logic;
SIGNAL irq_type : std_logic_vector(1 DOWNTO 0);
SIGNAL latchabus : std_logic;
SIGNAL latchclr : std_logic;
SIGNAL latchm : std_logic;
SIGNAL latchrw : std_logic;
SIGNAL ldposplus1 : std_logic;
SIGNAL lutbus : std_logic_vector(15 DOWNTO 0);
SIGNAL mux_addr : std_logic_vector(2 DOWNTO 0);
SIGNAL mux_data : std_logic_vector(3 DOWNTO 0);
SIGNAL mux_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL muxabus : std_logic_vector(1 DOWNTO 0);
SIGNAL nbreq : std_logic_vector(2 DOWNTO 0);
SIGNAL rdcode_s : std_logic;
SIGNAL rddata_s : std_logic;
SIGNAL reg1freed : std_logic; -- Delayed version (1 clk) of reg1free
SIGNAL reg4free : std_logic;
SIGNAL regnbok : std_logic;
SIGNAL regplus1 : std_logic;
SIGNAL w_biufsm_s : std_logic;
SIGNAL wr_s : std_logic;
SIGNAL flush_ack_internal : std_logic;
SIGNAL inta1_internal : std_logic;
SIGNAL irq_req_internal : std_logic;
SIGNAL latcho_internal : std_logic;
signal nmi_s : std_logic;
signal nmipre_s : std_logic_vector(1 downto 0); -- metastability first FF for nmi
signal outbus_s : std_logic_vector(7 downto 0); -- used in out instr. bus streering
signal latchmd_s : std_logic; -- internal rdl_s signal
signal abusdp_inp1l_s: std_logic_vector(15 downto 0);
signal latchrw_d_s: std_logic; -- latchrw delayed 1 clk cycle
signal latchclr_d_s: std_logic; -- latchclr delayed 1 clk cycle
signal iom_s : std_logic;
signal instr_trace_s : std_logic; -- TF latched by exec_state pulse
signal irq_req_s : std_logic;
-- Component Declarations
COMPONENT biufsm
PORT (
clk : IN std_logic ;
flush_coming : IN std_logic ;
flush_req : IN std_logic ;
irq_req : IN std_logic ;
irq_type : IN std_logic_vector (1 DOWNTO 0);
opc_req : IN std_logic ;
read_req : IN std_logic ;
reg1freed : IN std_logic ;
reg4free : IN std_logic ;
regnbok : IN std_logic ;
reset : IN std_logic ;
w_biufsm_s : IN std_logic ;
write_req : IN std_logic ;
addrplus4 : OUT std_logic ;
biu_error : OUT std_logic ;
biu_status : OUT std_logic_vector (2 DOWNTO 0);
irq_ack : OUT std_logic ;
irq_clr : OUT std_logic ;
latchabus : OUT std_logic ;
latchclr : OUT std_logic ;
latchm : OUT std_logic ;
latcho : OUT std_logic ;
latchrw : OUT std_logic ;
ldposplus1 : OUT std_logic ;
muxabus : OUT std_logic_vector (1 DOWNTO 0);
rdcode_s : OUT std_logic ;
rddata_s : OUT std_logic ;
regplus1 : OUT std_logic ;
rw_ack : OUT std_logic ;
wr_s : OUT std_logic ;
flush_ack : BUFFER std_logic ;
inta1 : BUFFER std_logic
);
END COMPONENT;
COMPONENT formatter
PORT (
lutbus : IN std_logic_vector (15 DOWNTO 0);
mux_addr : OUT std_logic_vector (2 DOWNTO 0);
mux_data : OUT std_logic_vector (3 DOWNTO 0);
mux_reg : OUT std_logic_vector (2 DOWNTO 0);
nbreq : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
COMPONENT regshiftmux
PORT (
clk : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
flush_req : IN std_logic ;
latchm : IN std_logic ;
latcho : IN std_logic ;
mux_addr : IN std_logic_vector (2 DOWNTO 0);
mux_data : IN std_logic_vector (3 DOWNTO 0);
mux_reg : IN std_logic_vector (2 DOWNTO 0);
nbreq : IN std_logic_vector (2 DOWNTO 0);
regplus1 : IN std_logic ;
ldposplus1 : IN std_logic ;
reset : IN std_logic ;
irq : IN std_logic ;
inta1 : IN std_logic ; -- Added for ver 0.71
inta2_s : IN std_logic ;
irq_type : IN std_logic_vector (1 DOWNTO 0);
instr : OUT instruction_type ;
halt_instr : OUT std_logic ;
lutbus : OUT std_logic_vector (15 DOWNTO 0);
reg1free : BUFFER std_logic ;
reg1freed : BUFFER std_logic ; -- Delayed version (1 clk) of reg1free
regnbok : OUT std_logic
);
END COMPONENT;
BEGIN
-------------------------------------------------------------------------
-- Databus Latch
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
dbus_out <= DONTCARE(7 downto 0);
elsif rising_edge(clk) then
if latchrw='1' then -- Latch Data from DataPath
dbus_out <= outbus_s;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- OUT instruction bus steering
-- IO/~M & A[1:0]
---------------------------------------------------------------------------
process(dbusdp_in,abus_s)
begin
if abus_s(0)='0' then
outbus_s <= dbusdp_in(7 downto 0); -- D0
else
outbus_s <= dbusdp_in(15 downto 8); -- D1
end if;
end process;
---------------------------------------------------------------------------
-- Latch word for BIU FSM
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
w_biufsm_s<='0';
elsif rising_edge(clk) then
if latchrw='1' then
w_biufsm_s<=word;
end if;
end if;
end process;
-- metastability sync
process(reset,clk) -- ireg
begin
if reset='1' then
nmipre_s <= "00";
elsif rising_edge(clk) then
nmipre_s <= nmipre_s(0) & nmi;
end if;
end process;
-- set/reset FF
process(reset, clk) -- ireg
begin
if (reset='1') then
nmi_s <= '0';
elsif rising_edge(clk) then
if (irq_clr='1') then
nmi_s <= '0';
else
nmi_s <= nmi_s or ((not nmipre_s(1)) and nmipre_s(0));
end if;
end if;
end process;
-- Instruction trace flag, the trace flag is latched by the decode_state signal. This will
-- result in the instruction after setting the trace flag not being traced (required).
-- The instr_trace_s flag is not set if the current instruction is a HLT
process(reset, clk)
begin
if (reset='1') then
instr_trace_s <= '0';
elsif rising_edge(clk) then
if (decode_state='1' and halt_instr='0') then
instr_trace_s <= status.flag(8);
end if;
end if;
end process;
-- int0_req=Divider/0 error
-- status(8)=TF
-- status(9)=IF
irq_req_s <= '1' when ((status.div_err='1' or instr_trace_s='1' or nmi_s='1' or (status.flag(9)='1' and intr='1')) and irq_block='0') else '0';
-- set/reset FF
process(reset, clk) -- ireg
begin
if (reset='1') then
irq_req_internal <= '0';
elsif rising_edge(clk) then
if (irq_clr='1') then
irq_req_internal <= '0';
elsif irq_req_s='1' then
irq_req_internal <= '1';
end if;
end if;
end process;
--process (nmi_s,status,intr)
process (reset,clk)
begin
if reset='1' then
irq_type <= (others => '0'); -- Don't care value
elsif rising_edge(clk) then
if irq_req_internal='1' then
if nmi_s='1' then
irq_type <= "10"; -- NMI result in INT2
elsif status.flag(8)='1' then
irq_type <= "01"; -- TF result in INT1
else
irq_type <= "00"; -- INTR result in INT <DBUS>
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Delayed signals
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
latchrw_d_s <= '0';
latchclr_d_s <= '0';
elsif rising_edge(clk) then
latchrw_d_s <= latchrw;
latchclr_d_s <= latchclr;
end if;
end process;
---------------------------------------------------------------------------
-- IO/~M strobe latch
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
iom_s <= '0';
elsif rising_edge(clk) then
if latchrw='1' and muxabus/="00" then
iom_s <= iomem;
elsif latchrw='1' then
iom_s <= '0';
end if;
end if;
end process;
iom <= iom_s;
---------------------------------------------------------------------------
-- Shifted WR strobe latch, to add some address and data hold time the WR
-- strobe is negated .5 clock cycles before address and data changes. This
-- is implemented using the falling edge of the clock. Generally using
-- both edges of a clock is not recommended. If this is not desirable
-- use the latchclr signal with the rising edge of clk. This will result
-- in a full clk cycle for the data hold.
---------------------------------------------------------------------------
process(clk,reset) -- note wr should be 1 clk cycle after latchrw
begin
if reset='1' then
wran <= '1';
elsif falling_edge(clk) then -- wran is negated 0.5 cycle before data&address changes
if latchclr_d_s='1' then
wran <= '1';
elsif wr_s='1' then
wran<='0';
end if;
-- elsif rising_edge(clk) then -- wran negated 1 clk cycle before data&address changes
-- if latchclr='1' then
-- wran <= '1';
-- elsif wr_s='1' then
-- wran<='0';
-- end if;
end if;
end process;
---------------------------------------------------------------------------
-- WR strobe latch. This signal can be use to drive the tri-state drivers
-- and will result in a data hold time until the end of the write cycle.
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
wrn <= '1';
elsif rising_edge(clk) then
if latchclr_d_s='1' then -- Change wrn at the same time as addr changes
wrn <= '1';
elsif wr_s='1' then
wrn<='0';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- RD strobe latch
-- rd is active low and connected to top entity
-- Use 1 clk delayed latchrw_d_s signal
-- Original signals were rd_data_s and rd_code_s, new signals rddata_s and
-- rdcode_s.
-- Add flushreq_s, prevend rd signal from starting
---------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
rdn <= '1';
latchmd_s <= '0';
elsif rising_edge(clk) then
if latchclr_d_s='1' then
rdn <= '1';
latchmd_s <= '0';
elsif latchrw_d_s='1' then
latchmd_s <= rddata_s;
-- Bug reported by Rick Kilgore
-- ver 0.69, stops RD from being asserted during second inta
rdn <= not((rdcode_s or rddata_s) AND NOT intack);
-- The next second was added to create a updown pulse on the rd strobe
-- during a flush action. This will result in a dummy read cycle (unavoidable?)
elsif latchrw='1' then
latchmd_s <= rddata_s;
rdn <= not(rdcode_s or rddata_s);
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Second INTA strobe latch
---------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
inta2_s<= '0';
elsif rising_edge(clk) then
if latchclr_d_s='1' then
inta2_s <= '0';
elsif latchrw_d_s='1' then
inta2_s <= intack;
end if;
end if;
end process;
inta <= not (inta2_s OR inta1_internal);
---------------------------------------------------------------------------
-- Databus stearing for the datapath input
-- mdbus_out(31..16) is only used for "int x", the value si used to load
-- ipreg at the same time as loading cs.
-- Note mdbus must be valid (i.e. contain dbus value) before rising edge
-- of wrn/rdn
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
mdbus_out <= (others => '0');
elsif rising_edge(clk) then
if latchmd_s='1' then
if word='0' then -- byte read
mdbus_out <= X"00" & dbus_in;
else
if muxabus="00" then -- first cycle of word read
mdbus_out(15 downto 8) <= dbus_in;
else -- Second cycle
mdbus_out(7 downto 0) <= dbus_in;
end if;
end if;
end if;
end if;
end process;
process(reset,clk)
begin
if reset='1' then
ipbusbiu_s <= RESET_IP_C; -- start 0x0000, CS=FFFF
csbusbiu_s <= RESET_CS_C;
elsif rising_edge(clk) then
if latchabus='1' then
if (addrplus4='1') then
ipbusbiu_s <= ipbusbiu_s+'1';
else
ipbusbiu_s <= ipbus; -- get new address after flush
csbusbiu_s <= csbus;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- Latch datapath address+4 for mis-aligned R/W
-------------------------------------------------------------------------
ipbusp1_s <= ipbus+'1';
abusdp_inp1l_s <= ipbus when latchrw='0' else ipbusp1_s;
process(abusdp_inp1l_s,muxabus,csbusbiu_s,ipbusbiu_s,csbus,ipbus)
begin
case muxabus is
when "01" => abus_s <= (csbus&"0000") + ("0000"&ipbus); --abusdp_in;
when "10" => abus_s <= (csbus&"0000") + ("0000"&abusdp_inp1l_s); -- Add 1 if odd address and write word
when others => abus_s <= (csbusbiu_s&"0000") + ("0000"&ipbusbiu_s); -- default to BIU word address
end case;
end process;
-------------------------------------------------------------------------
-- Address/Databus Latch
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
abus <= RESET_VECTOR_C;
elsif rising_edge(clk) then
if latchrw='1' then -- Latch Address
abus <= abus_s;
end if;
end if;
end process;
-- Instance port mappings.
fsm : biufsm
PORT MAP (
clk => clk,
flush_coming => flush_coming,
flush_req => flush_req,
irq_req => irq_req_internal,
irq_type => irq_type,
opc_req => opc_req,
read_req => read_req,
reg1freed => reg1freed,
reg4free => reg4free,
regnbok => regnbok,
reset => reset,
w_biufsm_s => w_biufsm_s,
write_req => write_req,
addrplus4 => addrplus4,
biu_error => biu_error,
biu_status => biu_status,
irq_ack => irq_ack,
irq_clr => irq_clr,
latchabus => latchabus,
latchclr => latchclr,
latchm => latchm,
latcho => latcho_internal,
latchrw => latchrw,
ldposplus1 => ldposplus1,
muxabus => muxabus,
rdcode_s => rdcode_s,
rddata_s => rddata_s,
regplus1 => regplus1,
rw_ack => rw_ack,
wr_s => wr_s,
flush_ack => flush_ack_internal,
inta1 => inta1_internal
);
I4 : formatter
PORT MAP (
lutbus => lutbus,
mux_addr => mux_addr,
mux_data => mux_data,
mux_reg => mux_reg,
nbreq => nbreq
);
shift : regshiftmux
PORT MAP (
clk => clk,
dbus_in => dbus_in,
flush_req => flush_req,
latchm => latchm,
latcho => latcho_internal,
mux_addr => mux_addr,
mux_data => mux_data,
mux_reg => mux_reg,
nbreq => nbreq,
regplus1 => regplus1,
ldposplus1 => ldposplus1,
reset => reset,
irq => irq_ack,
inta1 => inta1_internal,
inta2_s => inta2_s,
irq_type => irq_type,
instr => instr,
halt_instr => halt_instr,
lutbus => lutbus,
reg1free => reg4free,
reg1freed => reg1freed,
regnbok => regnbok
);
flush_ack <= flush_ack_internal;
inta1 <= inta1_internal;
irq_req <= irq_req_internal;
latcho <= latcho_internal;
END struct;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.cpu86pack.ALL;
ENTITY biu IS
PORT(
clk : IN std_logic;
csbus : IN std_logic_vector (15 DOWNTO 0);
dbus_in : IN std_logic_vector (7 DOWNTO 0);
dbusdp_in : IN std_logic_vector (15 DOWNTO 0);
decode_state : IN std_logic;
flush_coming : IN std_logic;
flush_req : IN std_logic;
intack : IN std_logic;
intr : IN std_logic;
iomem : IN std_logic;
ipbus : IN std_logic_vector (15 DOWNTO 0);
irq_block : IN std_logic;
nmi : IN std_logic;
opc_req : IN std_logic;
read_req : IN std_logic;
reset : IN std_logic;
status : IN status_out_type;
word : IN std_logic;
write_req : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
biu_error : OUT std_logic;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
flush_ack : OUT std_logic;
instr : OUT instruction_type;
inta : OUT std_logic;
inta1 : OUT std_logic;
iom : OUT std_logic;
irq_req : OUT std_logic;
latcho : OUT std_logic;
mdbus_out : OUT std_logic_vector (15 DOWNTO 0);
rdn : OUT std_logic;
rw_ack : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END biu ;
ARCHITECTURE struct OF biu IS
SIGNAL abus_s : std_logic_vector(19 DOWNTO 0);
SIGNAL abusdp_in : std_logic_vector(19 DOWNTO 0);
SIGNAL addrplus4 : std_logic;
SIGNAL biu_status : std_logic_vector(2 DOWNTO 0);
SIGNAL csbusbiu_s : std_logic_vector(15 DOWNTO 0);
SIGNAL halt_instr : std_logic;
SIGNAL inta2_s : std_logic; -- Second INTA pulse, used to latch 8 bist vector
SIGNAL ipbusbiu_s : std_logic_vector(15 DOWNTO 0);
SIGNAL ipbusp1_s : std_logic_vector(15 DOWNTO 0);
SIGNAL irq_ack : std_logic;
SIGNAL irq_clr : std_logic;
SIGNAL irq_type : std_logic_vector(1 DOWNTO 0);
SIGNAL latchabus : std_logic;
SIGNAL latchclr : std_logic;
SIGNAL latchm : std_logic;
SIGNAL latchrw : std_logic;
SIGNAL ldposplus1 : std_logic;
SIGNAL lutbus : std_logic_vector(15 DOWNTO 0);
SIGNAL mux_addr : std_logic_vector(2 DOWNTO 0);
SIGNAL mux_data : std_logic_vector(3 DOWNTO 0);
SIGNAL mux_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL muxabus : std_logic_vector(1 DOWNTO 0);
SIGNAL nbreq : std_logic_vector(2 DOWNTO 0);
SIGNAL rdcode_s : std_logic;
SIGNAL rddata_s : std_logic;
SIGNAL reg1freed : std_logic; -- Delayed version (1 clk) of reg1free
SIGNAL reg4free : std_logic;
SIGNAL regnbok : std_logic;
SIGNAL regplus1 : std_logic;
SIGNAL w_biufsm_s : std_logic;
SIGNAL wr_s : std_logic;
SIGNAL flush_ack_internal : std_logic;
SIGNAL inta1_internal : std_logic;
SIGNAL irq_req_internal : std_logic;
SIGNAL latcho_internal : std_logic;
signal nmi_s : std_logic;
signal nmipre_s : std_logic_vector(1 downto 0); -- metastability first FF for nmi
signal outbus_s : std_logic_vector(7 downto 0); -- used in out instr. bus streering
signal latchmd_s : std_logic; -- internal rdl_s signal
signal abusdp_inp1l_s: std_logic_vector(15 downto 0);
signal latchrw_d_s: std_logic; -- latchrw delayed 1 clk cycle
signal latchclr_d_s: std_logic; -- latchclr delayed 1 clk cycle
signal iom_s : std_logic;
signal instr_trace_s : std_logic; -- TF latched by exec_state pulse
signal irq_req_s : std_logic;
-- Component Declarations
COMPONENT biufsm
PORT (
clk : IN std_logic ;
flush_coming : IN std_logic ;
flush_req : IN std_logic ;
irq_req : IN std_logic ;
irq_type : IN std_logic_vector (1 DOWNTO 0);
opc_req : IN std_logic ;
read_req : IN std_logic ;
reg1freed : IN std_logic ;
reg4free : IN std_logic ;
regnbok : IN std_logic ;
reset : IN std_logic ;
w_biufsm_s : IN std_logic ;
write_req : IN std_logic ;
addrplus4 : OUT std_logic ;
biu_error : OUT std_logic ;
biu_status : OUT std_logic_vector (2 DOWNTO 0);
irq_ack : OUT std_logic ;
irq_clr : OUT std_logic ;
latchabus : OUT std_logic ;
latchclr : OUT std_logic ;
latchm : OUT std_logic ;
latcho : OUT std_logic ;
latchrw : OUT std_logic ;
ldposplus1 : OUT std_logic ;
muxabus : OUT std_logic_vector (1 DOWNTO 0);
rdcode_s : OUT std_logic ;
rddata_s : OUT std_logic ;
regplus1 : OUT std_logic ;
rw_ack : OUT std_logic ;
wr_s : OUT std_logic ;
flush_ack : BUFFER std_logic ;
inta1 : BUFFER std_logic
);
END COMPONENT;
COMPONENT formatter
PORT (
lutbus : IN std_logic_vector (15 DOWNTO 0);
mux_addr : OUT std_logic_vector (2 DOWNTO 0);
mux_data : OUT std_logic_vector (3 DOWNTO 0);
mux_reg : OUT std_logic_vector (2 DOWNTO 0);
nbreq : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
COMPONENT regshiftmux
PORT (
clk : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
flush_req : IN std_logic ;
latchm : IN std_logic ;
latcho : IN std_logic ;
mux_addr : IN std_logic_vector (2 DOWNTO 0);
mux_data : IN std_logic_vector (3 DOWNTO 0);
mux_reg : IN std_logic_vector (2 DOWNTO 0);
nbreq : IN std_logic_vector (2 DOWNTO 0);
regplus1 : IN std_logic ;
ldposplus1 : IN std_logic ;
reset : IN std_logic ;
irq : IN std_logic ;
inta1 : IN std_logic ; -- Added for ver 0.71
inta2_s : IN std_logic ;
irq_type : IN std_logic_vector (1 DOWNTO 0);
instr : OUT instruction_type ;
halt_instr : OUT std_logic ;
lutbus : OUT std_logic_vector (15 DOWNTO 0);
reg1free : BUFFER std_logic ;
reg1freed : BUFFER std_logic ; -- Delayed version (1 clk) of reg1free
regnbok : OUT std_logic
);
END COMPONENT;
BEGIN
-------------------------------------------------------------------------
-- Databus Latch
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
dbus_out <= DONTCARE(7 downto 0);
elsif rising_edge(clk) then
if latchrw='1' then -- Latch Data from DataPath
dbus_out <= outbus_s;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- OUT instruction bus steering
-- IO/~M & A[1:0]
---------------------------------------------------------------------------
process(dbusdp_in,abus_s)
begin
if abus_s(0)='0' then
outbus_s <= dbusdp_in(7 downto 0); -- D0
else
outbus_s <= dbusdp_in(15 downto 8); -- D1
end if;
end process;
---------------------------------------------------------------------------
-- Latch word for BIU FSM
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
w_biufsm_s<='0';
elsif rising_edge(clk) then
if latchrw='1' then
w_biufsm_s<=word;
end if;
end if;
end process;
-- metastability sync
process(reset,clk) -- ireg
begin
if reset='1' then
nmipre_s <= "00";
elsif rising_edge(clk) then
nmipre_s <= nmipre_s(0) & nmi;
end if;
end process;
-- set/reset FF
process(reset, clk) -- ireg
begin
if (reset='1') then
nmi_s <= '0';
elsif rising_edge(clk) then
if (irq_clr='1') then
nmi_s <= '0';
else
nmi_s <= nmi_s or ((not nmipre_s(1)) and nmipre_s(0));
end if;
end if;
end process;
-- Instruction trace flag, the trace flag is latched by the decode_state signal. This will
-- result in the instruction after setting the trace flag not being traced (required).
-- The instr_trace_s flag is not set if the current instruction is a HLT
process(reset, clk)
begin
if (reset='1') then
instr_trace_s <= '0';
elsif rising_edge(clk) then
if (decode_state='1' and halt_instr='0') then
instr_trace_s <= status.flag(8);
end if;
end if;
end process;
-- int0_req=Divider/0 error
-- status(8)=TF
-- status(9)=IF
irq_req_s <= '1' when ((status.div_err='1' or instr_trace_s='1' or nmi_s='1' or (status.flag(9)='1' and intr='1')) and irq_block='0') else '0';
-- set/reset FF
process(reset, clk) -- ireg
begin
if (reset='1') then
irq_req_internal <= '0';
elsif rising_edge(clk) then
if (irq_clr='1') then
irq_req_internal <= '0';
elsif irq_req_s='1' then
irq_req_internal <= '1';
end if;
end if;
end process;
--process (nmi_s,status,intr)
process (reset,clk)
begin
if reset='1' then
irq_type <= (others => '0'); -- Don't care value
elsif rising_edge(clk) then
if irq_req_internal='1' then
if nmi_s='1' then
irq_type <= "10"; -- NMI result in INT2
elsif status.flag(8)='1' then
irq_type <= "01"; -- TF result in INT1
else
irq_type <= "00"; -- INTR result in INT <DBUS>
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Delayed signals
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
latchrw_d_s <= '0';
latchclr_d_s <= '0';
elsif rising_edge(clk) then
latchrw_d_s <= latchrw;
latchclr_d_s <= latchclr;
end if;
end process;
---------------------------------------------------------------------------
-- IO/~M strobe latch
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
iom_s <= '0';
elsif rising_edge(clk) then
if latchrw='1' and muxabus/="00" then
iom_s <= iomem;
elsif latchrw='1' then
iom_s <= '0';
end if;
end if;
end process;
iom <= iom_s;
---------------------------------------------------------------------------
-- Shifted WR strobe latch, to add some address and data hold time the WR
-- strobe is negated .5 clock cycles before address and data changes. This
-- is implemented using the falling edge of the clock. Generally using
-- both edges of a clock is not recommended. If this is not desirable
-- use the latchclr signal with the rising edge of clk. This will result
-- in a full clk cycle for the data hold.
---------------------------------------------------------------------------
process(clk,reset) -- note wr should be 1 clk cycle after latchrw
begin
if reset='1' then
wran <= '1';
elsif falling_edge(clk) then -- wran is negated 0.5 cycle before data&address changes
if latchclr_d_s='1' then
wran <= '1';
elsif wr_s='1' then
wran<='0';
end if;
-- elsif rising_edge(clk) then -- wran negated 1 clk cycle before data&address changes
-- if latchclr='1' then
-- wran <= '1';
-- elsif wr_s='1' then
-- wran<='0';
-- end if;
end if;
end process;
---------------------------------------------------------------------------
-- WR strobe latch. This signal can be use to drive the tri-state drivers
-- and will result in a data hold time until the end of the write cycle.
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
wrn <= '1';
elsif rising_edge(clk) then
if latchclr_d_s='1' then -- Change wrn at the same time as addr changes
wrn <= '1';
elsif wr_s='1' then
wrn<='0';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- RD strobe latch
-- rd is active low and connected to top entity
-- Use 1 clk delayed latchrw_d_s signal
-- Original signals were rd_data_s and rd_code_s, new signals rddata_s and
-- rdcode_s.
-- Add flushreq_s, prevend rd signal from starting
---------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
rdn <= '1';
latchmd_s <= '0';
elsif rising_edge(clk) then
if latchclr_d_s='1' then
rdn <= '1';
latchmd_s <= '0';
elsif latchrw_d_s='1' then
latchmd_s <= rddata_s;
-- Bug reported by Rick Kilgore
-- ver 0.69, stops RD from being asserted during second inta
rdn <= not((rdcode_s or rddata_s) AND NOT intack);
-- The next second was added to create a updown pulse on the rd strobe
-- during a flush action. This will result in a dummy read cycle (unavoidable?)
elsif latchrw='1' then
latchmd_s <= rddata_s;
rdn <= not(rdcode_s or rddata_s);
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Second INTA strobe latch
---------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
inta2_s<= '0';
elsif rising_edge(clk) then
if latchclr_d_s='1' then
inta2_s <= '0';
elsif latchrw_d_s='1' then
inta2_s <= intack;
end if;
end if;
end process;
inta <= not (inta2_s OR inta1_internal);
---------------------------------------------------------------------------
-- Databus stearing for the datapath input
-- mdbus_out(31..16) is only used for "int x", the value si used to load
-- ipreg at the same time as loading cs.
-- Note mdbus must be valid (i.e. contain dbus value) before rising edge
-- of wrn/rdn
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
mdbus_out <= (others => '0');
elsif rising_edge(clk) then
if latchmd_s='1' then
if word='0' then -- byte read
mdbus_out <= X"00" & dbus_in;
else
if muxabus="00" then -- first cycle of word read
mdbus_out(15 downto 8) <= dbus_in;
else -- Second cycle
mdbus_out(7 downto 0) <= dbus_in;
end if;
end if;
end if;
end if;
end process;
process(reset,clk)
begin
if reset='1' then
ipbusbiu_s <= RESET_IP_C; -- start 0x0000, CS=FFFF
csbusbiu_s <= RESET_CS_C;
elsif rising_edge(clk) then
if latchabus='1' then
if (addrplus4='1') then
ipbusbiu_s <= ipbusbiu_s+'1';
else
ipbusbiu_s <= ipbus; -- get new address after flush
csbusbiu_s <= csbus;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- Latch datapath address+4 for mis-aligned R/W
-------------------------------------------------------------------------
ipbusp1_s <= ipbus+'1';
abusdp_inp1l_s <= ipbus when latchrw='0' else ipbusp1_s;
process(abusdp_inp1l_s,muxabus,csbusbiu_s,ipbusbiu_s,csbus,ipbus)
begin
case muxabus is
when "01" => abus_s <= (csbus&"0000") + ("0000"&ipbus); --abusdp_in;
when "10" => abus_s <= (csbus&"0000") + ("0000"&abusdp_inp1l_s); -- Add 1 if odd address and write word
when others => abus_s <= (csbusbiu_s&"0000") + ("0000"&ipbusbiu_s); -- default to BIU word address
end case;
end process;
-------------------------------------------------------------------------
-- Address/Databus Latch
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
abus <= RESET_VECTOR_C;
elsif rising_edge(clk) then
if latchrw='1' then -- Latch Address
abus <= abus_s;
end if;
end if;
end process;
-- Instance port mappings.
fsm : biufsm
PORT MAP (
clk => clk,
flush_coming => flush_coming,
flush_req => flush_req,
irq_req => irq_req_internal,
irq_type => irq_type,
opc_req => opc_req,
read_req => read_req,
reg1freed => reg1freed,
reg4free => reg4free,
regnbok => regnbok,
reset => reset,
w_biufsm_s => w_biufsm_s,
write_req => write_req,
addrplus4 => addrplus4,
biu_error => biu_error,
biu_status => biu_status,
irq_ack => irq_ack,
irq_clr => irq_clr,
latchabus => latchabus,
latchclr => latchclr,
latchm => latchm,
latcho => latcho_internal,
latchrw => latchrw,
ldposplus1 => ldposplus1,
muxabus => muxabus,
rdcode_s => rdcode_s,
rddata_s => rddata_s,
regplus1 => regplus1,
rw_ack => rw_ack,
wr_s => wr_s,
flush_ack => flush_ack_internal,
inta1 => inta1_internal
);
I4 : formatter
PORT MAP (
lutbus => lutbus,
mux_addr => mux_addr,
mux_data => mux_data,
mux_reg => mux_reg,
nbreq => nbreq
);
shift : regshiftmux
PORT MAP (
clk => clk,
dbus_in => dbus_in,
flush_req => flush_req,
latchm => latchm,
latcho => latcho_internal,
mux_addr => mux_addr,
mux_data => mux_data,
mux_reg => mux_reg,
nbreq => nbreq,
regplus1 => regplus1,
ldposplus1 => ldposplus1,
reset => reset,
irq => irq_ack,
inta1 => inta1_internal,
inta2_s => inta2_s,
irq_type => irq_type,
instr => instr,
halt_instr => halt_instr,
lutbus => lutbus,
reg1free => reg4free,
reg1freed => reg1freed,
regnbok => regnbok
);
flush_ack <= flush_ack_internal;
inta1 <= inta1_internal;
irq_req <= irq_req_internal;
latcho <= latcho_internal;
END struct;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_3_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_3_e-e.vhd,v 1.2 2005/07/15 16:20:01 wig Exp $
-- $Date: 2005/07/15 16:20:01 $
-- $Log: inst_3_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:20:01 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_3_e
--
entity inst_3_e is
-- Generics:
-- No Generated Generics for Entity inst_3_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_3_e
end inst_3_e;
--
-- End of Generated Entity inst_3_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
entity ent is
generic (gen1 : natural;
genb : boolean := false;
genv : std_logic_vector(7 downto 0) := "00001111";
gens : string);
port (d : out std_logic);
end ent;
architecture behav of ent is
begin
d <= '1' when gen1 = 5 and genb and (gens = "TRUE")
else '0';
end behav;
|
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant0.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant0 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END lpm_constant0;
ARCHITECTURE SYN OF lpm_constant0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(5 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 6,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=MYVA",
lpm_type => "LPM_CONSTANT",
lpm_width => 6
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "MYVA"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "6"
-- Retrieval info: PRIVATE: nBit NUMERIC "6"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "6"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=MYVA"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "6"
-- Retrieval info: USED_PORT: result 0 0 6 0 OUTPUT NODEFVAL "result[5..0]"
-- Retrieval info: CONNECT: result 0 0 6 0 @result 0 0 6 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-------------------------------------------------------------------------------
-- microblaze_0_bram_block_elaborate.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity microblaze_0_bram_block_elaborate is
generic (
C_MEMSIZE : integer;
C_PORT_DWIDTH : integer;
C_PORT_AWIDTH : integer;
C_NUM_WE : integer;
C_FAMILY : string
);
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
);
attribute keep_hierarchy : STRING;
attribute keep_hierarchy of microblaze_0_bram_block_elaborate : entity is "yes";
end microblaze_0_bram_block_elaborate;
architecture STRUCTURE of microblaze_0_bram_block_elaborate is
component RAMB16BWER is
generic (
INIT_FILE : string;
DATA_WIDTH_A : integer;
DATA_WIDTH_B : integer
);
port (
ADDRA : in std_logic_vector(13 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector(31 downto 0);
DIPA : in std_logic_vector(3 downto 0);
DOA : out std_logic_vector(31 downto 0);
DOPA : out std_logic_vector(3 downto 0);
ENA : in std_logic;
REGCEA : in std_logic;
RSTA : in std_logic;
WEA : in std_logic_vector(3 downto 0);
ADDRB : in std_logic_vector(13 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector(31 downto 0);
DIPB : in std_logic_vector(3 downto 0);
DOB : out std_logic_vector(31 downto 0);
DOPB : out std_logic_vector(3 downto 0);
ENB : in std_logic;
REGCEB : in std_logic;
RSTB : in std_logic;
WEB : in std_logic_vector(3 downto 0)
);
end component;
attribute BMM_INFO : STRING;
attribute BMM_INFO of ramb16bwer_0: label is " ";
attribute BMM_INFO of ramb16bwer_1: label is " ";
attribute BMM_INFO of ramb16bwer_2: label is " ";
attribute BMM_INFO of ramb16bwer_3: label is " ";
attribute BMM_INFO of ramb16bwer_4: label is " ";
attribute BMM_INFO of ramb16bwer_5: label is " ";
attribute BMM_INFO of ramb16bwer_6: label is " ";
attribute BMM_INFO of ramb16bwer_7: label is " ";
attribute BMM_INFO of ramb16bwer_8: label is " ";
attribute BMM_INFO of ramb16bwer_9: label is " ";
attribute BMM_INFO of ramb16bwer_10: label is " ";
attribute BMM_INFO of ramb16bwer_11: label is " ";
attribute BMM_INFO of ramb16bwer_12: label is " ";
attribute BMM_INFO of ramb16bwer_13: label is " ";
attribute BMM_INFO of ramb16bwer_14: label is " ";
attribute BMM_INFO of ramb16bwer_15: label is " ";
-- Internal signals
signal net_gnd0 : std_logic;
signal net_gnd4 : std_logic_vector(3 downto 0);
signal pgassign1 : std_logic_vector(0 to 0);
signal pgassign2 : std_logic_vector(0 to 29);
signal pgassign3 : std_logic_vector(13 downto 0);
signal pgassign4 : std_logic_vector(31 downto 0);
signal pgassign5 : std_logic_vector(31 downto 0);
signal pgassign6 : std_logic_vector(3 downto 0);
signal pgassign7 : std_logic_vector(13 downto 0);
signal pgassign8 : std_logic_vector(31 downto 0);
signal pgassign9 : std_logic_vector(31 downto 0);
signal pgassign10 : std_logic_vector(3 downto 0);
signal pgassign11 : std_logic_vector(13 downto 0);
signal pgassign12 : std_logic_vector(31 downto 0);
signal pgassign13 : std_logic_vector(31 downto 0);
signal pgassign14 : std_logic_vector(3 downto 0);
signal pgassign15 : std_logic_vector(13 downto 0);
signal pgassign16 : std_logic_vector(31 downto 0);
signal pgassign17 : std_logic_vector(31 downto 0);
signal pgassign18 : std_logic_vector(3 downto 0);
signal pgassign19 : std_logic_vector(13 downto 0);
signal pgassign20 : std_logic_vector(31 downto 0);
signal pgassign21 : std_logic_vector(31 downto 0);
signal pgassign22 : std_logic_vector(3 downto 0);
signal pgassign23 : std_logic_vector(13 downto 0);
signal pgassign24 : std_logic_vector(31 downto 0);
signal pgassign25 : std_logic_vector(31 downto 0);
signal pgassign26 : std_logic_vector(3 downto 0);
signal pgassign27 : std_logic_vector(13 downto 0);
signal pgassign28 : std_logic_vector(31 downto 0);
signal pgassign29 : std_logic_vector(31 downto 0);
signal pgassign30 : std_logic_vector(3 downto 0);
signal pgassign31 : std_logic_vector(13 downto 0);
signal pgassign32 : std_logic_vector(31 downto 0);
signal pgassign33 : std_logic_vector(31 downto 0);
signal pgassign34 : std_logic_vector(3 downto 0);
signal pgassign35 : std_logic_vector(13 downto 0);
signal pgassign36 : std_logic_vector(31 downto 0);
signal pgassign37 : std_logic_vector(31 downto 0);
signal pgassign38 : std_logic_vector(3 downto 0);
signal pgassign39 : std_logic_vector(13 downto 0);
signal pgassign40 : std_logic_vector(31 downto 0);
signal pgassign41 : std_logic_vector(31 downto 0);
signal pgassign42 : std_logic_vector(3 downto 0);
signal pgassign43 : std_logic_vector(13 downto 0);
signal pgassign44 : std_logic_vector(31 downto 0);
signal pgassign45 : std_logic_vector(31 downto 0);
signal pgassign46 : std_logic_vector(3 downto 0);
signal pgassign47 : std_logic_vector(13 downto 0);
signal pgassign48 : std_logic_vector(31 downto 0);
signal pgassign49 : std_logic_vector(31 downto 0);
signal pgassign50 : std_logic_vector(3 downto 0);
signal pgassign51 : std_logic_vector(13 downto 0);
signal pgassign52 : std_logic_vector(31 downto 0);
signal pgassign53 : std_logic_vector(31 downto 0);
signal pgassign54 : std_logic_vector(3 downto 0);
signal pgassign55 : std_logic_vector(13 downto 0);
signal pgassign56 : std_logic_vector(31 downto 0);
signal pgassign57 : std_logic_vector(31 downto 0);
signal pgassign58 : std_logic_vector(3 downto 0);
signal pgassign59 : std_logic_vector(13 downto 0);
signal pgassign60 : std_logic_vector(31 downto 0);
signal pgassign61 : std_logic_vector(31 downto 0);
signal pgassign62 : std_logic_vector(3 downto 0);
signal pgassign63 : std_logic_vector(13 downto 0);
signal pgassign64 : std_logic_vector(31 downto 0);
signal pgassign65 : std_logic_vector(31 downto 0);
signal pgassign66 : std_logic_vector(3 downto 0);
signal pgassign67 : std_logic_vector(13 downto 0);
signal pgassign68 : std_logic_vector(31 downto 0);
signal pgassign69 : std_logic_vector(31 downto 0);
signal pgassign70 : std_logic_vector(3 downto 0);
signal pgassign71 : std_logic_vector(13 downto 0);
signal pgassign72 : std_logic_vector(31 downto 0);
signal pgassign73 : std_logic_vector(31 downto 0);
signal pgassign74 : std_logic_vector(3 downto 0);
signal pgassign75 : std_logic_vector(13 downto 0);
signal pgassign76 : std_logic_vector(31 downto 0);
signal pgassign77 : std_logic_vector(31 downto 0);
signal pgassign78 : std_logic_vector(3 downto 0);
signal pgassign79 : std_logic_vector(13 downto 0);
signal pgassign80 : std_logic_vector(31 downto 0);
signal pgassign81 : std_logic_vector(31 downto 0);
signal pgassign82 : std_logic_vector(3 downto 0);
signal pgassign83 : std_logic_vector(13 downto 0);
signal pgassign84 : std_logic_vector(31 downto 0);
signal pgassign85 : std_logic_vector(31 downto 0);
signal pgassign86 : std_logic_vector(3 downto 0);
signal pgassign87 : std_logic_vector(13 downto 0);
signal pgassign88 : std_logic_vector(31 downto 0);
signal pgassign89 : std_logic_vector(31 downto 0);
signal pgassign90 : std_logic_vector(3 downto 0);
signal pgassign91 : std_logic_vector(13 downto 0);
signal pgassign92 : std_logic_vector(31 downto 0);
signal pgassign93 : std_logic_vector(31 downto 0);
signal pgassign94 : std_logic_vector(3 downto 0);
signal pgassign95 : std_logic_vector(13 downto 0);
signal pgassign96 : std_logic_vector(31 downto 0);
signal pgassign97 : std_logic_vector(31 downto 0);
signal pgassign98 : std_logic_vector(3 downto 0);
signal pgassign99 : std_logic_vector(13 downto 0);
signal pgassign100 : std_logic_vector(31 downto 0);
signal pgassign101 : std_logic_vector(31 downto 0);
signal pgassign102 : std_logic_vector(3 downto 0);
signal pgassign103 : std_logic_vector(13 downto 0);
signal pgassign104 : std_logic_vector(31 downto 0);
signal pgassign105 : std_logic_vector(31 downto 0);
signal pgassign106 : std_logic_vector(3 downto 0);
signal pgassign107 : std_logic_vector(13 downto 0);
signal pgassign108 : std_logic_vector(31 downto 0);
signal pgassign109 : std_logic_vector(31 downto 0);
signal pgassign110 : std_logic_vector(3 downto 0);
signal pgassign111 : std_logic_vector(13 downto 0);
signal pgassign112 : std_logic_vector(31 downto 0);
signal pgassign113 : std_logic_vector(31 downto 0);
signal pgassign114 : std_logic_vector(3 downto 0);
signal pgassign115 : std_logic_vector(13 downto 0);
signal pgassign116 : std_logic_vector(31 downto 0);
signal pgassign117 : std_logic_vector(31 downto 0);
signal pgassign118 : std_logic_vector(3 downto 0);
signal pgassign119 : std_logic_vector(13 downto 0);
signal pgassign120 : std_logic_vector(31 downto 0);
signal pgassign121 : std_logic_vector(31 downto 0);
signal pgassign122 : std_logic_vector(3 downto 0);
signal pgassign123 : std_logic_vector(13 downto 0);
signal pgassign124 : std_logic_vector(31 downto 0);
signal pgassign125 : std_logic_vector(31 downto 0);
signal pgassign126 : std_logic_vector(3 downto 0);
signal pgassign127 : std_logic_vector(13 downto 0);
signal pgassign128 : std_logic_vector(31 downto 0);
signal pgassign129 : std_logic_vector(31 downto 0);
signal pgassign130 : std_logic_vector(3 downto 0);
begin
-- Internal assignments
pgassign1(0 to 0) <= B"0";
pgassign2(0 to 29) <= B"000000000000000000000000000000";
pgassign3(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign3(0 downto 0) <= B"0";
pgassign4(31 downto 2) <= B"000000000000000000000000000000";
pgassign4(1 downto 0) <= BRAM_Dout_A(0 to 1);
BRAM_Din_A(0 to 1) <= pgassign5(1 downto 0);
pgassign6(3 downto 3) <= BRAM_WEN_A(0 to 0);
pgassign6(2 downto 2) <= BRAM_WEN_A(0 to 0);
pgassign6(1 downto 1) <= BRAM_WEN_A(0 to 0);
pgassign6(0 downto 0) <= BRAM_WEN_A(0 to 0);
pgassign7(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign7(0 downto 0) <= B"0";
pgassign8(31 downto 2) <= B"000000000000000000000000000000";
pgassign8(1 downto 0) <= BRAM_Dout_B(0 to 1);
BRAM_Din_B(0 to 1) <= pgassign9(1 downto 0);
pgassign10(3 downto 3) <= BRAM_WEN_B(0 to 0);
pgassign10(2 downto 2) <= BRAM_WEN_B(0 to 0);
pgassign10(1 downto 1) <= BRAM_WEN_B(0 to 0);
pgassign10(0 downto 0) <= BRAM_WEN_B(0 to 0);
pgassign11(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign11(0 downto 0) <= B"0";
pgassign12(31 downto 2) <= B"000000000000000000000000000000";
pgassign12(1 downto 0) <= BRAM_Dout_A(2 to 3);
BRAM_Din_A(2 to 3) <= pgassign13(1 downto 0);
pgassign14(3 downto 3) <= BRAM_WEN_A(0 to 0);
pgassign14(2 downto 2) <= BRAM_WEN_A(0 to 0);
pgassign14(1 downto 1) <= BRAM_WEN_A(0 to 0);
pgassign14(0 downto 0) <= BRAM_WEN_A(0 to 0);
pgassign15(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign15(0 downto 0) <= B"0";
pgassign16(31 downto 2) <= B"000000000000000000000000000000";
pgassign16(1 downto 0) <= BRAM_Dout_B(2 to 3);
BRAM_Din_B(2 to 3) <= pgassign17(1 downto 0);
pgassign18(3 downto 3) <= BRAM_WEN_B(0 to 0);
pgassign18(2 downto 2) <= BRAM_WEN_B(0 to 0);
pgassign18(1 downto 1) <= BRAM_WEN_B(0 to 0);
pgassign18(0 downto 0) <= BRAM_WEN_B(0 to 0);
pgassign19(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign19(0 downto 0) <= B"0";
pgassign20(31 downto 2) <= B"000000000000000000000000000000";
pgassign20(1 downto 0) <= BRAM_Dout_A(4 to 5);
BRAM_Din_A(4 to 5) <= pgassign21(1 downto 0);
pgassign22(3 downto 3) <= BRAM_WEN_A(0 to 0);
pgassign22(2 downto 2) <= BRAM_WEN_A(0 to 0);
pgassign22(1 downto 1) <= BRAM_WEN_A(0 to 0);
pgassign22(0 downto 0) <= BRAM_WEN_A(0 to 0);
pgassign23(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign23(0 downto 0) <= B"0";
pgassign24(31 downto 2) <= B"000000000000000000000000000000";
pgassign24(1 downto 0) <= BRAM_Dout_B(4 to 5);
BRAM_Din_B(4 to 5) <= pgassign25(1 downto 0);
pgassign26(3 downto 3) <= BRAM_WEN_B(0 to 0);
pgassign26(2 downto 2) <= BRAM_WEN_B(0 to 0);
pgassign26(1 downto 1) <= BRAM_WEN_B(0 to 0);
pgassign26(0 downto 0) <= BRAM_WEN_B(0 to 0);
pgassign27(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign27(0 downto 0) <= B"0";
pgassign28(31 downto 2) <= B"000000000000000000000000000000";
pgassign28(1 downto 0) <= BRAM_Dout_A(6 to 7);
BRAM_Din_A(6 to 7) <= pgassign29(1 downto 0);
pgassign30(3 downto 3) <= BRAM_WEN_A(0 to 0);
pgassign30(2 downto 2) <= BRAM_WEN_A(0 to 0);
pgassign30(1 downto 1) <= BRAM_WEN_A(0 to 0);
pgassign30(0 downto 0) <= BRAM_WEN_A(0 to 0);
pgassign31(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign31(0 downto 0) <= B"0";
pgassign32(31 downto 2) <= B"000000000000000000000000000000";
pgassign32(1 downto 0) <= BRAM_Dout_B(6 to 7);
BRAM_Din_B(6 to 7) <= pgassign33(1 downto 0);
pgassign34(3 downto 3) <= BRAM_WEN_B(0 to 0);
pgassign34(2 downto 2) <= BRAM_WEN_B(0 to 0);
pgassign34(1 downto 1) <= BRAM_WEN_B(0 to 0);
pgassign34(0 downto 0) <= BRAM_WEN_B(0 to 0);
pgassign35(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign35(0 downto 0) <= B"0";
pgassign36(31 downto 2) <= B"000000000000000000000000000000";
pgassign36(1 downto 0) <= BRAM_Dout_A(8 to 9);
BRAM_Din_A(8 to 9) <= pgassign37(1 downto 0);
pgassign38(3 downto 3) <= BRAM_WEN_A(1 to 1);
pgassign38(2 downto 2) <= BRAM_WEN_A(1 to 1);
pgassign38(1 downto 1) <= BRAM_WEN_A(1 to 1);
pgassign38(0 downto 0) <= BRAM_WEN_A(1 to 1);
pgassign39(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign39(0 downto 0) <= B"0";
pgassign40(31 downto 2) <= B"000000000000000000000000000000";
pgassign40(1 downto 0) <= BRAM_Dout_B(8 to 9);
BRAM_Din_B(8 to 9) <= pgassign41(1 downto 0);
pgassign42(3 downto 3) <= BRAM_WEN_B(1 to 1);
pgassign42(2 downto 2) <= BRAM_WEN_B(1 to 1);
pgassign42(1 downto 1) <= BRAM_WEN_B(1 to 1);
pgassign42(0 downto 0) <= BRAM_WEN_B(1 to 1);
pgassign43(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign43(0 downto 0) <= B"0";
pgassign44(31 downto 2) <= B"000000000000000000000000000000";
pgassign44(1 downto 0) <= BRAM_Dout_A(10 to 11);
BRAM_Din_A(10 to 11) <= pgassign45(1 downto 0);
pgassign46(3 downto 3) <= BRAM_WEN_A(1 to 1);
pgassign46(2 downto 2) <= BRAM_WEN_A(1 to 1);
pgassign46(1 downto 1) <= BRAM_WEN_A(1 to 1);
pgassign46(0 downto 0) <= BRAM_WEN_A(1 to 1);
pgassign47(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign47(0 downto 0) <= B"0";
pgassign48(31 downto 2) <= B"000000000000000000000000000000";
pgassign48(1 downto 0) <= BRAM_Dout_B(10 to 11);
BRAM_Din_B(10 to 11) <= pgassign49(1 downto 0);
pgassign50(3 downto 3) <= BRAM_WEN_B(1 to 1);
pgassign50(2 downto 2) <= BRAM_WEN_B(1 to 1);
pgassign50(1 downto 1) <= BRAM_WEN_B(1 to 1);
pgassign50(0 downto 0) <= BRAM_WEN_B(1 to 1);
pgassign51(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign51(0 downto 0) <= B"0";
pgassign52(31 downto 2) <= B"000000000000000000000000000000";
pgassign52(1 downto 0) <= BRAM_Dout_A(12 to 13);
BRAM_Din_A(12 to 13) <= pgassign53(1 downto 0);
pgassign54(3 downto 3) <= BRAM_WEN_A(1 to 1);
pgassign54(2 downto 2) <= BRAM_WEN_A(1 to 1);
pgassign54(1 downto 1) <= BRAM_WEN_A(1 to 1);
pgassign54(0 downto 0) <= BRAM_WEN_A(1 to 1);
pgassign55(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign55(0 downto 0) <= B"0";
pgassign56(31 downto 2) <= B"000000000000000000000000000000";
pgassign56(1 downto 0) <= BRAM_Dout_B(12 to 13);
BRAM_Din_B(12 to 13) <= pgassign57(1 downto 0);
pgassign58(3 downto 3) <= BRAM_WEN_B(1 to 1);
pgassign58(2 downto 2) <= BRAM_WEN_B(1 to 1);
pgassign58(1 downto 1) <= BRAM_WEN_B(1 to 1);
pgassign58(0 downto 0) <= BRAM_WEN_B(1 to 1);
pgassign59(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign59(0 downto 0) <= B"0";
pgassign60(31 downto 2) <= B"000000000000000000000000000000";
pgassign60(1 downto 0) <= BRAM_Dout_A(14 to 15);
BRAM_Din_A(14 to 15) <= pgassign61(1 downto 0);
pgassign62(3 downto 3) <= BRAM_WEN_A(1 to 1);
pgassign62(2 downto 2) <= BRAM_WEN_A(1 to 1);
pgassign62(1 downto 1) <= BRAM_WEN_A(1 to 1);
pgassign62(0 downto 0) <= BRAM_WEN_A(1 to 1);
pgassign63(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign63(0 downto 0) <= B"0";
pgassign64(31 downto 2) <= B"000000000000000000000000000000";
pgassign64(1 downto 0) <= BRAM_Dout_B(14 to 15);
BRAM_Din_B(14 to 15) <= pgassign65(1 downto 0);
pgassign66(3 downto 3) <= BRAM_WEN_B(1 to 1);
pgassign66(2 downto 2) <= BRAM_WEN_B(1 to 1);
pgassign66(1 downto 1) <= BRAM_WEN_B(1 to 1);
pgassign66(0 downto 0) <= BRAM_WEN_B(1 to 1);
pgassign67(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign67(0 downto 0) <= B"0";
pgassign68(31 downto 2) <= B"000000000000000000000000000000";
pgassign68(1 downto 0) <= BRAM_Dout_A(16 to 17);
BRAM_Din_A(16 to 17) <= pgassign69(1 downto 0);
pgassign70(3 downto 3) <= BRAM_WEN_A(2 to 2);
pgassign70(2 downto 2) <= BRAM_WEN_A(2 to 2);
pgassign70(1 downto 1) <= BRAM_WEN_A(2 to 2);
pgassign70(0 downto 0) <= BRAM_WEN_A(2 to 2);
pgassign71(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign71(0 downto 0) <= B"0";
pgassign72(31 downto 2) <= B"000000000000000000000000000000";
pgassign72(1 downto 0) <= BRAM_Dout_B(16 to 17);
BRAM_Din_B(16 to 17) <= pgassign73(1 downto 0);
pgassign74(3 downto 3) <= BRAM_WEN_B(2 to 2);
pgassign74(2 downto 2) <= BRAM_WEN_B(2 to 2);
pgassign74(1 downto 1) <= BRAM_WEN_B(2 to 2);
pgassign74(0 downto 0) <= BRAM_WEN_B(2 to 2);
pgassign75(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign75(0 downto 0) <= B"0";
pgassign76(31 downto 2) <= B"000000000000000000000000000000";
pgassign76(1 downto 0) <= BRAM_Dout_A(18 to 19);
BRAM_Din_A(18 to 19) <= pgassign77(1 downto 0);
pgassign78(3 downto 3) <= BRAM_WEN_A(2 to 2);
pgassign78(2 downto 2) <= BRAM_WEN_A(2 to 2);
pgassign78(1 downto 1) <= BRAM_WEN_A(2 to 2);
pgassign78(0 downto 0) <= BRAM_WEN_A(2 to 2);
pgassign79(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign79(0 downto 0) <= B"0";
pgassign80(31 downto 2) <= B"000000000000000000000000000000";
pgassign80(1 downto 0) <= BRAM_Dout_B(18 to 19);
BRAM_Din_B(18 to 19) <= pgassign81(1 downto 0);
pgassign82(3 downto 3) <= BRAM_WEN_B(2 to 2);
pgassign82(2 downto 2) <= BRAM_WEN_B(2 to 2);
pgassign82(1 downto 1) <= BRAM_WEN_B(2 to 2);
pgassign82(0 downto 0) <= BRAM_WEN_B(2 to 2);
pgassign83(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign83(0 downto 0) <= B"0";
pgassign84(31 downto 2) <= B"000000000000000000000000000000";
pgassign84(1 downto 0) <= BRAM_Dout_A(20 to 21);
BRAM_Din_A(20 to 21) <= pgassign85(1 downto 0);
pgassign86(3 downto 3) <= BRAM_WEN_A(2 to 2);
pgassign86(2 downto 2) <= BRAM_WEN_A(2 to 2);
pgassign86(1 downto 1) <= BRAM_WEN_A(2 to 2);
pgassign86(0 downto 0) <= BRAM_WEN_A(2 to 2);
pgassign87(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign87(0 downto 0) <= B"0";
pgassign88(31 downto 2) <= B"000000000000000000000000000000";
pgassign88(1 downto 0) <= BRAM_Dout_B(20 to 21);
BRAM_Din_B(20 to 21) <= pgassign89(1 downto 0);
pgassign90(3 downto 3) <= BRAM_WEN_B(2 to 2);
pgassign90(2 downto 2) <= BRAM_WEN_B(2 to 2);
pgassign90(1 downto 1) <= BRAM_WEN_B(2 to 2);
pgassign90(0 downto 0) <= BRAM_WEN_B(2 to 2);
pgassign91(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign91(0 downto 0) <= B"0";
pgassign92(31 downto 2) <= B"000000000000000000000000000000";
pgassign92(1 downto 0) <= BRAM_Dout_A(22 to 23);
BRAM_Din_A(22 to 23) <= pgassign93(1 downto 0);
pgassign94(3 downto 3) <= BRAM_WEN_A(2 to 2);
pgassign94(2 downto 2) <= BRAM_WEN_A(2 to 2);
pgassign94(1 downto 1) <= BRAM_WEN_A(2 to 2);
pgassign94(0 downto 0) <= BRAM_WEN_A(2 to 2);
pgassign95(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign95(0 downto 0) <= B"0";
pgassign96(31 downto 2) <= B"000000000000000000000000000000";
pgassign96(1 downto 0) <= BRAM_Dout_B(22 to 23);
BRAM_Din_B(22 to 23) <= pgassign97(1 downto 0);
pgassign98(3 downto 3) <= BRAM_WEN_B(2 to 2);
pgassign98(2 downto 2) <= BRAM_WEN_B(2 to 2);
pgassign98(1 downto 1) <= BRAM_WEN_B(2 to 2);
pgassign98(0 downto 0) <= BRAM_WEN_B(2 to 2);
pgassign99(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign99(0 downto 0) <= B"0";
pgassign100(31 downto 2) <= B"000000000000000000000000000000";
pgassign100(1 downto 0) <= BRAM_Dout_A(24 to 25);
BRAM_Din_A(24 to 25) <= pgassign101(1 downto 0);
pgassign102(3 downto 3) <= BRAM_WEN_A(3 to 3);
pgassign102(2 downto 2) <= BRAM_WEN_A(3 to 3);
pgassign102(1 downto 1) <= BRAM_WEN_A(3 to 3);
pgassign102(0 downto 0) <= BRAM_WEN_A(3 to 3);
pgassign103(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign103(0 downto 0) <= B"0";
pgassign104(31 downto 2) <= B"000000000000000000000000000000";
pgassign104(1 downto 0) <= BRAM_Dout_B(24 to 25);
BRAM_Din_B(24 to 25) <= pgassign105(1 downto 0);
pgassign106(3 downto 3) <= BRAM_WEN_B(3 to 3);
pgassign106(2 downto 2) <= BRAM_WEN_B(3 to 3);
pgassign106(1 downto 1) <= BRAM_WEN_B(3 to 3);
pgassign106(0 downto 0) <= BRAM_WEN_B(3 to 3);
pgassign107(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign107(0 downto 0) <= B"0";
pgassign108(31 downto 2) <= B"000000000000000000000000000000";
pgassign108(1 downto 0) <= BRAM_Dout_A(26 to 27);
BRAM_Din_A(26 to 27) <= pgassign109(1 downto 0);
pgassign110(3 downto 3) <= BRAM_WEN_A(3 to 3);
pgassign110(2 downto 2) <= BRAM_WEN_A(3 to 3);
pgassign110(1 downto 1) <= BRAM_WEN_A(3 to 3);
pgassign110(0 downto 0) <= BRAM_WEN_A(3 to 3);
pgassign111(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign111(0 downto 0) <= B"0";
pgassign112(31 downto 2) <= B"000000000000000000000000000000";
pgassign112(1 downto 0) <= BRAM_Dout_B(26 to 27);
BRAM_Din_B(26 to 27) <= pgassign113(1 downto 0);
pgassign114(3 downto 3) <= BRAM_WEN_B(3 to 3);
pgassign114(2 downto 2) <= BRAM_WEN_B(3 to 3);
pgassign114(1 downto 1) <= BRAM_WEN_B(3 to 3);
pgassign114(0 downto 0) <= BRAM_WEN_B(3 to 3);
pgassign115(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign115(0 downto 0) <= B"0";
pgassign116(31 downto 2) <= B"000000000000000000000000000000";
pgassign116(1 downto 0) <= BRAM_Dout_A(28 to 29);
BRAM_Din_A(28 to 29) <= pgassign117(1 downto 0);
pgassign118(3 downto 3) <= BRAM_WEN_A(3 to 3);
pgassign118(2 downto 2) <= BRAM_WEN_A(3 to 3);
pgassign118(1 downto 1) <= BRAM_WEN_A(3 to 3);
pgassign118(0 downto 0) <= BRAM_WEN_A(3 to 3);
pgassign119(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign119(0 downto 0) <= B"0";
pgassign120(31 downto 2) <= B"000000000000000000000000000000";
pgassign120(1 downto 0) <= BRAM_Dout_B(28 to 29);
BRAM_Din_B(28 to 29) <= pgassign121(1 downto 0);
pgassign122(3 downto 3) <= BRAM_WEN_B(3 to 3);
pgassign122(2 downto 2) <= BRAM_WEN_B(3 to 3);
pgassign122(1 downto 1) <= BRAM_WEN_B(3 to 3);
pgassign122(0 downto 0) <= BRAM_WEN_B(3 to 3);
pgassign123(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign123(0 downto 0) <= B"0";
pgassign124(31 downto 2) <= B"000000000000000000000000000000";
pgassign124(1 downto 0) <= BRAM_Dout_A(30 to 31);
BRAM_Din_A(30 to 31) <= pgassign125(1 downto 0);
pgassign126(3 downto 3) <= BRAM_WEN_A(3 to 3);
pgassign126(2 downto 2) <= BRAM_WEN_A(3 to 3);
pgassign126(1 downto 1) <= BRAM_WEN_A(3 to 3);
pgassign126(0 downto 0) <= BRAM_WEN_A(3 to 3);
pgassign127(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign127(0 downto 0) <= B"0";
pgassign128(31 downto 2) <= B"000000000000000000000000000000";
pgassign128(1 downto 0) <= BRAM_Dout_B(30 to 31);
BRAM_Din_B(30 to 31) <= pgassign129(1 downto 0);
pgassign130(3 downto 3) <= BRAM_WEN_B(3 to 3);
pgassign130(2 downto 2) <= BRAM_WEN_B(3 to 3);
pgassign130(1 downto 1) <= BRAM_WEN_B(3 to 3);
pgassign130(0 downto 0) <= BRAM_WEN_B(3 to 3);
net_gnd0 <= '0';
net_gnd4(3 downto 0) <= B"0000";
ramb16bwer_0 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_0.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign3,
CLKA => BRAM_Clk_A,
DIA => pgassign4,
DIPA => net_gnd4,
DOA => pgassign5,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign6,
ADDRB => pgassign7,
CLKB => BRAM_Clk_B,
DIB => pgassign8,
DIPB => net_gnd4,
DOB => pgassign9,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign10
);
ramb16bwer_1 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_1.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign11,
CLKA => BRAM_Clk_A,
DIA => pgassign12,
DIPA => net_gnd4,
DOA => pgassign13,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign14,
ADDRB => pgassign15,
CLKB => BRAM_Clk_B,
DIB => pgassign16,
DIPB => net_gnd4,
DOB => pgassign17,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign18
);
ramb16bwer_2 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_2.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign19,
CLKA => BRAM_Clk_A,
DIA => pgassign20,
DIPA => net_gnd4,
DOA => pgassign21,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign22,
ADDRB => pgassign23,
CLKB => BRAM_Clk_B,
DIB => pgassign24,
DIPB => net_gnd4,
DOB => pgassign25,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign26
);
ramb16bwer_3 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_3.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign27,
CLKA => BRAM_Clk_A,
DIA => pgassign28,
DIPA => net_gnd4,
DOA => pgassign29,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign30,
ADDRB => pgassign31,
CLKB => BRAM_Clk_B,
DIB => pgassign32,
DIPB => net_gnd4,
DOB => pgassign33,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign34
);
ramb16bwer_4 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_4.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign35,
CLKA => BRAM_Clk_A,
DIA => pgassign36,
DIPA => net_gnd4,
DOA => pgassign37,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign38,
ADDRB => pgassign39,
CLKB => BRAM_Clk_B,
DIB => pgassign40,
DIPB => net_gnd4,
DOB => pgassign41,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign42
);
ramb16bwer_5 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_5.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign43,
CLKA => BRAM_Clk_A,
DIA => pgassign44,
DIPA => net_gnd4,
DOA => pgassign45,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign46,
ADDRB => pgassign47,
CLKB => BRAM_Clk_B,
DIB => pgassign48,
DIPB => net_gnd4,
DOB => pgassign49,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign50
);
ramb16bwer_6 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_6.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign51,
CLKA => BRAM_Clk_A,
DIA => pgassign52,
DIPA => net_gnd4,
DOA => pgassign53,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign54,
ADDRB => pgassign55,
CLKB => BRAM_Clk_B,
DIB => pgassign56,
DIPB => net_gnd4,
DOB => pgassign57,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign58
);
ramb16bwer_7 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_7.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign59,
CLKA => BRAM_Clk_A,
DIA => pgassign60,
DIPA => net_gnd4,
DOA => pgassign61,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign62,
ADDRB => pgassign63,
CLKB => BRAM_Clk_B,
DIB => pgassign64,
DIPB => net_gnd4,
DOB => pgassign65,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign66
);
ramb16bwer_8 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_8.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign67,
CLKA => BRAM_Clk_A,
DIA => pgassign68,
DIPA => net_gnd4,
DOA => pgassign69,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign70,
ADDRB => pgassign71,
CLKB => BRAM_Clk_B,
DIB => pgassign72,
DIPB => net_gnd4,
DOB => pgassign73,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign74
);
ramb16bwer_9 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_9.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign75,
CLKA => BRAM_Clk_A,
DIA => pgassign76,
DIPA => net_gnd4,
DOA => pgassign77,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign78,
ADDRB => pgassign79,
CLKB => BRAM_Clk_B,
DIB => pgassign80,
DIPB => net_gnd4,
DOB => pgassign81,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign82
);
ramb16bwer_10 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_10.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign83,
CLKA => BRAM_Clk_A,
DIA => pgassign84,
DIPA => net_gnd4,
DOA => pgassign85,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign86,
ADDRB => pgassign87,
CLKB => BRAM_Clk_B,
DIB => pgassign88,
DIPB => net_gnd4,
DOB => pgassign89,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign90
);
ramb16bwer_11 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_11.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign91,
CLKA => BRAM_Clk_A,
DIA => pgassign92,
DIPA => net_gnd4,
DOA => pgassign93,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign94,
ADDRB => pgassign95,
CLKB => BRAM_Clk_B,
DIB => pgassign96,
DIPB => net_gnd4,
DOB => pgassign97,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign98
);
ramb16bwer_12 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_12.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign99,
CLKA => BRAM_Clk_A,
DIA => pgassign100,
DIPA => net_gnd4,
DOA => pgassign101,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign102,
ADDRB => pgassign103,
CLKB => BRAM_Clk_B,
DIB => pgassign104,
DIPB => net_gnd4,
DOB => pgassign105,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign106
);
ramb16bwer_13 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_13.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign107,
CLKA => BRAM_Clk_A,
DIA => pgassign108,
DIPA => net_gnd4,
DOA => pgassign109,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign110,
ADDRB => pgassign111,
CLKB => BRAM_Clk_B,
DIB => pgassign112,
DIPB => net_gnd4,
DOB => pgassign113,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign114
);
ramb16bwer_14 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_14.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign115,
CLKA => BRAM_Clk_A,
DIA => pgassign116,
DIPA => net_gnd4,
DOA => pgassign117,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign118,
ADDRB => pgassign119,
CLKB => BRAM_Clk_B,
DIB => pgassign120,
DIPB => net_gnd4,
DOB => pgassign121,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign122
);
ramb16bwer_15 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_15.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign123,
CLKA => BRAM_Clk_A,
DIA => pgassign124,
DIPA => net_gnd4,
DOA => pgassign125,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign126,
ADDRB => pgassign127,
CLKB => BRAM_Clk_B,
DIB => pgassign128,
DIPB => net_gnd4,
DOB => pgassign129,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign130
);
end architecture STRUCTURE;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Oct 17 02:50:12 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top RAT_util_vector_logic_0_0 -prefix
-- RAT_util_vector_logic_0_0_ RAT_util_vector_logic_0_0_stub.vhdl
-- Design : RAT_util_vector_logic_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RAT_util_vector_logic_0_0 is
Port (
Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
Res : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end RAT_util_vector_logic_0_0;
architecture stub of RAT_util_vector_logic_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "Op1[0:0],Op2[0:0],Res[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "util_vector_logic,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Oct 17 02:50:12 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top RAT_util_vector_logic_0_0 -prefix
-- RAT_util_vector_logic_0_0_ RAT_util_vector_logic_0_0_stub.vhdl
-- Design : RAT_util_vector_logic_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RAT_util_vector_logic_0_0 is
Port (
Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
Res : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end RAT_util_vector_logic_0_0;
architecture stub of RAT_util_vector_logic_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "Op1[0:0],Op2[0:0],Res[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "util_vector_logic,Vivado 2016.4";
begin
end;
|
-------------- Library statements -------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity declaration half_adder--
entity half_adder is
port (a, b : in std_logic;
sumD, carryD, sumB, carryB, sumS, carryS : out std_logic
);
end half_adder;
-------------- Library statements and_2 ------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity declaration and_2--
entity and_2 is
port(a, b : in std_logic;
carryS : out std_logic);
end and_2;
-- architecture declaration and_2--
architecture andX of and_2 is
begin
carryS <= a and b;
end andX;
------------- Library statements xor_2 -------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity declaration xor_2--
entity xor_2 is
port(a, b : in std_logic;
sum : out std_logic);
end xor_2;
-- architecture xorX --
architecture xorX of xor_2 is
begin
sum <= a xor b;
end xorX;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc28.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p11n01i00028ent IS
END c04s02b00x00p11n01i00028ent;
ARCHITECTURE c04s02b00x00p11n01i00028arch OF c04s02b00x00p11n01i00028ent IS
type MVL is ('0', '1', 'Z') ;
type MVL_VEC is array (positive range <>) of MVL;
function tristate (X:MVL_VEC) return MVL is
begin
return '1';
end tristate ;
type T1 is access MVL ;
subtype ST1 is tristate T1; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s02b00x00p11n01i00028- Subtype indication denoting an access type can not contain a resolution function."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p11n01i00028arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc28.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p11n01i00028ent IS
END c04s02b00x00p11n01i00028ent;
ARCHITECTURE c04s02b00x00p11n01i00028arch OF c04s02b00x00p11n01i00028ent IS
type MVL is ('0', '1', 'Z') ;
type MVL_VEC is array (positive range <>) of MVL;
function tristate (X:MVL_VEC) return MVL is
begin
return '1';
end tristate ;
type T1 is access MVL ;
subtype ST1 is tristate T1; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s02b00x00p11n01i00028- Subtype indication denoting an access type can not contain a resolution function."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p11n01i00028arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc28.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p11n01i00028ent IS
END c04s02b00x00p11n01i00028ent;
ARCHITECTURE c04s02b00x00p11n01i00028arch OF c04s02b00x00p11n01i00028ent IS
type MVL is ('0', '1', 'Z') ;
type MVL_VEC is array (positive range <>) of MVL;
function tristate (X:MVL_VEC) return MVL is
begin
return '1';
end tristate ;
type T1 is access MVL ;
subtype ST1 is tristate T1; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s02b00x00p11n01i00028- Subtype indication denoting an access type can not contain a resolution function."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p11n01i00028arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: rgmii
-- File: rgmii.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler
-- Description: GMII to RGMII interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.net.all;
use gaisler.misc.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library eth;
use eth.grethpkg.all;
entity rgmii is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
tech : integer := 0;
gmii : integer := 0;
debugmem : integer := 0;
abits : integer := 8;
no_clk_mux : integer := 0;
pirq : integer := 0;
use90degtxclk : integer := 0
);
port (
rstn : in std_ulogic;
gmiii : out eth_in_type;
gmiio : in eth_out_type;
rgmiii : in eth_in_type;
rgmiio : out eth_out_type;
-- APB Status bus
apb_clk : in std_logic;
apb_rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end ;
architecture rtl of rgmii is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_RGMII, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type rgmiiregs is record
clk25_wrap : unsigned(5 downto 0);
clk25_first_edge : unsigned(5 downto 0);
clk25_second_edge : unsigned(5 downto 0);
clk2_5_wrap : unsigned(5 downto 0);
clk2_5_first_edge : unsigned(5 downto 0);
clk2_5_second_edge : unsigned(5 downto 0);
irq : std_logic_vector(15 downto 0); -- interrupt
mask : std_logic_vector(15 downto 0); -- interrupt enable
clkedge : std_logic_vector(23 downto 0);
rxctrl_q1_delay : std_logic_vector(1 downto 0);
rxctrl_q2_delay : std_logic_vector(1 downto 0);
rxctrl_q1_sel : std_logic;
end record;
-- Global signal
signal vcc, gnd : std_ulogic;
signal tx_en, tx_ctl : std_ulogic;
signal txd : std_logic_vector(7 downto 0);
signal rxd, rxd_pre, rxd_int, rxd_int0, rxd_int1, rxd_int2,rxd_q1,rxd_q2 : std_logic_vector(7 downto 0);
signal rx_clk, nrx_clk : std_ulogic;
signal rx_dv, rx_dv_pre, rx_dv_int, rx_dv0 , rx_ctl, rx_ctl_pre, rx_ctl_int, rx_ctl0, rx_error : std_logic;
signal rx_dv_int0, rx_dv_int1, rx_dv_int2 : std_logic;
signal rx_ctl_int0, rx_ctl_int1, rx_ctl_int2 : std_logic;
signal clk25i, clk25ni, clk2_5i, clk2_5ni : std_ulogic;
signal txp, txn, tx_clk_ddr, tx_clk, tx_clki, ntx_clk : std_ulogic;
signal cnt2_5, cnt25 : unsigned(5 downto 0);
signal rsttxclkn,rsttxclk : std_logic;
-- RGMII Inband status signals
signal inbandopt,inbandreq : std_logic;
signal link_status : std_logic;
signal clock_speed : std_logic_vector(1 downto 0);
signal duplex_status : std_logic;
signal false_carrier_ind : std_logic;
signal carrier_ext : std_logic;
signal carrier_ext_error : std_logic;
signal carrier_sense : std_logic;
-- Extra registers to ease IOB placement
signal status_vector_apb : std_logic_vector(15 downto 0);
signal status_vector_apb1 : std_logic_vector(15 downto 0);
signal status_vector_apb2 : std_logic_vector(15 downto 0);
-- APB and RGMII control register
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
-- notech default settings
constant RES : rgmiiregs :=
( clk25_wrap => to_unsigned(4,6), clk25_first_edge => to_unsigned(1,6), clk25_second_edge => to_unsigned(2,6),
clk2_5_wrap => to_unsigned(49,6), clk2_5_first_edge => to_unsigned(23,6), clk2_5_second_edge => to_unsigned(24,6),
irq => (others => '0'), mask => (others => '0'), clkedge => "000000100000101100000111",
rxctrl_q1_delay => (others => '0'), rxctrl_q2_delay => (others => '0'), rxctrl_q1_sel => '0');
-- Kintex7 settings for KC705 Dev Board
constant RES_kintex7 : rgmiiregs :=
( clk25_wrap => to_unsigned(4,6), clk25_first_edge => to_unsigned(1,6), clk25_second_edge => to_unsigned(2,6),
clk2_5_wrap => to_unsigned(49,6), clk2_5_first_edge => to_unsigned(23,6), clk2_5_second_edge => to_unsigned(24,6),
irq => (others => '0'), mask => (others => '0'), clkedge => "000000100000101100000111",
rxctrl_q1_delay => (others => '0'), rxctrl_q2_delay => (others => '0'), rxctrl_q1_sel => '1');
-- Spartan6 settings for GR-XC6 Dev Board
constant RES_spartan6 : rgmiiregs :=
( clk25_wrap => to_unsigned(4,6), clk25_first_edge => to_unsigned(1,6), clk25_second_edge => to_unsigned(2,6),
clk2_5_wrap => to_unsigned(49,6), clk2_5_first_edge => to_unsigned(23,6), clk2_5_second_edge => to_unsigned(24,6),
irq => (others => '0'), mask => (others => '0'), clkedge => "000000100011100000111000",
rxctrl_q1_delay => (others => '0'), rxctrl_q2_delay => "01", rxctrl_q1_sel => '1');
signal r, rin : rgmiiregs;
signal clk_tx_90_n : std_logic;
signal sync_gbit : std_logic;
signal sync_speed : std_logic;
signal cnt2_5_en, cnt25_en : std_logic;
signal clkedge_sync : std_logic_vector(23 downto 0);
signal sync_rxctrl_q1_delay : std_logic_vector(1 downto 0);
signal sync_rxctrl_q2_delay : std_logic_vector(1 downto 0);
signal sync_rxctrl_q1_sel : std_logic;
signal cnt_en : std_logic;
signal clk10_100 : std_logic;
-- debug signal
signal WMemRgmiioData : std_logic_vector(15 downto 0);
signal RMemRgmiioData : std_logic_vector(15 downto 0);
signal RMemRgmiioAddr : std_logic_vector(9 downto 0);
signal WMemRgmiioAddr : std_logic_vector(9 downto 0);
signal WMemRgmiioWrEn : std_logic;
signal WMemRgmiiiData : std_logic_vector(15 downto 0);
signal RMemRgmiiiData : std_logic_vector(15 downto 0);
signal RMemRgmiiiAddr : std_logic_vector(9 downto 0);
signal WMemRgmiiiAddr : std_logic_vector(9 downto 0);
signal WMemRgmiiiWrEn : std_logic;
signal RMemRgmiiiRead : std_logic;
signal RMemRgmiioRead : std_logic;
begin -- rtl
vcc <= '1'; gnd <= '0';
---------------------------------------------------------------------------------------
-- MDIO path
---------------------------------------------------------------------------------------
gmiii.mdint <= rgmiii.mdint;
gmiii.mdio_i <= rgmiii.mdio_i;
rgmiio.mdio_o <= gmiio.mdio_o;
rgmiio.mdio_oe <= gmiio.mdio_oe;
rgmiio.mdc <= gmiio.mdc;
---------------------------------------------------------------------------------------
-- TX path
---------------------------------------------------------------------------------------
useclkmux0 : if no_clk_mux = 0 generate
process (apb_clk)
begin -- process
if rising_edge(apb_clk) then
clk25i <= not clk25i;
if cnt2_5 = "001001" then cnt2_5 <= "000000"; clk2_5i <= not clk2_5i;
else cnt2_5 <= cnt2_5 + 1; end if;
if apb_rstn = '0' then clk25i <= '0'; clk2_5i <= '0'; cnt2_5 <= "000000"; end if;
end if;
end process;
notecclkmux : if (has_clkmux(tech) = 0) generate
tx_clki <= rgmiii.gtx_clk when ((gmii = 1) and (gmiio.gbit = '1')) else
clk25i when gmiio.speed = '1' else clk2_5i;
end generate;
tecclkmux : if (has_clkmux(tech) = 1) generate
-- Select 2.5 or 25 Mhz clockL
clkmux10_100 : clkmux generic map (tech => tech) port map (clk2_5i,clk25i,gmiio.speed,clk10_100);
clkmux1000 : clkmux generic map (tech => tech) port map (clk10_100,rgmiii.gtx_clk,gmiio.gbit,tx_clki);
end generate;
clkbuf0: techbuf generic map (buftype => 2, tech => tech)
port map (i => tx_clki, o => tx_clk);
end generate;
noclkmux0 : if no_clk_mux = 1 generate
-- Generate transmit clocks.
tx_clk <= rgmiii.gtx_clk;
process (tx_clk)
begin -- process
if rising_edge(tx_clk) then
if cnt25 >= r.clk25_wrap then
cnt25 <= to_unsigned(0,cnt25'length);
cnt25_en <= '1';
else
cnt25_en <= '0';
cnt25 <= cnt25 + 1;
end if;
if (cnt25 >= r.clk25_wrap) then
clk25ni <= clkedge_sync(0);
clk25i <= clkedge_sync(1);
elsif (cnt25 = r.clk25_first_edge) then
clk25ni <= clkedge_sync(2);
clk25i <= clkedge_sync(3);
elsif (cnt25 = r.clk25_second_edge) then
clk25ni <= clkedge_sync(4);
clk25i <= clkedge_sync(5);
end if;
if cnt2_5 >= r.clk2_5_wrap then
cnt2_5 <= to_unsigned(0,cnt2_5'length);
cnt2_5_en <= '1';
else
cnt2_5 <= cnt2_5 + 1;
cnt2_5_en <= '0';
end if;
if (cnt2_5 >= r.clk2_5_wrap) then
clk2_5ni <= clkedge_sync(8);
clk2_5i <= clkedge_sync(9);
elsif (cnt25 = r.clk2_5_first_edge) then
clk2_5ni <= clkedge_sync(10);
clk2_5i <= clkedge_sync(11);
elsif (cnt2_5 = r.clk2_5_second_edge) then
clk2_5ni <= clkedge_sync(12);
clk2_5i <= clkedge_sync(13);
end if;
if rsttxclkn = '0' then
cnt2_5_en <= '0'; cnt25_en <= '0'; clk25i <= '0'; clk25ni <= '0';
clk2_5i <= '0'; clk2_5ni <= '0'; cnt2_5 <= to_unsigned(0,cnt2_5'length);
cnt25 <= to_unsigned(0,cnt25'length);
end if;
end if;
end process;
end generate;
ntx_clk <= not tx_clk;
gmiii.gtx_clk <= tx_clk;
gmiii.tx_clk <= tx_clk;
noclkmux1 : if no_clk_mux = 1 generate
cnt_en <= '1' when ((gmii = 1) and (gmiio.gbit = '1')) else
cnt25_en when gmiio.speed = '1' else cnt2_5_en;
end generate;
useclkmux1 : if no_clk_mux = 0 generate
cnt_en <= '1';
end generate;
gmiii.tx_dv <= cnt_en when gmiio.tx_en = '1' else '1';
-- Generate RGMII control signal and check data rate
process (tx_clk)
begin -- process
-- CDC (Only 1 CDC register is used since the signals are semi-static)
sync_gbit <= gmiio.gbit;
sync_speed <= gmiio.speed;
clkedge_sync <= r.clkedge;
if rising_edge(tx_clk) then
if (gmii = 1) and (sync_gbit = '1') then
txd(7 downto 0) <= gmiio.txd(7 downto 0);
else
txd(3 downto 0) <= gmiio.txd(3 downto 0);
txd(7 downto 4) <= gmiio.txd(3 downto 0);
end if;
tx_en <= gmiio.tx_en;
tx_ctl <= gmiio.tx_en xor gmiio.tx_er;
end if;
if (gmii = 1) and (sync_gbit = '1') then
txp <= clkedge_sync(17);
txn <= clkedge_sync(16);
else
if sync_speed = '1' then
txp <= clk25ni;
txn <= clk25i;
else
txp <= clk2_5ni;
txn <= clk2_5i;
end if;
end if;
end process;
clk_tx_rst : rstgen
generic map(syncin => 1, syncrst => 1)
port map(rstn, tx_clk, vcc, rsttxclkn, open);
rsttxclk <= not rsttxclkn;
-- DDR outputs
rgmii_txd : for i in 0 to 3 generate
ddr_oreg0 : ddr_oreg generic map (tech, arch => 1)
port map (q => rgmiio.txd(i), c1 => tx_clk, c2 => ntx_clk, ce => vcc,
d1 => txd(i), d2 => txd(i+4), r => gnd, s => gnd);
end generate;
rgmii_tx_ctl : ddr_oreg generic map (tech, arch => 1)
port map (q => rgmiio.tx_en, c1 => tx_clk, c2 => ntx_clk, ce => vcc,
d1 => tx_en, d2 => tx_ctl, r => gnd, s => gnd);
no_clk_mux1 : if no_clk_mux = 1 generate
use90degtxclk1 : if use90degtxclk = 1 generate
clk_tx_90_n <= not rgmiii.tx_clk_90;
rgmii_tx_clk : ddr_oreg generic map (tech, arch => 1)
port map (q => tx_clk_ddr, c1 => rgmiii.tx_clk_90, c2 => clk_tx_90_n, ce => vcc,
d1 => txp, d2 => txn, r => gnd, s => gnd);
end generate;
use90degtxclk0 : if use90degtxclk = 0 generate
rgmii_tx_clk : ddr_oreg generic map (tech, arch => 1)
port map (q => tx_clk_ddr, c1 => tx_clk, c2 => ntx_clk, ce => vcc,
d1 => txp, d2 => txn, r => gnd, s => gnd);
end generate;
end generate;
no_clk_mux0 : if no_clk_mux = 0 generate
rgmii_tx_clk : ddr_oreg generic map (tech, arch => 1)
port map (q => tx_clk_ddr, c1 => tx_clk, c2 => ntx_clk, ce => vcc,
d1 => '1', d2 => '0', r => gnd, s => gnd);
end generate;
rgmiio.tx_er <= '0';
rgmiio.tx_clk <= tx_clk_ddr;
rgmiio.reset <= rstn;
rgmiio.gbit <= gmiio.gbit;
rgmiio.speed <= gmiio.speed when (gmii = 1) else '0';
-- Not used in RGMII mode
rgmiio.txd(7 downto 4) <= (others => '0');
---------------------------------------------------------------------------------------
-- RX path
---------------------------------------------------------------------------------------
-- CDC (RX Control signal)
process (rx_clk)
begin
if rising_edge(rx_clk) then
sync_rxctrl_q1_delay <= r.rxctrl_q1_delay;
sync_rxctrl_q2_delay <= r.rxctrl_q2_delay;
sync_rxctrl_q1_sel <= r.rxctrl_q1_sel;
end if;
end process;
-- Rx Clocks
rx_clk <= rgmiii.rx_clk;
nrx_clk <= not rgmiii.rx_clk;
-- DDR inputs
rgmii_rxd : for i in 0 to 3 generate
ddr_ireg0 : ddr_ireg generic map (tech, arch => 1)
port map (q1 => rxd_pre(i), q2 => rxd_pre(i+4), c1 => rx_clk, c2 => nrx_clk,
ce => vcc, d => rgmiii.rxd(i), r => gnd, s => gnd);
process (rx_clk)
begin
if rising_edge(rx_clk) then
rxd_int <= rxd_pre;
rxd_int0(i) <= rxd_int(i);
rxd_int0(i+4) <= rxd_int(i+4);
rxd_int1(i) <= rxd_int0(i);
rxd_int1(i+4) <= rxd_int0(i+4);
rxd_int2(i) <= rxd_int1(i);
rxd_int2(i+4) <= rxd_int1(i+4);
end if;
end process;
end generate;
rgmii_rxd0 : for i in 0 to 3 generate
process (rx_clk)
begin
if (sync_rxctrl_q1_delay = "00") then
rxd_q1(i) <= rxd_int(i);
elsif (sync_rxctrl_q1_delay = "01") then
rxd_q1(i) <= rxd_int0(i);
elsif (sync_rxctrl_q1_delay = "10") then
rxd_q1(i) <= rxd_int1(i);
else
rxd_q1(i) <= rxd_int2(i);
end if;
end process;
end generate;
rgmii_rxd1 : for i in 4 to 7 generate
process (rx_clk)
begin
if (sync_rxctrl_q2_delay = "00") then
rxd_q2(i) <= rxd_int(i);
elsif (sync_rxctrl_q2_delay = "01") then
rxd_q2(i) <= rxd_int0(i);
elsif (sync_rxctrl_q2_delay = "10") then
rxd_q2(i) <= rxd_int1(i);
else
rxd_q2(i) <= rxd_int2(i);
end if;
end process;
end generate;
rxd(3 downto 0) <= rxd_q1(3 downto 0) when (sync_rxctrl_q1_sel = '0') else rxd_q2(7 downto 4);
rxd(7 downto 4) <= rxd_q2(7 downto 4) when (sync_rxctrl_q1_sel = '0') else rxd_q1(3 downto 0);
ddr_dv0 : ddr_ireg generic map (tech, arch => 1)
port map (q1 => rx_dv_pre, q2 => rx_ctl_pre, c1 => rx_clk, c2 => nrx_clk,
ce => vcc, d => rgmiii.rx_dv, r => gnd, s => gnd);
process (rx_clk)
begin
if rising_edge(rx_clk) then
rx_ctl_int <= rx_ctl_pre;
rx_dv_int <= rx_dv_pre;
rx_ctl_int0 <= rx_ctl_int;
rx_ctl_int1 <= rx_ctl_int0;
rx_ctl_int2 <= rx_ctl_int1;
rx_dv_int0 <= rx_dv_int;
rx_dv_int1 <= rx_dv_int1;
rx_dv_int2 <= rx_dv_int2;
end if;
end process;
process (rx_clk)
begin
if (sync_rxctrl_q1_delay = "00") then
rx_dv0 <= rx_dv_int;
elsif (sync_rxctrl_q1_delay = "01") then
rx_dv0 <= rx_dv_int0;
elsif (sync_rxctrl_q1_delay = "10") then
rx_dv0 <= rx_dv_int1;
else
rx_dv0 <= rx_dv_int2;
end if;
if (sync_rxctrl_q2_delay = "00") then
rx_ctl0 <= rx_ctl_int;
elsif (sync_rxctrl_q2_delay = "01") then
rx_ctl0 <= rx_ctl_int0;
elsif (sync_rxctrl_q2_delay = "10") then
rx_ctl0 <= rx_ctl_int1;
else
rx_ctl0 <= rx_ctl_int2;
end if;
end process;
rx_dv <= rx_dv0 when (sync_rxctrl_q1_sel = '0') else rx_ctl0;
rx_ctl <= rx_ctl0 when (sync_rxctrl_q1_sel = '0') else rx_dv0;
-- Decode GMII error signal
rx_error <= rx_dv xor rx_ctl;
-- Enable inband status registers during Interframe Gap
inbandopt <= not ( rx_dv or rx_error );
inbandreq <= rx_error and not rx_dv;
-- Sample RGMII inband information
process (rx_clk)
begin
if rising_edge(rx_clk) then
if (inbandopt = '1') then
link_status <= rxd(0);
clock_speed <= rxd(2 downto 1);
duplex_status <= rxd(3);
end if;
if (inbandreq = '1') then
if (rxd = x"0E") then false_carrier_ind <= '1'; else false_carrier_ind <= '0'; end if;
if (rxd = x"0F") then carrier_ext <= '1'; else carrier_ext <= '0'; end if;
if (rxd = x"1F") then carrier_ext_error <= '1'; else carrier_ext_error <= '0'; end if;
if (rxd = x"FF") then carrier_sense <= '1'; else carrier_sense <= '0'; end if;
end if;
end if;
end process;
-- GMII output
gmiii.rxd <= rxd;
gmiii.rx_dv <= rx_dv;
gmiii.rx_er <= rx_error;
gmiii.rx_clk <= rx_clk;
gmiii.rx_col <= '0';
gmiii.rx_crs <= rx_dv;
gmiii.rmii_clk <= '0';
gmiii.rx_en <= '1';
-- GMII output controlled via generics
gmiii.edclsepahb <= '0';
gmiii.edcldisable <= '0';
gmiii.phyrstaddr <= (others => '0');
gmiii.edcladdr <= (others => '0');
---------------------------------------------------------------------------------------
-- APB Section
---------------------------------------------------------------------------------------
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- Extra registers to ease CDC placement
process (apb_clk)
begin
if apb_clk'event and apb_clk = '1' then
if no_clk_mux = 1 then status_vector_apb(15) <= '1'; else status_vector_apb(15) <= '0'; end if;
if debugmem = 1 then status_vector_apb(14) <= '1'; else status_vector_apb(14) <= '0'; end if;
if gmii = 1 then status_vector_apb(13) <= '1'; else status_vector_apb(13) <= '0'; end if;
status_vector_apb(12 downto 10) <= (others => '0');
status_vector_apb(9) <= gmiio.gbit;
status_vector_apb(8) <= gmiio.speed;
status_vector_apb(7) <= carrier_sense;
status_vector_apb(6) <= carrier_ext_error;
status_vector_apb(5) <= carrier_ext;
status_vector_apb(4) <= false_carrier_ind;
status_vector_apb(3) <= duplex_status;
status_vector_apb(2) <= clock_speed(1);
status_vector_apb(1) <= clock_speed(0);
status_vector_apb(0) <= link_status;
-- Register to detect a speed change
status_vector_apb1 <= status_vector_apb;
status_vector_apb2 <= status_vector_apb1;
end if;
end process;
rgmiiapb : process(apb_rstn, r, apbi, status_vector_apb1, status_vector_apb2, RMemRgmiiiData, RMemRgmiiiRead, RMemRgmiioRead )
variable rdata : std_logic_vector(31 downto 0);
variable paddress : std_logic_vector(7 downto 2);
variable v : rgmiiregs;
begin
v := r;
paddress := (others => '0');
paddress(abits-1 downto 2) := apbi.paddr(abits-1 downto 2);
rdata := (others => '0');
-- read/write registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case paddress(7 downto 2) is
when "000000" =>
rdata(15 downto 0) := status_vector_apb1;
when "000001" =>
rdata(15 downto 0) := r.irq;
v.irq := (others => '0'); -- Interrupt is clear on read
when "000010" =>
rdata(15 downto 0) := r.mask;
when "000011" =>
rdata(5 downto 0) := std_logic_vector(r.clk25_wrap);
when "000100" =>
rdata(5 downto 0) := std_logic_vector(r.clk25_first_edge);
when "000101" =>
rdata(5 downto 0) := std_logic_vector(r.clk25_second_edge);
when "000110" =>
rdata(5 downto 0) := std_logic_vector(r.clk2_5_wrap);
when "000111" =>
rdata(5 downto 0) := std_logic_vector(r.clk2_5_first_edge);
when "001000" =>
rdata(5 downto 0) := std_logic_vector(r.clk2_5_second_edge);
when "001001" =>
rdata(23 downto 0) := r.clkedge;
when "001010" =>
rdata(1 downto 0) := v.rxctrl_q2_delay;
when "001011" =>
rdata(1 downto 0) := v.rxctrl_q1_delay;
when "001100" =>
rdata(0) := v.rxctrl_q1_sel;
when others =>
null;
end case;
end if;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddress(7 downto 2) is
when "000000" =>
null;
when "000001" =>
null;
when "000010" =>
v.mask := apbi.pwdata(15 downto 0);
when "000011" =>
v.clk25_wrap := unsigned(apbi.pwdata(5 downto 0));
when "000100" =>
v.clk25_first_edge := unsigned(apbi.pwdata(5 downto 0));
when "000101" =>
v.clk25_second_edge := unsigned(apbi.pwdata(5 downto 0));
when "000110" =>
v.clk2_5_wrap := unsigned(apbi.pwdata(5 downto 0));
when "000111" =>
v.clk2_5_first_edge := unsigned(apbi.pwdata(5 downto 0));
when "001000" =>
v.clk2_5_second_edge := unsigned(apbi.pwdata(5 downto 0));
when "001001" =>
v.clkedge := apbi.pwdata(23 downto 0);
when "001010" =>
v.rxctrl_q2_delay := apbi.pwdata(1 downto 0);
when "001011" =>
v.rxctrl_q1_delay := apbi.pwdata(1 downto 0);
when "001100" =>
v.rxctrl_q1_sel := apbi.pwdata(0);
when others =>
null;
end case;
end if;
-- Check interrupts
for i in 0 to status_vector_apb'length-1 loop
if ((status_vector_apb1(i) xor status_vector_apb2(i)) and v.mask(i)) = '1' then
v.irq(i) := '1';
end if;
end loop;
-- reset operation
if (not RESET_ALL) and (apb_rstn = '0') then
if (tech = kintex7) then
v := RES_kintex7;
elsif (tech = spartan6) then
v := RES_spartan6;
else
v := RES;
end if;
end if;
-- update registers
rin <= v;
-- drive outputs
if apbi.psel(pindex) = '0' then
apbo.prdata <= (others => '0');
elsif RMemRgmiiiRead = '1' then
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= RMemRgmiiiData;
elsif RMemRgmiioRead = '1' then
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= RMemRgmiioData;
else
apbo.prdata <= rdata;
end if;
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= orv(v.irq);
end process;
regs : process(apb_clk)
begin
if rising_edge(apb_clk) then
r <= rin;
if RESET_ALL and apb_rstn = '0' then
if (tech = kintex7) then
r <= RES_kintex7;
elsif (tech = spartan6) then
r <= RES_spartan6;
else
r <= RES;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------
-- Debug Mem
---------------------------------------------------------------------------------------
debugmem1 : if (debugmem /= 0) generate
-- Write GMII IN data
process (tx_clk)
begin -- process
if rising_edge(tx_clk) then
WMemRgmiioData(15 downto 0) <= "000" & tx_en & "000" & tx_ctl & txd;
if (tx_en = '1') and ((WMemRgmiioAddr < "0111111110") or (WMemRgmiioAddr = "1111111111")) then
WMemRgmiioAddr <= WMemRgmiioAddr + 1;
WMemRgmiioWrEn <= '1';
else
if (tx_en = '0') then
WMemRgmiioAddr <= (others => '1');
else
WMemRgmiioAddr <= WMemRgmiioAddr;
end if;
WMemRgmiioWrEn <= '0';
end if;
end if;
end process;
-- Read
RMemRgmiioRead <= apbi.paddr(10) and apbi.psel(pindex);
RMemRgmiioAddr <= "00" & apbi.paddr(10-1 downto 2);
gmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map(
apb_clk, RMemRgmiioRead, RMemRgmiioAddr, RMemRgmiioData,
tx_clk, WMemRgmiioWrEn, WMemRgmiioAddr(10-1 downto 0), WMemRgmiioData);
-- Write GMII IN data
process (rx_clk)
begin -- process
if rising_edge(rx_clk) then
WMemRgmiiiData(15 downto 0) <= "000" & rx_dv & "000" & rx_ctl & rxd(7 downto 4) & rxd(3 downto 0);
if ((rx_dv = '1') or (rx_ctl = '1')) and ((WMemRgmiiiAddr < "0111111110") or (WMemRgmiiiAddr = "1111111111")) then
WMemRgmiiiAddr <= WMemRgmiiiAddr + 1;
WMemRgmiiiWrEn <= '1';
else
if (rx_dv = '0') then
WMemRgmiiiAddr <= (others => '1');
else
WMemRgmiiiAddr <= WMemRgmiiiAddr;
end if;
WMemRgmiiiWrEn <= '0';
end if;
end if;
end process;
-- Read
RMemRgmiiiRead <= apbi.paddr(11) and apbi.psel(pindex);
RMemRgmiiiAddr <= "00" & apbi.paddr(10-1 downto 2);
rgmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map(
apb_clk, RMemRgmiiiRead, RMemRgmiiiAddr, RMemRgmiiiData,
rx_clk, WMemRgmiiiWrEn, WMemRgmiiiAddr(10-1 downto 0), WMemRgmiiiData);
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("rgmii" & tost(pindex) &
": RGMII rev " & tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end rtl;
|
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity image_selector is
port
(
-- HMDI input 0
rgb_H0 : in std_logic_vector(23 downto 0);
de_H0 : in std_logic;
pclk_H0 : in std_logic;
hsync_H0 : in std_logic;
vsync_H0 : in std_logic;
resX_H0 : in std_logic_vector(15 downto 0);
resY_H0 : in std_logic_vector(15 downto 0);
-- HMDI input 1
rgb_H1 : in std_logic_vector(23 downto 0);
de_H1 : in std_logic;
pclk_H1 : in std_logic;
hsync_H1 : in std_logic;
vsync_H1 : in std_logic;
resX_H1 : in std_logic_vector(15 downto 0);
resY_H1 : in std_logic_vector(15 downto 0);
-- Test Pattern
rgb_tp : in std_logic_vector(23 downto 0);
de_tp : in std_logic;
pclk_tp : in std_logic;
hsync_tp : in std_logic;
vsync_tp : in std_logic;
resX_tp : in std_logic_vector(15 downto 0);
resY_tp : in std_logic_vector(15 downto 0);
-- VGA input
rgb_vga : in std_logic_vector(23 downto 0);
de_vga : in std_logic;
pclk_vga : in std_logic;
hsync_vga : in std_logic;
vsync_vga : in std_logic;
resX_vga : in std_logic_vector(15 downto 0);
resY_vga : in std_logic_vector(15 downto 0);
-- selector_cmd
selector_cmd : in std_logic_vector(12 downto 0);
--Heart Beat Signals
HB_on : in std_logic; -- Port control of heart beat
HB_sw : in std_logic; -- Switch Control of heart beat
-- selected output
rgb : out std_logic_vector(23 downto 0);
de : out std_logic;
hsync : out std_logic;
vsync : out std_logic;
resX : out std_logic_vector(15 downto 0);
resY : out std_logic_vector(15 downto 0);
-- for HDMI Matrix input
rgb_H : out std_logic_vector(23 downto 0);
de_H : out std_logic;
pclk_H : out std_logic;
clk : in std_logic;
rst : in std_logic
);
end entity image_selector;
architecture rtl of image_selector is
COMPONENT image_selector_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT heart_beater is
Generic( HB_length : integer :=5; --length of the heart beat in pixels
HB_width : integer :=5; --width of the heart beat in pixels
alt_aft_frame : integer :=3 --alternate color after this many frames (max value 31)
);
PORT
(
clk : in std_logic;
rst : in std_logic;
HB_on : in std_logic;
HB_sw : in std_logic;
din : in std_logic_vector(23 downto 0);
vsync : in std_logic;
wr_en : in std_logic;
pclk_i : in std_logic;
resX : in std_logic_vector(15 downto 0);
resY : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(23 downto 0)
);
END COMPONENT;
signal pclk_i : std_logic;
signal hdmi_clk : std_logic;
--signal vga_tp_clk : std_logic;
signal full : std_logic;
signal almost_full : std_logic;
signal empty : std_logic;
signal almost_empty : std_logic;
signal valid : std_logic;
signal de_q : std_logic;
signal de_qq : std_logic;
signal de_qqq : std_logic;
signal de_qqqq : std_logic;
signal de_qqqqq : std_logic;
signal de_i : std_logic;
signal rgb_q : std_logic_vector(23 downto 0);
signal rgb_i : std_logic_vector(23 downto 0);
signal din : std_logic_vector(23 downto 0);
signal din_q : std_logic_vector(23 downto 0);
signal Y : std_logic_vector(17 downto 0);
signal Y1 : std_logic_vector(14 downto 0);
signal Y2 : std_logic_vector(16 downto 0);
signal Y3 : std_logic_vector(17 downto 0);
signal red_i : std_logic_vector(7 downto 0);
signal green_i : std_logic_vector(7 downto 0);
signal blue_i : std_logic_vector(7 downto 0);
signal red_q : std_logic_vector(7 downto 0);
signal green_q : std_logic_vector(7 downto 0);
signal blue_q : std_logic_vector(7 downto 0);
signal red_qq : std_logic_vector(7 downto 0);
signal green_qq : std_logic_vector(7 downto 0);
signal blue_qq : std_logic_vector(7 downto 0);
signal red_qqq : std_logic_vector(7 downto 0);
signal green_qqq : std_logic_vector(7 downto 0);
signal blue_qqq : std_logic_vector(7 downto 0);
signal selector : std_logic_vector(12 downto 0);
signal wr_en : std_logic;
signal de_H0_q : std_logic;
signal rgb_H0_q : std_logic_vector(23 downto 0);
signal hsync_H0_q : std_logic;
signal vsync_H0_q : std_logic;
signal resX_H0_q : std_logic_vector(15 downto 0);
signal resY_H0_q : std_logic_vector(15 downto 0);
signal rgb_H1_q : std_logic_vector(23 downto 0);
signal hsync_H1_q : std_logic;
signal de_H1_q : std_logic;
signal vsync_H1_q : std_logic;
signal resX_H1_q : std_logic_vector(15 downto 0);
signal resY_H1_q : std_logic_vector(15 downto 0);
signal rgb_tp_q : std_logic_vector(23 downto 0);
signal de_tp_q : std_logic;
signal hsync_tp_q : std_logic;
signal vsync_tp_q : std_logic;
signal resX_tp_q : std_logic_vector(15 downto 0);
signal resY_tp_q : std_logic_vector(15 downto 0);
signal resX_signal : std_logic_vector(15 downto 0);
signal resY_signal : std_logic_vector(15 downto 0);
signal vsync_s : std_logic;
begin
pclk_H <= pclk_i;--clk input to HDMI Matrix
resX <= resX_signal;
resY <= resY_signal;
process(rst,pclk_H0)
begin
if rst = '1' then
elsif rising_edge(pclk_H0) then
rgb_H0_q <=rgb_H0;
de_H0_q <= de_H0;
hsync_H0_q <= hsync_H0;
vsync_H0_q <= vsync_H0;
resX_H0_q <= resX_H0;
resY_H0_q <= resY_H0;
end if;
end process;
process(rst,pclk_H1)
begin
if rst = '1' then
elsif rising_edge(pclk_H1) then
rgb_H1_q <= rgb_H1;
de_H1_q <= de_H1;
hsync_H1_q <= hsync_H1;
vsync_H1_q <= vsync_H1;
resX_H1_q <= resX_H1;
resY_H1_q <= resY_H1;
end if;
end process;
process(rst,pclk_tp)
begin
if rst = '1' then
elsif rising_edge(pclk_tp) then
rgb_tp_q <= rgb_tp;
de_tp_q <= de_tp;
hsync_tp_q <= hsync_tp;
vsync_tp_q <= vsync_tp;
resX_tp_q <= resX_tp;
resY_tp_q <= resY_tp;
end if;
end process;
process(rst,pclk_i)
begin
if rst = '1' then
valid <= '0';
rgb_i <= (others => '0');
hsync <= '0';
vsync <= '0';
resX_signal <= (others => '0');
resY_signal <= (others => '0');
selector <= (others => '0');
elsif rising_edge(pclk_i) then
selector <= selector_cmd;
case selector(1 downto 0) is
when "00" => -- hdmi 0
rgb_i <= rgb_H0_q;
de_i <= de_H0_q;
hsync <= hsync_H0_q;
vsync <= vsync_H0_q;
resX_signal <= resX_H0_q;
resY_signal <= resY_H0_q;
vsync_s <= vsync_H0_q;
when "01" => -- hdmi 1
rgb_i <= rgb_H1_q;
de_i <= de_H1_q;
hsync <= hsync_H1_q;
vsync <= vsync_H1_q;
resX_signal <= resX_H1_q;
resY_signal <= resY_H1_q;
vsync_s <= vsync_H1_q;
-- when "10" => -- VGA
-- rgb_i <= rgb_vga_q;
-- valid <= de_vga_q;
-- hsync <= hsync_vga_q;
-- vsync <= vsync_vga_q;
-- resX_signal <= resX_vga_q;
-- resY_signal <= resY_vga_q;
when "11" => -- Test Pattern
rgb_i <= rgb_tp_q;
de_i <= de_tp_q;
hsync <= hsync_tp_q;
vsync <= vsync_tp_q;
resX_signal <= resX_tp_q;
resY_signal <= resY_tp_q;
vsync_s <= vsync_tp_q;
when others =>
end case;
end if;
end process;
BUFGMUX_HDMI : BUFGMUX
generic map (
CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
)
port map (
O => hdmi_clk, -- 1-bit output: Clock buffer output
I0 => pclk_H0, -- 1-bit input: Clock buffer input (S=0)
I1 => pclk_H1, -- 1-bit input: Clock buffer input (S=1)
S => selector_cmd(0) -- 1-bit input: Clock buffer select
);
-- BUFGMUX_VGATP : BUFGMUX
-- generic map (
-- CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
-- )
-- port map (
-- O => vga_tp_clk, -- 1-bit output: Clock buffer output
-- I0 => pclk_vga, -- 1-bit input: Clock buffer input (S=0)
-- I1 => pclk_tp, -- 1-bit input: Clock buffer input (S=1)
-- S => selector_q(0) -- 1-bit input: Clock buffer select
-- );
BUFGMUX_PCLK : BUFGMUX
generic map (
CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
)
port map (
O => pclk_i, -- 1-bit output: Clock buffer output
I0 => hdmi_clk, -- 1-bit input: Clock buffer input (S=0)
I1 => pclk_tp, -- 1-bit input: Clock buffer input (S=1)
S => selector_cmd(1) -- 1-bit input: Clock buffer select
);
Y <= Y1 + Y2 + Y3;
rgb_H <= din_q;
de_H <= wr_en;
imgprocess: process(rst,pclk_i)
begin
if rst = '1' then
rgb_q <= (others => '0');
elsif rising_edge(pclk_i) then
Y1 <= conv_std_logic_vector(113,7)*blue_qqq;
Y2 <= conv_std_logic_vector(307,9)*red_qqq;
Y3 <= conv_std_logic_vector(604,10)*green_qqq;
rgb_q <= (blue_i & green_i & red_i);
din <= rgb_q;
wr_en <= de_qqqqq;
de_q <= de_i;
de_qq <= de_q;
de_qqq <= de_qq;
de_qqqq <= de_qqq;
de_qqqqq<= de_qqqq;
if selector(10) = '1' then blue_q <= rgb_i(23 downto 16); else blue_q <= (others => '0'); end if;
if selector(11) = '1' then green_q <= rgb_i(15 downto 8); else green_q <= (others => '0'); end if;
if selector(12) = '1' then red_q <= rgb_i(7 downto 0); else red_q <= (others => '0'); end if;
case selector(5 downto 4) is -- blue
when "00" => blue_qq <= blue_q;
when "01" => blue_qq <= (blue_q(7 downto 3) & "000");
when "10" => blue_qq <= (blue_q(7 downto 4) & "0000");
when "11" => blue_qq <= (blue_q(7 downto 5) & "00000");
when others =>
end case;
case selector(7 downto 6) is -- green
when "00" => green_qq <= green_q;
when "01" => green_qq <= (green_q(7 downto 3) & "000");
when "10" => green_qq <= (green_q(7 downto 4) & "0000");
when "11" => green_qq <= (green_q(7 downto 5) & "00000");
when others =>
end case;
case selector(9 downto 8) is -- red
when "00" => red_qq <= red_q;
when "01" => red_qq <= (red_q(7 downto 3) & "000");
when "10" => red_qq <= (red_q(7 downto 4) & "0000");
when "11" => red_qq <= (red_q(7 downto 5) & "00000");
when others =>
end case;
if selector(3) = '1' then
blue_qqq <= ("11111111" - blue_qq);
green_qqq <= ("11111111" - green_qq);
red_qqq <= ("11111111" - red_qq);
else
blue_qqq <= blue_qq;
green_qqq <= green_qq;
red_qqq <= red_qq;
end if;
if selector(2) = '1' then
blue_i <= blue_qqq;
green_i <= green_qqq;
red_i <= red_qqq;
else
blue_i <= Y(17 downto 10);
green_i <= Y(17 downto 10);
red_i <= Y(17 downto 10);
end if;
end if;-- clk
end process; -- imgprocess
selector_fifo : image_selector_fifo
PORT MAP (
rst => rst,
wr_clk => pclk_i,
rd_clk => clk,
din => din_q,
wr_en => wr_en,
rd_en => '1',
dout => rgb,
full => full,
almost_full => almost_full,
empty => empty,
almost_empty => almost_empty,
valid => de
);
Inst_heart_beater: heart_beater
GENERIC MAP (
HB_length => 5,-- length of heart beat in pixel
HB_width => 5,-- width of heart beat in pixel
alt_aft_frame=>30 --the color alternates after this many frames
)
PORT MAP(
clk => clk,
rst =>rst ,
HB_on => HB_on,
HB_sw => HB_sw,
din => din,
wr_en => wr_en,
vsync => vsync_s,
pclk_i => pclk_i,
resX => resX_signal,
resY => resY_signal,
dout => din_q
);
end architecture;
|
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity image_selector is
port
(
-- HMDI input 0
rgb_H0 : in std_logic_vector(23 downto 0);
de_H0 : in std_logic;
pclk_H0 : in std_logic;
hsync_H0 : in std_logic;
vsync_H0 : in std_logic;
resX_H0 : in std_logic_vector(15 downto 0);
resY_H0 : in std_logic_vector(15 downto 0);
-- HMDI input 1
rgb_H1 : in std_logic_vector(23 downto 0);
de_H1 : in std_logic;
pclk_H1 : in std_logic;
hsync_H1 : in std_logic;
vsync_H1 : in std_logic;
resX_H1 : in std_logic_vector(15 downto 0);
resY_H1 : in std_logic_vector(15 downto 0);
-- Test Pattern
rgb_tp : in std_logic_vector(23 downto 0);
de_tp : in std_logic;
pclk_tp : in std_logic;
hsync_tp : in std_logic;
vsync_tp : in std_logic;
resX_tp : in std_logic_vector(15 downto 0);
resY_tp : in std_logic_vector(15 downto 0);
-- VGA input
rgb_vga : in std_logic_vector(23 downto 0);
de_vga : in std_logic;
pclk_vga : in std_logic;
hsync_vga : in std_logic;
vsync_vga : in std_logic;
resX_vga : in std_logic_vector(15 downto 0);
resY_vga : in std_logic_vector(15 downto 0);
-- selector_cmd
selector_cmd : in std_logic_vector(12 downto 0);
--Heart Beat Signals
HB_on : in std_logic; -- Port control of heart beat
HB_sw : in std_logic; -- Switch Control of heart beat
-- selected output
rgb : out std_logic_vector(23 downto 0);
de : out std_logic;
hsync : out std_logic;
vsync : out std_logic;
resX : out std_logic_vector(15 downto 0);
resY : out std_logic_vector(15 downto 0);
-- for HDMI Matrix input
rgb_H : out std_logic_vector(23 downto 0);
de_H : out std_logic;
pclk_H : out std_logic;
clk : in std_logic;
rst : in std_logic
);
end entity image_selector;
architecture rtl of image_selector is
COMPONENT image_selector_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT heart_beater is
Generic( HB_length : integer :=5; --length of the heart beat in pixels
HB_width : integer :=5; --width of the heart beat in pixels
alt_aft_frame : integer :=3 --alternate color after this many frames (max value 31)
);
PORT
(
clk : in std_logic;
rst : in std_logic;
HB_on : in std_logic;
HB_sw : in std_logic;
din : in std_logic_vector(23 downto 0);
vsync : in std_logic;
wr_en : in std_logic;
pclk_i : in std_logic;
resX : in std_logic_vector(15 downto 0);
resY : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(23 downto 0)
);
END COMPONENT;
signal pclk_i : std_logic;
signal hdmi_clk : std_logic;
--signal vga_tp_clk : std_logic;
signal full : std_logic;
signal almost_full : std_logic;
signal empty : std_logic;
signal almost_empty : std_logic;
signal valid : std_logic;
signal de_q : std_logic;
signal de_qq : std_logic;
signal de_qqq : std_logic;
signal de_qqqq : std_logic;
signal de_qqqqq : std_logic;
signal de_i : std_logic;
signal rgb_q : std_logic_vector(23 downto 0);
signal rgb_i : std_logic_vector(23 downto 0);
signal din : std_logic_vector(23 downto 0);
signal din_q : std_logic_vector(23 downto 0);
signal Y : std_logic_vector(17 downto 0);
signal Y1 : std_logic_vector(14 downto 0);
signal Y2 : std_logic_vector(16 downto 0);
signal Y3 : std_logic_vector(17 downto 0);
signal red_i : std_logic_vector(7 downto 0);
signal green_i : std_logic_vector(7 downto 0);
signal blue_i : std_logic_vector(7 downto 0);
signal red_q : std_logic_vector(7 downto 0);
signal green_q : std_logic_vector(7 downto 0);
signal blue_q : std_logic_vector(7 downto 0);
signal red_qq : std_logic_vector(7 downto 0);
signal green_qq : std_logic_vector(7 downto 0);
signal blue_qq : std_logic_vector(7 downto 0);
signal red_qqq : std_logic_vector(7 downto 0);
signal green_qqq : std_logic_vector(7 downto 0);
signal blue_qqq : std_logic_vector(7 downto 0);
signal selector : std_logic_vector(12 downto 0);
signal wr_en : std_logic;
signal de_H0_q : std_logic;
signal rgb_H0_q : std_logic_vector(23 downto 0);
signal hsync_H0_q : std_logic;
signal vsync_H0_q : std_logic;
signal resX_H0_q : std_logic_vector(15 downto 0);
signal resY_H0_q : std_logic_vector(15 downto 0);
signal rgb_H1_q : std_logic_vector(23 downto 0);
signal hsync_H1_q : std_logic;
signal de_H1_q : std_logic;
signal vsync_H1_q : std_logic;
signal resX_H1_q : std_logic_vector(15 downto 0);
signal resY_H1_q : std_logic_vector(15 downto 0);
signal rgb_tp_q : std_logic_vector(23 downto 0);
signal de_tp_q : std_logic;
signal hsync_tp_q : std_logic;
signal vsync_tp_q : std_logic;
signal resX_tp_q : std_logic_vector(15 downto 0);
signal resY_tp_q : std_logic_vector(15 downto 0);
signal resX_signal : std_logic_vector(15 downto 0);
signal resY_signal : std_logic_vector(15 downto 0);
signal vsync_s : std_logic;
begin
pclk_H <= pclk_i;--clk input to HDMI Matrix
resX <= resX_signal;
resY <= resY_signal;
process(rst,pclk_H0)
begin
if rst = '1' then
elsif rising_edge(pclk_H0) then
rgb_H0_q <=rgb_H0;
de_H0_q <= de_H0;
hsync_H0_q <= hsync_H0;
vsync_H0_q <= vsync_H0;
resX_H0_q <= resX_H0;
resY_H0_q <= resY_H0;
end if;
end process;
process(rst,pclk_H1)
begin
if rst = '1' then
elsif rising_edge(pclk_H1) then
rgb_H1_q <= rgb_H1;
de_H1_q <= de_H1;
hsync_H1_q <= hsync_H1;
vsync_H1_q <= vsync_H1;
resX_H1_q <= resX_H1;
resY_H1_q <= resY_H1;
end if;
end process;
process(rst,pclk_tp)
begin
if rst = '1' then
elsif rising_edge(pclk_tp) then
rgb_tp_q <= rgb_tp;
de_tp_q <= de_tp;
hsync_tp_q <= hsync_tp;
vsync_tp_q <= vsync_tp;
resX_tp_q <= resX_tp;
resY_tp_q <= resY_tp;
end if;
end process;
process(rst,pclk_i)
begin
if rst = '1' then
valid <= '0';
rgb_i <= (others => '0');
hsync <= '0';
vsync <= '0';
resX_signal <= (others => '0');
resY_signal <= (others => '0');
selector <= (others => '0');
elsif rising_edge(pclk_i) then
selector <= selector_cmd;
case selector(1 downto 0) is
when "00" => -- hdmi 0
rgb_i <= rgb_H0_q;
de_i <= de_H0_q;
hsync <= hsync_H0_q;
vsync <= vsync_H0_q;
resX_signal <= resX_H0_q;
resY_signal <= resY_H0_q;
vsync_s <= vsync_H0_q;
when "01" => -- hdmi 1
rgb_i <= rgb_H1_q;
de_i <= de_H1_q;
hsync <= hsync_H1_q;
vsync <= vsync_H1_q;
resX_signal <= resX_H1_q;
resY_signal <= resY_H1_q;
vsync_s <= vsync_H1_q;
-- when "10" => -- VGA
-- rgb_i <= rgb_vga_q;
-- valid <= de_vga_q;
-- hsync <= hsync_vga_q;
-- vsync <= vsync_vga_q;
-- resX_signal <= resX_vga_q;
-- resY_signal <= resY_vga_q;
when "11" => -- Test Pattern
rgb_i <= rgb_tp_q;
de_i <= de_tp_q;
hsync <= hsync_tp_q;
vsync <= vsync_tp_q;
resX_signal <= resX_tp_q;
resY_signal <= resY_tp_q;
vsync_s <= vsync_tp_q;
when others =>
end case;
end if;
end process;
BUFGMUX_HDMI : BUFGMUX
generic map (
CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
)
port map (
O => hdmi_clk, -- 1-bit output: Clock buffer output
I0 => pclk_H0, -- 1-bit input: Clock buffer input (S=0)
I1 => pclk_H1, -- 1-bit input: Clock buffer input (S=1)
S => selector_cmd(0) -- 1-bit input: Clock buffer select
);
-- BUFGMUX_VGATP : BUFGMUX
-- generic map (
-- CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
-- )
-- port map (
-- O => vga_tp_clk, -- 1-bit output: Clock buffer output
-- I0 => pclk_vga, -- 1-bit input: Clock buffer input (S=0)
-- I1 => pclk_tp, -- 1-bit input: Clock buffer input (S=1)
-- S => selector_q(0) -- 1-bit input: Clock buffer select
-- );
BUFGMUX_PCLK : BUFGMUX
generic map (
CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
)
port map (
O => pclk_i, -- 1-bit output: Clock buffer output
I0 => hdmi_clk, -- 1-bit input: Clock buffer input (S=0)
I1 => pclk_tp, -- 1-bit input: Clock buffer input (S=1)
S => selector_cmd(1) -- 1-bit input: Clock buffer select
);
Y <= Y1 + Y2 + Y3;
rgb_H <= din_q;
de_H <= wr_en;
imgprocess: process(rst,pclk_i)
begin
if rst = '1' then
rgb_q <= (others => '0');
elsif rising_edge(pclk_i) then
Y1 <= conv_std_logic_vector(113,7)*blue_qqq;
Y2 <= conv_std_logic_vector(307,9)*red_qqq;
Y3 <= conv_std_logic_vector(604,10)*green_qqq;
rgb_q <= (blue_i & green_i & red_i);
din <= rgb_q;
wr_en <= de_qqqqq;
de_q <= de_i;
de_qq <= de_q;
de_qqq <= de_qq;
de_qqqq <= de_qqq;
de_qqqqq<= de_qqqq;
if selector(10) = '1' then blue_q <= rgb_i(23 downto 16); else blue_q <= (others => '0'); end if;
if selector(11) = '1' then green_q <= rgb_i(15 downto 8); else green_q <= (others => '0'); end if;
if selector(12) = '1' then red_q <= rgb_i(7 downto 0); else red_q <= (others => '0'); end if;
case selector(5 downto 4) is -- blue
when "00" => blue_qq <= blue_q;
when "01" => blue_qq <= (blue_q(7 downto 3) & "000");
when "10" => blue_qq <= (blue_q(7 downto 4) & "0000");
when "11" => blue_qq <= (blue_q(7 downto 5) & "00000");
when others =>
end case;
case selector(7 downto 6) is -- green
when "00" => green_qq <= green_q;
when "01" => green_qq <= (green_q(7 downto 3) & "000");
when "10" => green_qq <= (green_q(7 downto 4) & "0000");
when "11" => green_qq <= (green_q(7 downto 5) & "00000");
when others =>
end case;
case selector(9 downto 8) is -- red
when "00" => red_qq <= red_q;
when "01" => red_qq <= (red_q(7 downto 3) & "000");
when "10" => red_qq <= (red_q(7 downto 4) & "0000");
when "11" => red_qq <= (red_q(7 downto 5) & "00000");
when others =>
end case;
if selector(3) = '1' then
blue_qqq <= ("11111111" - blue_qq);
green_qqq <= ("11111111" - green_qq);
red_qqq <= ("11111111" - red_qq);
else
blue_qqq <= blue_qq;
green_qqq <= green_qq;
red_qqq <= red_qq;
end if;
if selector(2) = '1' then
blue_i <= blue_qqq;
green_i <= green_qqq;
red_i <= red_qqq;
else
blue_i <= Y(17 downto 10);
green_i <= Y(17 downto 10);
red_i <= Y(17 downto 10);
end if;
end if;-- clk
end process; -- imgprocess
selector_fifo : image_selector_fifo
PORT MAP (
rst => rst,
wr_clk => pclk_i,
rd_clk => clk,
din => din_q,
wr_en => wr_en,
rd_en => '1',
dout => rgb,
full => full,
almost_full => almost_full,
empty => empty,
almost_empty => almost_empty,
valid => de
);
Inst_heart_beater: heart_beater
GENERIC MAP (
HB_length => 5,-- length of heart beat in pixel
HB_width => 5,-- width of heart beat in pixel
alt_aft_frame=>30 --the color alternates after this many frames
)
PORT MAP(
clk => clk,
rst =>rst ,
HB_on => HB_on,
HB_sw => HB_sw,
din => din,
wr_en => wr_en,
vsync => vsync_s,
pclk_i => pclk_i,
resX => resX_signal,
resY => resY_signal,
dout => din_q
);
end architecture;
|
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity image_selector is
port
(
-- HMDI input 0
rgb_H0 : in std_logic_vector(23 downto 0);
de_H0 : in std_logic;
pclk_H0 : in std_logic;
hsync_H0 : in std_logic;
vsync_H0 : in std_logic;
resX_H0 : in std_logic_vector(15 downto 0);
resY_H0 : in std_logic_vector(15 downto 0);
-- HMDI input 1
rgb_H1 : in std_logic_vector(23 downto 0);
de_H1 : in std_logic;
pclk_H1 : in std_logic;
hsync_H1 : in std_logic;
vsync_H1 : in std_logic;
resX_H1 : in std_logic_vector(15 downto 0);
resY_H1 : in std_logic_vector(15 downto 0);
-- Test Pattern
rgb_tp : in std_logic_vector(23 downto 0);
de_tp : in std_logic;
pclk_tp : in std_logic;
hsync_tp : in std_logic;
vsync_tp : in std_logic;
resX_tp : in std_logic_vector(15 downto 0);
resY_tp : in std_logic_vector(15 downto 0);
-- VGA input
rgb_vga : in std_logic_vector(23 downto 0);
de_vga : in std_logic;
pclk_vga : in std_logic;
hsync_vga : in std_logic;
vsync_vga : in std_logic;
resX_vga : in std_logic_vector(15 downto 0);
resY_vga : in std_logic_vector(15 downto 0);
-- selector_cmd
selector_cmd : in std_logic_vector(12 downto 0);
--Heart Beat Signals
HB_on : in std_logic; -- Port control of heart beat
HB_sw : in std_logic; -- Switch Control of heart beat
-- selected output
rgb : out std_logic_vector(23 downto 0);
de : out std_logic;
hsync : out std_logic;
vsync : out std_logic;
resX : out std_logic_vector(15 downto 0);
resY : out std_logic_vector(15 downto 0);
-- for HDMI Matrix input
rgb_H : out std_logic_vector(23 downto 0);
de_H : out std_logic;
pclk_H : out std_logic;
clk : in std_logic;
rst : in std_logic
);
end entity image_selector;
architecture rtl of image_selector is
COMPONENT image_selector_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT heart_beater is
Generic( HB_length : integer :=5; --length of the heart beat in pixels
HB_width : integer :=5; --width of the heart beat in pixels
alt_aft_frame : integer :=3 --alternate color after this many frames (max value 31)
);
PORT
(
clk : in std_logic;
rst : in std_logic;
HB_on : in std_logic;
HB_sw : in std_logic;
din : in std_logic_vector(23 downto 0);
vsync : in std_logic;
wr_en : in std_logic;
pclk_i : in std_logic;
resX : in std_logic_vector(15 downto 0);
resY : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(23 downto 0)
);
END COMPONENT;
signal pclk_i : std_logic;
signal hdmi_clk : std_logic;
--signal vga_tp_clk : std_logic;
signal full : std_logic;
signal almost_full : std_logic;
signal empty : std_logic;
signal almost_empty : std_logic;
signal valid : std_logic;
signal de_q : std_logic;
signal de_qq : std_logic;
signal de_qqq : std_logic;
signal de_qqqq : std_logic;
signal de_qqqqq : std_logic;
signal de_i : std_logic;
signal rgb_q : std_logic_vector(23 downto 0);
signal rgb_i : std_logic_vector(23 downto 0);
signal din : std_logic_vector(23 downto 0);
signal din_q : std_logic_vector(23 downto 0);
signal Y : std_logic_vector(17 downto 0);
signal Y1 : std_logic_vector(14 downto 0);
signal Y2 : std_logic_vector(16 downto 0);
signal Y3 : std_logic_vector(17 downto 0);
signal red_i : std_logic_vector(7 downto 0);
signal green_i : std_logic_vector(7 downto 0);
signal blue_i : std_logic_vector(7 downto 0);
signal red_q : std_logic_vector(7 downto 0);
signal green_q : std_logic_vector(7 downto 0);
signal blue_q : std_logic_vector(7 downto 0);
signal red_qq : std_logic_vector(7 downto 0);
signal green_qq : std_logic_vector(7 downto 0);
signal blue_qq : std_logic_vector(7 downto 0);
signal red_qqq : std_logic_vector(7 downto 0);
signal green_qqq : std_logic_vector(7 downto 0);
signal blue_qqq : std_logic_vector(7 downto 0);
signal selector : std_logic_vector(12 downto 0);
signal wr_en : std_logic;
signal de_H0_q : std_logic;
signal rgb_H0_q : std_logic_vector(23 downto 0);
signal hsync_H0_q : std_logic;
signal vsync_H0_q : std_logic;
signal resX_H0_q : std_logic_vector(15 downto 0);
signal resY_H0_q : std_logic_vector(15 downto 0);
signal rgb_H1_q : std_logic_vector(23 downto 0);
signal hsync_H1_q : std_logic;
signal de_H1_q : std_logic;
signal vsync_H1_q : std_logic;
signal resX_H1_q : std_logic_vector(15 downto 0);
signal resY_H1_q : std_logic_vector(15 downto 0);
signal rgb_tp_q : std_logic_vector(23 downto 0);
signal de_tp_q : std_logic;
signal hsync_tp_q : std_logic;
signal vsync_tp_q : std_logic;
signal resX_tp_q : std_logic_vector(15 downto 0);
signal resY_tp_q : std_logic_vector(15 downto 0);
signal resX_signal : std_logic_vector(15 downto 0);
signal resY_signal : std_logic_vector(15 downto 0);
signal vsync_s : std_logic;
begin
pclk_H <= pclk_i;--clk input to HDMI Matrix
resX <= resX_signal;
resY <= resY_signal;
process(rst,pclk_H0)
begin
if rst = '1' then
elsif rising_edge(pclk_H0) then
rgb_H0_q <=rgb_H0;
de_H0_q <= de_H0;
hsync_H0_q <= hsync_H0;
vsync_H0_q <= vsync_H0;
resX_H0_q <= resX_H0;
resY_H0_q <= resY_H0;
end if;
end process;
process(rst,pclk_H1)
begin
if rst = '1' then
elsif rising_edge(pclk_H1) then
rgb_H1_q <= rgb_H1;
de_H1_q <= de_H1;
hsync_H1_q <= hsync_H1;
vsync_H1_q <= vsync_H1;
resX_H1_q <= resX_H1;
resY_H1_q <= resY_H1;
end if;
end process;
process(rst,pclk_tp)
begin
if rst = '1' then
elsif rising_edge(pclk_tp) then
rgb_tp_q <= rgb_tp;
de_tp_q <= de_tp;
hsync_tp_q <= hsync_tp;
vsync_tp_q <= vsync_tp;
resX_tp_q <= resX_tp;
resY_tp_q <= resY_tp;
end if;
end process;
process(rst,pclk_i)
begin
if rst = '1' then
valid <= '0';
rgb_i <= (others => '0');
hsync <= '0';
vsync <= '0';
resX_signal <= (others => '0');
resY_signal <= (others => '0');
selector <= (others => '0');
elsif rising_edge(pclk_i) then
selector <= selector_cmd;
case selector(1 downto 0) is
when "00" => -- hdmi 0
rgb_i <= rgb_H0_q;
de_i <= de_H0_q;
hsync <= hsync_H0_q;
vsync <= vsync_H0_q;
resX_signal <= resX_H0_q;
resY_signal <= resY_H0_q;
vsync_s <= vsync_H0_q;
when "01" => -- hdmi 1
rgb_i <= rgb_H1_q;
de_i <= de_H1_q;
hsync <= hsync_H1_q;
vsync <= vsync_H1_q;
resX_signal <= resX_H1_q;
resY_signal <= resY_H1_q;
vsync_s <= vsync_H1_q;
-- when "10" => -- VGA
-- rgb_i <= rgb_vga_q;
-- valid <= de_vga_q;
-- hsync <= hsync_vga_q;
-- vsync <= vsync_vga_q;
-- resX_signal <= resX_vga_q;
-- resY_signal <= resY_vga_q;
when "11" => -- Test Pattern
rgb_i <= rgb_tp_q;
de_i <= de_tp_q;
hsync <= hsync_tp_q;
vsync <= vsync_tp_q;
resX_signal <= resX_tp_q;
resY_signal <= resY_tp_q;
vsync_s <= vsync_tp_q;
when others =>
end case;
end if;
end process;
BUFGMUX_HDMI : BUFGMUX
generic map (
CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
)
port map (
O => hdmi_clk, -- 1-bit output: Clock buffer output
I0 => pclk_H0, -- 1-bit input: Clock buffer input (S=0)
I1 => pclk_H1, -- 1-bit input: Clock buffer input (S=1)
S => selector_cmd(0) -- 1-bit input: Clock buffer select
);
-- BUFGMUX_VGATP : BUFGMUX
-- generic map (
-- CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
-- )
-- port map (
-- O => vga_tp_clk, -- 1-bit output: Clock buffer output
-- I0 => pclk_vga, -- 1-bit input: Clock buffer input (S=0)
-- I1 => pclk_tp, -- 1-bit input: Clock buffer input (S=1)
-- S => selector_q(0) -- 1-bit input: Clock buffer select
-- );
BUFGMUX_PCLK : BUFGMUX
generic map (
CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
)
port map (
O => pclk_i, -- 1-bit output: Clock buffer output
I0 => hdmi_clk, -- 1-bit input: Clock buffer input (S=0)
I1 => pclk_tp, -- 1-bit input: Clock buffer input (S=1)
S => selector_cmd(1) -- 1-bit input: Clock buffer select
);
Y <= Y1 + Y2 + Y3;
rgb_H <= din_q;
de_H <= wr_en;
imgprocess: process(rst,pclk_i)
begin
if rst = '1' then
rgb_q <= (others => '0');
elsif rising_edge(pclk_i) then
Y1 <= conv_std_logic_vector(113,7)*blue_qqq;
Y2 <= conv_std_logic_vector(307,9)*red_qqq;
Y3 <= conv_std_logic_vector(604,10)*green_qqq;
rgb_q <= (blue_i & green_i & red_i);
din <= rgb_q;
wr_en <= de_qqqqq;
de_q <= de_i;
de_qq <= de_q;
de_qqq <= de_qq;
de_qqqq <= de_qqq;
de_qqqqq<= de_qqqq;
if selector(10) = '1' then blue_q <= rgb_i(23 downto 16); else blue_q <= (others => '0'); end if;
if selector(11) = '1' then green_q <= rgb_i(15 downto 8); else green_q <= (others => '0'); end if;
if selector(12) = '1' then red_q <= rgb_i(7 downto 0); else red_q <= (others => '0'); end if;
case selector(5 downto 4) is -- blue
when "00" => blue_qq <= blue_q;
when "01" => blue_qq <= (blue_q(7 downto 3) & "000");
when "10" => blue_qq <= (blue_q(7 downto 4) & "0000");
when "11" => blue_qq <= (blue_q(7 downto 5) & "00000");
when others =>
end case;
case selector(7 downto 6) is -- green
when "00" => green_qq <= green_q;
when "01" => green_qq <= (green_q(7 downto 3) & "000");
when "10" => green_qq <= (green_q(7 downto 4) & "0000");
when "11" => green_qq <= (green_q(7 downto 5) & "00000");
when others =>
end case;
case selector(9 downto 8) is -- red
when "00" => red_qq <= red_q;
when "01" => red_qq <= (red_q(7 downto 3) & "000");
when "10" => red_qq <= (red_q(7 downto 4) & "0000");
when "11" => red_qq <= (red_q(7 downto 5) & "00000");
when others =>
end case;
if selector(3) = '1' then
blue_qqq <= ("11111111" - blue_qq);
green_qqq <= ("11111111" - green_qq);
red_qqq <= ("11111111" - red_qq);
else
blue_qqq <= blue_qq;
green_qqq <= green_qq;
red_qqq <= red_qq;
end if;
if selector(2) = '1' then
blue_i <= blue_qqq;
green_i <= green_qqq;
red_i <= red_qqq;
else
blue_i <= Y(17 downto 10);
green_i <= Y(17 downto 10);
red_i <= Y(17 downto 10);
end if;
end if;-- clk
end process; -- imgprocess
selector_fifo : image_selector_fifo
PORT MAP (
rst => rst,
wr_clk => pclk_i,
rd_clk => clk,
din => din_q,
wr_en => wr_en,
rd_en => '1',
dout => rgb,
full => full,
almost_full => almost_full,
empty => empty,
almost_empty => almost_empty,
valid => de
);
Inst_heart_beater: heart_beater
GENERIC MAP (
HB_length => 5,-- length of heart beat in pixel
HB_width => 5,-- width of heart beat in pixel
alt_aft_frame=>30 --the color alternates after this many frames
)
PORT MAP(
clk => clk,
rst =>rst ,
HB_on => HB_on,
HB_sw => HB_sw,
din => din,
wr_en => wr_en,
vsync => vsync_s,
pclk_i => pclk_i,
resX => resX_signal,
resY => resY_signal,
dout => din_q
);
end architecture;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT RX_RECV_FIFO_top IS
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
-------------------------------------------------------------------------------
--
-- Testbench for the T421 system toplevel.
--
-- $Id: tb_t421-c.vhd,v 1.1 2006-06-11 13:49:50 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration tb_t421_behav_c0 of tb_t421 is
for behav
for t421_b: t421
use configuration work.t421_struct_c0;
end for;
for tb_elems_b: tb_elems
use configuration work.tb_elems_behav_c0;
end for;
end for;
end tb_t421_behav_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc289.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p13n01i00289ent IS
END c03s01b03x00p13n01i00289ent;
ARCHITECTURE c03s01b03x00p13n01i00289arch OF c03s01b03x00p13n01i00289ent IS
type T is
range 1 to 100
units
I ;
J = 2 I;
K = 2 J;
L = 10 K;
end units;
signal S1 : T;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= 10 * L;
assert FALSE
report "***FAILED TEST: c03s01b03x00p13n01i00289 - Value doesn't belong to the physical type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p13n01i00289arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc289.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p13n01i00289ent IS
END c03s01b03x00p13n01i00289ent;
ARCHITECTURE c03s01b03x00p13n01i00289arch OF c03s01b03x00p13n01i00289ent IS
type T is
range 1 to 100
units
I ;
J = 2 I;
K = 2 J;
L = 10 K;
end units;
signal S1 : T;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= 10 * L;
assert FALSE
report "***FAILED TEST: c03s01b03x00p13n01i00289 - Value doesn't belong to the physical type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p13n01i00289arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc289.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p13n01i00289ent IS
END c03s01b03x00p13n01i00289ent;
ARCHITECTURE c03s01b03x00p13n01i00289arch OF c03s01b03x00p13n01i00289ent IS
type T is
range 1 to 100
units
I ;
J = 2 I;
K = 2 J;
L = 10 K;
end units;
signal S1 : T;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= 10 * L;
assert FALSE
report "***FAILED TEST: c03s01b03x00p13n01i00289 - Value doesn't belong to the physical type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p13n01i00289arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity cache is
port ( Sysadress : out std_logic_vector (15 downto 0);
Sysstrobe : out std_logic;
Sysrw : out std_logic;
Sysdata : inout std_logic_vector (7 downto 0));
end cache;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sample_iterator_get_offset is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
indices_req_din : OUT STD_LOGIC;
indices_req_full_n : IN STD_LOGIC;
indices_req_write : OUT STD_LOGIC;
indices_rsp_empty_n : IN STD_LOGIC;
indices_rsp_read : OUT STD_LOGIC;
indices_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_datain : IN STD_LOGIC_VECTOR (55 downto 0);
indices_dataout : OUT STD_LOGIC_VECTOR (55 downto 0);
indices_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of sample_iterator_get_offset is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000";
constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
constant ap_const_lv56_0 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal tmp_4_fu_92_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_reg_134 : STD_LOGIC_VECTOR (31 downto 0);
signal indices_stride_load_new_reg_139 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_fu_81_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_s_fu_113_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_s_fu_113_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_s_fu_113_p2 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_17_cast_fu_119_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_s_fu_113_p00 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_s_fu_113_p10 : STD_LOGIC_VECTOR (23 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and not((indices_rsp_empty_n = ap_const_logic_0)))) then
indices_stride_load_new_reg_139 <= indices_datain(55 downto 48);
tmp_4_reg_134 <= tmp_4_fu_92_p1;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , indices_rsp_empty_n)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
if (not((indices_rsp_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm)) or (ap_ST_st4_fsm_3 = ap_CS_fsm))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= std_logic_vector(unsigned(tmp_17_cast_fu_119_p1) + unsigned(tmp_4_reg_134));
indices_address <= tmp_fu_81_p1(32 - 1 downto 0);
indices_dataout <= ap_const_lv56_0;
indices_req_din <= ap_const_logic_0;
-- indices_req_write assign process. --
indices_req_write_assign_proc : process(ap_start, ap_CS_fsm)
begin
if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
indices_req_write <= ap_const_logic_1;
else
indices_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_rsp_read assign process. --
indices_rsp_read_assign_proc : process(ap_CS_fsm, indices_rsp_empty_n)
begin
if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and not((indices_rsp_empty_n = ap_const_logic_0)))) then
indices_rsp_read <= ap_const_logic_1;
else
indices_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_size <= ap_const_lv32_1;
tmp_17_cast_fu_119_p1 <= std_logic_vector(resize(unsigned(tmp_s_fu_113_p2),32));
tmp_4_fu_92_p1 <= indices_datain(32 - 1 downto 0);
tmp_fu_81_p1 <= std_logic_vector(resize(unsigned(i_index),64));
tmp_s_fu_113_p0 <= tmp_s_fu_113_p00(16 - 1 downto 0);
tmp_s_fu_113_p00 <= std_logic_vector(resize(unsigned(i_sample),24));
tmp_s_fu_113_p1 <= tmp_s_fu_113_p10(8 - 1 downto 0);
tmp_s_fu_113_p10 <= std_logic_vector(resize(unsigned(indices_stride_load_new_reg_139),24));
tmp_s_fu_113_p2 <= std_logic_vector(resize(unsigned(tmp_s_fu_113_p0) * unsigned(tmp_s_fu_113_p1), 24));
end behav;
|
-----------------------Implementation of a Full adder ---------------
-------------- Library statements -------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity declaration full_adder--
entity full_adder is
port (FAa, FAb, FAcin : in std_logic;
FAsum, FAcout : out std_logic;
FAc1, FAc2, s1 : buffer std_logic
);
end full_adder;
architecture FA of full_adder is
begin
h1: entity work.half_adder_structrual port map(a=>FAa,b=>FAb,sum=>s1,carry=>FAc1);
h2: entity work.half_adder_dataflow port map(a=>s1,b=>FAcin,sum=>FAsum,carry=>FAc2);
FAcout <= FAc1 or FAc2;
end FA; |
----------------------------------------------------------------------------------
-- Company: N/A
-- Engineer: WTMW
-- Create Date: 22:27:15 09/26/2014
-- Design Name:
-- Module Name: Hamming_byte_test.vhd
-- Project Name: project_nrf
-- Target Devices: Nexys 4
-- Tool versions: ISE WEBPACK 64-Bit
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
use work.project_nrf_subprog.all;
ENTITY Hamming_byte_test IS
END Hamming_byte_test;
ARCHITECTURE behavior OF Hamming_byte_test IS
-- Test Signals
signal data_byte : std_logic_vector(7 downto 0) := "00100101";
signal encoded_h_word : std_logic_vector(15 downto 0) := (others => '0');
signal err_h_word : std_logic_vector(15 downto 0) := "1000000010000000";
signal decoded_byte : std_logic_vector(7 downto 0) := (others => '0');
-- CLK Signals
signal clk : std_logic := '0';
constant clk_period : time := 10 ns;
signal masterReset : std_logic := '1';
BEGIN
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
process
begin
wait for clk_period*10;
encoded_h_word <= Hamming_Byte_encoder(data_byte);
wait for clk_period;
encoded_h_word <= encoded_h_word XOR err_h_word;
wait for clk_period;
decoded_byte <= Hamming_Byte_decoder(encoded_h_word);
wait for clk_period;
wait for clk_period*10;
wait;
end process;
END;
|
-- Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
-- Date : Thu Mar 27 13:22:53 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim /home/keith/Documents/VHDL-lib/top/lab_3/part_2/ip/dds/dds_funcsim.vhdl
-- Design : dds
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddspipe_add__parameterized0\ is
port (
temp : out STD_LOGIC_VECTOR ( 16 downto 0 );
L : in STD_LOGIC_VECTOR ( 15 downto 0 );
reg_s_phase_fifo_din : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddspipe_add__parameterized0\ : entity is "pipe_add";
end \ddspipe_add__parameterized0\;
architecture STRUCTURE of \ddspipe_add__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[11]_i_2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[11]_i_3\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[11]_i_4\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[11]_i_5\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[15]_i_2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[15]_i_3\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[15]_i_4\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[15]_i_5\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[3]_i_2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[3]_i_3\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[3]_i_4\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[3]_i_5\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[7]_i_2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[7]_i_3\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[7]_i_4\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[7]_i_5\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC;
signal \n_1_opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC;
signal \n_1_opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC;
signal \n_1_opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC;
signal \n_1_opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC;
signal \n_2_opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC;
signal \n_2_opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC;
signal \n_2_opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC;
signal \n_2_opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC;
signal \n_3_opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC;
signal \n_3_opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC;
signal \n_3_opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC;
signal \n_3_opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC;
signal \NLW_opt_has_pipe.first_q_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_opt_has_pipe.first_q_reg[16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\opt_has_pipe.first_q[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(11),
I1 => reg_s_phase_fifo_din(11),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(11),
O => \n_0_opt_has_pipe.first_q[11]_i_2\
);
\opt_has_pipe.first_q[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(10),
I1 => reg_s_phase_fifo_din(10),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(10),
O => \n_0_opt_has_pipe.first_q[11]_i_3\
);
\opt_has_pipe.first_q[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(9),
I1 => reg_s_phase_fifo_din(9),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(9),
O => \n_0_opt_has_pipe.first_q[11]_i_4\
);
\opt_has_pipe.first_q[11]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(8),
I1 => reg_s_phase_fifo_din(8),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(8),
O => \n_0_opt_has_pipe.first_q[11]_i_5\
);
\opt_has_pipe.first_q[15]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(15),
I1 => reg_s_phase_fifo_din(15),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(15),
O => \n_0_opt_has_pipe.first_q[15]_i_2\
);
\opt_has_pipe.first_q[15]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(14),
I1 => reg_s_phase_fifo_din(14),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(14),
O => \n_0_opt_has_pipe.first_q[15]_i_3\
);
\opt_has_pipe.first_q[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(13),
I1 => reg_s_phase_fifo_din(13),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(13),
O => \n_0_opt_has_pipe.first_q[15]_i_4\
);
\opt_has_pipe.first_q[15]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(12),
I1 => reg_s_phase_fifo_din(12),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(12),
O => \n_0_opt_has_pipe.first_q[15]_i_5\
);
\opt_has_pipe.first_q[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(3),
I1 => reg_s_phase_fifo_din(3),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(3),
O => \n_0_opt_has_pipe.first_q[3]_i_2\
);
\opt_has_pipe.first_q[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(2),
I1 => reg_s_phase_fifo_din(2),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(2),
O => \n_0_opt_has_pipe.first_q[3]_i_3\
);
\opt_has_pipe.first_q[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(1),
I1 => reg_s_phase_fifo_din(1),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(1),
O => \n_0_opt_has_pipe.first_q[3]_i_4\
);
\opt_has_pipe.first_q[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(0),
I1 => reg_s_phase_fifo_din(0),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(0),
O => \n_0_opt_has_pipe.first_q[3]_i_5\
);
\opt_has_pipe.first_q[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(7),
I1 => reg_s_phase_fifo_din(7),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(7),
O => \n_0_opt_has_pipe.first_q[7]_i_2\
);
\opt_has_pipe.first_q[7]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(6),
I1 => reg_s_phase_fifo_din(6),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(6),
O => \n_0_opt_has_pipe.first_q[7]_i_3\
);
\opt_has_pipe.first_q[7]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(5),
I1 => reg_s_phase_fifo_din(5),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(5),
O => \n_0_opt_has_pipe.first_q[7]_i_4\
);
\opt_has_pipe.first_q[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(4),
I1 => reg_s_phase_fifo_din(4),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(4),
O => \n_0_opt_has_pipe.first_q[7]_i_5\
);
\opt_has_pipe.first_q_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_opt_has_pipe.first_q_reg[7]_i_1\,
CO(3) => \n_0_opt_has_pipe.first_q_reg[11]_i_1\,
CO(2) => \n_1_opt_has_pipe.first_q_reg[11]_i_1\,
CO(1) => \n_2_opt_has_pipe.first_q_reg[11]_i_1\,
CO(0) => \n_3_opt_has_pipe.first_q_reg[11]_i_1\,
CYINIT => \<const0>\,
DI(3 downto 0) => L(11 downto 8),
O(3 downto 0) => temp(11 downto 8),
S(3) => \n_0_opt_has_pipe.first_q[11]_i_2\,
S(2) => \n_0_opt_has_pipe.first_q[11]_i_3\,
S(1) => \n_0_opt_has_pipe.first_q[11]_i_4\,
S(0) => \n_0_opt_has_pipe.first_q[11]_i_5\
);
\opt_has_pipe.first_q_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_opt_has_pipe.first_q_reg[11]_i_1\,
CO(3) => \n_0_opt_has_pipe.first_q_reg[15]_i_1\,
CO(2) => \n_1_opt_has_pipe.first_q_reg[15]_i_1\,
CO(1) => \n_2_opt_has_pipe.first_q_reg[15]_i_1\,
CO(0) => \n_3_opt_has_pipe.first_q_reg[15]_i_1\,
CYINIT => \<const0>\,
DI(3 downto 0) => L(15 downto 12),
O(3 downto 0) => temp(15 downto 12),
S(3) => \n_0_opt_has_pipe.first_q[15]_i_2\,
S(2) => \n_0_opt_has_pipe.first_q[15]_i_3\,
S(1) => \n_0_opt_has_pipe.first_q[15]_i_4\,
S(0) => \n_0_opt_has_pipe.first_q[15]_i_5\
);
\opt_has_pipe.first_q_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_opt_has_pipe.first_q_reg[15]_i_1\,
CO(3 downto 1) => \NLW_opt_has_pipe.first_q_reg[16]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => temp(16),
CYINIT => \<const0>\,
DI(3) => \<const0>\,
DI(2) => \<const0>\,
DI(1) => \<const0>\,
DI(0) => \<const0>\,
O(3 downto 0) => \NLW_opt_has_pipe.first_q_reg[16]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \<const0>\,
S(2) => \<const0>\,
S(1) => \<const0>\,
S(0) => \<const1>\
);
\opt_has_pipe.first_q_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \<const0>\,
CO(3) => \n_0_opt_has_pipe.first_q_reg[3]_i_1\,
CO(2) => \n_1_opt_has_pipe.first_q_reg[3]_i_1\,
CO(1) => \n_2_opt_has_pipe.first_q_reg[3]_i_1\,
CO(0) => \n_3_opt_has_pipe.first_q_reg[3]_i_1\,
CYINIT => \<const0>\,
DI(3 downto 0) => L(3 downto 0),
O(3 downto 0) => temp(3 downto 0),
S(3) => \n_0_opt_has_pipe.first_q[3]_i_2\,
S(2) => \n_0_opt_has_pipe.first_q[3]_i_3\,
S(1) => \n_0_opt_has_pipe.first_q[3]_i_4\,
S(0) => \n_0_opt_has_pipe.first_q[3]_i_5\
);
\opt_has_pipe.first_q_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_opt_has_pipe.first_q_reg[3]_i_1\,
CO(3) => \n_0_opt_has_pipe.first_q_reg[7]_i_1\,
CO(2) => \n_1_opt_has_pipe.first_q_reg[7]_i_1\,
CO(1) => \n_2_opt_has_pipe.first_q_reg[7]_i_1\,
CO(0) => \n_3_opt_has_pipe.first_q_reg[7]_i_1\,
CYINIT => \<const0>\,
DI(3 downto 0) => L(7 downto 4),
O(3 downto 0) => temp(7 downto 4),
S(3) => \n_0_opt_has_pipe.first_q[7]_i_2\,
S(2) => \n_0_opt_has_pipe.first_q[7]_i_3\,
S(1) => \n_0_opt_has_pipe.first_q[7]_i_4\,
S(0) => \n_0_opt_has_pipe.first_q[7]_i_5\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsxbip_pipe_v3_0_viv is
port (
m_axis_data_tvalid : out STD_LOGIC;
aclk : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC
);
end ddsxbip_pipe_v3_0_viv;
architecture STRUCTURE of ddsxbip_pipe_v3_0_viv is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal first_q : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of first_q : signal is "true";
signal \n_0_opt_has_pipe.first_q[0]_i_1__0\ : STD_LOGIC;
signal \n_0_opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\ : STD_LOGIC;
signal rdy_stream_i : STD_LOGIC;
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute srl_bus_name : string;
attribute srl_bus_name of \opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\ : label is "\U0/i_synth /\i_has_nd_rdy_pipe.valid_phase_read_del/opt_has_pipe.i_pipe[6].pipe_reg[6] ";
attribute srl_name : string;
attribute srl_name of \opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\ : label is "\U0/i_synth /\i_has_nd_rdy_pipe.valid_phase_read_del/opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5 ";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
m_axis_data_tvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axis_phase_tvalid,
I1 => rdy_stream_i,
O => m_axis_data_tvalid
);
\opt_has_pipe.first_q[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axis_phase_tvalid,
I1 => first_q,
O => \n_0_opt_has_pipe.first_q[0]_i_1__0\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \n_0_opt_has_pipe.first_q[0]_i_1__0\,
Q => first_q,
R => \<const0>\
);
\opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \<const0>\,
A1 => \<const0>\,
A2 => \<const1>\,
A3 => \<const0>\,
CE => s_axis_phase_tvalid,
CLK => aclk,
D => first_q,
Q => \n_0_opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\
);
\opt_has_pipe.i_pipe[7].pipe_reg[7][0]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \n_0_opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\,
Q => rdy_stream_i,
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsxbip_pipe_v3_0_viv_0 is
port (
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ddsxbip_pipe_v3_0_viv_0 : entity is "xbip_pipe_v3_0_viv";
end ddsxbip_pipe_v3_0_viv_0;
architecture STRUCTURE of ddsxbip_pipe_v3_0_viv_0 is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of first_q : signal is "true";
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \<const0>\,
Q => first_q,
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized0\ is
port (
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized0\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized0\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal first_q : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of first_q : signal is "true";
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \<const1>\,
Q => first_q,
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized12\ is
port (
invert_sin : out STD_LOGIC;
O1 : out STD_LOGIC;
O2 : out STD_LOGIC;
O3 : out STD_LOGIC;
O4 : out STD_LOGIC;
O5 : out STD_LOGIC;
O6 : out STD_LOGIC;
O7 : out STD_LOGIC;
O8 : out STD_LOGIC;
O9 : out STD_LOGIC;
O10 : out STD_LOGIC;
O11 : out STD_LOGIC;
O12 : out STD_LOGIC;
O13 : out STD_LOGIC;
O14 : out STD_LOGIC;
O15 : out STD_LOGIC;
O16 : out STD_LOGIC;
O17 : out STD_LOGIC;
O18 : out STD_LOGIC;
O19 : out STD_LOGIC;
O20 : out STD_LOGIC;
O21 : out STD_LOGIC;
O22 : out STD_LOGIC;
O23 : out STD_LOGIC;
O24 : out STD_LOGIC;
O25 : out STD_LOGIC;
O26 : out STD_LOGIC;
O27 : out STD_LOGIC;
O28 : out STD_LOGIC;
O29 : out STD_LOGIC;
O30 : out STD_LOGIC;
O31 : out STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 14 downto 0 );
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\ : in STD_LOGIC_VECTOR ( 14 downto 0 );
L : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized12\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized12\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized12\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^o18\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^invert_sin\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[8]_i_2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[8]_i_2__0\ : STD_LOGIC;
signal \n_0_opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[0]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[0]_i_1__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[1]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[1]_i_1__0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[1]_i_1__1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[1]_i_1__2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[2]_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[2]_i_1__1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[2]_i_1__2\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[3]_i_1__1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[3]_i_1__4\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[4]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[4]_i_1__2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[5]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[5]_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[5]_i_1__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[5]_i_1__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[6]_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[6]_i_1__2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[7]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[7]_i_1__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[8]_i_1\ : label is "soft_lutpair0";
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute srl_bus_name : string;
attribute srl_bus_name of \opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\ : label is "\U0/i_synth /\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3] ";
attribute srl_name : string;
attribute srl_name of \opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\ : label is "\U0/i_synth /\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2 ";
attribute srl_bus_name of \opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\ : label is "\U0/i_synth /\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3] ";
attribute srl_name of \opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\ : label is "\U0/i_synth /\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2 ";
begin
O18 <= \^o18\;
invert_sin <= \^invert_sin\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\opt_has_pipe.first_q[0]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(8),
O => O7
);
\opt_has_pipe.first_q[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(8),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O24
);
\opt_has_pipe.first_q[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(9),
O => O6
);
\opt_has_pipe.first_q[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \out\(1),
I1 => \out\(0),
I2 => \^invert_sin\,
O => O14
);
\opt_has_pipe.first_q[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"D728"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0),
I1 => \^invert_sin\,
I2 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I3 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1),
O => O23
);
\opt_has_pipe.first_q[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(9),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O25
);
\opt_has_pipe.first_q[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(10),
O => O5
);
\opt_has_pipe.first_q[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1EF0"
)
port map (
I0 => \out\(0),
I1 => \out\(1),
I2 => \out\(2),
I3 => \^invert_sin\,
O => O12
);
\opt_has_pipe.first_q[2]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F11F0EE0"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1),
I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0),
I2 => \^invert_sin\,
I3 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I4 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(2),
O => O15
);
\opt_has_pipe.first_q[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(10),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O26
);
\opt_has_pipe.first_q[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(11),
O => O4
);
\opt_has_pipe.first_q[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0101FF00FEFE00"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0),
I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1),
I2 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(2),
I3 => \^invert_sin\,
I4 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(3),
O => O16
);
\opt_has_pipe.first_q[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(11),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O27
);
\opt_has_pipe.first_q[3]_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FEFF00"
)
port map (
I0 => \out\(1),
I1 => \out\(0),
I2 => \out\(2),
I3 => \out\(3),
I4 => \^invert_sin\,
O => O31
);
\opt_has_pipe.first_q[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(12),
O => O3
);
\opt_has_pipe.first_q[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001FFFFFFFE0000"
)
port map (
I0 => \out\(1),
I1 => \out\(0),
I2 => \out\(2),
I3 => \out\(3),
I4 => \^invert_sin\,
I5 => \out\(4),
O => O13
);
\opt_has_pipe.first_q[4]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001FFFFFFFE0000"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(3),
I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(2),
I2 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1),
I3 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0),
I4 => \^o18\,
I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4),
O => O17
);
\opt_has_pipe.first_q[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(12),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O28
);
\opt_has_pipe.first_q[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(13),
O => O2
);
\opt_has_pipe.first_q[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_0_opt_has_pipe.first_q[8]_i_2\,
I1 => \out\(5),
I2 => \^invert_sin\,
O => O11
);
\opt_has_pipe.first_q[5]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D11D2EE2"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4),
I1 => \n_0_opt_has_pipe.first_q[8]_i_2__0\,
I2 => \^invert_sin\,
I3 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I4 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5),
O => O19
);
\opt_has_pipe.first_q[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(13),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O29
);
\opt_has_pipe.first_q[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(14),
O => O1
);
\opt_has_pipe.first_q[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"4B78"
)
port map (
I0 => \out\(5),
I1 => \n_0_opt_has_pipe.first_q[8]_i_2\,
I2 => \out\(6),
I3 => \^invert_sin\,
O => O10
);
\opt_has_pipe.first_q[6]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DF0101DF20FEFE20"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5),
I1 => \n_0_opt_has_pipe.first_q[8]_i_2__0\,
I2 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4),
I3 => \^invert_sin\,
I4 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(6),
O => O20
);
\opt_has_pipe.first_q[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(14),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O30
);
\opt_has_pipe.first_q[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FB7F80"
)
port map (
I0 => \out\(6),
I1 => \n_0_opt_has_pipe.first_q[8]_i_2\,
I2 => \out\(5),
I3 => \out\(7),
I4 => \^invert_sin\,
O => O8
);
\opt_has_pipe.first_q[7]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001F7FFFFFE0800"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(6),
I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4),
I2 => \n_0_opt_has_pipe.first_q[8]_i_2__0\,
I3 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5),
I4 => \^o18\,
I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(7),
O => O21
);
\opt_has_pipe.first_q[7]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
O => \^o18\
);
\opt_has_pipe.first_q[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00048000"
)
port map (
I0 => \out\(6),
I1 => \n_0_opt_has_pipe.first_q[8]_i_2\,
I2 => \out\(5),
I3 => \out\(7),
I4 => \^invert_sin\,
O => O9
);
\opt_has_pipe.first_q[8]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000080000010000"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(6),
I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4),
I2 => \n_0_opt_has_pipe.first_q[8]_i_2__0\,
I3 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5),
I4 => \^o18\,
I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(7),
O => O22
);
\opt_has_pipe.first_q[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \out\(3),
I1 => \out\(2),
I2 => \out\(0),
I3 => \out\(1),
I4 => \out\(4),
I5 => \^invert_sin\,
O => \n_0_opt_has_pipe.first_q[8]_i_2\
);
\opt_has_pipe.first_q[8]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFEFF"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0),
I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1),
I2 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(2),
I3 => \^invert_sin\,
I4 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(3),
O => \n_0_opt_has_pipe.first_q[8]_i_2__0\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => L(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => L(1),
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \<const1>\,
A1 => \<const0>\,
A2 => \<const0>\,
A3 => \<const0>\,
CE => s_axis_phase_tvalid,
CLK => aclk,
D => first_q(0),
Q => \n_0_opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\
);
\opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \<const1>\,
A1 => \<const0>\,
A2 => \<const0>\,
A3 => \<const0>\,
CE => s_axis_phase_tvalid,
CLK => aclk,
D => first_q(1),
Q => \n_0_opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\
);
\opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \n_0_opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\,
Q => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
R => \<const0>\
);
\opt_has_pipe.i_pipe[4].pipe_reg[4][1]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \n_0_opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\,
Q => \^invert_sin\,
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized14\ is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized14\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => m_axis_data_tdata(7)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => m_axis_data_tdata(6)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => m_axis_data_tdata(5)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => m_axis_data_tdata(4)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => m_axis_data_tdata(3)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => m_axis_data_tdata(2)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => m_axis_data_tdata(1)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => m_axis_data_tdata(0)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(1),
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(2),
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(3),
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(4),
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(5),
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(6),
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(7),
Q => first_q(7),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized14_1\ is
port (
O1 : out STD_LOGIC;
O2 : out STD_LOGIC;
O3 : out STD_LOGIC;
O4 : out STD_LOGIC;
O5 : out STD_LOGIC;
O6 : out STD_LOGIC;
O7 : out STD_LOGIC;
O8 : out STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_phase_tvalid : in STD_LOGIC;
I1 : in STD_LOGIC;
aclk : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
I5 : in STD_LOGIC;
I6 : in STD_LOGIC;
I7 : in STD_LOGIC;
I8 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_1\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized14_1\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_1\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \n_0_opt_has_pipe.first_q[7]_i_2__0\ : STD_LOGIC;
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\opt_has_pipe.first_q[0]_i_1__4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(0),
I1 => \out\(0),
O => O8
);
\opt_has_pipe.first_q[1]_i_1__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => first_q(1),
I1 => first_q(0),
I2 => \out\(0),
O => O1
);
\opt_has_pipe.first_q[2]_i_1__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => first_q(2),
I1 => \out\(0),
I2 => first_q(0),
I3 => first_q(1),
O => O2
);
\opt_has_pipe.first_q[3]_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => first_q(1),
I1 => first_q(0),
I2 => \out\(0),
I3 => first_q(2),
I4 => first_q(3),
O => O3
);
\opt_has_pipe.first_q[4]_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => first_q(4),
I1 => first_q(1),
I2 => first_q(0),
I3 => \out\(0),
I4 => first_q(2),
I5 => first_q(3),
O => O4
);
\opt_has_pipe.first_q[5]_i_1__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => first_q(5),
I1 => \n_0_opt_has_pipe.first_q[7]_i_2__0\,
I2 => first_q(4),
O => O5
);
\opt_has_pipe.first_q[6]_i_1__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => first_q(6),
I1 => first_q(4),
I2 => \n_0_opt_has_pipe.first_q[7]_i_2__0\,
I3 => first_q(5),
O => O6
);
\opt_has_pipe.first_q[7]_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => first_q(7),
I1 => first_q(5),
I2 => \n_0_opt_has_pipe.first_q[7]_i_2__0\,
I3 => first_q(4),
I4 => first_q(6),
O => O7
);
\opt_has_pipe.first_q[7]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => first_q(3),
I1 => first_q(2),
I2 => \out\(0),
I3 => first_q(0),
I4 => first_q(1),
O => \n_0_opt_has_pipe.first_q[7]_i_2__0\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I8,
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I7,
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I6,
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I5,
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I4,
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I3,
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I2,
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1,
Q => first_q(7),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized14_2\ is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
I1 : in STD_LOGIC;
aclk : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
I5 : in STD_LOGIC;
I6 : in STD_LOGIC;
I7 : in STD_LOGIC;
I8 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_2\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized14_2\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_2\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => m_axis_data_tdata(7)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => m_axis_data_tdata(6)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => m_axis_data_tdata(5)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => m_axis_data_tdata(4)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => m_axis_data_tdata(3)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => m_axis_data_tdata(2)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => m_axis_data_tdata(1)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => m_axis_data_tdata(0)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I8,
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I7,
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I6,
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I5,
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I4,
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I3,
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I2,
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1,
Q => first_q(7),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized14_3\ is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_3\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized14_3\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_3\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => m_axis_data_tdata(7)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => m_axis_data_tdata(6)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => m_axis_data_tdata(5)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => m_axis_data_tdata(4)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => m_axis_data_tdata(3)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => m_axis_data_tdata(2)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => m_axis_data_tdata(1)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => m_axis_data_tdata(0)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(1),
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(2),
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(3),
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(4),
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(5),
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(6),
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(7),
Q => first_q(7),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized14_4\ is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
I1 : in STD_LOGIC;
aclk : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
I5 : in STD_LOGIC;
I6 : in STD_LOGIC;
I7 : in STD_LOGIC;
I8 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_4\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized14_4\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_4\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => m_axis_data_tdata(7)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => m_axis_data_tdata(6)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => m_axis_data_tdata(5)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => m_axis_data_tdata(4)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => m_axis_data_tdata(3)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => m_axis_data_tdata(2)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => m_axis_data_tdata(1)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => m_axis_data_tdata(0)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I8,
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I7,
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I6,
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I5,
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I4,
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I3,
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I2,
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1,
Q => first_q(7),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized14_6\ is
port (
O1 : out STD_LOGIC;
O2 : out STD_LOGIC;
O3 : out STD_LOGIC;
O4 : out STD_LOGIC;
O5 : out STD_LOGIC;
O6 : out STD_LOGIC;
O7 : out STD_LOGIC;
O8 : out STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_phase_tvalid : in STD_LOGIC;
I1 : in STD_LOGIC;
aclk : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
I5 : in STD_LOGIC;
I6 : in STD_LOGIC;
I7 : in STD_LOGIC;
invert_sin : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_6\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized14_6\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_6\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \n_0_opt_has_pipe.first_q[7]_i_2\ : STD_LOGIC;
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\opt_has_pipe.first_q[0]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(0),
I1 => \out\(0),
O => O8
);
\opt_has_pipe.first_q[1]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => first_q(1),
I1 => first_q(0),
I2 => \out\(0),
O => O1
);
\opt_has_pipe.first_q[2]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => first_q(2),
I1 => \out\(0),
I2 => first_q(0),
I3 => first_q(1),
O => O2
);
\opt_has_pipe.first_q[3]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => first_q(1),
I1 => first_q(0),
I2 => \out\(0),
I3 => first_q(2),
I4 => first_q(3),
O => O3
);
\opt_has_pipe.first_q[4]_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => first_q(4),
I1 => first_q(1),
I2 => first_q(0),
I3 => \out\(0),
I4 => first_q(2),
I5 => first_q(3),
O => O4
);
\opt_has_pipe.first_q[5]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => first_q(5),
I1 => \n_0_opt_has_pipe.first_q[7]_i_2\,
I2 => first_q(4),
O => O5
);
\opt_has_pipe.first_q[6]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => first_q(6),
I1 => first_q(4),
I2 => \n_0_opt_has_pipe.first_q[7]_i_2\,
I3 => first_q(5),
O => O6
);
\opt_has_pipe.first_q[7]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => first_q(7),
I1 => first_q(5),
I2 => \n_0_opt_has_pipe.first_q[7]_i_2\,
I3 => first_q(4),
I4 => first_q(6),
O => O7
);
\opt_has_pipe.first_q[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => first_q(3),
I1 => first_q(2),
I2 => \out\(0),
I3 => first_q(0),
I4 => first_q(1),
O => \n_0_opt_has_pipe.first_q[7]_i_2\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I7,
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I6,
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I5,
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I4,
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I3,
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I2,
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1,
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => invert_sin,
Q => first_q(7),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized16\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
I1 : in STD_LOGIC;
aclk : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
I5 : in STD_LOGIC;
I6 : in STD_LOGIC;
I7 : in STD_LOGIC;
I8 : in STD_LOGIC;
DOBDO : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized16\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized16\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized16\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[8]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(8),
O => \out\(8)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => \out\(7)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => \out\(6)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => \out\(5)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => \out\(4)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => \out\(3)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => \out\(2)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => \out\(1)
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => \out\(0)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => DOBDO(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I8,
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I7,
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I6,
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I5,
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I4,
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I3,
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I2,
Q => first_q(7),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1,
Q => first_q(8),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized16_5\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
I1 : in STD_LOGIC;
aclk : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
I5 : in STD_LOGIC;
I6 : in STD_LOGIC;
I7 : in STD_LOGIC;
I8 : in STD_LOGIC;
I9 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized16_5\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized16_5\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized16_5\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[8]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(8),
O => \out\(8)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => \out\(7)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => \out\(6)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => \out\(5)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => \out\(4)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => \out\(3)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => \out\(2)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => \out\(1)
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => \out\(0)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I9(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I8,
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I7,
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I6,
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I5,
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I4,
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I3,
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I2,
Q => first_q(7),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1,
Q => first_q(8),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized2\ is
port (
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
mutant_x_op : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized2\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized2\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized2\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of first_q : signal is "true";
signal \n_0_opt_has_pipe.first_q[0]_i_1\ : STD_LOGIC;
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\opt_has_pipe.first_q[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => mutant_x_op(1),
I1 => mutant_x_op(0),
I2 => mutant_x_op(2),
O => \n_0_opt_has_pipe.first_q[0]_i_1\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \n_0_opt_has_pipe.first_q[0]_i_1\,
Q => first_q,
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized8\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
I1 : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
temp : in STD_LOGIC_VECTOR ( 16 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized8\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized8\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized8\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 16 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[10]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[11]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[12]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[13]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[14]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[15]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[16]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[8]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[9]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(15),
O => \out\(15)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(14),
O => \out\(14)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => \out\(5)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => \out\(4)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => \out\(3)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => \out\(2)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => \out\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => \out\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(13),
O => \out\(13)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(12),
O => \out\(12)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(11),
O => \out\(11)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(10),
O => \out\(10)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(9),
O => \out\(9)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(8),
O => \out\(8)
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => \out\(7)
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => \out\(6)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(0),
O => I1(0)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(10),
O => I1(10)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(11),
O => I1(11)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(12),
O => I1(12)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(13),
O => I1(13)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(1),
O => I1(1)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(2),
O => I1(2)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(3),
O => I1(3)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(4),
O => I1(4)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(5),
O => I1(5)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(6),
O => I1(6)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(7),
O => I1(7)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(8),
O => I1(8)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(9),
O => I1(9)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(0),
I1 => first_q(14),
O => D(0)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(10),
I1 => first_q(14),
O => D(10)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(11),
I1 => first_q(14),
O => D(11)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(12),
I1 => first_q(14),
O => D(12)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(13),
I1 => first_q(14),
O => D(13)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(1),
I1 => first_q(14),
O => D(1)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(2),
I1 => first_q(14),
O => D(2)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(3),
I1 => first_q(14),
O => D(3)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(4),
I1 => first_q(14),
O => D(4)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(5),
I1 => first_q(14),
O => D(5)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(6),
I1 => first_q(14),
O => D(6)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(7),
I1 => first_q(14),
O => D(7)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(8),
I1 => first_q(14),
O => D(8)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(9),
I1 => first_q(14),
O => D(9)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(10),
Q => first_q(10),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(11),
Q => first_q(11),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(12),
Q => first_q(12),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(13),
Q => first_q(13),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(14),
Q => first_q(14),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(15),
Q => first_q(15),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(16),
Q => first_q(16),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(1),
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(2),
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(3),
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(4),
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(5),
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(6),
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(7),
Q => first_q(7),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(8),
Q => first_q(8),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(9),
Q => first_q(9),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsaccum is
port (
L : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
I1 : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
reg_s_phase_fifo_din : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
end ddsaccum;
architecture STRUCTURE of ddsaccum is
signal \^l\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal acc_phase_shaped : STD_LOGIC_VECTOR ( 13 downto 0 );
signal temp : STD_LOGIC_VECTOR ( 16 downto 0 );
begin
L(1 downto 0) <= \^l\(1 downto 0);
\i_fabric.i_common.i_phase_acc\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized8\
port map (
D(13 downto 0) => D(13 downto 0),
I1(13 downto 0) => I1(13 downto 0),
aclk => aclk,
\out\(15 downto 14) => \^l\(1 downto 0),
\out\(13 downto 0) => acc_phase_shaped(13 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid,
temp(16 downto 0) => temp(16 downto 0)
);
\i_fabric.i_one_channel.i_accum\: entity work.\ddspipe_add__parameterized0\
port map (
L(15 downto 14) => \^l\(1 downto 0),
L(13 downto 0) => acc_phase_shaped(13 downto 0),
reg_s_phase_fifo_din(15 downto 0) => reg_s_phase_fifo_din(15 downto 0),
s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid,
temp(16 downto 0) => temp(16 downto 0)
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsdds_compiler_v6_0_rdy is
port (
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC
);
end ddsdds_compiler_v6_0_rdy;
architecture STRUCTURE of ddsdds_compiler_v6_0_rdy is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal mutant_x_op : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \n_0_mutant_x_op[0]_i_1\ : STD_LOGIC;
signal \n_0_mutant_x_op[1]_i_1\ : STD_LOGIC;
signal \n_0_mutant_x_op[2]_i_1\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \mutant_x_op[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \mutant_x_op[2]_i_1\ : label is "soft_lutpair12";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\i_single_channel.i_non_trivial_lat.i_rdy\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized2\
port map (
aclk => aclk,
mutant_x_op(2 downto 0) => mutant_x_op(2 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\mutant_x_op[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5A58"
)
port map (
I0 => s_axis_phase_tvalid,
I1 => mutant_x_op(2),
I2 => mutant_x_op(0),
I3 => mutant_x_op(1),
O => \n_0_mutant_x_op[0]_i_1\
);
\mutant_x_op[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F508"
)
port map (
I0 => s_axis_phase_tvalid,
I1 => mutant_x_op(2),
I2 => mutant_x_op(0),
I3 => mutant_x_op(1),
O => \n_0_mutant_x_op[1]_i_1\
);
\mutant_x_op[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCC4"
)
port map (
I0 => s_axis_phase_tvalid,
I1 => mutant_x_op(2),
I2 => mutant_x_op(0),
I3 => mutant_x_op(1),
O => \n_0_mutant_x_op[2]_i_1\
);
\mutant_x_op_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \n_0_mutant_x_op[0]_i_1\,
Q => mutant_x_op(0),
R => \<const0>\
);
\mutant_x_op_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => \<const1>\,
D => \n_0_mutant_x_op[1]_i_1\,
Q => mutant_x_op(1),
R => \<const0>\
);
\mutant_x_op_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => \<const1>\,
D => \n_0_mutant_x_op[2]_i_1\,
Q => mutant_x_op(2),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddssin_cos__parameterized0\ is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
L : in STD_LOGIC_VECTOR ( 1 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddssin_cos__parameterized0\ : entity is "sin_cos";
end \ddssin_cos__parameterized0\;
architecture STRUCTURE of \ddssin_cos__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal cos_addr : STD_LOGIC_VECTOR ( 13 downto 0 );
signal cos_ls1 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\ : STD_LOGIC_VECTOR ( 14 downto 0 );
signal \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal invert_sin : STD_LOGIC;
signal mod_cos_addr : STD_LOGIC_VECTOR ( 13 downto 0 );
signal mod_sin_addr : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \n_0_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_0_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_10_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_11_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_12_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_13_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_14_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_15_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_16_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_17_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_18_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_19_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_1_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_1_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_1_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_20_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_21_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_22_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_23_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_24_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_25_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_26_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_27_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_28_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_29_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_2_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_2_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_2_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_30_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_31_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_3_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_3_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_3_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_4_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_4_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_4_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_5_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_5_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_5_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_6_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_6_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_6_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_7_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_7_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_7_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_8_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_9_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 6 downto 0 );
signal sin_addr : STD_LOGIC_VECTOR ( 13 downto 0 );
signal sin_ls1 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is "";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is 16383;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is 1;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is 2;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is 3;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is 4;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is 5;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is 6;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is 7;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is 8;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is 9;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is 10;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is 11;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is 12;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is 13;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is 14;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is 15;
attribute use_sync_reset : string;
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[0]\ : label is "no";
attribute use_sync_set : string;
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[0]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[10]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[10]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[11]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[11]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[12]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[12]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[13]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[13]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[1]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[1]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[2]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[2]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[3]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[3]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[4]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[4]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[5]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[5]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[6]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[6]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[7]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[7]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[8]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[8]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[9]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[9]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[0]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[0]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[10]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[10]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[11]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[11]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[12]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[12]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[13]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[13]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[1]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[1]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[2]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[2]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[3]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[3]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[4]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[4]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[5]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[5]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[6]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[6]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[7]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[7]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[8]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[8]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[9]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[9]\ : label is "no";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\i_rtl.i_quarter_table.i_addr_reg_c\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized12\
port map (
L(1 downto 0) => L(1 downto 0),
O1 => \n_1_i_rtl.i_quarter_table.i_addr_reg_c\,
O10 => \n_10_i_rtl.i_quarter_table.i_addr_reg_c\,
O11 => \n_11_i_rtl.i_quarter_table.i_addr_reg_c\,
O12 => \n_12_i_rtl.i_quarter_table.i_addr_reg_c\,
O13 => \n_13_i_rtl.i_quarter_table.i_addr_reg_c\,
O14 => \n_14_i_rtl.i_quarter_table.i_addr_reg_c\,
O15 => \n_15_i_rtl.i_quarter_table.i_addr_reg_c\,
O16 => \n_16_i_rtl.i_quarter_table.i_addr_reg_c\,
O17 => \n_17_i_rtl.i_quarter_table.i_addr_reg_c\,
O18 => \n_18_i_rtl.i_quarter_table.i_addr_reg_c\,
O19 => \n_19_i_rtl.i_quarter_table.i_addr_reg_c\,
O2 => \n_2_i_rtl.i_quarter_table.i_addr_reg_c\,
O20 => \n_20_i_rtl.i_quarter_table.i_addr_reg_c\,
O21 => \n_21_i_rtl.i_quarter_table.i_addr_reg_c\,
O22 => \n_22_i_rtl.i_quarter_table.i_addr_reg_c\,
O23 => \n_23_i_rtl.i_quarter_table.i_addr_reg_c\,
O24 => \n_24_i_rtl.i_quarter_table.i_addr_reg_c\,
O25 => \n_25_i_rtl.i_quarter_table.i_addr_reg_c\,
O26 => \n_26_i_rtl.i_quarter_table.i_addr_reg_c\,
O27 => \n_27_i_rtl.i_quarter_table.i_addr_reg_c\,
O28 => \n_28_i_rtl.i_quarter_table.i_addr_reg_c\,
O29 => \n_29_i_rtl.i_quarter_table.i_addr_reg_c\,
O3 => \n_3_i_rtl.i_quarter_table.i_addr_reg_c\,
O30 => \n_30_i_rtl.i_quarter_table.i_addr_reg_c\,
O31 => \n_31_i_rtl.i_quarter_table.i_addr_reg_c\,
O4 => \n_4_i_rtl.i_quarter_table.i_addr_reg_c\,
O5 => \n_5_i_rtl.i_quarter_table.i_addr_reg_c\,
O6 => \n_6_i_rtl.i_quarter_table.i_addr_reg_c\,
O7 => \n_7_i_rtl.i_quarter_table.i_addr_reg_c\,
O8 => \n_8_i_rtl.i_quarter_table.i_addr_reg_c\,
O9 => \n_9_i_rtl.i_quarter_table.i_addr_reg_c\,
aclk => aclk,
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(14 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(14 downto 0),
invert_sin => invert_sin,
\out\(14 downto 8) => p_0_in(6 downto 0),
\out\(7 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(7 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"5B1BC6C5B1BC6C5B1BC6C5B1BC6C5B1BC6C5B1BC6C6B1B06C6B1B06C6B1B06C6",
INIT_01 => X"F1B16C6F1B16C6F1B16C6C1B1AC6C1B1AC6C1B1AC6C1B1AC6C1B1AC6C1B1BC6C",
INIT_02 => X"1B1AC6C5B1BC6C5B1BC6C5B1BC6C5B1B06C6B1B06C6B1B06C6B1B06C6F1B16C6",
INIT_03 => X"B1AC6C5B1BC6C5B1BC6C6B1B06C6B1B06C6F1B16C6F1B16C6F1B1AC6C1B1AC6C",
INIT_04 => X"16C6F1B16C6C1B1AC6C5B1BC6C5B1B06C6B1B06C6B1B16C6F1B16C6C1B1AC6C1",
INIT_05 => X"6F1B1AC6C1B1BC6C5B1B06C6B1B16C6F1B16C6C1B1AC6C5B1BC6C6B1B06C6B1B",
INIT_06 => X"BC6C6B1B06C6F1B1AC6C1B1BC6C5B1B06C6F1B16C6C1B1AC6C5B1B06C6B1B16C",
INIT_07 => X"B1AC6C5B1B06C6F1B1AC6C1B1BC6C6B1B16C6C1B1AC6C5B1B06C6F1B16C6C1B1",
INIT_08 => X"B16C6C5B1B06C6F1B1AC6C5B1B06C6F1B1AC6C5B1B06C6F1B1AC6C5B1B06C6F1",
INIT_09 => X"6C6C1B1BC6C6F1B1AC6C5B1B16C6C1B1BC6C6F1B1AC6C5B1B16C6C1B1BC6C6B1",
INIT_0A => X"1B16C6C5B1B16C6C1B1B06C6C1B1B06C6F1B1BC6C6B1B1AC6C6B1B16C6C5B1B0",
INIT_0B => X"B1B06C6C1B1B16C6C5B1B16C6C5B1B16C6C5B1B16C6C5B1B16C6C5B1B16C6C5B",
INIT_0C => X"06C6C5B1B1AC6C6F1B1BC6C6C1B1B16C6C5B1B1AC6C6B1B1BC6C6F1B1B06C6C1",
INIT_0D => X"1B1BC6C6C1B1B1AC6C6F1B1B06C6C5B1B1BC6C6C1B1B16C6C6B1B1BC6C6C1B1B",
INIT_0E => X"1B06C6C6F1B1B16C6C6F1B1B16C6C6F1B1B16C6C6F1B1B06C6C6B1B1B06C6C5B",
INIT_0F => X"C6B1B1B16C6C6C1B1B1BC6C6C6B1B1B16C6C6C1B1B1BC6C6C5B1B1B06C6C6B1B",
INIT_10 => X"6F1B1B1BC6C6C6C1B1B1B06C6C6C1B1B1B06C6C6C1B1B1B06C6C6F1B1B1BC6C6",
INIT_11 => X"AC6C6C6C1B1B1B1AC6C6C6C1B1B1B1AC6C6C6F1B1B1B06C6C6C5B1B1B1AC6C6C",
INIT_12 => X"6C6C6C6F1B1B1B1BC6C6C6C6F1B1B1B1BC6C6C6C6B1B1B1B16C6C6C6C1B1B1B1",
INIT_13 => X"1B1B16C6C6C6C6C5B1B1B1B1B06C6C6C6C6B1B1B1B1B06C6C6C6C5B1B1B1B1AC",
INIT_14 => X"6C6C6C6C6C6C1B1B1B1B1B1B06C6C6C6C6C6B1B1B1B1B1B06C6C6C6C6C5B1B1B",
INIT_15 => X"B16C6C6C6C6C6C6C6C6B1B1B1B1B1B1B1B06C6C6C6C6C6C6C5B1B1B1B1B1B1BC",
INIT_16 => X"1B1B1B1B1B1B1B1B1B1B1B1B1AC6C6C6C6C6C6C6C6C6C6C1B1B1B1B1B1B1B1B1",
INIT_17 => X"B1B1B1B1B1B1B1B1B1B1B1B1B1B06C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6F",
INIT_18 => X"B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1",
INIT_19 => X"6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6CB1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1",
INIT_1A => X"B1B1B1B1B1B1B1B1C6C6C6C6C6C6C6C6C6C6DB1B1B1B1B1B1B1B1B1B1B1B1C6C",
INIT_1B => X"6C6C6DB1B1B1B1B1B1C6C6C6C6C6C6C71B1B1B1B1B1B1B6C6C6C6C6C6C6C6CB1",
INIT_1C => X"C6C6C6DB1B1B1B1B6C6C6C6C6DB1B1B1B1B1C6C6C6C6C6DB1B1B1B1B1B6C6C6C",
INIT_1D => X"C6C6CB1B1B1B2C6C6C6CB1B1B1B1C6C6C6C61B1B1B1B6C6C6C6C71B1B1B1B2C6",
INIT_1E => X"6C71B1B186C6C6CB1B1B1C6C6C6DB1B1B1C6C6C6CB1B1B186C6C6C71B1B1B2C6",
INIT_1F => X"B1B1B6C6C6DB1B186C6C61B1B186C6C61B1B186C6C61B1B1B6C6C6DB1B1B2C6C",
INIT_20 => X"1B6C6C71B1B6C6C71B1B6C6C61B1B2C6C6DB1B1C6C6CB1B1B6C6C61B1B1C6C6C",
INIT_21 => X"6C6DB1B2C6C71B186C6DB1B2C6C71B186C6CB1B1C6C6DB1B2C6C61B1B6C6C71B",
INIT_22 => X"CB1B2C6CB1B2C6CB1B2C6CB1B1C6C71B1C6C61B186C6DB1B6C6CB1B2C6C71B18",
INIT_23 => X"1B2C6DB186C61B1C6CB1B2C6DB1B6C61B186C71B1C6C71B1C6CB1B2C6CB1B2C6",
INIT_24 => X"B6C71B2C6DB186CB1B6C61B1C6CB1B6C71B2C6DB186C71B1C6CB1B6C61B1C6CB",
INIT_25 => X"C6DB186CB186CB186C71B6C71B2C61B2C6DB1C6CB186C71B6C61B2C6DB1C6CB1",
INIT_26 => X"6C7186CB186CB186DB1C6DB1C6DB1C6DB1C6DB1C6DB1C6DB1C6DB1C6DB1C6DB1",
INIT_27 => X"2C71B6CB1C6DB2C61B6C7186CB1C6DB2C61B6C7186CB186DB1C61B2C61B2C71B",
INIT_28 => X"B2C7186DB2C71B6CB1C61B6CB1C61B2C7186DB2C61B6CB1C6DB2C71B6CB1C6DB",
INIT_29 => X"6DB6CB1C6186DB2C7186DB6CB1C61B6CB1C6186DB2C7186DB2C7186DB2C7186D",
INIT_2A => X"B1C71861B6DB2CB1C6186DB6CB2C71861B6CB2C71C61B6DB2C71861B6CB2C718",
INIT_2B => X"1861B6DB6DB2CB2C71C7186186DB6CB2CB1C71C6186DB6CB2CB1C71861B6DB2C",
INIT_2C => X"DB6DB6DB6DB2CB2CB2CB2CB1C71C71C71C61861861B6DB6DB6CB2CB2C71C71C6",
INIT_2D => X"2CB2DB6DB6DB6DB6DB6DB6DB6D861861861861861861861861861B6DB6DB6DB6",
INIT_2E => X"CB2CB2DB6DB61861871C71C72CB2CB6DB6DB6D861861861C71C71C72CB2CB2CB",
INIT_2F => X"C71CB2DB6D861C71CB2DB6D861871C72CB6DB61861C71C72CB2DB6D861861C71",
INIT_30 => X"D871CB2DB61871CB2D861C72CB6D861C72CB6D861871CB2DB61871C72CB6D861",
INIT_31 => X"B6D871CB6D871CB6D861CB2D861CB2DB61C72DB61872CB6D871CB2DB61C72CB6",
INIT_32 => X"61CB61872DB61CB6D872CB61C72D861CB6D872CB61872DB61C72D861CB2D861C",
INIT_33 => X"72D872D871CB61CB61872D872DB61CB61872D872CB61CB6D872DB61CB61872D8",
INIT_34 => X"CB61CB61CB61CB61CB61CB61CB61CB61CB2D872D872D872D871CB61CB61CB618",
INIT_35 => X"721CB61CB61CB72D872D872D872D8761CB61CB61CB61CB61CB61CB61CB61CB61",
INIT_36 => X"62D872DCB61C872D8761CB61D872D8721CB61C872D872D8B61CB61C872D872D8",
INIT_37 => X"721CB72D8B61D8721CB62D8761CB72D8B61C872D8B61C872D8B61CB72D8761CB",
INIT_38 => X"CB72DCB72D8B62D8B62D8761D8721C8721CB72D8B62D8761D8721CB72D8B61D8",
INIT_39 => X"62D8B62DCB721C8721D8761D8762D8B62D8B62DCB72DCB72DCB72DCB72DCB72D",
INIT_3A => X"1C8762DC8721D8B62DC8761D8B72DC8761D8B62DC8721D8762D8B72DC8721D87",
INIT_3B => X"D8B762DC8762DC8762DC8762D8B721D8B721D8B721D8B62DC8762DC8721D8B72",
INIT_3C => X"DD8B721DC87621D8B722DC8762DD8B721D8B762DC8762DC8B721D8B721D8B721",
INIT_3D => X"22DC8B722DD8B762DD8B762DD8B762DD8B762DD8B722DC8B721DC87721D88762",
INIT_3E => X"87722DD887722DD887722DC8B7621DC8B722DD887721DC8B762DD887621DC877",
INIT_3F => X"21DC887722DDC8B7722DD88B7621DD887722DDC8B7621DC8B7722DD887722DD8",
INIT_40 => X"C8877622DDC8877622DDC8877622DDC8B77221DD8877622DD88B7722DDC8B772",
INIT_41 => X"B776221DDC88B77622DDD888776221DDC88777221DD888776221DD88B77222DD",
INIT_42 => X"776222DDDC8887776222DDD888B777222DDDC88B777222DDD888B776221DDC88",
INIT_43 => X"7762222DDDD8888B77772222DDDD888877772222DDDD888877762221DDD888B7",
INIT_44 => X"7777622222DDDDDD88888B77777222221DDDDC8888B7777622221DDDD8888B77",
INIT_45 => X"88777777777222222221DDDDDDDC888888877777776222222DDDDDDD88888877",
INIT_46 => X"888888888888888888777777777777777222222222222DDDDDDDDDDD88888888",
INIT_47 => X"DDD2222222222222222222222221DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDC",
INIT_48 => X"77777777777748888888888888888889DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD",
INIT_49 => X"8888DDDDDDDD222222223777777774888888888DDDDDDDDDDD22222222222277",
INIT_4A => X"E2222377777888889DDDDD2222227777778888889DDDDDD22222237777774888",
INIT_4B => X"7748889DDDE222377748889DDDD22223777788889DDDD222237777488889DDDD",
INIT_4C => X"DDDE223774888DDD22237778889DDE2227774888DDDD22237778888DDDE22237",
INIT_4D => X"2377889DDE22774889DD222774889DDE22777888DDD222777888DDD222777888",
INIT_4E => X"889DE2277889DE2277489DD2237788DDE2277488DDE2277488DDE2277488DDE2",
INIT_4F => X"D227788DD227788DD227788DDE237489DE237788DD2237489DE2277889DE2277",
INIT_50 => X"3788DE23788DE23748DD237489D227789DE23748DD227789DE237489DE27788D",
INIT_51 => X"89D22748DE27489D23789DE27489D23788DE27789D22748DD23748DE23788DE2",
INIT_52 => X"DE2749D23789D23789E2748DE2748DE2748DE2748DE2748DE2748DE23789D237",
INIT_53 => X"2378DE3789E2749D2348DE3789E2749D2378DE2749D2378DE2749D23789E2748",
INIT_54 => X"378DE348D2349D2749D2749E2789E2789E2789E2789E2789D2749D2749D2348D",
INIT_55 => X"349E378D2749E378D2749E378D2349E278DE348D2749E278DE348D2749E2789E",
INIT_56 => X"789E349E349E349D278D278D2349E349E278D278DE349E378D278DE349E278D2",
INIT_57 => X"349E34D278D278D278D278D278D278D278D278D278D278D278D278D278D278D2",
INIT_58 => X"278E349E38D279E349E78D278E349E34D278D279E349E349278D278D249E349E",
INIT_59 => X"D249E78D349278E349279E34D279E34D279E34D279E349278E349E78D249E34D",
INIT_5A => X"4D249E79E38E34D249E79E38D349249E78E34D249E78E34D249E78D349279E38",
INIT_5B => X"E79E79E79E78E38E38E34D34D34D249249E79E78E38E34D349249279E78E38D3",
INIT_5C => X"4D34D34D38E38E38E79E79E79E79E79249249249249249249249249249249E79",
INIT_5D => X"934D38E79E4924D34E38E7924924D34E38E79E4924934D34E38E39E79E492492",
INIT_5E => X"E7924D38E7934E39E4934E39E4934E39E4924D38E7924D34E39E4934D38E79E4",
INIT_5F => X"E4938E4938E4934E7934E3924E39E4D38E4938E7924E39E4D38E7934E39E4938",
INIT_60 => X"E7938E4939E4E3934E7938E4D39E4E3924E7934E7934E4938E4938E4938E4938",
INIT_61 => X"924E4D3934E4E3938E4E3938E4E3938E4D3934E4D3924E4939E4E3934E493924",
INIT_62 => X"393924E4E793938E4E4D3939E4E4D3939E4E4D3938E4E493934E4E3939E4E493",
INIT_63 => X"9393924E4E4E4939393924E4E4E79393934E4E4E79393924E4E49393934E4E49",
INIT_64 => X"E4E4E4E4E4E4E4D39393939393939E4E4E4E4E4E493939393938E4E4E4E4E393",
INIT_65 => X"393939393939393939393939393939393939393939393939393939393924E4E4",
INIT_66 => X"39393939394E4E4E4E4E4E93939393939393A4E4E4E4E4E4E4E4E4E4E9393939",
INIT_67 => X"E4E4E939393E4E4E4F939393E4E4E4E93939394E4E4E4E93939393A4E4E4E4E5",
INIT_68 => X"4E9393E4E4F9390E4E439390E4E439390E4E4F9393E4E4E539390E4E4E939390",
INIT_69 => X"E4E9394E4393A4E5393E4E9390E4E9390E4E9390E4E9393E4E5393A4E439394E",
INIT_6A => X"390E4390E4F93E4F93E4E93A4E9394E5390E4F93E4E9394E5390E4F93A4E5390",
INIT_6B => X"394E93A4F90E4394E93A4F93E4390E5394E93A4E93E4F93E4F93E4390E4390E4",
INIT_6C => X"E93E43A4F90E53E4394E93E53A4F90E53A4F90E53A4F90E53A4F90E53A4F93E4",
INIT_6D => X"93E53E53A43A4394F94E90E93E53A43A4F94E90E53E53A4394E90E53E43A4F90",
INIT_6E => X"F94F94F94F943A43A43A43A43A43A43A43A43A43A4394F94F94F94F90E90E90E",
INIT_6F => X"3E90F94FA43E53E90E94F943A43E53E90E90F94F943A43A53E53E50E90E90E94",
INIT_70 => X"0E943A53E94FA53E90F943E50E94FA53E90F943A53E90F943A53E90E94FA43E5",
INIT_71 => X"FA50E943E94FA50F943E94FA50E943E50FA43E94FA53E943A50E943A50E943A5",
INIT_72 => X"943E943E943E943E943A50FA50FA50FA50F943E943E943A50FA50F943E943E50",
INIT_73 => X"FA50FE943E940FA50FA50FE943E943E950FA50FA50FA50FA543E943E943E943E",
INIT_74 => X"3EA50FE940FA543EA50FE943FA503E940FA503E940FA503E943FA50FA943E950",
INIT_75 => X"FE9503EA503EA543FA543FA543FA543FA543FA503EA503E950FE950FA943FA54",
INIT_76 => X"A540FEA540FA9503FA940FEA503FA940FEA503FA940FE9503EA543FA940FA950",
INIT_77 => X"0FFA9503FAA540FEA5403FA9503FA9503FA9503FA9503FA9503FA9503FA9503F",
INIT_78 => X"540FFAA5403FAA5503FEA5503FEA5503FEA5503FEA5403FA9540FEA9503FEA54",
INIT_79 => X"5403FFAA5500FFEA95403FEA95403FEA95403FEA95403FEA9500FFAA5503FEA9",
INIT_7A => X"00FFEAA955003FFAA95400FFEAA55403FFAA95500FFEA95500FFEA95500FFAA9",
INIT_7B => X"AAA9554003FFFAAA555000FFFAAA554003FFEAA955000FFEAA955003FFEAA554",
INIT_7C => X"03FFFEAAA955550000FFFEAAA95554000FFFEAAA95550003FFFAAA5554000FFF",
INIT_7D => X"0000FFFFFFAAAAAA55555400000FFFFFEAAAA95555400003FFFFAAAA95555000",
INIT_7E => X"3FFFFFFFFFFFAAAAAAAAAA955555555400000000FFFFFFFEAAAAAAA555555400",
INIT_7F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555500000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(1 downto 0),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1 downto 0),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"394E53A4E93A4F93E4F90E4390E5394E53A4E93A4F93E4390E4394E5394E93A4",
INIT_01 => X"3E4390E4394E5394E93A4F93E4F90E4390E5394E53A4E93A4F93E4F90E4390E5",
INIT_02 => X"4E93A4F93E4F90E4390E5394E53A4E93E4F93E4390E4394E5394E93A4E93E4F9",
INIT_03 => X"4390E5394E53A4E93A4F93E4390E4394E5394E93A4E93E4F93E4390E5394E53A",
INIT_04 => X"93A4E93E4F90E4390E5394E53A4E93E4F93E4390E4394E5394E93A4F93E4F90E",
INIT_05 => X"93E4390E5394E53A4E93E4F93E4390E4394E53A4E93A4F93E4F90E4394E5394E",
INIT_06 => X"90E5394E93A4E93E4F90E4390E5394E93A4E93E4F90E4390E5394E93A4E93E4F",
INIT_07 => X"94E53A4E93E4F93E4390E5394E53A4E93E4F90E4390E5394E93A4E93E4F90E43",
INIT_08 => X"94E53A4E93E4F93E4390E5394E93A4E93E4F90E4394E5394E93A4F93E4390E43",
INIT_09 => X"90E5394E53A4E93E4F90E4394E53A4E93A4F93E4390E5394E93A4F93E4F90E43",
INIT_0A => X"93E4F90E4394E53A4E93E4F90E4394E5394E93A4F93E4390E5394E93A4F93E43",
INIT_0B => X"4394E53A4E93E4F90E4394E53A4E93E4F90E4394E53A4E93E4F90E4394E53A4E",
INIT_0C => X"4E53A4E93E4F90E4394E53A4F93E4390E5394E93A4F93E4390E5394E93E4F90E",
INIT_0D => X"394E53A4F93E4390E5394E93E4F90E4394E53A4F93E4390E5394E93A4F90E439",
INIT_0E => X"E4390E5394E93E4F90E4394E93A4F93E4394E53A4E93E4390E5394E93E4F90E4",
INIT_0F => X"5394E93E4F90E5394E93A4F90E4394E93A4F90E4394E53A4F93E4394E53A4E93",
INIT_10 => X"394E93E4F90E53A4E93E4390E53A4E93E4390E53A4E93E4390E5394E93E4F90E",
INIT_11 => X"90E53A4F93E4394E53A4F90E4394E93A4F90E4394E93E4F90E5394E93E4F90E5",
INIT_12 => X"3A4F90E4394E93E4F90E53A4E93E4394E53A4F90E4394E93E4F90E53A4E93E43",
INIT_13 => X"93E4390E53A4F90E4394E93E4390E53A4F93E4394E93E4F90E53A4E93E4394E5",
INIT_14 => X"E53A4F90E53A4E93E4394E93E4F90E53A4F93E4394E93E4390E53A4F90E4394E",
INIT_15 => X"3E4F90E53A4F90E53A4E93E4394E93E4394E53A4F90E53A4F93E4394E93E4390",
INIT_16 => X"4E93E4394E93E4394E93E4394E53A4F90E53A4F90E53A4F93E4394E93E4394E9",
INIT_17 => X"4394E93E4394E93E4394E93E4394E53A4F90E53A4F90E53A4F90E53A4F90E539",
INIT_18 => X"4394E93E4394E93E4394E93E4394E93E4394E93E4394E93E4394E93E4394E93E",
INIT_19 => X"4F90E53A4F90E53A4F90E53A4F90E53A4394E93E4394E93E4394E93E4394E93E",
INIT_1A => X"3E4394E93E4394E90E53A4F90E53A4F90E53A4394E93E4394E93E4394E93E53A",
INIT_1B => X"E53A4F94E93E4394E90E53A4F90E53A4394E93E4394E93E53A4F90E53A4F90E9",
INIT_1C => X"53A4F90E93E4394E90E53A4F90E93E4394E90E53A4F90E53E4394E93E43A4F90",
INIT_1D => X"F90E53E4394E90E53A4F94E93E43A4F90E53E4394E93E53A4F90E93E4394E90E",
INIT_1E => X"4F94E93E53A4F90E93E43A4F90E53E4394F90E53A4394E90E53A4F94E93E43A4",
INIT_1F => X"94E93E53A4F94E90E53A4394E90E53A4394E90E53A4394E93E53A4F94E93E53A",
INIT_20 => X"E43A4F94E93E53A4394E90E53E4394F90E53E43A4F90E93E43A4F94E93E53A4F",
INIT_21 => X"E53A4394F90E93E53A4F94E90E53E43A4F90E93E53A4F94E90E53E4394F90E93",
INIT_22 => X"A4394F90E93E53A4394F90E93E53A4394F90E93E53A4F94E90E53E43A4F94E90",
INIT_23 => X"93E53A43A4F94E90E53E43A4F94E90E93E53A4394F90E93E53A4394F90E93E53",
INIT_24 => X"3E53E43A4F94F90E93E53E43A4F94E90E93E53A43A4F94E90E53E43A4394F90E",
INIT_25 => X"A4F94F90E90E53E53A4394F94E90E93E53A43A4F94F90E93E53E43A4F94F90E9",
INIT_26 => X"3A43A4F94F90E90E53E53A43A4F94F90E90E53E53A43A4F94F90E90E53E53A43",
INIT_27 => X"4F94E90E90E53E53E43A43A4F94F90E90E93E53E53A43A4F94F94E90E93E53E4",
INIT_28 => X"43A43A4F94F94E90E90E93E53E53E43A43A4F94F94E90E90E53E53E43A43A4F9",
INIT_29 => X"4F94F94F94F90E90E90E53E53E53E43A43A43A4F94F94F90E90E90E53E53E53A",
INIT_2A => X"3E53E53E43A43A43A43A4F94F94F94F94E90E90E90E93E53E53E53E43A43A43A",
INIT_2B => X"E53E43A43A43A43A43A43A43A4F94F94F94F94F94F90E90E90E90E90E93E53E5",
INIT_2C => X"0E90E90E90E90E90E90E90E90E90E90E90E90E90E93E53E53E53E53E53E53E53",
INIT_2D => X"90E90E90E90E90E90E90E90E90F94F94F94F94F94F94F94F94F94E90E90E90E9",
INIT_2E => X"A43A43A43A43E53E53E53E53E53E53E53E53E50E90E90E90E90E90E90E90E90E",
INIT_2F => X"A43A43A43A53E53E53E53E50E90E90E90E90E94F94F94F94F94F94FA43A43A43",
INIT_30 => X"50E90E90E94F94F94FA43A43A43A53E53E53E50E90E90E90E94F94F94F94FA43",
INIT_31 => X"3E50E90E90F94F94FA43A43A53E53E53E90E90E94F94F94FA43A43A43E53E53E",
INIT_32 => X"94F943A43A43E53E50E90E94F94FA43A43A53E53E90E90E94F94FA43A43A53E5",
INIT_33 => X"E90F94FA43A43E53E90E90F94F943A43E53E50E90E94F94FA43A43E53E90E90F",
INIT_34 => X"F943A43E53E90E94F943A43E53E90E94F94FA43A53E50E90F94F943A43E53E90",
INIT_35 => X"E94F943A43E53E90F94FA43A53E50E94F943A43E53E90E94F943A43E53E90E94",
INIT_36 => X"94FA43A53E90F94FA43E53E90F94FA43E53E90F94FA43A53E90E94FA43A53E50",
INIT_37 => X"3E90E94FA43E50E94F943A53E90E94FA43E50E90F943A53E50E94F943A53E90E",
INIT_38 => X"53E90F943A53E90F943A53E90F943A53E90E94FA43E50E94FA43E53E90F943A5",
INIT_39 => X"94FA43E50E943A53E90F943A53E90F943A53E90F943A53E90F943A53E90F943A",
INIT_3A => X"90F943A50E94FA43E50F943A53E90FA43E50E94FA53E90F943A53E90FA43E50E",
INIT_3B => X"0F943E50F943A50E94FA53E90F943E50E943A53E94FA43E50F943A50E94FA43E",
INIT_3C => X"A50E943A50E943A53E94FA53E90FA43E90F943E50F943A50E943A53E94FA43E9",
INIT_3D => X"3E50F943E50F943E50F943E50F943E50F943E50F943E50F943E50F943E50F943",
INIT_3E => X"0E943A50F943E50FA43E90FA43E94FA53E94FA50E943A50E943A50F943E50F94",
INIT_3F => X"3E50FA43E90FA53E943A50F943E90FA53E94FA50E943E50F943E90FA53E94FA5",
INIT_40 => X"A50E943E50FA53E943A50FA43E94FA50E943E90FA53E943A50F943E90FA53E94",
INIT_41 => X"3E943E90FA50E943E90FA50F943E94FA50F943E94FA50F943E94FA50E943E90F",
INIT_42 => X"43E943A50FA50E943E94FA50FA43E943E50FA50E943E94FA50FA43E943E50FA5",
INIT_43 => X"43E943E50FA50FA43E943E94FA50FA50E943E943A50FA50F943E943E50FA50E9",
INIT_44 => X"3E943E943E50FA50FA50F943E943E943E50FA50FA53E943E943E90FA50FA53E9",
INIT_45 => X"A53E943E943E943E943E50FA50FA50FA50F943E943E943E94FA50FA50FA50F94",
INIT_46 => X"FA50FA50FA50FA50FA43E943E943E943E943E943E943E50FA50FA50FA50FA50F",
INIT_47 => X"FA543E943E943E943E943E943E94FA50FA50FA50FA50FA50FA50FA50FA50FA50",
INIT_48 => X"E943E943E943FA50FA50FA50FA50FA50FA50FA50FA50FA50FA50FA50FA50FA50",
INIT_49 => X"50FA50FA50FA943E943E943E943E950FA50FA50FA50FA50FA543E943E943E943",
INIT_4A => X"A943E943E940FA50FA50FA943E943E943EA50FA50FA50FA943E943E943E950FA",
INIT_4B => X"E950FA50FA543E943EA50FA50FA943E943E950FA50FA543E943E940FA50FA50F",
INIT_4C => X"A50FE943EA50FA503E943E950FA50FE943E950FA50FA943E943FA50FA503E943",
INIT_4D => X"43E950FA503E940FA50FE943EA50FA503E943FA50FA943E940FA50FE943E950F",
INIT_4E => X"A50FA943EA50FA943EA50FA943E950FA543E950FA503E940FA50FE943FA50FA9",
INIT_4F => X"A943EA50FE943FA503E940FA503E950FA543E950FA943EA50FA943EA50FA943E",
INIT_50 => X"940FA543EA50FE940FA543EA50FE943FA503E950FA943EA50FE940FA503E950F",
INIT_51 => X"0FA943FA503EA50FE940FA543FA503E950FA943FA543EA50FE940FA543EA50FE",
INIT_52 => X"503EA503E950FE940FA940FA543FA503EA50FE950FA940FA543FA503E950FE94",
INIT_53 => X"943FA543FA543FA543FA503EA503EA503E950FE950FE940FA940FA943FA543FA",
INIT_54 => X"43FA540FA940FA940FA940FA940FA940FA940FA940FA940FA940FA940FA940FA",
INIT_55 => X"EA503EA543FA543FA940FA940FE950FE950FEA503EA503EA503FA543FA543FA5",
INIT_56 => X"3FA540FA950FEA503EA543FA940FA950FE9503EA503FA543FA940FA950FE9503",
INIT_57 => X"3FA540FE9503EA543FA940FE9503EA543FA940FE9503EA543FA940FE9503EA54",
INIT_58 => X"E9503FA540FE9503FA540FE9503FA540FE9503EA540FA9503EA543FA950FEA50",
INIT_59 => X"03FA540FEA543FA9503EA540FE9503FA940FEA543FA9503EA540FA9503FA540F",
INIT_5A => X"503FA540FEA540FEA503FA9503FA950FEA540FEA503FA9503FA540FEA543FA95",
INIT_5B => X"03FA9503FA9503FA9503FA9503FA9503FA540FEA540FEA540FEA543FA9503FA9",
INIT_5C => X"FA9503FA9503FA9503FA9503FA9503FEA540FEA540FEA540FEA540FEA540FA95",
INIT_5D => X"03FA9503FAA540FEA540FEA9503FA9503FA9500FEA540FEA540FEA540FFA9503",
INIT_5E => X"03FEA540FEA9503FAA540FEA5503FA9500FEA540FEA9503FA9500FEA540FEA55",
INIT_5F => X"FFA9500FEA5503FA9540FEA9503FAA540FFA9503FEA540FFA9503FEA540FFA95",
INIT_60 => X"5403FAA540FFA9540FEA9500FEA5503FEA5403FA9540FFA9500FEA5503FAA540",
INIT_61 => X"A9500FEA9500FEA9500FEA9500FEA9500FEA9500FEA9500FEA5503FEA5503FEA",
INIT_62 => X"95403FAA5403FEA5500FEA9500FFA9540FFAA5403FAA5503FEA5503FEA5500FE",
INIT_63 => X"03FEA9500FFAA5403FEA9500FFA95403FEA5500FEA95403FAA5503FEA9500FFA",
INIT_64 => X"5500FFAA5500FFA95403FEA95403FAA5500FFAA5503FEA95403FAA5500FFA954",
INIT_65 => X"95403FEA95403FEA95403FEA95403FEA95403FEA95403FEA95403FEA9540FFAA",
INIT_66 => X"403FEA95400FFAA5500FFAA95403FEA95403FFAA5500FFAA5500FFAA55403FEA",
INIT_67 => X"AA55003FEA95500FFAA95403FFAA55003FEA95500FFAA55403FEA95500FFAA55",
INIT_68 => X"FAA95400FFAA95500FFEA95500FFEA95500FFAA95400FFAA95400FFAA55403FF",
INIT_69 => X"AA55400FFEA955003FEAA55400FFAA95500FFEAA55003FEAA55403FFAA95400F",
INIT_6A => X"400FFEAA55003FFAA955003FFAA955003FFAA55400FFEAA55400FFAA955003FF",
INIT_6B => X"955003FFAAA55400FFEAA554003FFAA955003FFAA955003FFAA955400FFEAA55",
INIT_6C => X"554003FFAAA554003FFAA955400FFFAA955000FFEAA555003FFAAA55400FFEAA",
INIT_6D => X"03FFEAA9554003FFAAA555003FFEAA955000FFFAA9554003FFAAA554003FFAAA",
INIT_6E => X"555000FFFAAA9554003FFEAA9554003FFEAA9554003FFAAA555000FFFAAA5550",
INIT_6F => X"9555000FFFEAA9555000FFFEAA9554000FFFAAA5554003FFEAA9555000FFFAAA",
INIT_70 => X"50003FFEAAA5554000FFFEAAA5550003FFFAAA9554000FFFEAA9555000FFFEAA",
INIT_71 => X"AAAA5554000FFFFAAA95550000FFFEAAA5554000FFFEAAA95550003FFFAAA955",
INIT_72 => X"FFEAAA955540003FFFEAAA55550000FFFFAAA955540003FFFAAAA55540003FFF",
INIT_73 => X"AAAA555540000FFFFAAAA555540003FFFFAAAA55550000FFFFEAAA955540003F",
INIT_74 => X"40000FFFFFAAAA9555500003FFFFEAAAA555540000FFFFEAAA9555500003FFFF",
INIT_75 => X"55555400003FFFFEAAAA95555400003FFFFEAAAA9555540000FFFFFAAAA95555",
INIT_76 => X"5555000000FFFFFEAAAAA55555400000FFFFFEAAAAA55555400003FFFFFAAAAA",
INIT_77 => X"0FFFFFFEAAAAAA5555554000003FFFFFEAAAAA9555554000003FFFFFEAAAAA95",
INIT_78 => X"55500000003FFFFFFEAAAAAA955555540000003FFFFFFEAAAAAA555555400000",
INIT_79 => X"555400000000FFFFFFFFEAAAAAAA95555555400000003FFFFFFFAAAAAAA95555",
INIT_7A => X"00FFFFFFFFFFEAAAAAAAAA5555555554000000000FFFFFFFFFAAAAAAAAA55555",
INIT_7B => X"5555555554000000000000FFFFFFFFFFFEAAAAAAAAAAA5555555555400000000",
INIT_7C => X"A95555555555555555000000000000000FFFFFFFFFFFFFFEAAAAAAAAAAAAA555",
INIT_7D => X"555500000000000000000000000FFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAA",
INIT_7E => X"EAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555555555",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(3 downto 2),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(3 downto 2),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"400FFEAA55400FFEAA555003FFAA955003FFAA955003FFEAA55400FFEAA55400",
INIT_01 => X"955400FFEAA55400FFEAA55400FFFAA955003FFAA955003FFAA955000FFEAA55",
INIT_02 => X"FAA955003FFAAA55400FFEAA55400FFEAA554003FFAA955003FFAA955003FFAA",
INIT_03 => X"03FFAA955003FFAA955003FFEAA55400FFEAA55400FFEAA554003FFAA955003F",
INIT_04 => X"5400FFEAA555003FFAA955003FFAA955003FFEAA55400FFEAA55400FFEAA5550",
INIT_05 => X"A955400FFEAA55400FFEAA554003FFAA955003FFAA955003FFAAA55400FFEAA5",
INIT_06 => X"FFAA955003FFAA955000FFEAA55400FFEAA55400FFFAA955003FFAA955003FFA",
INIT_07 => X"00FFEAA55400FFEAA955003FFAA955003FFAAA55400FFEAA55400FFEAA555003",
INIT_08 => X"55003FFAA955003FFEAA55400FFEAA55400FFFAA955003FFAA955003FFEAA554",
INIT_09 => X"AA55400FFEAA55400FFFAA955003FFAA955003FFEAA55400FFEAA55400FFFAA9",
INIT_0A => X"FEAA555003FFAA955003FFAAA55400FFEAA55400FFEAA955003FFAA955003FFE",
INIT_0B => X"03FFAA955003FFAAA55400FFEAA55400FFFAA955003FFAA955000FFEAA55400F",
INIT_0C => X"5003FFAA955000FFEAA55400FFEAA955003FFAA955003FFEAA55400FFEAA5550",
INIT_0D => X"955003FFAA955400FFEAA55400FFFAA955003FFAA955400FFEAA55400FFFAA95",
INIT_0E => X"AA955003FFAA955000FFEAA55400FFEAA955003FFAA955400FFEAA55400FFFAA",
INIT_0F => X"FEAA55400FFFAA955003FFAAA55400FFEAA555003FFAA955003FFEAA55400FFE",
INIT_10 => X"3FFAA955000FFEAA554003FFAA955003FFEAA55400FFEAA955003FFAA955000F",
INIT_11 => X"00FFEAA554003FFAA955000FFEAA55400FFFAA955003FFAAA55400FFEAA55500",
INIT_12 => X"400FFFAA955003FFAAA55400FFEAA955003FFAAA55400FFEAA555003FFAA9554",
INIT_13 => X"54003FFAA955000FFEAA554003FFAA955003FFEAA55400FFFAA955003FFEAA55",
INIT_14 => X"55400FFFAA955003FFEAA55400FFFAA955003FFEAA554003FFAA955000FFEAA5",
INIT_15 => X"955000FFEAA555003FFAA955400FFEAA955003FFAAA55400FFEAA955003FFEAA",
INIT_16 => X"A554003FFAA955400FFEAA955003FFAAA55400FFFAA955003FFEAA554003FFAA",
INIT_17 => X"A955003FFEAA554003FFAA955400FFEAA555003FFAAA55400FFFAA955000FFEA",
INIT_18 => X"A955003FFEAA554003FFAA955400FFEAA955003FFEAA554003FFAA955400FFEA",
INIT_19 => X"A555003FFAAA55400FFFAA955000FFEAA955003FFEAA554003FFAA955400FFEA",
INIT_1A => X"955400FFEAA955000FFEAA555003FFAAA554003FFAA955400FFEAA955003FFEA",
INIT_1B => X"55400FFFAA955400FFFAA955000FFEAA955003FFEAA554003FFAAA55400FFFAA",
INIT_1C => X"5400FFFAA955400FFFAA955000FFEAA955000FFEAA555003FFEAA554003FFAAA",
INIT_1D => X"000FFEAA955000FFEAA555003FFEAA555003FFEAA554003FFAAA554003FFAAA5",
INIT_1E => X"0FFFAA955400FFFAA955400FFFAA955400FFFAA955400FFFAA955000FFEAA955",
INIT_1F => X"FFAA955400FFFAAA554003FFAAA554003FFAAA554003FFAA955400FFFAA95540",
INIT_20 => X"AA955000FFEAA955400FFFAA955400FFFAA955400FFFAA955400FFFAA955400F",
INIT_21 => X"554003FFAAA554003FFAAA555003FFEAA555003FFEAA555000FFEAA955000FFE",
INIT_22 => X"003FFAAA554003FFEAA555003FFEAA955000FFEAA955000FFFAA955400FFFAAA",
INIT_23 => X"FEAA955400FFFAAA554003FFAAA555003FFEAA955000FFEAA955400FFFAA9554",
INIT_24 => X"9554003FFAAA555003FFEAA955000FFFAA9554003FFAAA555003FFEAA955000F",
INIT_25 => X"00FFFAAA555003FFEAA955000FFFAA9554003FFAAA555003FFEAA955000FFFAA",
INIT_26 => X"EAA955000FFFAAA554003FFEAA555000FFFAA9554003FFAAA555000FFEAA9554",
INIT_27 => X"5000FFFAAA554003FFEAA955000FFFAAA554003FFEAA955000FFFAAA554003FF",
INIT_28 => X"FEAA955000FFFAAA555003FFEAA9554003FFAAA555000FFFAA9554003FFEAA55",
INIT_29 => X"5000FFFAAA555000FFFAA9554003FFEAA955400FFFAAA555000FFFAA9554003F",
INIT_2A => X"EAA9554003FFEAA955400FFFAAA555000FFFAAA555003FFEAA9554003FFEAA95",
INIT_2B => X"003FFEAA9554003FFEAA955400FFFAAA555000FFFAAA555000FFFAAA554003FF",
INIT_2C => X"A555000FFFAAA555000FFFAAA555000FFFAAA555003FFEAA9554003FFEAA9554",
INIT_2D => X"FFAAA555000FFFAAA555000FFFAAA555000FFFAAA555000FFFAAA555000FFFAA",
INIT_2E => X"003FFEAA9554003FFEAA9554003FFEAA9554000FFFAAA555000FFFAAA555000F",
INIT_2F => X"554003FFEAA9554003FFEAAA555000FFFAAA555000FFFAAA555000FFFEAA9554",
INIT_30 => X"AA555000FFFAAA5550003FFEAA9554003FFEAAA555000FFFAAA555000FFFAAA9",
INIT_31 => X"EAAA555000FFFAAA5554003FFEAA9554000FFFAAA555000FFFEAA9554003FFEA",
INIT_32 => X"FFAAA9554003FFEAAA555000FFFAAA9554003FFEAAA555000FFFAAA9554003FF",
INIT_33 => X"FFFAAA5554003FFEAAA555000FFFEAA9554000FFFAAA5550003FFEAA9555000F",
INIT_34 => X"FFFEAA9554000FFFAAA9554003FFFAAA5550003FFEAAA555000FFFEAA9554000",
INIT_35 => X"FFFAAA9554003FFFAAA5554003FFFAAA5554003FFEAAA5550003FFEAA9555000",
INIT_36 => X"FFAAA9554000FFFAAA9554000FFFAAA9554000FFFAAA9554000FFFAAA9554000",
INIT_37 => X"EAAA5550003FFFAAA5554003FFFAAA5554000FFFAAA9554000FFFAAA9554000F",
INIT_38 => X"A95550003FFEAAA5554003FFFAAA9554000FFFAAA9555000FFFEAA95550003FF",
INIT_39 => X"550003FFFAAA9554000FFFEAA95550003FFEAAA5554003FFFAAA9554000FFFEA",
INIT_3A => X"00FFFEAAA5550003FFFAAA9554000FFFEAAA5550003FFFAAA9554000FFFEAAA5",
INIT_3B => X"FAAA95550003FFFAAA5554000FFFEAAA5554003FFFAAA95550003FFFAAA55540",
INIT_3C => X"5550003FFFAAA9554000FFFEAAA5554000FFFEAAA5554000FFFEAA95550003FF",
INIT_3D => X"3FFFAAA95550003FFFAAA95550003FFFAAA95550003FFFAAA95550003FFFAAA9",
INIT_3E => X"A5554000FFFEAAA5554000FFFEAAA5554000FFFFAAA95550003FFFAAA9555000",
INIT_3F => X"3FFFAAA95550003FFFEAAA5554000FFFEAAA55550003FFFAAA95550003FFFAAA",
INIT_40 => X"5550003FFFAAA95554000FFFEAAA55550003FFFAAA95554000FFFEAAA5554000",
INIT_41 => X"EAAA95550000FFFEAAA55550003FFFAAAA5554000FFFFAAA95550000FFFEAAA5",
INIT_42 => X"03FFFEAAA55550003FFFAAAA55540003FFFAAAA5554000FFFFAAA95554000FFF",
INIT_43 => X"540003FFFAAAA55540003FFFAAAA55550003FFFEAAA55550003FFFEAAA555500",
INIT_44 => X"955540003FFFAAAA55550003FFFEAAA95550000FFFEAAA95554000FFFFAAA955",
INIT_45 => X"AA955540003FFFEAAA95550000FFFFAAAA55540003FFFEAAA55550000FFFFAAA",
INIT_46 => X"AAAA55550000FFFFAAA955540003FFFEAAA955540003FFFAAAA55550000FFFFA",
INIT_47 => X"AAAA955540003FFFEAAA95554000FFFFAAAA55550000FFFFAAAA55550000FFFF",
INIT_48 => X"AAA955540003FFFFAAAA55550000FFFFAAAA55550000FFFFAAAA55550000FFFF",
INIT_49 => X"AA55550000FFFFEAAA955540003FFFFAAAA55550000FFFFAAAA955540003FFFE",
INIT_4A => X"55540003FFFFAAAA555500003FFFEAAA955550000FFFFAAAA955540003FFFFAA",
INIT_4B => X"0000FFFFAAAA955540000FFFFAAAA955540000FFFFAAAA955540000FFFFAAAA5",
INIT_4C => X"FFFAAAA9555500003FFFEAAAA555500003FFFFAAAA555540003FFFFAAAA95554",
INIT_4D => X"A9555500003FFFFAAAA555540000FFFFEAAA9555500003FFFFAAAA555540000F",
INIT_4E => X"000FFFFEAAAA555540000FFFFEAAAA555540000FFFFEAAAA555500003FFFFAAA",
INIT_4F => X"AAA9555500003FFFFEAAAA555540000FFFFEAAAA555540000FFFFEAAAA555540",
INIT_50 => X"000FFFFEAAAA5555500003FFFFAAAA9555540000FFFFEAAAA5555500003FFFFA",
INIT_51 => X"A5555400003FFFFAAAAA5555400003FFFFAAAA9555540000FFFFFAAAA9555500",
INIT_52 => X"FFEAAAA9555500000FFFFFAAAA9555540000FFFFFAAAAA5555400003FFFFAAAA",
INIT_53 => X"003FFFFEAAAA95555400003FFFFEAAAA9555500000FFFFFAAAAA5555400003FF",
INIT_54 => X"5400000FFFFFAAAAA5555500000FFFFFAAAAA5555500000FFFFFAAAAA5555500",
INIT_55 => X"5555400003FFFFEAAAAA5555500000FFFFFAAAAA95555400003FFFFEAAAA9555",
INIT_56 => X"95555500000FFFFFEAAAA95555500000FFFFFEAAAA95555400000FFFFFAAAAA9",
INIT_57 => X"955555000003FFFFEAAAAA55555400003FFFFFAAAAA95555400000FFFFFEAAAA",
INIT_58 => X"5555400000FFFFFEAAAAA55555400000FFFFFEAAAAA55555400003FFFFFAAAAA",
INIT_59 => X"5400000FFFFFEAAAAA955555000003FFFFFAAAAA955555400000FFFFFEAAAAA5",
INIT_5A => X"003FFFFFAAAAAA555554000003FFFFFAAAAAA555554000003FFFFFAAAAA95555",
INIT_5B => X"FEAAAAA9555554000003FFFFFEAAAAA955555000000FFFFFFAAAAA9555554000",
INIT_5C => X"555554000003FFFFFEAAAAA9555554000000FFFFFFAAAAAA555555000000FFFF",
INIT_5D => X"03FFFFFEAAAAAA5555550000003FFFFFEAAAAAA555555000000FFFFFFAAAAAA9",
INIT_5E => X"A95555550000003FFFFFFAAAAAA9555555000000FFFFFFEAAAAAA55555500000",
INIT_5F => X"FFFFFFFAAAAAA95555550000003FFFFFFAAAAAA95555550000003FFFFFFAAAAA",
INIT_60 => X"5554000000FFFFFFFAAAAAAA55555540000003FFFFFFAAAAAAA5555554000000",
INIT_61 => X"AAAAA55555550000000FFFFFFFAAAAAAA55555550000000FFFFFFEAAAAAA9555",
INIT_62 => X"FFFFEAAAAAA955555550000000FFFFFFFAAAAAAA955555540000003FFFFFFFAA",
INIT_63 => X"03FFFFFFFAAAAAAA9555555500000003FFFFFFFAAAAAAA955555540000000FFF",
INIT_64 => X"0000FFFFFFFFAAAAAAA9555555540000000FFFFFFFEAAAAAAA95555555000000",
INIT_65 => X"00003FFFFFFFEAAAAAAA95555555400000003FFFFFFFEAAAAAAA955555550000",
INIT_66 => X"003FFFFFFFFAAAAAAAA55555555400000003FFFFFFFFAAAAAAAA555555554000",
INIT_67 => X"FFFFFFEAAAAAAAA555555554000000003FFFFFFFFAAAAAAAA955555555000000",
INIT_68 => X"AAAAAAAA555555555000000000FFFFFFFFFAAAAAAAAA555555555000000003FF",
INIT_69 => X"55555550000000003FFFFFFFFFAAAAAAAAA5555555554000000003FFFFFFFFFA",
INIT_6A => X"000FFFFFFFFFEAAAAAAAAA95555555554000000000FFFFFFFFFFAAAAAAAAA955",
INIT_6B => X"AAAAA9555555555500000000003FFFFFFFFFEAAAAAAAAA955555555550000000",
INIT_6C => X"000003FFFFFFFFFFEAAAAAAAAAA5555555555500000000003FFFFFFFFFFAAAAA",
INIT_6D => X"A955555555555400000000003FFFFFFFFFFFAAAAAAAAAAA95555555555400000",
INIT_6E => X"FFFFFFAAAAAAAAAAAA9555555555554000000000003FFFFFFFFFFFAAAAAAAAAA",
INIT_6F => X"0000000FFFFFFFFFFFFFAAAAAAAAAAAAA5555555555554000000000000FFFFFF",
INIT_70 => X"555540000000000000FFFFFFFFFFFFFEAAAAAAAAAAAAA5555555555555000000",
INIT_71 => X"55555555555000000000000000FFFFFFFFFFFFFFAAAAAAAAAAAAAA9555555555",
INIT_72 => X"555555555555554000000000000000FFFFFFFFFFFFFFFEAAAAAAAAAAAAAA9555",
INIT_73 => X"555555555555500000000000000003FFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAA95",
INIT_74 => X"555550000000000000000003FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAA95555",
INIT_75 => X"00000000003FFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAA55555555555555",
INIT_76 => X"FFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAA55555555555555555555540000000000",
INIT_77 => X"A55555555555555555555555554000000000000000000000003FFFFFFFFFFFFF",
INIT_78 => X"00000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_79 => X"AAAAAAAAAAAA5555555555555555555555555555555540000000000000000000",
INIT_7A => X"00FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAA",
INIT_7B => X"5555555555555555555555000000000000000000000000000000000000000000",
INIT_7C => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555555555555555555555555555",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(5 downto 4),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5 downto 4),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"AAA555555555500000000003FFFFFFFFFEAAAAAAAAA955555555550000000000",
INIT_01 => X"000000FFFFFFFFFFAAAAAAAAAA555555555540000000003FFFFFFFFFFAAAAAAA",
INIT_02 => X"AAAAAAAA955555555550000000000FFFFFFFFFFEAAAAAAAAA955555555540000",
INIT_03 => X"540000000003FFFFFFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFEA",
INIT_04 => X"FFFFAAAAAAAAAA955555555540000000003FFFFFFFFFFAAAAAAAAAA555555555",
INIT_05 => X"55555550000000000FFFFFFFFFFEAAAAAAAAA955555555540000000000FFFFFF",
INIT_06 => X"FFFFFFFFFEAAAAAAAAAA55555555550000000000FFFFFFFFFFEAAAAAAAAA9555",
INIT_07 => X"AA555555555500000000003FFFFFFFFFEAAAAAAAAAA555555555500000000003",
INIT_08 => X"00003FFFFFFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFEAAAAAAAA",
INIT_09 => X"AAAAAAA555555555500000000003FFFFFFFFFEAAAAAAAAAA5555555555000000",
INIT_0A => X"0000000003FFFFFFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFEAAA",
INIT_0B => X"FEAAAAAAAAA955555555550000000000FFFFFFFFFFEAAAAAAAAAA55555555550",
INIT_0C => X"55540000000000FFFFFFFFFFAAAAAAAAAA955555555540000000000FFFFFFFFF",
INIT_0D => X"FFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFFAAAAAAAAAA5555555",
INIT_0E => X"555555540000000000FFFFFFFFFFAAAAAAAAAA955555555550000000000FFFFF",
INIT_0F => X"FFFFFFFFFAAAAAAAAAA9555555555500000000003FFFFFFFFFEAAAAAAAAAA555",
INIT_10 => X"9555555555500000000003FFFFFFFFFEAAAAAAAAAA555555555540000000000F",
INIT_11 => X"00FFFFFFFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFFAAAAAAAAAA",
INIT_12 => X"AAA555555555540000000000FFFFFFFFFFEAAAAAAAAAA5555555555400000000",
INIT_13 => X"00003FFFFFFFFFFAAAAAAAAAA955555555540000000000FFFFFFFFFFEAAAAAAA",
INIT_14 => X"AAAAA555555555540000000000FFFFFFFFFFEAAAAAAAAAA95555555555000000",
INIT_15 => X"000000FFFFFFFFFFEAAAAAAAAAA555555555540000000000FFFFFFFFFFEAAAAA",
INIT_16 => X"AAAAAA9555555555500000000003FFFFFFFFFFAAAAAAAAAA9555555555540000",
INIT_17 => X"0000003FFFFFFFFFFEAAAAAAAAAA555555555540000000000FFFFFFFFFFFAAAA",
INIT_18 => X"AAAAAA9555555555540000000000FFFFFFFFFFEAAAAAAAAAA955555555550000",
INIT_19 => X"0000003FFFFFFFFFFAAAAAAAAAAA5555555555400000000003FFFFFFFFFFAAAA",
INIT_1A => X"AAAAAA5555555555500000000003FFFFFFFFFFEAAAAAAAAAA555555555540000",
INIT_1B => X"00000FFFFFFFFFFFAAAAAAAAAAA5555555555400000000003FFFFFFFFFFAAAAA",
INIT_1C => X"AAAA5555555555500000000000FFFFFFFFFFFAAAAAAAAAA95555555555400000",
INIT_1D => X"000FFFFFFFFFFFAAAAAAAAAA95555555555400000000003FFFFFFFFFFEAAAAAA",
INIT_1E => X"A5555555555500000000000FFFFFFFFFFFAAAAAAAAAAA5555555555500000000",
INIT_1F => X"FFFFFFFFFFAAAAAAAAAAA95555555555400000000003FFFFFFFFFFAAAAAAAAAA",
INIT_20 => X"5555555500000000000FFFFFFFFFFFAAAAAAAAAAA5555555555500000000000F",
INIT_21 => X"FFFFFEAAAAAAAAAA95555555555400000000003FFFFFFFFFFFAAAAAAAAAAA555",
INIT_22 => X"55400000000003FFFFFFFFFFEAAAAAAAAAAA5555555555500000000000FFFFFF",
INIT_23 => X"AAAAAAAAAA55555555555400000000003FFFFFFFFFFFAAAAAAAAAAA555555555",
INIT_24 => X"0000003FFFFFFFFFFEAAAAAAAAAAA55555555555400000000003FFFFFFFFFFFA",
INIT_25 => X"AA55555555555400000000000FFFFFFFFFFFEAAAAAAAAAA95555555555500000",
INIT_26 => X"FFFFFFFFFAAAAAAAAAAA955555555555000000000003FFFFFFFFFFFAAAAAAAAA",
INIT_27 => X"5555000000000003FFFFFFFFFFFAAAAAAAAAAA955555555555000000000003FF",
INIT_28 => X"AAAAAAAAAA555555555554000000000003FFFFFFFFFFFAAAAAAAAAAA95555555",
INIT_29 => X"0000FFFFFFFFFFFFAAAAAAAAAAA955555555555000000000000FFFFFFFFFFFEA",
INIT_2A => X"555555555400000000000FFFFFFFFFFFFAAAAAAAAAAA95555555555540000000",
INIT_2B => X"FFEAAAAAAAAAAA955555555555000000000000FFFFFFFFFFFFAAAAAAAAAAA955",
INIT_2C => X"0000000FFFFFFFFFFFFAAAAAAAAAAAA555555555554000000000003FFFFFFFFF",
INIT_2D => X"55555555555000000000000FFFFFFFFFFFFAAAAAAAAAAAA55555555555500000",
INIT_2E => X"FFEAAAAAAAAAAA9555555555554000000000000FFFFFFFFFFFFAAAAAAAAAAAA5",
INIT_2F => X"000003FFFFFFFFFFFEAAAAAAAAAAAA555555555555000000000000FFFFFFFFFF",
INIT_30 => X"555555550000000000003FFFFFFFFFFFEAAAAAAAAAAAA5555555555550000000",
INIT_31 => X"AAAAAAAAAA5555555555554000000000000FFFFFFFFFFFFAAAAAAAAAAAA95555",
INIT_32 => X"FFFFFFFFFFFEAAAAAAAAAAAA5555555555554000000000000FFFFFFFFFFFFEAA",
INIT_33 => X"0000000000003FFFFFFFFFFFFAAAAAAAAAAAAA5555555555554000000000000F",
INIT_34 => X"55555555555550000000000003FFFFFFFFFFFFEAAAAAAAAAAAA5555555555555",
INIT_35 => X"AAAAAAAAAAAA955555555555540000000000003FFFFFFFFFFFFEAAAAAAAAAAAA",
INIT_36 => X"FFFFFFFFFFFFAAAAAAAAAAAAA55555555555550000000000000FFFFFFFFFFFFF",
INIT_37 => X"00000000003FFFFFFFFFFFFEAAAAAAAAAAAAA55555555555550000000000000F",
INIT_38 => X"5555555540000000000003FFFFFFFFFFFFFAAAAAAAAAAAAA5555555555555400",
INIT_39 => X"AAAAA9555555555555500000000000003FFFFFFFFFFFFEAAAAAAAAAAAAA55555",
INIT_3A => X"FFAAAAAAAAAAAAA9555555555555500000000000003FFFFFFFFFFFFFAAAAAAAA",
INIT_3B => X"FFFFFFFFFFFEAAAAAAAAAAAAA5555555555555400000000000003FFFFFFFFFFF",
INIT_3C => X"0000003FFFFFFFFFFFFFAAAAAAAAAAAAAA5555555555555500000000000003FF",
INIT_3D => X"400000000000003FFFFFFFFFFFFFEAAAAAAAAAAAAA9555555555555540000000",
INIT_3E => X"5555555500000000000000FFFFFFFFFFFFFFAAAAAAAAAAAAAA95555555555555",
INIT_3F => X"95555555555555400000000000000FFFFFFFFFFFFFFEAAAAAAAAAAAAA9555555",
INIT_40 => X"AAAAAA955555555555555000000000000003FFFFFFFFFFFFFFAAAAAAAAAAAAAA",
INIT_41 => X"AAAAAAAAAAAA55555555555555400000000000000FFFFFFFFFFFFFFFAAAAAAAA",
INIT_42 => X"FEAAAAAAAAAAAAAA955555555555555400000000000000FFFFFFFFFFFFFFFAAA",
INIT_43 => X"FFFFFEAAAAAAAAAAAAAA9555555555555554000000000000003FFFFFFFFFFFFF",
INIT_44 => X"FFFFFFFFEAAAAAAAAAAAAAA9555555555555555000000000000000FFFFFFFFFF",
INIT_45 => X"FFFFFFFFFFEAAAAAAAAAAAAAAA5555555555555554000000000000000FFFFFFF",
INIT_46 => X"FFFFFFFFFFFFAAAAAAAAAAAAAAA95555555555555554000000000000000FFFFF",
INIT_47 => X"FFFFFFFFFFFFEAAAAAAAAAAAAAAA55555555555555550000000000000000FFFF",
INIT_48 => X"FFFFFFFFFFFEAAAAAAAAAAAAAAAA55555555555555550000000000000000FFFF",
INIT_49 => X"FFFFFFFFFFAAAAAAAAAAAAAAAA9555555555555555500000000000000003FFFF",
INIT_4A => X"FFFFFFFEAAAAAAAAAAAAAAAA9555555555555555500000000000000003FFFFFF",
INIT_4B => X"FFFFAAAAAAAAAAAAAAAAA5555555555555555500000000000000000FFFFFFFFF",
INIT_4C => X"AAAAAAAAAAAAAAAA95555555555555555400000000000000003FFFFFFFFFFFFF",
INIT_4D => X"AAAAAAAAAA955555555555555555000000000000000003FFFFFFFFFFFFFFFFFA",
INIT_4E => X"AAA555555555555555555000000000000000000FFFFFFFFFFFFFFFFFEAAAAAAA",
INIT_4F => X"5555555555554000000000000000000FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAA",
INIT_50 => X"5550000000000000000003FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAA955555",
INIT_51 => X"00000000003FFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAA5555555555555555",
INIT_52 => X"FFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAA5555555555555555555400000000",
INIT_53 => X"FFEAAAAAAAAAAAAAAAAAAA9555555555555555555500000000000000000003FF",
INIT_54 => X"AAAAAAA5555555555555555555500000000000000000000FFFFFFFFFFFFFFFFF",
INIT_55 => X"555555555400000000000000000000FFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAA",
INIT_56 => X"00000000000FFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAA55555555555",
INIT_57 => X"FFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAA95555555555555555555550000000000",
INIT_58 => X"AAAAAAAAAA55555555555555555555550000000000000000000003FFFFFFFFFF",
INIT_59 => X"555555500000000000000000000003FFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAA",
INIT_5A => X"003FFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAA9555555555555555",
INIT_5B => X"AAAAAAAAAAAAAAAAAAA955555555555555555555555000000000000000000000",
INIT_5C => X"555555555554000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFAAAA",
INIT_5D => X"03FFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAA5555555555555",
INIT_5E => X"AAAAAAAAAAAAAA95555555555555555555555555000000000000000000000000",
INIT_5F => X"000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAA",
INIT_60 => X"FFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAA955555555555555555555555555",
INIT_61 => X"55555555555555555550000000000000000000000000000FFFFFFFFFFFFFFFFF",
INIT_62 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAA9555555555",
INIT_63 => X"A955555555555555555555555555555400000000000000000000000000000FFF",
INIT_64 => X"0000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_65 => X"AAAA955555555555555555555555555555554000000000000000000000000000",
INIT_66 => X"003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_67 => X"5555555555555555555555555555555540000000000000000000000000000000",
INIT_68 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955",
INIT_69 => X"555555555555555540000000000000000000000000000000000003FFFFFFFFFF",
INIT_6A => X"FFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555555555555555555",
INIT_6B => X"000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6C => X"AAAAA95555555555555555555555555555555555555555554000000000000000",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_6E => X"0000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"AAAAAAA555555555555555555555555555555555555555555555555555000000",
INIT_70 => X"FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_71 => X"00000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_72 => X"5555555555555555555555555555550000000000000000000000000000000000",
INIT_73 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555555",
INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_75 => X"00000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"5555555555555555555555555555555555555555555555555540000000000000",
INIT_78 => X"AAAAAAAAAA955555555555555555555555555555555555555555555555555555",
INIT_79 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_7A => X"FFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(7 downto 6),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(7 downto 6),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"5555555555555555555555540000000000000000000000000000000000000000",
INIT_01 => X"FFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955555555555555555",
INIT_02 => X"00000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"AAAAAAAAAAA95555555555555555555555555555555555555555400000000000",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_05 => X"5555555555555555500000000000000000000000000000000000000000FFFFFF",
INIT_06 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555555555",
INIT_07 => X"00000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_08 => X"AAAA955555555555555555555555555555555555555554000000000000000000",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_0A => X"555555555400000000000000000000000000000000000000003FFFFFFFFFFFFF",
INIT_0B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555555555555555",
INIT_0C => X"00000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAA",
INIT_0D => X"5555555555555555555555555555555555554000000000000000000000000000",
INIT_0E => X"FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555",
INIT_0F => X"00000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"AAAAAAAAAAAAAAAAAAAAA9555555555555555555555555555555555555555550",
INIT_11 => X"00FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAA",
INIT_12 => X"5555555555555555555555550000000000000000000000000000000000000000",
INIT_13 => X"FFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555",
INIT_14 => X"00000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"AAAAAA5555555555555555555555555555555555555555550000000000000000",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_17 => X"5555554000000000000000000000000000000000000000000FFFFFFFFFFFFFFF",
INIT_18 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555555555555555555555",
INIT_19 => X"0000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAA",
INIT_1A => X"5555555555555555555555555554000000000000000000000000000000000000",
INIT_1B => X"FFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA9555555555555555",
INIT_1C => X"00000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"AAA5555555555555555555555555555555555555555555400000000000000000",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1F => X"00000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"AAAAAAAAAAAAAAAAAAA555555555555555555555555555555555555555555550",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_22 => X"5555555555555400000000000000000000000000000000000000000000FFFFFF",
INIT_23 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555",
INIT_24 => X"0000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAA",
INIT_25 => X"5555555555555555555555555000000000000000000000000000000000000000",
INIT_26 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955555555555555555555",
INIT_27 => X"0000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAA",
INIT_28 => X"5555555555555555555555555555555554000000000000000000000000000000",
INIT_29 => X"FFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555555555",
INIT_2A => X"000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"5555555555555555555555555555555555555500000000000000000000000000",
INIT_2C => X"FFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA9555555555",
INIT_2D => X"00000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"5555555555555555555555555555555555555550000000000000000000000000",
INIT_2F => X"FFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555555",
INIT_30 => X"000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_31 => X"5555555555555555555555555555555555500000000000000000000000000000",
INIT_32 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555",
INIT_33 => X"0000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA",
INIT_34 => X"5555555555555555555555555400000000000000000000000000000000000000",
INIT_35 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAA",
INIT_37 => X"555555555540000000000000000000000000000000000000000000000000000F",
INIT_38 => X"AAAAAAAAAAAAAAAAAAAAA9555555555555555555555555555555555555555555",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_3A => X"0000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFF",
INIT_3B => X"5555555555555555555555555555555555555555555555555555400000000000",
INIT_3C => X"FFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955",
INIT_3D => X"000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3E => X"5555555555555555555555000000000000000000000000000000000000000000",
INIT_3F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555555555555555555",
INIT_40 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_41 => X"00000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFF",
INIT_42 => X"5555555555555555555555555555555555555555555555000000000000000000",
INIT_43 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555",
INIT_44 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAA",
INIT_45 => X"000000000000000000000000000000000000000000000000000000000FFFFFFF",
INIT_46 => X"5555555555555555555555555555555555555555555555555555555555500000",
INIT_47 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555",
INIT_48 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAA",
INIT_49 => X"000000000000000000000000000000000000000000000000000000000003FFFF",
INIT_4A => X"5555555555555555555555555555555555555555555555555555555554000000",
INIT_4B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555",
INIT_4C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAA",
INIT_4D => X"0000000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFF",
INIT_4E => X"5555555555555555555555555555555555555550000000000000000000000000",
INIT_4F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555555555555555555",
INIT_50 => X"FFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_51 => X"00000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"5555555555555555555555555555555555555555555555555555555555555400",
INIT_54 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555",
INIT_55 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_56 => X"00000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"5555555555555555555555555555555555555555555555555555540000000000",
INIT_59 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555555",
INIT_5A => X"FFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5C => X"000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5D => X"5400000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_5F => X"AAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555555555",
INIT_60 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_61 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAA",
INIT_62 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000FFF",
INIT_64 => X"5555000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_66 => X"AA95555555555555555555555555555555555555555555555555555555555555",
INIT_67 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_68 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_69 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAA",
INIT_6A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6B => X"000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"5555555555555555555555555555555555555555554000000000000000000000",
INIT_6F => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_70 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_71 => X"AAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555555555555555555555",
INIT_72 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_73 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_74 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_75 => X"FFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => p_0_in(1 downto 0),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(9 downto 8),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"5555555555555555555555555555500000000000000000000000000000000000",
INIT_03 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_04 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_05 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555",
INIT_06 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"000000000000000000000000000000000000000000000000003FFFFFFFFFFFFF",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"5555555555555500000000000000000000000000000000000000000000000000",
INIT_0D => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0E => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955555555555555555555555",
INIT_10 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_11 => X"FFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"00000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"5555555555555555555555555555555555555555555555555000000000000000",
INIT_18 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_19 => X"AAAAAA9555555555555555555555555555555555555555555555555555555555",
INIT_1A => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"00000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"5555555555555555555555555555555555555555555555555555555555000000",
INIT_23 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_24 => X"AAAAAA9555555555555555555555555555555555555555555555555555555555",
INIT_25 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_26 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_27 => X"FFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"5555555555555555555555500000000000000000000000000000000000000000",
INIT_2E => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_2F => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_30 => X"AAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555555555555555",
INIT_31 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_32 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_33 => X"FFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"000000000000000000000000000000000000000000000000000000000000000F",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"5555555555555555555555555555555555555555554000000000000000000000",
INIT_3B => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3C => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3D => X"AAAAAAAAAAAAAA95555555555555555555555555555555555555555555555555",
INIT_3E => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_3F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_40 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_41 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAA",
INIT_42 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_43 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_44 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_45 => X"000000000000000000000000000000000000000000000000000000000FFFFFFF",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"5555555555555555555555555555555555555555555555555555555555540000",
INIT_4A => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_4B => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_4C => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_4D => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA9555555555555555555",
INIT_4E => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_50 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_51 => X"FFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_52 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_53 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_54 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_55 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_56 => X"00000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"5555555555555555555555555555555555550000000000000000000000000000",
INIT_5D => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_5E => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_5F => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_60 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_61 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_62 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_63 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555",
INIT_64 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_65 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_66 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_67 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_68 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_69 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_6A => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_6B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_6C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_70 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_71 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_73 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_75 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => p_0_in(3 downto 2),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(11 downto 10),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"5555555555555555555555555555555555555555555555555540000000000000",
INIT_0B => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0C => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0D => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0E => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0F => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_10 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_11 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_12 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_13 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_14 => X"AAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555555555555555555555",
INIT_15 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_16 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_17 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_18 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_19 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1A => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1C => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1D => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1E => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAA",
INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"5555555555555555555555555555555555555555555555555555555555555550",
INIT_38 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_39 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3A => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3B => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3C => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3D => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3E => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3F => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_40 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_41 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_42 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_43 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_44 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_45 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555",
INIT_46 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_47 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_48 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_49 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4A => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4C => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4D => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4E => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_50 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_51 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_52 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_53 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_54 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_55 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_56 => X"FFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_57 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_58 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_59 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_60 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_61 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_62 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_63 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_64 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_65 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_66 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_67 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_68 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_69 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_70 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_71 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_73 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_75 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => p_0_in(5 downto 4),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(13 downto 12),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000000000000000000000",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 0) => sin_addr(13 downto 0),
ADDRBWRADDR(13 downto 0) => cos_addr(13 downto 0),
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const0>\,
DIADI(0) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(15 downto 1) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => p_0_in(6),
DOBDO(15 downto 1) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOBDO_UNCONNECTED\(15 downto 1),
DOBDO(0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(14),
DOPADOP(1 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(0),
Q => mod_cos_addr(0),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(10),
Q => mod_cos_addr(10),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(11),
Q => mod_cos_addr(11),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(12),
Q => mod_cos_addr(12),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(13),
Q => mod_cos_addr(13),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(1),
Q => mod_cos_addr(1),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(2),
Q => mod_cos_addr(2),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(3),
Q => mod_cos_addr(3),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(4),
Q => mod_cos_addr(4),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(5),
Q => mod_cos_addr(5),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(6),
Q => mod_cos_addr(6),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(7),
Q => mod_cos_addr(7),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(8),
Q => mod_cos_addr(8),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(9),
Q => mod_cos_addr(9),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(0),
Q => mod_sin_addr(0),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(10),
Q => mod_sin_addr(10),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(11),
Q => mod_sin_addr(11),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(12),
Q => mod_sin_addr(12),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(13),
Q => mod_sin_addr(13),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(1),
Q => mod_sin_addr(1),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(2),
Q => mod_sin_addr(2),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(3),
Q => mod_sin_addr(3),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(4),
Q => mod_sin_addr(4),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(5),
Q => mod_sin_addr(5),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(6),
Q => mod_sin_addr(6),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(7),
Q => mod_sin_addr(7),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(8),
Q => mod_sin_addr(8),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(9),
Q => mod_sin_addr(9),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_3\
port map (
aclk => aclk,
m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(7 downto 0),
\out\(7 downto 0) => cos_ls1(7 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_4\
port map (
I1 => \n_6_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I2 => \n_5_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I3 => \n_4_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I4 => \n_3_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I5 => \n_2_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I6 => \n_1_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I7 => \n_0_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I8 => \n_7_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
aclk => aclk,
m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(15 downto 8),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14\
port map (
aclk => aclk,
m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(23 downto 16),
\out\(7 downto 0) => sin_ls1(7 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_2\
port map (
I1 => \n_6_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I2 => \n_5_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I3 => \n_4_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I4 => \n_3_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I5 => \n_2_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I6 => \n_1_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I7 => \n_0_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I8 => \n_7_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
aclk => aclk,
m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(31 downto 24),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized16\
port map (
DOBDO(0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0),
I1 => \n_22_i_rtl.i_quarter_table.i_addr_reg_c\,
I2 => \n_21_i_rtl.i_quarter_table.i_addr_reg_c\,
I3 => \n_20_i_rtl.i_quarter_table.i_addr_reg_c\,
I4 => \n_19_i_rtl.i_quarter_table.i_addr_reg_c\,
I5 => \n_17_i_rtl.i_quarter_table.i_addr_reg_c\,
I6 => \n_16_i_rtl.i_quarter_table.i_addr_reg_c\,
I7 => \n_15_i_rtl.i_quarter_table.i_addr_reg_c\,
I8 => \n_23_i_rtl.i_quarter_table.i_addr_reg_c\,
aclk => aclk,
\out\(8 downto 0) => cos_ls1(8 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_1\
port map (
I1 => \n_18_i_rtl.i_quarter_table.i_addr_reg_c\,
I2 => \n_30_i_rtl.i_quarter_table.i_addr_reg_c\,
I3 => \n_29_i_rtl.i_quarter_table.i_addr_reg_c\,
I4 => \n_28_i_rtl.i_quarter_table.i_addr_reg_c\,
I5 => \n_27_i_rtl.i_quarter_table.i_addr_reg_c\,
I6 => \n_26_i_rtl.i_quarter_table.i_addr_reg_c\,
I7 => \n_25_i_rtl.i_quarter_table.i_addr_reg_c\,
I8 => \n_24_i_rtl.i_quarter_table.i_addr_reg_c\,
O1 => \n_0_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O2 => \n_1_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O3 => \n_2_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O4 => \n_3_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O5 => \n_4_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O6 => \n_5_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O7 => \n_6_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O8 => \n_7_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
aclk => aclk,
\out\(0) => cos_ls1(8),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_original_sin_ls\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized16_5\
port map (
I1 => \n_9_i_rtl.i_quarter_table.i_addr_reg_c\,
I2 => \n_8_i_rtl.i_quarter_table.i_addr_reg_c\,
I3 => \n_10_i_rtl.i_quarter_table.i_addr_reg_c\,
I4 => \n_11_i_rtl.i_quarter_table.i_addr_reg_c\,
I5 => \n_13_i_rtl.i_quarter_table.i_addr_reg_c\,
I6 => \n_31_i_rtl.i_quarter_table.i_addr_reg_c\,
I7 => \n_12_i_rtl.i_quarter_table.i_addr_reg_c\,
I8 => \n_14_i_rtl.i_quarter_table.i_addr_reg_c\,
I9(0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(0),
aclk => aclk,
\out\(8 downto 0) => sin_ls1(8 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_6\
port map (
I1 => \n_1_i_rtl.i_quarter_table.i_addr_reg_c\,
I2 => \n_2_i_rtl.i_quarter_table.i_addr_reg_c\,
I3 => \n_3_i_rtl.i_quarter_table.i_addr_reg_c\,
I4 => \n_4_i_rtl.i_quarter_table.i_addr_reg_c\,
I5 => \n_5_i_rtl.i_quarter_table.i_addr_reg_c\,
I6 => \n_6_i_rtl.i_quarter_table.i_addr_reg_c\,
I7 => \n_7_i_rtl.i_quarter_table.i_addr_reg_c\,
O1 => \n_0_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O2 => \n_1_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O3 => \n_2_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O4 => \n_3_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O5 => \n_4_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O6 => \n_5_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O7 => \n_6_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O8 => \n_7_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
aclk => aclk,
invert_sin => invert_sin,
\out\(0) => sin_ls1(8),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(0),
Q => cos_addr(0),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(10),
Q => cos_addr(10),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(11),
Q => cos_addr(11),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(12),
Q => cos_addr(12),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(13),
Q => cos_addr(13),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(1),
Q => cos_addr(1),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(2),
Q => cos_addr(2),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(3),
Q => cos_addr(3),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(4),
Q => cos_addr(4),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(5),
Q => cos_addr(5),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(6),
Q => cos_addr(6),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(7),
Q => cos_addr(7),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(8),
Q => cos_addr(8),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(9),
Q => cos_addr(9),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(0),
Q => sin_addr(0),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(10),
Q => sin_addr(10),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(11),
Q => sin_addr(11),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(12),
Q => sin_addr(12),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(13),
Q => sin_addr(13),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(1),
Q => sin_addr(1),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(2),
Q => sin_addr(2),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(3),
Q => sin_addr(3),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(4),
Q => sin_addr(4),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(5),
Q => sin_addr(5),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(6),
Q => sin_addr(6),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(7),
Q => sin_addr(7),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(8),
Q => sin_addr(8),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(9),
Q => sin_addr(9),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsdds_compiler_v6_0_core is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
reg_s_phase_fifo_din : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
end ddsdds_compiler_v6_0_core;
architecture STRUCTURE of ddsdds_compiler_v6_0_core is
signal acc_phase_shaped : STD_LOGIC_VECTOR ( 15 downto 14 );
signal asyn_mod_sin_addr : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \n_16_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_17_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_18_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_19_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_20_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_21_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_22_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_23_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_24_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_25_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_26_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_27_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_28_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_29_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
begin
\I_PHASEGEN.i_conventional_accum.i_accum\: entity work.ddsaccum
port map (
D(13 downto 0) => asyn_mod_sin_addr(13 downto 0),
I1(13) => \n_16_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(12) => \n_17_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(11) => \n_18_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(10) => \n_19_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(9) => \n_20_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(8) => \n_21_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(7) => \n_22_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(6) => \n_23_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(5) => \n_24_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(4) => \n_25_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(3) => \n_26_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(2) => \n_27_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(1) => \n_28_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(0) => \n_29_I_PHASEGEN.i_conventional_accum.i_accum\,
L(1 downto 0) => acc_phase_shaped(15 downto 14),
aclk => aclk,
reg_s_phase_fifo_din(15 downto 0) => reg_s_phase_fifo_din(15 downto 0),
s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\I_SINCOS.i_std_rom.i_rom\: entity work.\ddssin_cos__parameterized0\
port map (
D(13 downto 0) => asyn_mod_sin_addr(13 downto 0),
I1(13) => \n_16_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(12) => \n_17_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(11) => \n_18_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(10) => \n_19_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(9) => \n_20_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(8) => \n_21_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(7) => \n_22_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(6) => \n_23_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(5) => \n_24_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(4) => \n_25_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(3) => \n_26_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(2) => \n_27_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(1) => \n_28_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(0) => \n_29_I_PHASEGEN.i_conventional_accum.i_accum\,
L(1 downto 0) => acc_phase_shaped(15 downto 14),
aclk => aclk,
m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rdy.rdy_logic\: entity work.ddsdds_compiler_v6_0_rdy
port map (
aclk => aclk,
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsdds_compiler_v6_0_viv__parameterized0\ is
port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tready : out STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_phase_tlast : in STD_LOGIC;
s_axis_phase_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tvalid : in STD_LOGIC;
s_axis_config_tready : out STD_LOGIC;
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tlast : in STD_LOGIC;
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tready : in STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_data_tlast : out STD_LOGIC;
m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tvalid : out STD_LOGIC;
m_axis_phase_tready : in STD_LOGIC;
m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tlast : out STD_LOGIC;
m_axis_phase_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
event_pinc_invalid : out STD_LOGIC;
event_poff_invalid : out STD_LOGIC;
event_phase_in_invalid : out STD_LOGIC;
event_s_phase_tlast_missing : out STD_LOGIC;
event_s_phase_tlast_unexpected : out STD_LOGIC;
event_s_phase_chanid_incorrect : out STD_LOGIC;
event_s_config_tlast_missing : out STD_LOGIC;
event_s_config_tlast_unexpected : out STD_LOGIC;
debug_axi_pinc_in : out STD_LOGIC_VECTOR ( 15 downto 0 );
debug_axi_poff_in : out STD_LOGIC_VECTOR ( 15 downto 0 );
debug_axi_resync_in : out STD_LOGIC;
debug_axi_chan_in : out STD_LOGIC_VECTOR ( 0 to 0 );
debug_core_nd : out STD_LOGIC;
debug_phase : out STD_LOGIC_VECTOR ( 15 downto 0 );
debug_phase_nd : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "dds_compiler_v6_0_viv";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "zynq";
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 9;
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 16;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_LATENCY : integer;
attribute C_LATENCY of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 7;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 2;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 16;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 16;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_RESYNC : integer;
attribute C_RESYNC of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_POR_MODE : integer;
attribute C_POR_MODE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 16;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 32;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "yes";
end \ddsdds_compiler_v6_0_viv__parameterized0\;
architecture STRUCTURE of \ddsdds_compiler_v6_0_viv__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal reg_s_phase_fifo_din : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
debug_axi_chan_in(0) <= \<const0>\;
debug_axi_pinc_in(15) <= \<const0>\;
debug_axi_pinc_in(14) <= \<const0>\;
debug_axi_pinc_in(13) <= \<const0>\;
debug_axi_pinc_in(12) <= \<const0>\;
debug_axi_pinc_in(11) <= \<const0>\;
debug_axi_pinc_in(10) <= \<const0>\;
debug_axi_pinc_in(9) <= \<const0>\;
debug_axi_pinc_in(8) <= \<const0>\;
debug_axi_pinc_in(7) <= \<const0>\;
debug_axi_pinc_in(6) <= \<const0>\;
debug_axi_pinc_in(5) <= \<const0>\;
debug_axi_pinc_in(4) <= \<const0>\;
debug_axi_pinc_in(3) <= \<const0>\;
debug_axi_pinc_in(2) <= \<const0>\;
debug_axi_pinc_in(1) <= \<const0>\;
debug_axi_pinc_in(0) <= \<const0>\;
debug_axi_poff_in(15) <= \<const0>\;
debug_axi_poff_in(14) <= \<const0>\;
debug_axi_poff_in(13) <= \<const0>\;
debug_axi_poff_in(12) <= \<const0>\;
debug_axi_poff_in(11) <= \<const0>\;
debug_axi_poff_in(10) <= \<const0>\;
debug_axi_poff_in(9) <= \<const0>\;
debug_axi_poff_in(8) <= \<const0>\;
debug_axi_poff_in(7) <= \<const0>\;
debug_axi_poff_in(6) <= \<const0>\;
debug_axi_poff_in(5) <= \<const0>\;
debug_axi_poff_in(4) <= \<const0>\;
debug_axi_poff_in(3) <= \<const0>\;
debug_axi_poff_in(2) <= \<const0>\;
debug_axi_poff_in(1) <= \<const0>\;
debug_axi_poff_in(0) <= \<const0>\;
debug_axi_resync_in <= \<const0>\;
debug_core_nd <= \<const0>\;
debug_phase(15) <= \<const0>\;
debug_phase(14) <= \<const0>\;
debug_phase(13) <= \<const0>\;
debug_phase(12) <= \<const0>\;
debug_phase(11) <= \<const0>\;
debug_phase(10) <= \<const0>\;
debug_phase(9) <= \<const0>\;
debug_phase(8) <= \<const0>\;
debug_phase(7) <= \<const0>\;
debug_phase(6) <= \<const0>\;
debug_phase(5) <= \<const0>\;
debug_phase(4) <= \<const0>\;
debug_phase(3) <= \<const0>\;
debug_phase(2) <= \<const0>\;
debug_phase(1) <= \<const0>\;
debug_phase(0) <= \<const0>\;
debug_phase_nd <= \<const0>\;
event_phase_in_invalid <= \<const0>\;
event_pinc_invalid <= \<const0>\;
event_poff_invalid <= \<const0>\;
event_s_config_tlast_missing <= \<const0>\;
event_s_config_tlast_unexpected <= \<const0>\;
event_s_phase_chanid_incorrect <= \<const0>\;
event_s_phase_tlast_missing <= \<const0>\;
event_s_phase_tlast_unexpected <= \<const0>\;
m_axis_data_tlast <= \<const0>\;
m_axis_data_tuser(0) <= \<const0>\;
m_axis_phase_tdata(0) <= \<const0>\;
m_axis_phase_tlast <= \<const0>\;
m_axis_phase_tuser(0) <= \<const0>\;
m_axis_phase_tvalid <= \<const0>\;
s_axis_config_tready <= \<const0>\;
s_axis_phase_tready <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\has_s_phase.ce_i_delay\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized0\
port map (
aclk => aclk
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(0),
Q => reg_s_phase_fifo_din(0),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(10),
Q => reg_s_phase_fifo_din(10),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(11),
Q => reg_s_phase_fifo_din(11),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(12),
Q => reg_s_phase_fifo_din(12),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(13),
Q => reg_s_phase_fifo_din(13),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(14),
Q => reg_s_phase_fifo_din(14),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(15),
Q => reg_s_phase_fifo_din(15),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(1),
Q => reg_s_phase_fifo_din(1),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(2),
Q => reg_s_phase_fifo_din(2),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(3),
Q => reg_s_phase_fifo_din(3),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(4),
Q => reg_s_phase_fifo_din(4),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(5),
Q => reg_s_phase_fifo_din(5),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(6),
Q => reg_s_phase_fifo_din(6),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(7),
Q => reg_s_phase_fifo_din(7),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(8),
Q => reg_s_phase_fifo_din(8),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(9),
Q => reg_s_phase_fifo_din(9),
R => \<const0>\
);
i_dds: entity work.ddsdds_compiler_v6_0_core
port map (
aclk => aclk,
m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0),
reg_s_phase_fifo_din(15 downto 0) => reg_s_phase_fifo_din(15 downto 0),
s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_has_nd_rdy_pipe.channel_pipe\: entity work.ddsxbip_pipe_v3_0_viv_0
port map (
aclk => aclk,
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_has_nd_rdy_pipe.valid_phase_read_del\: entity work.ddsxbip_pipe_v3_0_viv
port map (
aclk => aclk,
m_axis_data_tvalid => m_axis_data_tvalid,
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsdds_compiler_v6_0__parameterized0\ is
port (
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
aclk : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsdds_compiler_v6_0__parameterized0\ : entity is "dds_compiler_v6_0";
end \ddsdds_compiler_v6_0__parameterized0\;
architecture STRUCTURE of \ddsdds_compiler_v6_0__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal NLW_i_synth_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_core_nd_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_phase_nd_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_phase_in_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_pinc_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_poff_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_data_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_phase_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_config_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_phase_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_axi_chan_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_debug_axi_pinc_in_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_i_synth_debug_axi_poff_in_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_i_synth_debug_phase_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_i_synth_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_m_axis_phase_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_m_axis_phase_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of i_synth : label is 16;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of i_synth : label is 0;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of i_synth : label is 1;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of i_synth : label is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of i_synth : label is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of i_synth : label is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of i_synth : label is 0;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of i_synth : label is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of i_synth : label is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of i_synth : label is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of i_synth : label is 0;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of i_synth : label is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of i_synth : label is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of i_synth : label is 1;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of i_synth : label is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of i_synth : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of i_synth : label is 7;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of i_synth : label is 1;
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of i_synth : label is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of i_synth : label is 9;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of i_synth : label is 0;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of i_synth : label is 32;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of i_synth : label is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of i_synth : label is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of i_synth : label is 0;
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of i_synth : label is 0;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of i_synth : label is 2;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of i_synth : label is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of i_synth : label is 16;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of i_synth : label is 16;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of i_synth : label is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of i_synth : label is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE : integer;
attribute C_POR_MODE of i_synth : label is 0;
attribute C_RESYNC : integer;
attribute C_RESYNC of i_synth : label is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of i_synth : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of i_synth : label is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of i_synth : label is 16;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of i_synth : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of i_synth : label is "zynq";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of i_synth : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
i_synth: entity work.\ddsdds_compiler_v6_0_viv__parameterized0\
port map (
aclk => aclk,
aclken => \<const1>\,
aresetn => \<const1>\,
debug_axi_chan_in(0) => NLW_i_synth_debug_axi_chan_in_UNCONNECTED(0),
debug_axi_pinc_in(15 downto 0) => NLW_i_synth_debug_axi_pinc_in_UNCONNECTED(15 downto 0),
debug_axi_poff_in(15 downto 0) => NLW_i_synth_debug_axi_poff_in_UNCONNECTED(15 downto 0),
debug_axi_resync_in => NLW_i_synth_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => NLW_i_synth_debug_core_nd_UNCONNECTED,
debug_phase(15 downto 0) => NLW_i_synth_debug_phase_UNCONNECTED(15 downto 0),
debug_phase_nd => NLW_i_synth_debug_phase_nd_UNCONNECTED,
event_phase_in_invalid => NLW_i_synth_event_phase_in_invalid_UNCONNECTED,
event_pinc_invalid => NLW_i_synth_event_pinc_invalid_UNCONNECTED,
event_poff_invalid => NLW_i_synth_event_poff_invalid_UNCONNECTED,
event_s_config_tlast_missing => NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED,
event_s_config_tlast_unexpected => NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED,
event_s_phase_chanid_incorrect => NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED,
event_s_phase_tlast_missing => NLW_i_synth_event_s_phase_tlast_missing_UNCONNECTED,
event_s_phase_tlast_unexpected => NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED,
m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0),
m_axis_data_tlast => NLW_i_synth_m_axis_data_tlast_UNCONNECTED,
m_axis_data_tready => \<const0>\,
m_axis_data_tuser(0) => NLW_i_synth_m_axis_data_tuser_UNCONNECTED(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(0) => NLW_i_synth_m_axis_phase_tdata_UNCONNECTED(0),
m_axis_phase_tlast => NLW_i_synth_m_axis_phase_tlast_UNCONNECTED,
m_axis_phase_tready => \<const0>\,
m_axis_phase_tuser(0) => NLW_i_synth_m_axis_phase_tuser_UNCONNECTED(0),
m_axis_phase_tvalid => NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED,
s_axis_config_tdata(0) => \<const0>\,
s_axis_config_tlast => \<const0>\,
s_axis_config_tready => NLW_i_synth_s_axis_config_tready_UNCONNECTED,
s_axis_config_tvalid => \<const0>\,
s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0),
s_axis_phase_tlast => \<const0>\,
s_axis_phase_tready => NLW_i_synth_s_axis_phase_tready_UNCONNECTED,
s_axis_phase_tuser(0) => \<const0>\,
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity dds is
port (
aclk : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of dds : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of dds : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of dds : entity is "dds_compiler_v6_0,Vivado 2013.4";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of dds : entity is "dds,dds_compiler_v6_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of dds : entity is "dds,dds_compiler_v6_0,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dds_compiler,x_ipVersion=6.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,C_XDEVICEFAMILY=zynq,C_MODE_OF_OPERATION=0,C_MODULUS=9,C_ACCUMULATOR_WIDTH=16,C_CHANNELS=1,C_HAS_PHASE_OUT=0,C_HAS_PHASEGEN=1,C_HAS_SINCOS=1,C_LATENCY=7,C_MEM_TYPE=1,C_NEGATIVE_COSINE=0,C_NEGATIVE_SINE=0,C_NOISE_SHAPING=0,C_OUTPUTS_REQUIRED=2,C_OUTPUT_FORM=0,C_OUTPUT_WIDTH=16,C_PHASE_ANGLE_WIDTH=16,C_PHASE_INCREMENT=3,C_PHASE_INCREMENT_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_RESYNC=0,C_PHASE_OFFSET=0,C_PHASE_OFFSET_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_OPTIMISE_GOAL=0,C_USE_DSP48=0,C_POR_MODE=0,C_AMPLITUDE=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_HAS_TLAST=0,C_HAS_TREADY=0,C_HAS_S_PHASE=1,C_S_PHASE_TDATA_WIDTH=16,C_S_PHASE_HAS_TUSER=0,C_S_PHASE_TUSER_WIDTH=1,C_HAS_S_CONFIG=0,C_S_CONFIG_SYNC_MODE=0,C_S_CONFIG_TDATA_WIDTH=1,C_HAS_M_DATA=1,C_M_DATA_TDATA_WIDTH=32,C_M_DATA_HAS_TUSER=0,C_M_DATA_TUSER_WIDTH=1,C_HAS_M_PHASE=0,C_M_PHASE_TDATA_WIDTH=1,C_M_PHASE_HAS_TUSER=0,C_M_PHASE_TUSER_WIDTH=1,C_DEBUG_INTERFACE=0,C_CHAN_WIDTH=1}";
end dds;
architecture STRUCTURE of dds is
begin
U0: entity work.\ddsdds_compiler_v6_0__parameterized0\
port map (
aclk => aclk,
m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0),
m_axis_data_tvalid => m_axis_data_tvalid,
s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
|
-- Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
-- Date : Thu Mar 27 13:22:53 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim /home/keith/Documents/VHDL-lib/top/lab_3/part_2/ip/dds/dds_funcsim.vhdl
-- Design : dds
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddspipe_add__parameterized0\ is
port (
temp : out STD_LOGIC_VECTOR ( 16 downto 0 );
L : in STD_LOGIC_VECTOR ( 15 downto 0 );
reg_s_phase_fifo_din : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddspipe_add__parameterized0\ : entity is "pipe_add";
end \ddspipe_add__parameterized0\;
architecture STRUCTURE of \ddspipe_add__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[11]_i_2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[11]_i_3\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[11]_i_4\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[11]_i_5\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[15]_i_2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[15]_i_3\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[15]_i_4\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[15]_i_5\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[3]_i_2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[3]_i_3\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[3]_i_4\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[3]_i_5\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[7]_i_2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[7]_i_3\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[7]_i_4\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[7]_i_5\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC;
signal \n_1_opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC;
signal \n_1_opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC;
signal \n_1_opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC;
signal \n_1_opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC;
signal \n_2_opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC;
signal \n_2_opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC;
signal \n_2_opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC;
signal \n_2_opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC;
signal \n_3_opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC;
signal \n_3_opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC;
signal \n_3_opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC;
signal \n_3_opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC;
signal \NLW_opt_has_pipe.first_q_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_opt_has_pipe.first_q_reg[16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\opt_has_pipe.first_q[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(11),
I1 => reg_s_phase_fifo_din(11),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(11),
O => \n_0_opt_has_pipe.first_q[11]_i_2\
);
\opt_has_pipe.first_q[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(10),
I1 => reg_s_phase_fifo_din(10),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(10),
O => \n_0_opt_has_pipe.first_q[11]_i_3\
);
\opt_has_pipe.first_q[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(9),
I1 => reg_s_phase_fifo_din(9),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(9),
O => \n_0_opt_has_pipe.first_q[11]_i_4\
);
\opt_has_pipe.first_q[11]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(8),
I1 => reg_s_phase_fifo_din(8),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(8),
O => \n_0_opt_has_pipe.first_q[11]_i_5\
);
\opt_has_pipe.first_q[15]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(15),
I1 => reg_s_phase_fifo_din(15),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(15),
O => \n_0_opt_has_pipe.first_q[15]_i_2\
);
\opt_has_pipe.first_q[15]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(14),
I1 => reg_s_phase_fifo_din(14),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(14),
O => \n_0_opt_has_pipe.first_q[15]_i_3\
);
\opt_has_pipe.first_q[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(13),
I1 => reg_s_phase_fifo_din(13),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(13),
O => \n_0_opt_has_pipe.first_q[15]_i_4\
);
\opt_has_pipe.first_q[15]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(12),
I1 => reg_s_phase_fifo_din(12),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(12),
O => \n_0_opt_has_pipe.first_q[15]_i_5\
);
\opt_has_pipe.first_q[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(3),
I1 => reg_s_phase_fifo_din(3),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(3),
O => \n_0_opt_has_pipe.first_q[3]_i_2\
);
\opt_has_pipe.first_q[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(2),
I1 => reg_s_phase_fifo_din(2),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(2),
O => \n_0_opt_has_pipe.first_q[3]_i_3\
);
\opt_has_pipe.first_q[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(1),
I1 => reg_s_phase_fifo_din(1),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(1),
O => \n_0_opt_has_pipe.first_q[3]_i_4\
);
\opt_has_pipe.first_q[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(0),
I1 => reg_s_phase_fifo_din(0),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(0),
O => \n_0_opt_has_pipe.first_q[3]_i_5\
);
\opt_has_pipe.first_q[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(7),
I1 => reg_s_phase_fifo_din(7),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(7),
O => \n_0_opt_has_pipe.first_q[7]_i_2\
);
\opt_has_pipe.first_q[7]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(6),
I1 => reg_s_phase_fifo_din(6),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(6),
O => \n_0_opt_has_pipe.first_q[7]_i_3\
);
\opt_has_pipe.first_q[7]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(5),
I1 => reg_s_phase_fifo_din(5),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(5),
O => \n_0_opt_has_pipe.first_q[7]_i_4\
);
\opt_has_pipe.first_q[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(4),
I1 => reg_s_phase_fifo_din(4),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(4),
O => \n_0_opt_has_pipe.first_q[7]_i_5\
);
\opt_has_pipe.first_q_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_opt_has_pipe.first_q_reg[7]_i_1\,
CO(3) => \n_0_opt_has_pipe.first_q_reg[11]_i_1\,
CO(2) => \n_1_opt_has_pipe.first_q_reg[11]_i_1\,
CO(1) => \n_2_opt_has_pipe.first_q_reg[11]_i_1\,
CO(0) => \n_3_opt_has_pipe.first_q_reg[11]_i_1\,
CYINIT => \<const0>\,
DI(3 downto 0) => L(11 downto 8),
O(3 downto 0) => temp(11 downto 8),
S(3) => \n_0_opt_has_pipe.first_q[11]_i_2\,
S(2) => \n_0_opt_has_pipe.first_q[11]_i_3\,
S(1) => \n_0_opt_has_pipe.first_q[11]_i_4\,
S(0) => \n_0_opt_has_pipe.first_q[11]_i_5\
);
\opt_has_pipe.first_q_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_opt_has_pipe.first_q_reg[11]_i_1\,
CO(3) => \n_0_opt_has_pipe.first_q_reg[15]_i_1\,
CO(2) => \n_1_opt_has_pipe.first_q_reg[15]_i_1\,
CO(1) => \n_2_opt_has_pipe.first_q_reg[15]_i_1\,
CO(0) => \n_3_opt_has_pipe.first_q_reg[15]_i_1\,
CYINIT => \<const0>\,
DI(3 downto 0) => L(15 downto 12),
O(3 downto 0) => temp(15 downto 12),
S(3) => \n_0_opt_has_pipe.first_q[15]_i_2\,
S(2) => \n_0_opt_has_pipe.first_q[15]_i_3\,
S(1) => \n_0_opt_has_pipe.first_q[15]_i_4\,
S(0) => \n_0_opt_has_pipe.first_q[15]_i_5\
);
\opt_has_pipe.first_q_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_opt_has_pipe.first_q_reg[15]_i_1\,
CO(3 downto 1) => \NLW_opt_has_pipe.first_q_reg[16]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => temp(16),
CYINIT => \<const0>\,
DI(3) => \<const0>\,
DI(2) => \<const0>\,
DI(1) => \<const0>\,
DI(0) => \<const0>\,
O(3 downto 0) => \NLW_opt_has_pipe.first_q_reg[16]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \<const0>\,
S(2) => \<const0>\,
S(1) => \<const0>\,
S(0) => \<const1>\
);
\opt_has_pipe.first_q_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \<const0>\,
CO(3) => \n_0_opt_has_pipe.first_q_reg[3]_i_1\,
CO(2) => \n_1_opt_has_pipe.first_q_reg[3]_i_1\,
CO(1) => \n_2_opt_has_pipe.first_q_reg[3]_i_1\,
CO(0) => \n_3_opt_has_pipe.first_q_reg[3]_i_1\,
CYINIT => \<const0>\,
DI(3 downto 0) => L(3 downto 0),
O(3 downto 0) => temp(3 downto 0),
S(3) => \n_0_opt_has_pipe.first_q[3]_i_2\,
S(2) => \n_0_opt_has_pipe.first_q[3]_i_3\,
S(1) => \n_0_opt_has_pipe.first_q[3]_i_4\,
S(0) => \n_0_opt_has_pipe.first_q[3]_i_5\
);
\opt_has_pipe.first_q_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_opt_has_pipe.first_q_reg[3]_i_1\,
CO(3) => \n_0_opt_has_pipe.first_q_reg[7]_i_1\,
CO(2) => \n_1_opt_has_pipe.first_q_reg[7]_i_1\,
CO(1) => \n_2_opt_has_pipe.first_q_reg[7]_i_1\,
CO(0) => \n_3_opt_has_pipe.first_q_reg[7]_i_1\,
CYINIT => \<const0>\,
DI(3 downto 0) => L(7 downto 4),
O(3 downto 0) => temp(7 downto 4),
S(3) => \n_0_opt_has_pipe.first_q[7]_i_2\,
S(2) => \n_0_opt_has_pipe.first_q[7]_i_3\,
S(1) => \n_0_opt_has_pipe.first_q[7]_i_4\,
S(0) => \n_0_opt_has_pipe.first_q[7]_i_5\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsxbip_pipe_v3_0_viv is
port (
m_axis_data_tvalid : out STD_LOGIC;
aclk : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC
);
end ddsxbip_pipe_v3_0_viv;
architecture STRUCTURE of ddsxbip_pipe_v3_0_viv is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal first_q : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of first_q : signal is "true";
signal \n_0_opt_has_pipe.first_q[0]_i_1__0\ : STD_LOGIC;
signal \n_0_opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\ : STD_LOGIC;
signal rdy_stream_i : STD_LOGIC;
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute srl_bus_name : string;
attribute srl_bus_name of \opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\ : label is "\U0/i_synth /\i_has_nd_rdy_pipe.valid_phase_read_del/opt_has_pipe.i_pipe[6].pipe_reg[6] ";
attribute srl_name : string;
attribute srl_name of \opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\ : label is "\U0/i_synth /\i_has_nd_rdy_pipe.valid_phase_read_del/opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5 ";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
m_axis_data_tvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axis_phase_tvalid,
I1 => rdy_stream_i,
O => m_axis_data_tvalid
);
\opt_has_pipe.first_q[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axis_phase_tvalid,
I1 => first_q,
O => \n_0_opt_has_pipe.first_q[0]_i_1__0\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \n_0_opt_has_pipe.first_q[0]_i_1__0\,
Q => first_q,
R => \<const0>\
);
\opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \<const0>\,
A1 => \<const0>\,
A2 => \<const1>\,
A3 => \<const0>\,
CE => s_axis_phase_tvalid,
CLK => aclk,
D => first_q,
Q => \n_0_opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\
);
\opt_has_pipe.i_pipe[7].pipe_reg[7][0]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \n_0_opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\,
Q => rdy_stream_i,
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsxbip_pipe_v3_0_viv_0 is
port (
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ddsxbip_pipe_v3_0_viv_0 : entity is "xbip_pipe_v3_0_viv";
end ddsxbip_pipe_v3_0_viv_0;
architecture STRUCTURE of ddsxbip_pipe_v3_0_viv_0 is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of first_q : signal is "true";
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \<const0>\,
Q => first_q,
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized0\ is
port (
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized0\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized0\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal first_q : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of first_q : signal is "true";
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \<const1>\,
Q => first_q,
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized12\ is
port (
invert_sin : out STD_LOGIC;
O1 : out STD_LOGIC;
O2 : out STD_LOGIC;
O3 : out STD_LOGIC;
O4 : out STD_LOGIC;
O5 : out STD_LOGIC;
O6 : out STD_LOGIC;
O7 : out STD_LOGIC;
O8 : out STD_LOGIC;
O9 : out STD_LOGIC;
O10 : out STD_LOGIC;
O11 : out STD_LOGIC;
O12 : out STD_LOGIC;
O13 : out STD_LOGIC;
O14 : out STD_LOGIC;
O15 : out STD_LOGIC;
O16 : out STD_LOGIC;
O17 : out STD_LOGIC;
O18 : out STD_LOGIC;
O19 : out STD_LOGIC;
O20 : out STD_LOGIC;
O21 : out STD_LOGIC;
O22 : out STD_LOGIC;
O23 : out STD_LOGIC;
O24 : out STD_LOGIC;
O25 : out STD_LOGIC;
O26 : out STD_LOGIC;
O27 : out STD_LOGIC;
O28 : out STD_LOGIC;
O29 : out STD_LOGIC;
O30 : out STD_LOGIC;
O31 : out STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 14 downto 0 );
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\ : in STD_LOGIC_VECTOR ( 14 downto 0 );
L : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized12\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized12\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized12\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^o18\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^invert_sin\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[8]_i_2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[8]_i_2__0\ : STD_LOGIC;
signal \n_0_opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[0]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[0]_i_1__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[1]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[1]_i_1__0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[1]_i_1__1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[1]_i_1__2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[2]_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[2]_i_1__1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[2]_i_1__2\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[3]_i_1__1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[3]_i_1__4\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[4]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[4]_i_1__2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[5]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[5]_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[5]_i_1__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[5]_i_1__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[6]_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[6]_i_1__2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[7]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[7]_i_1__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[8]_i_1\ : label is "soft_lutpair0";
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute srl_bus_name : string;
attribute srl_bus_name of \opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\ : label is "\U0/i_synth /\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3] ";
attribute srl_name : string;
attribute srl_name of \opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\ : label is "\U0/i_synth /\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2 ";
attribute srl_bus_name of \opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\ : label is "\U0/i_synth /\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3] ";
attribute srl_name of \opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\ : label is "\U0/i_synth /\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2 ";
begin
O18 <= \^o18\;
invert_sin <= \^invert_sin\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\opt_has_pipe.first_q[0]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(8),
O => O7
);
\opt_has_pipe.first_q[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(8),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O24
);
\opt_has_pipe.first_q[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(9),
O => O6
);
\opt_has_pipe.first_q[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \out\(1),
I1 => \out\(0),
I2 => \^invert_sin\,
O => O14
);
\opt_has_pipe.first_q[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"D728"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0),
I1 => \^invert_sin\,
I2 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I3 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1),
O => O23
);
\opt_has_pipe.first_q[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(9),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O25
);
\opt_has_pipe.first_q[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(10),
O => O5
);
\opt_has_pipe.first_q[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1EF0"
)
port map (
I0 => \out\(0),
I1 => \out\(1),
I2 => \out\(2),
I3 => \^invert_sin\,
O => O12
);
\opt_has_pipe.first_q[2]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F11F0EE0"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1),
I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0),
I2 => \^invert_sin\,
I3 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I4 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(2),
O => O15
);
\opt_has_pipe.first_q[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(10),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O26
);
\opt_has_pipe.first_q[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(11),
O => O4
);
\opt_has_pipe.first_q[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0101FF00FEFE00"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0),
I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1),
I2 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(2),
I3 => \^invert_sin\,
I4 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(3),
O => O16
);
\opt_has_pipe.first_q[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(11),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O27
);
\opt_has_pipe.first_q[3]_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FEFF00"
)
port map (
I0 => \out\(1),
I1 => \out\(0),
I2 => \out\(2),
I3 => \out\(3),
I4 => \^invert_sin\,
O => O31
);
\opt_has_pipe.first_q[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(12),
O => O3
);
\opt_has_pipe.first_q[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001FFFFFFFE0000"
)
port map (
I0 => \out\(1),
I1 => \out\(0),
I2 => \out\(2),
I3 => \out\(3),
I4 => \^invert_sin\,
I5 => \out\(4),
O => O13
);
\opt_has_pipe.first_q[4]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001FFFFFFFE0000"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(3),
I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(2),
I2 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1),
I3 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0),
I4 => \^o18\,
I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4),
O => O17
);
\opt_has_pipe.first_q[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(12),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O28
);
\opt_has_pipe.first_q[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(13),
O => O2
);
\opt_has_pipe.first_q[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_0_opt_has_pipe.first_q[8]_i_2\,
I1 => \out\(5),
I2 => \^invert_sin\,
O => O11
);
\opt_has_pipe.first_q[5]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D11D2EE2"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4),
I1 => \n_0_opt_has_pipe.first_q[8]_i_2__0\,
I2 => \^invert_sin\,
I3 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I4 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5),
O => O19
);
\opt_has_pipe.first_q[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(13),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O29
);
\opt_has_pipe.first_q[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(14),
O => O1
);
\opt_has_pipe.first_q[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"4B78"
)
port map (
I0 => \out\(5),
I1 => \n_0_opt_has_pipe.first_q[8]_i_2\,
I2 => \out\(6),
I3 => \^invert_sin\,
O => O10
);
\opt_has_pipe.first_q[6]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DF0101DF20FEFE20"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5),
I1 => \n_0_opt_has_pipe.first_q[8]_i_2__0\,
I2 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4),
I3 => \^invert_sin\,
I4 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(6),
O => O20
);
\opt_has_pipe.first_q[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(14),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O30
);
\opt_has_pipe.first_q[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FB7F80"
)
port map (
I0 => \out\(6),
I1 => \n_0_opt_has_pipe.first_q[8]_i_2\,
I2 => \out\(5),
I3 => \out\(7),
I4 => \^invert_sin\,
O => O8
);
\opt_has_pipe.first_q[7]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001F7FFFFFE0800"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(6),
I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4),
I2 => \n_0_opt_has_pipe.first_q[8]_i_2__0\,
I3 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5),
I4 => \^o18\,
I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(7),
O => O21
);
\opt_has_pipe.first_q[7]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
O => \^o18\
);
\opt_has_pipe.first_q[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00048000"
)
port map (
I0 => \out\(6),
I1 => \n_0_opt_has_pipe.first_q[8]_i_2\,
I2 => \out\(5),
I3 => \out\(7),
I4 => \^invert_sin\,
O => O9
);
\opt_has_pipe.first_q[8]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000080000010000"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(6),
I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4),
I2 => \n_0_opt_has_pipe.first_q[8]_i_2__0\,
I3 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5),
I4 => \^o18\,
I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(7),
O => O22
);
\opt_has_pipe.first_q[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \out\(3),
I1 => \out\(2),
I2 => \out\(0),
I3 => \out\(1),
I4 => \out\(4),
I5 => \^invert_sin\,
O => \n_0_opt_has_pipe.first_q[8]_i_2\
);
\opt_has_pipe.first_q[8]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFEFF"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0),
I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1),
I2 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(2),
I3 => \^invert_sin\,
I4 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(3),
O => \n_0_opt_has_pipe.first_q[8]_i_2__0\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => L(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => L(1),
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \<const1>\,
A1 => \<const0>\,
A2 => \<const0>\,
A3 => \<const0>\,
CE => s_axis_phase_tvalid,
CLK => aclk,
D => first_q(0),
Q => \n_0_opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\
);
\opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \<const1>\,
A1 => \<const0>\,
A2 => \<const0>\,
A3 => \<const0>\,
CE => s_axis_phase_tvalid,
CLK => aclk,
D => first_q(1),
Q => \n_0_opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\
);
\opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \n_0_opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\,
Q => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
R => \<const0>\
);
\opt_has_pipe.i_pipe[4].pipe_reg[4][1]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \n_0_opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\,
Q => \^invert_sin\,
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized14\ is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized14\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => m_axis_data_tdata(7)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => m_axis_data_tdata(6)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => m_axis_data_tdata(5)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => m_axis_data_tdata(4)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => m_axis_data_tdata(3)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => m_axis_data_tdata(2)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => m_axis_data_tdata(1)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => m_axis_data_tdata(0)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(1),
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(2),
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(3),
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(4),
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(5),
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(6),
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(7),
Q => first_q(7),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized14_1\ is
port (
O1 : out STD_LOGIC;
O2 : out STD_LOGIC;
O3 : out STD_LOGIC;
O4 : out STD_LOGIC;
O5 : out STD_LOGIC;
O6 : out STD_LOGIC;
O7 : out STD_LOGIC;
O8 : out STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_phase_tvalid : in STD_LOGIC;
I1 : in STD_LOGIC;
aclk : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
I5 : in STD_LOGIC;
I6 : in STD_LOGIC;
I7 : in STD_LOGIC;
I8 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_1\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized14_1\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_1\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \n_0_opt_has_pipe.first_q[7]_i_2__0\ : STD_LOGIC;
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\opt_has_pipe.first_q[0]_i_1__4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(0),
I1 => \out\(0),
O => O8
);
\opt_has_pipe.first_q[1]_i_1__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => first_q(1),
I1 => first_q(0),
I2 => \out\(0),
O => O1
);
\opt_has_pipe.first_q[2]_i_1__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => first_q(2),
I1 => \out\(0),
I2 => first_q(0),
I3 => first_q(1),
O => O2
);
\opt_has_pipe.first_q[3]_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => first_q(1),
I1 => first_q(0),
I2 => \out\(0),
I3 => first_q(2),
I4 => first_q(3),
O => O3
);
\opt_has_pipe.first_q[4]_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => first_q(4),
I1 => first_q(1),
I2 => first_q(0),
I3 => \out\(0),
I4 => first_q(2),
I5 => first_q(3),
O => O4
);
\opt_has_pipe.first_q[5]_i_1__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => first_q(5),
I1 => \n_0_opt_has_pipe.first_q[7]_i_2__0\,
I2 => first_q(4),
O => O5
);
\opt_has_pipe.first_q[6]_i_1__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => first_q(6),
I1 => first_q(4),
I2 => \n_0_opt_has_pipe.first_q[7]_i_2__0\,
I3 => first_q(5),
O => O6
);
\opt_has_pipe.first_q[7]_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => first_q(7),
I1 => first_q(5),
I2 => \n_0_opt_has_pipe.first_q[7]_i_2__0\,
I3 => first_q(4),
I4 => first_q(6),
O => O7
);
\opt_has_pipe.first_q[7]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => first_q(3),
I1 => first_q(2),
I2 => \out\(0),
I3 => first_q(0),
I4 => first_q(1),
O => \n_0_opt_has_pipe.first_q[7]_i_2__0\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I8,
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I7,
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I6,
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I5,
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I4,
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I3,
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I2,
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1,
Q => first_q(7),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized14_2\ is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
I1 : in STD_LOGIC;
aclk : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
I5 : in STD_LOGIC;
I6 : in STD_LOGIC;
I7 : in STD_LOGIC;
I8 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_2\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized14_2\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_2\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => m_axis_data_tdata(7)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => m_axis_data_tdata(6)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => m_axis_data_tdata(5)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => m_axis_data_tdata(4)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => m_axis_data_tdata(3)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => m_axis_data_tdata(2)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => m_axis_data_tdata(1)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => m_axis_data_tdata(0)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I8,
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I7,
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I6,
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I5,
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I4,
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I3,
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I2,
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1,
Q => first_q(7),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized14_3\ is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_3\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized14_3\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_3\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => m_axis_data_tdata(7)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => m_axis_data_tdata(6)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => m_axis_data_tdata(5)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => m_axis_data_tdata(4)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => m_axis_data_tdata(3)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => m_axis_data_tdata(2)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => m_axis_data_tdata(1)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => m_axis_data_tdata(0)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(1),
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(2),
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(3),
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(4),
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(5),
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(6),
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(7),
Q => first_q(7),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized14_4\ is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
I1 : in STD_LOGIC;
aclk : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
I5 : in STD_LOGIC;
I6 : in STD_LOGIC;
I7 : in STD_LOGIC;
I8 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_4\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized14_4\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_4\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => m_axis_data_tdata(7)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => m_axis_data_tdata(6)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => m_axis_data_tdata(5)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => m_axis_data_tdata(4)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => m_axis_data_tdata(3)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => m_axis_data_tdata(2)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => m_axis_data_tdata(1)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => m_axis_data_tdata(0)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I8,
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I7,
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I6,
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I5,
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I4,
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I3,
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I2,
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1,
Q => first_q(7),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized14_6\ is
port (
O1 : out STD_LOGIC;
O2 : out STD_LOGIC;
O3 : out STD_LOGIC;
O4 : out STD_LOGIC;
O5 : out STD_LOGIC;
O6 : out STD_LOGIC;
O7 : out STD_LOGIC;
O8 : out STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_phase_tvalid : in STD_LOGIC;
I1 : in STD_LOGIC;
aclk : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
I5 : in STD_LOGIC;
I6 : in STD_LOGIC;
I7 : in STD_LOGIC;
invert_sin : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_6\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized14_6\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_6\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \n_0_opt_has_pipe.first_q[7]_i_2\ : STD_LOGIC;
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\opt_has_pipe.first_q[0]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(0),
I1 => \out\(0),
O => O8
);
\opt_has_pipe.first_q[1]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => first_q(1),
I1 => first_q(0),
I2 => \out\(0),
O => O1
);
\opt_has_pipe.first_q[2]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => first_q(2),
I1 => \out\(0),
I2 => first_q(0),
I3 => first_q(1),
O => O2
);
\opt_has_pipe.first_q[3]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => first_q(1),
I1 => first_q(0),
I2 => \out\(0),
I3 => first_q(2),
I4 => first_q(3),
O => O3
);
\opt_has_pipe.first_q[4]_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => first_q(4),
I1 => first_q(1),
I2 => first_q(0),
I3 => \out\(0),
I4 => first_q(2),
I5 => first_q(3),
O => O4
);
\opt_has_pipe.first_q[5]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => first_q(5),
I1 => \n_0_opt_has_pipe.first_q[7]_i_2\,
I2 => first_q(4),
O => O5
);
\opt_has_pipe.first_q[6]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => first_q(6),
I1 => first_q(4),
I2 => \n_0_opt_has_pipe.first_q[7]_i_2\,
I3 => first_q(5),
O => O6
);
\opt_has_pipe.first_q[7]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => first_q(7),
I1 => first_q(5),
I2 => \n_0_opt_has_pipe.first_q[7]_i_2\,
I3 => first_q(4),
I4 => first_q(6),
O => O7
);
\opt_has_pipe.first_q[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => first_q(3),
I1 => first_q(2),
I2 => \out\(0),
I3 => first_q(0),
I4 => first_q(1),
O => \n_0_opt_has_pipe.first_q[7]_i_2\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I7,
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I6,
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I5,
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I4,
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I3,
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I2,
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1,
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => invert_sin,
Q => first_q(7),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized16\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
I1 : in STD_LOGIC;
aclk : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
I5 : in STD_LOGIC;
I6 : in STD_LOGIC;
I7 : in STD_LOGIC;
I8 : in STD_LOGIC;
DOBDO : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized16\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized16\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized16\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[8]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(8),
O => \out\(8)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => \out\(7)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => \out\(6)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => \out\(5)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => \out\(4)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => \out\(3)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => \out\(2)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => \out\(1)
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => \out\(0)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => DOBDO(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I8,
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I7,
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I6,
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I5,
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I4,
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I3,
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I2,
Q => first_q(7),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1,
Q => first_q(8),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized16_5\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
I1 : in STD_LOGIC;
aclk : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
I5 : in STD_LOGIC;
I6 : in STD_LOGIC;
I7 : in STD_LOGIC;
I8 : in STD_LOGIC;
I9 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized16_5\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized16_5\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized16_5\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[8]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(8),
O => \out\(8)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => \out\(7)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => \out\(6)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => \out\(5)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => \out\(4)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => \out\(3)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => \out\(2)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => \out\(1)
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => \out\(0)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I9(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I8,
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I7,
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I6,
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I5,
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I4,
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I3,
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I2,
Q => first_q(7),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1,
Q => first_q(8),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized2\ is
port (
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
mutant_x_op : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized2\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized2\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized2\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of first_q : signal is "true";
signal \n_0_opt_has_pipe.first_q[0]_i_1\ : STD_LOGIC;
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\opt_has_pipe.first_q[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => mutant_x_op(1),
I1 => mutant_x_op(0),
I2 => mutant_x_op(2),
O => \n_0_opt_has_pipe.first_q[0]_i_1\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \n_0_opt_has_pipe.first_q[0]_i_1\,
Q => first_q,
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized8\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
I1 : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
temp : in STD_LOGIC_VECTOR ( 16 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized8\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized8\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized8\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 16 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[10]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[11]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[12]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[13]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[14]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[15]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[16]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[8]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[9]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(15),
O => \out\(15)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(14),
O => \out\(14)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => \out\(5)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => \out\(4)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => \out\(3)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => \out\(2)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => \out\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => \out\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(13),
O => \out\(13)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(12),
O => \out\(12)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(11),
O => \out\(11)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(10),
O => \out\(10)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(9),
O => \out\(9)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(8),
O => \out\(8)
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => \out\(7)
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => \out\(6)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(0),
O => I1(0)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(10),
O => I1(10)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(11),
O => I1(11)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(12),
O => I1(12)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(13),
O => I1(13)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(1),
O => I1(1)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(2),
O => I1(2)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(3),
O => I1(3)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(4),
O => I1(4)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(5),
O => I1(5)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(6),
O => I1(6)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(7),
O => I1(7)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(8),
O => I1(8)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(9),
O => I1(9)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(0),
I1 => first_q(14),
O => D(0)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(10),
I1 => first_q(14),
O => D(10)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(11),
I1 => first_q(14),
O => D(11)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(12),
I1 => first_q(14),
O => D(12)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(13),
I1 => first_q(14),
O => D(13)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(1),
I1 => first_q(14),
O => D(1)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(2),
I1 => first_q(14),
O => D(2)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(3),
I1 => first_q(14),
O => D(3)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(4),
I1 => first_q(14),
O => D(4)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(5),
I1 => first_q(14),
O => D(5)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(6),
I1 => first_q(14),
O => D(6)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(7),
I1 => first_q(14),
O => D(7)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(8),
I1 => first_q(14),
O => D(8)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(9),
I1 => first_q(14),
O => D(9)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(10),
Q => first_q(10),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(11),
Q => first_q(11),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(12),
Q => first_q(12),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(13),
Q => first_q(13),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(14),
Q => first_q(14),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(15),
Q => first_q(15),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(16),
Q => first_q(16),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(1),
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(2),
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(3),
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(4),
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(5),
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(6),
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(7),
Q => first_q(7),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(8),
Q => first_q(8),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(9),
Q => first_q(9),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsaccum is
port (
L : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
I1 : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
reg_s_phase_fifo_din : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
end ddsaccum;
architecture STRUCTURE of ddsaccum is
signal \^l\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal acc_phase_shaped : STD_LOGIC_VECTOR ( 13 downto 0 );
signal temp : STD_LOGIC_VECTOR ( 16 downto 0 );
begin
L(1 downto 0) <= \^l\(1 downto 0);
\i_fabric.i_common.i_phase_acc\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized8\
port map (
D(13 downto 0) => D(13 downto 0),
I1(13 downto 0) => I1(13 downto 0),
aclk => aclk,
\out\(15 downto 14) => \^l\(1 downto 0),
\out\(13 downto 0) => acc_phase_shaped(13 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid,
temp(16 downto 0) => temp(16 downto 0)
);
\i_fabric.i_one_channel.i_accum\: entity work.\ddspipe_add__parameterized0\
port map (
L(15 downto 14) => \^l\(1 downto 0),
L(13 downto 0) => acc_phase_shaped(13 downto 0),
reg_s_phase_fifo_din(15 downto 0) => reg_s_phase_fifo_din(15 downto 0),
s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid,
temp(16 downto 0) => temp(16 downto 0)
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsdds_compiler_v6_0_rdy is
port (
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC
);
end ddsdds_compiler_v6_0_rdy;
architecture STRUCTURE of ddsdds_compiler_v6_0_rdy is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal mutant_x_op : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \n_0_mutant_x_op[0]_i_1\ : STD_LOGIC;
signal \n_0_mutant_x_op[1]_i_1\ : STD_LOGIC;
signal \n_0_mutant_x_op[2]_i_1\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \mutant_x_op[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \mutant_x_op[2]_i_1\ : label is "soft_lutpair12";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\i_single_channel.i_non_trivial_lat.i_rdy\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized2\
port map (
aclk => aclk,
mutant_x_op(2 downto 0) => mutant_x_op(2 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\mutant_x_op[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5A58"
)
port map (
I0 => s_axis_phase_tvalid,
I1 => mutant_x_op(2),
I2 => mutant_x_op(0),
I3 => mutant_x_op(1),
O => \n_0_mutant_x_op[0]_i_1\
);
\mutant_x_op[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F508"
)
port map (
I0 => s_axis_phase_tvalid,
I1 => mutant_x_op(2),
I2 => mutant_x_op(0),
I3 => mutant_x_op(1),
O => \n_0_mutant_x_op[1]_i_1\
);
\mutant_x_op[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCC4"
)
port map (
I0 => s_axis_phase_tvalid,
I1 => mutant_x_op(2),
I2 => mutant_x_op(0),
I3 => mutant_x_op(1),
O => \n_0_mutant_x_op[2]_i_1\
);
\mutant_x_op_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \n_0_mutant_x_op[0]_i_1\,
Q => mutant_x_op(0),
R => \<const0>\
);
\mutant_x_op_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => \<const1>\,
D => \n_0_mutant_x_op[1]_i_1\,
Q => mutant_x_op(1),
R => \<const0>\
);
\mutant_x_op_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => \<const1>\,
D => \n_0_mutant_x_op[2]_i_1\,
Q => mutant_x_op(2),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddssin_cos__parameterized0\ is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
L : in STD_LOGIC_VECTOR ( 1 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddssin_cos__parameterized0\ : entity is "sin_cos";
end \ddssin_cos__parameterized0\;
architecture STRUCTURE of \ddssin_cos__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal cos_addr : STD_LOGIC_VECTOR ( 13 downto 0 );
signal cos_ls1 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\ : STD_LOGIC_VECTOR ( 14 downto 0 );
signal \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal invert_sin : STD_LOGIC;
signal mod_cos_addr : STD_LOGIC_VECTOR ( 13 downto 0 );
signal mod_sin_addr : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \n_0_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_0_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_10_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_11_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_12_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_13_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_14_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_15_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_16_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_17_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_18_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_19_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_1_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_1_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_1_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_20_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_21_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_22_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_23_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_24_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_25_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_26_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_27_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_28_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_29_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_2_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_2_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_2_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_30_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_31_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_3_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_3_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_3_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_4_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_4_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_4_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_5_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_5_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_5_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_6_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_6_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_6_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_7_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_7_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_7_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_8_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_9_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 6 downto 0 );
signal sin_addr : STD_LOGIC_VECTOR ( 13 downto 0 );
signal sin_ls1 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is "";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is 16383;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is 1;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is 2;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is 3;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is 4;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is 5;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is 6;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is 7;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is 8;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is 9;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is 10;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is 11;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is 12;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is 13;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is 14;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is 15;
attribute use_sync_reset : string;
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[0]\ : label is "no";
attribute use_sync_set : string;
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[0]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[10]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[10]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[11]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[11]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[12]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[12]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[13]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[13]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[1]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[1]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[2]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[2]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[3]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[3]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[4]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[4]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[5]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[5]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[6]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[6]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[7]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[7]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[8]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[8]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[9]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[9]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[0]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[0]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[10]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[10]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[11]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[11]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[12]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[12]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[13]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[13]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[1]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[1]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[2]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[2]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[3]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[3]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[4]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[4]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[5]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[5]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[6]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[6]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[7]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[7]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[8]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[8]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[9]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[9]\ : label is "no";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\i_rtl.i_quarter_table.i_addr_reg_c\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized12\
port map (
L(1 downto 0) => L(1 downto 0),
O1 => \n_1_i_rtl.i_quarter_table.i_addr_reg_c\,
O10 => \n_10_i_rtl.i_quarter_table.i_addr_reg_c\,
O11 => \n_11_i_rtl.i_quarter_table.i_addr_reg_c\,
O12 => \n_12_i_rtl.i_quarter_table.i_addr_reg_c\,
O13 => \n_13_i_rtl.i_quarter_table.i_addr_reg_c\,
O14 => \n_14_i_rtl.i_quarter_table.i_addr_reg_c\,
O15 => \n_15_i_rtl.i_quarter_table.i_addr_reg_c\,
O16 => \n_16_i_rtl.i_quarter_table.i_addr_reg_c\,
O17 => \n_17_i_rtl.i_quarter_table.i_addr_reg_c\,
O18 => \n_18_i_rtl.i_quarter_table.i_addr_reg_c\,
O19 => \n_19_i_rtl.i_quarter_table.i_addr_reg_c\,
O2 => \n_2_i_rtl.i_quarter_table.i_addr_reg_c\,
O20 => \n_20_i_rtl.i_quarter_table.i_addr_reg_c\,
O21 => \n_21_i_rtl.i_quarter_table.i_addr_reg_c\,
O22 => \n_22_i_rtl.i_quarter_table.i_addr_reg_c\,
O23 => \n_23_i_rtl.i_quarter_table.i_addr_reg_c\,
O24 => \n_24_i_rtl.i_quarter_table.i_addr_reg_c\,
O25 => \n_25_i_rtl.i_quarter_table.i_addr_reg_c\,
O26 => \n_26_i_rtl.i_quarter_table.i_addr_reg_c\,
O27 => \n_27_i_rtl.i_quarter_table.i_addr_reg_c\,
O28 => \n_28_i_rtl.i_quarter_table.i_addr_reg_c\,
O29 => \n_29_i_rtl.i_quarter_table.i_addr_reg_c\,
O3 => \n_3_i_rtl.i_quarter_table.i_addr_reg_c\,
O30 => \n_30_i_rtl.i_quarter_table.i_addr_reg_c\,
O31 => \n_31_i_rtl.i_quarter_table.i_addr_reg_c\,
O4 => \n_4_i_rtl.i_quarter_table.i_addr_reg_c\,
O5 => \n_5_i_rtl.i_quarter_table.i_addr_reg_c\,
O6 => \n_6_i_rtl.i_quarter_table.i_addr_reg_c\,
O7 => \n_7_i_rtl.i_quarter_table.i_addr_reg_c\,
O8 => \n_8_i_rtl.i_quarter_table.i_addr_reg_c\,
O9 => \n_9_i_rtl.i_quarter_table.i_addr_reg_c\,
aclk => aclk,
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(14 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(14 downto 0),
invert_sin => invert_sin,
\out\(14 downto 8) => p_0_in(6 downto 0),
\out\(7 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(7 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"5B1BC6C5B1BC6C5B1BC6C5B1BC6C5B1BC6C5B1BC6C6B1B06C6B1B06C6B1B06C6",
INIT_01 => X"F1B16C6F1B16C6F1B16C6C1B1AC6C1B1AC6C1B1AC6C1B1AC6C1B1AC6C1B1BC6C",
INIT_02 => X"1B1AC6C5B1BC6C5B1BC6C5B1BC6C5B1B06C6B1B06C6B1B06C6B1B06C6F1B16C6",
INIT_03 => X"B1AC6C5B1BC6C5B1BC6C6B1B06C6B1B06C6F1B16C6F1B16C6F1B1AC6C1B1AC6C",
INIT_04 => X"16C6F1B16C6C1B1AC6C5B1BC6C5B1B06C6B1B06C6B1B16C6F1B16C6C1B1AC6C1",
INIT_05 => X"6F1B1AC6C1B1BC6C5B1B06C6B1B16C6F1B16C6C1B1AC6C5B1BC6C6B1B06C6B1B",
INIT_06 => X"BC6C6B1B06C6F1B1AC6C1B1BC6C5B1B06C6F1B16C6C1B1AC6C5B1B06C6B1B16C",
INIT_07 => X"B1AC6C5B1B06C6F1B1AC6C1B1BC6C6B1B16C6C1B1AC6C5B1B06C6F1B16C6C1B1",
INIT_08 => X"B16C6C5B1B06C6F1B1AC6C5B1B06C6F1B1AC6C5B1B06C6F1B1AC6C5B1B06C6F1",
INIT_09 => X"6C6C1B1BC6C6F1B1AC6C5B1B16C6C1B1BC6C6F1B1AC6C5B1B16C6C1B1BC6C6B1",
INIT_0A => X"1B16C6C5B1B16C6C1B1B06C6C1B1B06C6F1B1BC6C6B1B1AC6C6B1B16C6C5B1B0",
INIT_0B => X"B1B06C6C1B1B16C6C5B1B16C6C5B1B16C6C5B1B16C6C5B1B16C6C5B1B16C6C5B",
INIT_0C => X"06C6C5B1B1AC6C6F1B1BC6C6C1B1B16C6C5B1B1AC6C6B1B1BC6C6F1B1B06C6C1",
INIT_0D => X"1B1BC6C6C1B1B1AC6C6F1B1B06C6C5B1B1BC6C6C1B1B16C6C6B1B1BC6C6C1B1B",
INIT_0E => X"1B06C6C6F1B1B16C6C6F1B1B16C6C6F1B1B16C6C6F1B1B06C6C6B1B1B06C6C5B",
INIT_0F => X"C6B1B1B16C6C6C1B1B1BC6C6C6B1B1B16C6C6C1B1B1BC6C6C5B1B1B06C6C6B1B",
INIT_10 => X"6F1B1B1BC6C6C6C1B1B1B06C6C6C1B1B1B06C6C6C1B1B1B06C6C6F1B1B1BC6C6",
INIT_11 => X"AC6C6C6C1B1B1B1AC6C6C6C1B1B1B1AC6C6C6F1B1B1B06C6C6C5B1B1B1AC6C6C",
INIT_12 => X"6C6C6C6F1B1B1B1BC6C6C6C6F1B1B1B1BC6C6C6C6B1B1B1B16C6C6C6C1B1B1B1",
INIT_13 => X"1B1B16C6C6C6C6C5B1B1B1B1B06C6C6C6C6B1B1B1B1B06C6C6C6C5B1B1B1B1AC",
INIT_14 => X"6C6C6C6C6C6C1B1B1B1B1B1B06C6C6C6C6C6B1B1B1B1B1B06C6C6C6C6C5B1B1B",
INIT_15 => X"B16C6C6C6C6C6C6C6C6B1B1B1B1B1B1B1B06C6C6C6C6C6C6C5B1B1B1B1B1B1BC",
INIT_16 => X"1B1B1B1B1B1B1B1B1B1B1B1B1AC6C6C6C6C6C6C6C6C6C6C1B1B1B1B1B1B1B1B1",
INIT_17 => X"B1B1B1B1B1B1B1B1B1B1B1B1B1B06C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6F",
INIT_18 => X"B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1",
INIT_19 => X"6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6CB1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1",
INIT_1A => X"B1B1B1B1B1B1B1B1C6C6C6C6C6C6C6C6C6C6DB1B1B1B1B1B1B1B1B1B1B1B1C6C",
INIT_1B => X"6C6C6DB1B1B1B1B1B1C6C6C6C6C6C6C71B1B1B1B1B1B1B6C6C6C6C6C6C6C6CB1",
INIT_1C => X"C6C6C6DB1B1B1B1B6C6C6C6C6DB1B1B1B1B1C6C6C6C6C6DB1B1B1B1B1B6C6C6C",
INIT_1D => X"C6C6CB1B1B1B2C6C6C6CB1B1B1B1C6C6C6C61B1B1B1B6C6C6C6C71B1B1B1B2C6",
INIT_1E => X"6C71B1B186C6C6CB1B1B1C6C6C6DB1B1B1C6C6C6CB1B1B186C6C6C71B1B1B2C6",
INIT_1F => X"B1B1B6C6C6DB1B186C6C61B1B186C6C61B1B186C6C61B1B1B6C6C6DB1B1B2C6C",
INIT_20 => X"1B6C6C71B1B6C6C71B1B6C6C61B1B2C6C6DB1B1C6C6CB1B1B6C6C61B1B1C6C6C",
INIT_21 => X"6C6DB1B2C6C71B186C6DB1B2C6C71B186C6CB1B1C6C6DB1B2C6C61B1B6C6C71B",
INIT_22 => X"CB1B2C6CB1B2C6CB1B2C6CB1B1C6C71B1C6C61B186C6DB1B6C6CB1B2C6C71B18",
INIT_23 => X"1B2C6DB186C61B1C6CB1B2C6DB1B6C61B186C71B1C6C71B1C6CB1B2C6CB1B2C6",
INIT_24 => X"B6C71B2C6DB186CB1B6C61B1C6CB1B6C71B2C6DB186C71B1C6CB1B6C61B1C6CB",
INIT_25 => X"C6DB186CB186CB186C71B6C71B2C61B2C6DB1C6CB186C71B6C61B2C6DB1C6CB1",
INIT_26 => X"6C7186CB186CB186DB1C6DB1C6DB1C6DB1C6DB1C6DB1C6DB1C6DB1C6DB1C6DB1",
INIT_27 => X"2C71B6CB1C6DB2C61B6C7186CB1C6DB2C61B6C7186CB186DB1C61B2C61B2C71B",
INIT_28 => X"B2C7186DB2C71B6CB1C61B6CB1C61B2C7186DB2C61B6CB1C6DB2C71B6CB1C6DB",
INIT_29 => X"6DB6CB1C6186DB2C7186DB6CB1C61B6CB1C6186DB2C7186DB2C7186DB2C7186D",
INIT_2A => X"B1C71861B6DB2CB1C6186DB6CB2C71861B6CB2C71C61B6DB2C71861B6CB2C718",
INIT_2B => X"1861B6DB6DB2CB2C71C7186186DB6CB2CB1C71C6186DB6CB2CB1C71861B6DB2C",
INIT_2C => X"DB6DB6DB6DB2CB2CB2CB2CB1C71C71C71C61861861B6DB6DB6CB2CB2C71C71C6",
INIT_2D => X"2CB2DB6DB6DB6DB6DB6DB6DB6D861861861861861861861861861B6DB6DB6DB6",
INIT_2E => X"CB2CB2DB6DB61861871C71C72CB2CB6DB6DB6D861861861C71C71C72CB2CB2CB",
INIT_2F => X"C71CB2DB6D861C71CB2DB6D861871C72CB6DB61861C71C72CB2DB6D861861C71",
INIT_30 => X"D871CB2DB61871CB2D861C72CB6D861C72CB6D861871CB2DB61871C72CB6D861",
INIT_31 => X"B6D871CB6D871CB6D861CB2D861CB2DB61C72DB61872CB6D871CB2DB61C72CB6",
INIT_32 => X"61CB61872DB61CB6D872CB61C72D861CB6D872CB61872DB61C72D861CB2D861C",
INIT_33 => X"72D872D871CB61CB61872D872DB61CB61872D872CB61CB6D872DB61CB61872D8",
INIT_34 => X"CB61CB61CB61CB61CB61CB61CB61CB61CB2D872D872D872D871CB61CB61CB618",
INIT_35 => X"721CB61CB61CB72D872D872D872D8761CB61CB61CB61CB61CB61CB61CB61CB61",
INIT_36 => X"62D872DCB61C872D8761CB61D872D8721CB61C872D872D8B61CB61C872D872D8",
INIT_37 => X"721CB72D8B61D8721CB62D8761CB72D8B61C872D8B61C872D8B61CB72D8761CB",
INIT_38 => X"CB72DCB72D8B62D8B62D8761D8721C8721CB72D8B62D8761D8721CB72D8B61D8",
INIT_39 => X"62D8B62DCB721C8721D8761D8762D8B62D8B62DCB72DCB72DCB72DCB72DCB72D",
INIT_3A => X"1C8762DC8721D8B62DC8761D8B72DC8761D8B62DC8721D8762D8B72DC8721D87",
INIT_3B => X"D8B762DC8762DC8762DC8762D8B721D8B721D8B721D8B62DC8762DC8721D8B72",
INIT_3C => X"DD8B721DC87621D8B722DC8762DD8B721D8B762DC8762DC8B721D8B721D8B721",
INIT_3D => X"22DC8B722DD8B762DD8B762DD8B762DD8B762DD8B722DC8B721DC87721D88762",
INIT_3E => X"87722DD887722DD887722DC8B7621DC8B722DD887721DC8B762DD887621DC877",
INIT_3F => X"21DC887722DDC8B7722DD88B7621DD887722DDC8B7621DC8B7722DD887722DD8",
INIT_40 => X"C8877622DDC8877622DDC8877622DDC8B77221DD8877622DD88B7722DDC8B772",
INIT_41 => X"B776221DDC88B77622DDD888776221DDC88777221DD888776221DD88B77222DD",
INIT_42 => X"776222DDDC8887776222DDD888B777222DDDC88B777222DDD888B776221DDC88",
INIT_43 => X"7762222DDDD8888B77772222DDDD888877772222DDDD888877762221DDD888B7",
INIT_44 => X"7777622222DDDDDD88888B77777222221DDDDC8888B7777622221DDDD8888B77",
INIT_45 => X"88777777777222222221DDDDDDDC888888877777776222222DDDDDDD88888877",
INIT_46 => X"888888888888888888777777777777777222222222222DDDDDDDDDDD88888888",
INIT_47 => X"DDD2222222222222222222222221DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDC",
INIT_48 => X"77777777777748888888888888888889DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD",
INIT_49 => X"8888DDDDDDDD222222223777777774888888888DDDDDDDDDDD22222222222277",
INIT_4A => X"E2222377777888889DDDDD2222227777778888889DDDDDD22222237777774888",
INIT_4B => X"7748889DDDE222377748889DDDD22223777788889DDDD222237777488889DDDD",
INIT_4C => X"DDDE223774888DDD22237778889DDE2227774888DDDD22237778888DDDE22237",
INIT_4D => X"2377889DDE22774889DD222774889DDE22777888DDD222777888DDD222777888",
INIT_4E => X"889DE2277889DE2277489DD2237788DDE2277488DDE2277488DDE2277488DDE2",
INIT_4F => X"D227788DD227788DD227788DDE237489DE237788DD2237489DE2277889DE2277",
INIT_50 => X"3788DE23788DE23748DD237489D227789DE23748DD227789DE237489DE27788D",
INIT_51 => X"89D22748DE27489D23789DE27489D23788DE27789D22748DD23748DE23788DE2",
INIT_52 => X"DE2749D23789D23789E2748DE2748DE2748DE2748DE2748DE2748DE23789D237",
INIT_53 => X"2378DE3789E2749D2348DE3789E2749D2378DE2749D2378DE2749D23789E2748",
INIT_54 => X"378DE348D2349D2749D2749E2789E2789E2789E2789E2789D2749D2749D2348D",
INIT_55 => X"349E378D2749E378D2749E378D2349E278DE348D2749E278DE348D2749E2789E",
INIT_56 => X"789E349E349E349D278D278D2349E349E278D278DE349E378D278DE349E278D2",
INIT_57 => X"349E34D278D278D278D278D278D278D278D278D278D278D278D278D278D278D2",
INIT_58 => X"278E349E38D279E349E78D278E349E34D278D279E349E349278D278D249E349E",
INIT_59 => X"D249E78D349278E349279E34D279E34D279E34D279E349278E349E78D249E34D",
INIT_5A => X"4D249E79E38E34D249E79E38D349249E78E34D249E78E34D249E78D349279E38",
INIT_5B => X"E79E79E79E78E38E38E34D34D34D249249E79E78E38E34D349249279E78E38D3",
INIT_5C => X"4D34D34D38E38E38E79E79E79E79E79249249249249249249249249249249E79",
INIT_5D => X"934D38E79E4924D34E38E7924924D34E38E79E4924934D34E38E39E79E492492",
INIT_5E => X"E7924D38E7934E39E4934E39E4934E39E4924D38E7924D34E39E4934D38E79E4",
INIT_5F => X"E4938E4938E4934E7934E3924E39E4D38E4938E7924E39E4D38E7934E39E4938",
INIT_60 => X"E7938E4939E4E3934E7938E4D39E4E3924E7934E7934E4938E4938E4938E4938",
INIT_61 => X"924E4D3934E4E3938E4E3938E4E3938E4D3934E4D3924E4939E4E3934E493924",
INIT_62 => X"393924E4E793938E4E4D3939E4E4D3939E4E4D3938E4E493934E4E3939E4E493",
INIT_63 => X"9393924E4E4E4939393924E4E4E79393934E4E4E79393924E4E49393934E4E49",
INIT_64 => X"E4E4E4E4E4E4E4D39393939393939E4E4E4E4E4E493939393938E4E4E4E4E393",
INIT_65 => X"393939393939393939393939393939393939393939393939393939393924E4E4",
INIT_66 => X"39393939394E4E4E4E4E4E93939393939393A4E4E4E4E4E4E4E4E4E4E9393939",
INIT_67 => X"E4E4E939393E4E4E4F939393E4E4E4E93939394E4E4E4E93939393A4E4E4E4E5",
INIT_68 => X"4E9393E4E4F9390E4E439390E4E439390E4E4F9393E4E4E539390E4E4E939390",
INIT_69 => X"E4E9394E4393A4E5393E4E9390E4E9390E4E9390E4E9393E4E5393A4E439394E",
INIT_6A => X"390E4390E4F93E4F93E4E93A4E9394E5390E4F93E4E9394E5390E4F93A4E5390",
INIT_6B => X"394E93A4F90E4394E93A4F93E4390E5394E93A4E93E4F93E4F93E4390E4390E4",
INIT_6C => X"E93E43A4F90E53E4394E93E53A4F90E53A4F90E53A4F90E53A4F90E53A4F93E4",
INIT_6D => X"93E53E53A43A4394F94E90E93E53A43A4F94E90E53E53A4394E90E53E43A4F90",
INIT_6E => X"F94F94F94F943A43A43A43A43A43A43A43A43A43A4394F94F94F94F90E90E90E",
INIT_6F => X"3E90F94FA43E53E90E94F943A43E53E90E90F94F943A43A53E53E50E90E90E94",
INIT_70 => X"0E943A53E94FA53E90F943E50E94FA53E90F943A53E90F943A53E90E94FA43E5",
INIT_71 => X"FA50E943E94FA50F943E94FA50E943E50FA43E94FA53E943A50E943A50E943A5",
INIT_72 => X"943E943E943E943E943A50FA50FA50FA50F943E943E943A50FA50F943E943E50",
INIT_73 => X"FA50FE943E940FA50FA50FE943E943E950FA50FA50FA50FA543E943E943E943E",
INIT_74 => X"3EA50FE940FA543EA50FE943FA503E940FA503E940FA503E943FA50FA943E950",
INIT_75 => X"FE9503EA503EA543FA543FA543FA543FA543FA503EA503E950FE950FA943FA54",
INIT_76 => X"A540FEA540FA9503FA940FEA503FA940FEA503FA940FE9503EA543FA940FA950",
INIT_77 => X"0FFA9503FAA540FEA5403FA9503FA9503FA9503FA9503FA9503FA9503FA9503F",
INIT_78 => X"540FFAA5403FAA5503FEA5503FEA5503FEA5503FEA5403FA9540FEA9503FEA54",
INIT_79 => X"5403FFAA5500FFEA95403FEA95403FEA95403FEA95403FEA9500FFAA5503FEA9",
INIT_7A => X"00FFEAA955003FFAA95400FFEAA55403FFAA95500FFEA95500FFEA95500FFAA9",
INIT_7B => X"AAA9554003FFFAAA555000FFFAAA554003FFEAA955000FFEAA955003FFEAA554",
INIT_7C => X"03FFFEAAA955550000FFFEAAA95554000FFFEAAA95550003FFFAAA5554000FFF",
INIT_7D => X"0000FFFFFFAAAAAA55555400000FFFFFEAAAA95555400003FFFFAAAA95555000",
INIT_7E => X"3FFFFFFFFFFFAAAAAAAAAA955555555400000000FFFFFFFEAAAAAAA555555400",
INIT_7F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555500000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(1 downto 0),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1 downto 0),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"394E53A4E93A4F93E4F90E4390E5394E53A4E93A4F93E4390E4394E5394E93A4",
INIT_01 => X"3E4390E4394E5394E93A4F93E4F90E4390E5394E53A4E93A4F93E4F90E4390E5",
INIT_02 => X"4E93A4F93E4F90E4390E5394E53A4E93E4F93E4390E4394E5394E93A4E93E4F9",
INIT_03 => X"4390E5394E53A4E93A4F93E4390E4394E5394E93A4E93E4F93E4390E5394E53A",
INIT_04 => X"93A4E93E4F90E4390E5394E53A4E93E4F93E4390E4394E5394E93A4F93E4F90E",
INIT_05 => X"93E4390E5394E53A4E93E4F93E4390E4394E53A4E93A4F93E4F90E4394E5394E",
INIT_06 => X"90E5394E93A4E93E4F90E4390E5394E93A4E93E4F90E4390E5394E93A4E93E4F",
INIT_07 => X"94E53A4E93E4F93E4390E5394E53A4E93E4F90E4390E5394E93A4E93E4F90E43",
INIT_08 => X"94E53A4E93E4F93E4390E5394E93A4E93E4F90E4394E5394E93A4F93E4390E43",
INIT_09 => X"90E5394E53A4E93E4F90E4394E53A4E93A4F93E4390E5394E93A4F93E4F90E43",
INIT_0A => X"93E4F90E4394E53A4E93E4F90E4394E5394E93A4F93E4390E5394E93A4F93E43",
INIT_0B => X"4394E53A4E93E4F90E4394E53A4E93E4F90E4394E53A4E93E4F90E4394E53A4E",
INIT_0C => X"4E53A4E93E4F90E4394E53A4F93E4390E5394E93A4F93E4390E5394E93E4F90E",
INIT_0D => X"394E53A4F93E4390E5394E93E4F90E4394E53A4F93E4390E5394E93A4F90E439",
INIT_0E => X"E4390E5394E93E4F90E4394E93A4F93E4394E53A4E93E4390E5394E93E4F90E4",
INIT_0F => X"5394E93E4F90E5394E93A4F90E4394E93A4F90E4394E53A4F93E4394E53A4E93",
INIT_10 => X"394E93E4F90E53A4E93E4390E53A4E93E4390E53A4E93E4390E5394E93E4F90E",
INIT_11 => X"90E53A4F93E4394E53A4F90E4394E93A4F90E4394E93E4F90E5394E93E4F90E5",
INIT_12 => X"3A4F90E4394E93E4F90E53A4E93E4394E53A4F90E4394E93E4F90E53A4E93E43",
INIT_13 => X"93E4390E53A4F90E4394E93E4390E53A4F93E4394E93E4F90E53A4E93E4394E5",
INIT_14 => X"E53A4F90E53A4E93E4394E93E4F90E53A4F93E4394E93E4390E53A4F90E4394E",
INIT_15 => X"3E4F90E53A4F90E53A4E93E4394E93E4394E53A4F90E53A4F93E4394E93E4390",
INIT_16 => X"4E93E4394E93E4394E93E4394E53A4F90E53A4F90E53A4F93E4394E93E4394E9",
INIT_17 => X"4394E93E4394E93E4394E93E4394E53A4F90E53A4F90E53A4F90E53A4F90E539",
INIT_18 => X"4394E93E4394E93E4394E93E4394E93E4394E93E4394E93E4394E93E4394E93E",
INIT_19 => X"4F90E53A4F90E53A4F90E53A4F90E53A4394E93E4394E93E4394E93E4394E93E",
INIT_1A => X"3E4394E93E4394E90E53A4F90E53A4F90E53A4394E93E4394E93E4394E93E53A",
INIT_1B => X"E53A4F94E93E4394E90E53A4F90E53A4394E93E4394E93E53A4F90E53A4F90E9",
INIT_1C => X"53A4F90E93E4394E90E53A4F90E93E4394E90E53A4F90E53E4394E93E43A4F90",
INIT_1D => X"F90E53E4394E90E53A4F94E93E43A4F90E53E4394E93E53A4F90E93E4394E90E",
INIT_1E => X"4F94E93E53A4F90E93E43A4F90E53E4394F90E53A4394E90E53A4F94E93E43A4",
INIT_1F => X"94E93E53A4F94E90E53A4394E90E53A4394E90E53A4394E93E53A4F94E93E53A",
INIT_20 => X"E43A4F94E93E53A4394E90E53E4394F90E53E43A4F90E93E43A4F94E93E53A4F",
INIT_21 => X"E53A4394F90E93E53A4F94E90E53E43A4F90E93E53A4F94E90E53E4394F90E93",
INIT_22 => X"A4394F90E93E53A4394F90E93E53A4394F90E93E53A4F94E90E53E43A4F94E90",
INIT_23 => X"93E53A43A4F94E90E53E43A4F94E90E93E53A4394F90E93E53A4394F90E93E53",
INIT_24 => X"3E53E43A4F94F90E93E53E43A4F94E90E93E53A43A4F94E90E53E43A4394F90E",
INIT_25 => X"A4F94F90E90E53E53A4394F94E90E93E53A43A4F94F90E93E53E43A4F94F90E9",
INIT_26 => X"3A43A4F94F90E90E53E53A43A4F94F90E90E53E53A43A4F94F90E90E53E53A43",
INIT_27 => X"4F94E90E90E53E53E43A43A4F94F90E90E93E53E53A43A4F94F94E90E93E53E4",
INIT_28 => X"43A43A4F94F94E90E90E93E53E53E43A43A4F94F94E90E90E53E53E43A43A4F9",
INIT_29 => X"4F94F94F94F90E90E90E53E53E53E43A43A43A4F94F94F90E90E90E53E53E53A",
INIT_2A => X"3E53E53E43A43A43A43A4F94F94F94F94E90E90E90E93E53E53E53E43A43A43A",
INIT_2B => X"E53E43A43A43A43A43A43A43A4F94F94F94F94F94F90E90E90E90E90E93E53E5",
INIT_2C => X"0E90E90E90E90E90E90E90E90E90E90E90E90E90E93E53E53E53E53E53E53E53",
INIT_2D => X"90E90E90E90E90E90E90E90E90F94F94F94F94F94F94F94F94F94E90E90E90E9",
INIT_2E => X"A43A43A43A43E53E53E53E53E53E53E53E53E50E90E90E90E90E90E90E90E90E",
INIT_2F => X"A43A43A43A53E53E53E53E50E90E90E90E90E94F94F94F94F94F94FA43A43A43",
INIT_30 => X"50E90E90E94F94F94FA43A43A43A53E53E53E50E90E90E90E94F94F94F94FA43",
INIT_31 => X"3E50E90E90F94F94FA43A43A53E53E53E90E90E94F94F94FA43A43A43E53E53E",
INIT_32 => X"94F943A43A43E53E50E90E94F94FA43A43A53E53E90E90E94F94FA43A43A53E5",
INIT_33 => X"E90F94FA43A43E53E90E90F94F943A43E53E50E90E94F94FA43A43E53E90E90F",
INIT_34 => X"F943A43E53E90E94F943A43E53E90E94F94FA43A53E50E90F94F943A43E53E90",
INIT_35 => X"E94F943A43E53E90F94FA43A53E50E94F943A43E53E90E94F943A43E53E90E94",
INIT_36 => X"94FA43A53E90F94FA43E53E90F94FA43E53E90F94FA43A53E90E94FA43A53E50",
INIT_37 => X"3E90E94FA43E50E94F943A53E90E94FA43E50E90F943A53E50E94F943A53E90E",
INIT_38 => X"53E90F943A53E90F943A53E90F943A53E90E94FA43E50E94FA43E53E90F943A5",
INIT_39 => X"94FA43E50E943A53E90F943A53E90F943A53E90F943A53E90F943A53E90F943A",
INIT_3A => X"90F943A50E94FA43E50F943A53E90FA43E50E94FA53E90F943A53E90FA43E50E",
INIT_3B => X"0F943E50F943A50E94FA53E90F943E50E943A53E94FA43E50F943A50E94FA43E",
INIT_3C => X"A50E943A50E943A53E94FA53E90FA43E90F943E50F943A50E943A53E94FA43E9",
INIT_3D => X"3E50F943E50F943E50F943E50F943E50F943E50F943E50F943E50F943E50F943",
INIT_3E => X"0E943A50F943E50FA43E90FA43E94FA53E94FA50E943A50E943A50F943E50F94",
INIT_3F => X"3E50FA43E90FA53E943A50F943E90FA53E94FA50E943E50F943E90FA53E94FA5",
INIT_40 => X"A50E943E50FA53E943A50FA43E94FA50E943E90FA53E943A50F943E90FA53E94",
INIT_41 => X"3E943E90FA50E943E90FA50F943E94FA50F943E94FA50F943E94FA50E943E90F",
INIT_42 => X"43E943A50FA50E943E94FA50FA43E943E50FA50E943E94FA50FA43E943E50FA5",
INIT_43 => X"43E943E50FA50FA43E943E94FA50FA50E943E943A50FA50F943E943E50FA50E9",
INIT_44 => X"3E943E943E50FA50FA50F943E943E943E50FA50FA53E943E943E90FA50FA53E9",
INIT_45 => X"A53E943E943E943E943E50FA50FA50FA50F943E943E943E94FA50FA50FA50F94",
INIT_46 => X"FA50FA50FA50FA50FA43E943E943E943E943E943E943E50FA50FA50FA50FA50F",
INIT_47 => X"FA543E943E943E943E943E943E94FA50FA50FA50FA50FA50FA50FA50FA50FA50",
INIT_48 => X"E943E943E943FA50FA50FA50FA50FA50FA50FA50FA50FA50FA50FA50FA50FA50",
INIT_49 => X"50FA50FA50FA943E943E943E943E950FA50FA50FA50FA50FA543E943E943E943",
INIT_4A => X"A943E943E940FA50FA50FA943E943E943EA50FA50FA50FA943E943E943E950FA",
INIT_4B => X"E950FA50FA543E943EA50FA50FA943E943E950FA50FA543E943E940FA50FA50F",
INIT_4C => X"A50FE943EA50FA503E943E950FA50FE943E950FA50FA943E943FA50FA503E943",
INIT_4D => X"43E950FA503E940FA50FE943EA50FA503E943FA50FA943E940FA50FE943E950F",
INIT_4E => X"A50FA943EA50FA943EA50FA943E950FA543E950FA503E940FA50FE943FA50FA9",
INIT_4F => X"A943EA50FE943FA503E940FA503E950FA543E950FA943EA50FA943EA50FA943E",
INIT_50 => X"940FA543EA50FE940FA543EA50FE943FA503E950FA943EA50FE940FA503E950F",
INIT_51 => X"0FA943FA503EA50FE940FA543FA503E950FA943FA543EA50FE940FA543EA50FE",
INIT_52 => X"503EA503E950FE940FA940FA543FA503EA50FE950FA940FA543FA503E950FE94",
INIT_53 => X"943FA543FA543FA543FA503EA503EA503E950FE950FE940FA940FA943FA543FA",
INIT_54 => X"43FA540FA940FA940FA940FA940FA940FA940FA940FA940FA940FA940FA940FA",
INIT_55 => X"EA503EA543FA543FA940FA940FE950FE950FEA503EA503EA503FA543FA543FA5",
INIT_56 => X"3FA540FA950FEA503EA543FA940FA950FE9503EA503FA543FA940FA950FE9503",
INIT_57 => X"3FA540FE9503EA543FA940FE9503EA543FA940FE9503EA543FA940FE9503EA54",
INIT_58 => X"E9503FA540FE9503FA540FE9503FA540FE9503EA540FA9503EA543FA950FEA50",
INIT_59 => X"03FA540FEA543FA9503EA540FE9503FA940FEA543FA9503EA540FA9503FA540F",
INIT_5A => X"503FA540FEA540FEA503FA9503FA950FEA540FEA503FA9503FA540FEA543FA95",
INIT_5B => X"03FA9503FA9503FA9503FA9503FA9503FA540FEA540FEA540FEA543FA9503FA9",
INIT_5C => X"FA9503FA9503FA9503FA9503FA9503FEA540FEA540FEA540FEA540FEA540FA95",
INIT_5D => X"03FA9503FAA540FEA540FEA9503FA9503FA9500FEA540FEA540FEA540FFA9503",
INIT_5E => X"03FEA540FEA9503FAA540FEA5503FA9500FEA540FEA9503FA9500FEA540FEA55",
INIT_5F => X"FFA9500FEA5503FA9540FEA9503FAA540FFA9503FEA540FFA9503FEA540FFA95",
INIT_60 => X"5403FAA540FFA9540FEA9500FEA5503FEA5403FA9540FFA9500FEA5503FAA540",
INIT_61 => X"A9500FEA9500FEA9500FEA9500FEA9500FEA9500FEA9500FEA5503FEA5503FEA",
INIT_62 => X"95403FAA5403FEA5500FEA9500FFA9540FFAA5403FAA5503FEA5503FEA5500FE",
INIT_63 => X"03FEA9500FFAA5403FEA9500FFA95403FEA5500FEA95403FAA5503FEA9500FFA",
INIT_64 => X"5500FFAA5500FFA95403FEA95403FAA5500FFAA5503FEA95403FAA5500FFA954",
INIT_65 => X"95403FEA95403FEA95403FEA95403FEA95403FEA95403FEA95403FEA9540FFAA",
INIT_66 => X"403FEA95400FFAA5500FFAA95403FEA95403FFAA5500FFAA5500FFAA55403FEA",
INIT_67 => X"AA55003FEA95500FFAA95403FFAA55003FEA95500FFAA55403FEA95500FFAA55",
INIT_68 => X"FAA95400FFAA95500FFEA95500FFEA95500FFAA95400FFAA95400FFAA55403FF",
INIT_69 => X"AA55400FFEA955003FEAA55400FFAA95500FFEAA55003FEAA55403FFAA95400F",
INIT_6A => X"400FFEAA55003FFAA955003FFAA955003FFAA55400FFEAA55400FFAA955003FF",
INIT_6B => X"955003FFAAA55400FFEAA554003FFAA955003FFAA955003FFAA955400FFEAA55",
INIT_6C => X"554003FFAAA554003FFAA955400FFFAA955000FFEAA555003FFAAA55400FFEAA",
INIT_6D => X"03FFEAA9554003FFAAA555003FFEAA955000FFFAA9554003FFAAA554003FFAAA",
INIT_6E => X"555000FFFAAA9554003FFEAA9554003FFEAA9554003FFAAA555000FFFAAA5550",
INIT_6F => X"9555000FFFEAA9555000FFFEAA9554000FFFAAA5554003FFEAA9555000FFFAAA",
INIT_70 => X"50003FFEAAA5554000FFFEAAA5550003FFFAAA9554000FFFEAA9555000FFFEAA",
INIT_71 => X"AAAA5554000FFFFAAA95550000FFFEAAA5554000FFFEAAA95550003FFFAAA955",
INIT_72 => X"FFEAAA955540003FFFEAAA55550000FFFFAAA955540003FFFAAAA55540003FFF",
INIT_73 => X"AAAA555540000FFFFAAAA555540003FFFFAAAA55550000FFFFEAAA955540003F",
INIT_74 => X"40000FFFFFAAAA9555500003FFFFEAAAA555540000FFFFEAAA9555500003FFFF",
INIT_75 => X"55555400003FFFFEAAAA95555400003FFFFEAAAA9555540000FFFFFAAAA95555",
INIT_76 => X"5555000000FFFFFEAAAAA55555400000FFFFFEAAAAA55555400003FFFFFAAAAA",
INIT_77 => X"0FFFFFFEAAAAAA5555554000003FFFFFEAAAAA9555554000003FFFFFEAAAAA95",
INIT_78 => X"55500000003FFFFFFEAAAAAA955555540000003FFFFFFEAAAAAA555555400000",
INIT_79 => X"555400000000FFFFFFFFEAAAAAAA95555555400000003FFFFFFFAAAAAAA95555",
INIT_7A => X"00FFFFFFFFFFEAAAAAAAAA5555555554000000000FFFFFFFFFAAAAAAAAA55555",
INIT_7B => X"5555555554000000000000FFFFFFFFFFFEAAAAAAAAAAA5555555555400000000",
INIT_7C => X"A95555555555555555000000000000000FFFFFFFFFFFFFFEAAAAAAAAAAAAA555",
INIT_7D => X"555500000000000000000000000FFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAA",
INIT_7E => X"EAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555555555",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(3 downto 2),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(3 downto 2),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"400FFEAA55400FFEAA555003FFAA955003FFAA955003FFEAA55400FFEAA55400",
INIT_01 => X"955400FFEAA55400FFEAA55400FFFAA955003FFAA955003FFAA955000FFEAA55",
INIT_02 => X"FAA955003FFAAA55400FFEAA55400FFEAA554003FFAA955003FFAA955003FFAA",
INIT_03 => X"03FFAA955003FFAA955003FFEAA55400FFEAA55400FFEAA554003FFAA955003F",
INIT_04 => X"5400FFEAA555003FFAA955003FFAA955003FFEAA55400FFEAA55400FFEAA5550",
INIT_05 => X"A955400FFEAA55400FFEAA554003FFAA955003FFAA955003FFAAA55400FFEAA5",
INIT_06 => X"FFAA955003FFAA955000FFEAA55400FFEAA55400FFFAA955003FFAA955003FFA",
INIT_07 => X"00FFEAA55400FFEAA955003FFAA955003FFAAA55400FFEAA55400FFEAA555003",
INIT_08 => X"55003FFAA955003FFEAA55400FFEAA55400FFFAA955003FFAA955003FFEAA554",
INIT_09 => X"AA55400FFEAA55400FFFAA955003FFAA955003FFEAA55400FFEAA55400FFFAA9",
INIT_0A => X"FEAA555003FFAA955003FFAAA55400FFEAA55400FFEAA955003FFAA955003FFE",
INIT_0B => X"03FFAA955003FFAAA55400FFEAA55400FFFAA955003FFAA955000FFEAA55400F",
INIT_0C => X"5003FFAA955000FFEAA55400FFEAA955003FFAA955003FFEAA55400FFEAA5550",
INIT_0D => X"955003FFAA955400FFEAA55400FFFAA955003FFAA955400FFEAA55400FFFAA95",
INIT_0E => X"AA955003FFAA955000FFEAA55400FFEAA955003FFAA955400FFEAA55400FFFAA",
INIT_0F => X"FEAA55400FFFAA955003FFAAA55400FFEAA555003FFAA955003FFEAA55400FFE",
INIT_10 => X"3FFAA955000FFEAA554003FFAA955003FFEAA55400FFEAA955003FFAA955000F",
INIT_11 => X"00FFEAA554003FFAA955000FFEAA55400FFFAA955003FFAAA55400FFEAA55500",
INIT_12 => X"400FFFAA955003FFAAA55400FFEAA955003FFAAA55400FFEAA555003FFAA9554",
INIT_13 => X"54003FFAA955000FFEAA554003FFAA955003FFEAA55400FFFAA955003FFEAA55",
INIT_14 => X"55400FFFAA955003FFEAA55400FFFAA955003FFEAA554003FFAA955000FFEAA5",
INIT_15 => X"955000FFEAA555003FFAA955400FFEAA955003FFAAA55400FFEAA955003FFEAA",
INIT_16 => X"A554003FFAA955400FFEAA955003FFAAA55400FFFAA955003FFEAA554003FFAA",
INIT_17 => X"A955003FFEAA554003FFAA955400FFEAA555003FFAAA55400FFFAA955000FFEA",
INIT_18 => X"A955003FFEAA554003FFAA955400FFEAA955003FFEAA554003FFAA955400FFEA",
INIT_19 => X"A555003FFAAA55400FFFAA955000FFEAA955003FFEAA554003FFAA955400FFEA",
INIT_1A => X"955400FFEAA955000FFEAA555003FFAAA554003FFAA955400FFEAA955003FFEA",
INIT_1B => X"55400FFFAA955400FFFAA955000FFEAA955003FFEAA554003FFAAA55400FFFAA",
INIT_1C => X"5400FFFAA955400FFFAA955000FFEAA955000FFEAA555003FFEAA554003FFAAA",
INIT_1D => X"000FFEAA955000FFEAA555003FFEAA555003FFEAA554003FFAAA554003FFAAA5",
INIT_1E => X"0FFFAA955400FFFAA955400FFFAA955400FFFAA955400FFFAA955000FFEAA955",
INIT_1F => X"FFAA955400FFFAAA554003FFAAA554003FFAAA554003FFAA955400FFFAA95540",
INIT_20 => X"AA955000FFEAA955400FFFAA955400FFFAA955400FFFAA955400FFFAA955400F",
INIT_21 => X"554003FFAAA554003FFAAA555003FFEAA555003FFEAA555000FFEAA955000FFE",
INIT_22 => X"003FFAAA554003FFEAA555003FFEAA955000FFEAA955000FFFAA955400FFFAAA",
INIT_23 => X"FEAA955400FFFAAA554003FFAAA555003FFEAA955000FFEAA955400FFFAA9554",
INIT_24 => X"9554003FFAAA555003FFEAA955000FFFAA9554003FFAAA555003FFEAA955000F",
INIT_25 => X"00FFFAAA555003FFEAA955000FFFAA9554003FFAAA555003FFEAA955000FFFAA",
INIT_26 => X"EAA955000FFFAAA554003FFEAA555000FFFAA9554003FFAAA555000FFEAA9554",
INIT_27 => X"5000FFFAAA554003FFEAA955000FFFAAA554003FFEAA955000FFFAAA554003FF",
INIT_28 => X"FEAA955000FFFAAA555003FFEAA9554003FFAAA555000FFFAA9554003FFEAA55",
INIT_29 => X"5000FFFAAA555000FFFAA9554003FFEAA955400FFFAAA555000FFFAA9554003F",
INIT_2A => X"EAA9554003FFEAA955400FFFAAA555000FFFAAA555003FFEAA9554003FFEAA95",
INIT_2B => X"003FFEAA9554003FFEAA955400FFFAAA555000FFFAAA555000FFFAAA554003FF",
INIT_2C => X"A555000FFFAAA555000FFFAAA555000FFFAAA555003FFEAA9554003FFEAA9554",
INIT_2D => X"FFAAA555000FFFAAA555000FFFAAA555000FFFAAA555000FFFAAA555000FFFAA",
INIT_2E => X"003FFEAA9554003FFEAA9554003FFEAA9554000FFFAAA555000FFFAAA555000F",
INIT_2F => X"554003FFEAA9554003FFEAAA555000FFFAAA555000FFFAAA555000FFFEAA9554",
INIT_30 => X"AA555000FFFAAA5550003FFEAA9554003FFEAAA555000FFFAAA555000FFFAAA9",
INIT_31 => X"EAAA555000FFFAAA5554003FFEAA9554000FFFAAA555000FFFEAA9554003FFEA",
INIT_32 => X"FFAAA9554003FFEAAA555000FFFAAA9554003FFEAAA555000FFFAAA9554003FF",
INIT_33 => X"FFFAAA5554003FFEAAA555000FFFEAA9554000FFFAAA5550003FFEAA9555000F",
INIT_34 => X"FFFEAA9554000FFFAAA9554003FFFAAA5550003FFEAAA555000FFFEAA9554000",
INIT_35 => X"FFFAAA9554003FFFAAA5554003FFFAAA5554003FFEAAA5550003FFEAA9555000",
INIT_36 => X"FFAAA9554000FFFAAA9554000FFFAAA9554000FFFAAA9554000FFFAAA9554000",
INIT_37 => X"EAAA5550003FFFAAA5554003FFFAAA5554000FFFAAA9554000FFFAAA9554000F",
INIT_38 => X"A95550003FFEAAA5554003FFFAAA9554000FFFAAA9555000FFFEAA95550003FF",
INIT_39 => X"550003FFFAAA9554000FFFEAA95550003FFEAAA5554003FFFAAA9554000FFFEA",
INIT_3A => X"00FFFEAAA5550003FFFAAA9554000FFFEAAA5550003FFFAAA9554000FFFEAAA5",
INIT_3B => X"FAAA95550003FFFAAA5554000FFFEAAA5554003FFFAAA95550003FFFAAA55540",
INIT_3C => X"5550003FFFAAA9554000FFFEAAA5554000FFFEAAA5554000FFFEAA95550003FF",
INIT_3D => X"3FFFAAA95550003FFFAAA95550003FFFAAA95550003FFFAAA95550003FFFAAA9",
INIT_3E => X"A5554000FFFEAAA5554000FFFEAAA5554000FFFFAAA95550003FFFAAA9555000",
INIT_3F => X"3FFFAAA95550003FFFEAAA5554000FFFEAAA55550003FFFAAA95550003FFFAAA",
INIT_40 => X"5550003FFFAAA95554000FFFEAAA55550003FFFAAA95554000FFFEAAA5554000",
INIT_41 => X"EAAA95550000FFFEAAA55550003FFFAAAA5554000FFFFAAA95550000FFFEAAA5",
INIT_42 => X"03FFFEAAA55550003FFFAAAA55540003FFFAAAA5554000FFFFAAA95554000FFF",
INIT_43 => X"540003FFFAAAA55540003FFFAAAA55550003FFFEAAA55550003FFFEAAA555500",
INIT_44 => X"955540003FFFAAAA55550003FFFEAAA95550000FFFEAAA95554000FFFFAAA955",
INIT_45 => X"AA955540003FFFEAAA95550000FFFFAAAA55540003FFFEAAA55550000FFFFAAA",
INIT_46 => X"AAAA55550000FFFFAAA955540003FFFEAAA955540003FFFAAAA55550000FFFFA",
INIT_47 => X"AAAA955540003FFFEAAA95554000FFFFAAAA55550000FFFFAAAA55550000FFFF",
INIT_48 => X"AAA955540003FFFFAAAA55550000FFFFAAAA55550000FFFFAAAA55550000FFFF",
INIT_49 => X"AA55550000FFFFEAAA955540003FFFFAAAA55550000FFFFAAAA955540003FFFE",
INIT_4A => X"55540003FFFFAAAA555500003FFFEAAA955550000FFFFAAAA955540003FFFFAA",
INIT_4B => X"0000FFFFAAAA955540000FFFFAAAA955540000FFFFAAAA955540000FFFFAAAA5",
INIT_4C => X"FFFAAAA9555500003FFFEAAAA555500003FFFFAAAA555540003FFFFAAAA95554",
INIT_4D => X"A9555500003FFFFAAAA555540000FFFFEAAA9555500003FFFFAAAA555540000F",
INIT_4E => X"000FFFFEAAAA555540000FFFFEAAAA555540000FFFFEAAAA555500003FFFFAAA",
INIT_4F => X"AAA9555500003FFFFEAAAA555540000FFFFEAAAA555540000FFFFEAAAA555540",
INIT_50 => X"000FFFFEAAAA5555500003FFFFAAAA9555540000FFFFEAAAA5555500003FFFFA",
INIT_51 => X"A5555400003FFFFAAAAA5555400003FFFFAAAA9555540000FFFFFAAAA9555500",
INIT_52 => X"FFEAAAA9555500000FFFFFAAAA9555540000FFFFFAAAAA5555400003FFFFAAAA",
INIT_53 => X"003FFFFEAAAA95555400003FFFFEAAAA9555500000FFFFFAAAAA5555400003FF",
INIT_54 => X"5400000FFFFFAAAAA5555500000FFFFFAAAAA5555500000FFFFFAAAAA5555500",
INIT_55 => X"5555400003FFFFEAAAAA5555500000FFFFFAAAAA95555400003FFFFEAAAA9555",
INIT_56 => X"95555500000FFFFFEAAAA95555500000FFFFFEAAAA95555400000FFFFFAAAAA9",
INIT_57 => X"955555000003FFFFEAAAAA55555400003FFFFFAAAAA95555400000FFFFFEAAAA",
INIT_58 => X"5555400000FFFFFEAAAAA55555400000FFFFFEAAAAA55555400003FFFFFAAAAA",
INIT_59 => X"5400000FFFFFEAAAAA955555000003FFFFFAAAAA955555400000FFFFFEAAAAA5",
INIT_5A => X"003FFFFFAAAAAA555554000003FFFFFAAAAAA555554000003FFFFFAAAAA95555",
INIT_5B => X"FEAAAAA9555554000003FFFFFEAAAAA955555000000FFFFFFAAAAA9555554000",
INIT_5C => X"555554000003FFFFFEAAAAA9555554000000FFFFFFAAAAAA555555000000FFFF",
INIT_5D => X"03FFFFFEAAAAAA5555550000003FFFFFEAAAAAA555555000000FFFFFFAAAAAA9",
INIT_5E => X"A95555550000003FFFFFFAAAAAA9555555000000FFFFFFEAAAAAA55555500000",
INIT_5F => X"FFFFFFFAAAAAA95555550000003FFFFFFAAAAAA95555550000003FFFFFFAAAAA",
INIT_60 => X"5554000000FFFFFFFAAAAAAA55555540000003FFFFFFAAAAAAA5555554000000",
INIT_61 => X"AAAAA55555550000000FFFFFFFAAAAAAA55555550000000FFFFFFEAAAAAA9555",
INIT_62 => X"FFFFEAAAAAA955555550000000FFFFFFFAAAAAAA955555540000003FFFFFFFAA",
INIT_63 => X"03FFFFFFFAAAAAAA9555555500000003FFFFFFFAAAAAAA955555540000000FFF",
INIT_64 => X"0000FFFFFFFFAAAAAAA9555555540000000FFFFFFFEAAAAAAA95555555000000",
INIT_65 => X"00003FFFFFFFEAAAAAAA95555555400000003FFFFFFFEAAAAAAA955555550000",
INIT_66 => X"003FFFFFFFFAAAAAAAA55555555400000003FFFFFFFFAAAAAAAA555555554000",
INIT_67 => X"FFFFFFEAAAAAAAA555555554000000003FFFFFFFFAAAAAAAA955555555000000",
INIT_68 => X"AAAAAAAA555555555000000000FFFFFFFFFAAAAAAAAA555555555000000003FF",
INIT_69 => X"55555550000000003FFFFFFFFFAAAAAAAAA5555555554000000003FFFFFFFFFA",
INIT_6A => X"000FFFFFFFFFEAAAAAAAAA95555555554000000000FFFFFFFFFFAAAAAAAAA955",
INIT_6B => X"AAAAA9555555555500000000003FFFFFFFFFEAAAAAAAAA955555555550000000",
INIT_6C => X"000003FFFFFFFFFFEAAAAAAAAAA5555555555500000000003FFFFFFFFFFAAAAA",
INIT_6D => X"A955555555555400000000003FFFFFFFFFFFAAAAAAAAAAA95555555555400000",
INIT_6E => X"FFFFFFAAAAAAAAAAAA9555555555554000000000003FFFFFFFFFFFAAAAAAAAAA",
INIT_6F => X"0000000FFFFFFFFFFFFFAAAAAAAAAAAAA5555555555554000000000000FFFFFF",
INIT_70 => X"555540000000000000FFFFFFFFFFFFFEAAAAAAAAAAAAA5555555555555000000",
INIT_71 => X"55555555555000000000000000FFFFFFFFFFFFFFAAAAAAAAAAAAAA9555555555",
INIT_72 => X"555555555555554000000000000000FFFFFFFFFFFFFFFEAAAAAAAAAAAAAA9555",
INIT_73 => X"555555555555500000000000000003FFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAA95",
INIT_74 => X"555550000000000000000003FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAA95555",
INIT_75 => X"00000000003FFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAA55555555555555",
INIT_76 => X"FFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAA55555555555555555555540000000000",
INIT_77 => X"A55555555555555555555555554000000000000000000000003FFFFFFFFFFFFF",
INIT_78 => X"00000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_79 => X"AAAAAAAAAAAA5555555555555555555555555555555540000000000000000000",
INIT_7A => X"00FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAA",
INIT_7B => X"5555555555555555555555000000000000000000000000000000000000000000",
INIT_7C => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555555555555555555555555555",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(5 downto 4),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5 downto 4),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"AAA555555555500000000003FFFFFFFFFEAAAAAAAAA955555555550000000000",
INIT_01 => X"000000FFFFFFFFFFAAAAAAAAAA555555555540000000003FFFFFFFFFFAAAAAAA",
INIT_02 => X"AAAAAAAA955555555550000000000FFFFFFFFFFEAAAAAAAAA955555555540000",
INIT_03 => X"540000000003FFFFFFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFEA",
INIT_04 => X"FFFFAAAAAAAAAA955555555540000000003FFFFFFFFFFAAAAAAAAAA555555555",
INIT_05 => X"55555550000000000FFFFFFFFFFEAAAAAAAAA955555555540000000000FFFFFF",
INIT_06 => X"FFFFFFFFFEAAAAAAAAAA55555555550000000000FFFFFFFFFFEAAAAAAAAA9555",
INIT_07 => X"AA555555555500000000003FFFFFFFFFEAAAAAAAAAA555555555500000000003",
INIT_08 => X"00003FFFFFFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFEAAAAAAAA",
INIT_09 => X"AAAAAAA555555555500000000003FFFFFFFFFEAAAAAAAAAA5555555555000000",
INIT_0A => X"0000000003FFFFFFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFEAAA",
INIT_0B => X"FEAAAAAAAAA955555555550000000000FFFFFFFFFFEAAAAAAAAAA55555555550",
INIT_0C => X"55540000000000FFFFFFFFFFAAAAAAAAAA955555555540000000000FFFFFFFFF",
INIT_0D => X"FFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFFAAAAAAAAAA5555555",
INIT_0E => X"555555540000000000FFFFFFFFFFAAAAAAAAAA955555555550000000000FFFFF",
INIT_0F => X"FFFFFFFFFAAAAAAAAAA9555555555500000000003FFFFFFFFFEAAAAAAAAAA555",
INIT_10 => X"9555555555500000000003FFFFFFFFFEAAAAAAAAAA555555555540000000000F",
INIT_11 => X"00FFFFFFFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFFAAAAAAAAAA",
INIT_12 => X"AAA555555555540000000000FFFFFFFFFFEAAAAAAAAAA5555555555400000000",
INIT_13 => X"00003FFFFFFFFFFAAAAAAAAAA955555555540000000000FFFFFFFFFFEAAAAAAA",
INIT_14 => X"AAAAA555555555540000000000FFFFFFFFFFEAAAAAAAAAA95555555555000000",
INIT_15 => X"000000FFFFFFFFFFEAAAAAAAAAA555555555540000000000FFFFFFFFFFEAAAAA",
INIT_16 => X"AAAAAA9555555555500000000003FFFFFFFFFFAAAAAAAAAA9555555555540000",
INIT_17 => X"0000003FFFFFFFFFFEAAAAAAAAAA555555555540000000000FFFFFFFFFFFAAAA",
INIT_18 => X"AAAAAA9555555555540000000000FFFFFFFFFFEAAAAAAAAAA955555555550000",
INIT_19 => X"0000003FFFFFFFFFFAAAAAAAAAAA5555555555400000000003FFFFFFFFFFAAAA",
INIT_1A => X"AAAAAA5555555555500000000003FFFFFFFFFFEAAAAAAAAAA555555555540000",
INIT_1B => X"00000FFFFFFFFFFFAAAAAAAAAAA5555555555400000000003FFFFFFFFFFAAAAA",
INIT_1C => X"AAAA5555555555500000000000FFFFFFFFFFFAAAAAAAAAA95555555555400000",
INIT_1D => X"000FFFFFFFFFFFAAAAAAAAAA95555555555400000000003FFFFFFFFFFEAAAAAA",
INIT_1E => X"A5555555555500000000000FFFFFFFFFFFAAAAAAAAAAA5555555555500000000",
INIT_1F => X"FFFFFFFFFFAAAAAAAAAAA95555555555400000000003FFFFFFFFFFAAAAAAAAAA",
INIT_20 => X"5555555500000000000FFFFFFFFFFFAAAAAAAAAAA5555555555500000000000F",
INIT_21 => X"FFFFFEAAAAAAAAAA95555555555400000000003FFFFFFFFFFFAAAAAAAAAAA555",
INIT_22 => X"55400000000003FFFFFFFFFFEAAAAAAAAAAA5555555555500000000000FFFFFF",
INIT_23 => X"AAAAAAAAAA55555555555400000000003FFFFFFFFFFFAAAAAAAAAAA555555555",
INIT_24 => X"0000003FFFFFFFFFFEAAAAAAAAAAA55555555555400000000003FFFFFFFFFFFA",
INIT_25 => X"AA55555555555400000000000FFFFFFFFFFFEAAAAAAAAAA95555555555500000",
INIT_26 => X"FFFFFFFFFAAAAAAAAAAA955555555555000000000003FFFFFFFFFFFAAAAAAAAA",
INIT_27 => X"5555000000000003FFFFFFFFFFFAAAAAAAAAAA955555555555000000000003FF",
INIT_28 => X"AAAAAAAAAA555555555554000000000003FFFFFFFFFFFAAAAAAAAAAA95555555",
INIT_29 => X"0000FFFFFFFFFFFFAAAAAAAAAAA955555555555000000000000FFFFFFFFFFFEA",
INIT_2A => X"555555555400000000000FFFFFFFFFFFFAAAAAAAAAAA95555555555540000000",
INIT_2B => X"FFEAAAAAAAAAAA955555555555000000000000FFFFFFFFFFFFAAAAAAAAAAA955",
INIT_2C => X"0000000FFFFFFFFFFFFAAAAAAAAAAAA555555555554000000000003FFFFFFFFF",
INIT_2D => X"55555555555000000000000FFFFFFFFFFFFAAAAAAAAAAAA55555555555500000",
INIT_2E => X"FFEAAAAAAAAAAA9555555555554000000000000FFFFFFFFFFFFAAAAAAAAAAAA5",
INIT_2F => X"000003FFFFFFFFFFFEAAAAAAAAAAAA555555555555000000000000FFFFFFFFFF",
INIT_30 => X"555555550000000000003FFFFFFFFFFFEAAAAAAAAAAAA5555555555550000000",
INIT_31 => X"AAAAAAAAAA5555555555554000000000000FFFFFFFFFFFFAAAAAAAAAAAA95555",
INIT_32 => X"FFFFFFFFFFFEAAAAAAAAAAAA5555555555554000000000000FFFFFFFFFFFFEAA",
INIT_33 => X"0000000000003FFFFFFFFFFFFAAAAAAAAAAAAA5555555555554000000000000F",
INIT_34 => X"55555555555550000000000003FFFFFFFFFFFFEAAAAAAAAAAAA5555555555555",
INIT_35 => X"AAAAAAAAAAAA955555555555540000000000003FFFFFFFFFFFFEAAAAAAAAAAAA",
INIT_36 => X"FFFFFFFFFFFFAAAAAAAAAAAAA55555555555550000000000000FFFFFFFFFFFFF",
INIT_37 => X"00000000003FFFFFFFFFFFFEAAAAAAAAAAAAA55555555555550000000000000F",
INIT_38 => X"5555555540000000000003FFFFFFFFFFFFFAAAAAAAAAAAAA5555555555555400",
INIT_39 => X"AAAAA9555555555555500000000000003FFFFFFFFFFFFEAAAAAAAAAAAAA55555",
INIT_3A => X"FFAAAAAAAAAAAAA9555555555555500000000000003FFFFFFFFFFFFFAAAAAAAA",
INIT_3B => X"FFFFFFFFFFFEAAAAAAAAAAAAA5555555555555400000000000003FFFFFFFFFFF",
INIT_3C => X"0000003FFFFFFFFFFFFFAAAAAAAAAAAAAA5555555555555500000000000003FF",
INIT_3D => X"400000000000003FFFFFFFFFFFFFEAAAAAAAAAAAAA9555555555555540000000",
INIT_3E => X"5555555500000000000000FFFFFFFFFFFFFFAAAAAAAAAAAAAA95555555555555",
INIT_3F => X"95555555555555400000000000000FFFFFFFFFFFFFFEAAAAAAAAAAAAA9555555",
INIT_40 => X"AAAAAA955555555555555000000000000003FFFFFFFFFFFFFFAAAAAAAAAAAAAA",
INIT_41 => X"AAAAAAAAAAAA55555555555555400000000000000FFFFFFFFFFFFFFFAAAAAAAA",
INIT_42 => X"FEAAAAAAAAAAAAAA955555555555555400000000000000FFFFFFFFFFFFFFFAAA",
INIT_43 => X"FFFFFEAAAAAAAAAAAAAA9555555555555554000000000000003FFFFFFFFFFFFF",
INIT_44 => X"FFFFFFFFEAAAAAAAAAAAAAA9555555555555555000000000000000FFFFFFFFFF",
INIT_45 => X"FFFFFFFFFFEAAAAAAAAAAAAAAA5555555555555554000000000000000FFFFFFF",
INIT_46 => X"FFFFFFFFFFFFAAAAAAAAAAAAAAA95555555555555554000000000000000FFFFF",
INIT_47 => X"FFFFFFFFFFFFEAAAAAAAAAAAAAAA55555555555555550000000000000000FFFF",
INIT_48 => X"FFFFFFFFFFFEAAAAAAAAAAAAAAAA55555555555555550000000000000000FFFF",
INIT_49 => X"FFFFFFFFFFAAAAAAAAAAAAAAAA9555555555555555500000000000000003FFFF",
INIT_4A => X"FFFFFFFEAAAAAAAAAAAAAAAA9555555555555555500000000000000003FFFFFF",
INIT_4B => X"FFFFAAAAAAAAAAAAAAAAA5555555555555555500000000000000000FFFFFFFFF",
INIT_4C => X"AAAAAAAAAAAAAAAA95555555555555555400000000000000003FFFFFFFFFFFFF",
INIT_4D => X"AAAAAAAAAA955555555555555555000000000000000003FFFFFFFFFFFFFFFFFA",
INIT_4E => X"AAA555555555555555555000000000000000000FFFFFFFFFFFFFFFFFEAAAAAAA",
INIT_4F => X"5555555555554000000000000000000FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAA",
INIT_50 => X"5550000000000000000003FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAA955555",
INIT_51 => X"00000000003FFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAA5555555555555555",
INIT_52 => X"FFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAA5555555555555555555400000000",
INIT_53 => X"FFEAAAAAAAAAAAAAAAAAAA9555555555555555555500000000000000000003FF",
INIT_54 => X"AAAAAAA5555555555555555555500000000000000000000FFFFFFFFFFFFFFFFF",
INIT_55 => X"555555555400000000000000000000FFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAA",
INIT_56 => X"00000000000FFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAA55555555555",
INIT_57 => X"FFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAA95555555555555555555550000000000",
INIT_58 => X"AAAAAAAAAA55555555555555555555550000000000000000000003FFFFFFFFFF",
INIT_59 => X"555555500000000000000000000003FFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAA",
INIT_5A => X"003FFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAA9555555555555555",
INIT_5B => X"AAAAAAAAAAAAAAAAAAA955555555555555555555555000000000000000000000",
INIT_5C => X"555555555554000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFAAAA",
INIT_5D => X"03FFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAA5555555555555",
INIT_5E => X"AAAAAAAAAAAAAA95555555555555555555555555000000000000000000000000",
INIT_5F => X"000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAA",
INIT_60 => X"FFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAA955555555555555555555555555",
INIT_61 => X"55555555555555555550000000000000000000000000000FFFFFFFFFFFFFFFFF",
INIT_62 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAA9555555555",
INIT_63 => X"A955555555555555555555555555555400000000000000000000000000000FFF",
INIT_64 => X"0000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_65 => X"AAAA955555555555555555555555555555554000000000000000000000000000",
INIT_66 => X"003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_67 => X"5555555555555555555555555555555540000000000000000000000000000000",
INIT_68 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955",
INIT_69 => X"555555555555555540000000000000000000000000000000000003FFFFFFFFFF",
INIT_6A => X"FFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555555555555555555",
INIT_6B => X"000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6C => X"AAAAA95555555555555555555555555555555555555555554000000000000000",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_6E => X"0000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"AAAAAAA555555555555555555555555555555555555555555555555555000000",
INIT_70 => X"FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_71 => X"00000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_72 => X"5555555555555555555555555555550000000000000000000000000000000000",
INIT_73 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555555",
INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_75 => X"00000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"5555555555555555555555555555555555555555555555555540000000000000",
INIT_78 => X"AAAAAAAAAA955555555555555555555555555555555555555555555555555555",
INIT_79 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_7A => X"FFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(7 downto 6),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(7 downto 6),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"5555555555555555555555540000000000000000000000000000000000000000",
INIT_01 => X"FFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955555555555555555",
INIT_02 => X"00000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"AAAAAAAAAAA95555555555555555555555555555555555555555400000000000",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_05 => X"5555555555555555500000000000000000000000000000000000000000FFFFFF",
INIT_06 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555555555",
INIT_07 => X"00000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_08 => X"AAAA955555555555555555555555555555555555555554000000000000000000",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_0A => X"555555555400000000000000000000000000000000000000003FFFFFFFFFFFFF",
INIT_0B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555555555555555",
INIT_0C => X"00000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAA",
INIT_0D => X"5555555555555555555555555555555555554000000000000000000000000000",
INIT_0E => X"FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555",
INIT_0F => X"00000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"AAAAAAAAAAAAAAAAAAAAA9555555555555555555555555555555555555555550",
INIT_11 => X"00FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAA",
INIT_12 => X"5555555555555555555555550000000000000000000000000000000000000000",
INIT_13 => X"FFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555",
INIT_14 => X"00000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"AAAAAA5555555555555555555555555555555555555555550000000000000000",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_17 => X"5555554000000000000000000000000000000000000000000FFFFFFFFFFFFFFF",
INIT_18 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555555555555555555555",
INIT_19 => X"0000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAA",
INIT_1A => X"5555555555555555555555555554000000000000000000000000000000000000",
INIT_1B => X"FFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA9555555555555555",
INIT_1C => X"00000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"AAA5555555555555555555555555555555555555555555400000000000000000",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1F => X"00000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"AAAAAAAAAAAAAAAAAAA555555555555555555555555555555555555555555550",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_22 => X"5555555555555400000000000000000000000000000000000000000000FFFFFF",
INIT_23 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555",
INIT_24 => X"0000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAA",
INIT_25 => X"5555555555555555555555555000000000000000000000000000000000000000",
INIT_26 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955555555555555555555",
INIT_27 => X"0000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAA",
INIT_28 => X"5555555555555555555555555555555554000000000000000000000000000000",
INIT_29 => X"FFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555555555",
INIT_2A => X"000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"5555555555555555555555555555555555555500000000000000000000000000",
INIT_2C => X"FFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA9555555555",
INIT_2D => X"00000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"5555555555555555555555555555555555555550000000000000000000000000",
INIT_2F => X"FFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555555",
INIT_30 => X"000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_31 => X"5555555555555555555555555555555555500000000000000000000000000000",
INIT_32 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555",
INIT_33 => X"0000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA",
INIT_34 => X"5555555555555555555555555400000000000000000000000000000000000000",
INIT_35 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAA",
INIT_37 => X"555555555540000000000000000000000000000000000000000000000000000F",
INIT_38 => X"AAAAAAAAAAAAAAAAAAAAA9555555555555555555555555555555555555555555",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_3A => X"0000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFF",
INIT_3B => X"5555555555555555555555555555555555555555555555555555400000000000",
INIT_3C => X"FFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955",
INIT_3D => X"000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3E => X"5555555555555555555555000000000000000000000000000000000000000000",
INIT_3F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555555555555555555",
INIT_40 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_41 => X"00000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFF",
INIT_42 => X"5555555555555555555555555555555555555555555555000000000000000000",
INIT_43 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555",
INIT_44 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAA",
INIT_45 => X"000000000000000000000000000000000000000000000000000000000FFFFFFF",
INIT_46 => X"5555555555555555555555555555555555555555555555555555555555500000",
INIT_47 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555",
INIT_48 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAA",
INIT_49 => X"000000000000000000000000000000000000000000000000000000000003FFFF",
INIT_4A => X"5555555555555555555555555555555555555555555555555555555554000000",
INIT_4B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555",
INIT_4C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAA",
INIT_4D => X"0000000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFF",
INIT_4E => X"5555555555555555555555555555555555555550000000000000000000000000",
INIT_4F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555555555555555555",
INIT_50 => X"FFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_51 => X"00000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"5555555555555555555555555555555555555555555555555555555555555400",
INIT_54 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555",
INIT_55 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_56 => X"00000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"5555555555555555555555555555555555555555555555555555540000000000",
INIT_59 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555555",
INIT_5A => X"FFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5C => X"000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5D => X"5400000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_5F => X"AAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555555555",
INIT_60 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_61 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAA",
INIT_62 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000FFF",
INIT_64 => X"5555000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_66 => X"AA95555555555555555555555555555555555555555555555555555555555555",
INIT_67 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_68 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_69 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAA",
INIT_6A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6B => X"000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"5555555555555555555555555555555555555555554000000000000000000000",
INIT_6F => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_70 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_71 => X"AAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555555555555555555555",
INIT_72 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_73 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_74 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_75 => X"FFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => p_0_in(1 downto 0),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(9 downto 8),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"5555555555555555555555555555500000000000000000000000000000000000",
INIT_03 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_04 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_05 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555",
INIT_06 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"000000000000000000000000000000000000000000000000003FFFFFFFFFFFFF",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"5555555555555500000000000000000000000000000000000000000000000000",
INIT_0D => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0E => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955555555555555555555555",
INIT_10 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_11 => X"FFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"00000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"5555555555555555555555555555555555555555555555555000000000000000",
INIT_18 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_19 => X"AAAAAA9555555555555555555555555555555555555555555555555555555555",
INIT_1A => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"00000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"5555555555555555555555555555555555555555555555555555555555000000",
INIT_23 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_24 => X"AAAAAA9555555555555555555555555555555555555555555555555555555555",
INIT_25 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_26 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_27 => X"FFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"5555555555555555555555500000000000000000000000000000000000000000",
INIT_2E => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_2F => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_30 => X"AAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555555555555555",
INIT_31 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_32 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_33 => X"FFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"000000000000000000000000000000000000000000000000000000000000000F",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"5555555555555555555555555555555555555555554000000000000000000000",
INIT_3B => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3C => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3D => X"AAAAAAAAAAAAAA95555555555555555555555555555555555555555555555555",
INIT_3E => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_3F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_40 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_41 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAA",
INIT_42 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_43 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_44 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_45 => X"000000000000000000000000000000000000000000000000000000000FFFFFFF",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"5555555555555555555555555555555555555555555555555555555555540000",
INIT_4A => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_4B => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_4C => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_4D => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA9555555555555555555",
INIT_4E => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_50 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_51 => X"FFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_52 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_53 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_54 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_55 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_56 => X"00000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"5555555555555555555555555555555555550000000000000000000000000000",
INIT_5D => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_5E => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_5F => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_60 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_61 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_62 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_63 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555",
INIT_64 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_65 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_66 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_67 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_68 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_69 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_6A => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_6B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_6C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_70 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_71 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_73 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_75 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => p_0_in(3 downto 2),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(11 downto 10),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"5555555555555555555555555555555555555555555555555540000000000000",
INIT_0B => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0C => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0D => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0E => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0F => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_10 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_11 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_12 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_13 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_14 => X"AAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555555555555555555555",
INIT_15 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_16 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_17 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_18 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_19 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1A => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1C => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1D => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1E => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAA",
INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"5555555555555555555555555555555555555555555555555555555555555550",
INIT_38 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_39 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3A => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3B => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3C => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3D => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3E => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3F => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_40 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_41 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_42 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_43 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_44 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_45 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555",
INIT_46 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_47 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_48 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_49 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4A => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4C => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4D => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4E => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_50 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_51 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_52 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_53 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_54 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_55 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_56 => X"FFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_57 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_58 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_59 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_60 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_61 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_62 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_63 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_64 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_65 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_66 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_67 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_68 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_69 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_70 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_71 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_73 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_75 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => p_0_in(5 downto 4),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(13 downto 12),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000000000000000000000",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 0) => sin_addr(13 downto 0),
ADDRBWRADDR(13 downto 0) => cos_addr(13 downto 0),
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const0>\,
DIADI(0) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(15 downto 1) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => p_0_in(6),
DOBDO(15 downto 1) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOBDO_UNCONNECTED\(15 downto 1),
DOBDO(0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(14),
DOPADOP(1 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(0),
Q => mod_cos_addr(0),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(10),
Q => mod_cos_addr(10),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(11),
Q => mod_cos_addr(11),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(12),
Q => mod_cos_addr(12),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(13),
Q => mod_cos_addr(13),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(1),
Q => mod_cos_addr(1),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(2),
Q => mod_cos_addr(2),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(3),
Q => mod_cos_addr(3),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(4),
Q => mod_cos_addr(4),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(5),
Q => mod_cos_addr(5),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(6),
Q => mod_cos_addr(6),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(7),
Q => mod_cos_addr(7),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(8),
Q => mod_cos_addr(8),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(9),
Q => mod_cos_addr(9),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(0),
Q => mod_sin_addr(0),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(10),
Q => mod_sin_addr(10),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(11),
Q => mod_sin_addr(11),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(12),
Q => mod_sin_addr(12),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(13),
Q => mod_sin_addr(13),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(1),
Q => mod_sin_addr(1),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(2),
Q => mod_sin_addr(2),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(3),
Q => mod_sin_addr(3),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(4),
Q => mod_sin_addr(4),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(5),
Q => mod_sin_addr(5),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(6),
Q => mod_sin_addr(6),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(7),
Q => mod_sin_addr(7),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(8),
Q => mod_sin_addr(8),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(9),
Q => mod_sin_addr(9),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_3\
port map (
aclk => aclk,
m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(7 downto 0),
\out\(7 downto 0) => cos_ls1(7 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_4\
port map (
I1 => \n_6_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I2 => \n_5_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I3 => \n_4_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I4 => \n_3_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I5 => \n_2_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I6 => \n_1_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I7 => \n_0_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I8 => \n_7_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
aclk => aclk,
m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(15 downto 8),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14\
port map (
aclk => aclk,
m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(23 downto 16),
\out\(7 downto 0) => sin_ls1(7 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_2\
port map (
I1 => \n_6_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I2 => \n_5_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I3 => \n_4_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I4 => \n_3_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I5 => \n_2_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I6 => \n_1_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I7 => \n_0_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I8 => \n_7_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
aclk => aclk,
m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(31 downto 24),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized16\
port map (
DOBDO(0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0),
I1 => \n_22_i_rtl.i_quarter_table.i_addr_reg_c\,
I2 => \n_21_i_rtl.i_quarter_table.i_addr_reg_c\,
I3 => \n_20_i_rtl.i_quarter_table.i_addr_reg_c\,
I4 => \n_19_i_rtl.i_quarter_table.i_addr_reg_c\,
I5 => \n_17_i_rtl.i_quarter_table.i_addr_reg_c\,
I6 => \n_16_i_rtl.i_quarter_table.i_addr_reg_c\,
I7 => \n_15_i_rtl.i_quarter_table.i_addr_reg_c\,
I8 => \n_23_i_rtl.i_quarter_table.i_addr_reg_c\,
aclk => aclk,
\out\(8 downto 0) => cos_ls1(8 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_1\
port map (
I1 => \n_18_i_rtl.i_quarter_table.i_addr_reg_c\,
I2 => \n_30_i_rtl.i_quarter_table.i_addr_reg_c\,
I3 => \n_29_i_rtl.i_quarter_table.i_addr_reg_c\,
I4 => \n_28_i_rtl.i_quarter_table.i_addr_reg_c\,
I5 => \n_27_i_rtl.i_quarter_table.i_addr_reg_c\,
I6 => \n_26_i_rtl.i_quarter_table.i_addr_reg_c\,
I7 => \n_25_i_rtl.i_quarter_table.i_addr_reg_c\,
I8 => \n_24_i_rtl.i_quarter_table.i_addr_reg_c\,
O1 => \n_0_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O2 => \n_1_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O3 => \n_2_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O4 => \n_3_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O5 => \n_4_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O6 => \n_5_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O7 => \n_6_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O8 => \n_7_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
aclk => aclk,
\out\(0) => cos_ls1(8),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_original_sin_ls\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized16_5\
port map (
I1 => \n_9_i_rtl.i_quarter_table.i_addr_reg_c\,
I2 => \n_8_i_rtl.i_quarter_table.i_addr_reg_c\,
I3 => \n_10_i_rtl.i_quarter_table.i_addr_reg_c\,
I4 => \n_11_i_rtl.i_quarter_table.i_addr_reg_c\,
I5 => \n_13_i_rtl.i_quarter_table.i_addr_reg_c\,
I6 => \n_31_i_rtl.i_quarter_table.i_addr_reg_c\,
I7 => \n_12_i_rtl.i_quarter_table.i_addr_reg_c\,
I8 => \n_14_i_rtl.i_quarter_table.i_addr_reg_c\,
I9(0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(0),
aclk => aclk,
\out\(8 downto 0) => sin_ls1(8 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_6\
port map (
I1 => \n_1_i_rtl.i_quarter_table.i_addr_reg_c\,
I2 => \n_2_i_rtl.i_quarter_table.i_addr_reg_c\,
I3 => \n_3_i_rtl.i_quarter_table.i_addr_reg_c\,
I4 => \n_4_i_rtl.i_quarter_table.i_addr_reg_c\,
I5 => \n_5_i_rtl.i_quarter_table.i_addr_reg_c\,
I6 => \n_6_i_rtl.i_quarter_table.i_addr_reg_c\,
I7 => \n_7_i_rtl.i_quarter_table.i_addr_reg_c\,
O1 => \n_0_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O2 => \n_1_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O3 => \n_2_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O4 => \n_3_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O5 => \n_4_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O6 => \n_5_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O7 => \n_6_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O8 => \n_7_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
aclk => aclk,
invert_sin => invert_sin,
\out\(0) => sin_ls1(8),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(0),
Q => cos_addr(0),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(10),
Q => cos_addr(10),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(11),
Q => cos_addr(11),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(12),
Q => cos_addr(12),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(13),
Q => cos_addr(13),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(1),
Q => cos_addr(1),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(2),
Q => cos_addr(2),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(3),
Q => cos_addr(3),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(4),
Q => cos_addr(4),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(5),
Q => cos_addr(5),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(6),
Q => cos_addr(6),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(7),
Q => cos_addr(7),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(8),
Q => cos_addr(8),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(9),
Q => cos_addr(9),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(0),
Q => sin_addr(0),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(10),
Q => sin_addr(10),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(11),
Q => sin_addr(11),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(12),
Q => sin_addr(12),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(13),
Q => sin_addr(13),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(1),
Q => sin_addr(1),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(2),
Q => sin_addr(2),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(3),
Q => sin_addr(3),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(4),
Q => sin_addr(4),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(5),
Q => sin_addr(5),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(6),
Q => sin_addr(6),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(7),
Q => sin_addr(7),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(8),
Q => sin_addr(8),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(9),
Q => sin_addr(9),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsdds_compiler_v6_0_core is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
reg_s_phase_fifo_din : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
end ddsdds_compiler_v6_0_core;
architecture STRUCTURE of ddsdds_compiler_v6_0_core is
signal acc_phase_shaped : STD_LOGIC_VECTOR ( 15 downto 14 );
signal asyn_mod_sin_addr : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \n_16_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_17_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_18_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_19_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_20_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_21_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_22_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_23_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_24_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_25_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_26_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_27_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_28_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_29_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
begin
\I_PHASEGEN.i_conventional_accum.i_accum\: entity work.ddsaccum
port map (
D(13 downto 0) => asyn_mod_sin_addr(13 downto 0),
I1(13) => \n_16_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(12) => \n_17_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(11) => \n_18_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(10) => \n_19_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(9) => \n_20_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(8) => \n_21_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(7) => \n_22_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(6) => \n_23_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(5) => \n_24_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(4) => \n_25_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(3) => \n_26_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(2) => \n_27_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(1) => \n_28_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(0) => \n_29_I_PHASEGEN.i_conventional_accum.i_accum\,
L(1 downto 0) => acc_phase_shaped(15 downto 14),
aclk => aclk,
reg_s_phase_fifo_din(15 downto 0) => reg_s_phase_fifo_din(15 downto 0),
s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\I_SINCOS.i_std_rom.i_rom\: entity work.\ddssin_cos__parameterized0\
port map (
D(13 downto 0) => asyn_mod_sin_addr(13 downto 0),
I1(13) => \n_16_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(12) => \n_17_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(11) => \n_18_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(10) => \n_19_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(9) => \n_20_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(8) => \n_21_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(7) => \n_22_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(6) => \n_23_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(5) => \n_24_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(4) => \n_25_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(3) => \n_26_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(2) => \n_27_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(1) => \n_28_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(0) => \n_29_I_PHASEGEN.i_conventional_accum.i_accum\,
L(1 downto 0) => acc_phase_shaped(15 downto 14),
aclk => aclk,
m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rdy.rdy_logic\: entity work.ddsdds_compiler_v6_0_rdy
port map (
aclk => aclk,
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsdds_compiler_v6_0_viv__parameterized0\ is
port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tready : out STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_phase_tlast : in STD_LOGIC;
s_axis_phase_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tvalid : in STD_LOGIC;
s_axis_config_tready : out STD_LOGIC;
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tlast : in STD_LOGIC;
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tready : in STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_data_tlast : out STD_LOGIC;
m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tvalid : out STD_LOGIC;
m_axis_phase_tready : in STD_LOGIC;
m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tlast : out STD_LOGIC;
m_axis_phase_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
event_pinc_invalid : out STD_LOGIC;
event_poff_invalid : out STD_LOGIC;
event_phase_in_invalid : out STD_LOGIC;
event_s_phase_tlast_missing : out STD_LOGIC;
event_s_phase_tlast_unexpected : out STD_LOGIC;
event_s_phase_chanid_incorrect : out STD_LOGIC;
event_s_config_tlast_missing : out STD_LOGIC;
event_s_config_tlast_unexpected : out STD_LOGIC;
debug_axi_pinc_in : out STD_LOGIC_VECTOR ( 15 downto 0 );
debug_axi_poff_in : out STD_LOGIC_VECTOR ( 15 downto 0 );
debug_axi_resync_in : out STD_LOGIC;
debug_axi_chan_in : out STD_LOGIC_VECTOR ( 0 to 0 );
debug_core_nd : out STD_LOGIC;
debug_phase : out STD_LOGIC_VECTOR ( 15 downto 0 );
debug_phase_nd : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "dds_compiler_v6_0_viv";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "zynq";
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 9;
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 16;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_LATENCY : integer;
attribute C_LATENCY of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 7;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 2;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 16;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 16;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_RESYNC : integer;
attribute C_RESYNC of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_POR_MODE : integer;
attribute C_POR_MODE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 16;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 32;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "yes";
end \ddsdds_compiler_v6_0_viv__parameterized0\;
architecture STRUCTURE of \ddsdds_compiler_v6_0_viv__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal reg_s_phase_fifo_din : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
debug_axi_chan_in(0) <= \<const0>\;
debug_axi_pinc_in(15) <= \<const0>\;
debug_axi_pinc_in(14) <= \<const0>\;
debug_axi_pinc_in(13) <= \<const0>\;
debug_axi_pinc_in(12) <= \<const0>\;
debug_axi_pinc_in(11) <= \<const0>\;
debug_axi_pinc_in(10) <= \<const0>\;
debug_axi_pinc_in(9) <= \<const0>\;
debug_axi_pinc_in(8) <= \<const0>\;
debug_axi_pinc_in(7) <= \<const0>\;
debug_axi_pinc_in(6) <= \<const0>\;
debug_axi_pinc_in(5) <= \<const0>\;
debug_axi_pinc_in(4) <= \<const0>\;
debug_axi_pinc_in(3) <= \<const0>\;
debug_axi_pinc_in(2) <= \<const0>\;
debug_axi_pinc_in(1) <= \<const0>\;
debug_axi_pinc_in(0) <= \<const0>\;
debug_axi_poff_in(15) <= \<const0>\;
debug_axi_poff_in(14) <= \<const0>\;
debug_axi_poff_in(13) <= \<const0>\;
debug_axi_poff_in(12) <= \<const0>\;
debug_axi_poff_in(11) <= \<const0>\;
debug_axi_poff_in(10) <= \<const0>\;
debug_axi_poff_in(9) <= \<const0>\;
debug_axi_poff_in(8) <= \<const0>\;
debug_axi_poff_in(7) <= \<const0>\;
debug_axi_poff_in(6) <= \<const0>\;
debug_axi_poff_in(5) <= \<const0>\;
debug_axi_poff_in(4) <= \<const0>\;
debug_axi_poff_in(3) <= \<const0>\;
debug_axi_poff_in(2) <= \<const0>\;
debug_axi_poff_in(1) <= \<const0>\;
debug_axi_poff_in(0) <= \<const0>\;
debug_axi_resync_in <= \<const0>\;
debug_core_nd <= \<const0>\;
debug_phase(15) <= \<const0>\;
debug_phase(14) <= \<const0>\;
debug_phase(13) <= \<const0>\;
debug_phase(12) <= \<const0>\;
debug_phase(11) <= \<const0>\;
debug_phase(10) <= \<const0>\;
debug_phase(9) <= \<const0>\;
debug_phase(8) <= \<const0>\;
debug_phase(7) <= \<const0>\;
debug_phase(6) <= \<const0>\;
debug_phase(5) <= \<const0>\;
debug_phase(4) <= \<const0>\;
debug_phase(3) <= \<const0>\;
debug_phase(2) <= \<const0>\;
debug_phase(1) <= \<const0>\;
debug_phase(0) <= \<const0>\;
debug_phase_nd <= \<const0>\;
event_phase_in_invalid <= \<const0>\;
event_pinc_invalid <= \<const0>\;
event_poff_invalid <= \<const0>\;
event_s_config_tlast_missing <= \<const0>\;
event_s_config_tlast_unexpected <= \<const0>\;
event_s_phase_chanid_incorrect <= \<const0>\;
event_s_phase_tlast_missing <= \<const0>\;
event_s_phase_tlast_unexpected <= \<const0>\;
m_axis_data_tlast <= \<const0>\;
m_axis_data_tuser(0) <= \<const0>\;
m_axis_phase_tdata(0) <= \<const0>\;
m_axis_phase_tlast <= \<const0>\;
m_axis_phase_tuser(0) <= \<const0>\;
m_axis_phase_tvalid <= \<const0>\;
s_axis_config_tready <= \<const0>\;
s_axis_phase_tready <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\has_s_phase.ce_i_delay\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized0\
port map (
aclk => aclk
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(0),
Q => reg_s_phase_fifo_din(0),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(10),
Q => reg_s_phase_fifo_din(10),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(11),
Q => reg_s_phase_fifo_din(11),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(12),
Q => reg_s_phase_fifo_din(12),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(13),
Q => reg_s_phase_fifo_din(13),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(14),
Q => reg_s_phase_fifo_din(14),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(15),
Q => reg_s_phase_fifo_din(15),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(1),
Q => reg_s_phase_fifo_din(1),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(2),
Q => reg_s_phase_fifo_din(2),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(3),
Q => reg_s_phase_fifo_din(3),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(4),
Q => reg_s_phase_fifo_din(4),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(5),
Q => reg_s_phase_fifo_din(5),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(6),
Q => reg_s_phase_fifo_din(6),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(7),
Q => reg_s_phase_fifo_din(7),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(8),
Q => reg_s_phase_fifo_din(8),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(9),
Q => reg_s_phase_fifo_din(9),
R => \<const0>\
);
i_dds: entity work.ddsdds_compiler_v6_0_core
port map (
aclk => aclk,
m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0),
reg_s_phase_fifo_din(15 downto 0) => reg_s_phase_fifo_din(15 downto 0),
s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_has_nd_rdy_pipe.channel_pipe\: entity work.ddsxbip_pipe_v3_0_viv_0
port map (
aclk => aclk,
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_has_nd_rdy_pipe.valid_phase_read_del\: entity work.ddsxbip_pipe_v3_0_viv
port map (
aclk => aclk,
m_axis_data_tvalid => m_axis_data_tvalid,
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsdds_compiler_v6_0__parameterized0\ is
port (
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
aclk : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsdds_compiler_v6_0__parameterized0\ : entity is "dds_compiler_v6_0";
end \ddsdds_compiler_v6_0__parameterized0\;
architecture STRUCTURE of \ddsdds_compiler_v6_0__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal NLW_i_synth_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_core_nd_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_phase_nd_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_phase_in_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_pinc_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_poff_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_data_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_phase_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_config_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_phase_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_axi_chan_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_debug_axi_pinc_in_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_i_synth_debug_axi_poff_in_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_i_synth_debug_phase_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_i_synth_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_m_axis_phase_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_m_axis_phase_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of i_synth : label is 16;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of i_synth : label is 0;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of i_synth : label is 1;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of i_synth : label is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of i_synth : label is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of i_synth : label is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of i_synth : label is 0;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of i_synth : label is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of i_synth : label is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of i_synth : label is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of i_synth : label is 0;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of i_synth : label is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of i_synth : label is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of i_synth : label is 1;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of i_synth : label is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of i_synth : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of i_synth : label is 7;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of i_synth : label is 1;
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of i_synth : label is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of i_synth : label is 9;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of i_synth : label is 0;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of i_synth : label is 32;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of i_synth : label is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of i_synth : label is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of i_synth : label is 0;
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of i_synth : label is 0;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of i_synth : label is 2;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of i_synth : label is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of i_synth : label is 16;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of i_synth : label is 16;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of i_synth : label is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of i_synth : label is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE : integer;
attribute C_POR_MODE of i_synth : label is 0;
attribute C_RESYNC : integer;
attribute C_RESYNC of i_synth : label is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of i_synth : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of i_synth : label is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of i_synth : label is 16;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of i_synth : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of i_synth : label is "zynq";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of i_synth : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
i_synth: entity work.\ddsdds_compiler_v6_0_viv__parameterized0\
port map (
aclk => aclk,
aclken => \<const1>\,
aresetn => \<const1>\,
debug_axi_chan_in(0) => NLW_i_synth_debug_axi_chan_in_UNCONNECTED(0),
debug_axi_pinc_in(15 downto 0) => NLW_i_synth_debug_axi_pinc_in_UNCONNECTED(15 downto 0),
debug_axi_poff_in(15 downto 0) => NLW_i_synth_debug_axi_poff_in_UNCONNECTED(15 downto 0),
debug_axi_resync_in => NLW_i_synth_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => NLW_i_synth_debug_core_nd_UNCONNECTED,
debug_phase(15 downto 0) => NLW_i_synth_debug_phase_UNCONNECTED(15 downto 0),
debug_phase_nd => NLW_i_synth_debug_phase_nd_UNCONNECTED,
event_phase_in_invalid => NLW_i_synth_event_phase_in_invalid_UNCONNECTED,
event_pinc_invalid => NLW_i_synth_event_pinc_invalid_UNCONNECTED,
event_poff_invalid => NLW_i_synth_event_poff_invalid_UNCONNECTED,
event_s_config_tlast_missing => NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED,
event_s_config_tlast_unexpected => NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED,
event_s_phase_chanid_incorrect => NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED,
event_s_phase_tlast_missing => NLW_i_synth_event_s_phase_tlast_missing_UNCONNECTED,
event_s_phase_tlast_unexpected => NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED,
m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0),
m_axis_data_tlast => NLW_i_synth_m_axis_data_tlast_UNCONNECTED,
m_axis_data_tready => \<const0>\,
m_axis_data_tuser(0) => NLW_i_synth_m_axis_data_tuser_UNCONNECTED(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(0) => NLW_i_synth_m_axis_phase_tdata_UNCONNECTED(0),
m_axis_phase_tlast => NLW_i_synth_m_axis_phase_tlast_UNCONNECTED,
m_axis_phase_tready => \<const0>\,
m_axis_phase_tuser(0) => NLW_i_synth_m_axis_phase_tuser_UNCONNECTED(0),
m_axis_phase_tvalid => NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED,
s_axis_config_tdata(0) => \<const0>\,
s_axis_config_tlast => \<const0>\,
s_axis_config_tready => NLW_i_synth_s_axis_config_tready_UNCONNECTED,
s_axis_config_tvalid => \<const0>\,
s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0),
s_axis_phase_tlast => \<const0>\,
s_axis_phase_tready => NLW_i_synth_s_axis_phase_tready_UNCONNECTED,
s_axis_phase_tuser(0) => \<const0>\,
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity dds is
port (
aclk : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of dds : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of dds : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of dds : entity is "dds_compiler_v6_0,Vivado 2013.4";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of dds : entity is "dds,dds_compiler_v6_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of dds : entity is "dds,dds_compiler_v6_0,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dds_compiler,x_ipVersion=6.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,C_XDEVICEFAMILY=zynq,C_MODE_OF_OPERATION=0,C_MODULUS=9,C_ACCUMULATOR_WIDTH=16,C_CHANNELS=1,C_HAS_PHASE_OUT=0,C_HAS_PHASEGEN=1,C_HAS_SINCOS=1,C_LATENCY=7,C_MEM_TYPE=1,C_NEGATIVE_COSINE=0,C_NEGATIVE_SINE=0,C_NOISE_SHAPING=0,C_OUTPUTS_REQUIRED=2,C_OUTPUT_FORM=0,C_OUTPUT_WIDTH=16,C_PHASE_ANGLE_WIDTH=16,C_PHASE_INCREMENT=3,C_PHASE_INCREMENT_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_RESYNC=0,C_PHASE_OFFSET=0,C_PHASE_OFFSET_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_OPTIMISE_GOAL=0,C_USE_DSP48=0,C_POR_MODE=0,C_AMPLITUDE=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_HAS_TLAST=0,C_HAS_TREADY=0,C_HAS_S_PHASE=1,C_S_PHASE_TDATA_WIDTH=16,C_S_PHASE_HAS_TUSER=0,C_S_PHASE_TUSER_WIDTH=1,C_HAS_S_CONFIG=0,C_S_CONFIG_SYNC_MODE=0,C_S_CONFIG_TDATA_WIDTH=1,C_HAS_M_DATA=1,C_M_DATA_TDATA_WIDTH=32,C_M_DATA_HAS_TUSER=0,C_M_DATA_TUSER_WIDTH=1,C_HAS_M_PHASE=0,C_M_PHASE_TDATA_WIDTH=1,C_M_PHASE_HAS_TUSER=0,C_M_PHASE_TUSER_WIDTH=1,C_DEBUG_INTERFACE=0,C_CHAN_WIDTH=1}";
end dds;
architecture STRUCTURE of dds is
begin
U0: entity work.\ddsdds_compiler_v6_0__parameterized0\
port map (
aclk => aclk,
m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0),
m_axis_data_tvalid => m_axis_data_tvalid,
s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
|
-- Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
-- Date : Thu Mar 27 13:22:53 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim /home/keith/Documents/VHDL-lib/top/lab_3/part_2/ip/dds/dds_funcsim.vhdl
-- Design : dds
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddspipe_add__parameterized0\ is
port (
temp : out STD_LOGIC_VECTOR ( 16 downto 0 );
L : in STD_LOGIC_VECTOR ( 15 downto 0 );
reg_s_phase_fifo_din : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddspipe_add__parameterized0\ : entity is "pipe_add";
end \ddspipe_add__parameterized0\;
architecture STRUCTURE of \ddspipe_add__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[11]_i_2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[11]_i_3\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[11]_i_4\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[11]_i_5\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[15]_i_2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[15]_i_3\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[15]_i_4\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[15]_i_5\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[3]_i_2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[3]_i_3\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[3]_i_4\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[3]_i_5\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[7]_i_2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[7]_i_3\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[7]_i_4\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[7]_i_5\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC;
signal \n_1_opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC;
signal \n_1_opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC;
signal \n_1_opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC;
signal \n_1_opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC;
signal \n_2_opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC;
signal \n_2_opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC;
signal \n_2_opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC;
signal \n_2_opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC;
signal \n_3_opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC;
signal \n_3_opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC;
signal \n_3_opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC;
signal \n_3_opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC;
signal \NLW_opt_has_pipe.first_q_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_opt_has_pipe.first_q_reg[16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\opt_has_pipe.first_q[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(11),
I1 => reg_s_phase_fifo_din(11),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(11),
O => \n_0_opt_has_pipe.first_q[11]_i_2\
);
\opt_has_pipe.first_q[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(10),
I1 => reg_s_phase_fifo_din(10),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(10),
O => \n_0_opt_has_pipe.first_q[11]_i_3\
);
\opt_has_pipe.first_q[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(9),
I1 => reg_s_phase_fifo_din(9),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(9),
O => \n_0_opt_has_pipe.first_q[11]_i_4\
);
\opt_has_pipe.first_q[11]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(8),
I1 => reg_s_phase_fifo_din(8),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(8),
O => \n_0_opt_has_pipe.first_q[11]_i_5\
);
\opt_has_pipe.first_q[15]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(15),
I1 => reg_s_phase_fifo_din(15),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(15),
O => \n_0_opt_has_pipe.first_q[15]_i_2\
);
\opt_has_pipe.first_q[15]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(14),
I1 => reg_s_phase_fifo_din(14),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(14),
O => \n_0_opt_has_pipe.first_q[15]_i_3\
);
\opt_has_pipe.first_q[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(13),
I1 => reg_s_phase_fifo_din(13),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(13),
O => \n_0_opt_has_pipe.first_q[15]_i_4\
);
\opt_has_pipe.first_q[15]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(12),
I1 => reg_s_phase_fifo_din(12),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(12),
O => \n_0_opt_has_pipe.first_q[15]_i_5\
);
\opt_has_pipe.first_q[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(3),
I1 => reg_s_phase_fifo_din(3),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(3),
O => \n_0_opt_has_pipe.first_q[3]_i_2\
);
\opt_has_pipe.first_q[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(2),
I1 => reg_s_phase_fifo_din(2),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(2),
O => \n_0_opt_has_pipe.first_q[3]_i_3\
);
\opt_has_pipe.first_q[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(1),
I1 => reg_s_phase_fifo_din(1),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(1),
O => \n_0_opt_has_pipe.first_q[3]_i_4\
);
\opt_has_pipe.first_q[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(0),
I1 => reg_s_phase_fifo_din(0),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(0),
O => \n_0_opt_has_pipe.first_q[3]_i_5\
);
\opt_has_pipe.first_q[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(7),
I1 => reg_s_phase_fifo_din(7),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(7),
O => \n_0_opt_has_pipe.first_q[7]_i_2\
);
\opt_has_pipe.first_q[7]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(6),
I1 => reg_s_phase_fifo_din(6),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(6),
O => \n_0_opt_has_pipe.first_q[7]_i_3\
);
\opt_has_pipe.first_q[7]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(5),
I1 => reg_s_phase_fifo_din(5),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(5),
O => \n_0_opt_has_pipe.first_q[7]_i_4\
);
\opt_has_pipe.first_q[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => L(4),
I1 => reg_s_phase_fifo_din(4),
I2 => s_axis_phase_tvalid,
I3 => s_axis_phase_tdata(4),
O => \n_0_opt_has_pipe.first_q[7]_i_5\
);
\opt_has_pipe.first_q_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_opt_has_pipe.first_q_reg[7]_i_1\,
CO(3) => \n_0_opt_has_pipe.first_q_reg[11]_i_1\,
CO(2) => \n_1_opt_has_pipe.first_q_reg[11]_i_1\,
CO(1) => \n_2_opt_has_pipe.first_q_reg[11]_i_1\,
CO(0) => \n_3_opt_has_pipe.first_q_reg[11]_i_1\,
CYINIT => \<const0>\,
DI(3 downto 0) => L(11 downto 8),
O(3 downto 0) => temp(11 downto 8),
S(3) => \n_0_opt_has_pipe.first_q[11]_i_2\,
S(2) => \n_0_opt_has_pipe.first_q[11]_i_3\,
S(1) => \n_0_opt_has_pipe.first_q[11]_i_4\,
S(0) => \n_0_opt_has_pipe.first_q[11]_i_5\
);
\opt_has_pipe.first_q_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_opt_has_pipe.first_q_reg[11]_i_1\,
CO(3) => \n_0_opt_has_pipe.first_q_reg[15]_i_1\,
CO(2) => \n_1_opt_has_pipe.first_q_reg[15]_i_1\,
CO(1) => \n_2_opt_has_pipe.first_q_reg[15]_i_1\,
CO(0) => \n_3_opt_has_pipe.first_q_reg[15]_i_1\,
CYINIT => \<const0>\,
DI(3 downto 0) => L(15 downto 12),
O(3 downto 0) => temp(15 downto 12),
S(3) => \n_0_opt_has_pipe.first_q[15]_i_2\,
S(2) => \n_0_opt_has_pipe.first_q[15]_i_3\,
S(1) => \n_0_opt_has_pipe.first_q[15]_i_4\,
S(0) => \n_0_opt_has_pipe.first_q[15]_i_5\
);
\opt_has_pipe.first_q_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_opt_has_pipe.first_q_reg[15]_i_1\,
CO(3 downto 1) => \NLW_opt_has_pipe.first_q_reg[16]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => temp(16),
CYINIT => \<const0>\,
DI(3) => \<const0>\,
DI(2) => \<const0>\,
DI(1) => \<const0>\,
DI(0) => \<const0>\,
O(3 downto 0) => \NLW_opt_has_pipe.first_q_reg[16]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \<const0>\,
S(2) => \<const0>\,
S(1) => \<const0>\,
S(0) => \<const1>\
);
\opt_has_pipe.first_q_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \<const0>\,
CO(3) => \n_0_opt_has_pipe.first_q_reg[3]_i_1\,
CO(2) => \n_1_opt_has_pipe.first_q_reg[3]_i_1\,
CO(1) => \n_2_opt_has_pipe.first_q_reg[3]_i_1\,
CO(0) => \n_3_opt_has_pipe.first_q_reg[3]_i_1\,
CYINIT => \<const0>\,
DI(3 downto 0) => L(3 downto 0),
O(3 downto 0) => temp(3 downto 0),
S(3) => \n_0_opt_has_pipe.first_q[3]_i_2\,
S(2) => \n_0_opt_has_pipe.first_q[3]_i_3\,
S(1) => \n_0_opt_has_pipe.first_q[3]_i_4\,
S(0) => \n_0_opt_has_pipe.first_q[3]_i_5\
);
\opt_has_pipe.first_q_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_opt_has_pipe.first_q_reg[3]_i_1\,
CO(3) => \n_0_opt_has_pipe.first_q_reg[7]_i_1\,
CO(2) => \n_1_opt_has_pipe.first_q_reg[7]_i_1\,
CO(1) => \n_2_opt_has_pipe.first_q_reg[7]_i_1\,
CO(0) => \n_3_opt_has_pipe.first_q_reg[7]_i_1\,
CYINIT => \<const0>\,
DI(3 downto 0) => L(7 downto 4),
O(3 downto 0) => temp(7 downto 4),
S(3) => \n_0_opt_has_pipe.first_q[7]_i_2\,
S(2) => \n_0_opt_has_pipe.first_q[7]_i_3\,
S(1) => \n_0_opt_has_pipe.first_q[7]_i_4\,
S(0) => \n_0_opt_has_pipe.first_q[7]_i_5\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsxbip_pipe_v3_0_viv is
port (
m_axis_data_tvalid : out STD_LOGIC;
aclk : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC
);
end ddsxbip_pipe_v3_0_viv;
architecture STRUCTURE of ddsxbip_pipe_v3_0_viv is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal first_q : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of first_q : signal is "true";
signal \n_0_opt_has_pipe.first_q[0]_i_1__0\ : STD_LOGIC;
signal \n_0_opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\ : STD_LOGIC;
signal rdy_stream_i : STD_LOGIC;
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute srl_bus_name : string;
attribute srl_bus_name of \opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\ : label is "\U0/i_synth /\i_has_nd_rdy_pipe.valid_phase_read_del/opt_has_pipe.i_pipe[6].pipe_reg[6] ";
attribute srl_name : string;
attribute srl_name of \opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\ : label is "\U0/i_synth /\i_has_nd_rdy_pipe.valid_phase_read_del/opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5 ";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
m_axis_data_tvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axis_phase_tvalid,
I1 => rdy_stream_i,
O => m_axis_data_tvalid
);
\opt_has_pipe.first_q[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axis_phase_tvalid,
I1 => first_q,
O => \n_0_opt_has_pipe.first_q[0]_i_1__0\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \n_0_opt_has_pipe.first_q[0]_i_1__0\,
Q => first_q,
R => \<const0>\
);
\opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \<const0>\,
A1 => \<const0>\,
A2 => \<const1>\,
A3 => \<const0>\,
CE => s_axis_phase_tvalid,
CLK => aclk,
D => first_q,
Q => \n_0_opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\
);
\opt_has_pipe.i_pipe[7].pipe_reg[7][0]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \n_0_opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\,
Q => rdy_stream_i,
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsxbip_pipe_v3_0_viv_0 is
port (
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ddsxbip_pipe_v3_0_viv_0 : entity is "xbip_pipe_v3_0_viv";
end ddsxbip_pipe_v3_0_viv_0;
architecture STRUCTURE of ddsxbip_pipe_v3_0_viv_0 is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of first_q : signal is "true";
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \<const0>\,
Q => first_q,
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized0\ is
port (
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized0\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized0\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal first_q : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of first_q : signal is "true";
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \<const1>\,
Q => first_q,
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized12\ is
port (
invert_sin : out STD_LOGIC;
O1 : out STD_LOGIC;
O2 : out STD_LOGIC;
O3 : out STD_LOGIC;
O4 : out STD_LOGIC;
O5 : out STD_LOGIC;
O6 : out STD_LOGIC;
O7 : out STD_LOGIC;
O8 : out STD_LOGIC;
O9 : out STD_LOGIC;
O10 : out STD_LOGIC;
O11 : out STD_LOGIC;
O12 : out STD_LOGIC;
O13 : out STD_LOGIC;
O14 : out STD_LOGIC;
O15 : out STD_LOGIC;
O16 : out STD_LOGIC;
O17 : out STD_LOGIC;
O18 : out STD_LOGIC;
O19 : out STD_LOGIC;
O20 : out STD_LOGIC;
O21 : out STD_LOGIC;
O22 : out STD_LOGIC;
O23 : out STD_LOGIC;
O24 : out STD_LOGIC;
O25 : out STD_LOGIC;
O26 : out STD_LOGIC;
O27 : out STD_LOGIC;
O28 : out STD_LOGIC;
O29 : out STD_LOGIC;
O30 : out STD_LOGIC;
O31 : out STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 14 downto 0 );
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\ : in STD_LOGIC_VECTOR ( 14 downto 0 );
L : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized12\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized12\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized12\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^o18\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^invert_sin\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[8]_i_2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[8]_i_2__0\ : STD_LOGIC;
signal \n_0_opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\ : STD_LOGIC;
signal \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[0]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[0]_i_1__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[1]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[1]_i_1__0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[1]_i_1__1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[1]_i_1__2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[2]_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[2]_i_1__1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[2]_i_1__2\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[3]_i_1__1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[3]_i_1__4\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[4]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[4]_i_1__2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[5]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[5]_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[5]_i_1__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[5]_i_1__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[6]_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[6]_i_1__2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[7]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[7]_i_1__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \opt_has_pipe.first_q[8]_i_1\ : label is "soft_lutpair0";
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute srl_bus_name : string;
attribute srl_bus_name of \opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\ : label is "\U0/i_synth /\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3] ";
attribute srl_name : string;
attribute srl_name of \opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\ : label is "\U0/i_synth /\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2 ";
attribute srl_bus_name of \opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\ : label is "\U0/i_synth /\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3] ";
attribute srl_name of \opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\ : label is "\U0/i_synth /\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2 ";
begin
O18 <= \^o18\;
invert_sin <= \^invert_sin\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\opt_has_pipe.first_q[0]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(8),
O => O7
);
\opt_has_pipe.first_q[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(8),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O24
);
\opt_has_pipe.first_q[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(9),
O => O6
);
\opt_has_pipe.first_q[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \out\(1),
I1 => \out\(0),
I2 => \^invert_sin\,
O => O14
);
\opt_has_pipe.first_q[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"D728"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0),
I1 => \^invert_sin\,
I2 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I3 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1),
O => O23
);
\opt_has_pipe.first_q[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(9),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O25
);
\opt_has_pipe.first_q[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(10),
O => O5
);
\opt_has_pipe.first_q[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1EF0"
)
port map (
I0 => \out\(0),
I1 => \out\(1),
I2 => \out\(2),
I3 => \^invert_sin\,
O => O12
);
\opt_has_pipe.first_q[2]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F11F0EE0"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1),
I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0),
I2 => \^invert_sin\,
I3 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I4 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(2),
O => O15
);
\opt_has_pipe.first_q[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(10),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O26
);
\opt_has_pipe.first_q[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(11),
O => O4
);
\opt_has_pipe.first_q[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0101FF00FEFE00"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0),
I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1),
I2 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(2),
I3 => \^invert_sin\,
I4 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(3),
O => O16
);
\opt_has_pipe.first_q[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(11),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O27
);
\opt_has_pipe.first_q[3]_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FEFF00"
)
port map (
I0 => \out\(1),
I1 => \out\(0),
I2 => \out\(2),
I3 => \out\(3),
I4 => \^invert_sin\,
O => O31
);
\opt_has_pipe.first_q[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(12),
O => O3
);
\opt_has_pipe.first_q[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001FFFFFFFE0000"
)
port map (
I0 => \out\(1),
I1 => \out\(0),
I2 => \out\(2),
I3 => \out\(3),
I4 => \^invert_sin\,
I5 => \out\(4),
O => O13
);
\opt_has_pipe.first_q[4]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001FFFFFFFE0000"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(3),
I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(2),
I2 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1),
I3 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0),
I4 => \^o18\,
I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4),
O => O17
);
\opt_has_pipe.first_q[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(12),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O28
);
\opt_has_pipe.first_q[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(13),
O => O2
);
\opt_has_pipe.first_q[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_0_opt_has_pipe.first_q[8]_i_2\,
I1 => \out\(5),
I2 => \^invert_sin\,
O => O11
);
\opt_has_pipe.first_q[5]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D11D2EE2"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4),
I1 => \n_0_opt_has_pipe.first_q[8]_i_2__0\,
I2 => \^invert_sin\,
I3 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I4 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5),
O => O19
);
\opt_has_pipe.first_q[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(13),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O29
);
\opt_has_pipe.first_q[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \out\(14),
O => O1
);
\opt_has_pipe.first_q[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"4B78"
)
port map (
I0 => \out\(5),
I1 => \n_0_opt_has_pipe.first_q[8]_i_2\,
I2 => \out\(6),
I3 => \^invert_sin\,
O => O10
);
\opt_has_pipe.first_q[6]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DF0101DF20FEFE20"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5),
I1 => \n_0_opt_has_pipe.first_q[8]_i_2__0\,
I2 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4),
I3 => \^invert_sin\,
I4 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(6),
O => O20
);
\opt_has_pipe.first_q[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(14),
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I2 => \^invert_sin\,
O => O30
);
\opt_has_pipe.first_q[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FB7F80"
)
port map (
I0 => \out\(6),
I1 => \n_0_opt_has_pipe.first_q[8]_i_2\,
I2 => \out\(5),
I3 => \out\(7),
I4 => \^invert_sin\,
O => O8
);
\opt_has_pipe.first_q[7]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001F7FFFFFE0800"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(6),
I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4),
I2 => \n_0_opt_has_pipe.first_q[8]_i_2__0\,
I3 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5),
I4 => \^o18\,
I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(7),
O => O21
);
\opt_has_pipe.first_q[7]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^invert_sin\,
I1 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
O => \^o18\
);
\opt_has_pipe.first_q[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00048000"
)
port map (
I0 => \out\(6),
I1 => \n_0_opt_has_pipe.first_q[8]_i_2\,
I2 => \out\(5),
I3 => \out\(7),
I4 => \^invert_sin\,
O => O9
);
\opt_has_pipe.first_q[8]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000080000010000"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(6),
I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4),
I2 => \n_0_opt_has_pipe.first_q[8]_i_2__0\,
I3 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5),
I4 => \^o18\,
I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(7),
O => O22
);
\opt_has_pipe.first_q[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \out\(3),
I1 => \out\(2),
I2 => \out\(0),
I3 => \out\(1),
I4 => \out\(4),
I5 => \^invert_sin\,
O => \n_0_opt_has_pipe.first_q[8]_i_2\
);
\opt_has_pipe.first_q[8]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFEFF"
)
port map (
I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0),
I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1),
I2 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(2),
I3 => \^invert_sin\,
I4 => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(3),
O => \n_0_opt_has_pipe.first_q[8]_i_2__0\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => L(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => L(1),
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \<const1>\,
A1 => \<const0>\,
A2 => \<const0>\,
A3 => \<const0>\,
CE => s_axis_phase_tvalid,
CLK => aclk,
D => first_q(0),
Q => \n_0_opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\
);
\opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \<const1>\,
A1 => \<const0>\,
A2 => \<const0>\,
A3 => \<const0>\,
CE => s_axis_phase_tvalid,
CLK => aclk,
D => first_q(1),
Q => \n_0_opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\
);
\opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \n_0_opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\,
Q => \n_0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\,
R => \<const0>\
);
\opt_has_pipe.i_pipe[4].pipe_reg[4][1]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \n_0_opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\,
Q => \^invert_sin\,
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized14\ is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized14\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => m_axis_data_tdata(7)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => m_axis_data_tdata(6)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => m_axis_data_tdata(5)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => m_axis_data_tdata(4)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => m_axis_data_tdata(3)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => m_axis_data_tdata(2)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => m_axis_data_tdata(1)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => m_axis_data_tdata(0)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(1),
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(2),
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(3),
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(4),
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(5),
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(6),
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(7),
Q => first_q(7),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized14_1\ is
port (
O1 : out STD_LOGIC;
O2 : out STD_LOGIC;
O3 : out STD_LOGIC;
O4 : out STD_LOGIC;
O5 : out STD_LOGIC;
O6 : out STD_LOGIC;
O7 : out STD_LOGIC;
O8 : out STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_phase_tvalid : in STD_LOGIC;
I1 : in STD_LOGIC;
aclk : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
I5 : in STD_LOGIC;
I6 : in STD_LOGIC;
I7 : in STD_LOGIC;
I8 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_1\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized14_1\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_1\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \n_0_opt_has_pipe.first_q[7]_i_2__0\ : STD_LOGIC;
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\opt_has_pipe.first_q[0]_i_1__4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(0),
I1 => \out\(0),
O => O8
);
\opt_has_pipe.first_q[1]_i_1__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => first_q(1),
I1 => first_q(0),
I2 => \out\(0),
O => O1
);
\opt_has_pipe.first_q[2]_i_1__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => first_q(2),
I1 => \out\(0),
I2 => first_q(0),
I3 => first_q(1),
O => O2
);
\opt_has_pipe.first_q[3]_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => first_q(1),
I1 => first_q(0),
I2 => \out\(0),
I3 => first_q(2),
I4 => first_q(3),
O => O3
);
\opt_has_pipe.first_q[4]_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => first_q(4),
I1 => first_q(1),
I2 => first_q(0),
I3 => \out\(0),
I4 => first_q(2),
I5 => first_q(3),
O => O4
);
\opt_has_pipe.first_q[5]_i_1__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => first_q(5),
I1 => \n_0_opt_has_pipe.first_q[7]_i_2__0\,
I2 => first_q(4),
O => O5
);
\opt_has_pipe.first_q[6]_i_1__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => first_q(6),
I1 => first_q(4),
I2 => \n_0_opt_has_pipe.first_q[7]_i_2__0\,
I3 => first_q(5),
O => O6
);
\opt_has_pipe.first_q[7]_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => first_q(7),
I1 => first_q(5),
I2 => \n_0_opt_has_pipe.first_q[7]_i_2__0\,
I3 => first_q(4),
I4 => first_q(6),
O => O7
);
\opt_has_pipe.first_q[7]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => first_q(3),
I1 => first_q(2),
I2 => \out\(0),
I3 => first_q(0),
I4 => first_q(1),
O => \n_0_opt_has_pipe.first_q[7]_i_2__0\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I8,
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I7,
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I6,
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I5,
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I4,
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I3,
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I2,
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1,
Q => first_q(7),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized14_2\ is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
I1 : in STD_LOGIC;
aclk : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
I5 : in STD_LOGIC;
I6 : in STD_LOGIC;
I7 : in STD_LOGIC;
I8 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_2\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized14_2\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_2\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => m_axis_data_tdata(7)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => m_axis_data_tdata(6)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => m_axis_data_tdata(5)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => m_axis_data_tdata(4)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => m_axis_data_tdata(3)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => m_axis_data_tdata(2)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => m_axis_data_tdata(1)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => m_axis_data_tdata(0)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I8,
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I7,
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I6,
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I5,
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I4,
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I3,
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I2,
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1,
Q => first_q(7),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized14_3\ is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_3\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized14_3\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_3\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => m_axis_data_tdata(7)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => m_axis_data_tdata(6)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => m_axis_data_tdata(5)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => m_axis_data_tdata(4)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => m_axis_data_tdata(3)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => m_axis_data_tdata(2)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => m_axis_data_tdata(1)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => m_axis_data_tdata(0)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(1),
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(2),
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(3),
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(4),
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(5),
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(6),
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \out\(7),
Q => first_q(7),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized14_4\ is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
I1 : in STD_LOGIC;
aclk : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
I5 : in STD_LOGIC;
I6 : in STD_LOGIC;
I7 : in STD_LOGIC;
I8 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_4\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized14_4\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_4\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => m_axis_data_tdata(7)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => m_axis_data_tdata(6)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => m_axis_data_tdata(5)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => m_axis_data_tdata(4)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => m_axis_data_tdata(3)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => m_axis_data_tdata(2)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => m_axis_data_tdata(1)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => m_axis_data_tdata(0)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I8,
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I7,
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I6,
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I5,
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I4,
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I3,
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I2,
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1,
Q => first_q(7),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized14_6\ is
port (
O1 : out STD_LOGIC;
O2 : out STD_LOGIC;
O3 : out STD_LOGIC;
O4 : out STD_LOGIC;
O5 : out STD_LOGIC;
O6 : out STD_LOGIC;
O7 : out STD_LOGIC;
O8 : out STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_phase_tvalid : in STD_LOGIC;
I1 : in STD_LOGIC;
aclk : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
I5 : in STD_LOGIC;
I6 : in STD_LOGIC;
I7 : in STD_LOGIC;
invert_sin : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_6\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized14_6\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_6\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \n_0_opt_has_pipe.first_q[7]_i_2\ : STD_LOGIC;
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\opt_has_pipe.first_q[0]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(0),
I1 => \out\(0),
O => O8
);
\opt_has_pipe.first_q[1]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => first_q(1),
I1 => first_q(0),
I2 => \out\(0),
O => O1
);
\opt_has_pipe.first_q[2]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => first_q(2),
I1 => \out\(0),
I2 => first_q(0),
I3 => first_q(1),
O => O2
);
\opt_has_pipe.first_q[3]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => first_q(1),
I1 => first_q(0),
I2 => \out\(0),
I3 => first_q(2),
I4 => first_q(3),
O => O3
);
\opt_has_pipe.first_q[4]_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => first_q(4),
I1 => first_q(1),
I2 => first_q(0),
I3 => \out\(0),
I4 => first_q(2),
I5 => first_q(3),
O => O4
);
\opt_has_pipe.first_q[5]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => first_q(5),
I1 => \n_0_opt_has_pipe.first_q[7]_i_2\,
I2 => first_q(4),
O => O5
);
\opt_has_pipe.first_q[6]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => first_q(6),
I1 => first_q(4),
I2 => \n_0_opt_has_pipe.first_q[7]_i_2\,
I3 => first_q(5),
O => O6
);
\opt_has_pipe.first_q[7]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => first_q(7),
I1 => first_q(5),
I2 => \n_0_opt_has_pipe.first_q[7]_i_2\,
I3 => first_q(4),
I4 => first_q(6),
O => O7
);
\opt_has_pipe.first_q[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => first_q(3),
I1 => first_q(2),
I2 => \out\(0),
I3 => first_q(0),
I4 => first_q(1),
O => \n_0_opt_has_pipe.first_q[7]_i_2\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I7,
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I6,
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I5,
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I4,
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I3,
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I2,
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1,
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => invert_sin,
Q => first_q(7),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized16\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
I1 : in STD_LOGIC;
aclk : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
I5 : in STD_LOGIC;
I6 : in STD_LOGIC;
I7 : in STD_LOGIC;
I8 : in STD_LOGIC;
DOBDO : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized16\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized16\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized16\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[8]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(8),
O => \out\(8)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => \out\(7)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => \out\(6)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => \out\(5)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => \out\(4)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => \out\(3)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => \out\(2)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => \out\(1)
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => \out\(0)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => DOBDO(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I8,
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I7,
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I6,
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I5,
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I4,
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I3,
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I2,
Q => first_q(7),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1,
Q => first_q(8),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized16_5\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
I1 : in STD_LOGIC;
aclk : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
I5 : in STD_LOGIC;
I6 : in STD_LOGIC;
I7 : in STD_LOGIC;
I8 : in STD_LOGIC;
I9 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized16_5\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized16_5\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized16_5\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[8]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(8),
O => \out\(8)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => \out\(7)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => \out\(6)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => \out\(5)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => \out\(4)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => \out\(3)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => \out\(2)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => \out\(1)
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => \out\(0)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I9(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I8,
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I7,
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I6,
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I5,
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I4,
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I3,
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I2,
Q => first_q(7),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1,
Q => first_q(8),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized2\ is
port (
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
mutant_x_op : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized2\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized2\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized2\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of first_q : signal is "true";
signal \n_0_opt_has_pipe.first_q[0]_i_1\ : STD_LOGIC;
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\opt_has_pipe.first_q[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => mutant_x_op(1),
I1 => mutant_x_op(0),
I2 => mutant_x_op(2),
O => \n_0_opt_has_pipe.first_q[0]_i_1\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => \n_0_opt_has_pipe.first_q[0]_i_1\,
Q => first_q,
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized8\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
I1 : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
temp : in STD_LOGIC_VECTOR ( 16 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized8\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized8\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized8\ is
signal \<const0>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 16 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[10]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[11]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[12]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[13]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[14]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[15]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[16]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[8]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[9]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(15),
O => \out\(15)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(14),
O => \out\(14)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => \out\(5)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => \out\(4)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => \out\(3)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => \out\(2)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => \out\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => \out\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(13),
O => \out\(13)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(12),
O => \out\(12)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(11),
O => \out\(11)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(10),
O => \out\(10)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(9),
O => \out\(9)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(8),
O => \out\(8)
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => \out\(7)
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => \out\(6)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(0),
O => I1(0)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(10),
O => I1(10)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(11),
O => I1(11)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(12),
O => I1(12)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(13),
O => I1(13)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(1),
O => I1(1)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(2),
O => I1(2)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(3),
O => I1(3)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(4),
O => I1(4)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(5),
O => I1(5)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(6),
O => I1(6)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(7),
O => I1(7)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(8),
O => I1(8)
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => first_q(14),
I1 => first_q(9),
O => I1(9)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(0),
I1 => first_q(14),
O => D(0)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(10),
I1 => first_q(14),
O => D(10)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(11),
I1 => first_q(14),
O => D(11)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(12),
I1 => first_q(14),
O => D(12)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(13),
I1 => first_q(14),
O => D(13)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(1),
I1 => first_q(14),
O => D(1)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(2),
I1 => first_q(14),
O => D(2)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(3),
I1 => first_q(14),
O => D(3)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(4),
I1 => first_q(14),
O => D(4)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(5),
I1 => first_q(14),
O => D(5)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(6),
I1 => first_q(14),
O => D(6)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(7),
I1 => first_q(14),
O => D(7)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(8),
I1 => first_q(14),
O => D(8)
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => first_q(9),
I1 => first_q(14),
O => D(9)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(10),
Q => first_q(10),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(11),
Q => first_q(11),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(12),
Q => first_q(12),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(13),
Q => first_q(13),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(14),
Q => first_q(14),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(15),
Q => first_q(15),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(16),
Q => first_q(16),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(1),
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(2),
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(3),
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(4),
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(5),
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(6),
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(7),
Q => first_q(7),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(8),
Q => first_q(8),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => temp(9),
Q => first_q(9),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsaccum is
port (
L : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
I1 : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
reg_s_phase_fifo_din : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
end ddsaccum;
architecture STRUCTURE of ddsaccum is
signal \^l\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal acc_phase_shaped : STD_LOGIC_VECTOR ( 13 downto 0 );
signal temp : STD_LOGIC_VECTOR ( 16 downto 0 );
begin
L(1 downto 0) <= \^l\(1 downto 0);
\i_fabric.i_common.i_phase_acc\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized8\
port map (
D(13 downto 0) => D(13 downto 0),
I1(13 downto 0) => I1(13 downto 0),
aclk => aclk,
\out\(15 downto 14) => \^l\(1 downto 0),
\out\(13 downto 0) => acc_phase_shaped(13 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid,
temp(16 downto 0) => temp(16 downto 0)
);
\i_fabric.i_one_channel.i_accum\: entity work.\ddspipe_add__parameterized0\
port map (
L(15 downto 14) => \^l\(1 downto 0),
L(13 downto 0) => acc_phase_shaped(13 downto 0),
reg_s_phase_fifo_din(15 downto 0) => reg_s_phase_fifo_din(15 downto 0),
s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid,
temp(16 downto 0) => temp(16 downto 0)
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsdds_compiler_v6_0_rdy is
port (
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC
);
end ddsdds_compiler_v6_0_rdy;
architecture STRUCTURE of ddsdds_compiler_v6_0_rdy is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal mutant_x_op : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \n_0_mutant_x_op[0]_i_1\ : STD_LOGIC;
signal \n_0_mutant_x_op[1]_i_1\ : STD_LOGIC;
signal \n_0_mutant_x_op[2]_i_1\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \mutant_x_op[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \mutant_x_op[2]_i_1\ : label is "soft_lutpair12";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\i_single_channel.i_non_trivial_lat.i_rdy\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized2\
port map (
aclk => aclk,
mutant_x_op(2 downto 0) => mutant_x_op(2 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\mutant_x_op[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5A58"
)
port map (
I0 => s_axis_phase_tvalid,
I1 => mutant_x_op(2),
I2 => mutant_x_op(0),
I3 => mutant_x_op(1),
O => \n_0_mutant_x_op[0]_i_1\
);
\mutant_x_op[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F508"
)
port map (
I0 => s_axis_phase_tvalid,
I1 => mutant_x_op(2),
I2 => mutant_x_op(0),
I3 => mutant_x_op(1),
O => \n_0_mutant_x_op[1]_i_1\
);
\mutant_x_op[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCC4"
)
port map (
I0 => s_axis_phase_tvalid,
I1 => mutant_x_op(2),
I2 => mutant_x_op(0),
I3 => mutant_x_op(1),
O => \n_0_mutant_x_op[2]_i_1\
);
\mutant_x_op_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \n_0_mutant_x_op[0]_i_1\,
Q => mutant_x_op(0),
R => \<const0>\
);
\mutant_x_op_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => \<const1>\,
D => \n_0_mutant_x_op[1]_i_1\,
Q => mutant_x_op(1),
R => \<const0>\
);
\mutant_x_op_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => \<const1>\,
D => \n_0_mutant_x_op[2]_i_1\,
Q => mutant_x_op(2),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddssin_cos__parameterized0\ is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
L : in STD_LOGIC_VECTOR ( 1 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddssin_cos__parameterized0\ : entity is "sin_cos";
end \ddssin_cos__parameterized0\;
architecture STRUCTURE of \ddssin_cos__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal cos_addr : STD_LOGIC_VECTOR ( 13 downto 0 );
signal cos_ls1 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\ : STD_LOGIC_VECTOR ( 14 downto 0 );
signal \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal invert_sin : STD_LOGIC;
signal mod_cos_addr : STD_LOGIC_VECTOR ( 13 downto 0 );
signal mod_sin_addr : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \n_0_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_0_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_10_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_11_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_12_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_13_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_14_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_15_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_16_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_17_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_18_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_19_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_1_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_1_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_1_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_20_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_21_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_22_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_23_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_24_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_25_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_26_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_27_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_28_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_29_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_2_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_2_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_2_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_30_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_31_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_3_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_3_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_3_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_4_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_4_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_4_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_5_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_5_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_5_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_6_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_6_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_6_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_7_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_7_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC;
signal \n_7_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC;
signal \n_8_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal \n_9_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 6 downto 0 );
signal sin_addr : STD_LOGIC_VECTOR ( 13 downto 0 );
signal sin_ls1 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is "";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is 16383;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is 1;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is 2;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is 3;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is 4;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is 5;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is 6;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is 7;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is 8;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is 9;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is 10;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is 11;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is 12;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is 13;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is "";
attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is 0;
attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is 16383;
attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is 14;
attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is 15;
attribute use_sync_reset : string;
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[0]\ : label is "no";
attribute use_sync_set : string;
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[0]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[10]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[10]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[11]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[11]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[12]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[12]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[13]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[13]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[1]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[1]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[2]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[2]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[3]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[3]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[4]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[4]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[5]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[5]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[6]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[6]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[7]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[7]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[8]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[8]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[9]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[9]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[0]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[0]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[10]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[10]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[11]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[11]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[12]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[12]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[13]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[13]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[1]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[1]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[2]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[2]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[3]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[3]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[4]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[4]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[5]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[5]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[6]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[6]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[7]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[7]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[8]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[8]\ : label is "no";
attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[9]\ : label is "no";
attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[9]\ : label is "no";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\i_rtl.i_quarter_table.i_addr_reg_c\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized12\
port map (
L(1 downto 0) => L(1 downto 0),
O1 => \n_1_i_rtl.i_quarter_table.i_addr_reg_c\,
O10 => \n_10_i_rtl.i_quarter_table.i_addr_reg_c\,
O11 => \n_11_i_rtl.i_quarter_table.i_addr_reg_c\,
O12 => \n_12_i_rtl.i_quarter_table.i_addr_reg_c\,
O13 => \n_13_i_rtl.i_quarter_table.i_addr_reg_c\,
O14 => \n_14_i_rtl.i_quarter_table.i_addr_reg_c\,
O15 => \n_15_i_rtl.i_quarter_table.i_addr_reg_c\,
O16 => \n_16_i_rtl.i_quarter_table.i_addr_reg_c\,
O17 => \n_17_i_rtl.i_quarter_table.i_addr_reg_c\,
O18 => \n_18_i_rtl.i_quarter_table.i_addr_reg_c\,
O19 => \n_19_i_rtl.i_quarter_table.i_addr_reg_c\,
O2 => \n_2_i_rtl.i_quarter_table.i_addr_reg_c\,
O20 => \n_20_i_rtl.i_quarter_table.i_addr_reg_c\,
O21 => \n_21_i_rtl.i_quarter_table.i_addr_reg_c\,
O22 => \n_22_i_rtl.i_quarter_table.i_addr_reg_c\,
O23 => \n_23_i_rtl.i_quarter_table.i_addr_reg_c\,
O24 => \n_24_i_rtl.i_quarter_table.i_addr_reg_c\,
O25 => \n_25_i_rtl.i_quarter_table.i_addr_reg_c\,
O26 => \n_26_i_rtl.i_quarter_table.i_addr_reg_c\,
O27 => \n_27_i_rtl.i_quarter_table.i_addr_reg_c\,
O28 => \n_28_i_rtl.i_quarter_table.i_addr_reg_c\,
O29 => \n_29_i_rtl.i_quarter_table.i_addr_reg_c\,
O3 => \n_3_i_rtl.i_quarter_table.i_addr_reg_c\,
O30 => \n_30_i_rtl.i_quarter_table.i_addr_reg_c\,
O31 => \n_31_i_rtl.i_quarter_table.i_addr_reg_c\,
O4 => \n_4_i_rtl.i_quarter_table.i_addr_reg_c\,
O5 => \n_5_i_rtl.i_quarter_table.i_addr_reg_c\,
O6 => \n_6_i_rtl.i_quarter_table.i_addr_reg_c\,
O7 => \n_7_i_rtl.i_quarter_table.i_addr_reg_c\,
O8 => \n_8_i_rtl.i_quarter_table.i_addr_reg_c\,
O9 => \n_9_i_rtl.i_quarter_table.i_addr_reg_c\,
aclk => aclk,
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(14 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(14 downto 0),
invert_sin => invert_sin,
\out\(14 downto 8) => p_0_in(6 downto 0),
\out\(7 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(7 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"5B1BC6C5B1BC6C5B1BC6C5B1BC6C5B1BC6C5B1BC6C6B1B06C6B1B06C6B1B06C6",
INIT_01 => X"F1B16C6F1B16C6F1B16C6C1B1AC6C1B1AC6C1B1AC6C1B1AC6C1B1AC6C1B1BC6C",
INIT_02 => X"1B1AC6C5B1BC6C5B1BC6C5B1BC6C5B1B06C6B1B06C6B1B06C6B1B06C6F1B16C6",
INIT_03 => X"B1AC6C5B1BC6C5B1BC6C6B1B06C6B1B06C6F1B16C6F1B16C6F1B1AC6C1B1AC6C",
INIT_04 => X"16C6F1B16C6C1B1AC6C5B1BC6C5B1B06C6B1B06C6B1B16C6F1B16C6C1B1AC6C1",
INIT_05 => X"6F1B1AC6C1B1BC6C5B1B06C6B1B16C6F1B16C6C1B1AC6C5B1BC6C6B1B06C6B1B",
INIT_06 => X"BC6C6B1B06C6F1B1AC6C1B1BC6C5B1B06C6F1B16C6C1B1AC6C5B1B06C6B1B16C",
INIT_07 => X"B1AC6C5B1B06C6F1B1AC6C1B1BC6C6B1B16C6C1B1AC6C5B1B06C6F1B16C6C1B1",
INIT_08 => X"B16C6C5B1B06C6F1B1AC6C5B1B06C6F1B1AC6C5B1B06C6F1B1AC6C5B1B06C6F1",
INIT_09 => X"6C6C1B1BC6C6F1B1AC6C5B1B16C6C1B1BC6C6F1B1AC6C5B1B16C6C1B1BC6C6B1",
INIT_0A => X"1B16C6C5B1B16C6C1B1B06C6C1B1B06C6F1B1BC6C6B1B1AC6C6B1B16C6C5B1B0",
INIT_0B => X"B1B06C6C1B1B16C6C5B1B16C6C5B1B16C6C5B1B16C6C5B1B16C6C5B1B16C6C5B",
INIT_0C => X"06C6C5B1B1AC6C6F1B1BC6C6C1B1B16C6C5B1B1AC6C6B1B1BC6C6F1B1B06C6C1",
INIT_0D => X"1B1BC6C6C1B1B1AC6C6F1B1B06C6C5B1B1BC6C6C1B1B16C6C6B1B1BC6C6C1B1B",
INIT_0E => X"1B06C6C6F1B1B16C6C6F1B1B16C6C6F1B1B16C6C6F1B1B06C6C6B1B1B06C6C5B",
INIT_0F => X"C6B1B1B16C6C6C1B1B1BC6C6C6B1B1B16C6C6C1B1B1BC6C6C5B1B1B06C6C6B1B",
INIT_10 => X"6F1B1B1BC6C6C6C1B1B1B06C6C6C1B1B1B06C6C6C1B1B1B06C6C6F1B1B1BC6C6",
INIT_11 => X"AC6C6C6C1B1B1B1AC6C6C6C1B1B1B1AC6C6C6F1B1B1B06C6C6C5B1B1B1AC6C6C",
INIT_12 => X"6C6C6C6F1B1B1B1BC6C6C6C6F1B1B1B1BC6C6C6C6B1B1B1B16C6C6C6C1B1B1B1",
INIT_13 => X"1B1B16C6C6C6C6C5B1B1B1B1B06C6C6C6C6B1B1B1B1B06C6C6C6C5B1B1B1B1AC",
INIT_14 => X"6C6C6C6C6C6C1B1B1B1B1B1B06C6C6C6C6C6B1B1B1B1B1B06C6C6C6C6C5B1B1B",
INIT_15 => X"B16C6C6C6C6C6C6C6C6B1B1B1B1B1B1B1B06C6C6C6C6C6C6C5B1B1B1B1B1B1BC",
INIT_16 => X"1B1B1B1B1B1B1B1B1B1B1B1B1AC6C6C6C6C6C6C6C6C6C6C1B1B1B1B1B1B1B1B1",
INIT_17 => X"B1B1B1B1B1B1B1B1B1B1B1B1B1B06C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6F",
INIT_18 => X"B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1",
INIT_19 => X"6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6CB1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1",
INIT_1A => X"B1B1B1B1B1B1B1B1C6C6C6C6C6C6C6C6C6C6DB1B1B1B1B1B1B1B1B1B1B1B1C6C",
INIT_1B => X"6C6C6DB1B1B1B1B1B1C6C6C6C6C6C6C71B1B1B1B1B1B1B6C6C6C6C6C6C6C6CB1",
INIT_1C => X"C6C6C6DB1B1B1B1B6C6C6C6C6DB1B1B1B1B1C6C6C6C6C6DB1B1B1B1B1B6C6C6C",
INIT_1D => X"C6C6CB1B1B1B2C6C6C6CB1B1B1B1C6C6C6C61B1B1B1B6C6C6C6C71B1B1B1B2C6",
INIT_1E => X"6C71B1B186C6C6CB1B1B1C6C6C6DB1B1B1C6C6C6CB1B1B186C6C6C71B1B1B2C6",
INIT_1F => X"B1B1B6C6C6DB1B186C6C61B1B186C6C61B1B186C6C61B1B1B6C6C6DB1B1B2C6C",
INIT_20 => X"1B6C6C71B1B6C6C71B1B6C6C61B1B2C6C6DB1B1C6C6CB1B1B6C6C61B1B1C6C6C",
INIT_21 => X"6C6DB1B2C6C71B186C6DB1B2C6C71B186C6CB1B1C6C6DB1B2C6C61B1B6C6C71B",
INIT_22 => X"CB1B2C6CB1B2C6CB1B2C6CB1B1C6C71B1C6C61B186C6DB1B6C6CB1B2C6C71B18",
INIT_23 => X"1B2C6DB186C61B1C6CB1B2C6DB1B6C61B186C71B1C6C71B1C6CB1B2C6CB1B2C6",
INIT_24 => X"B6C71B2C6DB186CB1B6C61B1C6CB1B6C71B2C6DB186C71B1C6CB1B6C61B1C6CB",
INIT_25 => X"C6DB186CB186CB186C71B6C71B2C61B2C6DB1C6CB186C71B6C61B2C6DB1C6CB1",
INIT_26 => X"6C7186CB186CB186DB1C6DB1C6DB1C6DB1C6DB1C6DB1C6DB1C6DB1C6DB1C6DB1",
INIT_27 => X"2C71B6CB1C6DB2C61B6C7186CB1C6DB2C61B6C7186CB186DB1C61B2C61B2C71B",
INIT_28 => X"B2C7186DB2C71B6CB1C61B6CB1C61B2C7186DB2C61B6CB1C6DB2C71B6CB1C6DB",
INIT_29 => X"6DB6CB1C6186DB2C7186DB6CB1C61B6CB1C6186DB2C7186DB2C7186DB2C7186D",
INIT_2A => X"B1C71861B6DB2CB1C6186DB6CB2C71861B6CB2C71C61B6DB2C71861B6CB2C718",
INIT_2B => X"1861B6DB6DB2CB2C71C7186186DB6CB2CB1C71C6186DB6CB2CB1C71861B6DB2C",
INIT_2C => X"DB6DB6DB6DB2CB2CB2CB2CB1C71C71C71C61861861B6DB6DB6CB2CB2C71C71C6",
INIT_2D => X"2CB2DB6DB6DB6DB6DB6DB6DB6D861861861861861861861861861B6DB6DB6DB6",
INIT_2E => X"CB2CB2DB6DB61861871C71C72CB2CB6DB6DB6D861861861C71C71C72CB2CB2CB",
INIT_2F => X"C71CB2DB6D861C71CB2DB6D861871C72CB6DB61861C71C72CB2DB6D861861C71",
INIT_30 => X"D871CB2DB61871CB2D861C72CB6D861C72CB6D861871CB2DB61871C72CB6D861",
INIT_31 => X"B6D871CB6D871CB6D861CB2D861CB2DB61C72DB61872CB6D871CB2DB61C72CB6",
INIT_32 => X"61CB61872DB61CB6D872CB61C72D861CB6D872CB61872DB61C72D861CB2D861C",
INIT_33 => X"72D872D871CB61CB61872D872DB61CB61872D872CB61CB6D872DB61CB61872D8",
INIT_34 => X"CB61CB61CB61CB61CB61CB61CB61CB61CB2D872D872D872D871CB61CB61CB618",
INIT_35 => X"721CB61CB61CB72D872D872D872D8761CB61CB61CB61CB61CB61CB61CB61CB61",
INIT_36 => X"62D872DCB61C872D8761CB61D872D8721CB61C872D872D8B61CB61C872D872D8",
INIT_37 => X"721CB72D8B61D8721CB62D8761CB72D8B61C872D8B61C872D8B61CB72D8761CB",
INIT_38 => X"CB72DCB72D8B62D8B62D8761D8721C8721CB72D8B62D8761D8721CB72D8B61D8",
INIT_39 => X"62D8B62DCB721C8721D8761D8762D8B62D8B62DCB72DCB72DCB72DCB72DCB72D",
INIT_3A => X"1C8762DC8721D8B62DC8761D8B72DC8761D8B62DC8721D8762D8B72DC8721D87",
INIT_3B => X"D8B762DC8762DC8762DC8762D8B721D8B721D8B721D8B62DC8762DC8721D8B72",
INIT_3C => X"DD8B721DC87621D8B722DC8762DD8B721D8B762DC8762DC8B721D8B721D8B721",
INIT_3D => X"22DC8B722DD8B762DD8B762DD8B762DD8B762DD8B722DC8B721DC87721D88762",
INIT_3E => X"87722DD887722DD887722DC8B7621DC8B722DD887721DC8B762DD887621DC877",
INIT_3F => X"21DC887722DDC8B7722DD88B7621DD887722DDC8B7621DC8B7722DD887722DD8",
INIT_40 => X"C8877622DDC8877622DDC8877622DDC8B77221DD8877622DD88B7722DDC8B772",
INIT_41 => X"B776221DDC88B77622DDD888776221DDC88777221DD888776221DD88B77222DD",
INIT_42 => X"776222DDDC8887776222DDD888B777222DDDC88B777222DDD888B776221DDC88",
INIT_43 => X"7762222DDDD8888B77772222DDDD888877772222DDDD888877762221DDD888B7",
INIT_44 => X"7777622222DDDDDD88888B77777222221DDDDC8888B7777622221DDDD8888B77",
INIT_45 => X"88777777777222222221DDDDDDDC888888877777776222222DDDDDDD88888877",
INIT_46 => X"888888888888888888777777777777777222222222222DDDDDDDDDDD88888888",
INIT_47 => X"DDD2222222222222222222222221DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDC",
INIT_48 => X"77777777777748888888888888888889DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD",
INIT_49 => X"8888DDDDDDDD222222223777777774888888888DDDDDDDDDDD22222222222277",
INIT_4A => X"E2222377777888889DDDDD2222227777778888889DDDDDD22222237777774888",
INIT_4B => X"7748889DDDE222377748889DDDD22223777788889DDDD222237777488889DDDD",
INIT_4C => X"DDDE223774888DDD22237778889DDE2227774888DDDD22237778888DDDE22237",
INIT_4D => X"2377889DDE22774889DD222774889DDE22777888DDD222777888DDD222777888",
INIT_4E => X"889DE2277889DE2277489DD2237788DDE2277488DDE2277488DDE2277488DDE2",
INIT_4F => X"D227788DD227788DD227788DDE237489DE237788DD2237489DE2277889DE2277",
INIT_50 => X"3788DE23788DE23748DD237489D227789DE23748DD227789DE237489DE27788D",
INIT_51 => X"89D22748DE27489D23789DE27489D23788DE27789D22748DD23748DE23788DE2",
INIT_52 => X"DE2749D23789D23789E2748DE2748DE2748DE2748DE2748DE2748DE23789D237",
INIT_53 => X"2378DE3789E2749D2348DE3789E2749D2378DE2749D2378DE2749D23789E2748",
INIT_54 => X"378DE348D2349D2749D2749E2789E2789E2789E2789E2789D2749D2749D2348D",
INIT_55 => X"349E378D2749E378D2749E378D2349E278DE348D2749E278DE348D2749E2789E",
INIT_56 => X"789E349E349E349D278D278D2349E349E278D278DE349E378D278DE349E278D2",
INIT_57 => X"349E34D278D278D278D278D278D278D278D278D278D278D278D278D278D278D2",
INIT_58 => X"278E349E38D279E349E78D278E349E34D278D279E349E349278D278D249E349E",
INIT_59 => X"D249E78D349278E349279E34D279E34D279E34D279E349278E349E78D249E34D",
INIT_5A => X"4D249E79E38E34D249E79E38D349249E78E34D249E78E34D249E78D349279E38",
INIT_5B => X"E79E79E79E78E38E38E34D34D34D249249E79E78E38E34D349249279E78E38D3",
INIT_5C => X"4D34D34D38E38E38E79E79E79E79E79249249249249249249249249249249E79",
INIT_5D => X"934D38E79E4924D34E38E7924924D34E38E79E4924934D34E38E39E79E492492",
INIT_5E => X"E7924D38E7934E39E4934E39E4934E39E4924D38E7924D34E39E4934D38E79E4",
INIT_5F => X"E4938E4938E4934E7934E3924E39E4D38E4938E7924E39E4D38E7934E39E4938",
INIT_60 => X"E7938E4939E4E3934E7938E4D39E4E3924E7934E7934E4938E4938E4938E4938",
INIT_61 => X"924E4D3934E4E3938E4E3938E4E3938E4D3934E4D3924E4939E4E3934E493924",
INIT_62 => X"393924E4E793938E4E4D3939E4E4D3939E4E4D3938E4E493934E4E3939E4E493",
INIT_63 => X"9393924E4E4E4939393924E4E4E79393934E4E4E79393924E4E49393934E4E49",
INIT_64 => X"E4E4E4E4E4E4E4D39393939393939E4E4E4E4E4E493939393938E4E4E4E4E393",
INIT_65 => X"393939393939393939393939393939393939393939393939393939393924E4E4",
INIT_66 => X"39393939394E4E4E4E4E4E93939393939393A4E4E4E4E4E4E4E4E4E4E9393939",
INIT_67 => X"E4E4E939393E4E4E4F939393E4E4E4E93939394E4E4E4E93939393A4E4E4E4E5",
INIT_68 => X"4E9393E4E4F9390E4E439390E4E439390E4E4F9393E4E4E539390E4E4E939390",
INIT_69 => X"E4E9394E4393A4E5393E4E9390E4E9390E4E9390E4E9393E4E5393A4E439394E",
INIT_6A => X"390E4390E4F93E4F93E4E93A4E9394E5390E4F93E4E9394E5390E4F93A4E5390",
INIT_6B => X"394E93A4F90E4394E93A4F93E4390E5394E93A4E93E4F93E4F93E4390E4390E4",
INIT_6C => X"E93E43A4F90E53E4394E93E53A4F90E53A4F90E53A4F90E53A4F90E53A4F93E4",
INIT_6D => X"93E53E53A43A4394F94E90E93E53A43A4F94E90E53E53A4394E90E53E43A4F90",
INIT_6E => X"F94F94F94F943A43A43A43A43A43A43A43A43A43A4394F94F94F94F90E90E90E",
INIT_6F => X"3E90F94FA43E53E90E94F943A43E53E90E90F94F943A43A53E53E50E90E90E94",
INIT_70 => X"0E943A53E94FA53E90F943E50E94FA53E90F943A53E90F943A53E90E94FA43E5",
INIT_71 => X"FA50E943E94FA50F943E94FA50E943E50FA43E94FA53E943A50E943A50E943A5",
INIT_72 => X"943E943E943E943E943A50FA50FA50FA50F943E943E943A50FA50F943E943E50",
INIT_73 => X"FA50FE943E940FA50FA50FE943E943E950FA50FA50FA50FA543E943E943E943E",
INIT_74 => X"3EA50FE940FA543EA50FE943FA503E940FA503E940FA503E943FA50FA943E950",
INIT_75 => X"FE9503EA503EA543FA543FA543FA543FA543FA503EA503E950FE950FA943FA54",
INIT_76 => X"A540FEA540FA9503FA940FEA503FA940FEA503FA940FE9503EA543FA940FA950",
INIT_77 => X"0FFA9503FAA540FEA5403FA9503FA9503FA9503FA9503FA9503FA9503FA9503F",
INIT_78 => X"540FFAA5403FAA5503FEA5503FEA5503FEA5503FEA5403FA9540FEA9503FEA54",
INIT_79 => X"5403FFAA5500FFEA95403FEA95403FEA95403FEA95403FEA9500FFAA5503FEA9",
INIT_7A => X"00FFEAA955003FFAA95400FFEAA55403FFAA95500FFEA95500FFEA95500FFAA9",
INIT_7B => X"AAA9554003FFFAAA555000FFFAAA554003FFEAA955000FFEAA955003FFEAA554",
INIT_7C => X"03FFFEAAA955550000FFFEAAA95554000FFFEAAA95550003FFFAAA5554000FFF",
INIT_7D => X"0000FFFFFFAAAAAA55555400000FFFFFEAAAA95555400003FFFFAAAA95555000",
INIT_7E => X"3FFFFFFFFFFFAAAAAAAAAA955555555400000000FFFFFFFEAAAAAAA555555400",
INIT_7F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555500000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(1 downto 0),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1 downto 0),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"394E53A4E93A4F93E4F90E4390E5394E53A4E93A4F93E4390E4394E5394E93A4",
INIT_01 => X"3E4390E4394E5394E93A4F93E4F90E4390E5394E53A4E93A4F93E4F90E4390E5",
INIT_02 => X"4E93A4F93E4F90E4390E5394E53A4E93E4F93E4390E4394E5394E93A4E93E4F9",
INIT_03 => X"4390E5394E53A4E93A4F93E4390E4394E5394E93A4E93E4F93E4390E5394E53A",
INIT_04 => X"93A4E93E4F90E4390E5394E53A4E93E4F93E4390E4394E5394E93A4F93E4F90E",
INIT_05 => X"93E4390E5394E53A4E93E4F93E4390E4394E53A4E93A4F93E4F90E4394E5394E",
INIT_06 => X"90E5394E93A4E93E4F90E4390E5394E93A4E93E4F90E4390E5394E93A4E93E4F",
INIT_07 => X"94E53A4E93E4F93E4390E5394E53A4E93E4F90E4390E5394E93A4E93E4F90E43",
INIT_08 => X"94E53A4E93E4F93E4390E5394E93A4E93E4F90E4394E5394E93A4F93E4390E43",
INIT_09 => X"90E5394E53A4E93E4F90E4394E53A4E93A4F93E4390E5394E93A4F93E4F90E43",
INIT_0A => X"93E4F90E4394E53A4E93E4F90E4394E5394E93A4F93E4390E5394E93A4F93E43",
INIT_0B => X"4394E53A4E93E4F90E4394E53A4E93E4F90E4394E53A4E93E4F90E4394E53A4E",
INIT_0C => X"4E53A4E93E4F90E4394E53A4F93E4390E5394E93A4F93E4390E5394E93E4F90E",
INIT_0D => X"394E53A4F93E4390E5394E93E4F90E4394E53A4F93E4390E5394E93A4F90E439",
INIT_0E => X"E4390E5394E93E4F90E4394E93A4F93E4394E53A4E93E4390E5394E93E4F90E4",
INIT_0F => X"5394E93E4F90E5394E93A4F90E4394E93A4F90E4394E53A4F93E4394E53A4E93",
INIT_10 => X"394E93E4F90E53A4E93E4390E53A4E93E4390E53A4E93E4390E5394E93E4F90E",
INIT_11 => X"90E53A4F93E4394E53A4F90E4394E93A4F90E4394E93E4F90E5394E93E4F90E5",
INIT_12 => X"3A4F90E4394E93E4F90E53A4E93E4394E53A4F90E4394E93E4F90E53A4E93E43",
INIT_13 => X"93E4390E53A4F90E4394E93E4390E53A4F93E4394E93E4F90E53A4E93E4394E5",
INIT_14 => X"E53A4F90E53A4E93E4394E93E4F90E53A4F93E4394E93E4390E53A4F90E4394E",
INIT_15 => X"3E4F90E53A4F90E53A4E93E4394E93E4394E53A4F90E53A4F93E4394E93E4390",
INIT_16 => X"4E93E4394E93E4394E93E4394E53A4F90E53A4F90E53A4F93E4394E93E4394E9",
INIT_17 => X"4394E93E4394E93E4394E93E4394E53A4F90E53A4F90E53A4F90E53A4F90E539",
INIT_18 => X"4394E93E4394E93E4394E93E4394E93E4394E93E4394E93E4394E93E4394E93E",
INIT_19 => X"4F90E53A4F90E53A4F90E53A4F90E53A4394E93E4394E93E4394E93E4394E93E",
INIT_1A => X"3E4394E93E4394E90E53A4F90E53A4F90E53A4394E93E4394E93E4394E93E53A",
INIT_1B => X"E53A4F94E93E4394E90E53A4F90E53A4394E93E4394E93E53A4F90E53A4F90E9",
INIT_1C => X"53A4F90E93E4394E90E53A4F90E93E4394E90E53A4F90E53E4394E93E43A4F90",
INIT_1D => X"F90E53E4394E90E53A4F94E93E43A4F90E53E4394E93E53A4F90E93E4394E90E",
INIT_1E => X"4F94E93E53A4F90E93E43A4F90E53E4394F90E53A4394E90E53A4F94E93E43A4",
INIT_1F => X"94E93E53A4F94E90E53A4394E90E53A4394E90E53A4394E93E53A4F94E93E53A",
INIT_20 => X"E43A4F94E93E53A4394E90E53E4394F90E53E43A4F90E93E43A4F94E93E53A4F",
INIT_21 => X"E53A4394F90E93E53A4F94E90E53E43A4F90E93E53A4F94E90E53E4394F90E93",
INIT_22 => X"A4394F90E93E53A4394F90E93E53A4394F90E93E53A4F94E90E53E43A4F94E90",
INIT_23 => X"93E53A43A4F94E90E53E43A4F94E90E93E53A4394F90E93E53A4394F90E93E53",
INIT_24 => X"3E53E43A4F94F90E93E53E43A4F94E90E93E53A43A4F94E90E53E43A4394F90E",
INIT_25 => X"A4F94F90E90E53E53A4394F94E90E93E53A43A4F94F90E93E53E43A4F94F90E9",
INIT_26 => X"3A43A4F94F90E90E53E53A43A4F94F90E90E53E53A43A4F94F90E90E53E53A43",
INIT_27 => X"4F94E90E90E53E53E43A43A4F94F90E90E93E53E53A43A4F94F94E90E93E53E4",
INIT_28 => X"43A43A4F94F94E90E90E93E53E53E43A43A4F94F94E90E90E53E53E43A43A4F9",
INIT_29 => X"4F94F94F94F90E90E90E53E53E53E43A43A43A4F94F94F90E90E90E53E53E53A",
INIT_2A => X"3E53E53E43A43A43A43A4F94F94F94F94E90E90E90E93E53E53E53E43A43A43A",
INIT_2B => X"E53E43A43A43A43A43A43A43A4F94F94F94F94F94F90E90E90E90E90E93E53E5",
INIT_2C => X"0E90E90E90E90E90E90E90E90E90E90E90E90E90E93E53E53E53E53E53E53E53",
INIT_2D => X"90E90E90E90E90E90E90E90E90F94F94F94F94F94F94F94F94F94E90E90E90E9",
INIT_2E => X"A43A43A43A43E53E53E53E53E53E53E53E53E50E90E90E90E90E90E90E90E90E",
INIT_2F => X"A43A43A43A53E53E53E53E50E90E90E90E90E94F94F94F94F94F94FA43A43A43",
INIT_30 => X"50E90E90E94F94F94FA43A43A43A53E53E53E50E90E90E90E94F94F94F94FA43",
INIT_31 => X"3E50E90E90F94F94FA43A43A53E53E53E90E90E94F94F94FA43A43A43E53E53E",
INIT_32 => X"94F943A43A43E53E50E90E94F94FA43A43A53E53E90E90E94F94FA43A43A53E5",
INIT_33 => X"E90F94FA43A43E53E90E90F94F943A43E53E50E90E94F94FA43A43E53E90E90F",
INIT_34 => X"F943A43E53E90E94F943A43E53E90E94F94FA43A53E50E90F94F943A43E53E90",
INIT_35 => X"E94F943A43E53E90F94FA43A53E50E94F943A43E53E90E94F943A43E53E90E94",
INIT_36 => X"94FA43A53E90F94FA43E53E90F94FA43E53E90F94FA43A53E90E94FA43A53E50",
INIT_37 => X"3E90E94FA43E50E94F943A53E90E94FA43E50E90F943A53E50E94F943A53E90E",
INIT_38 => X"53E90F943A53E90F943A53E90F943A53E90E94FA43E50E94FA43E53E90F943A5",
INIT_39 => X"94FA43E50E943A53E90F943A53E90F943A53E90F943A53E90F943A53E90F943A",
INIT_3A => X"90F943A50E94FA43E50F943A53E90FA43E50E94FA53E90F943A53E90FA43E50E",
INIT_3B => X"0F943E50F943A50E94FA53E90F943E50E943A53E94FA43E50F943A50E94FA43E",
INIT_3C => X"A50E943A50E943A53E94FA53E90FA43E90F943E50F943A50E943A53E94FA43E9",
INIT_3D => X"3E50F943E50F943E50F943E50F943E50F943E50F943E50F943E50F943E50F943",
INIT_3E => X"0E943A50F943E50FA43E90FA43E94FA53E94FA50E943A50E943A50F943E50F94",
INIT_3F => X"3E50FA43E90FA53E943A50F943E90FA53E94FA50E943E50F943E90FA53E94FA5",
INIT_40 => X"A50E943E50FA53E943A50FA43E94FA50E943E90FA53E943A50F943E90FA53E94",
INIT_41 => X"3E943E90FA50E943E90FA50F943E94FA50F943E94FA50F943E94FA50E943E90F",
INIT_42 => X"43E943A50FA50E943E94FA50FA43E943E50FA50E943E94FA50FA43E943E50FA5",
INIT_43 => X"43E943E50FA50FA43E943E94FA50FA50E943E943A50FA50F943E943E50FA50E9",
INIT_44 => X"3E943E943E50FA50FA50F943E943E943E50FA50FA53E943E943E90FA50FA53E9",
INIT_45 => X"A53E943E943E943E943E50FA50FA50FA50F943E943E943E94FA50FA50FA50F94",
INIT_46 => X"FA50FA50FA50FA50FA43E943E943E943E943E943E943E50FA50FA50FA50FA50F",
INIT_47 => X"FA543E943E943E943E943E943E94FA50FA50FA50FA50FA50FA50FA50FA50FA50",
INIT_48 => X"E943E943E943FA50FA50FA50FA50FA50FA50FA50FA50FA50FA50FA50FA50FA50",
INIT_49 => X"50FA50FA50FA943E943E943E943E950FA50FA50FA50FA50FA543E943E943E943",
INIT_4A => X"A943E943E940FA50FA50FA943E943E943EA50FA50FA50FA943E943E943E950FA",
INIT_4B => X"E950FA50FA543E943EA50FA50FA943E943E950FA50FA543E943E940FA50FA50F",
INIT_4C => X"A50FE943EA50FA503E943E950FA50FE943E950FA50FA943E943FA50FA503E943",
INIT_4D => X"43E950FA503E940FA50FE943EA50FA503E943FA50FA943E940FA50FE943E950F",
INIT_4E => X"A50FA943EA50FA943EA50FA943E950FA543E950FA503E940FA50FE943FA50FA9",
INIT_4F => X"A943EA50FE943FA503E940FA503E950FA543E950FA943EA50FA943EA50FA943E",
INIT_50 => X"940FA543EA50FE940FA543EA50FE943FA503E950FA943EA50FE940FA503E950F",
INIT_51 => X"0FA943FA503EA50FE940FA543FA503E950FA943FA543EA50FE940FA543EA50FE",
INIT_52 => X"503EA503E950FE940FA940FA543FA503EA50FE950FA940FA543FA503E950FE94",
INIT_53 => X"943FA543FA543FA543FA503EA503EA503E950FE950FE940FA940FA943FA543FA",
INIT_54 => X"43FA540FA940FA940FA940FA940FA940FA940FA940FA940FA940FA940FA940FA",
INIT_55 => X"EA503EA543FA543FA940FA940FE950FE950FEA503EA503EA503FA543FA543FA5",
INIT_56 => X"3FA540FA950FEA503EA543FA940FA950FE9503EA503FA543FA940FA950FE9503",
INIT_57 => X"3FA540FE9503EA543FA940FE9503EA543FA940FE9503EA543FA940FE9503EA54",
INIT_58 => X"E9503FA540FE9503FA540FE9503FA540FE9503EA540FA9503EA543FA950FEA50",
INIT_59 => X"03FA540FEA543FA9503EA540FE9503FA940FEA543FA9503EA540FA9503FA540F",
INIT_5A => X"503FA540FEA540FEA503FA9503FA950FEA540FEA503FA9503FA540FEA543FA95",
INIT_5B => X"03FA9503FA9503FA9503FA9503FA9503FA540FEA540FEA540FEA543FA9503FA9",
INIT_5C => X"FA9503FA9503FA9503FA9503FA9503FEA540FEA540FEA540FEA540FEA540FA95",
INIT_5D => X"03FA9503FAA540FEA540FEA9503FA9503FA9500FEA540FEA540FEA540FFA9503",
INIT_5E => X"03FEA540FEA9503FAA540FEA5503FA9500FEA540FEA9503FA9500FEA540FEA55",
INIT_5F => X"FFA9500FEA5503FA9540FEA9503FAA540FFA9503FEA540FFA9503FEA540FFA95",
INIT_60 => X"5403FAA540FFA9540FEA9500FEA5503FEA5403FA9540FFA9500FEA5503FAA540",
INIT_61 => X"A9500FEA9500FEA9500FEA9500FEA9500FEA9500FEA9500FEA5503FEA5503FEA",
INIT_62 => X"95403FAA5403FEA5500FEA9500FFA9540FFAA5403FAA5503FEA5503FEA5500FE",
INIT_63 => X"03FEA9500FFAA5403FEA9500FFA95403FEA5500FEA95403FAA5503FEA9500FFA",
INIT_64 => X"5500FFAA5500FFA95403FEA95403FAA5500FFAA5503FEA95403FAA5500FFA954",
INIT_65 => X"95403FEA95403FEA95403FEA95403FEA95403FEA95403FEA95403FEA9540FFAA",
INIT_66 => X"403FEA95400FFAA5500FFAA95403FEA95403FFAA5500FFAA5500FFAA55403FEA",
INIT_67 => X"AA55003FEA95500FFAA95403FFAA55003FEA95500FFAA55403FEA95500FFAA55",
INIT_68 => X"FAA95400FFAA95500FFEA95500FFEA95500FFAA95400FFAA95400FFAA55403FF",
INIT_69 => X"AA55400FFEA955003FEAA55400FFAA95500FFEAA55003FEAA55403FFAA95400F",
INIT_6A => X"400FFEAA55003FFAA955003FFAA955003FFAA55400FFEAA55400FFAA955003FF",
INIT_6B => X"955003FFAAA55400FFEAA554003FFAA955003FFAA955003FFAA955400FFEAA55",
INIT_6C => X"554003FFAAA554003FFAA955400FFFAA955000FFEAA555003FFAAA55400FFEAA",
INIT_6D => X"03FFEAA9554003FFAAA555003FFEAA955000FFFAA9554003FFAAA554003FFAAA",
INIT_6E => X"555000FFFAAA9554003FFEAA9554003FFEAA9554003FFAAA555000FFFAAA5550",
INIT_6F => X"9555000FFFEAA9555000FFFEAA9554000FFFAAA5554003FFEAA9555000FFFAAA",
INIT_70 => X"50003FFEAAA5554000FFFEAAA5550003FFFAAA9554000FFFEAA9555000FFFEAA",
INIT_71 => X"AAAA5554000FFFFAAA95550000FFFEAAA5554000FFFEAAA95550003FFFAAA955",
INIT_72 => X"FFEAAA955540003FFFEAAA55550000FFFFAAA955540003FFFAAAA55540003FFF",
INIT_73 => X"AAAA555540000FFFFAAAA555540003FFFFAAAA55550000FFFFEAAA955540003F",
INIT_74 => X"40000FFFFFAAAA9555500003FFFFEAAAA555540000FFFFEAAA9555500003FFFF",
INIT_75 => X"55555400003FFFFEAAAA95555400003FFFFEAAAA9555540000FFFFFAAAA95555",
INIT_76 => X"5555000000FFFFFEAAAAA55555400000FFFFFEAAAAA55555400003FFFFFAAAAA",
INIT_77 => X"0FFFFFFEAAAAAA5555554000003FFFFFEAAAAA9555554000003FFFFFEAAAAA95",
INIT_78 => X"55500000003FFFFFFEAAAAAA955555540000003FFFFFFEAAAAAA555555400000",
INIT_79 => X"555400000000FFFFFFFFEAAAAAAA95555555400000003FFFFFFFAAAAAAA95555",
INIT_7A => X"00FFFFFFFFFFEAAAAAAAAA5555555554000000000FFFFFFFFFAAAAAAAAA55555",
INIT_7B => X"5555555554000000000000FFFFFFFFFFFEAAAAAAAAAAA5555555555400000000",
INIT_7C => X"A95555555555555555000000000000000FFFFFFFFFFFFFFEAAAAAAAAAAAAA555",
INIT_7D => X"555500000000000000000000000FFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAA",
INIT_7E => X"EAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555555555",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(3 downto 2),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(3 downto 2),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"400FFEAA55400FFEAA555003FFAA955003FFAA955003FFEAA55400FFEAA55400",
INIT_01 => X"955400FFEAA55400FFEAA55400FFFAA955003FFAA955003FFAA955000FFEAA55",
INIT_02 => X"FAA955003FFAAA55400FFEAA55400FFEAA554003FFAA955003FFAA955003FFAA",
INIT_03 => X"03FFAA955003FFAA955003FFEAA55400FFEAA55400FFEAA554003FFAA955003F",
INIT_04 => X"5400FFEAA555003FFAA955003FFAA955003FFEAA55400FFEAA55400FFEAA5550",
INIT_05 => X"A955400FFEAA55400FFEAA554003FFAA955003FFAA955003FFAAA55400FFEAA5",
INIT_06 => X"FFAA955003FFAA955000FFEAA55400FFEAA55400FFFAA955003FFAA955003FFA",
INIT_07 => X"00FFEAA55400FFEAA955003FFAA955003FFAAA55400FFEAA55400FFEAA555003",
INIT_08 => X"55003FFAA955003FFEAA55400FFEAA55400FFFAA955003FFAA955003FFEAA554",
INIT_09 => X"AA55400FFEAA55400FFFAA955003FFAA955003FFEAA55400FFEAA55400FFFAA9",
INIT_0A => X"FEAA555003FFAA955003FFAAA55400FFEAA55400FFEAA955003FFAA955003FFE",
INIT_0B => X"03FFAA955003FFAAA55400FFEAA55400FFFAA955003FFAA955000FFEAA55400F",
INIT_0C => X"5003FFAA955000FFEAA55400FFEAA955003FFAA955003FFEAA55400FFEAA5550",
INIT_0D => X"955003FFAA955400FFEAA55400FFFAA955003FFAA955400FFEAA55400FFFAA95",
INIT_0E => X"AA955003FFAA955000FFEAA55400FFEAA955003FFAA955400FFEAA55400FFFAA",
INIT_0F => X"FEAA55400FFFAA955003FFAAA55400FFEAA555003FFAA955003FFEAA55400FFE",
INIT_10 => X"3FFAA955000FFEAA554003FFAA955003FFEAA55400FFEAA955003FFAA955000F",
INIT_11 => X"00FFEAA554003FFAA955000FFEAA55400FFFAA955003FFAAA55400FFEAA55500",
INIT_12 => X"400FFFAA955003FFAAA55400FFEAA955003FFAAA55400FFEAA555003FFAA9554",
INIT_13 => X"54003FFAA955000FFEAA554003FFAA955003FFEAA55400FFFAA955003FFEAA55",
INIT_14 => X"55400FFFAA955003FFEAA55400FFFAA955003FFEAA554003FFAA955000FFEAA5",
INIT_15 => X"955000FFEAA555003FFAA955400FFEAA955003FFAAA55400FFEAA955003FFEAA",
INIT_16 => X"A554003FFAA955400FFEAA955003FFAAA55400FFFAA955003FFEAA554003FFAA",
INIT_17 => X"A955003FFEAA554003FFAA955400FFEAA555003FFAAA55400FFFAA955000FFEA",
INIT_18 => X"A955003FFEAA554003FFAA955400FFEAA955003FFEAA554003FFAA955400FFEA",
INIT_19 => X"A555003FFAAA55400FFFAA955000FFEAA955003FFEAA554003FFAA955400FFEA",
INIT_1A => X"955400FFEAA955000FFEAA555003FFAAA554003FFAA955400FFEAA955003FFEA",
INIT_1B => X"55400FFFAA955400FFFAA955000FFEAA955003FFEAA554003FFAAA55400FFFAA",
INIT_1C => X"5400FFFAA955400FFFAA955000FFEAA955000FFEAA555003FFEAA554003FFAAA",
INIT_1D => X"000FFEAA955000FFEAA555003FFEAA555003FFEAA554003FFAAA554003FFAAA5",
INIT_1E => X"0FFFAA955400FFFAA955400FFFAA955400FFFAA955400FFFAA955000FFEAA955",
INIT_1F => X"FFAA955400FFFAAA554003FFAAA554003FFAAA554003FFAA955400FFFAA95540",
INIT_20 => X"AA955000FFEAA955400FFFAA955400FFFAA955400FFFAA955400FFFAA955400F",
INIT_21 => X"554003FFAAA554003FFAAA555003FFEAA555003FFEAA555000FFEAA955000FFE",
INIT_22 => X"003FFAAA554003FFEAA555003FFEAA955000FFEAA955000FFFAA955400FFFAAA",
INIT_23 => X"FEAA955400FFFAAA554003FFAAA555003FFEAA955000FFEAA955400FFFAA9554",
INIT_24 => X"9554003FFAAA555003FFEAA955000FFFAA9554003FFAAA555003FFEAA955000F",
INIT_25 => X"00FFFAAA555003FFEAA955000FFFAA9554003FFAAA555003FFEAA955000FFFAA",
INIT_26 => X"EAA955000FFFAAA554003FFEAA555000FFFAA9554003FFAAA555000FFEAA9554",
INIT_27 => X"5000FFFAAA554003FFEAA955000FFFAAA554003FFEAA955000FFFAAA554003FF",
INIT_28 => X"FEAA955000FFFAAA555003FFEAA9554003FFAAA555000FFFAA9554003FFEAA55",
INIT_29 => X"5000FFFAAA555000FFFAA9554003FFEAA955400FFFAAA555000FFFAA9554003F",
INIT_2A => X"EAA9554003FFEAA955400FFFAAA555000FFFAAA555003FFEAA9554003FFEAA95",
INIT_2B => X"003FFEAA9554003FFEAA955400FFFAAA555000FFFAAA555000FFFAAA554003FF",
INIT_2C => X"A555000FFFAAA555000FFFAAA555000FFFAAA555003FFEAA9554003FFEAA9554",
INIT_2D => X"FFAAA555000FFFAAA555000FFFAAA555000FFFAAA555000FFFAAA555000FFFAA",
INIT_2E => X"003FFEAA9554003FFEAA9554003FFEAA9554000FFFAAA555000FFFAAA555000F",
INIT_2F => X"554003FFEAA9554003FFEAAA555000FFFAAA555000FFFAAA555000FFFEAA9554",
INIT_30 => X"AA555000FFFAAA5550003FFEAA9554003FFEAAA555000FFFAAA555000FFFAAA9",
INIT_31 => X"EAAA555000FFFAAA5554003FFEAA9554000FFFAAA555000FFFEAA9554003FFEA",
INIT_32 => X"FFAAA9554003FFEAAA555000FFFAAA9554003FFEAAA555000FFFAAA9554003FF",
INIT_33 => X"FFFAAA5554003FFEAAA555000FFFEAA9554000FFFAAA5550003FFEAA9555000F",
INIT_34 => X"FFFEAA9554000FFFAAA9554003FFFAAA5550003FFEAAA555000FFFEAA9554000",
INIT_35 => X"FFFAAA9554003FFFAAA5554003FFFAAA5554003FFEAAA5550003FFEAA9555000",
INIT_36 => X"FFAAA9554000FFFAAA9554000FFFAAA9554000FFFAAA9554000FFFAAA9554000",
INIT_37 => X"EAAA5550003FFFAAA5554003FFFAAA5554000FFFAAA9554000FFFAAA9554000F",
INIT_38 => X"A95550003FFEAAA5554003FFFAAA9554000FFFAAA9555000FFFEAA95550003FF",
INIT_39 => X"550003FFFAAA9554000FFFEAA95550003FFEAAA5554003FFFAAA9554000FFFEA",
INIT_3A => X"00FFFEAAA5550003FFFAAA9554000FFFEAAA5550003FFFAAA9554000FFFEAAA5",
INIT_3B => X"FAAA95550003FFFAAA5554000FFFEAAA5554003FFFAAA95550003FFFAAA55540",
INIT_3C => X"5550003FFFAAA9554000FFFEAAA5554000FFFEAAA5554000FFFEAA95550003FF",
INIT_3D => X"3FFFAAA95550003FFFAAA95550003FFFAAA95550003FFFAAA95550003FFFAAA9",
INIT_3E => X"A5554000FFFEAAA5554000FFFEAAA5554000FFFFAAA95550003FFFAAA9555000",
INIT_3F => X"3FFFAAA95550003FFFEAAA5554000FFFEAAA55550003FFFAAA95550003FFFAAA",
INIT_40 => X"5550003FFFAAA95554000FFFEAAA55550003FFFAAA95554000FFFEAAA5554000",
INIT_41 => X"EAAA95550000FFFEAAA55550003FFFAAAA5554000FFFFAAA95550000FFFEAAA5",
INIT_42 => X"03FFFEAAA55550003FFFAAAA55540003FFFAAAA5554000FFFFAAA95554000FFF",
INIT_43 => X"540003FFFAAAA55540003FFFAAAA55550003FFFEAAA55550003FFFEAAA555500",
INIT_44 => X"955540003FFFAAAA55550003FFFEAAA95550000FFFEAAA95554000FFFFAAA955",
INIT_45 => X"AA955540003FFFEAAA95550000FFFFAAAA55540003FFFEAAA55550000FFFFAAA",
INIT_46 => X"AAAA55550000FFFFAAA955540003FFFEAAA955540003FFFAAAA55550000FFFFA",
INIT_47 => X"AAAA955540003FFFEAAA95554000FFFFAAAA55550000FFFFAAAA55550000FFFF",
INIT_48 => X"AAA955540003FFFFAAAA55550000FFFFAAAA55550000FFFFAAAA55550000FFFF",
INIT_49 => X"AA55550000FFFFEAAA955540003FFFFAAAA55550000FFFFAAAA955540003FFFE",
INIT_4A => X"55540003FFFFAAAA555500003FFFEAAA955550000FFFFAAAA955540003FFFFAA",
INIT_4B => X"0000FFFFAAAA955540000FFFFAAAA955540000FFFFAAAA955540000FFFFAAAA5",
INIT_4C => X"FFFAAAA9555500003FFFEAAAA555500003FFFFAAAA555540003FFFFAAAA95554",
INIT_4D => X"A9555500003FFFFAAAA555540000FFFFEAAA9555500003FFFFAAAA555540000F",
INIT_4E => X"000FFFFEAAAA555540000FFFFEAAAA555540000FFFFEAAAA555500003FFFFAAA",
INIT_4F => X"AAA9555500003FFFFEAAAA555540000FFFFEAAAA555540000FFFFEAAAA555540",
INIT_50 => X"000FFFFEAAAA5555500003FFFFAAAA9555540000FFFFEAAAA5555500003FFFFA",
INIT_51 => X"A5555400003FFFFAAAAA5555400003FFFFAAAA9555540000FFFFFAAAA9555500",
INIT_52 => X"FFEAAAA9555500000FFFFFAAAA9555540000FFFFFAAAAA5555400003FFFFAAAA",
INIT_53 => X"003FFFFEAAAA95555400003FFFFEAAAA9555500000FFFFFAAAAA5555400003FF",
INIT_54 => X"5400000FFFFFAAAAA5555500000FFFFFAAAAA5555500000FFFFFAAAAA5555500",
INIT_55 => X"5555400003FFFFEAAAAA5555500000FFFFFAAAAA95555400003FFFFEAAAA9555",
INIT_56 => X"95555500000FFFFFEAAAA95555500000FFFFFEAAAA95555400000FFFFFAAAAA9",
INIT_57 => X"955555000003FFFFEAAAAA55555400003FFFFFAAAAA95555400000FFFFFEAAAA",
INIT_58 => X"5555400000FFFFFEAAAAA55555400000FFFFFEAAAAA55555400003FFFFFAAAAA",
INIT_59 => X"5400000FFFFFEAAAAA955555000003FFFFFAAAAA955555400000FFFFFEAAAAA5",
INIT_5A => X"003FFFFFAAAAAA555554000003FFFFFAAAAAA555554000003FFFFFAAAAA95555",
INIT_5B => X"FEAAAAA9555554000003FFFFFEAAAAA955555000000FFFFFFAAAAA9555554000",
INIT_5C => X"555554000003FFFFFEAAAAA9555554000000FFFFFFAAAAAA555555000000FFFF",
INIT_5D => X"03FFFFFEAAAAAA5555550000003FFFFFEAAAAAA555555000000FFFFFFAAAAAA9",
INIT_5E => X"A95555550000003FFFFFFAAAAAA9555555000000FFFFFFEAAAAAA55555500000",
INIT_5F => X"FFFFFFFAAAAAA95555550000003FFFFFFAAAAAA95555550000003FFFFFFAAAAA",
INIT_60 => X"5554000000FFFFFFFAAAAAAA55555540000003FFFFFFAAAAAAA5555554000000",
INIT_61 => X"AAAAA55555550000000FFFFFFFAAAAAAA55555550000000FFFFFFEAAAAAA9555",
INIT_62 => X"FFFFEAAAAAA955555550000000FFFFFFFAAAAAAA955555540000003FFFFFFFAA",
INIT_63 => X"03FFFFFFFAAAAAAA9555555500000003FFFFFFFAAAAAAA955555540000000FFF",
INIT_64 => X"0000FFFFFFFFAAAAAAA9555555540000000FFFFFFFEAAAAAAA95555555000000",
INIT_65 => X"00003FFFFFFFEAAAAAAA95555555400000003FFFFFFFEAAAAAAA955555550000",
INIT_66 => X"003FFFFFFFFAAAAAAAA55555555400000003FFFFFFFFAAAAAAAA555555554000",
INIT_67 => X"FFFFFFEAAAAAAAA555555554000000003FFFFFFFFAAAAAAAA955555555000000",
INIT_68 => X"AAAAAAAA555555555000000000FFFFFFFFFAAAAAAAAA555555555000000003FF",
INIT_69 => X"55555550000000003FFFFFFFFFAAAAAAAAA5555555554000000003FFFFFFFFFA",
INIT_6A => X"000FFFFFFFFFEAAAAAAAAA95555555554000000000FFFFFFFFFFAAAAAAAAA955",
INIT_6B => X"AAAAA9555555555500000000003FFFFFFFFFEAAAAAAAAA955555555550000000",
INIT_6C => X"000003FFFFFFFFFFEAAAAAAAAAA5555555555500000000003FFFFFFFFFFAAAAA",
INIT_6D => X"A955555555555400000000003FFFFFFFFFFFAAAAAAAAAAA95555555555400000",
INIT_6E => X"FFFFFFAAAAAAAAAAAA9555555555554000000000003FFFFFFFFFFFAAAAAAAAAA",
INIT_6F => X"0000000FFFFFFFFFFFFFAAAAAAAAAAAAA5555555555554000000000000FFFFFF",
INIT_70 => X"555540000000000000FFFFFFFFFFFFFEAAAAAAAAAAAAA5555555555555000000",
INIT_71 => X"55555555555000000000000000FFFFFFFFFFFFFFAAAAAAAAAAAAAA9555555555",
INIT_72 => X"555555555555554000000000000000FFFFFFFFFFFFFFFEAAAAAAAAAAAAAA9555",
INIT_73 => X"555555555555500000000000000003FFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAA95",
INIT_74 => X"555550000000000000000003FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAA95555",
INIT_75 => X"00000000003FFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAA55555555555555",
INIT_76 => X"FFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAA55555555555555555555540000000000",
INIT_77 => X"A55555555555555555555555554000000000000000000000003FFFFFFFFFFFFF",
INIT_78 => X"00000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_79 => X"AAAAAAAAAAAA5555555555555555555555555555555540000000000000000000",
INIT_7A => X"00FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAA",
INIT_7B => X"5555555555555555555555000000000000000000000000000000000000000000",
INIT_7C => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555555555555555555555555555",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(5 downto 4),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5 downto 4),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"AAA555555555500000000003FFFFFFFFFEAAAAAAAAA955555555550000000000",
INIT_01 => X"000000FFFFFFFFFFAAAAAAAAAA555555555540000000003FFFFFFFFFFAAAAAAA",
INIT_02 => X"AAAAAAAA955555555550000000000FFFFFFFFFFEAAAAAAAAA955555555540000",
INIT_03 => X"540000000003FFFFFFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFEA",
INIT_04 => X"FFFFAAAAAAAAAA955555555540000000003FFFFFFFFFFAAAAAAAAAA555555555",
INIT_05 => X"55555550000000000FFFFFFFFFFEAAAAAAAAA955555555540000000000FFFFFF",
INIT_06 => X"FFFFFFFFFEAAAAAAAAAA55555555550000000000FFFFFFFFFFEAAAAAAAAA9555",
INIT_07 => X"AA555555555500000000003FFFFFFFFFEAAAAAAAAAA555555555500000000003",
INIT_08 => X"00003FFFFFFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFEAAAAAAAA",
INIT_09 => X"AAAAAAA555555555500000000003FFFFFFFFFEAAAAAAAAAA5555555555000000",
INIT_0A => X"0000000003FFFFFFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFEAAA",
INIT_0B => X"FEAAAAAAAAA955555555550000000000FFFFFFFFFFEAAAAAAAAAA55555555550",
INIT_0C => X"55540000000000FFFFFFFFFFAAAAAAAAAA955555555540000000000FFFFFFFFF",
INIT_0D => X"FFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFFAAAAAAAAAA5555555",
INIT_0E => X"555555540000000000FFFFFFFFFFAAAAAAAAAA955555555550000000000FFFFF",
INIT_0F => X"FFFFFFFFFAAAAAAAAAA9555555555500000000003FFFFFFFFFEAAAAAAAAAA555",
INIT_10 => X"9555555555500000000003FFFFFFFFFEAAAAAAAAAA555555555540000000000F",
INIT_11 => X"00FFFFFFFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFFAAAAAAAAAA",
INIT_12 => X"AAA555555555540000000000FFFFFFFFFFEAAAAAAAAAA5555555555400000000",
INIT_13 => X"00003FFFFFFFFFFAAAAAAAAAA955555555540000000000FFFFFFFFFFEAAAAAAA",
INIT_14 => X"AAAAA555555555540000000000FFFFFFFFFFEAAAAAAAAAA95555555555000000",
INIT_15 => X"000000FFFFFFFFFFEAAAAAAAAAA555555555540000000000FFFFFFFFFFEAAAAA",
INIT_16 => X"AAAAAA9555555555500000000003FFFFFFFFFFAAAAAAAAAA9555555555540000",
INIT_17 => X"0000003FFFFFFFFFFEAAAAAAAAAA555555555540000000000FFFFFFFFFFFAAAA",
INIT_18 => X"AAAAAA9555555555540000000000FFFFFFFFFFEAAAAAAAAAA955555555550000",
INIT_19 => X"0000003FFFFFFFFFFAAAAAAAAAAA5555555555400000000003FFFFFFFFFFAAAA",
INIT_1A => X"AAAAAA5555555555500000000003FFFFFFFFFFEAAAAAAAAAA555555555540000",
INIT_1B => X"00000FFFFFFFFFFFAAAAAAAAAAA5555555555400000000003FFFFFFFFFFAAAAA",
INIT_1C => X"AAAA5555555555500000000000FFFFFFFFFFFAAAAAAAAAA95555555555400000",
INIT_1D => X"000FFFFFFFFFFFAAAAAAAAAA95555555555400000000003FFFFFFFFFFEAAAAAA",
INIT_1E => X"A5555555555500000000000FFFFFFFFFFFAAAAAAAAAAA5555555555500000000",
INIT_1F => X"FFFFFFFFFFAAAAAAAAAAA95555555555400000000003FFFFFFFFFFAAAAAAAAAA",
INIT_20 => X"5555555500000000000FFFFFFFFFFFAAAAAAAAAAA5555555555500000000000F",
INIT_21 => X"FFFFFEAAAAAAAAAA95555555555400000000003FFFFFFFFFFFAAAAAAAAAAA555",
INIT_22 => X"55400000000003FFFFFFFFFFEAAAAAAAAAAA5555555555500000000000FFFFFF",
INIT_23 => X"AAAAAAAAAA55555555555400000000003FFFFFFFFFFFAAAAAAAAAAA555555555",
INIT_24 => X"0000003FFFFFFFFFFEAAAAAAAAAAA55555555555400000000003FFFFFFFFFFFA",
INIT_25 => X"AA55555555555400000000000FFFFFFFFFFFEAAAAAAAAAA95555555555500000",
INIT_26 => X"FFFFFFFFFAAAAAAAAAAA955555555555000000000003FFFFFFFFFFFAAAAAAAAA",
INIT_27 => X"5555000000000003FFFFFFFFFFFAAAAAAAAAAA955555555555000000000003FF",
INIT_28 => X"AAAAAAAAAA555555555554000000000003FFFFFFFFFFFAAAAAAAAAAA95555555",
INIT_29 => X"0000FFFFFFFFFFFFAAAAAAAAAAA955555555555000000000000FFFFFFFFFFFEA",
INIT_2A => X"555555555400000000000FFFFFFFFFFFFAAAAAAAAAAA95555555555540000000",
INIT_2B => X"FFEAAAAAAAAAAA955555555555000000000000FFFFFFFFFFFFAAAAAAAAAAA955",
INIT_2C => X"0000000FFFFFFFFFFFFAAAAAAAAAAAA555555555554000000000003FFFFFFFFF",
INIT_2D => X"55555555555000000000000FFFFFFFFFFFFAAAAAAAAAAAA55555555555500000",
INIT_2E => X"FFEAAAAAAAAAAA9555555555554000000000000FFFFFFFFFFFFAAAAAAAAAAAA5",
INIT_2F => X"000003FFFFFFFFFFFEAAAAAAAAAAAA555555555555000000000000FFFFFFFFFF",
INIT_30 => X"555555550000000000003FFFFFFFFFFFEAAAAAAAAAAAA5555555555550000000",
INIT_31 => X"AAAAAAAAAA5555555555554000000000000FFFFFFFFFFFFAAAAAAAAAAAA95555",
INIT_32 => X"FFFFFFFFFFFEAAAAAAAAAAAA5555555555554000000000000FFFFFFFFFFFFEAA",
INIT_33 => X"0000000000003FFFFFFFFFFFFAAAAAAAAAAAAA5555555555554000000000000F",
INIT_34 => X"55555555555550000000000003FFFFFFFFFFFFEAAAAAAAAAAAA5555555555555",
INIT_35 => X"AAAAAAAAAAAA955555555555540000000000003FFFFFFFFFFFFEAAAAAAAAAAAA",
INIT_36 => X"FFFFFFFFFFFFAAAAAAAAAAAAA55555555555550000000000000FFFFFFFFFFFFF",
INIT_37 => X"00000000003FFFFFFFFFFFFEAAAAAAAAAAAAA55555555555550000000000000F",
INIT_38 => X"5555555540000000000003FFFFFFFFFFFFFAAAAAAAAAAAAA5555555555555400",
INIT_39 => X"AAAAA9555555555555500000000000003FFFFFFFFFFFFEAAAAAAAAAAAAA55555",
INIT_3A => X"FFAAAAAAAAAAAAA9555555555555500000000000003FFFFFFFFFFFFFAAAAAAAA",
INIT_3B => X"FFFFFFFFFFFEAAAAAAAAAAAAA5555555555555400000000000003FFFFFFFFFFF",
INIT_3C => X"0000003FFFFFFFFFFFFFAAAAAAAAAAAAAA5555555555555500000000000003FF",
INIT_3D => X"400000000000003FFFFFFFFFFFFFEAAAAAAAAAAAAA9555555555555540000000",
INIT_3E => X"5555555500000000000000FFFFFFFFFFFFFFAAAAAAAAAAAAAA95555555555555",
INIT_3F => X"95555555555555400000000000000FFFFFFFFFFFFFFEAAAAAAAAAAAAA9555555",
INIT_40 => X"AAAAAA955555555555555000000000000003FFFFFFFFFFFFFFAAAAAAAAAAAAAA",
INIT_41 => X"AAAAAAAAAAAA55555555555555400000000000000FFFFFFFFFFFFFFFAAAAAAAA",
INIT_42 => X"FEAAAAAAAAAAAAAA955555555555555400000000000000FFFFFFFFFFFFFFFAAA",
INIT_43 => X"FFFFFEAAAAAAAAAAAAAA9555555555555554000000000000003FFFFFFFFFFFFF",
INIT_44 => X"FFFFFFFFEAAAAAAAAAAAAAA9555555555555555000000000000000FFFFFFFFFF",
INIT_45 => X"FFFFFFFFFFEAAAAAAAAAAAAAAA5555555555555554000000000000000FFFFFFF",
INIT_46 => X"FFFFFFFFFFFFAAAAAAAAAAAAAAA95555555555555554000000000000000FFFFF",
INIT_47 => X"FFFFFFFFFFFFEAAAAAAAAAAAAAAA55555555555555550000000000000000FFFF",
INIT_48 => X"FFFFFFFFFFFEAAAAAAAAAAAAAAAA55555555555555550000000000000000FFFF",
INIT_49 => X"FFFFFFFFFFAAAAAAAAAAAAAAAA9555555555555555500000000000000003FFFF",
INIT_4A => X"FFFFFFFEAAAAAAAAAAAAAAAA9555555555555555500000000000000003FFFFFF",
INIT_4B => X"FFFFAAAAAAAAAAAAAAAAA5555555555555555500000000000000000FFFFFFFFF",
INIT_4C => X"AAAAAAAAAAAAAAAA95555555555555555400000000000000003FFFFFFFFFFFFF",
INIT_4D => X"AAAAAAAAAA955555555555555555000000000000000003FFFFFFFFFFFFFFFFFA",
INIT_4E => X"AAA555555555555555555000000000000000000FFFFFFFFFFFFFFFFFEAAAAAAA",
INIT_4F => X"5555555555554000000000000000000FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAA",
INIT_50 => X"5550000000000000000003FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAA955555",
INIT_51 => X"00000000003FFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAA5555555555555555",
INIT_52 => X"FFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAA5555555555555555555400000000",
INIT_53 => X"FFEAAAAAAAAAAAAAAAAAAA9555555555555555555500000000000000000003FF",
INIT_54 => X"AAAAAAA5555555555555555555500000000000000000000FFFFFFFFFFFFFFFFF",
INIT_55 => X"555555555400000000000000000000FFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAA",
INIT_56 => X"00000000000FFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAA55555555555",
INIT_57 => X"FFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAA95555555555555555555550000000000",
INIT_58 => X"AAAAAAAAAA55555555555555555555550000000000000000000003FFFFFFFFFF",
INIT_59 => X"555555500000000000000000000003FFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAA",
INIT_5A => X"003FFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAA9555555555555555",
INIT_5B => X"AAAAAAAAAAAAAAAAAAA955555555555555555555555000000000000000000000",
INIT_5C => X"555555555554000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFAAAA",
INIT_5D => X"03FFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAA5555555555555",
INIT_5E => X"AAAAAAAAAAAAAA95555555555555555555555555000000000000000000000000",
INIT_5F => X"000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAA",
INIT_60 => X"FFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAA955555555555555555555555555",
INIT_61 => X"55555555555555555550000000000000000000000000000FFFFFFFFFFFFFFFFF",
INIT_62 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAA9555555555",
INIT_63 => X"A955555555555555555555555555555400000000000000000000000000000FFF",
INIT_64 => X"0000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_65 => X"AAAA955555555555555555555555555555554000000000000000000000000000",
INIT_66 => X"003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_67 => X"5555555555555555555555555555555540000000000000000000000000000000",
INIT_68 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955",
INIT_69 => X"555555555555555540000000000000000000000000000000000003FFFFFFFFFF",
INIT_6A => X"FFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555555555555555555",
INIT_6B => X"000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6C => X"AAAAA95555555555555555555555555555555555555555554000000000000000",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_6E => X"0000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"AAAAAAA555555555555555555555555555555555555555555555555555000000",
INIT_70 => X"FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_71 => X"00000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_72 => X"5555555555555555555555555555550000000000000000000000000000000000",
INIT_73 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555555",
INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_75 => X"00000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"5555555555555555555555555555555555555555555555555540000000000000",
INIT_78 => X"AAAAAAAAAA955555555555555555555555555555555555555555555555555555",
INIT_79 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_7A => X"FFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(7 downto 6),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(7 downto 6),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"5555555555555555555555540000000000000000000000000000000000000000",
INIT_01 => X"FFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955555555555555555",
INIT_02 => X"00000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"AAAAAAAAAAA95555555555555555555555555555555555555555400000000000",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_05 => X"5555555555555555500000000000000000000000000000000000000000FFFFFF",
INIT_06 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555555555",
INIT_07 => X"00000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_08 => X"AAAA955555555555555555555555555555555555555554000000000000000000",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_0A => X"555555555400000000000000000000000000000000000000003FFFFFFFFFFFFF",
INIT_0B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555555555555555",
INIT_0C => X"00000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAA",
INIT_0D => X"5555555555555555555555555555555555554000000000000000000000000000",
INIT_0E => X"FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555",
INIT_0F => X"00000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"AAAAAAAAAAAAAAAAAAAAA9555555555555555555555555555555555555555550",
INIT_11 => X"00FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAA",
INIT_12 => X"5555555555555555555555550000000000000000000000000000000000000000",
INIT_13 => X"FFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555",
INIT_14 => X"00000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"AAAAAA5555555555555555555555555555555555555555550000000000000000",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_17 => X"5555554000000000000000000000000000000000000000000FFFFFFFFFFFFFFF",
INIT_18 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555555555555555555555",
INIT_19 => X"0000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAA",
INIT_1A => X"5555555555555555555555555554000000000000000000000000000000000000",
INIT_1B => X"FFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA9555555555555555",
INIT_1C => X"00000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"AAA5555555555555555555555555555555555555555555400000000000000000",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1F => X"00000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"AAAAAAAAAAAAAAAAAAA555555555555555555555555555555555555555555550",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_22 => X"5555555555555400000000000000000000000000000000000000000000FFFFFF",
INIT_23 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555",
INIT_24 => X"0000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAA",
INIT_25 => X"5555555555555555555555555000000000000000000000000000000000000000",
INIT_26 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955555555555555555555",
INIT_27 => X"0000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAA",
INIT_28 => X"5555555555555555555555555555555554000000000000000000000000000000",
INIT_29 => X"FFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555555555",
INIT_2A => X"000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"5555555555555555555555555555555555555500000000000000000000000000",
INIT_2C => X"FFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA9555555555",
INIT_2D => X"00000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"5555555555555555555555555555555555555550000000000000000000000000",
INIT_2F => X"FFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555555",
INIT_30 => X"000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_31 => X"5555555555555555555555555555555555500000000000000000000000000000",
INIT_32 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555",
INIT_33 => X"0000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA",
INIT_34 => X"5555555555555555555555555400000000000000000000000000000000000000",
INIT_35 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAA",
INIT_37 => X"555555555540000000000000000000000000000000000000000000000000000F",
INIT_38 => X"AAAAAAAAAAAAAAAAAAAAA9555555555555555555555555555555555555555555",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_3A => X"0000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFF",
INIT_3B => X"5555555555555555555555555555555555555555555555555555400000000000",
INIT_3C => X"FFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955",
INIT_3D => X"000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3E => X"5555555555555555555555000000000000000000000000000000000000000000",
INIT_3F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555555555555555555",
INIT_40 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_41 => X"00000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFF",
INIT_42 => X"5555555555555555555555555555555555555555555555000000000000000000",
INIT_43 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555",
INIT_44 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAA",
INIT_45 => X"000000000000000000000000000000000000000000000000000000000FFFFFFF",
INIT_46 => X"5555555555555555555555555555555555555555555555555555555555500000",
INIT_47 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555",
INIT_48 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAA",
INIT_49 => X"000000000000000000000000000000000000000000000000000000000003FFFF",
INIT_4A => X"5555555555555555555555555555555555555555555555555555555554000000",
INIT_4B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555",
INIT_4C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAA",
INIT_4D => X"0000000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFF",
INIT_4E => X"5555555555555555555555555555555555555550000000000000000000000000",
INIT_4F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555555555555555555",
INIT_50 => X"FFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_51 => X"00000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"5555555555555555555555555555555555555555555555555555555555555400",
INIT_54 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555",
INIT_55 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_56 => X"00000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"5555555555555555555555555555555555555555555555555555540000000000",
INIT_59 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555555",
INIT_5A => X"FFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5C => X"000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5D => X"5400000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_5F => X"AAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555555555",
INIT_60 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_61 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAA",
INIT_62 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000FFF",
INIT_64 => X"5555000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_66 => X"AA95555555555555555555555555555555555555555555555555555555555555",
INIT_67 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_68 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_69 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAA",
INIT_6A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6B => X"000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"5555555555555555555555555555555555555555554000000000000000000000",
INIT_6F => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_70 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_71 => X"AAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555555555555555555555",
INIT_72 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_73 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_74 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_75 => X"FFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => p_0_in(1 downto 0),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(9 downto 8),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"5555555555555555555555555555500000000000000000000000000000000000",
INIT_03 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_04 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_05 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555",
INIT_06 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"000000000000000000000000000000000000000000000000003FFFFFFFFFFFFF",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"5555555555555500000000000000000000000000000000000000000000000000",
INIT_0D => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0E => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955555555555555555555555",
INIT_10 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_11 => X"FFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"00000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"5555555555555555555555555555555555555555555555555000000000000000",
INIT_18 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_19 => X"AAAAAA9555555555555555555555555555555555555555555555555555555555",
INIT_1A => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"00000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"5555555555555555555555555555555555555555555555555555555555000000",
INIT_23 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_24 => X"AAAAAA9555555555555555555555555555555555555555555555555555555555",
INIT_25 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_26 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_27 => X"FFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"5555555555555555555555500000000000000000000000000000000000000000",
INIT_2E => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_2F => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_30 => X"AAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555555555555555",
INIT_31 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_32 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_33 => X"FFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"000000000000000000000000000000000000000000000000000000000000000F",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"5555555555555555555555555555555555555555554000000000000000000000",
INIT_3B => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3C => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3D => X"AAAAAAAAAAAAAA95555555555555555555555555555555555555555555555555",
INIT_3E => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_3F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_40 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_41 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAA",
INIT_42 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_43 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_44 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_45 => X"000000000000000000000000000000000000000000000000000000000FFFFFFF",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"5555555555555555555555555555555555555555555555555555555555540000",
INIT_4A => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_4B => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_4C => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_4D => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA9555555555555555555",
INIT_4E => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_50 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_51 => X"FFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_52 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_53 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_54 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_55 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_56 => X"00000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"5555555555555555555555555555555555550000000000000000000000000000",
INIT_5D => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_5E => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_5F => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_60 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_61 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_62 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_63 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555",
INIT_64 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_65 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_66 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_67 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_68 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_69 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_6A => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_6B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_6C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_70 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_71 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_73 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_75 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => p_0_in(3 downto 2),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(11 downto 10),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"5555555555555555555555555555555555555555555555555540000000000000",
INIT_0B => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0C => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0D => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0E => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_0F => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_10 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_11 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_12 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_13 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_14 => X"AAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555555555555555555555",
INIT_15 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_16 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_17 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_18 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_19 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1A => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1C => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1D => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1E => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAA",
INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"5555555555555555555555555555555555555555555555555555555555555550",
INIT_38 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_39 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3A => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3B => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3C => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3D => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3E => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_3F => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_40 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_41 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_42 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_43 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_44 => X"5555555555555555555555555555555555555555555555555555555555555555",
INIT_45 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555",
INIT_46 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_47 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_48 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_49 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4A => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4C => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4D => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4E => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_4F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_50 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_51 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_52 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_53 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_54 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_55 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_56 => X"FFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INIT_57 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_58 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_59 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_60 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_61 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_62 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_63 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_64 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_65 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_66 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_67 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_68 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_69 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_70 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_71 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_73 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_75 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(15) => \<const1>\,
ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0),
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(15) => \<const1>\,
ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0),
ADDRBWRADDR(0) => \<const0>\,
CASCADEINA => \<const1>\,
CASCADEINB => \<const0>\,
CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DBITERR_UNCONNECTED\,
DIADI(31) => \<const0>\,
DIADI(30) => \<const0>\,
DIADI(29) => \<const0>\,
DIADI(28) => \<const0>\,
DIADI(27) => \<const0>\,
DIADI(26) => \<const0>\,
DIADI(25) => \<const0>\,
DIADI(24) => \<const0>\,
DIADI(23) => \<const0>\,
DIADI(22) => \<const0>\,
DIADI(21) => \<const0>\,
DIADI(20) => \<const0>\,
DIADI(19) => \<const0>\,
DIADI(18) => \<const0>\,
DIADI(17) => \<const0>\,
DIADI(16) => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(31) => \<const1>\,
DIBDI(30) => \<const1>\,
DIBDI(29) => \<const1>\,
DIBDI(28) => \<const1>\,
DIBDI(27) => \<const1>\,
DIBDI(26) => \<const1>\,
DIBDI(25) => \<const1>\,
DIBDI(24) => \<const1>\,
DIBDI(23) => \<const1>\,
DIBDI(22) => \<const1>\,
DIBDI(21) => \<const1>\,
DIBDI(20) => \<const1>\,
DIBDI(19) => \<const1>\,
DIBDI(18) => \<const1>\,
DIBDI(17) => \<const1>\,
DIBDI(16) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(3) => \<const0>\,
DIPADIP(2) => \<const0>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(3) => \<const1>\,
DIPBDIP(2) => \<const1>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => p_0_in(5 downto 4),
DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(13 downto 12),
DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_SBITERR_UNCONNECTED\,
WEA(3) => \<const0>\,
WEA(2) => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(7) => \<const0>\,
WEBWE(6) => \<const0>\,
WEBWE(5) => \<const0>\,
WEBWE(4) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000000000000000000000",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 0) => sin_addr(13 downto 0),
ADDRBWRADDR(13 downto 0) => cos_addr(13 downto 0),
CLKARDCLK => aclk,
CLKBWRCLK => aclk,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const0>\,
DIADI(6) => \<const0>\,
DIADI(5) => \<const0>\,
DIADI(4) => \<const0>\,
DIADI(3) => \<const0>\,
DIADI(2) => \<const0>\,
DIADI(1) => \<const0>\,
DIADI(0) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(15 downto 1) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => p_0_in(6),
DOBDO(15 downto 1) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOBDO_UNCONNECTED\(15 downto 1),
DOBDO(0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(14),
DOPADOP(1 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => s_axis_phase_tvalid,
ENBWREN => s_axis_phase_tvalid,
REGCEAREGCE => s_axis_phase_tvalid,
REGCEB => s_axis_phase_tvalid,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(0),
Q => mod_cos_addr(0),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(10),
Q => mod_cos_addr(10),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(11),
Q => mod_cos_addr(11),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(12),
Q => mod_cos_addr(12),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(13),
Q => mod_cos_addr(13),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(1),
Q => mod_cos_addr(1),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(2),
Q => mod_cos_addr(2),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(3),
Q => mod_cos_addr(3),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(4),
Q => mod_cos_addr(4),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(5),
Q => mod_cos_addr(5),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(6),
Q => mod_cos_addr(6),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(7),
Q => mod_cos_addr(7),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(8),
Q => mod_cos_addr(8),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => I1(9),
Q => mod_cos_addr(9),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(0),
Q => mod_sin_addr(0),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(10),
Q => mod_sin_addr(10),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(11),
Q => mod_sin_addr(11),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(12),
Q => mod_sin_addr(12),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(13),
Q => mod_sin_addr(13),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(1),
Q => mod_sin_addr(1),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(2),
Q => mod_sin_addr(2),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(3),
Q => mod_sin_addr(3),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(4),
Q => mod_sin_addr(4),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(5),
Q => mod_sin_addr(5),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(6),
Q => mod_sin_addr(6),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(7),
Q => mod_sin_addr(7),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(8),
Q => mod_sin_addr(8),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => D(9),
Q => mod_sin_addr(9),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_3\
port map (
aclk => aclk,
m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(7 downto 0),
\out\(7 downto 0) => cos_ls1(7 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_4\
port map (
I1 => \n_6_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I2 => \n_5_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I3 => \n_4_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I4 => \n_3_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I5 => \n_2_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I6 => \n_1_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I7 => \n_0_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
I8 => \n_7_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
aclk => aclk,
m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(15 downto 8),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14\
port map (
aclk => aclk,
m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(23 downto 16),
\out\(7 downto 0) => sin_ls1(7 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_2\
port map (
I1 => \n_6_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I2 => \n_5_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I3 => \n_4_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I4 => \n_3_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I5 => \n_2_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I6 => \n_1_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I7 => \n_0_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
I8 => \n_7_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
aclk => aclk,
m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(31 downto 24),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized16\
port map (
DOBDO(0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0),
I1 => \n_22_i_rtl.i_quarter_table.i_addr_reg_c\,
I2 => \n_21_i_rtl.i_quarter_table.i_addr_reg_c\,
I3 => \n_20_i_rtl.i_quarter_table.i_addr_reg_c\,
I4 => \n_19_i_rtl.i_quarter_table.i_addr_reg_c\,
I5 => \n_17_i_rtl.i_quarter_table.i_addr_reg_c\,
I6 => \n_16_i_rtl.i_quarter_table.i_addr_reg_c\,
I7 => \n_15_i_rtl.i_quarter_table.i_addr_reg_c\,
I8 => \n_23_i_rtl.i_quarter_table.i_addr_reg_c\,
aclk => aclk,
\out\(8 downto 0) => cos_ls1(8 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_1\
port map (
I1 => \n_18_i_rtl.i_quarter_table.i_addr_reg_c\,
I2 => \n_30_i_rtl.i_quarter_table.i_addr_reg_c\,
I3 => \n_29_i_rtl.i_quarter_table.i_addr_reg_c\,
I4 => \n_28_i_rtl.i_quarter_table.i_addr_reg_c\,
I5 => \n_27_i_rtl.i_quarter_table.i_addr_reg_c\,
I6 => \n_26_i_rtl.i_quarter_table.i_addr_reg_c\,
I7 => \n_25_i_rtl.i_quarter_table.i_addr_reg_c\,
I8 => \n_24_i_rtl.i_quarter_table.i_addr_reg_c\,
O1 => \n_0_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O2 => \n_1_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O3 => \n_2_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O4 => \n_3_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O5 => \n_4_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O6 => \n_5_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O7 => \n_6_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
O8 => \n_7_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\,
aclk => aclk,
\out\(0) => cos_ls1(8),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_original_sin_ls\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized16_5\
port map (
I1 => \n_9_i_rtl.i_quarter_table.i_addr_reg_c\,
I2 => \n_8_i_rtl.i_quarter_table.i_addr_reg_c\,
I3 => \n_10_i_rtl.i_quarter_table.i_addr_reg_c\,
I4 => \n_11_i_rtl.i_quarter_table.i_addr_reg_c\,
I5 => \n_13_i_rtl.i_quarter_table.i_addr_reg_c\,
I6 => \n_31_i_rtl.i_quarter_table.i_addr_reg_c\,
I7 => \n_12_i_rtl.i_quarter_table.i_addr_reg_c\,
I8 => \n_14_i_rtl.i_quarter_table.i_addr_reg_c\,
I9(0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(0),
aclk => aclk,
\out\(8 downto 0) => sin_ls1(8 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_6\
port map (
I1 => \n_1_i_rtl.i_quarter_table.i_addr_reg_c\,
I2 => \n_2_i_rtl.i_quarter_table.i_addr_reg_c\,
I3 => \n_3_i_rtl.i_quarter_table.i_addr_reg_c\,
I4 => \n_4_i_rtl.i_quarter_table.i_addr_reg_c\,
I5 => \n_5_i_rtl.i_quarter_table.i_addr_reg_c\,
I6 => \n_6_i_rtl.i_quarter_table.i_addr_reg_c\,
I7 => \n_7_i_rtl.i_quarter_table.i_addr_reg_c\,
O1 => \n_0_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O2 => \n_1_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O3 => \n_2_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O4 => \n_3_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O5 => \n_4_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O6 => \n_5_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O7 => \n_6_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
O8 => \n_7_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\,
aclk => aclk,
invert_sin => invert_sin,
\out\(0) => sin_ls1(8),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(0),
Q => cos_addr(0),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(10),
Q => cos_addr(10),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(11),
Q => cos_addr(11),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(12),
Q => cos_addr(12),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(13),
Q => cos_addr(13),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(1),
Q => cos_addr(1),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(2),
Q => cos_addr(2),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(3),
Q => cos_addr(3),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(4),
Q => cos_addr(4),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(5),
Q => cos_addr(5),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(6),
Q => cos_addr(6),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(7),
Q => cos_addr(7),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(8),
Q => cos_addr(8),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_cos_addr(9),
Q => cos_addr(9),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(0),
Q => sin_addr(0),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(10),
Q => sin_addr(10),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(11),
Q => sin_addr(11),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(12),
Q => sin_addr(12),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(13),
Q => sin_addr(13),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(1),
Q => sin_addr(1),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(2),
Q => sin_addr(2),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(3),
Q => sin_addr(3),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(4),
Q => sin_addr(4),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(5),
Q => sin_addr(5),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(6),
Q => sin_addr(6),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(7),
Q => sin_addr(7),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(8),
Q => sin_addr(8),
R => \<const0>\
);
\i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => mod_sin_addr(9),
Q => sin_addr(9),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsdds_compiler_v6_0_core is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_phase_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
reg_s_phase_fifo_din : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
end ddsdds_compiler_v6_0_core;
architecture STRUCTURE of ddsdds_compiler_v6_0_core is
signal acc_phase_shaped : STD_LOGIC_VECTOR ( 15 downto 14 );
signal asyn_mod_sin_addr : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \n_16_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_17_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_18_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_19_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_20_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_21_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_22_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_23_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_24_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_25_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_26_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_27_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_28_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
signal \n_29_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC;
begin
\I_PHASEGEN.i_conventional_accum.i_accum\: entity work.ddsaccum
port map (
D(13 downto 0) => asyn_mod_sin_addr(13 downto 0),
I1(13) => \n_16_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(12) => \n_17_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(11) => \n_18_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(10) => \n_19_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(9) => \n_20_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(8) => \n_21_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(7) => \n_22_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(6) => \n_23_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(5) => \n_24_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(4) => \n_25_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(3) => \n_26_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(2) => \n_27_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(1) => \n_28_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(0) => \n_29_I_PHASEGEN.i_conventional_accum.i_accum\,
L(1 downto 0) => acc_phase_shaped(15 downto 14),
aclk => aclk,
reg_s_phase_fifo_din(15 downto 0) => reg_s_phase_fifo_din(15 downto 0),
s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\I_SINCOS.i_std_rom.i_rom\: entity work.\ddssin_cos__parameterized0\
port map (
D(13 downto 0) => asyn_mod_sin_addr(13 downto 0),
I1(13) => \n_16_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(12) => \n_17_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(11) => \n_18_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(10) => \n_19_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(9) => \n_20_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(8) => \n_21_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(7) => \n_22_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(6) => \n_23_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(5) => \n_24_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(4) => \n_25_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(3) => \n_26_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(2) => \n_27_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(1) => \n_28_I_PHASEGEN.i_conventional_accum.i_accum\,
I1(0) => \n_29_I_PHASEGEN.i_conventional_accum.i_accum\,
L(1 downto 0) => acc_phase_shaped(15 downto 14),
aclk => aclk,
m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_rdy.rdy_logic\: entity work.ddsdds_compiler_v6_0_rdy
port map (
aclk => aclk,
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsdds_compiler_v6_0_viv__parameterized0\ is
port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tready : out STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_phase_tlast : in STD_LOGIC;
s_axis_phase_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tvalid : in STD_LOGIC;
s_axis_config_tready : out STD_LOGIC;
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tlast : in STD_LOGIC;
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tready : in STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_data_tlast : out STD_LOGIC;
m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tvalid : out STD_LOGIC;
m_axis_phase_tready : in STD_LOGIC;
m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tlast : out STD_LOGIC;
m_axis_phase_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
event_pinc_invalid : out STD_LOGIC;
event_poff_invalid : out STD_LOGIC;
event_phase_in_invalid : out STD_LOGIC;
event_s_phase_tlast_missing : out STD_LOGIC;
event_s_phase_tlast_unexpected : out STD_LOGIC;
event_s_phase_chanid_incorrect : out STD_LOGIC;
event_s_config_tlast_missing : out STD_LOGIC;
event_s_config_tlast_unexpected : out STD_LOGIC;
debug_axi_pinc_in : out STD_LOGIC_VECTOR ( 15 downto 0 );
debug_axi_poff_in : out STD_LOGIC_VECTOR ( 15 downto 0 );
debug_axi_resync_in : out STD_LOGIC;
debug_axi_chan_in : out STD_LOGIC_VECTOR ( 0 to 0 );
debug_core_nd : out STD_LOGIC;
debug_phase : out STD_LOGIC_VECTOR ( 15 downto 0 );
debug_phase_nd : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "dds_compiler_v6_0_viv";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "zynq";
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 9;
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 16;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_LATENCY : integer;
attribute C_LATENCY of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 7;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 2;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 16;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 16;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_RESYNC : integer;
attribute C_RESYNC of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_POR_MODE : integer;
attribute C_POR_MODE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 16;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 32;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "yes";
end \ddsdds_compiler_v6_0_viv__parameterized0\;
architecture STRUCTURE of \ddsdds_compiler_v6_0_viv__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal reg_s_phase_fifo_din : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
debug_axi_chan_in(0) <= \<const0>\;
debug_axi_pinc_in(15) <= \<const0>\;
debug_axi_pinc_in(14) <= \<const0>\;
debug_axi_pinc_in(13) <= \<const0>\;
debug_axi_pinc_in(12) <= \<const0>\;
debug_axi_pinc_in(11) <= \<const0>\;
debug_axi_pinc_in(10) <= \<const0>\;
debug_axi_pinc_in(9) <= \<const0>\;
debug_axi_pinc_in(8) <= \<const0>\;
debug_axi_pinc_in(7) <= \<const0>\;
debug_axi_pinc_in(6) <= \<const0>\;
debug_axi_pinc_in(5) <= \<const0>\;
debug_axi_pinc_in(4) <= \<const0>\;
debug_axi_pinc_in(3) <= \<const0>\;
debug_axi_pinc_in(2) <= \<const0>\;
debug_axi_pinc_in(1) <= \<const0>\;
debug_axi_pinc_in(0) <= \<const0>\;
debug_axi_poff_in(15) <= \<const0>\;
debug_axi_poff_in(14) <= \<const0>\;
debug_axi_poff_in(13) <= \<const0>\;
debug_axi_poff_in(12) <= \<const0>\;
debug_axi_poff_in(11) <= \<const0>\;
debug_axi_poff_in(10) <= \<const0>\;
debug_axi_poff_in(9) <= \<const0>\;
debug_axi_poff_in(8) <= \<const0>\;
debug_axi_poff_in(7) <= \<const0>\;
debug_axi_poff_in(6) <= \<const0>\;
debug_axi_poff_in(5) <= \<const0>\;
debug_axi_poff_in(4) <= \<const0>\;
debug_axi_poff_in(3) <= \<const0>\;
debug_axi_poff_in(2) <= \<const0>\;
debug_axi_poff_in(1) <= \<const0>\;
debug_axi_poff_in(0) <= \<const0>\;
debug_axi_resync_in <= \<const0>\;
debug_core_nd <= \<const0>\;
debug_phase(15) <= \<const0>\;
debug_phase(14) <= \<const0>\;
debug_phase(13) <= \<const0>\;
debug_phase(12) <= \<const0>\;
debug_phase(11) <= \<const0>\;
debug_phase(10) <= \<const0>\;
debug_phase(9) <= \<const0>\;
debug_phase(8) <= \<const0>\;
debug_phase(7) <= \<const0>\;
debug_phase(6) <= \<const0>\;
debug_phase(5) <= \<const0>\;
debug_phase(4) <= \<const0>\;
debug_phase(3) <= \<const0>\;
debug_phase(2) <= \<const0>\;
debug_phase(1) <= \<const0>\;
debug_phase(0) <= \<const0>\;
debug_phase_nd <= \<const0>\;
event_phase_in_invalid <= \<const0>\;
event_pinc_invalid <= \<const0>\;
event_poff_invalid <= \<const0>\;
event_s_config_tlast_missing <= \<const0>\;
event_s_config_tlast_unexpected <= \<const0>\;
event_s_phase_chanid_incorrect <= \<const0>\;
event_s_phase_tlast_missing <= \<const0>\;
event_s_phase_tlast_unexpected <= \<const0>\;
m_axis_data_tlast <= \<const0>\;
m_axis_data_tuser(0) <= \<const0>\;
m_axis_phase_tdata(0) <= \<const0>\;
m_axis_phase_tlast <= \<const0>\;
m_axis_phase_tuser(0) <= \<const0>\;
m_axis_phase_tvalid <= \<const0>\;
s_axis_config_tready <= \<const0>\;
s_axis_phase_tready <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\has_s_phase.ce_i_delay\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized0\
port map (
aclk => aclk
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(0),
Q => reg_s_phase_fifo_din(0),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(10),
Q => reg_s_phase_fifo_din(10),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(11),
Q => reg_s_phase_fifo_din(11),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(12),
Q => reg_s_phase_fifo_din(12),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(13),
Q => reg_s_phase_fifo_din(13),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(14),
Q => reg_s_phase_fifo_din(14),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(15),
Q => reg_s_phase_fifo_din(15),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(1),
Q => reg_s_phase_fifo_din(1),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(2),
Q => reg_s_phase_fifo_din(2),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(3),
Q => reg_s_phase_fifo_din(3),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(4),
Q => reg_s_phase_fifo_din(4),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(5),
Q => reg_s_phase_fifo_din(5),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(6),
Q => reg_s_phase_fifo_din(6),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(7),
Q => reg_s_phase_fifo_din(7),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(8),
Q => reg_s_phase_fifo_din(8),
R => \<const0>\
);
\has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => s_axis_phase_tvalid,
D => s_axis_phase_tdata(9),
Q => reg_s_phase_fifo_din(9),
R => \<const0>\
);
i_dds: entity work.ddsdds_compiler_v6_0_core
port map (
aclk => aclk,
m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0),
reg_s_phase_fifo_din(15 downto 0) => reg_s_phase_fifo_din(15 downto 0),
s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_has_nd_rdy_pipe.channel_pipe\: entity work.ddsxbip_pipe_v3_0_viv_0
port map (
aclk => aclk,
s_axis_phase_tvalid => s_axis_phase_tvalid
);
\i_has_nd_rdy_pipe.valid_phase_read_del\: entity work.ddsxbip_pipe_v3_0_viv
port map (
aclk => aclk,
m_axis_data_tvalid => m_axis_data_tvalid,
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsdds_compiler_v6_0__parameterized0\ is
port (
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
aclk : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsdds_compiler_v6_0__parameterized0\ : entity is "dds_compiler_v6_0";
end \ddsdds_compiler_v6_0__parameterized0\;
architecture STRUCTURE of \ddsdds_compiler_v6_0__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal NLW_i_synth_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_core_nd_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_phase_nd_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_phase_in_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_pinc_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_poff_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_data_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_phase_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_config_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_phase_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_axi_chan_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_debug_axi_pinc_in_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_i_synth_debug_axi_poff_in_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_i_synth_debug_phase_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_i_synth_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_m_axis_phase_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_m_axis_phase_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of i_synth : label is 16;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of i_synth : label is 0;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of i_synth : label is 1;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of i_synth : label is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of i_synth : label is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of i_synth : label is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of i_synth : label is 0;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of i_synth : label is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of i_synth : label is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of i_synth : label is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of i_synth : label is 0;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of i_synth : label is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of i_synth : label is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of i_synth : label is 1;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of i_synth : label is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of i_synth : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of i_synth : label is 7;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of i_synth : label is 1;
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of i_synth : label is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of i_synth : label is 9;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of i_synth : label is 0;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of i_synth : label is 32;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of i_synth : label is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of i_synth : label is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of i_synth : label is 0;
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of i_synth : label is 0;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of i_synth : label is 2;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of i_synth : label is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of i_synth : label is 16;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of i_synth : label is 16;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of i_synth : label is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of i_synth : label is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE : integer;
attribute C_POR_MODE of i_synth : label is 0;
attribute C_RESYNC : integer;
attribute C_RESYNC of i_synth : label is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of i_synth : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of i_synth : label is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of i_synth : label is 16;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of i_synth : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of i_synth : label is "zynq";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of i_synth : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
i_synth: entity work.\ddsdds_compiler_v6_0_viv__parameterized0\
port map (
aclk => aclk,
aclken => \<const1>\,
aresetn => \<const1>\,
debug_axi_chan_in(0) => NLW_i_synth_debug_axi_chan_in_UNCONNECTED(0),
debug_axi_pinc_in(15 downto 0) => NLW_i_synth_debug_axi_pinc_in_UNCONNECTED(15 downto 0),
debug_axi_poff_in(15 downto 0) => NLW_i_synth_debug_axi_poff_in_UNCONNECTED(15 downto 0),
debug_axi_resync_in => NLW_i_synth_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => NLW_i_synth_debug_core_nd_UNCONNECTED,
debug_phase(15 downto 0) => NLW_i_synth_debug_phase_UNCONNECTED(15 downto 0),
debug_phase_nd => NLW_i_synth_debug_phase_nd_UNCONNECTED,
event_phase_in_invalid => NLW_i_synth_event_phase_in_invalid_UNCONNECTED,
event_pinc_invalid => NLW_i_synth_event_pinc_invalid_UNCONNECTED,
event_poff_invalid => NLW_i_synth_event_poff_invalid_UNCONNECTED,
event_s_config_tlast_missing => NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED,
event_s_config_tlast_unexpected => NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED,
event_s_phase_chanid_incorrect => NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED,
event_s_phase_tlast_missing => NLW_i_synth_event_s_phase_tlast_missing_UNCONNECTED,
event_s_phase_tlast_unexpected => NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED,
m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0),
m_axis_data_tlast => NLW_i_synth_m_axis_data_tlast_UNCONNECTED,
m_axis_data_tready => \<const0>\,
m_axis_data_tuser(0) => NLW_i_synth_m_axis_data_tuser_UNCONNECTED(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(0) => NLW_i_synth_m_axis_phase_tdata_UNCONNECTED(0),
m_axis_phase_tlast => NLW_i_synth_m_axis_phase_tlast_UNCONNECTED,
m_axis_phase_tready => \<const0>\,
m_axis_phase_tuser(0) => NLW_i_synth_m_axis_phase_tuser_UNCONNECTED(0),
m_axis_phase_tvalid => NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED,
s_axis_config_tdata(0) => \<const0>\,
s_axis_config_tlast => \<const0>\,
s_axis_config_tready => NLW_i_synth_s_axis_config_tready_UNCONNECTED,
s_axis_config_tvalid => \<const0>\,
s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0),
s_axis_phase_tlast => \<const0>\,
s_axis_phase_tready => NLW_i_synth_s_axis_phase_tready_UNCONNECTED,
s_axis_phase_tuser(0) => \<const0>\,
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity dds is
port (
aclk : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of dds : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of dds : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of dds : entity is "dds_compiler_v6_0,Vivado 2013.4";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of dds : entity is "dds,dds_compiler_v6_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of dds : entity is "dds,dds_compiler_v6_0,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dds_compiler,x_ipVersion=6.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,C_XDEVICEFAMILY=zynq,C_MODE_OF_OPERATION=0,C_MODULUS=9,C_ACCUMULATOR_WIDTH=16,C_CHANNELS=1,C_HAS_PHASE_OUT=0,C_HAS_PHASEGEN=1,C_HAS_SINCOS=1,C_LATENCY=7,C_MEM_TYPE=1,C_NEGATIVE_COSINE=0,C_NEGATIVE_SINE=0,C_NOISE_SHAPING=0,C_OUTPUTS_REQUIRED=2,C_OUTPUT_FORM=0,C_OUTPUT_WIDTH=16,C_PHASE_ANGLE_WIDTH=16,C_PHASE_INCREMENT=3,C_PHASE_INCREMENT_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_RESYNC=0,C_PHASE_OFFSET=0,C_PHASE_OFFSET_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_OPTIMISE_GOAL=0,C_USE_DSP48=0,C_POR_MODE=0,C_AMPLITUDE=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_HAS_TLAST=0,C_HAS_TREADY=0,C_HAS_S_PHASE=1,C_S_PHASE_TDATA_WIDTH=16,C_S_PHASE_HAS_TUSER=0,C_S_PHASE_TUSER_WIDTH=1,C_HAS_S_CONFIG=0,C_S_CONFIG_SYNC_MODE=0,C_S_CONFIG_TDATA_WIDTH=1,C_HAS_M_DATA=1,C_M_DATA_TDATA_WIDTH=32,C_M_DATA_HAS_TUSER=0,C_M_DATA_TUSER_WIDTH=1,C_HAS_M_PHASE=0,C_M_PHASE_TDATA_WIDTH=1,C_M_PHASE_HAS_TUSER=0,C_M_PHASE_TUSER_WIDTH=1,C_DEBUG_INTERFACE=0,C_CHAN_WIDTH=1}";
end dds;
architecture STRUCTURE of dds is
begin
U0: entity work.\ddsdds_compiler_v6_0__parameterized0\
port map (
aclk => aclk,
m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0),
m_axis_data_tvalid => m_axis_data_tvalid,
s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_nco_sync_sync
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for a synchronized numeric controlled
-- oscillator
--
-- Synchronization of two oscillators
-- Whenever the master's phase ends, reset slave's phase.
-- Slave's frequency usually higher and not dividable by
-- master's frequency
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_nco_sync is
generic(
SND_COMP_CLK_FREQ : integer := 100_000_000;
SND_COMP_NCO_SYNC_TPYE : integer := 2
);
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_nco_sync;
architecture Behavioral of hwt_nco_sync is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
component nco_sync is
generic(
FPGA_FREQUENCY : integer := 100_000_000;
WAVEFORM : WAVEFORM_TYPE := SAW -- sync nco eignet sich eigentlich nur für square oder saw
);
Port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
master_phase_offset : in signed(31 downto 0);
master_phase_incr : in signed(31 downto 0);
slave_phase_offset : in signed(31 downto 0);
slave_phase_incr : in signed(31 downto 0);
soundout : out signed(31 downto 0)
);
end component nco_sync;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT_PHASE_OFFSET, STATE_REFRESH_INPUT_PHASE_INCR, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 1024;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 10;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_nco_sync : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_nco_sync : std_logic_vector(0 to 31); -- nco_sync to local ram
signal i_RAMData_nco_sync : std_logic_vector(0 to 31); -- local ram to nco_sync
signal o_RAMWE_nco_sync : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(C_MAX_SAMPLE_COUNT, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal nco_sync_ce : std_logic; -- nco_sync clock enable (like a start/stop signal)
signal master_offset_addr : std_logic_vector(31 downto 0);
signal master_incr_addr : std_logic_vector(31 downto 0);
signal slave_offset_addr : std_logic_vector(31 downto 0);
signal slave_incr_addr : std_logic_vector(31 downto 0);
signal master_phase_offset : std_logic_vector(31 downto 0);
signal master_phase_incr : std_logic_vector(31 downto 0);
signal slave_phase_offset : std_logic_vector(31 downto 0);
signal slave_phase_incr : std_logic_vector(31 downto 0);
signal nco_sync_data : signed(31 downto 0);
signal state_inner_process : std_logic;
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant nco_sync_START : std_logic_vector(31 downto 0) := x"0000000F";
constant nco_sync_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
o_RAMData_nco_sync <= std_logic_vector(nco_sync_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stufff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
nco_sync_inst : nco_sync
generic map(
FPGA_FREQUENCY => SND_COMP_CLK_FREQ,
WAVEFORM => WAVEFORM_TYPE'val(SND_COMP_NCO_TPYE)
)
port map(
clk => clk,
rst => rst,
ce => nco_sync_ce,
master_phase_offset => signed(master_phase_offset),
master_phase_incr => signed(master_phase_incr),
slave_phase_offset => signed(slave_phase_offset),
slave_phase_incr => signed(slave_phase_incr),
soundout => nco_sync_data
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_nco_sync = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_nco_sync))) := o_RAMData_nco_sync;
--else -- else not needed, because nco_sync is not consuming any samples
-- i_RAMData_nco_sync <= local_ram(conv_integer(unsigned(o_RAMAddr_nco_sync)));
end if;
end if;
end process;
NCO_SYNC_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
osif_ctrl_signal <= (others => '0');
nco_sync_ce <= '0';
o_RAMWE_nco_sync <= '0';
state_inner_process <= '0';
done := False;
elsif rising_edge(clk) then
nco_sync_ce <= '0';
o_RAMWE_nco_sync <= '0';
osif_ctrl_signal <= ( others => '0');
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
-- Initialize your signals
master_offset_addr <= snd_comp_header.opt_arg_addr;
master_incr_addr <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 4);
master_offset_addr <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 8);
slave_incr_addr <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 12);
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = nco_sync_START then
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
state <= STATE_REFRESH_INPUT_PHASE_OFFSET;
elsif osif_ctrl_signal = nco_sync_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_MASTER_INPUT_PHASE_OFFSET =>
memif_read_word(i_memif, o_memif, master_offset_addr, master_phase_offset, done);
if done then
state <= STATE_REFRESH_INPUT_PHASE_INCR;
end if;
when STATE_REFRESH_INPUT_MASTER_PHASE_INCR =>
memif_read_word(i_memif, o_memif, master_incr_addr, master_phase_incr, done);
if done then
state <= STATE_REFRESH_MASTER_INPUT_PHASE_OFFSET;
end if;
when STATE_REFRESH_MASTER_INPUT_PHASE_OFFSET =>
memif_read_word(i_memif, o_memif, slave_offset_addr, slave_phase_offset, done);
if done then
state <= STATE_REFRESH_INPUT_SLAVE_PHASE_INCR;
end if;
when STATE_REFRESH_INPUT_SLAVE_PHASE_INCR =>
memif_read_word(i_memif, o_memif, slave_incr_addr, slave_phase_incr, done);
if done then
state <= STATE_PROCESS;
end if;
when STATE_PROCESS =>
if sample_count > 0 then
case state_inner_process is
when '0' =>
o_RAMWE_nco_sync <= '1';
nco_sync_ce <= '1'; -- ein takt früher
state_inner_process <= '1';
when '1' =>
o_RAMAddr_nco_sync <= std_logic_vector(unsigned(o_RAMAddr_nco_sync) + 1);
sample_count <= sample_count - 1;
state_inner_process <= '0';
end case;
else
-- Samples have been generated
o_RAMAddr_nco_sync <= (others => '0');
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_ADDR std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1819.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01819ent IS
type small_int is range 0 to 7;
type byte is range 0 to 3;
END c07s01b00x00p08n01i01819ent;
ARCHITECTURE c07s01b00x00p08n01i01819arch OF c07s01b00x00p08n01i01819ent IS
function test return small_int is
variable tmp : small_int := 0;
begin
tmp := small_int; -- type name illegal here
return tmp;
end test;
signal s_int : small_int := 0;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= test after 5 ns;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01819 - Type names are not permitted as primaries in a variable assignment statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01819arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1819.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01819ent IS
type small_int is range 0 to 7;
type byte is range 0 to 3;
END c07s01b00x00p08n01i01819ent;
ARCHITECTURE c07s01b00x00p08n01i01819arch OF c07s01b00x00p08n01i01819ent IS
function test return small_int is
variable tmp : small_int := 0;
begin
tmp := small_int; -- type name illegal here
return tmp;
end test;
signal s_int : small_int := 0;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= test after 5 ns;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01819 - Type names are not permitted as primaries in a variable assignment statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01819arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1819.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01819ent IS
type small_int is range 0 to 7;
type byte is range 0 to 3;
END c07s01b00x00p08n01i01819ent;
ARCHITECTURE c07s01b00x00p08n01i01819arch OF c07s01b00x00p08n01i01819ent IS
function test return small_int is
variable tmp : small_int := 0;
begin
tmp := small_int; -- type name illegal here
return tmp;
end test;
signal s_int : small_int := 0;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= test after 5 ns;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01819 - Type names are not permitted as primaries in a variable assignment statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01819arch;
|
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Albert Fazakas, Elod Gyorgy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 14:50:40 03/17/2014
-- Design Name:
-- Module Name: TempDisplay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TempDisplay is
generic(
X_TMP_COL_WIDTH : natural := 50; -- = SZ_TH_WIDTH - width of a TEMP column
Y_TMP_COL_HEIGHT : natural := 472; -- = SZ_TH_HEIGHT - height of a TEMP column
X_TMP_H_LOC : natural := 1050; -- X Location of the TEMP Column
Y_TMP_V_LOC : natural := 80; -- Y Location of the TEMP Column
INPUT_DATA_WIDTH : natural := 12; -- Data width is 13 for the ADT7420 Temperature Sensor and
-- 12 for the XADC temperature data and the Accelerometer Temperature Sensor
TMP_TYPE : string := "XADC" -- Either "XADC" or "TEMP_ACC"
);
Port ( CLK_I : in STD_LOGIC;
TEMP_IN : in STD_LOGIC_VECTOR (INPUT_DATA_WIDTH - 1 downto 0);
H_COUNT_I : in STD_LOGIC_VECTOR (11 downto 0);
V_COUNT_I : in STD_LOGIC_VECTOR (11 downto 0);
-- Temperature Red, Green and Blue signals
TEMP_R_OUT : out STD_LOGIC_VECTOR (3 downto 0);
TEMP_G_OUT : out STD_LOGIC_VECTOR (3 downto 0);
TEMP_B_OUT : out STD_LOGIC_VECTOR (3 downto 0)
);
end TempDisplay;
architecture Behavioral of TempDisplay is
-- Used as starting point for the Temperature level size
-- The Temperature level size is according to the value of the temperature displayed
constant TEMP_OFFSET : std_logic_vector (11 downto 0) := "001000100110"; --550
constant TEMP_BOTTOM : natural := Y_TMP_V_LOC + Y_TMP_COL_HEIGHT + 1;
-- Maximum temperature
constant TEMP_MAX : std_logic_vector (23 downto 0) := X"000500"; -- 80C * 16
-- Convert Celsius to pixels such as 0C = 0 pixels, 80C = 480pixels
constant CELSIUS_TO_PIXELS : std_logic_vector(2 downto 0) := "110"; --6 = 480/(80-0)
-- Scale incoming XADC temperature data, according to the XADC datasheet
constant XADC_TMP_SCALE : std_logic_vector(17 downto 0) := "111110111" & "111110011"; --503.975 (18bit)
-- Convert Kelvin to Celsius
constant XADC_TMP_OFFSET : std_logic_vector(30 downto 0) := conv_std_logic_vector(integer(round(273.15)*4096.0), 31);
-- Converted and scaled temperature value
signal temp_value : std_logic_vector(9 downto 0);
-- Synchronize incoming temperature to the clock
signal temp_sync0, temp_sync : std_logic_vector(TEMP_IN'range);
-- signal storing the scaled XADC temperature data
signal temp_xad_scaled : std_logic_vector(temp_sync'length+XADC_TMP_SCALE'length-1 downto 0); --12bit*18bit=30bit
-- signal storing the offseted XADC temperature data
signal temp_xad_offset : std_logic_vector(XADC_TMP_OFFSET'range); --31bit
-- signal storing XADC temperature data converted to Celsius
signal temp_xad_celsius : std_logic_vector(temp_xad_offset'length-8-1 downto 0); --23bit
-- Signal storing the FPGA temperature limited to between 0C and 80C * 16
signal temp_xad_capped : std_logic_vector(temp_xad_celsius'high-1 downto 0); --no sign bit
-- The temperature scaled to pixels
signal temp_xad_px_scaled : std_logic_vector(temp_xad_capped'high+CELSIUS_TO_PIXELS'high+1 downto temp_xad_capped'low);
-- Signal storing the Temp Sensor or Accelerometer temperature limited to between 0C and 80C * 16
signal temp_capped : std_logic_vector(temp_sync'high-1 downto temp_sync'low);
-- Signal storing the Temp Sensor or Accelerometer temperature scaled to pixels: 0 = 0C, 480 = 80C * 16
signal temp_scaled : std_logic_vector(temp_capped'high+CELSIUS_TO_PIXELS'high+1 downto temp_capped'low);
-- Temp Column green and red color components
signal temp_color_red : std_logic_vector(3 downto 0);
signal temp_color_green : std_logic_vector(3 downto 0);
-- Temp Column red, green and blue signals
signal temp_red : std_logic_vector (3 downto 0);
signal temp_green : std_logic_vector (3 downto 0);
signal temp_blue : std_logic_vector (3 downto 0);
begin
-- The XADC temperature data will have to scaled with 503.975,
-- then transformed from Kelvin to Celsius
-- Then limit and scale it to pixels: 0 = 0C, 480 = 80C * 16, and multiply by 0.0625 (i.e. divide by 16)
XADC:
if TMP_TYPE = "XADC" generate
begin
process(CLK_I)
begin
if CLK_I'EVENT and CLK_I = '1' then
temp_sync0 <= TEMP_IN; --synchronize with pxl_clk domain
temp_sync <= temp_sync0;
--30b 12b 18b
temp_xad_scaled <= temp_sync * XADC_TMP_SCALE; -- ADC * 503.975 (fixed-point; decimal point at 9b)
temp_xad_offset <= '0' & temp_xad_scaled(29 downto 9) - XADC_TMP_OFFSET; -- ADC * 503.975 - 273.15 * 4096
temp_xad_celsius <= temp_xad_offset(temp_xad_offset'high downto 8); -- (ADC * 503.975 - 273.15) / 256; 1LSB=0.625C
if (temp_xad_celsius(temp_xad_celsius'high) = '1') then --if negative, cap to 0
temp_xad_capped <= (others => '0');
elsif (temp_xad_celsius(temp_xad_celsius'high-1 downto 0) > TEMP_MAX) then --if too big, cap to maximum scale /0.0625
temp_xad_capped <= TEMP_MAX(temp_xad_capped'range);
else
temp_xad_capped <= temp_xad_celsius(temp_xad_celsius'high-1 downto 0); --get rid of the sign bit
end if;
temp_xad_px_scaled <= temp_xad_capped * CELSIUS_TO_PIXELS; --scale to pixels
end if;
end process;
temp_value <= temp_xad_px_scaled(13 downto 4); -- * 0.0625 (1/2^4)
end generate;
-- The ADT7420 temperature sensor data and the ADXL362 accelerometer temperature data
-- will have to be limited and scaled to pixels: 0 = 0C, 480 = 80C * 16,
-- then multiply by 0.0625 (i.e. divide by 16)
-- Note that the accelerometer temperature data in fact is 0.065C /LSB. Multiplying it by 0.0625
-- at 80C the error will be about 3..4C
TEMP_ACC:
if TMP_TYPE = "TEMP_ACC" generate
process(CLK_I)
begin
if CLK_I'EVENT and CLK_I = '1' then
temp_sync0 <= TEMP_IN; --synchronize with pxl_clk domain
temp_sync <= temp_sync0;
if (temp_sync(temp_sync'high) = '1') then --if negative, cap to 0
temp_capped <= (others => '0');
elsif (temp_sync(temp_sync'high-1 downto 0) > TEMP_MAX) then -- if too big, cap to maximum scale /0.0625
temp_capped <= TEMP_MAX(temp_capped'range);
else
temp_capped <= temp_sync(temp_sync'high-1 downto 0); --get rid of the sign bit
end if;
temp_scaled <= temp_capped * CELSIUS_TO_PIXELS; --scale to pixels
end if;
end process;
temp_value <= temp_scaled(13 downto 4); -- * 0.0625 (1/2^4)
end generate;
-- Temperature Color Decode - As temperature is higher, the color turns from green to red
temp_color_red <= x"0" when temp_value < 16 else
x"1" when temp_value < 32 else
x"2" when temp_value < 48 else
x"3" when temp_value < 64 else
x"4" when temp_value < 80 else
x"5" when temp_value < 96 else
x"6" when temp_value < 112 else
x"7" when temp_value < 128 else
x"8" when temp_value < 144 else
x"9" when temp_value < 160 else
x"A" when temp_value < 176 else
x"B" when temp_value < 192 else
x"C" when temp_value < 208 else
x"D" when temp_value < 224 else
x"E" when temp_value < 240 else
x"F";
temp_color_green <= x"F" when temp_value < 256 else
x"E" when temp_value < 272 else
x"D" when temp_value < 288 else
x"C" when temp_value < 304 else
x"B" when temp_value < 320 else
x"A" when temp_value < 336 else
x"9" when temp_value < 352 else
x"8" when temp_value < 368 else
x"7" when temp_value < 384 else
x"6" when temp_value < 400 else
x"5" when temp_value < 416 else
x"4" when temp_value < 432 else
x"3" when temp_value < 448 else
x"2" when temp_value < 464 else
x"1" when temp_value < 480 else
x"0";
-- Red, Green and Blue Signals for the Temperature Column
temp_red <= temp_color_red when (H_COUNT_I > X_TMP_H_LOC and H_COUNT_I < X_TMP_H_LOC + X_TMP_COL_WIDTH)
and (V_COUNT_I > (TEMP_OFFSET - temp_value) and V_COUNT_I < TEMP_BOTTOM)
else x"F";
temp_green <= temp_color_green when (H_COUNT_I > X_TMP_H_LOC and H_COUNT_I < X_TMP_H_LOC + X_TMP_COL_WIDTH)
and (V_COUNT_I > (TEMP_OFFSET - temp_value) and V_COUNT_I < TEMP_BOTTOM)
else x"F";
-- The Temperature Colum color will be either a green-red combination (from green to orange, then red), or white
temp_blue <= x"0" when (H_COUNT_I > X_TMP_H_LOC and H_COUNT_I < X_TMP_H_LOC + X_TMP_COL_WIDTH)
and (V_COUNT_I > (TEMP_OFFSET - temp_value) and V_COUNT_I < TEMP_BOTTOM)
else x"F";
-- Assign Outputs
TEMP_R_OUT <= temp_red;
TEMP_G_OUT <= temp_green;
TEMP_B_OUT <= temp_blue;
end Behavioral;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex4;
constant CFG_MEMTECH : integer := virtex4;
constant CFG_PADTECH : integer := virtex4;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex4;
constant CFG_CLKMUL : integer := (13);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#00002F#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (64);
constant CFG_DDRSP_RSKEW : integer := (0);
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0FFFE#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AvalonSTToI2S is
generic (
gDataWidth : natural := 24; -- Avalon ST interface Datawidth
gDataWidthLen : natural := 5 -- Number of bits to represent gDataWidth
);
port (
-- clk and reset
iClk : in std_logic; -- clk
inReset : in std_logic; -- low active reset
-- audio codec interface
iLRC : in std_logic;
iBCLK : in std_logic;
oDAT : out std_logic;
-- Avalon ST sink left and right channel
iLeftData : in std_logic_vector(gDataWidth-1 downto 0); -- data
iLeftValid : in std_logic; -- valid
iRightData : in std_logic_vector(gDataWidth-1 downto 0); -- data
iRightValid : in std_logic -- valid
);
end entity AvalonSTToI2S;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 1;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
entity wave6 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of wave6 is
type pair is record
a, b : integer;
end record;
type rec is record
x : integer;
y : std_logic_vector;
z : pair;
end record;
subtype rec_c is rec(y(1 to 3));
signal r : rec_c;
begin
main: process is
begin
wait for 1 ns;
r.y <= "101";
wait for 1 ns;
r.z.b <= 5;
r.z.a <= 6;
wait for 1 ns;
r.x <= 2;
r.z.a <= 1;
r.y <= "010";
wait;
end process;
end architecture;
|
package body fifo_pkg is
end package body;
package body fifo_pkg is --comment
end package body;
|
library verilog;
use verilog.vl_types.all;
entity altera_merlin_master_translator is
generic(
AV_ADDRESS_W : integer := 32;
AV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
USE_BURSTCOUNT : integer := 1;
USE_BEGINBURSTTRANSFER: integer := 0;
USE_BEGINTRANSFER: integer := 0;
USE_CHIPSELECT : integer := 0;
USE_READ : integer := 1;
USE_READDATAVALID: integer := 1;
USE_WRITE : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_WRITERESPONSE: integer := 0;
USE_READRESPONSE: integer := 0;
AV_REGISTERINCOMINGSIGNALS: integer := 0;
AV_SYMBOLS_PER_WORD: integer := 4;
AV_ADDRESS_SYMBOLS: integer := 0;
AV_CONSTANT_BURST_BEHAVIOR: integer := 1;
AV_BURSTCOUNT_SYMBOLS: integer := 0;
AV_LINEWRAPBURSTS: integer := 0;
UAV_ADDRESS_W : integer := 38;
UAV_BURSTCOUNT_W: integer := 10;
UAV_CONSTANT_BURST_BEHAVIOR: integer := 0
);
port(
clk : in vl_logic;
reset : in vl_logic;
uav_write : out vl_logic;
uav_read : out vl_logic;
uav_address : out vl_logic_vector;
uav_burstcount : out vl_logic_vector;
uav_byteenable : out vl_logic_vector;
uav_writedata : out vl_logic_vector;
uav_lock : out vl_logic;
uav_debugaccess : out vl_logic;
uav_clken : out vl_logic;
uav_readdata : in vl_logic_vector;
uav_readdatavalid: in vl_logic;
uav_waitrequest : in vl_logic;
uav_response : in vl_logic_vector(1 downto 0);
uav_writeresponserequest: out vl_logic;
uav_writeresponsevalid: in vl_logic;
av_write : in vl_logic;
av_read : in vl_logic;
av_address : in vl_logic_vector;
av_byteenable : in vl_logic_vector;
av_burstcount : in vl_logic_vector;
av_writedata : in vl_logic_vector;
av_begintransfer: in vl_logic;
av_beginbursttransfer: in vl_logic;
av_lock : in vl_logic;
av_chipselect : in vl_logic;
av_debugaccess : in vl_logic;
av_clken : in vl_logic;
av_readdata : out vl_logic_vector;
av_readdatavalid: out vl_logic;
av_waitrequest : out vl_logic;
av_response : out vl_logic_vector(1 downto 0);
av_writeresponserequest: in vl_logic;
av_writeresponsevalid: out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of AV_ADDRESS_W : constant is 1;
attribute mti_svvh_generic_type of AV_DATA_W : constant is 1;
attribute mti_svvh_generic_type of AV_BURSTCOUNT_W : constant is 1;
attribute mti_svvh_generic_type of AV_BYTEENABLE_W : constant is 1;
attribute mti_svvh_generic_type of USE_BURSTCOUNT : constant is 1;
attribute mti_svvh_generic_type of USE_BEGINBURSTTRANSFER : constant is 1;
attribute mti_svvh_generic_type of USE_BEGINTRANSFER : constant is 1;
attribute mti_svvh_generic_type of USE_CHIPSELECT : constant is 1;
attribute mti_svvh_generic_type of USE_READ : constant is 1;
attribute mti_svvh_generic_type of USE_READDATAVALID : constant is 1;
attribute mti_svvh_generic_type of USE_WRITE : constant is 1;
attribute mti_svvh_generic_type of USE_WAITREQUEST : constant is 1;
attribute mti_svvh_generic_type of USE_WRITERESPONSE : constant is 1;
attribute mti_svvh_generic_type of USE_READRESPONSE : constant is 1;
attribute mti_svvh_generic_type of AV_REGISTERINCOMINGSIGNALS : constant is 1;
attribute mti_svvh_generic_type of AV_SYMBOLS_PER_WORD : constant is 1;
attribute mti_svvh_generic_type of AV_ADDRESS_SYMBOLS : constant is 1;
attribute mti_svvh_generic_type of AV_CONSTANT_BURST_BEHAVIOR : constant is 1;
attribute mti_svvh_generic_type of AV_BURSTCOUNT_SYMBOLS : constant is 1;
attribute mti_svvh_generic_type of AV_LINEWRAPBURSTS : constant is 1;
attribute mti_svvh_generic_type of UAV_ADDRESS_W : constant is 1;
attribute mti_svvh_generic_type of UAV_BURSTCOUNT_W : constant is 1;
attribute mti_svvh_generic_type of UAV_CONSTANT_BURST_BEHAVIOR : constant is 1;
end altera_merlin_master_translator;
|
--**************************************************************************
-- $Id$
--
-- hwt_build_histo.vhd: ReconOS package
--
-- This hardware thread creates a histogram over a sequence of bytes. The
-- input is received in a sequence of blocks via a posix message queue.
-- After receiving the last block, the histogram is send to the outgoing
-- message queue.
--
-- Author : Andreas Agne <agne@upb.de>
-- Created: 1.8.2008
--*************************************************************************/
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
entity hwt_build_histo is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector( C_BURST_AWIDTH-1 downto 0);
o_RAMData : out std_logic_vector( C_BURST_DWIDTH-1 downto 0);
i_RAMData : in std_logic_vector( C_BURST_DWIDTH-1 downto 0);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end entity;
architecture Behavioral of hwt_build_histo is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
constant C_MQ_IN : std_logic_vector(31 downto 0) := X"00000000";
constant C_MQ_OUT : std_logic_vector(31 downto 0) := X"00000001";
-- ReconOS state machine
type t_state is (
STATE_INIT,
STATE_CLEAR_HISTOGRAM,
STATE_RECV_NUM_BLOCKS,
STATE_SAVE_NUM_BLOCKS,
STATE_LOOP,
STATE_RECV_BLOCK,
STATE_UPDATE_HISTOGRAM,
STATE_COPY_HISTOGRAM,
STATE_SEND_RESULT,
STATE_FINAL);
signal state : t_state;
signal block_size : std_logic_vector(31 downto 0); -- size of the last received block
-- update histogram
signal update_histo_en : std_logic; -- handshake signal
signal update_histo_done : std_logic; -- handshake signal
signal update_histo_addr : std_logic_vector(C_BURST_AWIDTH-1 downto 0); -- burst ram addr
signal update_histo_bucket : std_logic_vector(7 downto 0); -- histogram addr
-- copy histogram
signal copy_histo_en : std_logic; -- handshake signal
signal copy_histo_done : std_logic; -- handshake signal
signal copy_histo_addr : std_logic_vector(C_BURST_AWIDTH-1 downto 0); -- burst ram addr
signal copy_histo_bucket : std_logic_vector(7 downto 0); -- histogram addr
-- clear histogram
signal clear_histo_en : std_logic; -- handshake signal
signal clear_histo_done : std_logic; -- handshake signal
signal clear_histo_bucket : std_logic_vector(7 downto 0); -- histogram addr
-- histogram
type t_ram is array (255 downto 0) of std_logic_vector(31 downto 0);
signal histo_ram : t_ram; -- histogram memory
signal histo_bucket : std_logic_vector(7 downto 0); -- current histogram bucket
signal histo_inc : std_logic; -- enables incrementing
signal histo_clear : std_logic; -- enables setting to zero
signal histo_value : std_logic_vector(31 downto 0); -- value of current bucket
signal histo_value_max : std_logic_vector(31 downto 0);
signal histo_value16 : std_logic_vector(15 downto 0);
begin
-- connect burst-ram to clk:
o_RAMClk <= clk;
-- histogram memory is basically a single port ram with
-- asynchronous read. the current bucket is incremented each
-- clock cycle when histo_inc is high, or set to zero when
-- histo_clear is high.
histo_value <= histo_ram(CONV_INTEGER(histo_bucket));
process(clk, reset)
variable tmp : std_logic_vector(31 downto 0);
begin
if reset = '1' then
tmp := (others => '0');
histo_value_max <= (others => '0');
elsif rising_edge(clk) then
if histo_inc = '1' then
if tmp > histo_value_max then
histo_value_max <= tmp;
end if;
tmp := histo_value + 1;
histo_ram(CONV_INTEGER(histo_bucket)) <= tmp;
elsif histo_clear = '1' then
histo_ram(CONV_INTEGER(histo_bucket)) <= (others => '0');
tmp := (others => '0');
histo_value_max <= (others => '0');
end if;
end if;
end process;
process(histo_value, histo_value_max)
variable max_bit : natural range 15 to 31;
begin
max_bit := 15;
for i in 16 to 31 loop
if histo_value_max(i) = '1' then
max_bit := i;
end if;
end loop;
histo_value16 <= histo_value(max_bit downto max_bit - 15);
end process;
-- signals and processes related to updating the histogram from
-- burst-ram data
update_histogramm : process(clk, reset, update_histo_en)
variable step : natural range 0 to 7;
begin
if reset = '1' or update_histo_en = '0' then
step := 0;
histo_inc <= '0';
update_histo_addr <= (others => '0');
update_histo_done <= '0';
update_histo_bucket <= (others => '0');
elsif rising_edge(clk) then
case step is
when 0 => -- set burst ram address to 0
update_histo_addr <= (others => '0');
step := step + 1;
when 1 => -- wait until address is valid
step := step + 1;
when 2 => -- turn on histogram incrementing, first byte
histo_inc <= '1';
update_histo_bucket <= i_ramdata(7 downto 0);
step := step + 1;
when 3 => -- second byte
update_histo_bucket <= i_ramdata(15 downto 8);
step := step + 1;
when 4 => -- load next word from burst ram, third byte
update_histo_bucket <= i_ramdata(23 downto 16);
if update_histo_addr + 1 < block_size(31 downto 2) then
update_histo_addr <= update_histo_addr + 1;
step := step + 1;
else
step := 6;
end if;
when 5 => -- last byte in word, continue
update_histo_bucket <= i_ramdata(31 downto 24);
step := 2;
when 6 => -- last byte in word, end of block
update_histo_bucket <= i_ramdata(31 downto 24);
step := step + 1;
when 7 => -- turn off histogram incrementing, set handshake signal
histo_inc <= '0';
update_histo_done <= '1';
end case;
end if;
end process;
-- signals and processes related to copying the histogram to
-- burst-ram
copy_histogram : process(clk, reset, copy_histo_en)
variable step : natural range 0 to 5;
begin
if reset = '1' or copy_histo_en = '0' then
copy_histo_addr <= (others => '0');
copy_histo_bucket <= (others => '0');
copy_histo_done <= '0';
o_ramwe <= '0';
step := 0;
elsif rising_edge(clk) then
case step is
when 0 => -- set histogram and burst ram addresses to 0
copy_histo_addr <= (others => '0');
copy_histo_bucket <= (others => '0');
step := step + 1;
when 1 =>
o_ramdata(31 downto 16) <= histo_value16;
copy_histo_bucket <= copy_histo_bucket + 1;
step := step + 1;
when 2 => -- copy first word
copy_histo_addr <= (others => '0');
copy_histo_bucket <= copy_histo_bucket + 1;
o_ramwe <= '1';
o_ramdata(15 downto 0) <= histo_value16;
step := step + 1;
when 3 =>
o_ramdata(31 downto 16) <= histo_value16;
copy_histo_addr <= copy_histo_addr + 1;
copy_histo_bucket <= copy_histo_bucket + 1;
step := step + 1;
when 4 => -- copy remaining histogram buckets to burst ram
copy_histo_bucket <= copy_histo_bucket + 1;
o_ramwe <= '1';
o_ramdata(15 downto 0) <= histo_value16;
if copy_histo_addr >= 127 then
step := step + 1;
else
step := 3;
end if;
when 5 => -- all buckets copied -> set handshake signal
copy_histo_done <= '1';
o_ramwe <= '0';
end case;
end if;
end process;
-- signals and processes related to clearing the histogram
clear_histogram : process(clk, reset, clear_histo_en)
variable step : natural range 0 to 2;
begin
if reset = '1' or clear_histo_en = '0' then
step := 0;
histo_clear <= '0';
clear_histo_bucket <= (others => '0');
clear_histo_done <= '0';
elsif rising_edge(clk) then
case step is
when 0 => -- enable bucket zeroing
clear_histo_bucket <= (others => '0');
histo_clear <= '1';
step := step + 1;
when 1 => -- visit every bucket
clear_histo_bucket <= clear_histo_bucket + 1;
if clear_histo_bucket = 255 then
step := step + 1;
end if;
when 2 => -- set handshake signal
histo_clear <= '0';
clear_histo_done <= '1';
end case;
end if;
end process;
-- histogram ram mux
process(update_histo_en, copy_histo_en, clear_histo_en, update_histo_addr, update_histo_bucket,
copy_histo_addr, copy_histo_bucket, clear_histo_bucket)
variable addr : std_logic_vector(C_BURST_AWIDTH - 1 downto 0);
variable bucket : std_logic_vector(7 downto 0);
begin
if update_histo_en = '1' then
addr := update_histo_addr;
bucket := update_histo_bucket;
elsif copy_histo_en = '1' then
addr := copy_histo_addr;
bucket := copy_histo_bucket;
elsif clear_histo_en = '1' then
addr := (others => '0');
bucket := clear_histo_bucket;
else
addr := (others => '0');
bucket := (others => '0');
end if;
o_RAMAddr <= addr(C_BURST_AWIDTH - 1 downto 1) & not addr(0);
histo_bucket <= bucket;
end process;
-- the os interaction state machine performs the following sequential program:
--
-- set all histogram buckets to 0
-- receive the numer of blocks to process
-- for each block:
-- receive block
-- update histogram
-- copy histogram to burst ram
-- send histogram
--
state_proc: process( clk, reset )
variable done : boolean;
variable success : boolean;
variable num_blocks : std_logic_vector(31 downto 0);
variable len : std_logic_vector(31 downto 0);
begin
if reset = '1' then
reconos_reset( o_osif, i_osif );
state <= STATE_INIT;
done := false;
success := false;
num_blocks := (others => '0');
block_size <= (others => '0');
len := (others => '0');
elsif rising_edge( clk ) then
reconos_begin( o_osif, i_osif );
if reconos_ready( i_osif ) then
case state is
when STATE_INIT =>
clear_histo_en <= '1';
state <= STATE_CLEAR_HISTOGRAM;
--reconos_get_init_data(done, o_osif, i_osif, offset);
--if done then state <= STATE_FILL; end if;
when STATE_CLEAR_HISTOGRAM =>
if clear_histo_done = '1' then
clear_histo_en <= '0';
state <= STATE_RECV_NUM_BLOCKS;
end if;
when STATE_RECV_NUM_BLOCKS =>
reconos_mq_receive(done, success, o_osif, i_osif, C_MQ_IN, X"00000000", len);
if done then
state <= STATE_SAVE_NUM_BLOCKS;
end if;
when STATE_SAVE_NUM_BLOCKS =>
num_blocks := i_ramdata;
state <= STATE_LOOP;
when STATE_LOOP =>
if num_blocks = 0 then
copy_histo_en <= '1';
state <= STATE_COPY_HISTOGRAM;
else
state <= STATE_RECV_BLOCK;
end if;
when STATE_RECV_BLOCK =>
reconos_mq_receive(done, success, o_osif, i_osif, C_MQ_IN, X"00000000", len);
if done then
state <= STATE_UPDATE_HISTOGRAM;
block_size <= len;
update_histo_en <= '1';
end if;
when STATE_UPDATE_HISTOGRAM =>
if update_histo_done = '1' then
update_histo_en <= '0';
num_blocks := num_blocks - 1;
state <= STATE_LOOP;
end if;
when STATE_COPY_HISTOGRAM =>
if copy_histo_done = '1' then
copy_histo_en <= '0';
state <= STATE_SEND_RESULT;
end if;
when STATE_SEND_RESULT =>
len := X"00000200";
reconos_mq_send(done,success,o_osif, i_osif, C_MQ_OUT, X"00000000", len);
if done then
state <= STATE_FINAL;
end if;
when others =>
end case;
end if;
end if;
end process;
end architecture;
|
--**************************************************************************
-- $Id$
--
-- hwt_build_histo.vhd: ReconOS package
--
-- This hardware thread creates a histogram over a sequence of bytes. The
-- input is received in a sequence of blocks via a posix message queue.
-- After receiving the last block, the histogram is send to the outgoing
-- message queue.
--
-- Author : Andreas Agne <agne@upb.de>
-- Created: 1.8.2008
--*************************************************************************/
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
entity hwt_build_histo is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector( C_BURST_AWIDTH-1 downto 0);
o_RAMData : out std_logic_vector( C_BURST_DWIDTH-1 downto 0);
i_RAMData : in std_logic_vector( C_BURST_DWIDTH-1 downto 0);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end entity;
architecture Behavioral of hwt_build_histo is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
constant C_MQ_IN : std_logic_vector(31 downto 0) := X"00000000";
constant C_MQ_OUT : std_logic_vector(31 downto 0) := X"00000001";
-- ReconOS state machine
type t_state is (
STATE_INIT,
STATE_CLEAR_HISTOGRAM,
STATE_RECV_NUM_BLOCKS,
STATE_SAVE_NUM_BLOCKS,
STATE_LOOP,
STATE_RECV_BLOCK,
STATE_UPDATE_HISTOGRAM,
STATE_COPY_HISTOGRAM,
STATE_SEND_RESULT,
STATE_FINAL);
signal state : t_state;
signal block_size : std_logic_vector(31 downto 0); -- size of the last received block
-- update histogram
signal update_histo_en : std_logic; -- handshake signal
signal update_histo_done : std_logic; -- handshake signal
signal update_histo_addr : std_logic_vector(C_BURST_AWIDTH-1 downto 0); -- burst ram addr
signal update_histo_bucket : std_logic_vector(7 downto 0); -- histogram addr
-- copy histogram
signal copy_histo_en : std_logic; -- handshake signal
signal copy_histo_done : std_logic; -- handshake signal
signal copy_histo_addr : std_logic_vector(C_BURST_AWIDTH-1 downto 0); -- burst ram addr
signal copy_histo_bucket : std_logic_vector(7 downto 0); -- histogram addr
-- clear histogram
signal clear_histo_en : std_logic; -- handshake signal
signal clear_histo_done : std_logic; -- handshake signal
signal clear_histo_bucket : std_logic_vector(7 downto 0); -- histogram addr
-- histogram
type t_ram is array (255 downto 0) of std_logic_vector(31 downto 0);
signal histo_ram : t_ram; -- histogram memory
signal histo_bucket : std_logic_vector(7 downto 0); -- current histogram bucket
signal histo_inc : std_logic; -- enables incrementing
signal histo_clear : std_logic; -- enables setting to zero
signal histo_value : std_logic_vector(31 downto 0); -- value of current bucket
signal histo_value_max : std_logic_vector(31 downto 0);
signal histo_value16 : std_logic_vector(15 downto 0);
begin
-- connect burst-ram to clk:
o_RAMClk <= clk;
-- histogram memory is basically a single port ram with
-- asynchronous read. the current bucket is incremented each
-- clock cycle when histo_inc is high, or set to zero when
-- histo_clear is high.
histo_value <= histo_ram(CONV_INTEGER(histo_bucket));
process(clk, reset)
variable tmp : std_logic_vector(31 downto 0);
begin
if reset = '1' then
tmp := (others => '0');
histo_value_max <= (others => '0');
elsif rising_edge(clk) then
if histo_inc = '1' then
if tmp > histo_value_max then
histo_value_max <= tmp;
end if;
tmp := histo_value + 1;
histo_ram(CONV_INTEGER(histo_bucket)) <= tmp;
elsif histo_clear = '1' then
histo_ram(CONV_INTEGER(histo_bucket)) <= (others => '0');
tmp := (others => '0');
histo_value_max <= (others => '0');
end if;
end if;
end process;
process(histo_value, histo_value_max)
variable max_bit : natural range 15 to 31;
begin
max_bit := 15;
for i in 16 to 31 loop
if histo_value_max(i) = '1' then
max_bit := i;
end if;
end loop;
histo_value16 <= histo_value(max_bit downto max_bit - 15);
end process;
-- signals and processes related to updating the histogram from
-- burst-ram data
update_histogramm : process(clk, reset, update_histo_en)
variable step : natural range 0 to 7;
begin
if reset = '1' or update_histo_en = '0' then
step := 0;
histo_inc <= '0';
update_histo_addr <= (others => '0');
update_histo_done <= '0';
update_histo_bucket <= (others => '0');
elsif rising_edge(clk) then
case step is
when 0 => -- set burst ram address to 0
update_histo_addr <= (others => '0');
step := step + 1;
when 1 => -- wait until address is valid
step := step + 1;
when 2 => -- turn on histogram incrementing, first byte
histo_inc <= '1';
update_histo_bucket <= i_ramdata(7 downto 0);
step := step + 1;
when 3 => -- second byte
update_histo_bucket <= i_ramdata(15 downto 8);
step := step + 1;
when 4 => -- load next word from burst ram, third byte
update_histo_bucket <= i_ramdata(23 downto 16);
if update_histo_addr + 1 < block_size(31 downto 2) then
update_histo_addr <= update_histo_addr + 1;
step := step + 1;
else
step := 6;
end if;
when 5 => -- last byte in word, continue
update_histo_bucket <= i_ramdata(31 downto 24);
step := 2;
when 6 => -- last byte in word, end of block
update_histo_bucket <= i_ramdata(31 downto 24);
step := step + 1;
when 7 => -- turn off histogram incrementing, set handshake signal
histo_inc <= '0';
update_histo_done <= '1';
end case;
end if;
end process;
-- signals and processes related to copying the histogram to
-- burst-ram
copy_histogram : process(clk, reset, copy_histo_en)
variable step : natural range 0 to 5;
begin
if reset = '1' or copy_histo_en = '0' then
copy_histo_addr <= (others => '0');
copy_histo_bucket <= (others => '0');
copy_histo_done <= '0';
o_ramwe <= '0';
step := 0;
elsif rising_edge(clk) then
case step is
when 0 => -- set histogram and burst ram addresses to 0
copy_histo_addr <= (others => '0');
copy_histo_bucket <= (others => '0');
step := step + 1;
when 1 =>
o_ramdata(31 downto 16) <= histo_value16;
copy_histo_bucket <= copy_histo_bucket + 1;
step := step + 1;
when 2 => -- copy first word
copy_histo_addr <= (others => '0');
copy_histo_bucket <= copy_histo_bucket + 1;
o_ramwe <= '1';
o_ramdata(15 downto 0) <= histo_value16;
step := step + 1;
when 3 =>
o_ramdata(31 downto 16) <= histo_value16;
copy_histo_addr <= copy_histo_addr + 1;
copy_histo_bucket <= copy_histo_bucket + 1;
step := step + 1;
when 4 => -- copy remaining histogram buckets to burst ram
copy_histo_bucket <= copy_histo_bucket + 1;
o_ramwe <= '1';
o_ramdata(15 downto 0) <= histo_value16;
if copy_histo_addr >= 127 then
step := step + 1;
else
step := 3;
end if;
when 5 => -- all buckets copied -> set handshake signal
copy_histo_done <= '1';
o_ramwe <= '0';
end case;
end if;
end process;
-- signals and processes related to clearing the histogram
clear_histogram : process(clk, reset, clear_histo_en)
variable step : natural range 0 to 2;
begin
if reset = '1' or clear_histo_en = '0' then
step := 0;
histo_clear <= '0';
clear_histo_bucket <= (others => '0');
clear_histo_done <= '0';
elsif rising_edge(clk) then
case step is
when 0 => -- enable bucket zeroing
clear_histo_bucket <= (others => '0');
histo_clear <= '1';
step := step + 1;
when 1 => -- visit every bucket
clear_histo_bucket <= clear_histo_bucket + 1;
if clear_histo_bucket = 255 then
step := step + 1;
end if;
when 2 => -- set handshake signal
histo_clear <= '0';
clear_histo_done <= '1';
end case;
end if;
end process;
-- histogram ram mux
process(update_histo_en, copy_histo_en, clear_histo_en, update_histo_addr, update_histo_bucket,
copy_histo_addr, copy_histo_bucket, clear_histo_bucket)
variable addr : std_logic_vector(C_BURST_AWIDTH - 1 downto 0);
variable bucket : std_logic_vector(7 downto 0);
begin
if update_histo_en = '1' then
addr := update_histo_addr;
bucket := update_histo_bucket;
elsif copy_histo_en = '1' then
addr := copy_histo_addr;
bucket := copy_histo_bucket;
elsif clear_histo_en = '1' then
addr := (others => '0');
bucket := clear_histo_bucket;
else
addr := (others => '0');
bucket := (others => '0');
end if;
o_RAMAddr <= addr(C_BURST_AWIDTH - 1 downto 1) & not addr(0);
histo_bucket <= bucket;
end process;
-- the os interaction state machine performs the following sequential program:
--
-- set all histogram buckets to 0
-- receive the numer of blocks to process
-- for each block:
-- receive block
-- update histogram
-- copy histogram to burst ram
-- send histogram
--
state_proc: process( clk, reset )
variable done : boolean;
variable success : boolean;
variable num_blocks : std_logic_vector(31 downto 0);
variable len : std_logic_vector(31 downto 0);
begin
if reset = '1' then
reconos_reset( o_osif, i_osif );
state <= STATE_INIT;
done := false;
success := false;
num_blocks := (others => '0');
block_size <= (others => '0');
len := (others => '0');
elsif rising_edge( clk ) then
reconos_begin( o_osif, i_osif );
if reconos_ready( i_osif ) then
case state is
when STATE_INIT =>
clear_histo_en <= '1';
state <= STATE_CLEAR_HISTOGRAM;
--reconos_get_init_data(done, o_osif, i_osif, offset);
--if done then state <= STATE_FILL; end if;
when STATE_CLEAR_HISTOGRAM =>
if clear_histo_done = '1' then
clear_histo_en <= '0';
state <= STATE_RECV_NUM_BLOCKS;
end if;
when STATE_RECV_NUM_BLOCKS =>
reconos_mq_receive(done, success, o_osif, i_osif, C_MQ_IN, X"00000000", len);
if done then
state <= STATE_SAVE_NUM_BLOCKS;
end if;
when STATE_SAVE_NUM_BLOCKS =>
num_blocks := i_ramdata;
state <= STATE_LOOP;
when STATE_LOOP =>
if num_blocks = 0 then
copy_histo_en <= '1';
state <= STATE_COPY_HISTOGRAM;
else
state <= STATE_RECV_BLOCK;
end if;
when STATE_RECV_BLOCK =>
reconos_mq_receive(done, success, o_osif, i_osif, C_MQ_IN, X"00000000", len);
if done then
state <= STATE_UPDATE_HISTOGRAM;
block_size <= len;
update_histo_en <= '1';
end if;
when STATE_UPDATE_HISTOGRAM =>
if update_histo_done = '1' then
update_histo_en <= '0';
num_blocks := num_blocks - 1;
state <= STATE_LOOP;
end if;
when STATE_COPY_HISTOGRAM =>
if copy_histo_done = '1' then
copy_histo_en <= '0';
state <= STATE_SEND_RESULT;
end if;
when STATE_SEND_RESULT =>
len := X"00000200";
reconos_mq_send(done,success,o_osif, i_osif, C_MQ_OUT, X"00000000", len);
if done then
state <= STATE_FINAL;
end if;
when others =>
end case;
end if;
end if;
end process;
end architecture;
|
------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity circuit is
--generic declarations
port (
x: in std_logic_vector(1 downto 0) ;
y: out std_logic_vector(1 downto 0) );
end entity;
------------------------------
architecture circuit of circuit is
--signals and declarations
begin
y <= "00" when x = "00" else
"10" when x = "01" else
"01" when x = "10" else
"--";
end architecture;
------------------------------
|
package p is
procedure print_char(c : in character);
end package;
package body p is
procedure print_char(c : in character) is
begin
report character'image(c);
end procedure;
end package body;
entity image is
end entity;
use work.p.all;
architecture test of image is
begin
process is
variable i : integer;
begin
report integer'image(4);
report integer'image(-42);
i := 73;
report integer'image(i);
report "i=" & integer'image(i) & " units";
report character'image('c');
print_char('X');
wait for 10 ps;
report time'image(now);
wait;
end process;
end architecture;
|
package p is
procedure print_char(c : in character);
end package;
package body p is
procedure print_char(c : in character) is
begin
report character'image(c);
end procedure;
end package body;
entity image is
end entity;
use work.p.all;
architecture test of image is
begin
process is
variable i : integer;
begin
report integer'image(4);
report integer'image(-42);
i := 73;
report integer'image(i);
report "i=" & integer'image(i) & " units";
report character'image('c');
print_char('X');
wait for 10 ps;
report time'image(now);
wait;
end process;
end architecture;
|
package p is
procedure print_char(c : in character);
end package;
package body p is
procedure print_char(c : in character) is
begin
report character'image(c);
end procedure;
end package body;
entity image is
end entity;
use work.p.all;
architecture test of image is
begin
process is
variable i : integer;
begin
report integer'image(4);
report integer'image(-42);
i := 73;
report integer'image(i);
report "i=" & integer'image(i) & " units";
report character'image('c');
print_char('X');
wait for 10 ps;
report time'image(now);
wait;
end process;
end architecture;
|
package p is
procedure print_char(c : in character);
end package;
package body p is
procedure print_char(c : in character) is
begin
report character'image(c);
end procedure;
end package body;
entity image is
end entity;
use work.p.all;
architecture test of image is
begin
process is
variable i : integer;
begin
report integer'image(4);
report integer'image(-42);
i := 73;
report integer'image(i);
report "i=" & integer'image(i) & " units";
report character'image('c');
print_char('X');
wait for 10 ps;
report time'image(now);
wait;
end process;
end architecture;
|
library verilog;
use verilog.vl_types.all;
entity cw3_vlg_vec_tst is
end cw3_vlg_vec_tst;
|
library verilog;
use verilog.vl_types.all;
entity cw3_vlg_vec_tst is
end cw3_vlg_vec_tst;
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_in_one_hot_checkers is
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_checkers;
architecture behavior of Arbiter_in_one_hot_checkers is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= X_N & X_E & X_W & X_S & X_L;
-- Checkers
--checked
process (state, Requests, state_in)
begin
--if ( (state = North or state = East or state = West or state = South or state = Local or state = IDLE) and Requests = "00000" and state_in /= state ) then
if (Requests = "00000" and state_in /= state ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
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-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_Req_N <= '1';
else
err_IDLE_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = IDLE and req_X_N = '1' and X_N = '0' ) then
err_IDLE_grant_N <= '1';
else
err_IDLE_grant_N <= '0';
end if;
end process;
process (state, req_X_N, state_in)
begin
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_Req_N <= '1';
else
err_North_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = North and req_X_N = '1' and X_N = '0' ) then
err_North_grant_N <= '1';
else
err_North_grant_N <= '0';
end if;
end process;
process (state, req_X_E, state_in)
begin
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_Req_E <= '1';
else
err_East_Req_E <= '0';
end if;
end process;
process (state, req_X_E, X_E)
begin
if ( state = East and req_X_E = '1' and X_E = '0' ) then
err_East_grant_E <= '1';
else
err_East_grant_E <= '0';
end if;
end process;
process (state, req_X_W, state_in)
begin
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_Req_W <= '1';
else
err_West_Req_W <= '0';
end if;
end process;
process (state, req_X_W, X_W)
begin
if ( state = West and req_X_W = '1' and X_W = '0' ) then
err_West_grant_W <= '1';
else
err_West_grant_W <= '0';
end if;
end process;
process (state, req_X_S, state_in)
begin
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_Req_S <= '1';
else
err_South_Req_S <= '0';
end if;
end process;
process (state, req_X_S, X_S)
begin
if ( state = South and req_X_S = '1' and X_S = '0' ) then
err_South_grant_S <= '1';
else
err_South_grant_S <= '0';
end if;
end process;
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_Req_L <= '1';
else
err_Local_Req_L <= '0';
end if;
end process;
process (state, req_X_L, X_L)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and X_L = '0' ) then
err_Local_grant_L <= '1';
else
err_Local_grant_L <= '0';
end if;
end process;
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-- Round 2
--checked
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_Req_E <= '1';
else
err_IDLE_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_IDLE_grant_E <= '1';
else
err_IDLE_grant_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_Req_E <= '1';
else
err_North_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_North_grant_E <= '1';
else
err_North_grant_E <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_Req_W <= '1';
else
err_East_Req_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, X_W)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_East_grant_W <= '1';
else
err_East_grant_W <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_Req_S <= '1';
else
err_West_Req_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, X_S)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_West_grant_S <= '1';
else
err_West_grant_S <= '0';
end if;
end process;
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_Req_L <= '1';
else
err_South_Req_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, X_L)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_South_grant_L <= '1';
else
err_South_grant_L <= '0';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_Req_N <= '1';
else
err_Local_Req_N <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, X_N)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_Local_grant_N <= '1';
else
err_Local_grant_N <= '0';
end if;
end process;
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-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_Req_W <= '1';
else
err_IDLE_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_IDLE_grant_W <= '1';
else
err_IDLE_grant_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_Req_W <= '1';
else
err_North_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_North_grant_W <= '1';
else
err_North_grant_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_Req_S <= '1';
else
err_East_Req_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_East_grant_S <= '1';
else
err_East_grant_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_Req_L <= '1';
else
err_West_Req_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_West_grant_L <= '1';
else
err_West_grant_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_Req_N <= '1';
else
err_South_Req_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_South_grant_N <= '1';
else
err_South_grant_N <= '0';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_Req_E <= '1';
else
err_Local_Req_E <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_Local_grant_E <= '1';
else
err_Local_grant_E <= '0';
end if;
end process;
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-----------------------------------------------------------------------------------------------------------------------
-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_Req_S <= '1';
else
err_IDLE_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_IDLE_grant_S <= '1';
else
err_IDLE_grant_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_Req_S <= '1';
else
err_North_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_North_grant_S <= '1';
else
err_North_grant_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_Req_L <= '1';
else
err_East_Req_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0') then
err_East_grant_L <= '1';
else
err_East_grant_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_Req_N <= '1';
else
err_West_Req_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0') then
err_West_grant_N <= '1';
else
err_West_grant_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_Req_E <= '1';
else
err_South_Req_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0') then
err_South_grant_E <= '1';
else
err_South_grant_E <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_Req_W <= '1';
else
err_Local_Req_W <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0') then
err_Local_grant_W <= '1';
else
err_Local_grant_W <= '0';
end if;
end process;
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-----------------------------------------------------------------------------------------------------------------------
-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_Req_L <= '1';
else
err_IDLE_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_IDLE_grant_L <= '1';
else
err_IDLE_grant_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_Req_L <= '1';
else
err_North_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_North_grant_L <= '1';
else
err_North_grant_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_Req_N <= '1';
else
err_East_Req_N <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0' ) then
err_East_grant_N <= '1';
else
err_East_grant_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_Req_E <= '1';
else
err_West_Req_E <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0' ) then
err_West_grant_E <= '1';
else
err_West_grant_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_Req_W <= '1';
else
err_South_Req_W <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0' ) then
err_South_grant_W <= '1';
else
err_South_grant_W <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_Req_S <= '1';
else
err_Local_Req_S <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0' ) then
err_Local_grant_S <= '1';
else
err_Local_grant_S <= '0';
end if;
end process;
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process (state_in)
begin
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
else
err_no_request_grants <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests /= "00000" and Grants = "00000") then
err_request_no_grants <= '1';
else
err_request_no_grants <= '0';
end if;
end process;
process (req_X_N, X_N)
begin
if (req_X_N = '0' and X_N = '1') then
err_no_Req_N_grant_N <= '1';
else
err_no_Req_N_grant_N <= '0';
end if;
end process;
process (req_X_E, X_E)
begin
if (req_X_E = '0' and X_E = '1') then
err_no_Req_E_grant_E <= '1';
else
err_no_Req_E_grant_E <= '0';
end if;
end process;
process (req_X_W, X_W)
begin
if (req_X_W = '0' and X_W = '1') then
err_no_Req_W_grant_W <= '1';
else
err_no_Req_W_grant_W <= '0';
end if;
end process;
process (req_X_S, X_S)
begin
if (req_X_S = '0' and X_S = '1') then
err_no_Req_S_grant_S <= '1';
else
err_no_Req_S_grant_S <= '0';
end if;
end process;
process (req_X_L, X_L)
begin
if (req_X_L = '0' and X_L = '1') then
err_no_Req_L_grant_L <= '1';
else
err_no_Req_L_grant_L <= '0';
end if;
end process;
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_in_one_hot_checkers is
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_checkers;
architecture behavior of Arbiter_in_one_hot_checkers is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= X_N & X_E & X_W & X_S & X_L;
-- Checkers
--checked
process (state, Requests, state_in)
begin
--if ( (state = North or state = East or state = West or state = South or state = Local or state = IDLE) and Requests = "00000" and state_in /= state ) then
if (Requests = "00000" and state_in /= state ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
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-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_Req_N <= '1';
else
err_IDLE_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = IDLE and req_X_N = '1' and X_N = '0' ) then
err_IDLE_grant_N <= '1';
else
err_IDLE_grant_N <= '0';
end if;
end process;
process (state, req_X_N, state_in)
begin
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_Req_N <= '1';
else
err_North_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = North and req_X_N = '1' and X_N = '0' ) then
err_North_grant_N <= '1';
else
err_North_grant_N <= '0';
end if;
end process;
process (state, req_X_E, state_in)
begin
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_Req_E <= '1';
else
err_East_Req_E <= '0';
end if;
end process;
process (state, req_X_E, X_E)
begin
if ( state = East and req_X_E = '1' and X_E = '0' ) then
err_East_grant_E <= '1';
else
err_East_grant_E <= '0';
end if;
end process;
process (state, req_X_W, state_in)
begin
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_Req_W <= '1';
else
err_West_Req_W <= '0';
end if;
end process;
process (state, req_X_W, X_W)
begin
if ( state = West and req_X_W = '1' and X_W = '0' ) then
err_West_grant_W <= '1';
else
err_West_grant_W <= '0';
end if;
end process;
process (state, req_X_S, state_in)
begin
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_Req_S <= '1';
else
err_South_Req_S <= '0';
end if;
end process;
process (state, req_X_S, X_S)
begin
if ( state = South and req_X_S = '1' and X_S = '0' ) then
err_South_grant_S <= '1';
else
err_South_grant_S <= '0';
end if;
end process;
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_Req_L <= '1';
else
err_Local_Req_L <= '0';
end if;
end process;
process (state, req_X_L, X_L)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and X_L = '0' ) then
err_Local_grant_L <= '1';
else
err_Local_grant_L <= '0';
end if;
end process;
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-- Round 2
--checked
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_Req_E <= '1';
else
err_IDLE_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_IDLE_grant_E <= '1';
else
err_IDLE_grant_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_Req_E <= '1';
else
err_North_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_North_grant_E <= '1';
else
err_North_grant_E <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_Req_W <= '1';
else
err_East_Req_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, X_W)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_East_grant_W <= '1';
else
err_East_grant_W <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_Req_S <= '1';
else
err_West_Req_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, X_S)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_West_grant_S <= '1';
else
err_West_grant_S <= '0';
end if;
end process;
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_Req_L <= '1';
else
err_South_Req_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, X_L)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_South_grant_L <= '1';
else
err_South_grant_L <= '0';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_Req_N <= '1';
else
err_Local_Req_N <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, X_N)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_Local_grant_N <= '1';
else
err_Local_grant_N <= '0';
end if;
end process;
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-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_Req_W <= '1';
else
err_IDLE_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_IDLE_grant_W <= '1';
else
err_IDLE_grant_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_Req_W <= '1';
else
err_North_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_North_grant_W <= '1';
else
err_North_grant_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_Req_S <= '1';
else
err_East_Req_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_East_grant_S <= '1';
else
err_East_grant_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_Req_L <= '1';
else
err_West_Req_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_West_grant_L <= '1';
else
err_West_grant_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_Req_N <= '1';
else
err_South_Req_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_South_grant_N <= '1';
else
err_South_grant_N <= '0';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_Req_E <= '1';
else
err_Local_Req_E <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_Local_grant_E <= '1';
else
err_Local_grant_E <= '0';
end if;
end process;
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-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_Req_S <= '1';
else
err_IDLE_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_IDLE_grant_S <= '1';
else
err_IDLE_grant_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_Req_S <= '1';
else
err_North_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_North_grant_S <= '1';
else
err_North_grant_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_Req_L <= '1';
else
err_East_Req_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0') then
err_East_grant_L <= '1';
else
err_East_grant_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_Req_N <= '1';
else
err_West_Req_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0') then
err_West_grant_N <= '1';
else
err_West_grant_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_Req_E <= '1';
else
err_South_Req_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0') then
err_South_grant_E <= '1';
else
err_South_grant_E <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_Req_W <= '1';
else
err_Local_Req_W <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0') then
err_Local_grant_W <= '1';
else
err_Local_grant_W <= '0';
end if;
end process;
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-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_Req_L <= '1';
else
err_IDLE_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_IDLE_grant_L <= '1';
else
err_IDLE_grant_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_Req_L <= '1';
else
err_North_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_North_grant_L <= '1';
else
err_North_grant_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_Req_N <= '1';
else
err_East_Req_N <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0' ) then
err_East_grant_N <= '1';
else
err_East_grant_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_Req_E <= '1';
else
err_West_Req_E <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0' ) then
err_West_grant_E <= '1';
else
err_West_grant_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_Req_W <= '1';
else
err_South_Req_W <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0' ) then
err_South_grant_W <= '1';
else
err_South_grant_W <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_Req_S <= '1';
else
err_Local_Req_S <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0' ) then
err_Local_grant_S <= '1';
else
err_Local_grant_S <= '0';
end if;
end process;
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process (state_in)
begin
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
else
err_no_request_grants <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests /= "00000" and Grants = "00000") then
err_request_no_grants <= '1';
else
err_request_no_grants <= '0';
end if;
end process;
process (req_X_N, X_N)
begin
if (req_X_N = '0' and X_N = '1') then
err_no_Req_N_grant_N <= '1';
else
err_no_Req_N_grant_N <= '0';
end if;
end process;
process (req_X_E, X_E)
begin
if (req_X_E = '0' and X_E = '1') then
err_no_Req_E_grant_E <= '1';
else
err_no_Req_E_grant_E <= '0';
end if;
end process;
process (req_X_W, X_W)
begin
if (req_X_W = '0' and X_W = '1') then
err_no_Req_W_grant_W <= '1';
else
err_no_Req_W_grant_W <= '0';
end if;
end process;
process (req_X_S, X_S)
begin
if (req_X_S = '0' and X_S = '1') then
err_no_Req_S_grant_S <= '1';
else
err_no_Req_S_grant_S <= '0';
end if;
end process;
process (req_X_L, X_L)
begin
if (req_X_L = '0' and X_L = '1') then
err_no_Req_L_grant_L <= '1';
else
err_no_Req_L_grant_L <= '0';
end if;
end process;
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_in_one_hot_checkers is
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_checkers;
architecture behavior of Arbiter_in_one_hot_checkers is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= X_N & X_E & X_W & X_S & X_L;
-- Checkers
--checked
process (state, Requests, state_in)
begin
--if ( (state = North or state = East or state = West or state = South or state = Local or state = IDLE) and Requests = "00000" and state_in /= state ) then
if (Requests = "00000" and state_in /= state ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
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-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_Req_N <= '1';
else
err_IDLE_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = IDLE and req_X_N = '1' and X_N = '0' ) then
err_IDLE_grant_N <= '1';
else
err_IDLE_grant_N <= '0';
end if;
end process;
process (state, req_X_N, state_in)
begin
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_Req_N <= '1';
else
err_North_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = North and req_X_N = '1' and X_N = '0' ) then
err_North_grant_N <= '1';
else
err_North_grant_N <= '0';
end if;
end process;
process (state, req_X_E, state_in)
begin
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_Req_E <= '1';
else
err_East_Req_E <= '0';
end if;
end process;
process (state, req_X_E, X_E)
begin
if ( state = East and req_X_E = '1' and X_E = '0' ) then
err_East_grant_E <= '1';
else
err_East_grant_E <= '0';
end if;
end process;
process (state, req_X_W, state_in)
begin
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_Req_W <= '1';
else
err_West_Req_W <= '0';
end if;
end process;
process (state, req_X_W, X_W)
begin
if ( state = West and req_X_W = '1' and X_W = '0' ) then
err_West_grant_W <= '1';
else
err_West_grant_W <= '0';
end if;
end process;
process (state, req_X_S, state_in)
begin
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_Req_S <= '1';
else
err_South_Req_S <= '0';
end if;
end process;
process (state, req_X_S, X_S)
begin
if ( state = South and req_X_S = '1' and X_S = '0' ) then
err_South_grant_S <= '1';
else
err_South_grant_S <= '0';
end if;
end process;
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_Req_L <= '1';
else
err_Local_Req_L <= '0';
end if;
end process;
process (state, req_X_L, X_L)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and X_L = '0' ) then
err_Local_grant_L <= '1';
else
err_Local_grant_L <= '0';
end if;
end process;
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-- Round 2
--checked
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_Req_E <= '1';
else
err_IDLE_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_IDLE_grant_E <= '1';
else
err_IDLE_grant_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_Req_E <= '1';
else
err_North_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_North_grant_E <= '1';
else
err_North_grant_E <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_Req_W <= '1';
else
err_East_Req_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, X_W)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_East_grant_W <= '1';
else
err_East_grant_W <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_Req_S <= '1';
else
err_West_Req_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, X_S)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_West_grant_S <= '1';
else
err_West_grant_S <= '0';
end if;
end process;
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_Req_L <= '1';
else
err_South_Req_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, X_L)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_South_grant_L <= '1';
else
err_South_grant_L <= '0';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_Req_N <= '1';
else
err_Local_Req_N <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, X_N)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_Local_grant_N <= '1';
else
err_Local_grant_N <= '0';
end if;
end process;
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-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_Req_W <= '1';
else
err_IDLE_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_IDLE_grant_W <= '1';
else
err_IDLE_grant_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_Req_W <= '1';
else
err_North_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_North_grant_W <= '1';
else
err_North_grant_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_Req_S <= '1';
else
err_East_Req_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_East_grant_S <= '1';
else
err_East_grant_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_Req_L <= '1';
else
err_West_Req_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_West_grant_L <= '1';
else
err_West_grant_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_Req_N <= '1';
else
err_South_Req_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_South_grant_N <= '1';
else
err_South_grant_N <= '0';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_Req_E <= '1';
else
err_Local_Req_E <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_Local_grant_E <= '1';
else
err_Local_grant_E <= '0';
end if;
end process;
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-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_Req_S <= '1';
else
err_IDLE_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_IDLE_grant_S <= '1';
else
err_IDLE_grant_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_Req_S <= '1';
else
err_North_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_North_grant_S <= '1';
else
err_North_grant_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_Req_L <= '1';
else
err_East_Req_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0') then
err_East_grant_L <= '1';
else
err_East_grant_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_Req_N <= '1';
else
err_West_Req_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0') then
err_West_grant_N <= '1';
else
err_West_grant_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_Req_E <= '1';
else
err_South_Req_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0') then
err_South_grant_E <= '1';
else
err_South_grant_E <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_Req_W <= '1';
else
err_Local_Req_W <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0') then
err_Local_grant_W <= '1';
else
err_Local_grant_W <= '0';
end if;
end process;
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-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_Req_L <= '1';
else
err_IDLE_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_IDLE_grant_L <= '1';
else
err_IDLE_grant_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_Req_L <= '1';
else
err_North_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_North_grant_L <= '1';
else
err_North_grant_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_Req_N <= '1';
else
err_East_Req_N <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0' ) then
err_East_grant_N <= '1';
else
err_East_grant_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_Req_E <= '1';
else
err_West_Req_E <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0' ) then
err_West_grant_E <= '1';
else
err_West_grant_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_Req_W <= '1';
else
err_South_Req_W <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0' ) then
err_South_grant_W <= '1';
else
err_South_grant_W <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_Req_S <= '1';
else
err_Local_Req_S <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0' ) then
err_Local_grant_S <= '1';
else
err_Local_grant_S <= '0';
end if;
end process;
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process (state_in)
begin
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
else
err_no_request_grants <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests /= "00000" and Grants = "00000") then
err_request_no_grants <= '1';
else
err_request_no_grants <= '0';
end if;
end process;
process (req_X_N, X_N)
begin
if (req_X_N = '0' and X_N = '1') then
err_no_Req_N_grant_N <= '1';
else
err_no_Req_N_grant_N <= '0';
end if;
end process;
process (req_X_E, X_E)
begin
if (req_X_E = '0' and X_E = '1') then
err_no_Req_E_grant_E <= '1';
else
err_no_Req_E_grant_E <= '0';
end if;
end process;
process (req_X_W, X_W)
begin
if (req_X_W = '0' and X_W = '1') then
err_no_Req_W_grant_W <= '1';
else
err_no_Req_W_grant_W <= '0';
end if;
end process;
process (req_X_S, X_S)
begin
if (req_X_S = '0' and X_S = '1') then
err_no_Req_S_grant_S <= '1';
else
err_no_Req_S_grant_S <= '0';
end if;
end process;
process (req_X_L, X_L)
begin
if (req_X_L = '0' and X_L = '1') then
err_no_Req_L_grant_L <= '1';
else
err_no_Req_L_grant_L <= '0';
end if;
end process;
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_in_one_hot_checkers is
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_checkers;
architecture behavior of Arbiter_in_one_hot_checkers is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= X_N & X_E & X_W & X_S & X_L;
-- Checkers
--checked
process (state, Requests, state_in)
begin
--if ( (state = North or state = East or state = West or state = South or state = Local or state = IDLE) and Requests = "00000" and state_in /= state ) then
if (Requests = "00000" and state_in /= state ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
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-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_Req_N <= '1';
else
err_IDLE_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = IDLE and req_X_N = '1' and X_N = '0' ) then
err_IDLE_grant_N <= '1';
else
err_IDLE_grant_N <= '0';
end if;
end process;
process (state, req_X_N, state_in)
begin
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_Req_N <= '1';
else
err_North_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = North and req_X_N = '1' and X_N = '0' ) then
err_North_grant_N <= '1';
else
err_North_grant_N <= '0';
end if;
end process;
process (state, req_X_E, state_in)
begin
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_Req_E <= '1';
else
err_East_Req_E <= '0';
end if;
end process;
process (state, req_X_E, X_E)
begin
if ( state = East and req_X_E = '1' and X_E = '0' ) then
err_East_grant_E <= '1';
else
err_East_grant_E <= '0';
end if;
end process;
process (state, req_X_W, state_in)
begin
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_Req_W <= '1';
else
err_West_Req_W <= '0';
end if;
end process;
process (state, req_X_W, X_W)
begin
if ( state = West and req_X_W = '1' and X_W = '0' ) then
err_West_grant_W <= '1';
else
err_West_grant_W <= '0';
end if;
end process;
process (state, req_X_S, state_in)
begin
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_Req_S <= '1';
else
err_South_Req_S <= '0';
end if;
end process;
process (state, req_X_S, X_S)
begin
if ( state = South and req_X_S = '1' and X_S = '0' ) then
err_South_grant_S <= '1';
else
err_South_grant_S <= '0';
end if;
end process;
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_Req_L <= '1';
else
err_Local_Req_L <= '0';
end if;
end process;
process (state, req_X_L, X_L)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and X_L = '0' ) then
err_Local_grant_L <= '1';
else
err_Local_grant_L <= '0';
end if;
end process;
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-- Round 2
--checked
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_Req_E <= '1';
else
err_IDLE_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_IDLE_grant_E <= '1';
else
err_IDLE_grant_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_Req_E <= '1';
else
err_North_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_North_grant_E <= '1';
else
err_North_grant_E <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_Req_W <= '1';
else
err_East_Req_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, X_W)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_East_grant_W <= '1';
else
err_East_grant_W <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_Req_S <= '1';
else
err_West_Req_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, X_S)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_West_grant_S <= '1';
else
err_West_grant_S <= '0';
end if;
end process;
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_Req_L <= '1';
else
err_South_Req_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, X_L)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_South_grant_L <= '1';
else
err_South_grant_L <= '0';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_Req_N <= '1';
else
err_Local_Req_N <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, X_N)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_Local_grant_N <= '1';
else
err_Local_grant_N <= '0';
end if;
end process;
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-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_Req_W <= '1';
else
err_IDLE_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_IDLE_grant_W <= '1';
else
err_IDLE_grant_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_Req_W <= '1';
else
err_North_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_North_grant_W <= '1';
else
err_North_grant_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_Req_S <= '1';
else
err_East_Req_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_East_grant_S <= '1';
else
err_East_grant_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_Req_L <= '1';
else
err_West_Req_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_West_grant_L <= '1';
else
err_West_grant_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_Req_N <= '1';
else
err_South_Req_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_South_grant_N <= '1';
else
err_South_grant_N <= '0';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_Req_E <= '1';
else
err_Local_Req_E <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_Local_grant_E <= '1';
else
err_Local_grant_E <= '0';
end if;
end process;
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-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_Req_S <= '1';
else
err_IDLE_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_IDLE_grant_S <= '1';
else
err_IDLE_grant_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_Req_S <= '1';
else
err_North_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_North_grant_S <= '1';
else
err_North_grant_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_Req_L <= '1';
else
err_East_Req_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0') then
err_East_grant_L <= '1';
else
err_East_grant_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_Req_N <= '1';
else
err_West_Req_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0') then
err_West_grant_N <= '1';
else
err_West_grant_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_Req_E <= '1';
else
err_South_Req_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0') then
err_South_grant_E <= '1';
else
err_South_grant_E <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_Req_W <= '1';
else
err_Local_Req_W <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0') then
err_Local_grant_W <= '1';
else
err_Local_grant_W <= '0';
end if;
end process;
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-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_Req_L <= '1';
else
err_IDLE_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_IDLE_grant_L <= '1';
else
err_IDLE_grant_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_Req_L <= '1';
else
err_North_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_North_grant_L <= '1';
else
err_North_grant_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_Req_N <= '1';
else
err_East_Req_N <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0' ) then
err_East_grant_N <= '1';
else
err_East_grant_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_Req_E <= '1';
else
err_West_Req_E <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0' ) then
err_West_grant_E <= '1';
else
err_West_grant_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_Req_W <= '1';
else
err_South_Req_W <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0' ) then
err_South_grant_W <= '1';
else
err_South_grant_W <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_Req_S <= '1';
else
err_Local_Req_S <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0' ) then
err_Local_grant_S <= '1';
else
err_Local_grant_S <= '0';
end if;
end process;
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process (state_in)
begin
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
else
err_no_request_grants <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests /= "00000" and Grants = "00000") then
err_request_no_grants <= '1';
else
err_request_no_grants <= '0';
end if;
end process;
process (req_X_N, X_N)
begin
if (req_X_N = '0' and X_N = '1') then
err_no_Req_N_grant_N <= '1';
else
err_no_Req_N_grant_N <= '0';
end if;
end process;
process (req_X_E, X_E)
begin
if (req_X_E = '0' and X_E = '1') then
err_no_Req_E_grant_E <= '1';
else
err_no_Req_E_grant_E <= '0';
end if;
end process;
process (req_X_W, X_W)
begin
if (req_X_W = '0' and X_W = '1') then
err_no_Req_W_grant_W <= '1';
else
err_no_Req_W_grant_W <= '0';
end if;
end process;
process (req_X_S, X_S)
begin
if (req_X_S = '0' and X_S = '1') then
err_no_Req_S_grant_S <= '1';
else
err_no_Req_S_grant_S <= '0';
end if;
end process;
process (req_X_L, X_L)
begin
if (req_X_L = '0' and X_L = '1') then
err_no_Req_L_grant_L <= '1';
else
err_no_Req_L_grant_L <= '0';
end if;
end process;
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_in_one_hot_checkers is
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_checkers;
architecture behavior of Arbiter_in_one_hot_checkers is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= X_N & X_E & X_W & X_S & X_L;
-- Checkers
--checked
process (state, Requests, state_in)
begin
--if ( (state = North or state = East or state = West or state = South or state = Local or state = IDLE) and Requests = "00000" and state_in /= state ) then
if (Requests = "00000" and state_in /= state ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
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-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_Req_N <= '1';
else
err_IDLE_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = IDLE and req_X_N = '1' and X_N = '0' ) then
err_IDLE_grant_N <= '1';
else
err_IDLE_grant_N <= '0';
end if;
end process;
process (state, req_X_N, state_in)
begin
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_Req_N <= '1';
else
err_North_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = North and req_X_N = '1' and X_N = '0' ) then
err_North_grant_N <= '1';
else
err_North_grant_N <= '0';
end if;
end process;
process (state, req_X_E, state_in)
begin
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_Req_E <= '1';
else
err_East_Req_E <= '0';
end if;
end process;
process (state, req_X_E, X_E)
begin
if ( state = East and req_X_E = '1' and X_E = '0' ) then
err_East_grant_E <= '1';
else
err_East_grant_E <= '0';
end if;
end process;
process (state, req_X_W, state_in)
begin
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_Req_W <= '1';
else
err_West_Req_W <= '0';
end if;
end process;
process (state, req_X_W, X_W)
begin
if ( state = West and req_X_W = '1' and X_W = '0' ) then
err_West_grant_W <= '1';
else
err_West_grant_W <= '0';
end if;
end process;
process (state, req_X_S, state_in)
begin
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_Req_S <= '1';
else
err_South_Req_S <= '0';
end if;
end process;
process (state, req_X_S, X_S)
begin
if ( state = South and req_X_S = '1' and X_S = '0' ) then
err_South_grant_S <= '1';
else
err_South_grant_S <= '0';
end if;
end process;
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_Req_L <= '1';
else
err_Local_Req_L <= '0';
end if;
end process;
process (state, req_X_L, X_L)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and X_L = '0' ) then
err_Local_grant_L <= '1';
else
err_Local_grant_L <= '0';
end if;
end process;
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-- Round 2
--checked
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_Req_E <= '1';
else
err_IDLE_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_IDLE_grant_E <= '1';
else
err_IDLE_grant_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_Req_E <= '1';
else
err_North_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_North_grant_E <= '1';
else
err_North_grant_E <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_Req_W <= '1';
else
err_East_Req_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, X_W)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_East_grant_W <= '1';
else
err_East_grant_W <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_Req_S <= '1';
else
err_West_Req_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, X_S)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_West_grant_S <= '1';
else
err_West_grant_S <= '0';
end if;
end process;
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_Req_L <= '1';
else
err_South_Req_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, X_L)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_South_grant_L <= '1';
else
err_South_grant_L <= '0';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_Req_N <= '1';
else
err_Local_Req_N <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, X_N)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_Local_grant_N <= '1';
else
err_Local_grant_N <= '0';
end if;
end process;
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-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_Req_W <= '1';
else
err_IDLE_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_IDLE_grant_W <= '1';
else
err_IDLE_grant_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_Req_W <= '1';
else
err_North_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_North_grant_W <= '1';
else
err_North_grant_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_Req_S <= '1';
else
err_East_Req_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_East_grant_S <= '1';
else
err_East_grant_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_Req_L <= '1';
else
err_West_Req_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_West_grant_L <= '1';
else
err_West_grant_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_Req_N <= '1';
else
err_South_Req_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_South_grant_N <= '1';
else
err_South_grant_N <= '0';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_Req_E <= '1';
else
err_Local_Req_E <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_Local_grant_E <= '1';
else
err_Local_grant_E <= '0';
end if;
end process;
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-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_Req_S <= '1';
else
err_IDLE_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_IDLE_grant_S <= '1';
else
err_IDLE_grant_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_Req_S <= '1';
else
err_North_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_North_grant_S <= '1';
else
err_North_grant_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_Req_L <= '1';
else
err_East_Req_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0') then
err_East_grant_L <= '1';
else
err_East_grant_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_Req_N <= '1';
else
err_West_Req_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0') then
err_West_grant_N <= '1';
else
err_West_grant_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_Req_E <= '1';
else
err_South_Req_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0') then
err_South_grant_E <= '1';
else
err_South_grant_E <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_Req_W <= '1';
else
err_Local_Req_W <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0') then
err_Local_grant_W <= '1';
else
err_Local_grant_W <= '0';
end if;
end process;
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-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_Req_L <= '1';
else
err_IDLE_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_IDLE_grant_L <= '1';
else
err_IDLE_grant_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_Req_L <= '1';
else
err_North_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_North_grant_L <= '1';
else
err_North_grant_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_Req_N <= '1';
else
err_East_Req_N <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0' ) then
err_East_grant_N <= '1';
else
err_East_grant_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_Req_E <= '1';
else
err_West_Req_E <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0' ) then
err_West_grant_E <= '1';
else
err_West_grant_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_Req_W <= '1';
else
err_South_Req_W <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0' ) then
err_South_grant_W <= '1';
else
err_South_grant_W <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_Req_S <= '1';
else
err_Local_Req_S <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0' ) then
err_Local_grant_S <= '1';
else
err_Local_grant_S <= '0';
end if;
end process;
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process (state_in)
begin
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
else
err_no_request_grants <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests /= "00000" and Grants = "00000") then
err_request_no_grants <= '1';
else
err_request_no_grants <= '0';
end if;
end process;
process (req_X_N, X_N)
begin
if (req_X_N = '0' and X_N = '1') then
err_no_Req_N_grant_N <= '1';
else
err_no_Req_N_grant_N <= '0';
end if;
end process;
process (req_X_E, X_E)
begin
if (req_X_E = '0' and X_E = '1') then
err_no_Req_E_grant_E <= '1';
else
err_no_Req_E_grant_E <= '0';
end if;
end process;
process (req_X_W, X_W)
begin
if (req_X_W = '0' and X_W = '1') then
err_no_Req_W_grant_W <= '1';
else
err_no_Req_W_grant_W <= '0';
end if;
end process;
process (req_X_S, X_S)
begin
if (req_X_S = '0' and X_S = '1') then
err_no_Req_S_grant_S <= '1';
else
err_no_Req_S_grant_S <= '0';
end if;
end process;
process (req_X_L, X_L)
begin
if (req_X_L = '0' and X_L = '1') then
err_no_Req_L_grant_L <= '1';
else
err_no_Req_L_grant_L <= '0';
end if;
end process;
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_in_one_hot_checkers is
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_checkers;
architecture behavior of Arbiter_in_one_hot_checkers is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= X_N & X_E & X_W & X_S & X_L;
-- Checkers
--checked
process (state, Requests, state_in)
begin
--if ( (state = North or state = East or state = West or state = South or state = Local or state = IDLE) and Requests = "00000" and state_in /= state ) then
if (Requests = "00000" and state_in /= state ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
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-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_Req_N <= '1';
else
err_IDLE_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = IDLE and req_X_N = '1' and X_N = '0' ) then
err_IDLE_grant_N <= '1';
else
err_IDLE_grant_N <= '0';
end if;
end process;
process (state, req_X_N, state_in)
begin
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_Req_N <= '1';
else
err_North_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = North and req_X_N = '1' and X_N = '0' ) then
err_North_grant_N <= '1';
else
err_North_grant_N <= '0';
end if;
end process;
process (state, req_X_E, state_in)
begin
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_Req_E <= '1';
else
err_East_Req_E <= '0';
end if;
end process;
process (state, req_X_E, X_E)
begin
if ( state = East and req_X_E = '1' and X_E = '0' ) then
err_East_grant_E <= '1';
else
err_East_grant_E <= '0';
end if;
end process;
process (state, req_X_W, state_in)
begin
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_Req_W <= '1';
else
err_West_Req_W <= '0';
end if;
end process;
process (state, req_X_W, X_W)
begin
if ( state = West and req_X_W = '1' and X_W = '0' ) then
err_West_grant_W <= '1';
else
err_West_grant_W <= '0';
end if;
end process;
process (state, req_X_S, state_in)
begin
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_Req_S <= '1';
else
err_South_Req_S <= '0';
end if;
end process;
process (state, req_X_S, X_S)
begin
if ( state = South and req_X_S = '1' and X_S = '0' ) then
err_South_grant_S <= '1';
else
err_South_grant_S <= '0';
end if;
end process;
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_Req_L <= '1';
else
err_Local_Req_L <= '0';
end if;
end process;
process (state, req_X_L, X_L)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and X_L = '0' ) then
err_Local_grant_L <= '1';
else
err_Local_grant_L <= '0';
end if;
end process;
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-- Round 2
--checked
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_Req_E <= '1';
else
err_IDLE_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_IDLE_grant_E <= '1';
else
err_IDLE_grant_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_Req_E <= '1';
else
err_North_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_North_grant_E <= '1';
else
err_North_grant_E <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_Req_W <= '1';
else
err_East_Req_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, X_W)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_East_grant_W <= '1';
else
err_East_grant_W <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_Req_S <= '1';
else
err_West_Req_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, X_S)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_West_grant_S <= '1';
else
err_West_grant_S <= '0';
end if;
end process;
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_Req_L <= '1';
else
err_South_Req_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, X_L)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_South_grant_L <= '1';
else
err_South_grant_L <= '0';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_Req_N <= '1';
else
err_Local_Req_N <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, X_N)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_Local_grant_N <= '1';
else
err_Local_grant_N <= '0';
end if;
end process;
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-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_Req_W <= '1';
else
err_IDLE_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_IDLE_grant_W <= '1';
else
err_IDLE_grant_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_Req_W <= '1';
else
err_North_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_North_grant_W <= '1';
else
err_North_grant_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_Req_S <= '1';
else
err_East_Req_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_East_grant_S <= '1';
else
err_East_grant_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_Req_L <= '1';
else
err_West_Req_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_West_grant_L <= '1';
else
err_West_grant_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_Req_N <= '1';
else
err_South_Req_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_South_grant_N <= '1';
else
err_South_grant_N <= '0';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_Req_E <= '1';
else
err_Local_Req_E <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_Local_grant_E <= '1';
else
err_Local_grant_E <= '0';
end if;
end process;
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-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_Req_S <= '1';
else
err_IDLE_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_IDLE_grant_S <= '1';
else
err_IDLE_grant_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_Req_S <= '1';
else
err_North_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_North_grant_S <= '1';
else
err_North_grant_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_Req_L <= '1';
else
err_East_Req_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0') then
err_East_grant_L <= '1';
else
err_East_grant_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_Req_N <= '1';
else
err_West_Req_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0') then
err_West_grant_N <= '1';
else
err_West_grant_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_Req_E <= '1';
else
err_South_Req_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0') then
err_South_grant_E <= '1';
else
err_South_grant_E <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_Req_W <= '1';
else
err_Local_Req_W <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0') then
err_Local_grant_W <= '1';
else
err_Local_grant_W <= '0';
end if;
end process;
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-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_Req_L <= '1';
else
err_IDLE_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_IDLE_grant_L <= '1';
else
err_IDLE_grant_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_Req_L <= '1';
else
err_North_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_North_grant_L <= '1';
else
err_North_grant_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_Req_N <= '1';
else
err_East_Req_N <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0' ) then
err_East_grant_N <= '1';
else
err_East_grant_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_Req_E <= '1';
else
err_West_Req_E <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0' ) then
err_West_grant_E <= '1';
else
err_West_grant_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_Req_W <= '1';
else
err_South_Req_W <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0' ) then
err_South_grant_W <= '1';
else
err_South_grant_W <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_Req_S <= '1';
else
err_Local_Req_S <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0' ) then
err_Local_grant_S <= '1';
else
err_Local_grant_S <= '0';
end if;
end process;
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process (state_in)
begin
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
else
err_no_request_grants <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests /= "00000" and Grants = "00000") then
err_request_no_grants <= '1';
else
err_request_no_grants <= '0';
end if;
end process;
process (req_X_N, X_N)
begin
if (req_X_N = '0' and X_N = '1') then
err_no_Req_N_grant_N <= '1';
else
err_no_Req_N_grant_N <= '0';
end if;
end process;
process (req_X_E, X_E)
begin
if (req_X_E = '0' and X_E = '1') then
err_no_Req_E_grant_E <= '1';
else
err_no_Req_E_grant_E <= '0';
end if;
end process;
process (req_X_W, X_W)
begin
if (req_X_W = '0' and X_W = '1') then
err_no_Req_W_grant_W <= '1';
else
err_no_Req_W_grant_W <= '0';
end if;
end process;
process (req_X_S, X_S)
begin
if (req_X_S = '0' and X_S = '1') then
err_no_Req_S_grant_S <= '1';
else
err_no_Req_S_grant_S <= '0';
end if;
end process;
process (req_X_L, X_L)
begin
if (req_X_L = '0' and X_L = '1') then
err_no_Req_L_grant_L <= '1';
else
err_no_Req_L_grant_L <= '0';
end if;
end process;
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_in_one_hot_checkers is
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_checkers;
architecture behavior of Arbiter_in_one_hot_checkers is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= X_N & X_E & X_W & X_S & X_L;
-- Checkers
--checked
process (state, Requests, state_in)
begin
--if ( (state = North or state = East or state = West or state = South or state = Local or state = IDLE) and Requests = "00000" and state_in /= state ) then
if (Requests = "00000" and state_in /= state ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
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-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_Req_N <= '1';
else
err_IDLE_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = IDLE and req_X_N = '1' and X_N = '0' ) then
err_IDLE_grant_N <= '1';
else
err_IDLE_grant_N <= '0';
end if;
end process;
process (state, req_X_N, state_in)
begin
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_Req_N <= '1';
else
err_North_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = North and req_X_N = '1' and X_N = '0' ) then
err_North_grant_N <= '1';
else
err_North_grant_N <= '0';
end if;
end process;
process (state, req_X_E, state_in)
begin
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_Req_E <= '1';
else
err_East_Req_E <= '0';
end if;
end process;
process (state, req_X_E, X_E)
begin
if ( state = East and req_X_E = '1' and X_E = '0' ) then
err_East_grant_E <= '1';
else
err_East_grant_E <= '0';
end if;
end process;
process (state, req_X_W, state_in)
begin
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_Req_W <= '1';
else
err_West_Req_W <= '0';
end if;
end process;
process (state, req_X_W, X_W)
begin
if ( state = West and req_X_W = '1' and X_W = '0' ) then
err_West_grant_W <= '1';
else
err_West_grant_W <= '0';
end if;
end process;
process (state, req_X_S, state_in)
begin
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_Req_S <= '1';
else
err_South_Req_S <= '0';
end if;
end process;
process (state, req_X_S, X_S)
begin
if ( state = South and req_X_S = '1' and X_S = '0' ) then
err_South_grant_S <= '1';
else
err_South_grant_S <= '0';
end if;
end process;
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_Req_L <= '1';
else
err_Local_Req_L <= '0';
end if;
end process;
process (state, req_X_L, X_L)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and X_L = '0' ) then
err_Local_grant_L <= '1';
else
err_Local_grant_L <= '0';
end if;
end process;
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-- Round 2
--checked
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_Req_E <= '1';
else
err_IDLE_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_IDLE_grant_E <= '1';
else
err_IDLE_grant_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_Req_E <= '1';
else
err_North_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_North_grant_E <= '1';
else
err_North_grant_E <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_Req_W <= '1';
else
err_East_Req_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, X_W)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_East_grant_W <= '1';
else
err_East_grant_W <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_Req_S <= '1';
else
err_West_Req_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, X_S)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_West_grant_S <= '1';
else
err_West_grant_S <= '0';
end if;
end process;
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_Req_L <= '1';
else
err_South_Req_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, X_L)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_South_grant_L <= '1';
else
err_South_grant_L <= '0';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_Req_N <= '1';
else
err_Local_Req_N <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, X_N)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_Local_grant_N <= '1';
else
err_Local_grant_N <= '0';
end if;
end process;
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-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_Req_W <= '1';
else
err_IDLE_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_IDLE_grant_W <= '1';
else
err_IDLE_grant_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_Req_W <= '1';
else
err_North_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_North_grant_W <= '1';
else
err_North_grant_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_Req_S <= '1';
else
err_East_Req_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_East_grant_S <= '1';
else
err_East_grant_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_Req_L <= '1';
else
err_West_Req_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_West_grant_L <= '1';
else
err_West_grant_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_Req_N <= '1';
else
err_South_Req_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_South_grant_N <= '1';
else
err_South_grant_N <= '0';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_Req_E <= '1';
else
err_Local_Req_E <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_Local_grant_E <= '1';
else
err_Local_grant_E <= '0';
end if;
end process;
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-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_Req_S <= '1';
else
err_IDLE_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_IDLE_grant_S <= '1';
else
err_IDLE_grant_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_Req_S <= '1';
else
err_North_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_North_grant_S <= '1';
else
err_North_grant_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_Req_L <= '1';
else
err_East_Req_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0') then
err_East_grant_L <= '1';
else
err_East_grant_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_Req_N <= '1';
else
err_West_Req_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0') then
err_West_grant_N <= '1';
else
err_West_grant_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_Req_E <= '1';
else
err_South_Req_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0') then
err_South_grant_E <= '1';
else
err_South_grant_E <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_Req_W <= '1';
else
err_Local_Req_W <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0') then
err_Local_grant_W <= '1';
else
err_Local_grant_W <= '0';
end if;
end process;
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-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_Req_L <= '1';
else
err_IDLE_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_IDLE_grant_L <= '1';
else
err_IDLE_grant_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_Req_L <= '1';
else
err_North_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_North_grant_L <= '1';
else
err_North_grant_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_Req_N <= '1';
else
err_East_Req_N <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0' ) then
err_East_grant_N <= '1';
else
err_East_grant_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_Req_E <= '1';
else
err_West_Req_E <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0' ) then
err_West_grant_E <= '1';
else
err_West_grant_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_Req_W <= '1';
else
err_South_Req_W <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0' ) then
err_South_grant_W <= '1';
else
err_South_grant_W <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_Req_S <= '1';
else
err_Local_Req_S <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0' ) then
err_Local_grant_S <= '1';
else
err_Local_grant_S <= '0';
end if;
end process;
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process (state_in)
begin
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
else
err_no_request_grants <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests /= "00000" and Grants = "00000") then
err_request_no_grants <= '1';
else
err_request_no_grants <= '0';
end if;
end process;
process (req_X_N, X_N)
begin
if (req_X_N = '0' and X_N = '1') then
err_no_Req_N_grant_N <= '1';
else
err_no_Req_N_grant_N <= '0';
end if;
end process;
process (req_X_E, X_E)
begin
if (req_X_E = '0' and X_E = '1') then
err_no_Req_E_grant_E <= '1';
else
err_no_Req_E_grant_E <= '0';
end if;
end process;
process (req_X_W, X_W)
begin
if (req_X_W = '0' and X_W = '1') then
err_no_Req_W_grant_W <= '1';
else
err_no_Req_W_grant_W <= '0';
end if;
end process;
process (req_X_S, X_S)
begin
if (req_X_S = '0' and X_S = '1') then
err_no_Req_S_grant_S <= '1';
else
err_no_Req_S_grant_S <= '0';
end if;
end process;
process (req_X_L, X_L)
begin
if (req_X_L = '0' and X_L = '1') then
err_no_Req_L_grant_L <= '1';
else
err_no_Req_L_grant_L <= '0';
end if;
end process;
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_in_one_hot_checkers is
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_checkers;
architecture behavior of Arbiter_in_one_hot_checkers is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= X_N & X_E & X_W & X_S & X_L;
-- Checkers
--checked
process (state, Requests, state_in)
begin
--if ( (state = North or state = East or state = West or state = South or state = Local or state = IDLE) and Requests = "00000" and state_in /= state ) then
if (Requests = "00000" and state_in /= state ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
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-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_Req_N <= '1';
else
err_IDLE_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = IDLE and req_X_N = '1' and X_N = '0' ) then
err_IDLE_grant_N <= '1';
else
err_IDLE_grant_N <= '0';
end if;
end process;
process (state, req_X_N, state_in)
begin
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_Req_N <= '1';
else
err_North_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = North and req_X_N = '1' and X_N = '0' ) then
err_North_grant_N <= '1';
else
err_North_grant_N <= '0';
end if;
end process;
process (state, req_X_E, state_in)
begin
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_Req_E <= '1';
else
err_East_Req_E <= '0';
end if;
end process;
process (state, req_X_E, X_E)
begin
if ( state = East and req_X_E = '1' and X_E = '0' ) then
err_East_grant_E <= '1';
else
err_East_grant_E <= '0';
end if;
end process;
process (state, req_X_W, state_in)
begin
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_Req_W <= '1';
else
err_West_Req_W <= '0';
end if;
end process;
process (state, req_X_W, X_W)
begin
if ( state = West and req_X_W = '1' and X_W = '0' ) then
err_West_grant_W <= '1';
else
err_West_grant_W <= '0';
end if;
end process;
process (state, req_X_S, state_in)
begin
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_Req_S <= '1';
else
err_South_Req_S <= '0';
end if;
end process;
process (state, req_X_S, X_S)
begin
if ( state = South and req_X_S = '1' and X_S = '0' ) then
err_South_grant_S <= '1';
else
err_South_grant_S <= '0';
end if;
end process;
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_Req_L <= '1';
else
err_Local_Req_L <= '0';
end if;
end process;
process (state, req_X_L, X_L)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and X_L = '0' ) then
err_Local_grant_L <= '1';
else
err_Local_grant_L <= '0';
end if;
end process;
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-- Round 2
--checked
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_Req_E <= '1';
else
err_IDLE_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_IDLE_grant_E <= '1';
else
err_IDLE_grant_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_Req_E <= '1';
else
err_North_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_North_grant_E <= '1';
else
err_North_grant_E <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_Req_W <= '1';
else
err_East_Req_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, X_W)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_East_grant_W <= '1';
else
err_East_grant_W <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_Req_S <= '1';
else
err_West_Req_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, X_S)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_West_grant_S <= '1';
else
err_West_grant_S <= '0';
end if;
end process;
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_Req_L <= '1';
else
err_South_Req_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, X_L)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_South_grant_L <= '1';
else
err_South_grant_L <= '0';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_Req_N <= '1';
else
err_Local_Req_N <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, X_N)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_Local_grant_N <= '1';
else
err_Local_grant_N <= '0';
end if;
end process;
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-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_Req_W <= '1';
else
err_IDLE_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_IDLE_grant_W <= '1';
else
err_IDLE_grant_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_Req_W <= '1';
else
err_North_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_North_grant_W <= '1';
else
err_North_grant_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_Req_S <= '1';
else
err_East_Req_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_East_grant_S <= '1';
else
err_East_grant_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_Req_L <= '1';
else
err_West_Req_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_West_grant_L <= '1';
else
err_West_grant_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_Req_N <= '1';
else
err_South_Req_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_South_grant_N <= '1';
else
err_South_grant_N <= '0';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_Req_E <= '1';
else
err_Local_Req_E <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_Local_grant_E <= '1';
else
err_Local_grant_E <= '0';
end if;
end process;
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-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_Req_S <= '1';
else
err_IDLE_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_IDLE_grant_S <= '1';
else
err_IDLE_grant_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_Req_S <= '1';
else
err_North_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_North_grant_S <= '1';
else
err_North_grant_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_Req_L <= '1';
else
err_East_Req_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0') then
err_East_grant_L <= '1';
else
err_East_grant_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_Req_N <= '1';
else
err_West_Req_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0') then
err_West_grant_N <= '1';
else
err_West_grant_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_Req_E <= '1';
else
err_South_Req_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0') then
err_South_grant_E <= '1';
else
err_South_grant_E <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_Req_W <= '1';
else
err_Local_Req_W <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0') then
err_Local_grant_W <= '1';
else
err_Local_grant_W <= '0';
end if;
end process;
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-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_Req_L <= '1';
else
err_IDLE_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_IDLE_grant_L <= '1';
else
err_IDLE_grant_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_Req_L <= '1';
else
err_North_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_North_grant_L <= '1';
else
err_North_grant_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_Req_N <= '1';
else
err_East_Req_N <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0' ) then
err_East_grant_N <= '1';
else
err_East_grant_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_Req_E <= '1';
else
err_West_Req_E <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0' ) then
err_West_grant_E <= '1';
else
err_West_grant_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_Req_W <= '1';
else
err_South_Req_W <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0' ) then
err_South_grant_W <= '1';
else
err_South_grant_W <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_Req_S <= '1';
else
err_Local_Req_S <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0' ) then
err_Local_grant_S <= '1';
else
err_Local_grant_S <= '0';
end if;
end process;
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process (state_in)
begin
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
else
err_no_request_grants <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests /= "00000" and Grants = "00000") then
err_request_no_grants <= '1';
else
err_request_no_grants <= '0';
end if;
end process;
process (req_X_N, X_N)
begin
if (req_X_N = '0' and X_N = '1') then
err_no_Req_N_grant_N <= '1';
else
err_no_Req_N_grant_N <= '0';
end if;
end process;
process (req_X_E, X_E)
begin
if (req_X_E = '0' and X_E = '1') then
err_no_Req_E_grant_E <= '1';
else
err_no_Req_E_grant_E <= '0';
end if;
end process;
process (req_X_W, X_W)
begin
if (req_X_W = '0' and X_W = '1') then
err_no_Req_W_grant_W <= '1';
else
err_no_Req_W_grant_W <= '0';
end if;
end process;
process (req_X_S, X_S)
begin
if (req_X_S = '0' and X_S = '1') then
err_no_Req_S_grant_S <= '1';
else
err_no_Req_S_grant_S <= '0';
end if;
end process;
process (req_X_L, X_L)
begin
if (req_X_L = '0' and X_L = '1') then
err_no_Req_L_grant_L <= '1';
else
err_no_Req_L_grant_L <= '0';
end if;
end process;
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_in_one_hot_checkers is
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_checkers;
architecture behavior of Arbiter_in_one_hot_checkers is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= X_N & X_E & X_W & X_S & X_L;
-- Checkers
--checked
process (state, Requests, state_in)
begin
--if ( (state = North or state = East or state = West or state = South or state = Local or state = IDLE) and Requests = "00000" and state_in /= state ) then
if (Requests = "00000" and state_in /= state ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
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-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_Req_N <= '1';
else
err_IDLE_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = IDLE and req_X_N = '1' and X_N = '0' ) then
err_IDLE_grant_N <= '1';
else
err_IDLE_grant_N <= '0';
end if;
end process;
process (state, req_X_N, state_in)
begin
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_Req_N <= '1';
else
err_North_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = North and req_X_N = '1' and X_N = '0' ) then
err_North_grant_N <= '1';
else
err_North_grant_N <= '0';
end if;
end process;
process (state, req_X_E, state_in)
begin
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_Req_E <= '1';
else
err_East_Req_E <= '0';
end if;
end process;
process (state, req_X_E, X_E)
begin
if ( state = East and req_X_E = '1' and X_E = '0' ) then
err_East_grant_E <= '1';
else
err_East_grant_E <= '0';
end if;
end process;
process (state, req_X_W, state_in)
begin
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_Req_W <= '1';
else
err_West_Req_W <= '0';
end if;
end process;
process (state, req_X_W, X_W)
begin
if ( state = West and req_X_W = '1' and X_W = '0' ) then
err_West_grant_W <= '1';
else
err_West_grant_W <= '0';
end if;
end process;
process (state, req_X_S, state_in)
begin
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_Req_S <= '1';
else
err_South_Req_S <= '0';
end if;
end process;
process (state, req_X_S, X_S)
begin
if ( state = South and req_X_S = '1' and X_S = '0' ) then
err_South_grant_S <= '1';
else
err_South_grant_S <= '0';
end if;
end process;
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_Req_L <= '1';
else
err_Local_Req_L <= '0';
end if;
end process;
process (state, req_X_L, X_L)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and X_L = '0' ) then
err_Local_grant_L <= '1';
else
err_Local_grant_L <= '0';
end if;
end process;
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-- Round 2
--checked
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_Req_E <= '1';
else
err_IDLE_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_IDLE_grant_E <= '1';
else
err_IDLE_grant_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_Req_E <= '1';
else
err_North_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_North_grant_E <= '1';
else
err_North_grant_E <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_Req_W <= '1';
else
err_East_Req_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, X_W)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_East_grant_W <= '1';
else
err_East_grant_W <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_Req_S <= '1';
else
err_West_Req_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, X_S)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_West_grant_S <= '1';
else
err_West_grant_S <= '0';
end if;
end process;
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_Req_L <= '1';
else
err_South_Req_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, X_L)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_South_grant_L <= '1';
else
err_South_grant_L <= '0';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_Req_N <= '1';
else
err_Local_Req_N <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, X_N)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_Local_grant_N <= '1';
else
err_Local_grant_N <= '0';
end if;
end process;
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-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_Req_W <= '1';
else
err_IDLE_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_IDLE_grant_W <= '1';
else
err_IDLE_grant_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_Req_W <= '1';
else
err_North_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_North_grant_W <= '1';
else
err_North_grant_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_Req_S <= '1';
else
err_East_Req_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_East_grant_S <= '1';
else
err_East_grant_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_Req_L <= '1';
else
err_West_Req_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_West_grant_L <= '1';
else
err_West_grant_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_Req_N <= '1';
else
err_South_Req_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_South_grant_N <= '1';
else
err_South_grant_N <= '0';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_Req_E <= '1';
else
err_Local_Req_E <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_Local_grant_E <= '1';
else
err_Local_grant_E <= '0';
end if;
end process;
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-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_Req_S <= '1';
else
err_IDLE_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_IDLE_grant_S <= '1';
else
err_IDLE_grant_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_Req_S <= '1';
else
err_North_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_North_grant_S <= '1';
else
err_North_grant_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_Req_L <= '1';
else
err_East_Req_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0') then
err_East_grant_L <= '1';
else
err_East_grant_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_Req_N <= '1';
else
err_West_Req_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0') then
err_West_grant_N <= '1';
else
err_West_grant_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_Req_E <= '1';
else
err_South_Req_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0') then
err_South_grant_E <= '1';
else
err_South_grant_E <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_Req_W <= '1';
else
err_Local_Req_W <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0') then
err_Local_grant_W <= '1';
else
err_Local_grant_W <= '0';
end if;
end process;
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-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_Req_L <= '1';
else
err_IDLE_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_IDLE_grant_L <= '1';
else
err_IDLE_grant_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_Req_L <= '1';
else
err_North_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_North_grant_L <= '1';
else
err_North_grant_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_Req_N <= '1';
else
err_East_Req_N <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0' ) then
err_East_grant_N <= '1';
else
err_East_grant_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_Req_E <= '1';
else
err_West_Req_E <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0' ) then
err_West_grant_E <= '1';
else
err_West_grant_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_Req_W <= '1';
else
err_South_Req_W <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0' ) then
err_South_grant_W <= '1';
else
err_South_grant_W <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_Req_S <= '1';
else
err_Local_Req_S <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0' ) then
err_Local_grant_S <= '1';
else
err_Local_grant_S <= '0';
end if;
end process;
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process (state_in)
begin
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
else
err_no_request_grants <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests /= "00000" and Grants = "00000") then
err_request_no_grants <= '1';
else
err_request_no_grants <= '0';
end if;
end process;
process (req_X_N, X_N)
begin
if (req_X_N = '0' and X_N = '1') then
err_no_Req_N_grant_N <= '1';
else
err_no_Req_N_grant_N <= '0';
end if;
end process;
process (req_X_E, X_E)
begin
if (req_X_E = '0' and X_E = '1') then
err_no_Req_E_grant_E <= '1';
else
err_no_Req_E_grant_E <= '0';
end if;
end process;
process (req_X_W, X_W)
begin
if (req_X_W = '0' and X_W = '1') then
err_no_Req_W_grant_W <= '1';
else
err_no_Req_W_grant_W <= '0';
end if;
end process;
process (req_X_S, X_S)
begin
if (req_X_S = '0' and X_S = '1') then
err_no_Req_S_grant_S <= '1';
else
err_no_Req_S_grant_S <= '0';
end if;
end process;
process (req_X_L, X_L)
begin
if (req_X_L = '0' and X_L = '1') then
err_no_Req_L_grant_L <= '1';
else
err_no_Req_L_grant_L <= '0';
end if;
end process;
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_in_one_hot_checkers is
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_checkers;
architecture behavior of Arbiter_in_one_hot_checkers is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= X_N & X_E & X_W & X_S & X_L;
-- Checkers
--checked
process (state, Requests, state_in)
begin
--if ( (state = North or state = East or state = West or state = South or state = Local or state = IDLE) and Requests = "00000" and state_in /= state ) then
if (Requests = "00000" and state_in /= state ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
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-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_Req_N <= '1';
else
err_IDLE_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = IDLE and req_X_N = '1' and X_N = '0' ) then
err_IDLE_grant_N <= '1';
else
err_IDLE_grant_N <= '0';
end if;
end process;
process (state, req_X_N, state_in)
begin
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_Req_N <= '1';
else
err_North_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = North and req_X_N = '1' and X_N = '0' ) then
err_North_grant_N <= '1';
else
err_North_grant_N <= '0';
end if;
end process;
process (state, req_X_E, state_in)
begin
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_Req_E <= '1';
else
err_East_Req_E <= '0';
end if;
end process;
process (state, req_X_E, X_E)
begin
if ( state = East and req_X_E = '1' and X_E = '0' ) then
err_East_grant_E <= '1';
else
err_East_grant_E <= '0';
end if;
end process;
process (state, req_X_W, state_in)
begin
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_Req_W <= '1';
else
err_West_Req_W <= '0';
end if;
end process;
process (state, req_X_W, X_W)
begin
if ( state = West and req_X_W = '1' and X_W = '0' ) then
err_West_grant_W <= '1';
else
err_West_grant_W <= '0';
end if;
end process;
process (state, req_X_S, state_in)
begin
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_Req_S <= '1';
else
err_South_Req_S <= '0';
end if;
end process;
process (state, req_X_S, X_S)
begin
if ( state = South and req_X_S = '1' and X_S = '0' ) then
err_South_grant_S <= '1';
else
err_South_grant_S <= '0';
end if;
end process;
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_Req_L <= '1';
else
err_Local_Req_L <= '0';
end if;
end process;
process (state, req_X_L, X_L)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and X_L = '0' ) then
err_Local_grant_L <= '1';
else
err_Local_grant_L <= '0';
end if;
end process;
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-- Round 2
--checked
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_Req_E <= '1';
else
err_IDLE_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_IDLE_grant_E <= '1';
else
err_IDLE_grant_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_Req_E <= '1';
else
err_North_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_North_grant_E <= '1';
else
err_North_grant_E <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_Req_W <= '1';
else
err_East_Req_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, X_W)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_East_grant_W <= '1';
else
err_East_grant_W <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_Req_S <= '1';
else
err_West_Req_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, X_S)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_West_grant_S <= '1';
else
err_West_grant_S <= '0';
end if;
end process;
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_Req_L <= '1';
else
err_South_Req_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, X_L)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_South_grant_L <= '1';
else
err_South_grant_L <= '0';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_Req_N <= '1';
else
err_Local_Req_N <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, X_N)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_Local_grant_N <= '1';
else
err_Local_grant_N <= '0';
end if;
end process;
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-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_Req_W <= '1';
else
err_IDLE_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_IDLE_grant_W <= '1';
else
err_IDLE_grant_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_Req_W <= '1';
else
err_North_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_North_grant_W <= '1';
else
err_North_grant_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_Req_S <= '1';
else
err_East_Req_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_East_grant_S <= '1';
else
err_East_grant_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_Req_L <= '1';
else
err_West_Req_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_West_grant_L <= '1';
else
err_West_grant_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_Req_N <= '1';
else
err_South_Req_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_South_grant_N <= '1';
else
err_South_grant_N <= '0';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_Req_E <= '1';
else
err_Local_Req_E <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_Local_grant_E <= '1';
else
err_Local_grant_E <= '0';
end if;
end process;
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-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_Req_S <= '1';
else
err_IDLE_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_IDLE_grant_S <= '1';
else
err_IDLE_grant_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_Req_S <= '1';
else
err_North_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_North_grant_S <= '1';
else
err_North_grant_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_Req_L <= '1';
else
err_East_Req_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0') then
err_East_grant_L <= '1';
else
err_East_grant_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_Req_N <= '1';
else
err_West_Req_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0') then
err_West_grant_N <= '1';
else
err_West_grant_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_Req_E <= '1';
else
err_South_Req_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0') then
err_South_grant_E <= '1';
else
err_South_grant_E <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_Req_W <= '1';
else
err_Local_Req_W <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0') then
err_Local_grant_W <= '1';
else
err_Local_grant_W <= '0';
end if;
end process;
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-----------------------------------------------------------------------------------------------------------------------
-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_Req_L <= '1';
else
err_IDLE_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_IDLE_grant_L <= '1';
else
err_IDLE_grant_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_Req_L <= '1';
else
err_North_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_North_grant_L <= '1';
else
err_North_grant_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_Req_N <= '1';
else
err_East_Req_N <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0' ) then
err_East_grant_N <= '1';
else
err_East_grant_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_Req_E <= '1';
else
err_West_Req_E <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0' ) then
err_West_grant_E <= '1';
else
err_West_grant_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_Req_W <= '1';
else
err_South_Req_W <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0' ) then
err_South_grant_W <= '1';
else
err_South_grant_W <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_Req_S <= '1';
else
err_Local_Req_S <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0' ) then
err_Local_grant_S <= '1';
else
err_Local_grant_S <= '0';
end if;
end process;
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-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
process (state_in)
begin
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
else
err_no_request_grants <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests /= "00000" and Grants = "00000") then
err_request_no_grants <= '1';
else
err_request_no_grants <= '0';
end if;
end process;
process (req_X_N, X_N)
begin
if (req_X_N = '0' and X_N = '1') then
err_no_Req_N_grant_N <= '1';
else
err_no_Req_N_grant_N <= '0';
end if;
end process;
process (req_X_E, X_E)
begin
if (req_X_E = '0' and X_E = '1') then
err_no_Req_E_grant_E <= '1';
else
err_no_Req_E_grant_E <= '0';
end if;
end process;
process (req_X_W, X_W)
begin
if (req_X_W = '0' and X_W = '1') then
err_no_Req_W_grant_W <= '1';
else
err_no_Req_W_grant_W <= '0';
end if;
end process;
process (req_X_S, X_S)
begin
if (req_X_S = '0' and X_S = '1') then
err_no_Req_S_grant_S <= '1';
else
err_no_Req_S_grant_S <= '0';
end if;
end process;
process (req_X_L, X_L)
begin
if (req_X_L = '0' and X_L = '1') then
err_no_Req_L_grant_L <= '1';
else
err_no_Req_L_grant_L <= '0';
end if;
end process;
end behavior; |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
--use IEEE.math_real."ceil";
--use IEEE.math_real."log2";
entity fault_injector is
generic(
DATA_WIDTH : integer := 32;
ADDRESS_WIDTH : integer := 5
);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector (ADDRESS_WIDTH-1 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end fault_injector;
architecture behavior of fault_injector is
signal mask: std_logic_vector (DATA_WIDTH-1 downto 0);
begin
-- data_in | sta_0 | sta_1 | data_out
-- --------|--------|--------|----------
-- 0 | 0 | 0 | 0
-- 1 | 0 | 0 | 1
-- X | 0 | 1 | 1
-- X | 1 | 0 | 0
process (address) begin
mask <= (others => '0');
mask(to_integer(unsigned(address))) <= '1';
end process;
Gen_faulty:
for i in 0 to DATA_WIDTH-1 generate
data_out(i) <= (not mask(i) and data_in(i)) or (mask(i) and not sta_0 and not sta_1 and data_in(i)) or (mask(i) and sta_1 and not sta_0) ;
--data_out(i) <= data_in(i);
end generate;
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
--use IEEE.math_real."ceil";
--use IEEE.math_real."log2";
entity fault_injector is
generic(
DATA_WIDTH : integer := 32;
ADDRESS_WIDTH : integer := 5
);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector (ADDRESS_WIDTH-1 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end fault_injector;
architecture behavior of fault_injector is
signal mask: std_logic_vector (DATA_WIDTH-1 downto 0);
begin
-- data_in | sta_0 | sta_1 | data_out
-- --------|--------|--------|----------
-- 0 | 0 | 0 | 0
-- 1 | 0 | 0 | 1
-- X | 0 | 1 | 1
-- X | 1 | 0 | 0
process (address) begin
mask <= (others => '0');
mask(to_integer(unsigned(address))) <= '1';
end process;
Gen_faulty:
for i in 0 to DATA_WIDTH-1 generate
data_out(i) <= (not mask(i) and data_in(i)) or (mask(i) and not sta_0 and not sta_1 and data_in(i)) or (mask(i) and sta_1 and not sta_0) ;
--data_out(i) <= data_in(i);
end generate;
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
--use IEEE.math_real."ceil";
--use IEEE.math_real."log2";
entity fault_injector is
generic(
DATA_WIDTH : integer := 32;
ADDRESS_WIDTH : integer := 5
);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector (ADDRESS_WIDTH-1 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end fault_injector;
architecture behavior of fault_injector is
signal mask: std_logic_vector (DATA_WIDTH-1 downto 0);
begin
-- data_in | sta_0 | sta_1 | data_out
-- --------|--------|--------|----------
-- 0 | 0 | 0 | 0
-- 1 | 0 | 0 | 1
-- X | 0 | 1 | 1
-- X | 1 | 0 | 0
process (address) begin
mask <= (others => '0');
mask(to_integer(unsigned(address))) <= '1';
end process;
Gen_faulty:
for i in 0 to DATA_WIDTH-1 generate
data_out(i) <= (not mask(i) and data_in(i)) or (mask(i) and not sta_0 and not sta_1 and data_in(i)) or (mask(i) and sta_1 and not sta_0) ;
--data_out(i) <= data_in(i);
end generate;
end; |
chain: entity e5
|
--------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <ccl@xunit.de>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file labeling.vhd
--! @brief Connected Component Labeling two pass
--! @author Benjamin Bässler
--! @email ccl@xunit.de
--! @date 2013-06-04
--------------------------------------------------------------------------------
--! Use standard library
library ieee;
--! Use numeric std
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.types.all;
use work.utils.all;
--! The first pass of the labeling algorithm
entity labeling is
generic(
--! Max image width
G_MAX_IMG_WIDTH : NATURAL := C_MAX_IMAGE_WIDTH;
--! Max image height
G_MAX_IMG_HEIGHT : NATURAL := C_MAX_IMAGE_HEIGHT
);
port(
--! Clock input
clk_in : in STD_LOGIC;
--! Reset input
rst_in : in STD_LOGIC;
--! Output if the chain resolution stalls
stall_out : out STD_LOGIC;
--! Stall the output of the labeling
stall_in : in STD_LOGIC;
--! Pixel input 0 => background, 1=> foreground
px_in : in STD_LOGIC;
--! width of the image at the input
img_width_in : in STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_WIDTH) downto 0);
--! height of the image
img_height_in : in STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_HEIGHT) downto 0);
--! output data are valid
data_valid_out : out STD_LOGIC;
--! input data are valid
data_valid_in : in STD_LOGIC;
--! Signal rises if the last label of this image at output
last_lbl_out : out STD_LOGIC;
--! output of labeled image
label_out : out STD_LOGIC_VECTOR(T_LABEL'RANGE);
error_out : out STD_LOGIC
);
end entity labeling;
--! @brief arc description
--! @details more detailed description
architecture labeling_arc of labeling is
constant C_INSTANCES : natural := 3;
type T_STATE is (LABLING_P1, WAIT_LOOKUP, LABLING_P2, PRERESET, RESET);
Signal state_s : T_STATE;
type T_LABEL_VECTOR is array (C_INSTANCES - 1 downto 0) of T_LABEL;
type T_EQUI_VECTOR is array (C_INSTANCES - 1 downto 0) of T_EQUI;
-- Singals in generate statement
Signal lu_next_lbl_out_s : T_LABEL;
Signal lu_gen_lable_in_s : STD_LOGIC;
Signal lu_equi_in_s : T_EQUI;
Signal lu_ready_out_s : STD_LOGIC;
Signal lu_lbl_out_s : T_LABEL;
Signal lu_last_s : STD_LOGIC;
Signal st_px_valid_in_s : STD_LOGIC;
Signal st_rd_px_in_s : STD_LOGIC;
Signal st_rd_px_out_s : STD_LOGIC;
Signal st_rd_valid_out_s : STD_LOGIC;
Signal st_rd_last_out_s : STD_LOGIC;
Signal st_rd_slast_out_s : STD_LOGIC;
Signal rst_lbl_cnt_s : STD_LOGIC;
Signal stall_out_s : STD_LOGIC;
Signal last_lbl_s : STD_LOGIC;
Signal slast_lbl_s : STD_LOGIC;
Signal cnt_lbl2_s : T_LABEL;
Signal inc_lbl2_s : STD_LOGIC;
Signal next_gen_in_s : T_LABEL;
Signal gen_lable_out_s : STD_LOGIC;
Signal equi_out_s : T_EQUI;
Signal equi_valid_out_s : STD_LOGIC;
Signal p2_lbl_s : T_LABEL;
Signal rst_lbl_s : STD_LOGIC;
Signal px_lbl_in_s : STD_LOGIC;
Signal px_lbl_vl_in_s : STD_LOGIC;
Signal lbl_out_s : T_LABEL;
Signal lbl_vl_out_s : STD_LOGIC;
Signal rst_lu_s : STD_LOGIC;
Signal lu_equi_in_vl_s : STD_LOGIC;
Signal rst_px_st_s : STD_LOGIC;
begin
stall_out <= '0';
--! Finite State Machine for internal state
p_state : process (clk_in, rst_in) is
begin
if rst_in = '1' then
state_s <= LABLING_P1;
elsif rising_edge(clk_in) then
case state_s is
when LABLING_P1 =>
if last_lbl_s = '1' then
state_s <= WAIT_LOOKUP;
end if;
when WAIT_LOOKUP =>
if lu_ready_out_s = '1' then
state_s <= LABLING_P2;
end if;
when LABLING_P2 =>
if st_rd_last_out_s = '1' then
state_s <= PRERESET;
end if;
when PRERESET =>
state_s <= RESET;
when RESET =>
state_s <= LABLING_P1;
end case;
end if; -- clk/rst
end process p_state;
p_state_signals : process (state_s, rst_in, px_in,
data_valid_in, lu_next_lbl_out_s,
gen_lable_out_s, equi_out_s,
equi_valid_out_s, st_rd_px_out_s,
cnt_lbl2_s, lbl_out_s, lu_lbl_out_s,
st_rd_valid_out_s
) is
begin
-- default values
rst_lbl_s <= '0';
rst_lbl_cnt_s <= '0';
rst_lu_s <= '0';
px_lbl_in_s <= '-';
next_gen_in_s <= (others => '-');
lu_gen_lable_in_s <= '0';
lu_equi_in_s <= (others => (others => '-'));
lu_equi_in_vl_s <= '0';
px_lbl_vl_in_s <= '0';
inc_lbl2_s <= '0';
p2_lbl_s <= (others => '-');
label_out <= (others => '-');
last_lbl_out <= '0';
rst_px_st_s <= '0';
st_rd_px_in_s <= '0';
lu_last_s <= '0';
st_px_valid_in_s <= '0';
case state_s is
when LABLING_P1 =>
px_lbl_in_s <= px_in;
px_lbl_vl_in_s <= data_valid_in;
next_gen_in_s <= lu_next_lbl_out_s;
lu_gen_lable_in_s <= gen_lable_out_s;
lu_equi_in_s <= equi_out_s;
lu_equi_in_vl_s <= equi_valid_out_s;
st_px_valid_in_s <= data_valid_in;
when WAIT_LOOKUP =>
rst_lbl_cnt_s <= '1';
rst_lbl_s <= '1';
when LABLING_P2 =>
px_lbl_in_s <= st_rd_px_out_s;
px_lbl_vl_in_s <= st_rd_valid_out_s;
next_gen_in_s <= cnt_lbl2_s;
inc_lbl2_s <= gen_lable_out_s;
p2_lbl_s <= lbl_out_s;
st_rd_px_in_s <= '1';
label_out <= std_logic_vector(lu_lbl_out_s);
when PRERESET =>
px_lbl_in_s <= st_rd_px_out_s;
px_lbl_vl_in_s <= st_rd_valid_out_s;
next_gen_in_s <= cnt_lbl2_s;
inc_lbl2_s <= gen_lable_out_s;
p2_lbl_s <= lbl_out_s;
label_out <= std_logic_vector(lu_lbl_out_s);
when RESET =>
rst_lbl_s <= '1';
rst_lu_s <= '1';
rst_lu_s <= '1';
rst_px_st_s <= '1';
label_out <= std_logic_vector(lu_lbl_out_s);
last_lbl_out <= '1';
end case;
if rst_in = '1' then
rst_lbl_s <= '1';
rst_lu_s <= '1';
rst_lu_s <= '1';
rst_px_st_s <= '1';
end if;
end process;
--!brief delay the data_valid_out by one
p_vl_d : process (clk_in, rst_in) is
begin
if rst_in = '1' then
lbl_vl_out_s <= '0';
data_valid_out <= '0';
elsif rising_edge(clk_in) then
lbl_vl_out_s <= px_lbl_vl_in_s;
data_valid_out <= '0';
if state_s = LABLING_P2 or state_s = PRERESET then
-- if labling pass2 the output can be valid
data_valid_out <= lbl_vl_out_s;
end if;
end if;
end process;
labeling : entity work.labeling_p1 PORT MAP(
clk_in => clk_in,
rst_in => rst_lbl_s,
stall_out => stall_out_s,
stall_in => stall_in,
px_in => px_lbl_in_s,
px_valid_in => px_lbl_vl_in_s,
img_width_in => UNSIGNED(img_width_in),
img_height_in => UNSIGNED(img_height_in),
next_lable_in => next_gen_in_s,
gen_lable_out => gen_lable_out_s,
equi_out => equi_out_s,
equi_valid_out => equi_valid_out_s,
last_lbl_out => last_lbl_s,
slast_lbl_out => slast_lbl_s,
label_out => lbl_out_s
);
lookup_table : entity work.lookup_table PORT MAP(
clk_in => clk_in,
rst_in => rst_lu_s,
stall_out => open,
next_lable_out => lu_next_lbl_out_s,
gen_lable_in => lu_gen_lable_in_s,
equi_in => lu_equi_in_s,
equi_valid_in => lu_equi_in_vl_s,
lookup_ready_out=> lu_ready_out_s,
lookup_in => p2_lbl_s,
lookup_out => lu_lbl_out_s,
last_look_up_in => lu_last_s,
error_out => error_out
);
px_store : entity work.px_storage port map(
clk_in => clk_in,
rst_in => rst_px_st_s,
img_width_in => UNSIGNED(img_width_in),
img_height_in => UNSIGNED(img_height_in),
wr_px_in => px_in,
wr_valid_in => st_px_valid_in_s,
rd_px_in => st_rd_px_in_s,
rd_px_out => st_rd_px_out_s,
rd_valid_out => st_rd_valid_out_s,
rd_last_px_out => st_rd_last_out_s,
rd_slast_px_out => st_rd_slast_out_s
);
lbl_cnt_p2 : entity work.counter PORT MAP(
clk_in => clk_in,
rst_in => rst_lbl_cnt_s,
inc_in => inc_lbl2_s,
cnt_out => cnt_lbl2_s
);
end labeling_arc;
|
-------------------------------------------------------------------------------
--
-- The T8243 Core
-- This is the core module implementing all functionality of the
-- original 8243 chip.
--
-- $Id: t8243_core.vhd,v 1.2 2006-12-18 01:18:58 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee. std_logic_1164.all;
entity t8243_core is
generic (
clk_fall_level_g : integer := 0
);
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
clk_rise_en_i : in std_logic;
clk_fall_en_i : in std_logic;
reset_n_i : in std_logic;
-- Control Interface ------------------------------------------------------
cs_n_i : in std_logic;
prog_n_i : in std_logic;
-- Port 2 Interface -------------------------------------------------------
p2_i : in std_logic_vector(3 downto 0);
p2_o : out std_logic_vector(3 downto 0);
p2_en_o : out std_logic;
-- Port 4 Interface -------------------------------------------------------
p4_i : in std_logic_vector(3 downto 0);
p4_o : out std_logic_vector(3 downto 0);
p4_en_o : out std_logic;
-- Port 5 Interface -------------------------------------------------------
p5_i : in std_logic_vector(3 downto 0);
p5_o : out std_logic_vector(3 downto 0);
p5_en_o : out std_logic;
-- Port 6 Interface -------------------------------------------------------
p6_i : in std_logic_vector(3 downto 0);
p6_o : out std_logic_vector(3 downto 0);
p6_en_o : out std_logic;
-- Port 7 Interface -------------------------------------------------------
p7_i : in std_logic_vector(3 downto 0);
p7_o : out std_logic_vector(3 downto 0);
p7_en_o : out std_logic
);
end t8243_core;
library ieee;
use ieee.numeric_std.all;
architecture rtl of t8243_core is
function int2stdlogic_f(level_i : in integer) return std_logic is
begin
if level_i = 0 then
return '0';
else
return '1';
end if;
end;
constant clk_fall_level_c : std_logic := int2stdlogic_f(clk_fall_level_g);
type instr_t is (INSTR_READ, INSTR_WRITE, INSTR_ORLD, INSTR_ANLD);
signal instr_q : instr_t;
constant port_4_c : integer := 4;
constant port_5_c : integer := 5;
constant port_6_c : integer := 6;
constant port_7_c : integer := 7;
subtype port_range_t is natural range port_7_c downto port_4_c;
signal px_sel_q : std_logic_vector(port_range_t);
signal px_en_q : std_logic_vector(port_range_t);
signal p2_en_q : std_logic;
subtype port_vector_t is std_logic_vector(3 downto 0);
type four_ports_t is array (port_range_t) of port_vector_t;
signal px_latch_q : four_ports_t;
signal data_s : port_vector_t;
signal p2_s,
p4_s,
p5_s,
p6_s,
p7_s : port_vector_t;
begin
-- get rid of H and L
p2_s <= to_X01(p2_i);
p4_s <= to_X01(p4_i);
p5_s <= to_X01(p5_i);
p6_s <= to_X01(p6_i);
p7_s <= to_X01(p7_i);
-----------------------------------------------------------------------------
-- Process ctrl_seq
--
-- Purpose:
-- Implements the sequential elements that control the T8243 core.
-- * latch port number
-- * latch instruction
--
ctrl_seq: process (clk_i, cs_n_i)
begin
if cs_n_i = '1' then
px_sel_q <= (others => '0');
p2_en_q <= '0';
instr_q <= INSTR_WRITE;
elsif clk_i'event and clk_i = clk_fall_level_c then
if cs_n_i = '0' and clk_fall_en_i = '1' then
-- enable addressed port ----------------------------------------------
px_sel_q <= (others => '0');
px_sel_q(to_integer(unsigned(p2_s(1 downto 0))) +
port_range_t'low) <= '1';
p2_en_q <= '0';
-- decode instruction -------------------------------------------------
case p2_s(3 downto 2) is
when "00" =>
instr_q <= INSTR_READ;
p2_en_q <= '1';
when "01" =>
instr_q <= INSTR_WRITE;
when "10" =>
instr_q <= INSTR_ORLD;
when "11" =>
instr_q <= INSTR_ANLD;
when others =>
null;
end case;
end if;
end if;
end process ctrl_seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process port_seq
--
-- Purpose:
-- Implements the sequential elements of the four ports.
--
port_seq: process (clk_i, reset_n_i)
begin
if reset_n_i = '0' then
px_en_q <= (others => '0');
px_latch_q <= (others => (others => '0'));
elsif rising_edge(clk_i) then
if cs_n_i = '0' and clk_rise_en_i = '1' then
for idx in port_range_t loop
if px_sel_q(idx) = '1' then
if instr_q = INSTR_READ then
-- port is being read from, switch off output enable
px_en_q(idx) <= '0';
else
-- port is being written to, enable output
px_en_q(idx) <= '1';
-- and latch value
px_latch_q(idx) <= data_s;
end if;
end if;
end loop;
end if;
end if;
end process port_seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process data_gen
--
-- Purpose:
-- Generates the data for the four port latches.
-- * determines data inputs
-- * calculates result of instruction
--
-- Multiplexes the read value for P2.
--
data_gen: process (px_sel_q,
instr_q,
p2_s,
px_latch_q,
p4_s, p5_s, p6_s, p7_s)
variable port_v : port_vector_t;
begin
-- select addressed port
case px_sel_q is
when "0001" =>
port_v := px_latch_q(port_4_c);
p2_o <= p4_s;
when "0010" =>
port_v := px_latch_q(port_5_c);
p2_o <= p5_s;
when "0100" =>
port_v := px_latch_q(port_6_c);
p2_o <= p6_s;
when "1000" =>
port_v := px_latch_q(port_7_c);
p2_o <= p7_s;
when others =>
port_v := (others => '-');
p2_o <= (others => '-');
end case;
case instr_q is
when INSTR_WRITE =>
data_s <= p2_s;
when INSTR_ORLD =>
data_s <= p2_s or port_v;
when INSTR_ANLD =>
data_s <= p2_s and port_v;
when others =>
data_s <= (others => '-');
end case;
end process;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
p2_en_o <= '1'
when cs_n_i = '0' and prog_n_i = '0' and p2_en_q = '1' else
'0';
p4_o <= px_latch_q(port_4_c);
p4_en_o <= px_en_q(port_4_c);
p5_o <= px_latch_q(port_5_c);
p5_en_o <= px_en_q(port_5_c);
p6_o <= px_latch_q(port_6_c);
p6_en_o <= px_en_q(port_6_c);
p7_o <= px_latch_q(port_7_c);
p7_en_o <= px_en_q(port_7_c);
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2006/07/13 22:53:56 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Title : Package for Infrared transmitter
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.motor_control_pkg.all;
use work.bus_pkg.all;
package ir_tx_pkg is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component ir_tx_module
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#);
port (
ir_tx_p : out std_logic;
modulation_p : in std_logic;
clk_ir_enable_p : out std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic);
end component;
end ir_tx_pkg;
|
-------------------------------------------------------------------------------
-- Title : Package for Infrared transmitter
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.motor_control_pkg.all;
use work.bus_pkg.all;
package ir_tx_pkg is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component ir_tx_module
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#);
port (
ir_tx_p : out std_logic;
modulation_p : in std_logic;
clk_ir_enable_p : out std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic);
end component;
end ir_tx_pkg;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236S.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (synth'able) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236s IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236s;
ARCHITECTURE syn OF hcc_mul3236s IS
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (2*width-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => width,
width_b => width,
width_result => 2*width
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulcc
);
END syn;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236S.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (synth'able) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236s IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236s;
ARCHITECTURE syn OF hcc_mul3236s IS
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (2*width-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => width,
width_b => width,
width_result => 2*width
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulcc
);
END syn;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236S.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (synth'able) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236s IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236s;
ARCHITECTURE syn OF hcc_mul3236s IS
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (2*width-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => width,
width_b => width,
width_result => 2*width
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulcc
);
END syn;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236S.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (synth'able) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236s IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236s;
ARCHITECTURE syn OF hcc_mul3236s IS
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (2*width-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => width,
width_b => width,
width_result => 2*width
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulcc
);
END syn;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236S.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (synth'able) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236s IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236s;
ARCHITECTURE syn OF hcc_mul3236s IS
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (2*width-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => width,
width_b => width,
width_result => 2*width
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulcc
);
END syn;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236S.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (synth'able) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236s IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236s;
ARCHITECTURE syn OF hcc_mul3236s IS
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (2*width-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => width,
width_b => width,
width_result => 2*width
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulcc
);
END syn;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236S.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (synth'able) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236s IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236s;
ARCHITECTURE syn OF hcc_mul3236s IS
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (2*width-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => width,
width_b => width,
width_result => 2*width
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulcc
);
END syn;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236S.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (synth'able) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236s IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236s;
ARCHITECTURE syn OF hcc_mul3236s IS
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (2*width-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => width,
width_b => width,
width_result => 2*width
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulcc
);
END syn;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236S.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (synth'able) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236s IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236s;
ARCHITECTURE syn OF hcc_mul3236s IS
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (2*width-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => width,
width_b => width,
width_result => 2*width
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulcc
);
END syn;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236S.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (synth'able) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236s IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236s;
ARCHITECTURE syn OF hcc_mul3236s IS
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (2*width-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => width,
width_b => width,
width_result => 2*width
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulcc
);
END syn;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNTVBNRAAT is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "(a=b) or (a=c)";
number_inputs : integer := 3;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0);
c : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNTVBNRAAT is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc((a=b) or (a=c)) ;
true <= result;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNTVBNRAAT is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "(a=b) or (a=c)";
number_inputs : integer := 3;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0);
c : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNTVBNRAAT is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc((a=b) or (a=c)) ;
true <= result;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNTVBNRAAT is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "(a=b) or (a=c)";
number_inputs : integer := 3;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0);
c : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNTVBNRAAT is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc((a=b) or (a=c)) ;
true <= result;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNTVBNRAAT is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "(a=b) or (a=c)";
number_inputs : integer := 3;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0);
c : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNTVBNRAAT is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc((a=b) or (a=c)) ;
true <= result;
end architecture;
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter11.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter11 IS
PORT
(
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_counter11;
ARCHITECTURE SYN OF lpm_counter11 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 8
)
PORT MAP (
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter11.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter11.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter11.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter11.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter11_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use packageha4bit00.all;
entity topha4bit00 is
port(
A0: in std_logic ;
B0: in std_logic ;
S0: out std_logic ;
C0: out std_logic );
end;
architecture topha4bit0 of topha4bit00 is
begin
U1: and00 port map(Aa => A0,
Ba => B0,
Ya => C0);
U2: xor00 port map(Ax => A0,
Bx => B0,
Yx => S0);
end topha4bit0;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity feedforward_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
P_mode :out STD_LOGIC_VECTOR(31 downto 0)
);
end entity feedforward_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of P_mode
-- bit 31~0 - P_mode[31:0] (Read/Write)
-- 0x14 : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of feedforward_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_P_MODE_DATA_0 : INTEGER := 16#10#;
constant ADDR_P_MODE_CTRL : INTEGER := 16#14#;
constant ADDR_BITS : INTEGER := 5;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
signal int_P_mode : UNSIGNED(31 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_P_MODE_DATA_0 =>
rdata_data <= RESIZE(int_P_mode(31 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
P_mode <= STD_LOGIC_VECTOR(int_P_mode);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_MODE_DATA_0) then
int_P_mode(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_mode(31 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity feedforward_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
P_mode :out STD_LOGIC_VECTOR(31 downto 0)
);
end entity feedforward_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of P_mode
-- bit 31~0 - P_mode[31:0] (Read/Write)
-- 0x14 : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of feedforward_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_P_MODE_DATA_0 : INTEGER := 16#10#;
constant ADDR_P_MODE_CTRL : INTEGER := 16#14#;
constant ADDR_BITS : INTEGER := 5;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
signal int_P_mode : UNSIGNED(31 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_P_MODE_DATA_0 =>
rdata_data <= RESIZE(int_P_mode(31 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
P_mode <= STD_LOGIC_VECTOR(int_P_mode);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_MODE_DATA_0) then
int_P_mode(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_mode(31 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity feedforward_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
P_mode :out STD_LOGIC_VECTOR(31 downto 0)
);
end entity feedforward_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of P_mode
-- bit 31~0 - P_mode[31:0] (Read/Write)
-- 0x14 : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of feedforward_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_P_MODE_DATA_0 : INTEGER := 16#10#;
constant ADDR_P_MODE_CTRL : INTEGER := 16#14#;
constant ADDR_BITS : INTEGER := 5;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
signal int_P_mode : UNSIGNED(31 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_P_MODE_DATA_0 =>
rdata_data <= RESIZE(int_P_mode(31 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
P_mode <= STD_LOGIC_VECTOR(int_P_mode);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_MODE_DATA_0) then
int_P_mode(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_mode(31 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for __COMMON__
--
-- Generated
-- by: wig
-- on: Mon Oct 10 12:25:03 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: bitsplice-c.vhd,v 1.2 2005/11/30 14:20:41 wig Exp $
-- $Date: 2005/11/30 14:20:41 $
-- $Log: bitsplice-c.vhd,v $
-- Revision 1.2 2005/11/30 14:20:41 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.59 2005/10/06 11:21:44 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.37 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_a_e_rtl_conf / inst_a_e
--
configuration inst_a_e_rtl_conf of inst_a_e is
for rtl
-- Generated Configuration
for inst_aa : ent_aa
use configuration work.ent_aa_RTL_CONF;
end for;
for inst_ab : ent_ab
use configuration work.ent_ab_RTL_CONF;
end for;
for inst_ac : ent_ac
use configuration work.ent_ac_RTL_CONF;
end for;
for inst_ad : ent_ad
use configuration work.ent_ad_RTL_CONF;
end for;
for inst_ae : ent_ae
use configuration work.ent_ae_RTL_CONF;
end for;
end for;
end inst_a_e_rtl_conf;
--
-- End of Generated Configuration inst_a_e_rtl_conf
--
--
-- Start of Generated Configuration inst_b_e_rtl_conf / inst_b_e
--
configuration inst_b_e_rtl_conf of inst_b_e is
for rtl
-- Generated Configuration
for inst_ba : ent_ba
use configuration work.ent_ba_RTL_CONF;
end for;
for inst_bb : ent_bb
use configuration work.ent_bb_RTL_CONF;
end for;
end for;
end inst_b_e_rtl_conf;
--
-- End of Generated Configuration inst_b_e_rtl_conf
--
--
-- Start of Generated Configuration inst_e_e_rtl_conf / inst_e_e
--
configuration inst_e_e_rtl_conf of inst_e_e is
for rtl
-- Generated Configuration
for inst_ea : inst_ea_e
use configuration work.inst_ea_e_rtl_conf;
end for;
for inst_eb : inst_eb_e
use configuration work.inst_eb_e_rtl_conf;
end for;
for inst_ec : inst_ec_e
use configuration work.inst_ec_e_rtl_conf;
end for;
for inst_ed : inst_ed_e
use configuration work.inst_ed_e_rtl_conf;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_ee : inst_ee_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_ee_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_ef : inst_ef_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_ef_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_eg : inst_eg_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_eg_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end inst_e_e_rtl_conf;
--
-- End of Generated Configuration inst_e_e_rtl_conf
--
--
-- Start of Generated Configuration inst_ea_e_rtl_conf / inst_ea_e
--
configuration inst_ea_e_rtl_conf of inst_ea_e is
for rtl
-- Generated Configuration
for inst_eaa : inst_eaa_e
use configuration work.inst_eaa_e_rtl_conf;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_eab : inst_eab_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_eab_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_eac : inst_eac_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_eac_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_ead : inst_ead_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_ead_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end inst_ea_e_rtl_conf;
--
-- End of Generated Configuration inst_ea_e_rtl_conf
--
--
-- Start of Generated Configuration inst_eb_e_rtl_conf / inst_eb_e
--
configuration inst_eb_e_rtl_conf of inst_eb_e is
for rtl
-- Generated Configuration
for inst_eba : inst_eba_e
use configuration work.inst_eba_e_rtl_conf;
end for;
for inst_ebb : inst_ebb_e
use configuration work.inst_ebb_e_rtl_conf;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_ebc : inst_ebc_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_ebc_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end inst_eb_e_rtl_conf;
--
-- End of Generated Configuration inst_eb_e_rtl_conf
--
--
-- Start of Generated Configuration inst_ec_e_rtl_conf / inst_ec_e
--
configuration inst_ec_e_rtl_conf of inst_ec_e is
for rtl
-- Generated Configuration
-- __I_NO_CONFIG_VERILOG --for inst_eca : inst_eca_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_eca_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_ecb : inst_ecb_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_ecb_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_ecc : inst_ecc_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_ecc_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end inst_ec_e_rtl_conf;
--
-- End of Generated Configuration inst_ec_e_rtl_conf
--
--
-- Start of Generated Configuration inst_ed_e_rtl_conf / inst_ed_e
--
configuration inst_ed_e_rtl_conf of inst_ed_e is
for rtl
-- Generated Configuration
-- __I_NO_CONFIG_VERILOG --for inst_eda : inst_eda_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_eda_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for inst_edb : inst_edb_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_edb_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end inst_ed_e_rtl_conf;
--
-- End of Generated Configuration inst_ed_e_rtl_conf
--
--
-- Start of Generated Configuration inst_t_e_rtl_conf / inst_t_e
--
configuration inst_t_e_rtl_conf of inst_t_e is
for rtl
-- Generated Configuration
for inst_a : inst_a_e
use configuration work.inst_a_e_rtl_conf;
end for;
for inst_b : inst_b_e
use configuration work.inst_b_e_rtl_conf;
end for;
for inst_c : inst_c_e
use configuration work.inst_c_e_rtl_conf;
end for;
for inst_d : inst_d_e
use configuration work.inst_d_e_rtl_conf;
end for;
for inst_e : inst_e_e
use configuration work.inst_e_e_rtl_conf;
end for;
end for;
end inst_t_e_rtl_conf;
--
-- End of Generated Configuration inst_t_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief ROM storage with the boot image (4KB default = 16 x 256)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity nasti_bootrom is
generic (
memtech : integer := inferred;
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
sim_hexfile : string
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i : in nasti_slave_in_type;
o : out nasti_slave_out_type
);
end;
architecture arch_nasti_bootrom of nasti_bootrom is
constant xconfig : nasti_slave_config_type := (
xindex => xindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_BOOTROM,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
type registers is record
bank_axi : nasti_slave_bank_type;
end record;
signal r, rin : registers;
signal raddr_mux : global_addr_array_type;
signal rdata_mux : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
begin
comblogic : process(i, r, rdata_mux)
variable v : registers;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
begin
v := r;
procedureAxi4(i, xconfig, r.bank_axi, v.bank_axi);
raddr_mux <= functionAddressReorder(v.bank_axi.raddr(0)(3 downto 2),
v.bank_axi.raddr);
rdata := functionDataRestoreOrder(r.bank_axi.raddr(0)(3 downto 2),
rdata_mux);
o <= functionAxi4Output(r.bank_axi, rdata);
rin <= v;
end process;
cfg <= xconfig;
tech0 : BootRom_tech generic map (
memtech => memtech,
sim_hexfile => sim_hexfile
) port map (
clk => clk,
address => raddr_mux,
data => rdata_mux
);
-- registers:
regs : process(clk, nrst)
begin
if nrst = '0' then
r.bank_axi <= NASTI_SLAVE_BANK_RESET;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end; |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief ROM storage with the boot image (4KB default = 16 x 256)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity nasti_bootrom is
generic (
memtech : integer := inferred;
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
sim_hexfile : string
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i : in nasti_slave_in_type;
o : out nasti_slave_out_type
);
end;
architecture arch_nasti_bootrom of nasti_bootrom is
constant xconfig : nasti_slave_config_type := (
xindex => xindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_BOOTROM,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
type registers is record
bank_axi : nasti_slave_bank_type;
end record;
signal r, rin : registers;
signal raddr_mux : global_addr_array_type;
signal rdata_mux : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
begin
comblogic : process(i, r, rdata_mux)
variable v : registers;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
begin
v := r;
procedureAxi4(i, xconfig, r.bank_axi, v.bank_axi);
raddr_mux <= functionAddressReorder(v.bank_axi.raddr(0)(3 downto 2),
v.bank_axi.raddr);
rdata := functionDataRestoreOrder(r.bank_axi.raddr(0)(3 downto 2),
rdata_mux);
o <= functionAxi4Output(r.bank_axi, rdata);
rin <= v;
end process;
cfg <= xconfig;
tech0 : BootRom_tech generic map (
memtech => memtech,
sim_hexfile => sim_hexfile
) port map (
clk => clk,
address => raddr_mux,
data => rdata_mux
);
-- registers:
regs : process(clk, nrst)
begin
if nrst = '0' then
r.bank_axi <= NASTI_SLAVE_BANK_RESET;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end; |
entity issueD is
begin
end entity issueD;
architecture a of issueD is
component c is
generic (g : bit_vector);
end component c;
begin
u : c
generic map (g => (1 downto 0 => '1'));
end architecture a;
|
entity issueD is
begin
end entity issueD;
architecture a of issueD is
component c is
generic (g : bit_vector);
end component c;
begin
u : c
generic map (g => (1 downto 0 => '1'));
end architecture a;
|
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