content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_fg_17_14.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity test_bench is
end entity test_bench;
-- end not in book
library ieee; use ieee.std_logic_1164.all;
architecture initial_test of test_bench is
use work.stimulus_types.all;
-- . . . -- component and signal declarations
-- not in book
signal dut_signals : std_logic_vector(0 to stimulus_vector_length - 1);
-- end not in book
begin
-- . . . -- instantiate design under test
stimulus_generation : process is
use work.stimulus_element_ordered_collection_adt.all;
variable stimulus_list : ordered_collection := new_ordered_collection;
variable next_stimulus_position : position;
variable next_stimulus : stimulus_element;
variable position_is_null : boolean;
begin
insert(stimulus_list, stimulus_element'(0 ns, "0XXXXXXXXX"));
insert(stimulus_list, stimulus_element'(200 ns, "0000110110"));
insert(stimulus_list, stimulus_element'(300 ns, "10001ZZZZZ"));
insert(stimulus_list, stimulus_element'(50 ns, "1XXXXXXXXX"));
insert(stimulus_list, stimulus_element'(60 ns, "1ZZZZZZZZZ"));
-- . . .
-- not in book
insert(stimulus_list, stimulus_element'(100 ns, "----------"));
search(stimulus_list, 100 ns, next_stimulus_position);
delete(next_stimulus_position);
get_element(next_stimulus_position, next_stimulus);
-- end not in book
find_first(stimulus_list, next_stimulus_position);
loop
test_null_position(next_stimulus_position, position_is_null);
exit when position_is_null;
get_element(next_stimulus_position, next_stimulus);
wait for next_stimulus.application_time - now;
dut_signals <= next_stimulus.pattern;
advance(next_stimulus_position);
end loop;
wait;
end process stimulus_generation;
end architecture initial_test;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_m_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 08:31:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_m_e-rtl-a.vhd,v 1.2 2006/06/26 08:39:42 wig Exp $
-- $Date: 2006/06/26 08:39:42 $
-- $Log: inst_m_e-rtl-a.vhd,v $
-- Revision 1.2 2006/06/26 08:39:42 wig
-- Update more testcases (up to generic)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_m_e
--
architecture rtl of inst_m_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2cmst
-- File: i2cmst.vhd
-- Author: Jan Andersson - Gaisler Research
-- Contact: support@gaisler.com
-- Description:
--
-- APB interface to OpenCores I2C-master. This is an GRLIB AMBA wrapper
-- that instantiates the byte- and bit-controller of the OpenCores I2C
-- master (OC core developed by Richard Herveille, richard@asics.ws).
-- The OC byte- and bit-controller are located under lib/opencores/i2c
--
-- The original master had a WISHBONE interface with registers
-- aligned at byte boundaries. This wrapper has a slighly different
-- alignment of the registers, and also (optionally) adds a filter
-- filter register (FR):
--
-- +------------+--------------------------------------+
-- | Offset | Bits in word |
-- | |---------+---------+---------+--------+
-- | | 31 - 24 | 23 - 16 | 15 - 8 | 7 - 0 |
-- +------------+---------+---------+---------+--------+
-- | 0x00 | 0x00 | 0x00 | PRERhi | PRERlo |
-- | 0x04 | 0x00 | 0x00 | 0x00 | CTR |
-- | 0x08 | 0x00 | 0x00 | 0x00 | TXR |
-- | 0x08 | 0x00 | 0x00 | 0x00 | RXR |
-- | 0x0C | 0x00 | 0x00 | 0x00 | CR |
-- | 0x0C | 0x00 | 0x00 | 0x00 | SR |
-- | 0x10 | FR |
-- +------------+---------+---------+---------+--------+
--
-- Revision 1 of this core also sets the TIP bit when STO is set.
--
-- Revision 2 of this core adds a filter generic to adjust the low pass filter
--
-- Revision 3 of this core adds yet another filter generic that can be set to
-- make the filter soft configurable.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.i2c.all;
library opencores;
use opencores.i2coc.all;
entity i2cmst is
generic (
-- APB generics
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0; -- interrupt index
oepol : integer range 0 to 1 := 0; -- output enable polarity
filter : integer range 2 to 512 := 2; -- filter bit size
dynfilt : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2cmst;
architecture rtl of i2cmst is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant I2CMST_REV : integer := 3;
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_I2CMST, 0, I2CMST_REV, pirq),
1 => apb_iobar(paddr, pmask));
constant PRER_addr : std_logic_vector(7 downto 2) := "000000";
constant CTR_addr : std_logic_vector(7 downto 2) := "000001";
constant TXR_addr : std_logic_vector(7 downto 2) := "000010";
constant RXR_addr : std_logic_vector(7 downto 2) := "000010";
constant CR_addr : std_logic_vector(7 downto 2) := "000011";
constant SR_addr : std_logic_vector(7 downto 2) := "000011";
constant FR_addr : std_logic_vector(7 downto 2) := "000100";
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
-- Register interface
type ctrl_reg_type is record -- Control register
en : std_ulogic;
ien : std_ulogic;
end record;
type cmd_reg_type is record -- Command register
sta : std_ulogic;
sto : std_ulogic;
rd : std_ulogic;
wr : std_ulogic;
ack : std_ulogic;
end record;
type sts_reg_type is record -- Status register
rxack : std_ulogic;
busy : std_ulogic;
al : std_ulogic;
tip : std_ulogic;
ifl : std_ulogic;
end record;
-- Core registers
type i2c_reg_type is record
-- i2c registers
prer : std_logic_vector(15 downto 0); -- clock prescale register
ctrl : ctrl_reg_type; -- control register
txr : std_logic_vector(7 downto 0); -- transmit register
cmd : cmd_reg_type; -- command register
sts : sts_reg_type; -- status register
filt : std_logic_vector((filter-1)*dynfilt downto 0); -- filter register
--
irq : std_ulogic;
end record;
-- Signals to and from byte controller block
signal rxr : std_logic_vector(7 downto 0); -- Receive register
signal done : std_logic; -- Signals completion of command
signal rxack : std_logic; -- Received acknowledge
signal busy : std_logic; -- I2C core busy
signal al : std_logic; -- Aribitration lost
signal irst : std_ulogic; -- Internal, negated reset signal
signal iscloen : std_ulogic; -- Internal SCL output enable
signal isdaoen : std_ulogic; -- Internal SDA output enable
-- Register interface
signal r, rin : i2c_reg_type;
signal vcc : std_logic;
begin
-- Byte Controller from OpenCores I2C master,
-- by Richard Herveille (richard@asics.ws). The asynchronous
-- reset is tied to '1'. Only the synchronous reset is used.
vcc <= '1';
byte_ctrl: i2c_master_byte_ctrl
generic map (
filter => filter,
dynfilt => dynfilt)
port map (
clk => clk,
rst => irst,
nReset => vcc,
ena => r.ctrl.en,
clk_cnt => r.prer,
start => r.cmd.sta,
stop => r.cmd.sto,
read => r.cmd.rd,
write => r.cmd.wr,
ack_in => r.cmd.ack,
din => r.txr,
filt => r.filt,
cmd_ack => done,
ack_out => rxack,
i2c_busy => busy,
i2c_al => al,
dout => rxr,
scl_i => i2ci.scl,
scl_o => i2co.scl,
scl_oen => iscloen,
sda_i => i2ci.sda,
sda_o => i2co.sda,
sda_oen => isdaoen);
-- OC I2C logic has active high reset.
irst <= not rstn;
i2co.enable <= r.ctrl.en;
-- Fix output enable polarity
soepol0: if oepol = 0 generate
i2co.scloen <= iscloen;
i2co.sdaoen <= isdaoen;
end generate soepol0;
soepol1: if oepol /= 0 generate
i2co.scloen <= not iscloen;
i2co.sdaoen <= not isdaoen;
end generate soepol1;
comb: process (r, rstn, rxr, rxack, busy, al, done, apbi)
variable v : i2c_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable apbaddr : std_logic_vector(7 downto 2);
variable apbout : std_logic_vector(31 downto 0);
begin -- process comb
v := r; v.irq := '0'; irq := (others=>'0'); irq(pirq) := r.irq;
apbaddr := apbi.paddr(7 downto 2); apbout := (others => '0');
-- Command done or arbitration lost, clear command register
if (done or al) = '1' then
v.cmd := ('0', '0', '0', '0', '0');
end if;
-- Update status register
v.sts := (rxack => rxack,
busy => busy,
al => al or (r.sts.al and not r.cmd.sta),
tip => r.cmd.rd or r.cmd.wr or r.cmd.sto,
ifl => done or al or r.sts.ifl);
v.irq := (done or al) and r.ctrl.ien;
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when PRER_addr =>
apbout(15 downto 0) := r.prer;
when CTR_addr =>
apbout(7 downto 6) := r.ctrl.en & r.ctrl.ien;
when RXR_addr =>
apbout(7 downto 0) := rxr;
when SR_addr =>
apbout(7 downto 5) := r.sts.rxack & r.sts.busy & r.sts.al;
apbout(1 downto 0) := r.sts.tip & r.sts.ifl;
when FR_addr =>
if dynfilt /= 0 then apbout(r.filt'range) := r.filt; end if;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when PRER_addr => v.prer := apbi.pwdata(15 downto 0);
when CTR_addr => v.ctrl.en := apbi.pwdata(7);
v.ctrl.ien := apbi.pwdata(6);
when TXR_addr => v.txr := apbi.pwdata(7 downto 0);
when CR_addr =>
-- Check that core is enabled and that WR and RD has been cleared
-- before accepting new command.
if (r.ctrl.en and not (r.cmd.wr or r.cmd.rd)) = '1' then
v.cmd.sta := apbi.pwdata(7);
v.cmd.sto := apbi.pwdata(6);
v.cmd.rd := apbi.pwdata(5);
v.cmd.wr := apbi.pwdata(4);
v.cmd.ack := apbi.pwdata(3);
end if;
-- Bit 0 of CR is interrupt acknowledge. The core will only pulse one
-- interrupt per irq event. Software does not have to clear the
-- interrupt flag...
if apbi.pwdata(0) = '1' then
v.sts.ifl := '0';
end if;
when FR_addr =>
if dynfilt /= 0 then v.filt := apbi.pwdata(r.filt'range); end if;
when others => null;
end case;
end if;
if rstn = '0' then
v.prer := (others => '1');
v.ctrl := ('0', '0');
v.txr := (others => '0');
v.cmd := ('0','0','0','0', '0');
v.sts := ('0','0','0','0', '0');
if dynfilt /= 0 then v.filt := (others => '1'); end if;
end if;
if dynfilt = 0 then v.filt := (others => '0'); end if;
-- Update registers
rin <= v;
-- Update outputs
apbo.prdata <= apbout;
apbo.pirq <= irq;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"i2cmst" & tost(pindex) & ": AMBA Wrapper for OC I2C-master rev " &
tost(I2CMST_REV) & ", irq " & tost(pirq));
-- pragma translate_on
end architecture rtl;
|
--==============================================================================
-- CERN (BE-CO-HT)
-- I2C slave core
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-03-13
--
-- version: 1.0
--
-- description:
--
-- Simple I2C slave interface, providing the basic low-level functionality
-- of the I2C protocol.
--
-- The gc_i2c_slave module waits for a master to initiate a transfer via
-- a start condition. The address is sent next and if the address matches
-- the slave address set via the i2c_addr_i input, the addr_good_p_o output
-- is set. Based on the eighth bit of the first I2C transfer byte, the module
-- then starts shifting in or out each byte in the transfer, setting the
-- r/w_done_p_o output after each received/sent byte.
--
-- For master write (slave read) transfers, the received byte can be read at
-- the rx_byte_o output when the r_done_p_o pin is high. For master read (slave
-- write) transfers, the slave sends the byte at the tx_byte_i input, which
-- should be set when the w_done_p_o output is high, either after I2C address
-- reception, or a successful send of a previous byte.
--
-- dependencies:
-- OHWR general-cores library
--
-- references:
-- [1] The I2C bus specification, version 2.1, NXP Semiconductor, Jan. 2000
-- http://www.nxp.com/documents/other/39340011.pdf
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-03-13 Theodor Stana File created
-- 2013-11-22 Theodor Stana Changed to sampling SDA on SCL rising edge
--==============================================================================
-- TODO:
-- - Stop condition
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity gc_i2c_slave is
generic
(
-- Length of glitch filter
-- 0 - SCL and SDA lines are passed only through synchronizer
-- 1 - one clk_i glitches filtered
-- 2 - two clk_i glitches filtered
g_gf_len : natural := 0
);
port
(
-- Clock, reset ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- Slave address
i2c_addr_i : in std_logic_vector(6 downto 0);
-- ACK input, should be set after done_p_o = '1'
-- (note that the bit is reversed wrt I2C ACK bit)
-- '1' - ACK
-- '0' - NACK
ack_i : in std_logic;
-- Byte to send, should be loaded while done_p_o = '1'
tx_byte_i : in std_logic_vector(7 downto 0);
-- Received byte, valid after done_p_o = '1'
rx_byte_o : out std_logic_vector(7 downto 0);
-- Pulse outputs signaling various I2C actions
-- Start and stop conditions
i2c_sta_p_o : out std_logic;
i2c_sto_p_o : out std_logic;
-- Received address corresponds i2c_addr_i
addr_good_p_o : out std_logic;
-- Read and write done
r_done_p_o : out std_logic;
w_done_p_o : out std_logic;
-- I2C bus operation, set after address detection
-- '0' - write
-- '1' - read
op_o : out std_logic
);
end entity gc_i2c_slave;
architecture behav of gc_i2c_slave is
--============================================================================
-- Type declarations
--============================================================================
type t_state is
(
IDLE, -- idle
ADDR, -- shift in I2C address bits
ADDR_ACK, -- ACK/NACK to I2C address
RD, -- shift in byte to read
RD_ACK, -- ACK/NACK to received byte
WR_LOAD_TXSR, -- load byte to send via I2C
WR, -- shift out byte
WR_ACK -- get ACK/NACK from master
);
--============================================================================
-- Signal declarations
--============================================================================
-- Deglitched signals and delays for SCL and SDA lines
signal scl_synced : std_logic;
signal scl_deglitched : std_logic;
signal scl_deglitched_d0 : std_logic;
signal sda_synced : std_logic;
signal sda_deglitched : std_logic;
signal sda_deglitched_d0 : std_logic;
signal scl_r_edge_p : std_logic;
signal scl_f_edge_p : std_logic;
signal sda_f_edge_p : std_logic;
signal sda_r_edge_p : std_logic;
-- FSM signals
signal state : t_state;
signal inhibit : std_logic;
-- RX and TX shift registers
signal txsr : std_logic_vector(7 downto 0);
signal rxsr : std_logic_vector(7 downto 0);
-- Bit counter on RX & TX
signal bit_cnt : unsigned(2 downto 0);
-- Start and stop condition pulse signals
signal sta_p, sto_p : std_logic;
-- Master ACKed after it has read a byte from the slave
signal mst_acked : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- I/O logic
--============================================================================
-- No clock stretching implemented, always disable SCL line
scl_o <= '0';
scl_en_o <= '0';
-- SDA line driven low; SDA_EN line controls when the tristate buffer is enabled
sda_o <= '0';
-- Assign RX byte output
rx_byte_o <= rxsr;
--============================================================================
-- Deglitching logic
--============================================================================
-- First, synchronize the SCL signal in the clk_i domain
cmp_sync_scl : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => scl_i,
synced_o => scl_synced
);
-- Generate deglitched SCL signal
cmp_scl_deglitch : gc_glitch_filt
generic map
(
g_len => g_gf_len
)
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
dat_i => scl_synced,
dat_o => scl_deglitched
);
-- and create a delayed version of this signal, together with one-tick-long
-- falling-edge detection signal
p_scl_degl_d0 : process(clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
scl_deglitched_d0 <= '0';
scl_f_edge_p <= '0';
scl_r_edge_p <= '0';
else
scl_deglitched_d0 <= scl_deglitched;
scl_f_edge_p <= (not scl_deglitched) and scl_deglitched_d0;
scl_r_edge_p <= scl_deglitched and (not scl_deglitched_d0);
end if;
end if;
end process p_scl_degl_d0;
-- Synchronize SDA signal in clk_i domain
cmp_sda_sync : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => sda_i,
synced_o => sda_synced
);
-- Generate deglitched SDA signal
cmp_sda_deglitch : gc_glitch_filt
generic map
(
g_len => g_gf_len
)
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
dat_i => sda_synced,
dat_o => sda_deglitched
);
-- and create a delayed version of this signal, together with one-tick-long
-- falling- and rising-edge detection signals
p_sda_deglitched_d0 : process(clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
sda_deglitched_d0 <= '0';
sda_f_edge_p <= '0';
sda_r_edge_p <= '0';
else
sda_deglitched_d0 <= sda_deglitched;
sda_f_edge_p <= (not sda_deglitched) and sda_deglitched_d0;
sda_r_edge_p <= sda_deglitched and (not sda_deglitched_d0);
end if;
end if;
end process p_sda_deglitched_d0;
--============================================================================
-- Start and stop condition outputs
--============================================================================
-- First the process to set the start and stop conditions as per I2C standard
p_sta_sto : process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
sta_p <= '0';
sto_p <= '0';
else
sta_p <= sda_f_edge_p and scl_deglitched;
sto_p <= sda_r_edge_p and scl_deglitched;
end if;
end if;
end process p_sta_sto;
-- Finally, set the outputs
i2c_sta_p_o <= sta_p;
i2c_sto_p_o <= sto_p;
--============================================================================
-- FSM logic
--============================================================================
p_fsm: process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= IDLE;
inhibit <= '0';
bit_cnt <= (others => '0');
rxsr <= (others => '0');
txsr <= (others => '0');
mst_acked <= '0';
sda_en_o <= '0';
r_done_p_o <= '0';
w_done_p_o <= '0';
addr_good_p_o <= '0';
op_o <= '0';
-- start and stop conditions are followed by I2C address, so any byte
-- following would be an address byte; therefore, it is safe to deinhibit
-- the FSM
elsif (sta_p = '1') or (sto_p = '1') then
state <= IDLE;
inhibit <= '0';
-- state machine logic
else
case state is
---------------------------------------------------------------------
-- IDLE
---------------------------------------------------------------------
when IDLE =>
-- clear outputs and bit counter
bit_cnt <= (others => '0');
sda_en_o <= '0';
mst_acked <= '0';
r_done_p_o <= '0';
w_done_p_o <= '0';
addr_good_p_o <= '0';
if (scl_f_edge_p = '1') and (inhibit = '0') then
state <= ADDR;
end if;
---------------------------------------------------------------------
-- ADDR
---------------------------------------------------------------------
when ADDR =>
-- Shifting in is done on rising edge of SCL
if (scl_r_edge_p = '1') then
rxsr <= rxsr(6 downto 0) & sda_deglitched;
bit_cnt <= bit_cnt + 1;
end if;
--
-- Checking the bit counter is done on the falling edge of SCL
--
-- If 8 bits have been shifted in, the received address is checked
-- and the slave goes in the ADDR_ACK state.
--
-- If the address is not ours, go back to IDLE and set inhibit bits
-- so bytes sent to or received from another slave that happen to
-- coincide to the address of this slave don't get interpreted
-- as accesses to this slave.
--
if (scl_f_edge_p = '1') then
if (bit_cnt = 0) then
if (rxsr(7 downto 1) = i2c_addr_i) then
op_o <= rxsr(0);
addr_good_p_o <= '1';
state <= ADDR_ACK;
else
inhibit <= '1';
state <= IDLE;
end if;
end if;
end if;
---------------------------------------------------------------------
-- ADDR_ACK
---------------------------------------------------------------------
when ADDR_ACK =>
-- clear addr_good pulse
addr_good_p_o <= '0';
-- send ACK from input, check the ACK on falling edge and go to
-- loading of the TXSR if the OP bit is a write, or read otherwise
sda_en_o <= ack_i;
if (scl_f_edge_p = '1') then
if (ack_i = '1') then
if (rxsr(0) = '0') then
state <= RD;
else
state <= WR_LOAD_TXSR;
end if;
else
state <= IDLE;
end if;
end if;
---------------------------------------------------------------------
-- RD
---------------------------------------------------------------------
-- Shift in bits sent by the master
---------------------------------------------------------------------
when RD =>
-- not controlling SDA, clear enable signal
sda_en_o <= '0';
-- shift in on rising-edge
if (scl_r_edge_p = '1') then
rxsr <= rxsr(6 downto 0) & sda_deglitched;
bit_cnt <= bit_cnt + 1;
end if;
if (scl_f_edge_p = '1') then
-- Received 8 bits, go to RD_ACK and signal external module
if (bit_cnt = 0) then
state <= RD_ACK;
r_done_p_o <= '1';
end if;
end if;
---------------------------------------------------------------------
-- RD_ACK
---------------------------------------------------------------------
when RD_ACK =>
-- Clear done pulse
r_done_p_o <= '0';
-- we write the ACK bit, so control sda_en_o signal to send ACK/NACK
sda_en_o <= ack_i;
-- based on the ACK received by external command, we read the next
-- bit (ACK) or go back to idle state (NACK)
if (scl_f_edge_p = '1') then
if (ack_i = '1') then
state <= RD;
else
state <= IDLE;
end if;
end if;
---------------------------------------------------------------------
-- WR_LOAD_TXSR
---------------------------------------------------------------------
when WR_LOAD_TXSR =>
txsr <= tx_byte_i;
state <= WR;
---------------------------------------------------------------------
-- WR
---------------------------------------------------------------------
when WR =>
-- slave writes, SDA output enable is the negated value of the bit
-- to send (since on I2C, '1' is a release of the bus)
sda_en_o <= not txsr(7);
-- increment bit counter on rising edge
if (scl_r_edge_p = '1') then
bit_cnt <= bit_cnt + 1;
end if;
-- Shift TXSR on falling edge of SCL
if (scl_f_edge_p = '1') then
txsr <= txsr(6 downto 0) & '0';
-- Eight bits sent, disable SDA and go to WR_ACK
if (bit_cnt = 0) then
state <= WR_ACK;
w_done_p_o <= '1';
end if;
end if;
---------------------------------------------------------------------
-- WR_ACK
---------------------------------------------------------------------
when WR_ACK =>
-- master controls SDA, clear sda_en_o
sda_en_o <= '0';
-- clear done pulse
w_done_p_o <= '0';
-- sample in ACK from master on rising edge
if (scl_r_edge_p = '1') then
if (sda_deglitched = '0') then
mst_acked <= '1';
else
mst_acked <= '0';
end if;
end if;
-- and check it on falling edge
if (scl_f_edge_p = '1') then
if (mst_acked = '1') then
state <= WR_LOAD_TXSR;
else
state <= IDLE;
end if;
end if;
---------------------------------------------------------------------
-- Any other state: go back to IDLE
---------------------------------------------------------------------
when others =>
state <= IDLE;
end case;
end if;
end if;
end process p_fsm;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity memory_mapped_reset is
generic (
REGISTER_SIZE : integer := 32;
ADDR_WIDTH : integer := 2
);
port (
clk : in std_logic;
reset : in std_logic;
avm_address : in std_logic_vector(ADDR_WIDTH-1 downto 0);
avm_read : in std_logic;
avm_readdata : out std_logic_vector(REGISTER_SIZE-1 downto 0);
avm_readdatavalid : out std_logic;
avm_write : in std_logic;
avm_writedata : in std_logic_vector(REGISTER_SIZE-1 downto 0);
reset_out : out std_logic
);
end entity memory_mapped_reset;
architecture rtl of memory_mapped_reset is
signal reset_out_reg : std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
avm_readdatavalid <= '0';
-- reset_out is registered to prevent meta-stability.
reset_out <= reset_out_reg;
if reset = '1' then
reset_out <= '0';
reset_out_reg <= '0';
else
if avm_address = std_logic_vector(to_unsigned(0, ADDR_WIDTH)) then
if avm_write = '1' then
reset_out_reg <= avm_writedata(0);
end if;
if avm_read = '1' then
avm_readdata <= (0 => reset_out_reg, others => '0');
avm_readdatavalid <= '1';
end if;
end if;
end if;
end if;
end process;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity pia8255 is
port
(
-- uC interface
clk : in std_logic;
clken : in std_logic;
reset : in std_logic;
a : in std_logic_vector(1 downto 0);
d_i : in std_logic_vector(7 downto 0);
d_o : out std_logic_vector(7 downto 0);
cs : in std_logic;
rd : in std_logic;
wr : in std_logic;
-- I/O interface
pa_i : in std_logic_vector(7 downto 0);
pb_i : in std_logic_vector(7 downto 0);
pc_i : in std_logic_vector(7 downto 0);
pa_o : out std_logic_vector(7 downto 0);
pb_o : out std_logic_vector(7 downto 0);
pc_o : out std_logic_vector(7 downto 0)
);
end pia8255;
architecture SYN of pia8255 is
type byte_vector is array (natural range <>) of std_logic_vector(7 downto 0);
signal ctrl : std_logic_vector(7 downto 0);
signal pa_oen : std_logic;
signal pb_oen : std_logic;
signal pcl_oen : std_logic;
signal pch_oen : std_logic;
signal pa_d : std_logic_vector(7 downto 0);
signal pb_d : std_logic_vector(7 downto 0);
signal pc_d : std_logic_vector(7 downto 0);
begin
pa_o <= pa_d when (reset = '0' and pa_oen = '1') else X"FF";
pb_o <= pb_d when (reset = '0' and pb_oen = '1') else X"FF";
pc_o(7 downto 4) <= pc_d(7 downto 4) when (reset = '0' and pch_oen = '1') else X"F";
pc_o(3 downto 0) <= pc_d(3 downto 0) when (reset = '0' and pcl_oen = '1') else X"F";
-- Synchronous logic
process(clk, reset)
variable ctrl_r : std_logic_vector(7 downto 0);
variable csel : integer;
begin
pa_oen <= not ctrl_r(4);
pb_oen <= not ctrl_r(1);
pcl_oen <= not ctrl_r(0);
pch_oen <= not ctrl_r(3);
ctrl <= ctrl_r;
-- Reset values
if reset = '1' then
ctrl_r := X"9B";
pa_d <= X"00";
pb_d <= X"00";
pc_d <= X"00";
-- Handle register writes
elsif rising_edge(clk) and clken = '1' and cs = '1' and wr = '1' then
if a = "00" then
pa_d <= d_i;
end if;
if a = "01" then
pb_d <= d_i;
end if;
if a = "10" then
pc_d <= d_i;
end if;
if a = "11" then
-- D7=1, write control
if d_i(7) = '1' then
ctrl_r := d_i;
pa_d <= X"00";
pb_d <= X"00";
pc_d <= X"00";
-- D7=0, write C bit
else
csel := conv_integer(d_i(3 downto 1));
pc_d(csel) <= d_i(0);
end if;
end if;
end if;
end process;
-- Data out mux
process(a, cs, rd)
variable data_out : std_logic_vector(7 downto 0);
begin
if cs = '1' and rd = '1' then
case a is
when "00" => data_out := pa_i;
when "01" => data_out := pb_i;
when "10" => data_out := pc_i;
when "11" => data_out := ctrl;
when others => data_out := (others => 'X');
end case;
else
data_out := (others => 'X');
end if;
d_o <= data_out;
end process;
end SYN;
library IEEE;
use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity pia8255_n is
port
(
-- uC interface
clk : in std_logic;
clken : in std_logic;
reset : in std_logic;
a : in std_logic_vector(1 downto 0);
d_i : in std_logic_vector(7 downto 0);
d_o : out std_logic_vector(7 downto 0);
cs_n : in std_logic;
rd_n : in std_logic;
wr_n : in std_logic;
-- I/O interface
pa_i : in std_logic_vector(7 downto 0);
pb_i : in std_logic_vector(7 downto 0);
pc_i : in std_logic_vector(7 downto 0);
pa_o : out std_logic_vector(7 downto 0);
pb_o : out std_logic_vector(7 downto 0);
pc_o : out std_logic_vector(7 downto 0)
);
end pia8255_n;
architecture SYN of pia8255_n is
signal cs : std_logic;
signal rd : std_logic;
signal wr : std_logic;
begin
cs <= not cs_n;
rd <= not rd_n;
wr <= not wr_n;
pia_inst : entity work.pia8255
port map
(
-- uC interface
clk => clk,
clken => clken,
reset => reset,
a => a,
d_i => d_i,
d_o => d_o,
cs => cs,
rd => rd,
wr => wr,
-- I/O interface
pa_i => pa_i,
pb_i => pb_i,
pc_i => pc_i,
pa_o => pa_o,
pb_o => pb_o,
pc_o => pc_o
);
end SYN;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1029.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p02n01i01029ent IS
type THREE is range 1 to 3;
type A1 is array (THREE) of BOOLEAN;
type A2 is array (THREE, THREE) of BOOLEAN;
type A3 is array (THREE) of A1;
type R1 is record
RE1: A1;
end record;
type R2 is record
RE2: A2;
end record;
type R3 is record
RE3: A3;
end record;
END c06s04b00x00p02n01i01029ent;
ARCHITECTURE c06s04b00x00p02n01i01029arch OF c06s04b00x00p02n01i01029ent IS
BEGIN
TESTING: PROCESS
variable V: BOOLEAN;
variable V1: R1 ; -- := (RE1=>(others=>TRUE));
variable V2: R2 ; -- := (RE2=>(others=>(others=>TRUE)));
variable V3: R3 ; -- := (RE3=>(others=>(others=>TRUE)));
BEGIN
V := V2.RE2(2, 3);
assert NOT( V=false )
report "***PASSED TEST: c06s04b00x00p02n01i01029"
severity NOTE;
assert ( V=false )
report "***FAILED TEST: c06s04b00x00p02n01i01029 - The prefix of an indexed name can be a selected name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p02n01i01029arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1029.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p02n01i01029ent IS
type THREE is range 1 to 3;
type A1 is array (THREE) of BOOLEAN;
type A2 is array (THREE, THREE) of BOOLEAN;
type A3 is array (THREE) of A1;
type R1 is record
RE1: A1;
end record;
type R2 is record
RE2: A2;
end record;
type R3 is record
RE3: A3;
end record;
END c06s04b00x00p02n01i01029ent;
ARCHITECTURE c06s04b00x00p02n01i01029arch OF c06s04b00x00p02n01i01029ent IS
BEGIN
TESTING: PROCESS
variable V: BOOLEAN;
variable V1: R1 ; -- := (RE1=>(others=>TRUE));
variable V2: R2 ; -- := (RE2=>(others=>(others=>TRUE)));
variable V3: R3 ; -- := (RE3=>(others=>(others=>TRUE)));
BEGIN
V := V2.RE2(2, 3);
assert NOT( V=false )
report "***PASSED TEST: c06s04b00x00p02n01i01029"
severity NOTE;
assert ( V=false )
report "***FAILED TEST: c06s04b00x00p02n01i01029 - The prefix of an indexed name can be a selected name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p02n01i01029arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1029.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p02n01i01029ent IS
type THREE is range 1 to 3;
type A1 is array (THREE) of BOOLEAN;
type A2 is array (THREE, THREE) of BOOLEAN;
type A3 is array (THREE) of A1;
type R1 is record
RE1: A1;
end record;
type R2 is record
RE2: A2;
end record;
type R3 is record
RE3: A3;
end record;
END c06s04b00x00p02n01i01029ent;
ARCHITECTURE c06s04b00x00p02n01i01029arch OF c06s04b00x00p02n01i01029ent IS
BEGIN
TESTING: PROCESS
variable V: BOOLEAN;
variable V1: R1 ; -- := (RE1=>(others=>TRUE));
variable V2: R2 ; -- := (RE2=>(others=>(others=>TRUE)));
variable V3: R3 ; -- := (RE3=>(others=>(others=>TRUE)));
BEGIN
V := V2.RE2(2, 3);
assert NOT( V=false )
report "***PASSED TEST: c06s04b00x00p02n01i01029"
severity NOTE;
assert ( V=false )
report "***FAILED TEST: c06s04b00x00p02n01i01029 - The prefix of an indexed name can be a selected name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p02n01i01029arch;
|
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`protect end_protected
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
use work.pico_cpu.all;
entity Mem is
generic (BitWidth: integer);
port ( RdAddress: in std_logic_vector (BitWidth-1 downto 0);
Data_in: in std_logic_vector (BitWidth-1 downto 0);
WrtAddress: in std_logic_vector (BitWidth-1 downto 0);
clk: in std_logic;
RW: in std_logic;
rst: in std_logic;
Data_Out: out std_logic_vector (BitWidth-1 downto 0)
);
end Mem;
architecture beh of Mem is
type Mem_type is array (0 to DataMem_depth-1) of std_logic_vector(BitWidth-1 downto 0) ;
signal Mem : Mem_type := ((others=> (others=>'0')));
begin
MemProcess: process(clk,rst) is
begin
if rst = '1' then
Mem<= ((others=> (others=>'0')));
elsif rising_edge(clk) then
if RW = '1' then
if to_integer(unsigned(WrtAddress(BitWidth-1 downto 0))) <= DataMem_depth-1 then
Mem(to_integer(unsigned(WrtAddress(BitWidth-1 downto 0)))) <= Data_in;
end if;
end if;
end if;
end process MemProcess;
process(RdAddress)begin
if to_integer(unsigned(RdAddress(BitWidth-1 downto 0))) <= DataMem_depth-1 then
Data_Out <= Mem(to_integer(unsigned(RdAddress(BitWidth-1 downto 0))));
else
Data_Out <= (others=> '0');
end if;
end process;
end beh;
|
-- ALUNOS:
-- Bruno Luiz da Silva
-- Gustavo Fernades
--
--
-- TÍTULO:
-- Expoente
--
--
-- RESUMO:
-- Calcula o expoente baseado na normalização e nos expoentes dados
--
--
-- ENTRADAS/SAÍDAS (I/O):
-- (I) a,b: entradas de 4 bits cada que serão os expoentes que o usuário dará
-- (I) normal: entrada que receberá o número de vezes que a mantissa foi deslocada para ficar normalizada
-- (I) arguments: argumentos que serão recebidos para realizar a soma dos expoentes dados ou o resultado
-- dessa soma mais o número de deslocamentos realizados.
-- (I) clk,rst: clock e reset, sendo que o reset zera todas saídas
-- (O) q: saída do componente, sendo que será esse o expoente final
--
--
-- DESCRIÇÃO:
-- Esse componente será responsável por dar o expoente da multiplicação que será realizada. Para tal o
-- usuário entrará com os expoentes (em a e b) e dará o valor "110" para o "argument" para realizar a
-- soma de ambos. Para previnir casos onde houver uma soma que extrapole o valor "1111" (7 em decimal)
-- então foi adicionado um bit extra na saída para armazenar o possível valor extra. Em algum momento
-- será enviado o número de deslocamentos realizados para normalizar a mantissa (normal) e assim terá-se
-- um valor negativo que deverá ser decrementado do atual expoente. Após essa decrementação então tem-se
-- o expoente final, porém ele deve estar na faixa de "0000" a "1111" (0 a 15 em decimal), pois caso
-- extrapole essa faixa ele não poderá apresentar o valor correto nos LEDs designados sendo assim um caso
-- de overflow, que ativará o LED designado para tal.
--
--
-- ANEXO - ARGUMENTS:
-- O "arguments" será dado pela FSM e o mesmo é ligado ao bloco de multiplicação. Aproveitando essa mesma
-- saída então usa-se o arguments aqui. Os sinais utilizados e o que fazem são:
--
-- 110: realiza a soma entre os dois expoentes dados (a e b).
-- 111: realiza a subtração do atual valor guardado (soma de a e b) com o número de deslocamentos realizados
-- na normalização da mantissa.
--
--
-- (I): INPUT / (O): OUTPUT
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity expoente is
generic(N: natural := 4);
port(
a,b: in std_logic_vector((N-1) downto 0); -- Expoentes dados pelo usuário
normal: in std_logic_vector((N-1) downto 0); -- Deslocamentos que foram necessários para normalizar a mantissa
arguments: in std_logic_vector(2 downto 0); -- Argumentos que dará as ordens para o componente
clk,rst: in std_logic; -- Clock e reset
q: out std_logic_vector((N) downto 0) -- Expoente final
);
end expoente;
architecture func of expoente is
signal aux: std_logic_vector(N downto 0);
begin
EXPOENTE: process(clk,rst)
begin
if(rst = '1') then aux <= (others => '0');
elsif(rising_edge(clk)) then
if(arguments = "110") then
-- Soma dos dois expoentes dados com o bit extra para o carry
aux <= ('0'&a) + ('0'&b);
elsif(arguments = "111") then
-- Decremento do resultado da soma anterior com o número de deslocamentos da normalização
aux <= aux - ('0'&normal);
else aux <= aux;
end if;
end if;
q <= aux;
end process;
end func; |
-- $Id: debounce_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: debounce_gen - syn
-- Description: Generic signal debouncer
--
-- Dependencies: -
-- Test bench: tb/tb_debounce_gen
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 418 1.0.3 now numeric_std clean
-- 2007-12-26 105 1.0.2 add default for RESET
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-29 61 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity debounce_gen is -- debounce, generic vector
generic (
CWIDTH : positive := 2; -- clock interval counter width
CEDIV : positive := 3; -- clock interval divider
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_INT : in slbit; -- clock interval enable (usec or msec)
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end entity debounce_gen;
architecture syn of debounce_gen is
constant cntzero : slv(CWIDTH-1 downto 0) := (others=>'0');
constant datazero : slv(dWIDTH-1 downto 0) := (others=>'0');
type regs_type is record
cecnt : slv(CWIDTH-1 downto 0); -- clock interval counter
dref : slv(DWIDTH-1 downto 0); -- data reference
dchange : slv(DWIDTH-1 downto 0); -- data change flag
dout : slv(DWIDTH-1 downto 0); -- data output
end record regs_type;
constant regs_init : regs_type := (
cntzero,
datazero,
datazero,
datazero
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
assert CEDIV<=2**CWIDTH report "assert(CEDIV<=2**CWIDTH)" severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS.cecnt <= cntzero;
R_REGS.dref <= DI;
R_REGS.dchange <= datazero;
R_REGS.dout <= DI;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_INT, DI)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
for i in DI'range loop
if DI(i) /= r.dref(i) then
n.dchange(i) := '1';
end if;
end loop;
if CE_INT = '1' then
if unsigned(r.cecnt) = 0 then
n.cecnt := slv(to_unsigned(CEDIV-1,CWIDTH));
n.dref := DI;
n.dchange := datazero;
for i in DI'range loop
if r.dchange(i) = '0' then
n.dout(i) := r.dref(i);
end if;
end loop;
else
n.cecnt := slv(unsigned(r.cecnt) - 1);
end if;
end if;
N_REGS <= n;
DO <= r.dout;
end process proc_next;
end syn;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ByteHEXdisplay is
Port (
clk : in STD_LOGIC;
ssData : in STD_LOGIC_VECTOR (31 downto 0);
sevenseg : out STD_LOGIC_VECTOR (6 downto 0);
anode : out STD_LOGIC_VECTOR (7 downto 0)
);
end ByteHEXdisplay;
architecture Behavioral of ByteHEXdisplay is
signal nibble : STD_LOGIC_VECTOR (3 downto 0);
signal count : STD_LOGIC_VECTOR (15 downto 0);
begin
PROCESS
begin
wait until rising_edge(clk);
count <= count + 1;
if count(15 downto 13) = "001" then -- toggle on MSBits of count
anode <= "11111110";
nibble <= ssData(3 downto 0);
elsif count(15 downto 13) = "010" then
anode <= "11111101";
nibble <= ssData(7 downto 4);
elsif count(15 downto 13) = "011" then
anode <= "11111011";
nibble <= ssData(11 downto 8);
elsif count(15 downto 13) = "100" then
anode <= "11110111";
nibble <= ssData(15 downto 12);
elsif count(15 downto 13) = "101" then
anode <= "11101111";
nibble <= ssData(19 downto 16);
elsif count(15 downto 13) = "110" then
anode <= "11011111";
nibble <= ssData(23 downto 20);
elsif count(15 downto 13) = "111" then
anode <= "10111111";
nibble <= ssData(27 downto 24);
else
anode <= "01111111";
nibble <= ssData(31 downto 28);
end if;
case nibble is
when "0000" => sevenseg <= "1000000";
when "0001" => sevenseg <= "1111001";
when "0010" => sevenseg <= "0100100";
when "0011" => sevenseg <= "0110000";
when "0100" => sevenseg <= "0011001";
when "0101" => sevenseg <= "0010010";
when "0110" => sevenseg <= "0000010";
when "0111" => sevenseg <= "1111000";
when "1000" => sevenseg <= "0000000";
when "1001" => sevenseg <= "0011000";
when "1010" => sevenseg <= "0001000";
when "1011" => sevenseg <= "0000011";
when "1100" => sevenseg <= "1000110";
when "1101" => sevenseg <= "0100001";
when "1110" => sevenseg <= "0000110";
when others => sevenseg <= "0001110";
end case;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: A controller to send I2C commands to the ADAU1761 codec
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity i2c is
Port ( clk : in STD_LOGIC;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : out STD_LOGIC);
end i2c;
architecture Behavioral of i2c is
COMPONENT i3c2
Generic( clk_divide : STD_LOGIC_VECTOR (7 downto 0));
PORT(
clk : IN std_logic;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : OUT std_logic;
inst_data : IN std_logic_vector(8 downto 0);
inputs : IN std_logic_vector(15 downto 0);
inst_address : OUT std_logic_vector(9 downto 0);
debug_sda : OUT std_logic;
debug_scl : OUT std_logic;
outputs : OUT std_logic_vector(15 downto 0);
reg_addr : OUT std_logic_vector(4 downto 0);
reg_data : OUT std_logic_vector(7 downto 0);
reg_write : OUT std_logic;
error : OUT std_logic
);
END COMPONENT;
COMPONENT adau1761_configuraiton_data
PORT(
clk : IN std_logic;
address : IN std_logic_vector(9 downto 0);
data : OUT std_logic_vector(8 downto 0)
);
END COMPONENT;
signal inst_address : std_logic_vector(9 downto 0);
signal inst_data : std_logic_vector(8 downto 0);
signal debug_big : std_logic_vector(15 downto 0);
begin
Inst_adau1761_configuraiton_data: adau1761_configuraiton_data PORT MAP(
clk => clk,
address => inst_address,
data => inst_data
);
Inst_i3c2: i3c2 GENERIC MAP (
clk_divide => "01111000" -- 120 (48,000/120 = 400kHz I2C clock)
) PORT MAP(
clk => clk,
inst_address => inst_address,
inst_data => inst_data,
i2c_scl => i2c_scl,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
i2c_sda_t => i2c_sda_t,
inputs => (others => '0'),
outputs => debug_big,
reg_addr => open,
reg_data => open,
reg_write => open,
debug_scl => open,
debug_sda => open,
error => open
);
end Behavioral; |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: A controller to send I2C commands to the ADAU1761 codec
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity i2c is
Port ( clk : in STD_LOGIC;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : out STD_LOGIC);
end i2c;
architecture Behavioral of i2c is
COMPONENT i3c2
Generic( clk_divide : STD_LOGIC_VECTOR (7 downto 0));
PORT(
clk : IN std_logic;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : OUT std_logic;
inst_data : IN std_logic_vector(8 downto 0);
inputs : IN std_logic_vector(15 downto 0);
inst_address : OUT std_logic_vector(9 downto 0);
debug_sda : OUT std_logic;
debug_scl : OUT std_logic;
outputs : OUT std_logic_vector(15 downto 0);
reg_addr : OUT std_logic_vector(4 downto 0);
reg_data : OUT std_logic_vector(7 downto 0);
reg_write : OUT std_logic;
error : OUT std_logic
);
END COMPONENT;
COMPONENT adau1761_configuraiton_data
PORT(
clk : IN std_logic;
address : IN std_logic_vector(9 downto 0);
data : OUT std_logic_vector(8 downto 0)
);
END COMPONENT;
signal inst_address : std_logic_vector(9 downto 0);
signal inst_data : std_logic_vector(8 downto 0);
signal debug_big : std_logic_vector(15 downto 0);
begin
Inst_adau1761_configuraiton_data: adau1761_configuraiton_data PORT MAP(
clk => clk,
address => inst_address,
data => inst_data
);
Inst_i3c2: i3c2 GENERIC MAP (
clk_divide => "01111000" -- 120 (48,000/120 = 400kHz I2C clock)
) PORT MAP(
clk => clk,
inst_address => inst_address,
inst_data => inst_data,
i2c_scl => i2c_scl,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
i2c_sda_t => i2c_sda_t,
inputs => (others => '0'),
outputs => debug_big,
reg_addr => open,
reg_data => open,
reg_write => open,
debug_scl => open,
debug_sda => open,
error => open
);
end Behavioral; |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: A controller to send I2C commands to the ADAU1761 codec
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity i2c is
Port ( clk : in STD_LOGIC;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : out STD_LOGIC);
end i2c;
architecture Behavioral of i2c is
COMPONENT i3c2
Generic( clk_divide : STD_LOGIC_VECTOR (7 downto 0));
PORT(
clk : IN std_logic;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : OUT std_logic;
inst_data : IN std_logic_vector(8 downto 0);
inputs : IN std_logic_vector(15 downto 0);
inst_address : OUT std_logic_vector(9 downto 0);
debug_sda : OUT std_logic;
debug_scl : OUT std_logic;
outputs : OUT std_logic_vector(15 downto 0);
reg_addr : OUT std_logic_vector(4 downto 0);
reg_data : OUT std_logic_vector(7 downto 0);
reg_write : OUT std_logic;
error : OUT std_logic
);
END COMPONENT;
COMPONENT adau1761_configuraiton_data
PORT(
clk : IN std_logic;
address : IN std_logic_vector(9 downto 0);
data : OUT std_logic_vector(8 downto 0)
);
END COMPONENT;
signal inst_address : std_logic_vector(9 downto 0);
signal inst_data : std_logic_vector(8 downto 0);
signal debug_big : std_logic_vector(15 downto 0);
begin
Inst_adau1761_configuraiton_data: adau1761_configuraiton_data PORT MAP(
clk => clk,
address => inst_address,
data => inst_data
);
Inst_i3c2: i3c2 GENERIC MAP (
clk_divide => "01111000" -- 120 (48,000/120 = 400kHz I2C clock)
) PORT MAP(
clk => clk,
inst_address => inst_address,
inst_data => inst_data,
i2c_scl => i2c_scl,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
i2c_sda_t => i2c_sda_t,
inputs => (others => '0'),
outputs => debug_big,
reg_addr => open,
reg_data => open,
reg_write => open,
debug_scl => open,
debug_sda => open,
error => open
);
end Behavioral; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ALU is --do not change entity, it must match testbench component
Port ( a , b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
op : in STD_LOGIC_VECTOR (1 downto 0); --2 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end ALU;
architecture toplevel of ALU is
--the component for first function is created
component func1 is
Port ( a, b : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for second function is created
component func2 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for third function is created
component func3 is
Port ( a, b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for forth function is created
component func4 is
Port ( a, b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for mux is created
component mux is
Port (m_op : in STD_LOGIC_VECTOR (1 downto 0);
F1_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
F2_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
F3_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
F4_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
m_o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
signal F1_out, F2_out, F3_out, F4_out : STD_LOGIC_VECTOR (3 downto 0):="0000";
begin --beginning of the architecture
--components are port mapped according to workinstructions: http://priit.ati.ttu.ee/?page_id=2320
F1 : func1 port map (a => a,
b => b ,
o => F1_out);
F2 : func2 port map (a => a,
o => F2_out);
F3 : func3 port map (a => a,
b => b ,
o => F3_out);
F4 : func4 port map (a => a,
b => b,
o => F4_out);
MUX_tl : mux port map (m_op => op,
F1_in => F1_out,
F2_in => F2_out,
F3_in => F3_out,
F4_in => F4_out,
m_o => o);
end toplevel; |
------------------------------------------------------------------
-- BCD multiplier N by M digits
-- Fully combiational
-- Simple version
------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use work.my_package.all;
--library UNISIM;
--use UNISIM.VComponents.all;
entity mult_BCD_comb is
Generic (NDigit : natural:=5; MDigit : natural:=5);
Port ( a : in STD_LOGIC_VECTOR (NDigit*4-1 downto 0);
b : in STD_LOGIC_VECTOR (MDigit*4-1 downto 0);
p : out STD_LOGIC_VECTOR ((NDigit+MDigit)*4-1 downto 0));
end mult_BCD_comb;
architecture Behavioral of mult_BCD_comb is
function log2sup (num: natural) return natural is
variable i,pw: natural;
begin
i := 0; pw := 1;
while(pw < num) loop i := i+1; pw := pw*2; end loop;
return i;
end log2sup;
component mult_Nx1_BCD is
Generic (NDigit : integer);
Port ( a : in STD_LOGIC_VECTOR (NDigit*4-1 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
p : out STD_LOGIC_VECTOR ((NDigit+1)*4-1 downto 0));
end component;
component cych_adder_BCD_v2 is
Generic (NDigit : integer);
Port ( a, b : in STD_LOGIC_VECTOR (NDigit*4-1 downto 0);
cin : in STD_LOGIC;
cout : out STD_LOGIC;
s : out STD_LOGIC_VECTOR (NDigit*4-1 downto 0));
end component;
--constant logM natural := log2sup(MDigit);
type partialSum is array (2*MDigit-2 downto 0) of STD_LOGIC_VECTOR ((NDigit+MDigit)*4-1 downto 0);
signal pp,pps: partialSum;
begin
GenM: for i in 0 to (MDigit-1) generate --Multiply one by N
mlt: mult_Nx1_BCD generic map (NDIGIT => NDigit) PORT MAP (
a => a, b => b((i+1)*4-1 downto i*4), p => pp(i)((NDigit+1)*4-1 downto 0) );
end generate;
GenOps: for i in 0 to log2sup(MDigit)-1 generate --Tree of adders
G_P: for j in ((2**i-1)*2**(log2sup(MDigit)-i)) to (((2**i-1)*2**(log2sup(MDigit)-i)) + 2**(log2sup(MDigit)-i-1) -1) generate
pps(2*j)((NDigit+MDigit)*4-1 downto (NDigit)*4) <= (others => '0');
pps(2*j)((NDigit)*4-1 downto 0) <= pp(2*j)((NDigit+2**i)*4-1 downto (2**i)*4);
adder: cych_adder_BCD_v2 generic map (NDIGIT => NDigit+2**i)
PORT MAP( a => pps(2*j)((NDigit+2**i)*4-1 downto 0), b => pp(2*j+1)((NDigit+2**i)*4-1 downto 0),
cin => '0', cout => open, s => pp(MDIGIT+j)((NDigit+2**i+2**i)*4-1 downto ((2**i)*4)));
pp(MDIGIT+j)((2**i)*4-1 downto 0) <= pp(2*j)((2**i)*4-1 downto 0);
end generate;
end generate;
p((NDigit+MDigit)*4-1 downto 0) <= pp(MDigit*2-2);
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbjtag
-- File: ahbjtag.vhd
-- Author: Edvin Catovic, Jiri Gaisler - Gaisler Research
-- Description: JTAG communication link with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use gaisler.libjtagcom.all;
use gaisler.jtag.all;
entity ahbjtag is
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3;
scantest : integer := 0;
oepol : integer := 1;
tcknen : integer := 0;
versel : integer range 0 to 1 := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapi_tdo : in std_ulogic;
trst : in std_ulogic := '1';
tdoen : out std_ulogic;
tckn : in std_ulogic := '0';
tapo_tckn : out std_ulogic;
tapo_ninst : out std_logic_vector(7 downto 0);
tapo_iupd : out std_ulogic
);
end;
architecture struct of ahbjtag is
-- Use old jtagcom that only supports AHB clock up to 1/3 of JTAG clock
-- Must be used for certain techs where we don't have full access to TCK
-- Can also be forced by setting versel generic to 0
constant USEOLDCOM : integer := 1 - (1-tap_tck_gated(tech))*(versel);
-- Set REREAD to 1 to include support for re-read operation when host reads
-- out data register before jtagcom has completed the current AMBA access and
-- returned to state 'shft'.
constant REREAD : integer := 1;
constant REVISION : integer := 2 - (2-REREAD)*USEOLDCOM;
constant TAPSEL : integer := has_tapsel(tech);
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal ltapi : tap_in_type;
signal ltapo : tap_out_type;
signal lltck, lltckn, ltck, ltckn: std_ulogic;
signal lupd: std_ulogic;
signal ctrst: std_ulogic;
begin
ahbmst0 : ahbmst
generic map (hindex => hindex, venid => VENDOR_GAISLER,
devid => GAISLER_AHBJTAG, version => REVISION)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
tap0 : tap generic map (tech => tech, irlen => 6, idcode => idcode,
manf => manf, part => part, ver => ver, scantest => scantest, oepol => oepol,
tcknen => tcknen)
port map (trst, tck, tms, tdi, tdo, lltck, ltapo.tdi, ltapo.inst, ltapo.reset, ltapo.capt,
ltapo.shift, lupd, ltapo.asel, ltapo.dsel, ltapi.en, ltapi.tdo, tapi_tdo,
tapo_ninst, tapo_iupd, lltckn,
ahbi.testen, ahbi.testrst, ahbi.testoen, tdoen, tckn);
ltapo.tck <= ltck;
tapo_tckn <= ltckn;
gtckbuf : if (USEOLDCOM=0 and is_fpga(tech)/=0) generate
tckbuf: techbuf
generic map (buftype => 2, tech => tech)
port map (lltck, ltck);
ltckn <= not ltck;
end generate;
notckbuf: if not (USEOLDCOM=0 and is_fpga(tech)/=0) generate
ltck <= lltck;
ltckn <= lltckn;
end generate;
-- Quirk for Xilinx TAP - upd changes on falling TCK edge and
-- the flow doesn't maintain synchrony with user falling TCK edge logic.
gupdff : if (USEOLDCOM=0 and is_unisim(tech)/=0) generate
updff: grdff port map (ltck, lupd, ltapo.upd);
end generate;
noupdff: if not (USEOLDCOM=0 and is_unisim(tech)/=0) generate
ltapo.upd <= lupd;
end generate;
oldcom: if USEOLDCOM /= 0 generate
jtagcom0 : jtagcom generic map (isel => TAPSEL, nsync => nsync, ainst => ainst, dinst => dinst, reread => REREAD)
port map (rst, clk, ltapo, ltapi, dmao, dmai, ltck, ctrst);
end generate;
newcom: if USEOLDCOM=0 generate
jtagcom0 : jtagcom2 generic map (gatetech => tech, isel => TAPSEL, ainst => ainst, dinst => dinst)
port map (rst, clk, ltapo, ltapi, dmao, dmai, ltck, ltckn, ctrst);
end generate;
tapo_tck <= ltck; tapo_tdi <= ltapo.tdi; tapo_inst <= ltapo.inst;
tapo_rst <= ltapo.reset; tapo_capt <= ltapo.capt; tapo_shft <= ltapo.shift;
tapo_upd <= ltapo.upd;
-- Async reset for tck-domain FFs in jtagcom.
-- In FPGA configs use AMBA reset as real TRST may not be available.
-- For ASIC:s we want to use the real TRST to simplify constraining.
ctrst <= ahbi.testrst when scantest/=0 and ahbi.testen='1' else
rst when is_fpga(tech)/=0 else
trst;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbjtag AHB Debug JTAG rev " & tost(REVISION));
-- pragma translate_on
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Common primitives described as a function
--
-- Description:
-- ------------------------------------
-- This packages describes common primitives like flip flops and multiplexers
-- as a function to use them as one-liners.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
PACKAGE components IS
-- FlipFlop functions
function ffdre(q : STD_LOGIC; d : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- D-FlipFlop with reset and enable
function ffdre(q : STD_LOGIC_VECTOR; d : STD_LOGIC_VECTOR; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR; -- D-FlipFlop with reset and enable
function ffdse(q : STD_LOGIC; d : STD_LOGIC; set : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- D-FlipFlop with set and enable
function fftre(q : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- T-FlipFlop with reset and enable
function ffrs(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC; -- RS-FlipFlop with dominant rst
function ffsr(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC; -- RS-FlipFlop with dominant set
-- adder
function inc(value : STD_LOGIC_VECTOR; increment : NATURAL := 1) return STD_LOGIC_VECTOR;
function inc(value : UNSIGNED; increment : NATURAL := 1) return UNSIGNED;
function inc(value : SIGNED; increment : NATURAL := 1) return SIGNED;
function dec(value : STD_LOGIC_VECTOR; decrement : NATURAL := 1) return STD_LOGIC_VECTOR;
function dec(value : UNSIGNED; decrement : NATURAL := 1) return UNSIGNED;
function dec(value : SIGNED; decrement : NATURAL := 1) return SIGNED;
-- negate
function neg(value : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; -- calculate 2's complement
-- counter
function upcounter_next(cnt : UNSIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : NATURAL := 0) return UNSIGNED;
function upcounter_equal(cnt : UNSIGNED; value : NATURAL) return STD_LOGIC;
function downcounter_next(cnt : SIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : INTEGER := 0) return SIGNED;
function downcounter_equal(cnt : SIGNED; value : INTEGER) return STD_LOGIC;
function downcounter_neg(cnt : SIGNED) return STD_LOGIC;
-- shift/rotate registers
function sr_left(q : STD_LOGIC_VECTOR; i : STD_LOGIC) return STD_LOGIC_VECTOR;
function sr_right(q : STD_LOGIC_VECTOR; i : STD_LOGIC) return STD_LOGIC_VECTOR;
function rr_left(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function rr_right(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- compare
function comp(value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function comp(value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED;
function comp(value1 : SIGNED; value2 : SIGNED) return SIGNED;
function comp_allzero(value : STD_LOGIC_VECTOR) return STD_LOGIC;
function comp_allzero(value : UNSIGNED) return STD_LOGIC;
function comp_allzero(value : SIGNED) return STD_LOGIC;
function comp_allone(value : STD_LOGIC_VECTOR) return STD_LOGIC;
function comp_allone(value : UNSIGNED) return STD_LOGIC;
function comp_allone(value : SIGNED) return STD_LOGIC;
-- multiplexing
function mux(sel : STD_LOGIC; sl0 : STD_LOGIC; sl1 : STD_LOGIC) return STD_LOGIC;
function mux(sel : STD_LOGIC; slv0 : STD_LOGIC_VECTOR; slv1 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function mux(sel : STD_LOGIC; us0 : UNSIGNED; us1 : UNSIGNED) return UNSIGNED;
function mux(sel : STD_LOGIC; s0 : SIGNED; s1 : SIGNED) return SIGNED;
end;
package body components is
-- d-flipflop with reset and enable
function ffdre(q : STD_LOGIC; d : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is
begin
return ((d and en) or (q and not en)) and not rst;
end function;
function ffdre(q : STD_LOGIC_VECTOR; d : STD_LOGIC_VECTOR; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR is
begin
return ((d and (q'range => en)) or (q and not (q'range => en))) and not (q'range => rst);
end function;
-- d-flipflop with set and enable
function ffdse(q : STD_LOGIC; d : STD_LOGIC; set : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is
begin
return ((d and en) or (q and not en)) or set;
end function;
-- t-flipflop with reset and enable
function fftre(q : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is
begin
return ((not q and en) or (q and not en)) and not rst;
end function;
-- rs-flipflop with dominant rst
function ffrs(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC is
begin
return (q or set) and not rst;
end function;
-- rs-flipflop with dominant set
function ffsr(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC is
begin
return (q and not rst) or set;
end function;
-- adder
function inc(value : STD_LOGIC_VECTOR; increment : NATURAL := 1) return STD_LOGIC_VECTOR is
begin
return std_logic_vector(inc(unsigned(value), increment));
end function;
function inc(value : UNSIGNED; increment : NATURAL := 1) return UNSIGNED is
begin
return value + increment;
end function;
function inc(value : SIGNED; increment : NATURAL := 1) return SIGNED is
begin
return value + increment;
end function;
function dec(value : STD_LOGIC_VECTOR; decrement : NATURAL := 1) return STD_LOGIC_VECTOR is
begin
return std_logic_vector(dec(unsigned(value), decrement));
end function;
function dec(value : UNSIGNED; decrement : NATURAL := 1) return UNSIGNED is
begin
return value + decrement;
end function;
function dec(value : SIGNED; decrement : NATURAL := 1) return SIGNED is
begin
return value + decrement;
end function;
-- negate
function neg(value : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return std_logic_vector(inc(unsigned(not value))); -- 2's complement
end function;
-- counter
function upcounter_next(cnt : UNSIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : NATURAL := 0) return UNSIGNED is
begin
if (rst = '1') then
return to_unsigned(init, cnt'length);
elsif (en = '1') then
return cnt + 1;
else
return cnt;
end if;
end function;
function upcounter_equal(cnt : UNSIGNED; value : NATURAL) return STD_LOGIC is
begin
-- optimized comparison for only up counting values
return to_sl((cnt and to_unsigned(value, cnt'length)) = value);
end function;
function downcounter_next(cnt : SIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : INTEGER := 0) return SIGNED is
begin
if (rst = '1') then
return to_signed(init, cnt'length);
elsif (en = '1') then
return cnt - 1;
else
return cnt;
end if;
end function;
function downcounter_equal(cnt : SIGNED; value : INTEGER) return STD_LOGIC is
begin
-- optimized comparison for only down counting values
return to_sl((cnt nor to_signed(value, cnt'length)) /= value);
end function;
function downcounter_neg(cnt : SIGNED) return STD_LOGIC is
begin
return cnt(cnt'high);
end function;
-- shift/rotate registers
function sr_left(q : STD_LOGIC_VECTOR; i : std_logic) return STD_LOGIC_VECTOR is
begin
return q(q'left - 1 downto q'right) & i;
end function;
function sr_right(q : STD_LOGIC_VECTOR; i : std_logic) return STD_LOGIC_VECTOR is
begin
return i & q(q'left downto q'right - 1);
end function;
function rr_left(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return q(q'left - 1 downto q'right) & q(q'left);
end function;
function rr_right(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return q(q'right) & q(q'left downto q'right - 1);
end function;
-- compare functions
-- return value 1- => value1 < value2 (difference is negative)
-- return value 00 => value1 = value2 (difference is zero)
-- return value -1 => value1 > value2 (difference is positive)
function comp(value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
report "Comparing two STD_LOGIC_VECTORs - implicit conversion to UNSIGNED" severity WARNING;
return std_logic_vector(comp(unsigned(value1), unsigned(value2)));
end function;
function comp(value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED is
begin
if (value1 < value2) then
return "10";
elsif (value1 = value2) then
return "00";
else
return "01";
end if;
end function;
function comp(value1 : SIGNED; value2 : SIGNED) return SIGNED is
begin
if (value1 < value2) then
return "10";
elsif (value1 = value2) then
return "00";
else
return "01";
end if;
end function;
function comp_allzero(value : STD_LOGIC_VECTOR) return STD_LOGIC is
begin
return comp_allzero(unsigned(value));
end function;
function comp_allzero(value : UNSIGNED) return STD_LOGIC is
begin
return to_sl(value = (value'range => '0'));
end function;
function comp_allzero(value : SIGNED) return STD_LOGIC is
begin
return to_sl(value = (value'range => '0'));
end function;
function comp_allone(value : STD_LOGIC_VECTOR) return STD_LOGIC is
begin
return comp_allone(unsigned(value));
end function;
function comp_allone(value : UNSIGNED) return STD_LOGIC is
begin
return to_sl(value = (value'range => '1'));
end function;
function comp_allone(value : SIGNED) return STD_LOGIC is
begin
return to_sl(value = (value'range => '1'));
end function;
-- multiplexing
function mux(sel : STD_LOGIC; sl0 : STD_LOGIC; sl1 : STD_LOGIC) return STD_LOGIC is
begin
return (sl0 and not sel) or (sl1 and sel);
end function;
function mux(sel : STD_LOGIC; slv0 : STD_LOGIC_VECTOR; slv1 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return (slv0 and not (slv0'range => sel)) or (slv1 and (slv1'range => sel));
end function;
function mux(sel : STD_LOGIC; us0 : UNSIGNED; us1 : UNSIGNED) return UNSIGNED is
begin
return (us0 and not (us0'range => sel)) or (us1 and (us1'range => sel));
end function;
function mux(sel : STD_LOGIC; s0 : SIGNED; s1 : SIGNED) return SIGNED is
begin
return (s0 and not (s0'range => sel)) or (s1 and (s1'range => sel));
end function;
END PACKAGE BODY; |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Common primitives described as a function
--
-- Description:
-- ------------------------------------
-- This packages describes common primitives like flip flops and multiplexers
-- as a function to use them as one-liners.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
PACKAGE components IS
-- FlipFlop functions
function ffdre(q : STD_LOGIC; d : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- D-FlipFlop with reset and enable
function ffdre(q : STD_LOGIC_VECTOR; d : STD_LOGIC_VECTOR; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR; -- D-FlipFlop with reset and enable
function ffdse(q : STD_LOGIC; d : STD_LOGIC; set : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- D-FlipFlop with set and enable
function fftre(q : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- T-FlipFlop with reset and enable
function ffrs(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC; -- RS-FlipFlop with dominant rst
function ffsr(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC; -- RS-FlipFlop with dominant set
-- adder
function inc(value : STD_LOGIC_VECTOR; increment : NATURAL := 1) return STD_LOGIC_VECTOR;
function inc(value : UNSIGNED; increment : NATURAL := 1) return UNSIGNED;
function inc(value : SIGNED; increment : NATURAL := 1) return SIGNED;
function dec(value : STD_LOGIC_VECTOR; decrement : NATURAL := 1) return STD_LOGIC_VECTOR;
function dec(value : UNSIGNED; decrement : NATURAL := 1) return UNSIGNED;
function dec(value : SIGNED; decrement : NATURAL := 1) return SIGNED;
-- negate
function neg(value : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; -- calculate 2's complement
-- counter
function upcounter_next(cnt : UNSIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : NATURAL := 0) return UNSIGNED;
function upcounter_equal(cnt : UNSIGNED; value : NATURAL) return STD_LOGIC;
function downcounter_next(cnt : SIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : INTEGER := 0) return SIGNED;
function downcounter_equal(cnt : SIGNED; value : INTEGER) return STD_LOGIC;
function downcounter_neg(cnt : SIGNED) return STD_LOGIC;
-- shift/rotate registers
function sr_left(q : STD_LOGIC_VECTOR; i : STD_LOGIC) return STD_LOGIC_VECTOR;
function sr_right(q : STD_LOGIC_VECTOR; i : STD_LOGIC) return STD_LOGIC_VECTOR;
function rr_left(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function rr_right(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- compare
function comp(value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function comp(value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED;
function comp(value1 : SIGNED; value2 : SIGNED) return SIGNED;
function comp_allzero(value : STD_LOGIC_VECTOR) return STD_LOGIC;
function comp_allzero(value : UNSIGNED) return STD_LOGIC;
function comp_allzero(value : SIGNED) return STD_LOGIC;
function comp_allone(value : STD_LOGIC_VECTOR) return STD_LOGIC;
function comp_allone(value : UNSIGNED) return STD_LOGIC;
function comp_allone(value : SIGNED) return STD_LOGIC;
-- multiplexing
function mux(sel : STD_LOGIC; sl0 : STD_LOGIC; sl1 : STD_LOGIC) return STD_LOGIC;
function mux(sel : STD_LOGIC; slv0 : STD_LOGIC_VECTOR; slv1 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function mux(sel : STD_LOGIC; us0 : UNSIGNED; us1 : UNSIGNED) return UNSIGNED;
function mux(sel : STD_LOGIC; s0 : SIGNED; s1 : SIGNED) return SIGNED;
end;
package body components is
-- d-flipflop with reset and enable
function ffdre(q : STD_LOGIC; d : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is
begin
return ((d and en) or (q and not en)) and not rst;
end function;
function ffdre(q : STD_LOGIC_VECTOR; d : STD_LOGIC_VECTOR; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR is
begin
return ((d and (q'range => en)) or (q and not (q'range => en))) and not (q'range => rst);
end function;
-- d-flipflop with set and enable
function ffdse(q : STD_LOGIC; d : STD_LOGIC; set : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is
begin
return ((d and en) or (q and not en)) or set;
end function;
-- t-flipflop with reset and enable
function fftre(q : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is
begin
return ((not q and en) or (q and not en)) and not rst;
end function;
-- rs-flipflop with dominant rst
function ffrs(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC is
begin
return (q or set) and not rst;
end function;
-- rs-flipflop with dominant set
function ffsr(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC is
begin
return (q and not rst) or set;
end function;
-- adder
function inc(value : STD_LOGIC_VECTOR; increment : NATURAL := 1) return STD_LOGIC_VECTOR is
begin
return std_logic_vector(inc(unsigned(value), increment));
end function;
function inc(value : UNSIGNED; increment : NATURAL := 1) return UNSIGNED is
begin
return value + increment;
end function;
function inc(value : SIGNED; increment : NATURAL := 1) return SIGNED is
begin
return value + increment;
end function;
function dec(value : STD_LOGIC_VECTOR; decrement : NATURAL := 1) return STD_LOGIC_VECTOR is
begin
return std_logic_vector(dec(unsigned(value), decrement));
end function;
function dec(value : UNSIGNED; decrement : NATURAL := 1) return UNSIGNED is
begin
return value + decrement;
end function;
function dec(value : SIGNED; decrement : NATURAL := 1) return SIGNED is
begin
return value + decrement;
end function;
-- negate
function neg(value : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return std_logic_vector(inc(unsigned(not value))); -- 2's complement
end function;
-- counter
function upcounter_next(cnt : UNSIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : NATURAL := 0) return UNSIGNED is
begin
if (rst = '1') then
return to_unsigned(init, cnt'length);
elsif (en = '1') then
return cnt + 1;
else
return cnt;
end if;
end function;
function upcounter_equal(cnt : UNSIGNED; value : NATURAL) return STD_LOGIC is
begin
-- optimized comparison for only up counting values
return to_sl((cnt and to_unsigned(value, cnt'length)) = value);
end function;
function downcounter_next(cnt : SIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : INTEGER := 0) return SIGNED is
begin
if (rst = '1') then
return to_signed(init, cnt'length);
elsif (en = '1') then
return cnt - 1;
else
return cnt;
end if;
end function;
function downcounter_equal(cnt : SIGNED; value : INTEGER) return STD_LOGIC is
begin
-- optimized comparison for only down counting values
return to_sl((cnt nor to_signed(value, cnt'length)) /= value);
end function;
function downcounter_neg(cnt : SIGNED) return STD_LOGIC is
begin
return cnt(cnt'high);
end function;
-- shift/rotate registers
function sr_left(q : STD_LOGIC_VECTOR; i : std_logic) return STD_LOGIC_VECTOR is
begin
return q(q'left - 1 downto q'right) & i;
end function;
function sr_right(q : STD_LOGIC_VECTOR; i : std_logic) return STD_LOGIC_VECTOR is
begin
return i & q(q'left downto q'right - 1);
end function;
function rr_left(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return q(q'left - 1 downto q'right) & q(q'left);
end function;
function rr_right(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return q(q'right) & q(q'left downto q'right - 1);
end function;
-- compare functions
-- return value 1- => value1 < value2 (difference is negative)
-- return value 00 => value1 = value2 (difference is zero)
-- return value -1 => value1 > value2 (difference is positive)
function comp(value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
report "Comparing two STD_LOGIC_VECTORs - implicit conversion to UNSIGNED" severity WARNING;
return std_logic_vector(comp(unsigned(value1), unsigned(value2)));
end function;
function comp(value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED is
begin
if (value1 < value2) then
return "10";
elsif (value1 = value2) then
return "00";
else
return "01";
end if;
end function;
function comp(value1 : SIGNED; value2 : SIGNED) return SIGNED is
begin
if (value1 < value2) then
return "10";
elsif (value1 = value2) then
return "00";
else
return "01";
end if;
end function;
function comp_allzero(value : STD_LOGIC_VECTOR) return STD_LOGIC is
begin
return comp_allzero(unsigned(value));
end function;
function comp_allzero(value : UNSIGNED) return STD_LOGIC is
begin
return to_sl(value = (value'range => '0'));
end function;
function comp_allzero(value : SIGNED) return STD_LOGIC is
begin
return to_sl(value = (value'range => '0'));
end function;
function comp_allone(value : STD_LOGIC_VECTOR) return STD_LOGIC is
begin
return comp_allone(unsigned(value));
end function;
function comp_allone(value : UNSIGNED) return STD_LOGIC is
begin
return to_sl(value = (value'range => '1'));
end function;
function comp_allone(value : SIGNED) return STD_LOGIC is
begin
return to_sl(value = (value'range => '1'));
end function;
-- multiplexing
function mux(sel : STD_LOGIC; sl0 : STD_LOGIC; sl1 : STD_LOGIC) return STD_LOGIC is
begin
return (sl0 and not sel) or (sl1 and sel);
end function;
function mux(sel : STD_LOGIC; slv0 : STD_LOGIC_VECTOR; slv1 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return (slv0 and not (slv0'range => sel)) or (slv1 and (slv1'range => sel));
end function;
function mux(sel : STD_LOGIC; us0 : UNSIGNED; us1 : UNSIGNED) return UNSIGNED is
begin
return (us0 and not (us0'range => sel)) or (us1 and (us1'range => sel));
end function;
function mux(sel : STD_LOGIC; s0 : SIGNED; s1 : SIGNED) return SIGNED is
begin
return (s0 and not (s0'range => sel)) or (s1 and (s1'range => sel));
end function;
END PACKAGE BODY; |
library ieee;
use ieee.std_logic_1164.all;
entity clk_div is
generic (
period_g : in positive);
port (
rst_i : in std_ulogic := '0';
clk_i : in std_ulogic;
clk_o : out std_ulogic);
begin
assert period_g >= 2 and period_g mod 2 = 0
report "clk_div: invalid period_g";
end;
architecture rtl of clk_div is
signal clk : std_ulogic := '0';
signal cnt : natural range 0 to period_g/2 - 1 := 0;
begin
process(rst_i, clk_i)
begin
if rst_i = '1' then
clk <= '0';
cnt <= 0;
elsif rising_edge(clk_i) then
if cnt = period_g/2 - 1 then
clk <= not clk;
cnt <= 0;
else
cnt <= cnt + 1;
end if;
end if;
end process;
clk_o <= clk;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity foo is
port (
a : std_logic;
b : std_logic_vector(7 downto 0)
);
end entity foo;
architecture RTL of foo is
signal s_test : std_logic_vector(3 downto 0) := "1111";
begin
cmp_bar: entity work.bar
port map(
a => a
);
gen_bars: for i in 0 to 1 generate
cmp_generated_bar: entity work.bar
port map(
a => a
);
end generate gen_bars;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:50:31 01/26/2015
-- Design Name:
-- Module Name: test - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test is
Port ( sw : in STD_LOGIC_VECTOR (4 downto 0);
led : out STD_LOGIC_VECTOR (4 downto 0);
cpld_led : out STD_LOGIC_VECTOR (4 downto 0)
);
end test;
architecture Behavioral of test is
begin
led <= sw;
cpld_led <= "11100";
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Demultiplexer_4x16 is
Port ( Selector : in STD_LOGIC_VECTOR(3 downto 0);
input: in STD_LOGIC_VECTOR (15 downto 0);
output_A, output_B, output_C, output_D, output_E, output_F, output_G, output_H : out STD_LOGIC_VECTOR (15 downto 0);
output_I, output_J, output_K, output_L, output_M, output_N, output_O, output_P : out STD_LOGIC_VECTOR (15 downto 0));
end Demultiplexer_4x16;
architecture skeleton of Demultiplexer_4x16 is
begin
with Selector select
output_A <= input when "0000",
"0000000000000000" when others;
with Selector select
output_B <= input when "0001",
"0000000000000000" when others;
with Selector select
output_C <= input when "0010",
"0000000000000000" when others;
with Selector select
output_D <= input when "0011",
"0000000000000000" when others;
with Selector select
output_E <= input when "0100",
"0000000000000000" when others;
with Selector select
output_F <= input when "0101",
"0000000000000000" when others;
with Selector select
output_G <= input when "0110",
"0000000000000000" when others;
with Selector select
output_H <= input when "0111",
"0000000000000000" when others;
with Selector select
output_I <= input when "1000",
"0000000000000000" when others;
with Selector select
output_J <= input when "1001",
"0000000000000000" when others;
with Selector select
output_K <= input when "1010",
"0000000000000000" when others;
with Selector select
output_L <= input when "1011",
"0000000000000000" when others;
with Selector select
output_M <= input when "1100",
"0000000000000000" when others;
with Selector select
output_N <= input when "1101",
"0000000000000000" when others;
with Selector select
output_O <= input when "1110",
"0000000000000000" when others;
with Selector select
output_P <= input when "1111",
"0000000000000000" when others;
end skeleton; |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: controller_command_fifo_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity controller_command_fifo_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(128-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(128-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end controller_command_fifo_top_wrapper;
architecture xilinx of controller_command_fifo_top_wrapper is
SIGNAL clk_i : std_logic;
component controller_command_fifo_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(5-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : controller_command_fifo_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: weights_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY weights_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE weights_synth_ARCH OF weights_synth IS
COMPONENT weights_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(23 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 24,
READ_WIDTH => 24 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: weights_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
--
-- @file CMU.vhd
-- @date December, 2013
-- @author G. Roggemans <g.roggemans@grog.be>
-- @copyright Copyright (c) GROG [https://grog.be] 2013, All Rights Reserved
--
-- This application is free software: you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- This application is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
-- for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this application. If not, see <http://www.gnu.org/licenses/>.
--
--
-- entity CMU
--
-- CMU(Clock Managment Unit) verzorgt de verscheidene klokken die gebruikt worden in dit project
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CMU is
Port ( clk : in STD_LOGIC; -- basis klok 50Mhz
clk_25MHz : out STD_LOGIC; -- uitgang klok 25Mhz
clk_25Hz : out STD_LOGIC); -- uitgang klok 25Hz
end CMU;
architecture Behavioral of CMU is
signal c_clk_25MHz : STD_LOGIC:='0'; -- klok 25Mhz
signal c_clk_25Hz : STD_LOGIC:='0'; -- klok 25Hz
signal count : integer range 0 to 999999; -- counter value
begin
process (clk) begin
if rising_edge (clk) then
c_clk_25MHz <= not c_clk_25MHz; -- telkens op rising edge togle geeft 50Mhz/2 -> 25Mhz
if count = 999999 then -- telken op rising maar slechts om de (50Mhz/2) / 1 000 000 -> 25Hz
c_clk_25Hz <= not c_clk_25Hz;
count <= 0;
else
count <= count + 1;
end if;
end if;
end process;
clk_25MHz <= c_clk_25MHz;
clk_25Hz <= c_clk_25Hz;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:10:39 07/20/2015
-- Design Name:
-- Module Name: FPGA1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FPGA1 is
Port ( k5 : in STD_LOGIC_VECTOR (7 downto 0);
k6 : in STD_LOGIC_VECTOR (7 downto 0);
s0 : out STD_LOGIC_VECTOR (7 downto 0);
s1 : out STD_LOGIC_VECTOR (7 downto 0);
B : out STD_LOGIC_VECTOR (7 downto 0));
end FPGA1;
architecture Behavioral of FPGA1 is
begin
process(k5, k6)
begin
s0 <= k5;
s1 <= k5;
B <= k6;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_hack is
end tb_hack;
architecture Behavioral of tb_hack is
signal clock : std_ulogic := '0';
signal reset : std_ulogic := '0';
begin
clock <= not clock after 7.57575757 ns;
uut : entity work.Hack(Behavioral)
port map (
clock => clock,
reset => reset
);
stimuli : process
begin
reset <= '1';
wait for 10 us;
reset <= '0';
wait for 1000 ms;
wait;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc768.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p07n01i00768ent_a IS
port ( c1 : in integer ;
c2 : out integer );
END c01s01b01x02p07n01i00768ent_a;
ARCHITECTURE c01s01b01x02p07n01i00768arch_a OF c01s01b01x02p07n01i00768ent_a IS
BEGIN
c2 <= c1;
END c01s01b01x02p07n01i00768arch_a;
ENTITY c01s01b01x02p07n01i00768ent IS
port ( p1 : in integer ;
p2 : out integer );
END c01s01b01x02p07n01i00768ent;
ARCHITECTURE c01s01b01x02p07n01i00768arch OF c01s01b01x02p07n01i00768ent IS
component c01s01b01x02p07n01i00768ent_b
port ( c1 : in integer ;
c2 : out integer );
end component;
for L : c01s01b01x02p07n01i00768ent_b use entity work.c01s01b01x02p07n01i00768ent_a(c01s01b01x02p07n01i00768arch_a);
BEGIN
L : c01s01b01x02p07n01i00768ent_b port map (p1, p2);
-- Success_here
-- The formal c2 is of mode out .
-- The corresponding actual p2 is of
-- mode out which is legal
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b01x02p07n01i00768"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b01x02p07n01i00768arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc768.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p07n01i00768ent_a IS
port ( c1 : in integer ;
c2 : out integer );
END c01s01b01x02p07n01i00768ent_a;
ARCHITECTURE c01s01b01x02p07n01i00768arch_a OF c01s01b01x02p07n01i00768ent_a IS
BEGIN
c2 <= c1;
END c01s01b01x02p07n01i00768arch_a;
ENTITY c01s01b01x02p07n01i00768ent IS
port ( p1 : in integer ;
p2 : out integer );
END c01s01b01x02p07n01i00768ent;
ARCHITECTURE c01s01b01x02p07n01i00768arch OF c01s01b01x02p07n01i00768ent IS
component c01s01b01x02p07n01i00768ent_b
port ( c1 : in integer ;
c2 : out integer );
end component;
for L : c01s01b01x02p07n01i00768ent_b use entity work.c01s01b01x02p07n01i00768ent_a(c01s01b01x02p07n01i00768arch_a);
BEGIN
L : c01s01b01x02p07n01i00768ent_b port map (p1, p2);
-- Success_here
-- The formal c2 is of mode out .
-- The corresponding actual p2 is of
-- mode out which is legal
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b01x02p07n01i00768"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b01x02p07n01i00768arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc768.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p07n01i00768ent_a IS
port ( c1 : in integer ;
c2 : out integer );
END c01s01b01x02p07n01i00768ent_a;
ARCHITECTURE c01s01b01x02p07n01i00768arch_a OF c01s01b01x02p07n01i00768ent_a IS
BEGIN
c2 <= c1;
END c01s01b01x02p07n01i00768arch_a;
ENTITY c01s01b01x02p07n01i00768ent IS
port ( p1 : in integer ;
p2 : out integer );
END c01s01b01x02p07n01i00768ent;
ARCHITECTURE c01s01b01x02p07n01i00768arch OF c01s01b01x02p07n01i00768ent IS
component c01s01b01x02p07n01i00768ent_b
port ( c1 : in integer ;
c2 : out integer );
end component;
for L : c01s01b01x02p07n01i00768ent_b use entity work.c01s01b01x02p07n01i00768ent_a(c01s01b01x02p07n01i00768arch_a);
BEGIN
L : c01s01b01x02p07n01i00768ent_b port map (p1, p2);
-- Success_here
-- The formal c2 is of mode out .
-- The corresponding actual p2 is of
-- mode out which is legal
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b01x02p07n01i00768"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b01x02p07n01i00768arch;
|
--
-- 16450 compatible UART with synchronous bus interface
-- RClk/BaudOut is XIn enable instead of actual clock
--
-- Version : 0249b
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First release
--
-- 0249 : Fixed interrupt and baud rate bugs found by Andy Dyer
-- Added modem status and break detection
-- Added support for 1.5 and 2 stop bits
--
-- 0249b : Fixed loopback break generation bugs found by Andy Dyer
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T16450 is
port(
MR_n : in std_logic;
XIn : in std_logic;
RClk : in std_logic;
CS_n : in std_logic;
Rd_n : in std_logic;
Wr_n : in std_logic;
A : in std_logic_vector(2 downto 0);
D_In : in std_logic_vector(7 downto 0);
D_Out : out std_logic_vector(7 downto 0);
SIn : in std_logic;
CTS_n : in std_logic;
DSR_n : in std_logic;
RI_n : in std_logic;
DCD_n : in std_logic;
SOut : out std_logic;
RTS_n : out std_logic;
DTR_n : out std_logic;
OUT1_n : out std_logic;
OUT2_n : out std_logic;
BaudOut : out std_logic;
Intr : out std_logic
);
end T16450;
architecture rtl of T16450 is
signal RBR : std_logic_vector(7 downto 0); -- Reciever Buffer Register
signal THR : std_logic_vector(7 downto 0); -- Transmitter Holding Register
signal IER : std_logic_vector(7 downto 0); -- Interrupt Enable Register
signal IIR : std_logic_vector(7 downto 0); -- Interrupt Ident. Register
signal LCR : std_logic_vector(7 downto 0); -- Line Control Register
signal MCR : std_logic_vector(7 downto 0); -- MODEM Control Register
signal LSR : std_logic_vector(7 downto 0); -- Line Status Register
signal MSR : std_logic_vector(7 downto 0); -- MODEM Status Register
signal SCR : std_logic_vector(7 downto 0); -- Scratch Register
signal DLL : std_logic_vector(7 downto 0); -- Divisor Latch (LS)
signal DLM : std_logic_vector(7 downto 0); -- Divisor Latch (MS)
signal DM0 : std_logic_vector(7 downto 0);
signal DM1 : std_logic_vector(7 downto 0);
signal MSR_In : std_logic_vector(3 downto 0);
signal Bit_Phase : unsigned(3 downto 0);
signal Brk_Cnt : unsigned(3 downto 0);
signal RX_Filtered : std_logic;
signal RX_ShiftReg : std_logic_vector(7 downto 0);
signal RX_Bit_Cnt : integer range 0 to 11;
signal RX_Parity : std_logic;
signal RXD : std_logic;
signal TX_Tick : std_logic;
signal TX_ShiftReg : std_logic_vector(7 downto 0);
signal TX_Bit_Cnt : integer range 0 to 11;
signal TX_Parity : std_logic;
signal TX_Next_Is_Stop : std_logic;
signal TX_Stop_Bit : std_logic;
signal TXD : std_logic;
begin
DTR_n <= MCR(4) or not MCR(0);
RTS_n <= MCR(4) or not MCR(1);
OUT1_n <= MCR(4) or not MCR(2);
OUT2_n <= MCR(4) or not MCR(3);
SOut <= MCR(4) or (TXD and not LCR(6));
RXD <= SIn when MCR(4) = '0' else (TXD and not LCR(6));
Intr <= not IIR(0);
-- Registers
DM0 <= DLL when LCR(7) = '1' else RBR;
DM1 <= DLM when LCR(7) = '1' else IER;
with A select
D_Out <=
DM0 when "000",
DM1 when "001",
IIR when "010",
LCR when "011",
MCR when "100",
LSR when "101",
MSR when "110",
SCR when others;
process (MR_n, XIn)
begin
if MR_n = '0' then
THR <= "00000000";
IER <= "00000000";
LCR <= "00000000";
MCR <= "00000000";
MSR(3 downto 0) <= "0000";
SCR <= "00000000"; -- ??
DLL <= "00000000"; -- ??
DLM <= "00000000"; -- ??
elsif XIn'event and XIn = '1' then
if Wr_n = '0' and CS_n = '0' then
case A is
when "000" =>
if LCR(7) = '1' then
DLL <= D_In;
else
THR <= D_In;
end if;
when "001" =>
if LCR(7) = '1' then
DLM <= D_In;
else
IER(3 downto 0) <= D_In(3 downto 0);
end if;
when "011" =>
LCR <= D_In;
when "100" =>
MCR <= D_In;
when "111" =>
SCR <= D_In;
when others =>
end case;
end if;
if Rd_n = '0' and CS_n = '0' and A = "110" then
MSR(3 downto 0) <= "0000";
end if;
if MSR(4) /= MSR_In(0) then
MSR(0) <= '1';
end if;
if MSR(5) /= MSR_In(1) then
MSR(1) <= '1';
end if;
if MSR(6) = '0' and MSR_In(2) = '1' then
MSR(2) <= '1';
end if;
if MSR(7) /= MSR_In(3) then
MSR(3) <= '1';
end if;
end if;
end process;
process (XIn)
begin
if XIn'event and XIn = '1' then
if MCR(4) = '0' then
MSR(4) <= MSR_In(0);
MSR(5) <= MSR_In(1);
MSR(6) <= MSR_In(2);
MSR(7) <= MSR_In(3);
else
MSR(4) <= MCR(1);
MSR(5) <= MCR(0);
MSR(6) <= MCR(2);
MSR(7) <= MCR(3);
end if;
MSR_In(0) <= CTS_n;
MSR_In(1) <= DSR_n;
MSR_In(2) <= RI_n;
MSR_In(3) <= DCD_n;
end if;
end process;
IIR(7 downto 3) <= "00000";
IIR(2 downto 0) <=
"110" when IER(2) = '1' and LSR(4 downto 1) /= "0000" else
"100" when (IER(0) and LSR(0)) = '1' else
"010" when (IER(1) and LSR(5)) = '1' else
"000" when IER(3) = '1' and ((MCR(4) = '0' and MSR(3 downto 0) /= "0000") or
(MCR(4) = '1' and MCR(3 downto 0) /= "0000")) else
"001";
-- Baud x 16 clock generator
process (MR_n, XIn)
variable Baud_Cnt : unsigned(15 downto 0);
begin
if MR_n = '0' then
Baud_Cnt := "0000000000000000";
BaudOut <= '0';
elsif XIn'event and XIn = '1' then
if Baud_Cnt(15 downto 1) = "000000000000000" or (Wr_n = '0' and CS_n = '0' and A(2 downto 1) = "00" and LCR(7) = '1') then
Baud_Cnt(15 downto 8) := unsigned(DLM);
Baud_Cnt(7 downto 0) := unsigned(DLL);
BaudOut <= '1';
else
Baud_Cnt := Baud_Cnt - 1;
BaudOut <= '0';
end if;
end if;
end process;
-- Input filter
process (MR_n, XIn)
variable Samples : std_logic_vector(1 downto 0);
begin
if MR_n = '0' then
Samples := "11";
RX_Filtered <= '1';
elsif XIn'event and XIn = '1' then
if RClk = '1' then
Samples(1) := Samples(0);
Samples(0) := RXD;
end if;
if Samples = "00" then
RX_Filtered <= '0';
end if;
if Samples = "11" then
RX_Filtered <= '1';
end if;
end if;
end process;
-- Receive state machine
process (MR_n, XIn)
begin
if MR_n = '0' then
RBR <= "00000000";
LSR(4 downto 0) <= "00000";
Bit_Phase <= "0000";
Brk_Cnt <= "0000";
RX_ShiftReg(7 downto 0) <= "00000000";
RX_Bit_Cnt <= 0;
RX_Parity <= '0';
elsif XIn'event and XIn = '1' then
if A = "000" and LCR(7) = '0' and Rd_n = '0' and CS_n = '0' then
LSR(0) <= '0'; -- DR
end if;
if A = "101" and Rd_n = '0' and CS_n = '0' then
LSR(4) <= '0'; -- BI
LSR(3) <= '0'; -- FE
LSR(2) <= '0'; -- PE
LSR(1) <= '0'; -- OE
end if;
if RClk = '1' then
if RX_Bit_Cnt = 0 and (RX_Filtered = '1' or Bit_Phase = "0111") then
Bit_Phase <= "0000";
else
Bit_Phase <= Bit_Phase + 1;
end if;
if Bit_Phase = "1111" then
if RX_Filtered = '1' then
Brk_Cnt <= "0000";
else
Brk_Cnt <= Brk_Cnt + 1;
end if;
if Brk_Cnt = "1100" then
LSR(4) <= '1'; -- BI
end if;
end if;
if RX_Bit_Cnt = 0 then
if Bit_Phase = "0111" then
RX_Bit_Cnt <= RX_Bit_Cnt + 1;
RX_Parity <= not LCR(4); -- EPS
end if;
elsif Bit_Phase = "1111" then
RX_Bit_Cnt <= RX_Bit_Cnt + 1;
if RX_Bit_Cnt = 10 then -- Parity stop bit
RX_Bit_Cnt <= 0;
LSR(0) <= '1'; -- UART Receive complete
LSR(3) <= not RX_Filtered; -- Framing error
elsif (RX_Bit_Cnt = 9 and LCR(1 downto 0) = "11") or
(RX_Bit_Cnt = 8 and LCR(1 downto 0) = "10") or
(RX_Bit_Cnt = 7 and LCR(1 downto 0) = "01") or
(RX_Bit_Cnt = 6 and LCR(1 downto 0) = "00") then -- Stop bit/Parity
RX_Bit_Cnt <= 0;
if LCR(3) = '1' then -- PEN
RX_Bit_Cnt <= 10;
if LCR(5) = '1' then -- Stick parity
if RX_Filtered = LCR(4) then
LSR(2) <= '1';
end if;
else
if RX_Filtered /= RX_Parity then
LSR(2) <= '1';
end if;
end if;
else
LSR(0) <= '1'; -- UART Receive complete
LSR(3) <= not RX_Filtered; -- Framing error
end if;
RBR <= RX_ShiftReg(7 downto 0);
LSR(1) <= LSR(0);
if A = "101" and Rd_n = '0' and CS_n = '0' then
LSR(1) <= '0';
end if;
else
RX_ShiftReg(6 downto 0) <= RX_ShiftReg(7 downto 1);
RX_ShiftReg(7) <= RX_Filtered;
if LCR(1 downto 0) = "10" then
RX_ShiftReg(7) <= '0';
RX_ShiftReg(6) <= RX_Filtered;
end if;
if LCR(1 downto 0) = "01" then
RX_ShiftReg(7) <= '0';
RX_ShiftReg(6) <= '0';
RX_ShiftReg(5) <= RX_Filtered;
end if;
if LCR(1 downto 0) = "00" then
RX_ShiftReg(7) <= '0';
RX_ShiftReg(6) <= '0';
RX_ShiftReg(5) <= '0';
RX_ShiftReg(4) <= RX_Filtered;
end if;
RX_Parity <= RX_Filtered xor RX_Parity;
end if;
end if;
end if;
end if;
end process;
-- Transmit bit tick
process (MR_n, XIn)
variable TX_Cnt : unsigned(4 downto 0);
begin
if MR_n = '0' then
TX_Cnt := "00000";
TX_Tick <= '0';
elsif XIn'event and XIn = '1' then
TX_Tick <= '0';
if RClk = '1' then
TX_Cnt := TX_Cnt + 1;
if LCR(2) = '1' and TX_Stop_Bit = '1' then
if LCR(1 downto 0) = "00" then
if TX_Cnt = "10111" then
TX_Tick <= '1';
TX_Cnt(3 downto 0) := "0000";
end if;
else
if TX_Cnt = "11111" then
TX_Tick <= '1';
TX_Cnt(3 downto 0) := "0000";
end if;
end if;
else
TX_Cnt(4) := '1';
if TX_Cnt(3 downto 0) = "1111" then
TX_Tick <= '1';
end if;
end if;
end if;
end if;
end process;
-- Transmit state machine
process (MR_n, XIn)
begin
if MR_n = '0' then
LSR(7 downto 5) <= "011";
TX_Bit_Cnt <= 0;
TX_ShiftReg <= (others => '0');
TXD <= '1';
TX_Parity <= '0';
TX_Next_Is_Stop <= '0';
TX_Stop_Bit <= '0';
elsif XIn'event and XIn = '1' then
if TX_Tick = '1' then
TX_Next_Is_Stop <= '0';
TX_Stop_Bit <= TX_Next_Is_Stop;
case TX_Bit_Cnt is
when 0 =>
if LSR(5) <= '0' then -- THRE
TX_Bit_Cnt <= 1;
end if;
TXD <= '1';
when 1 => -- Start bit
TX_ShiftReg(7 downto 0) <= THR;
LSR(5) <= '1'; -- THRE
TXD <= '0';
TX_Parity <= not LCR(4); -- EPS
TX_Bit_Cnt <= TX_Bit_Cnt + 1;
when 10 => -- Parity bit
TXD <= TX_Parity;
if LCR(5) = '1' then -- Stick parity
TXD <= not LCR(4);
end if;
TX_Bit_Cnt <= 0;
TX_Next_Is_Stop <= '1';
when others =>
TX_Bit_Cnt <= TX_Bit_Cnt + 1;
if (TX_Bit_Cnt = 9 and LCR(1 downto 0) = "11") or
(TX_Bit_Cnt = 8 and LCR(1 downto 0) = "10") or
(TX_Bit_Cnt = 7 and LCR(1 downto 0) = "01") or
(TX_Bit_Cnt = 6 and LCR(1 downto 0) = "00") then
TX_Bit_Cnt <= 0;
if LCR(3) = '1' then -- PEN
TX_Bit_Cnt <= 10;
else
TX_Next_Is_Stop <= '1';
end if;
LSR(6) <= '1'; -- TEMT
end if;
TXD <= TX_ShiftReg(0);
TX_ShiftReg(6 downto 0) <= TX_ShiftReg(7 downto 1);
TX_Parity <= TX_ShiftReg(0) xor TX_Parity;
end case;
end if;
if Wr_n = '0' and CS_n = '0' and A = "000" and LCR(7) = '0' then
LSR(5) <= '0'; -- THRE
LSR(6) <= '0'; -- TEMT
end if;
end if;
end process;
end;
|
--
-- 16450 compatible UART with synchronous bus interface
-- RClk/BaudOut is XIn enable instead of actual clock
--
-- Version : 0249b
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First release
--
-- 0249 : Fixed interrupt and baud rate bugs found by Andy Dyer
-- Added modem status and break detection
-- Added support for 1.5 and 2 stop bits
--
-- 0249b : Fixed loopback break generation bugs found by Andy Dyer
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T16450 is
port(
MR_n : in std_logic;
XIn : in std_logic;
RClk : in std_logic;
CS_n : in std_logic;
Rd_n : in std_logic;
Wr_n : in std_logic;
A : in std_logic_vector(2 downto 0);
D_In : in std_logic_vector(7 downto 0);
D_Out : out std_logic_vector(7 downto 0);
SIn : in std_logic;
CTS_n : in std_logic;
DSR_n : in std_logic;
RI_n : in std_logic;
DCD_n : in std_logic;
SOut : out std_logic;
RTS_n : out std_logic;
DTR_n : out std_logic;
OUT1_n : out std_logic;
OUT2_n : out std_logic;
BaudOut : out std_logic;
Intr : out std_logic
);
end T16450;
architecture rtl of T16450 is
signal RBR : std_logic_vector(7 downto 0); -- Reciever Buffer Register
signal THR : std_logic_vector(7 downto 0); -- Transmitter Holding Register
signal IER : std_logic_vector(7 downto 0); -- Interrupt Enable Register
signal IIR : std_logic_vector(7 downto 0); -- Interrupt Ident. Register
signal LCR : std_logic_vector(7 downto 0); -- Line Control Register
signal MCR : std_logic_vector(7 downto 0); -- MODEM Control Register
signal LSR : std_logic_vector(7 downto 0); -- Line Status Register
signal MSR : std_logic_vector(7 downto 0); -- MODEM Status Register
signal SCR : std_logic_vector(7 downto 0); -- Scratch Register
signal DLL : std_logic_vector(7 downto 0); -- Divisor Latch (LS)
signal DLM : std_logic_vector(7 downto 0); -- Divisor Latch (MS)
signal DM0 : std_logic_vector(7 downto 0);
signal DM1 : std_logic_vector(7 downto 0);
signal MSR_In : std_logic_vector(3 downto 0);
signal Bit_Phase : unsigned(3 downto 0);
signal Brk_Cnt : unsigned(3 downto 0);
signal RX_Filtered : std_logic;
signal RX_ShiftReg : std_logic_vector(7 downto 0);
signal RX_Bit_Cnt : integer range 0 to 11;
signal RX_Parity : std_logic;
signal RXD : std_logic;
signal TX_Tick : std_logic;
signal TX_ShiftReg : std_logic_vector(7 downto 0);
signal TX_Bit_Cnt : integer range 0 to 11;
signal TX_Parity : std_logic;
signal TX_Next_Is_Stop : std_logic;
signal TX_Stop_Bit : std_logic;
signal TXD : std_logic;
begin
DTR_n <= MCR(4) or not MCR(0);
RTS_n <= MCR(4) or not MCR(1);
OUT1_n <= MCR(4) or not MCR(2);
OUT2_n <= MCR(4) or not MCR(3);
SOut <= MCR(4) or (TXD and not LCR(6));
RXD <= SIn when MCR(4) = '0' else (TXD and not LCR(6));
Intr <= not IIR(0);
-- Registers
DM0 <= DLL when LCR(7) = '1' else RBR;
DM1 <= DLM when LCR(7) = '1' else IER;
with A select
D_Out <=
DM0 when "000",
DM1 when "001",
IIR when "010",
LCR when "011",
MCR when "100",
LSR when "101",
MSR when "110",
SCR when others;
process (MR_n, XIn)
begin
if MR_n = '0' then
THR <= "00000000";
IER <= "00000000";
LCR <= "00000000";
MCR <= "00000000";
MSR(3 downto 0) <= "0000";
SCR <= "00000000"; -- ??
DLL <= "00000000"; -- ??
DLM <= "00000000"; -- ??
elsif XIn'event and XIn = '1' then
if Wr_n = '0' and CS_n = '0' then
case A is
when "000" =>
if LCR(7) = '1' then
DLL <= D_In;
else
THR <= D_In;
end if;
when "001" =>
if LCR(7) = '1' then
DLM <= D_In;
else
IER(3 downto 0) <= D_In(3 downto 0);
end if;
when "011" =>
LCR <= D_In;
when "100" =>
MCR <= D_In;
when "111" =>
SCR <= D_In;
when others =>
end case;
end if;
if Rd_n = '0' and CS_n = '0' and A = "110" then
MSR(3 downto 0) <= "0000";
end if;
if MSR(4) /= MSR_In(0) then
MSR(0) <= '1';
end if;
if MSR(5) /= MSR_In(1) then
MSR(1) <= '1';
end if;
if MSR(6) = '0' and MSR_In(2) = '1' then
MSR(2) <= '1';
end if;
if MSR(7) /= MSR_In(3) then
MSR(3) <= '1';
end if;
end if;
end process;
process (XIn)
begin
if XIn'event and XIn = '1' then
if MCR(4) = '0' then
MSR(4) <= MSR_In(0);
MSR(5) <= MSR_In(1);
MSR(6) <= MSR_In(2);
MSR(7) <= MSR_In(3);
else
MSR(4) <= MCR(1);
MSR(5) <= MCR(0);
MSR(6) <= MCR(2);
MSR(7) <= MCR(3);
end if;
MSR_In(0) <= CTS_n;
MSR_In(1) <= DSR_n;
MSR_In(2) <= RI_n;
MSR_In(3) <= DCD_n;
end if;
end process;
IIR(7 downto 3) <= "00000";
IIR(2 downto 0) <=
"110" when IER(2) = '1' and LSR(4 downto 1) /= "0000" else
"100" when (IER(0) and LSR(0)) = '1' else
"010" when (IER(1) and LSR(5)) = '1' else
"000" when IER(3) = '1' and ((MCR(4) = '0' and MSR(3 downto 0) /= "0000") or
(MCR(4) = '1' and MCR(3 downto 0) /= "0000")) else
"001";
-- Baud x 16 clock generator
process (MR_n, XIn)
variable Baud_Cnt : unsigned(15 downto 0);
begin
if MR_n = '0' then
Baud_Cnt := "0000000000000000";
BaudOut <= '0';
elsif XIn'event and XIn = '1' then
if Baud_Cnt(15 downto 1) = "000000000000000" or (Wr_n = '0' and CS_n = '0' and A(2 downto 1) = "00" and LCR(7) = '1') then
Baud_Cnt(15 downto 8) := unsigned(DLM);
Baud_Cnt(7 downto 0) := unsigned(DLL);
BaudOut <= '1';
else
Baud_Cnt := Baud_Cnt - 1;
BaudOut <= '0';
end if;
end if;
end process;
-- Input filter
process (MR_n, XIn)
variable Samples : std_logic_vector(1 downto 0);
begin
if MR_n = '0' then
Samples := "11";
RX_Filtered <= '1';
elsif XIn'event and XIn = '1' then
if RClk = '1' then
Samples(1) := Samples(0);
Samples(0) := RXD;
end if;
if Samples = "00" then
RX_Filtered <= '0';
end if;
if Samples = "11" then
RX_Filtered <= '1';
end if;
end if;
end process;
-- Receive state machine
process (MR_n, XIn)
begin
if MR_n = '0' then
RBR <= "00000000";
LSR(4 downto 0) <= "00000";
Bit_Phase <= "0000";
Brk_Cnt <= "0000";
RX_ShiftReg(7 downto 0) <= "00000000";
RX_Bit_Cnt <= 0;
RX_Parity <= '0';
elsif XIn'event and XIn = '1' then
if A = "000" and LCR(7) = '0' and Rd_n = '0' and CS_n = '0' then
LSR(0) <= '0'; -- DR
end if;
if A = "101" and Rd_n = '0' and CS_n = '0' then
LSR(4) <= '0'; -- BI
LSR(3) <= '0'; -- FE
LSR(2) <= '0'; -- PE
LSR(1) <= '0'; -- OE
end if;
if RClk = '1' then
if RX_Bit_Cnt = 0 and (RX_Filtered = '1' or Bit_Phase = "0111") then
Bit_Phase <= "0000";
else
Bit_Phase <= Bit_Phase + 1;
end if;
if Bit_Phase = "1111" then
if RX_Filtered = '1' then
Brk_Cnt <= "0000";
else
Brk_Cnt <= Brk_Cnt + 1;
end if;
if Brk_Cnt = "1100" then
LSR(4) <= '1'; -- BI
end if;
end if;
if RX_Bit_Cnt = 0 then
if Bit_Phase = "0111" then
RX_Bit_Cnt <= RX_Bit_Cnt + 1;
RX_Parity <= not LCR(4); -- EPS
end if;
elsif Bit_Phase = "1111" then
RX_Bit_Cnt <= RX_Bit_Cnt + 1;
if RX_Bit_Cnt = 10 then -- Parity stop bit
RX_Bit_Cnt <= 0;
LSR(0) <= '1'; -- UART Receive complete
LSR(3) <= not RX_Filtered; -- Framing error
elsif (RX_Bit_Cnt = 9 and LCR(1 downto 0) = "11") or
(RX_Bit_Cnt = 8 and LCR(1 downto 0) = "10") or
(RX_Bit_Cnt = 7 and LCR(1 downto 0) = "01") or
(RX_Bit_Cnt = 6 and LCR(1 downto 0) = "00") then -- Stop bit/Parity
RX_Bit_Cnt <= 0;
if LCR(3) = '1' then -- PEN
RX_Bit_Cnt <= 10;
if LCR(5) = '1' then -- Stick parity
if RX_Filtered = LCR(4) then
LSR(2) <= '1';
end if;
else
if RX_Filtered /= RX_Parity then
LSR(2) <= '1';
end if;
end if;
else
LSR(0) <= '1'; -- UART Receive complete
LSR(3) <= not RX_Filtered; -- Framing error
end if;
RBR <= RX_ShiftReg(7 downto 0);
LSR(1) <= LSR(0);
if A = "101" and Rd_n = '0' and CS_n = '0' then
LSR(1) <= '0';
end if;
else
RX_ShiftReg(6 downto 0) <= RX_ShiftReg(7 downto 1);
RX_ShiftReg(7) <= RX_Filtered;
if LCR(1 downto 0) = "10" then
RX_ShiftReg(7) <= '0';
RX_ShiftReg(6) <= RX_Filtered;
end if;
if LCR(1 downto 0) = "01" then
RX_ShiftReg(7) <= '0';
RX_ShiftReg(6) <= '0';
RX_ShiftReg(5) <= RX_Filtered;
end if;
if LCR(1 downto 0) = "00" then
RX_ShiftReg(7) <= '0';
RX_ShiftReg(6) <= '0';
RX_ShiftReg(5) <= '0';
RX_ShiftReg(4) <= RX_Filtered;
end if;
RX_Parity <= RX_Filtered xor RX_Parity;
end if;
end if;
end if;
end if;
end process;
-- Transmit bit tick
process (MR_n, XIn)
variable TX_Cnt : unsigned(4 downto 0);
begin
if MR_n = '0' then
TX_Cnt := "00000";
TX_Tick <= '0';
elsif XIn'event and XIn = '1' then
TX_Tick <= '0';
if RClk = '1' then
TX_Cnt := TX_Cnt + 1;
if LCR(2) = '1' and TX_Stop_Bit = '1' then
if LCR(1 downto 0) = "00" then
if TX_Cnt = "10111" then
TX_Tick <= '1';
TX_Cnt(3 downto 0) := "0000";
end if;
else
if TX_Cnt = "11111" then
TX_Tick <= '1';
TX_Cnt(3 downto 0) := "0000";
end if;
end if;
else
TX_Cnt(4) := '1';
if TX_Cnt(3 downto 0) = "1111" then
TX_Tick <= '1';
end if;
end if;
end if;
end if;
end process;
-- Transmit state machine
process (MR_n, XIn)
begin
if MR_n = '0' then
LSR(7 downto 5) <= "011";
TX_Bit_Cnt <= 0;
TX_ShiftReg <= (others => '0');
TXD <= '1';
TX_Parity <= '0';
TX_Next_Is_Stop <= '0';
TX_Stop_Bit <= '0';
elsif XIn'event and XIn = '1' then
if TX_Tick = '1' then
TX_Next_Is_Stop <= '0';
TX_Stop_Bit <= TX_Next_Is_Stop;
case TX_Bit_Cnt is
when 0 =>
if LSR(5) <= '0' then -- THRE
TX_Bit_Cnt <= 1;
end if;
TXD <= '1';
when 1 => -- Start bit
TX_ShiftReg(7 downto 0) <= THR;
LSR(5) <= '1'; -- THRE
TXD <= '0';
TX_Parity <= not LCR(4); -- EPS
TX_Bit_Cnt <= TX_Bit_Cnt + 1;
when 10 => -- Parity bit
TXD <= TX_Parity;
if LCR(5) = '1' then -- Stick parity
TXD <= not LCR(4);
end if;
TX_Bit_Cnt <= 0;
TX_Next_Is_Stop <= '1';
when others =>
TX_Bit_Cnt <= TX_Bit_Cnt + 1;
if (TX_Bit_Cnt = 9 and LCR(1 downto 0) = "11") or
(TX_Bit_Cnt = 8 and LCR(1 downto 0) = "10") or
(TX_Bit_Cnt = 7 and LCR(1 downto 0) = "01") or
(TX_Bit_Cnt = 6 and LCR(1 downto 0) = "00") then
TX_Bit_Cnt <= 0;
if LCR(3) = '1' then -- PEN
TX_Bit_Cnt <= 10;
else
TX_Next_Is_Stop <= '1';
end if;
LSR(6) <= '1'; -- TEMT
end if;
TXD <= TX_ShiftReg(0);
TX_ShiftReg(6 downto 0) <= TX_ShiftReg(7 downto 1);
TX_Parity <= TX_ShiftReg(0) xor TX_Parity;
end case;
end if;
if Wr_n = '0' and CS_n = '0' and A = "000" and LCR(7) = '0' then
LSR(5) <= '0'; -- THRE
LSR(6) <= '0'; -- TEMT
end if;
end if;
end process;
end;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.95e-06,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.95e-06,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => W_0,
W_0init => 9.05e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.95e-06,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net6,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.95e-06,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net6,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.75e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 6.85e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.75e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 6.85e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.75e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 6.85e-06,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.75e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 6.85e-06,
scope => private
)
port map(
D => net3,
G => net6,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
Lsrcinit => 7.3e-06,
W => Wsrc_2,
Wsrc_2init => 7.85e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
Lsrcinit => 7.3e-06,
W => Wsrc_2,
Wsrc_2init => 7.85e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 3.78e-05,
scope => Wprivate
)
port map(
D => net4,
G => vbias3,
S => net7
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.7e-06,
W => Wcm_1,
Wcm_1init => 1.54e-05,
scope => private
)
port map(
D => net7,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.7e-06,
W => Wcmout_1,
Wcmout_1init => 1.045e-05,
scope => private
)
port map(
D => net8,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 3.78e-05,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net8
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => (pfak)*(WBias),
WBiasinit => 2.15e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.15e-06,
W => (pfak)*(WBias),
WBiasinit => 2.15e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.15e-06,
W => WBias,
WBiasinit => 2.15e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => WBias,
WBiasinit => 2.15e-05
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => WBias,
WBiasinit => 2.15e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => WBias,
WBiasinit => 2.15e-05
)
port map(
D => net9,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net10,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net10,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net10,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: rcs.ei.tum.de:user:Syma_Ctrl_core:1.2
-- IP Revision: 18
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY Test_AXI_Master_simple_v1_0_hw_1_Syma_Ctrl_0 IS
PORT (
l_ss_init : OUT STD_LOGIC;
ppm_signal_in : IN STD_LOGIC;
sample_clk : IN STD_LOGIC;
ppm_irq_single : OUT STD_LOGIC;
ppm_irq_complete : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s01_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s01_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s01_axi_awvalid : IN STD_LOGIC;
s01_axi_awready : OUT STD_LOGIC;
s01_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s01_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s01_axi_wvalid : IN STD_LOGIC;
s01_axi_wready : OUT STD_LOGIC;
s01_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s01_axi_bvalid : OUT STD_LOGIC;
s01_axi_bready : IN STD_LOGIC;
s01_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s01_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s01_axi_arvalid : IN STD_LOGIC;
s01_axi_arready : OUT STD_LOGIC;
s01_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s01_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s01_axi_rvalid : OUT STD_LOGIC;
s01_axi_rready : IN STD_LOGIC;
s01_axi_aclk : IN STD_LOGIC;
s01_axi_aresetn : IN STD_LOGIC;
m01_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m01_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m01_axi_awvalid : OUT STD_LOGIC;
m01_axi_awready : IN STD_LOGIC;
m01_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m01_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m01_axi_wvalid : OUT STD_LOGIC;
m01_axi_wready : IN STD_LOGIC;
m01_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m01_axi_bvalid : IN STD_LOGIC;
m01_axi_bready : OUT STD_LOGIC;
m01_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m01_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m01_axi_arvalid : OUT STD_LOGIC;
m01_axi_arready : IN STD_LOGIC;
m01_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m01_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m01_axi_rvalid : IN STD_LOGIC;
m01_axi_rready : OUT STD_LOGIC;
m01_axi_aclk : IN STD_LOGIC;
m01_axi_aresetn : IN STD_LOGIC
);
END Test_AXI_Master_simple_v1_0_hw_1_Syma_Ctrl_0;
ARCHITECTURE Test_AXI_Master_simple_v1_0_hw_1_Syma_Ctrl_0_arch OF Test_AXI_Master_simple_v1_0_hw_1_Syma_Ctrl_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Test_AXI_Master_simple_v1_0_hw_1_Syma_Ctrl_0_arch: ARCHITECTURE IS "yes";
COMPONENT Syma_Ctrl_core_v1_1 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
C_S01_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S01_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
C_M01_AXI_START_DATA_VALUE : STD_LOGIC_VECTOR; -- The master will start generating data from the C_M_START_DATA_VALUE value
C_M01_AXI_TARGET_SLAVE_BASE_ADDR : STD_LOGIC_VECTOR; -- The master requires a target slave base address.
-- The master will initiate read and write transactions on the slave with base address specified here as a parameter.
C_M01_AXI_ADDR_WIDTH : INTEGER; -- Width of M_AXI address bus.
-- The master generates the read and write addresses of width specified as C_M_AXI_ADDR_WIDTH.
C_M01_AXI_DATA_WIDTH : INTEGER; -- Width of M_AXI data bus.
-- The master issues write data and accept read data where the width of the data bus is C_M_AXI_DATA_WIDTH
C_M01_AXI_TRANSACTIONS_NUM : INTEGER; -- Transaction number is the number of write
-- and read transactions the master will perform as a part of this example memory test.
DEBUG : INTEGER
);
PORT (
l_ss_init : OUT STD_LOGIC;
ppm_signal_in : IN STD_LOGIC;
sample_clk : IN STD_LOGIC;
ppm_irq_single : OUT STD_LOGIC;
ppm_irq_complete : OUT STD_LOGIC;
d_axi_done : OUT STD_LOGIC;
d_axi_start : OUT STD_LOGIC;
d_axi_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
d_axi_addr : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
d_slave_cr : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
d_slave_sr : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
d_slave_flight : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s01_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s01_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s01_axi_awvalid : IN STD_LOGIC;
s01_axi_awready : OUT STD_LOGIC;
s01_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s01_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s01_axi_wvalid : IN STD_LOGIC;
s01_axi_wready : OUT STD_LOGIC;
s01_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s01_axi_bvalid : OUT STD_LOGIC;
s01_axi_bready : IN STD_LOGIC;
s01_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s01_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s01_axi_arvalid : IN STD_LOGIC;
s01_axi_arready : OUT STD_LOGIC;
s01_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s01_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s01_axi_rvalid : OUT STD_LOGIC;
s01_axi_rready : IN STD_LOGIC;
s01_axi_aclk : IN STD_LOGIC;
s01_axi_aresetn : IN STD_LOGIC;
m01_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m01_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m01_axi_awvalid : OUT STD_LOGIC;
m01_axi_awready : IN STD_LOGIC;
m01_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m01_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m01_axi_wvalid : OUT STD_LOGIC;
m01_axi_wready : IN STD_LOGIC;
m01_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m01_axi_bvalid : IN STD_LOGIC;
m01_axi_bready : OUT STD_LOGIC;
m01_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m01_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m01_axi_arvalid : OUT STD_LOGIC;
m01_axi_arready : IN STD_LOGIC;
m01_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m01_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m01_axi_rvalid : IN STD_LOGIC;
m01_axi_rready : OUT STD_LOGIC;
m01_axi_aclk : IN STD_LOGIC;
m01_axi_aresetn : IN STD_LOGIC
);
END COMPONENT Syma_Ctrl_core_v1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Test_AXI_Master_simple_v1_0_hw_1_Syma_Ctrl_0_arch: ARCHITECTURE IS "Syma_Ctrl_core_v1_1,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Test_AXI_Master_simple_v1_0_hw_1_Syma_Ctrl_0_arch : ARCHITECTURE IS "Test_AXI_Master_simple_v1_0_hw_1_Syma_Ctrl_0,Syma_Ctrl_core_v1_1,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S01_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S01_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M01_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M01_AXI_RST RST";
BEGIN
U0 : Syma_Ctrl_core_v1_1
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4,
C_S01_AXI_DATA_WIDTH => 32,
C_S01_AXI_ADDR_WIDTH => 5,
C_M01_AXI_START_DATA_VALUE => X"AA000000",
C_M01_AXI_TARGET_SLAVE_BASE_ADDR => X"44A00000",
C_M01_AXI_ADDR_WIDTH => 32,
C_M01_AXI_DATA_WIDTH => 32,
C_M01_AXI_TRANSACTIONS_NUM => 1,
DEBUG => 0
)
PORT MAP (
l_ss_init => l_ss_init,
ppm_signal_in => ppm_signal_in,
sample_clk => sample_clk,
ppm_irq_single => ppm_irq_single,
ppm_irq_complete => ppm_irq_complete,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn,
s01_axi_awaddr => s01_axi_awaddr,
s01_axi_awprot => s01_axi_awprot,
s01_axi_awvalid => s01_axi_awvalid,
s01_axi_awready => s01_axi_awready,
s01_axi_wdata => s01_axi_wdata,
s01_axi_wstrb => s01_axi_wstrb,
s01_axi_wvalid => s01_axi_wvalid,
s01_axi_wready => s01_axi_wready,
s01_axi_bresp => s01_axi_bresp,
s01_axi_bvalid => s01_axi_bvalid,
s01_axi_bready => s01_axi_bready,
s01_axi_araddr => s01_axi_araddr,
s01_axi_arprot => s01_axi_arprot,
s01_axi_arvalid => s01_axi_arvalid,
s01_axi_arready => s01_axi_arready,
s01_axi_rdata => s01_axi_rdata,
s01_axi_rresp => s01_axi_rresp,
s01_axi_rvalid => s01_axi_rvalid,
s01_axi_rready => s01_axi_rready,
s01_axi_aclk => s01_axi_aclk,
s01_axi_aresetn => s01_axi_aresetn,
m01_axi_awaddr => m01_axi_awaddr,
m01_axi_awprot => m01_axi_awprot,
m01_axi_awvalid => m01_axi_awvalid,
m01_axi_awready => m01_axi_awready,
m01_axi_wdata => m01_axi_wdata,
m01_axi_wstrb => m01_axi_wstrb,
m01_axi_wvalid => m01_axi_wvalid,
m01_axi_wready => m01_axi_wready,
m01_axi_bresp => m01_axi_bresp,
m01_axi_bvalid => m01_axi_bvalid,
m01_axi_bready => m01_axi_bready,
m01_axi_araddr => m01_axi_araddr,
m01_axi_arprot => m01_axi_arprot,
m01_axi_arvalid => m01_axi_arvalid,
m01_axi_arready => m01_axi_arready,
m01_axi_rdata => m01_axi_rdata,
m01_axi_rresp => m01_axi_rresp,
m01_axi_rvalid => m01_axi_rvalid,
m01_axi_rready => m01_axi_rready,
m01_axi_aclk => m01_axi_aclk,
m01_axi_aresetn => m01_axi_aresetn
);
END Test_AXI_Master_simple_v1_0_hw_1_Syma_Ctrl_0_arch;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
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-- DISCLAIMER
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-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: rcs.ei.tum.de:user:Syma_Ctrl_core:1.2
-- IP Revision: 18
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY Test_AXI_Master_simple_v1_0_hw_1_Syma_Ctrl_0 IS
PORT (
l_ss_init : OUT STD_LOGIC;
ppm_signal_in : IN STD_LOGIC;
sample_clk : IN STD_LOGIC;
ppm_irq_single : OUT STD_LOGIC;
ppm_irq_complete : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s01_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s01_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s01_axi_awvalid : IN STD_LOGIC;
s01_axi_awready : OUT STD_LOGIC;
s01_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s01_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s01_axi_wvalid : IN STD_LOGIC;
s01_axi_wready : OUT STD_LOGIC;
s01_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s01_axi_bvalid : OUT STD_LOGIC;
s01_axi_bready : IN STD_LOGIC;
s01_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s01_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s01_axi_arvalid : IN STD_LOGIC;
s01_axi_arready : OUT STD_LOGIC;
s01_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s01_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s01_axi_rvalid : OUT STD_LOGIC;
s01_axi_rready : IN STD_LOGIC;
s01_axi_aclk : IN STD_LOGIC;
s01_axi_aresetn : IN STD_LOGIC;
m01_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m01_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m01_axi_awvalid : OUT STD_LOGIC;
m01_axi_awready : IN STD_LOGIC;
m01_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m01_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m01_axi_wvalid : OUT STD_LOGIC;
m01_axi_wready : IN STD_LOGIC;
m01_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m01_axi_bvalid : IN STD_LOGIC;
m01_axi_bready : OUT STD_LOGIC;
m01_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m01_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m01_axi_arvalid : OUT STD_LOGIC;
m01_axi_arready : IN STD_LOGIC;
m01_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m01_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m01_axi_rvalid : IN STD_LOGIC;
m01_axi_rready : OUT STD_LOGIC;
m01_axi_aclk : IN STD_LOGIC;
m01_axi_aresetn : IN STD_LOGIC
);
END Test_AXI_Master_simple_v1_0_hw_1_Syma_Ctrl_0;
ARCHITECTURE Test_AXI_Master_simple_v1_0_hw_1_Syma_Ctrl_0_arch OF Test_AXI_Master_simple_v1_0_hw_1_Syma_Ctrl_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Test_AXI_Master_simple_v1_0_hw_1_Syma_Ctrl_0_arch: ARCHITECTURE IS "yes";
COMPONENT Syma_Ctrl_core_v1_1 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
C_S01_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S01_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
C_M01_AXI_START_DATA_VALUE : STD_LOGIC_VECTOR; -- The master will start generating data from the C_M_START_DATA_VALUE value
C_M01_AXI_TARGET_SLAVE_BASE_ADDR : STD_LOGIC_VECTOR; -- The master requires a target slave base address.
-- The master will initiate read and write transactions on the slave with base address specified here as a parameter.
C_M01_AXI_ADDR_WIDTH : INTEGER; -- Width of M_AXI address bus.
-- The master generates the read and write addresses of width specified as C_M_AXI_ADDR_WIDTH.
C_M01_AXI_DATA_WIDTH : INTEGER; -- Width of M_AXI data bus.
-- The master issues write data and accept read data where the width of the data bus is C_M_AXI_DATA_WIDTH
C_M01_AXI_TRANSACTIONS_NUM : INTEGER; -- Transaction number is the number of write
-- and read transactions the master will perform as a part of this example memory test.
DEBUG : INTEGER
);
PORT (
l_ss_init : OUT STD_LOGIC;
ppm_signal_in : IN STD_LOGIC;
sample_clk : IN STD_LOGIC;
ppm_irq_single : OUT STD_LOGIC;
ppm_irq_complete : OUT STD_LOGIC;
d_axi_done : OUT STD_LOGIC;
d_axi_start : OUT STD_LOGIC;
d_axi_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
d_axi_addr : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
d_slave_cr : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
d_slave_sr : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
d_slave_flight : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s01_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s01_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s01_axi_awvalid : IN STD_LOGIC;
s01_axi_awready : OUT STD_LOGIC;
s01_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s01_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s01_axi_wvalid : IN STD_LOGIC;
s01_axi_wready : OUT STD_LOGIC;
s01_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s01_axi_bvalid : OUT STD_LOGIC;
s01_axi_bready : IN STD_LOGIC;
s01_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s01_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s01_axi_arvalid : IN STD_LOGIC;
s01_axi_arready : OUT STD_LOGIC;
s01_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s01_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s01_axi_rvalid : OUT STD_LOGIC;
s01_axi_rready : IN STD_LOGIC;
s01_axi_aclk : IN STD_LOGIC;
s01_axi_aresetn : IN STD_LOGIC;
m01_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m01_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m01_axi_awvalid : OUT STD_LOGIC;
m01_axi_awready : IN STD_LOGIC;
m01_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m01_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m01_axi_wvalid : OUT STD_LOGIC;
m01_axi_wready : IN STD_LOGIC;
m01_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m01_axi_bvalid : IN STD_LOGIC;
m01_axi_bready : OUT STD_LOGIC;
m01_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m01_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m01_axi_arvalid : OUT STD_LOGIC;
m01_axi_arready : IN STD_LOGIC;
m01_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m01_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m01_axi_rvalid : IN STD_LOGIC;
m01_axi_rready : OUT STD_LOGIC;
m01_axi_aclk : IN STD_LOGIC;
m01_axi_aresetn : IN STD_LOGIC
);
END COMPONENT Syma_Ctrl_core_v1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Test_AXI_Master_simple_v1_0_hw_1_Syma_Ctrl_0_arch: ARCHITECTURE IS "Syma_Ctrl_core_v1_1,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Test_AXI_Master_simple_v1_0_hw_1_Syma_Ctrl_0_arch : ARCHITECTURE IS "Test_AXI_Master_simple_v1_0_hw_1_Syma_Ctrl_0,Syma_Ctrl_core_v1_1,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S01_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S01_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s01_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S01_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M01_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M01_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m01_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M01_AXI_RST RST";
BEGIN
U0 : Syma_Ctrl_core_v1_1
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4,
C_S01_AXI_DATA_WIDTH => 32,
C_S01_AXI_ADDR_WIDTH => 5,
C_M01_AXI_START_DATA_VALUE => X"AA000000",
C_M01_AXI_TARGET_SLAVE_BASE_ADDR => X"44A00000",
C_M01_AXI_ADDR_WIDTH => 32,
C_M01_AXI_DATA_WIDTH => 32,
C_M01_AXI_TRANSACTIONS_NUM => 1,
DEBUG => 0
)
PORT MAP (
l_ss_init => l_ss_init,
ppm_signal_in => ppm_signal_in,
sample_clk => sample_clk,
ppm_irq_single => ppm_irq_single,
ppm_irq_complete => ppm_irq_complete,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn,
s01_axi_awaddr => s01_axi_awaddr,
s01_axi_awprot => s01_axi_awprot,
s01_axi_awvalid => s01_axi_awvalid,
s01_axi_awready => s01_axi_awready,
s01_axi_wdata => s01_axi_wdata,
s01_axi_wstrb => s01_axi_wstrb,
s01_axi_wvalid => s01_axi_wvalid,
s01_axi_wready => s01_axi_wready,
s01_axi_bresp => s01_axi_bresp,
s01_axi_bvalid => s01_axi_bvalid,
s01_axi_bready => s01_axi_bready,
s01_axi_araddr => s01_axi_araddr,
s01_axi_arprot => s01_axi_arprot,
s01_axi_arvalid => s01_axi_arvalid,
s01_axi_arready => s01_axi_arready,
s01_axi_rdata => s01_axi_rdata,
s01_axi_rresp => s01_axi_rresp,
s01_axi_rvalid => s01_axi_rvalid,
s01_axi_rready => s01_axi_rready,
s01_axi_aclk => s01_axi_aclk,
s01_axi_aresetn => s01_axi_aresetn,
m01_axi_awaddr => m01_axi_awaddr,
m01_axi_awprot => m01_axi_awprot,
m01_axi_awvalid => m01_axi_awvalid,
m01_axi_awready => m01_axi_awready,
m01_axi_wdata => m01_axi_wdata,
m01_axi_wstrb => m01_axi_wstrb,
m01_axi_wvalid => m01_axi_wvalid,
m01_axi_wready => m01_axi_wready,
m01_axi_bresp => m01_axi_bresp,
m01_axi_bvalid => m01_axi_bvalid,
m01_axi_bready => m01_axi_bready,
m01_axi_araddr => m01_axi_araddr,
m01_axi_arprot => m01_axi_arprot,
m01_axi_arvalid => m01_axi_arvalid,
m01_axi_arready => m01_axi_arready,
m01_axi_rdata => m01_axi_rdata,
m01_axi_rresp => m01_axi_rresp,
m01_axi_rvalid => m01_axi_rvalid,
m01_axi_rready => m01_axi_rready,
m01_axi_aclk => m01_axi_aclk,
m01_axi_aresetn => m01_axi_aresetn
);
END Test_AXI_Master_simple_v1_0_hw_1_Syma_Ctrl_0_arch;
|
----------------------------------------------------------------------------------------------
-- This file is part of mblite_ip.
--
-- mblite_ip is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- mblite_ip is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with mblite_ip. If not, see <http://www.gnu.org/licenses/>.
--
-- Input file : std_Pkg.vhd
-- Design name : std_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Package with several standard components.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
PACKAGE std_pkg IS
----------------------------------------------------------------------------------------------
-- STANDARD COMPONENTS IN STD_PKG
----------------------------------------------------------------------------------------------
component sram generic
(
WIDTH : positive;
SIZE : positive
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic
);
end component;
component sram_4en generic
(
WIDTH : positive;
SIZE : positive
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic_vector(3 downto 0);
ena_i : in std_logic;
clk_i : in std_logic
);
end component;
component dsram generic
(
WIDTH : positive;
SIZE : positive
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
ena_i : in std_logic;
dat_w_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_w_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic;
clk_i : in std_logic
);
end component;
----------------------------------------------------------------------------------------------
-- FUNCTIONS IN STD_PKG
----------------------------------------------------------------------------------------------
function v_or(d : std_logic_vector) return std_logic;
function is_zero(d : std_logic_vector) return std_logic;
function is_not_zero(d : std_logic_vector) return std_logic;
function my_conv_integer(a: std_logic_vector) return integer;
function notx(d : std_logic_vector) return boolean;
function compare(a, b : std_logic_vector) return std_logic;
function multiply(a, b : std_logic_vector) return std_logic_vector;
function sign_extend(value: std_logic_vector; fill: std_logic; size: positive) return std_logic_vector;
function add(a, b : std_logic_vector; ci: std_logic) return std_logic_vector;
function increment(a : std_logic_vector) return std_logic_vector;
function shift(value : std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0); s: std_logic; t: std_logic) return std_logic_vector;
function shift_left(value : std_logic_vector(31 downto 0); shamt : std_logic_vector(4 downto 0)) return std_logic_vector;
function shift_right(value : std_logic_vector(31 downto 0); shamt : std_logic_vector(4 downto 0); padding: std_logic) return std_logic_vector;
end std_Pkg;
PACKAGE BODY std_Pkg IS
-- Unary OR reduction
function v_or(d : std_logic_vector) return std_logic is
variable z : std_logic;
begin
z := '0';
if notx (d) then
for i in d'range loop
z := z or d(i);
end loop;
end if;
return z;
end;
-- Check for ones in the vector
function is_not_zero(d : std_logic_vector) return std_logic is
variable z : std_logic_vector(d'range);
begin
z := (others => '0');
if notx(d) then
if d = z then
return '0';
else
return '1';
end if;
else
return '0';
end if;
end;
-- Check for ones in the vector
function is_zero(d : std_logic_vector) return std_logic is
begin
return not is_not_zero(d);
end;
-- rewrite conv_integer to avoid modelsim warnings
function my_conv_integer(a : std_logic_vector) return integer is
variable res : integer range 0 to 2**a'length-1;
begin
res := 0;
if (notx(a)) then
res := to_integer(unsigned(a));
end if;
return res;
end;
function compare(a, b : std_logic_vector) return std_logic is
variable z : std_logic;
begin
if notx(a & b) and a = b then
return '1';
else
return '0';
end if;
end;
-- Unary NOT X test
function notx(d : std_logic_vector) return boolean is
variable res : boolean;
begin
res := true;
-- pragma translate_off
res := not is_x(d);
-- pragma translate_on
return (res);
end;
-- -- 32 bit shifter
-- -- SYNOPSIS:
-- -- value: value to be shifted
-- -- shamt: shift amount
-- -- s 0 / 1: shift right / left
-- -- t 0 / 1: shift logical / arithmetic
-- -- PSEUDOCODE (from microblaze reference guide)
-- -- if S = 1 then
-- -- (rD) = (rA) << (rB)[27:31]
-- -- else
-- -- if T = 1 then
-- -- if ((rB)[27:31]) != 0 then
-- -- (rD)[0:(rB)[27:31]-1] = (rA)[0]
-- -- (rD)[(rB)[27:31]:31] = (rA) >> (rB)[27:31]
-- -- else
-- -- (rD) = (rA)
-- -- else
-- -- (rD) = (rA) >> (rB)[27:31]
function shift(value: std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0); s: std_logic; t: std_logic) return std_logic_vector is
begin
if s = '1' then
-- left arithmetic or logical shift
return shift_left(value, shamt);
else
if t = '1' then
-- right arithmetic shift
return shift_right(value, shamt, value(31));
else
-- right logical shift
return shift_right(value, shamt, '0');
end if;
end if;
end;
function shift_left(value: std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0)) return std_logic_vector is
variable result: std_logic_vector(31 downto 0);
variable paddings: std_logic_vector(15 downto 0);
begin
paddings := (others => '0');
result := value;
if (shamt(4) = '1') then result := result(15 downto 0) & paddings(15 downto 0); end if;
if (shamt(3) = '1') then result := result(23 downto 0) & paddings( 7 downto 0); end if;
if (shamt(2) = '1') then result := result(27 downto 0) & paddings( 3 downto 0); end if;
if (shamt(1) = '1') then result := result(29 downto 0) & paddings( 1 downto 0); end if;
if (shamt(0) = '1') then result := result(30 downto 0) & paddings( 0 ); end if;
return result;
end;
function shift_right(value: std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0); padding: std_logic) return std_logic_vector is
variable result: std_logic_vector(31 downto 0);
variable paddings: std_logic_vector(15 downto 0);
begin
paddings := (others => padding);
result := value;
if (shamt(4) = '1') then result := paddings(15 downto 0) & result(31 downto 16); end if;
if (shamt(3) = '1') then result := paddings( 7 downto 0) & result(31 downto 8); end if;
if (shamt(2) = '1') then result := paddings( 3 downto 0) & result(31 downto 4); end if;
if (shamt(1) = '1') then result := paddings( 1 downto 0) & result(31 downto 2); end if;
if (shamt(0) = '1') then result := paddings( 0 ) & result(31 downto 1); end if;
return result;
end;
function multiply(a, b: std_logic_vector) return std_logic_vector is
variable x: std_logic_vector (a'length + b'length - 1 downto 0);
begin
x := std_logic_vector(signed(a) * signed(b));
return x(31 downto 0);
end;
function sign_extend(value: std_logic_vector; fill: std_logic; size: positive) return std_logic_vector is
variable a: std_logic_vector (size - 1 downto 0);
begin
a(size - 1 downto value'length) := (others => fill);
a(value'length - 1 downto 0) := value;
return a;
end;
function add(a, b : std_logic_vector; ci: std_logic) return std_logic_vector is
variable x : std_logic_vector(a'length + 1 downto 0);
begin
x := (others => '0');
if notx (a & b & ci) then
x := std_logic_vector(signed('0' & a & '1') + signed('0' & b & ci));
end if;
return x(a'length + 1 downto 1);
end;
function increment(a : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(a'length-1 downto 0);
begin
x := (others => '0');
if notx (a) then
x := std_logic_vector(signed(a) + 1);
end if;
return x;
end;
end std_pkg; |
-------------------------------------------------------------------------------
-- Title : iMotor UART send
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Simple UART that sends parallel data serially.
--
-- This implementation does not have an baud rate generator. As the intention
-- of this entity is to be used in parallel a global baud rate generator is
-- used. When new data is to be send the entity needs to wait for the first
-- clock enable of the baud rate generator. Otherwise the length of the start
-- bit would be different.
--
-- The parity bit is always present. If parity is set to None it is set '1'
-- which is interpreted as the stop bit. In this case there is one more
-- stop bit then requested.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.imotor_module_pkg.all;
-------------------------------------------------------------------------------
entity imotor_uart_tx is
generic (
START_BITS : positive := 1;
DATA_BITS : positive := 8;
STOP_BITS : positive := 1;
PARITY : parity_type := None
);
port (
data_in_p : in std_logic_vector(DATA_BITS - 1 downto 0); -- parallel
-- data in
start_in_p : in std_logic; -- start a transmission of data_in_p
busy_out_p : out std_logic; -- high when busy
txd_out_p : out std_logic; -- output to transceiver
clock_tx_in_p : in std_logic; -- Bit clock for transmitter
clk : in std_logic
);
end imotor_uart_tx;
-------------------------------------------------------------------------------
architecture behavioural of imotor_uart_tx is
type imotor_uart_tx_state_type is (
IDLE, -- Idle state:
STATE1, -- State 1: Request to send received, wait for first bit time.
STATE2 -- State 2: Sending of bis in progress
);
type imotor_uart_tx_type is record
-- shift register
-- Omitting -1 because of the parity bit
sr : std_logic_vector (START_BITS + DATA_BITS + STOP_BITS downto 0);
-- Number of bits
-- One more for parity bit
bitcnt : integer range 0 to START_BITS + DATA_BITS + 1 + STOP_BITS;
state : imotor_uart_tx_state_type;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : imotor_uart_tx_type := (state => IDLE,
sr => (others => '1'),
bitcnt => START_BITS + DATA_BITS + 1 + STOP_BITS);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
busy_out_p <= '1' when (start_in_p = '1' or r.state /= IDLE) else '0';
txd_out_p <= r.sr(0) when (r.state = STATE2) else '1';
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(clock_tx_in_p, data_in_p, r, start_in_p)
variable v : imotor_uart_tx_type;
variable parity_bit : std_logic := '1'; -- Computed parity, default '1'
-- for parity = None
begin
-- Parity bit:
parity_bit := '1';
for i in data_in_p'range loop
parity_bit := parity_bit xor data_in_p(i);
end loop;
v := r;
case r.state is
when IDLE =>
if start_in_p = '1' then
-- Set the shift register:
-- STOP_BITS PARITY_BIT DATA_BITS START_BITS
-- Upper bits: STOP_BITS set to '1':
v.sr(START_BITS + DATA_BITS + STOP_BITS downto START_BITS + DATA_BITS + 1) := (others => '1');
-- Set parity bit in shift register
case PARITY is
when None => v.sr(START_BITS + DATA_BITS) := '1';
when Even => v.sr(START_BITS + DATA_BITS) := parity_bit;
when Odd => v.sr(START_BITS + DATA_BITS) := not parity_bit;
end case;
-- Lower bits: START_BITS set to '0':
v.sr(START_BITS - 1 downto 0) := (others => '0');
-- Middle bits: DATA_BITS
v.sr(START_BITS + DATA_BITS - 1 downto START_BITS) := data_in_p;
v.bitcnt := 0;
v.state := STATE1;
end if;
when STATE1 =>
-- Bit clock enable arrived, send start bit now.
if clock_tx_in_p = '1' then
v.state := STATE2;
end if;
when STATE2 =>
if clock_tx_in_p = '1' then
if v.bitcnt < (START_BITS + DATA_BITS + STOP_BITS) then
-- Next bit
v.bitcnt := r.bitcnt + 1;
v.sr := '1' & r.sr(v.sr'left downto 1);
else
v.state := IDLE;
end if;
end if;
when others =>
v.state := IDLE;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
|
-------------------------------------------------------------------------------
-- Title : iMotor UART send
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Simple UART that sends parallel data serially.
--
-- This implementation does not have an baud rate generator. As the intention
-- of this entity is to be used in parallel a global baud rate generator is
-- used. When new data is to be send the entity needs to wait for the first
-- clock enable of the baud rate generator. Otherwise the length of the start
-- bit would be different.
--
-- The parity bit is always present. If parity is set to None it is set '1'
-- which is interpreted as the stop bit. In this case there is one more
-- stop bit then requested.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.imotor_module_pkg.all;
-------------------------------------------------------------------------------
entity imotor_uart_tx is
generic (
START_BITS : positive := 1;
DATA_BITS : positive := 8;
STOP_BITS : positive := 1;
PARITY : parity_type := None
);
port (
data_in_p : in std_logic_vector(DATA_BITS - 1 downto 0); -- parallel
-- data in
start_in_p : in std_logic; -- start a transmission of data_in_p
busy_out_p : out std_logic; -- high when busy
txd_out_p : out std_logic; -- output to transceiver
clock_tx_in_p : in std_logic; -- Bit clock for transmitter
clk : in std_logic
);
end imotor_uart_tx;
-------------------------------------------------------------------------------
architecture behavioural of imotor_uart_tx is
type imotor_uart_tx_state_type is (
IDLE, -- Idle state:
STATE1, -- State 1: Request to send received, wait for first bit time.
STATE2 -- State 2: Sending of bis in progress
);
type imotor_uart_tx_type is record
-- shift register
-- Omitting -1 because of the parity bit
sr : std_logic_vector (START_BITS + DATA_BITS + STOP_BITS downto 0);
-- Number of bits
-- One more for parity bit
bitcnt : integer range 0 to START_BITS + DATA_BITS + 1 + STOP_BITS;
state : imotor_uart_tx_state_type;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : imotor_uart_tx_type := (state => IDLE,
sr => (others => '1'),
bitcnt => START_BITS + DATA_BITS + 1 + STOP_BITS);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
busy_out_p <= '1' when (start_in_p = '1' or r.state /= IDLE) else '0';
txd_out_p <= r.sr(0) when (r.state = STATE2) else '1';
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(clock_tx_in_p, data_in_p, r, start_in_p)
variable v : imotor_uart_tx_type;
variable parity_bit : std_logic := '1'; -- Computed parity, default '1'
-- for parity = None
begin
-- Parity bit:
parity_bit := '1';
for i in data_in_p'range loop
parity_bit := parity_bit xor data_in_p(i);
end loop;
v := r;
case r.state is
when IDLE =>
if start_in_p = '1' then
-- Set the shift register:
-- STOP_BITS PARITY_BIT DATA_BITS START_BITS
-- Upper bits: STOP_BITS set to '1':
v.sr(START_BITS + DATA_BITS + STOP_BITS downto START_BITS + DATA_BITS + 1) := (others => '1');
-- Set parity bit in shift register
case PARITY is
when None => v.sr(START_BITS + DATA_BITS) := '1';
when Even => v.sr(START_BITS + DATA_BITS) := parity_bit;
when Odd => v.sr(START_BITS + DATA_BITS) := not parity_bit;
end case;
-- Lower bits: START_BITS set to '0':
v.sr(START_BITS - 1 downto 0) := (others => '0');
-- Middle bits: DATA_BITS
v.sr(START_BITS + DATA_BITS - 1 downto START_BITS) := data_in_p;
v.bitcnt := 0;
v.state := STATE1;
end if;
when STATE1 =>
-- Bit clock enable arrived, send start bit now.
if clock_tx_in_p = '1' then
v.state := STATE2;
end if;
when STATE2 =>
if clock_tx_in_p = '1' then
if v.bitcnt < (START_BITS + DATA_BITS + STOP_BITS) then
-- Next bit
v.bitcnt := r.bitcnt + 1;
v.sr := '1' & r.sr(v.sr'left downto 1);
else
v.state := IDLE;
end if;
end if;
when others =>
v.state := IDLE;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
|
--======================================================================
-- outport.vhd :: Digital Output Port
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity OUTPORT is
port(
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
WR_DATA : in std_logic_vector(7 downto 0); -- data in
RD_DATA : out std_logic_vector(7 downto 0); -- data out
RESET : in std_logic; -- system reset
FCLK : in std_logic -- fast clock
);
end entity OUTPORT;
architecture BEHAVIORAL of OUTPORT is
--=================================================================
-- Signal definitions
--=================================================================
signal OREG : std_logic_vector( 7 downto 0); -- output reg
begin
--=============================================
-- Output Register
--=============================================
OUTPUT_REG:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if (CS = '1' and WE = '1') then
OREG <= WR_DATA;
end if;
if (RESET = '1') then
OREG <= (others => '0');
end if;
end if;
end process;
RD_DATA <= OREG;
end architecture BEHAVIORAL;
|
--======================================================================
-- outport.vhd :: Digital Output Port
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity OUTPORT is
port(
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
WR_DATA : in std_logic_vector(7 downto 0); -- data in
RD_DATA : out std_logic_vector(7 downto 0); -- data out
RESET : in std_logic; -- system reset
FCLK : in std_logic -- fast clock
);
end entity OUTPORT;
architecture BEHAVIORAL of OUTPORT is
--=================================================================
-- Signal definitions
--=================================================================
signal OREG : std_logic_vector( 7 downto 0); -- output reg
begin
--=============================================
-- Output Register
--=============================================
OUTPUT_REG:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if (CS = '1' and WE = '1') then
OREG <= WR_DATA;
end if;
if (RESET = '1') then
OREG <= (others => '0');
end if;
end if;
end process;
RD_DATA <= OREG;
end architecture BEHAVIORAL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1307.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p06n01i01307ent IS
END c08s04b00x00p06n01i01307ent;
ARCHITECTURE c08s04b00x00p06n01i01307arch OF c08s04b00x00p06n01i01307ent IS
type UA is array (NATURAL range <>) of BIT;
subtype ARAY_1 is UA (0 to 500);
signal S2 : ARAY_1;
signal S1 : BIT := '1';
BEGIN
TESTING: PROCESS
BEGIN
S2(200) <= S1;
wait for 1 ns;
assert NOT(S2(200) = '1')
report "***PASSED TEST: c08s04b00x00p06n01i01307"
severity NOTE;
assert (S2(200) = '1')
report "***FAILED TEST: c08s04b00x00p06n01i01307 - A indexed name can be used on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p06n01i01307arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1307.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p06n01i01307ent IS
END c08s04b00x00p06n01i01307ent;
ARCHITECTURE c08s04b00x00p06n01i01307arch OF c08s04b00x00p06n01i01307ent IS
type UA is array (NATURAL range <>) of BIT;
subtype ARAY_1 is UA (0 to 500);
signal S2 : ARAY_1;
signal S1 : BIT := '1';
BEGIN
TESTING: PROCESS
BEGIN
S2(200) <= S1;
wait for 1 ns;
assert NOT(S2(200) = '1')
report "***PASSED TEST: c08s04b00x00p06n01i01307"
severity NOTE;
assert (S2(200) = '1')
report "***FAILED TEST: c08s04b00x00p06n01i01307 - A indexed name can be used on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p06n01i01307arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1307.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p06n01i01307ent IS
END c08s04b00x00p06n01i01307ent;
ARCHITECTURE c08s04b00x00p06n01i01307arch OF c08s04b00x00p06n01i01307ent IS
type UA is array (NATURAL range <>) of BIT;
subtype ARAY_1 is UA (0 to 500);
signal S2 : ARAY_1;
signal S1 : BIT := '1';
BEGIN
TESTING: PROCESS
BEGIN
S2(200) <= S1;
wait for 1 ns;
assert NOT(S2(200) = '1')
report "***PASSED TEST: c08s04b00x00p06n01i01307"
severity NOTE;
assert (S2(200) = '1')
report "***FAILED TEST: c08s04b00x00p06n01i01307 - A indexed name can be used on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p06n01i01307arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2273.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02273ent IS
END c07s02b06x00p14n01i02273ent;
ARCHITECTURE c07s02b06x00p14n01i02273arch OF c07s02b06x00p14n01i02273ent IS
BEGIN
TESTING: PROCESS
variable T : TIME := 1 sec;
BEGIN
T := T * 10 sec; -- Failure_here
-- SEMANTIC ERROR: if one operand is physical, then the other must
-- an integer or floating point type.
assert FALSE
report "***FAILED TEST: c07s02b06x00p14n01i02273 - If one operand is of type physical, the other has to be of type integer or real."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02273arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2273.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02273ent IS
END c07s02b06x00p14n01i02273ent;
ARCHITECTURE c07s02b06x00p14n01i02273arch OF c07s02b06x00p14n01i02273ent IS
BEGIN
TESTING: PROCESS
variable T : TIME := 1 sec;
BEGIN
T := T * 10 sec; -- Failure_here
-- SEMANTIC ERROR: if one operand is physical, then the other must
-- an integer or floating point type.
assert FALSE
report "***FAILED TEST: c07s02b06x00p14n01i02273 - If one operand is of type physical, the other has to be of type integer or real."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02273arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2273.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02273ent IS
END c07s02b06x00p14n01i02273ent;
ARCHITECTURE c07s02b06x00p14n01i02273arch OF c07s02b06x00p14n01i02273ent IS
BEGIN
TESTING: PROCESS
variable T : TIME := 1 sec;
BEGIN
T := T * 10 sec; -- Failure_here
-- SEMANTIC ERROR: if one operand is physical, then the other must
-- an integer or floating point type.
assert FALSE
report "***FAILED TEST: c07s02b06x00p14n01i02273 - If one operand is of type physical, the other has to be of type integer or real."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02273arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
use work.sincos.all;
entity sampler is
port (data : in signed14;
decay : in unsigned(15 downto 0);
rate : in unsigned8;
q : out signed15;
strobe : out std_logic;
clk : in std_logic);
end sampler;
architecture sampler of sampler is
signal low1, fb1, low2, decay2 : signed18;
signal prod3, acc : signed36;
signal data1, data2, data3, data4 : signed14;
signal decay_off : boolean;
signal divide : unsigned9;
begin
decay_off <= (decay = x"0000");
process
variable q_acc_addend : signed15;
begin
wait until rising_edge(clk);
if not decay_off then
low1 <= data(13) & data(13) & data & "00";
fb1 <= acc(33 downto 16);
low2 <= low1 - fb1;
decay2 <= '0' & signed(decay) & '0';
prod3 <= low2 * decay2;
acc <= acc + prod3;
end if;
data1 <= data;
data2 <= data1;
data3 <= data2;
data4 <= data3;
strobe <= divide(8);
if divide(8) = '1' then
divide <= ('0' & rate) - 1;
if decay_off then
q_acc_addend := (others => '0');
else
q_acc_addend := acc(32 downto 18);
end if;
q <= data4 + q_acc_addend;
else
divide <= divide - 1;
end if;
end process;
end sampler;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Single Port RAM
-- 4096 x 8-bits
-- One RAMB36E1 primitive
--
-- Ken Chapman
-- Xilinx UK
-- 24th July 2014
--
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity ram_4096x8 is
Port ( address : in std_logic_vector(11 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
we : in std_logic;
clk : in std_logic);
end ram_4096x8;
--
architecture low_level_definition of ram_4096x8 is
--
signal address_a : std_logic_vector(15 downto 0);
signal data_in_a : std_logic_vector(35 downto 0);
signal we_a : std_logic_vector(3 downto 0);
signal data_out_a : std_logic_vector(35 downto 0);
signal address_b : std_logic_vector(15 downto 0);
signal data_in_b : std_logic_vector(35 downto 0);
signal data_out_b : std_logic_vector(35 downto 0);
--
begin
--
address_a <= '1' & address(11 downto 0) & "111";
data_in_a <= "000" & data_out_a(32) & "000000000000000000000000" & data_in;
we_a <= we & we & we & we;
data_out <= data_out_a(7 downto 0);
--
address_b <= "1111111111111111";
data_in_b <= "000" & data_out_b(32) & "000000000000000000000000" & data_out_b(7 downto 0);
--
ram_4096x8: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a,
ENARDEN => '1',
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => we_a,
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => '0',
CLKBWRCLK => '0',
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => "00000000",
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE ram_4096x8.vhd
--
------------------------------------------------------------------------------------
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY Interface_Master_BD_rst_processing_system7_0_71M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END Interface_Master_BD_rst_processing_system7_0_71M_0;
ARCHITECTURE Interface_Master_BD_rst_processing_system7_0_71M_0_arch OF Interface_Master_BD_rst_processing_system7_0_71M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Interface_Master_BD_rst_processing_system7_0_71M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Interface_Master_BD_rst_processing_system7_0_71M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Interface_Master_BD_rst_processing_system7_0_71M_0_arch : ARCHITECTURE IS "Interface_Master_BD_rst_processing_system7_0_71M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF Interface_Master_BD_rst_processing_system7_0_71M_0_arch: ARCHITECTURE IS "Interface_Master_BD_rst_processing_system7_0_71M_0,proc_sys_reset,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END Interface_Master_BD_rst_processing_system7_0_71M_0_arch;
|
-- logic_unit.vhd --
-- TODO: replace this with a better structural LOGIC UNIT.
library ieee;
use ieee.std_logic_1164.all;
--use work.myTypes.all;
entity logic_unit is
generic (
SIZE : integer := 32
);
port (
IN1 : in std_logic_vector(SIZE - 1 downto 0);
IN2 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0); -- need to do only and, or and xor
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end logic_unit;
architecture Bhe of logic_unit is
begin
OUT1 <= IN1 and IN2 when CTRL = "00" else
IN1 or IN2 when CTRL = "01" else
IN1 xor IN2 when CTRL = "10" else
(others => '0'); -- should never appear
end Bhe;
|
-- logic_unit.vhd --
-- TODO: replace this with a better structural LOGIC UNIT.
library ieee;
use ieee.std_logic_1164.all;
--use work.myTypes.all;
entity logic_unit is
generic (
SIZE : integer := 32
);
port (
IN1 : in std_logic_vector(SIZE - 1 downto 0);
IN2 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0); -- need to do only and, or and xor
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end logic_unit;
architecture Bhe of logic_unit is
begin
OUT1 <= IN1 and IN2 when CTRL = "00" else
IN1 or IN2 when CTRL = "01" else
IN1 xor IN2 when CTRL = "10" else
(others => '0'); -- should never appear
end Bhe;
|
package pkg is
constant cst : natural := 5;
end pkg;
|
package sim_types_pkg is
type descriptor_t is record
--address : std_ulogic_vector(dma_addr_range);
--length : std_ulogic_vector(dma_len_range);
address : natural;
length : positive;
end record;
procedure call_report (v : natural);
end package;
package body sim_types_pkg is
procedure call_report (v : natural) is
begin
report "call_report " & natural'image(v) severity note;
end call_report;
end sim_types_pkg;
|
library std;
use std.env.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SMSMapper_tb is
end SMSMapper_tb;
architecture rtl of SMSMapper_tb is
--input from sms
signal ADDR : std_logic_vector(15 downto 0);
signal DATA : std_logic_vector(7 downto 0);
signal nRST : std_logic;
signal nWR : std_logic;
signal nCE : std_logic;
--output to ROM
signal nROMWE : std_logic;
signal nROMCE : std_logic;
signal ROMADDR1914 : std_logic_vector(5 downto 0);
--output to serial EEPROM
signal EE_CS : std_logic;
signal EE_SO : std_logic;
signal EE_SI : std_logic;
signal EE_SCK : std_logic;
--output to SRAM
signal nSRAMCE : std_logic;
signal nSRAMWE : std_logic;
signal SRAMADDR14 : std_logic;
begin
SMSMapper_u0: entity work.SMSMapper
port map(
ADDR_p => ADDR,
DATA_p => DATA,
nRST_p => nRST,
nWR_p => nWR,
nCE_p => nCE,
nROMWE_p => nROMWE,
nROMCE_p => nROMCE,
ROMADDR1914_p => ROMADDR1914,
EE_CS_p => EE_CS,
EE_SO_p => EE_SO,
EE_SI_p => EE_SI,
EE_SCK_p => EE_SCK,
nSRAMCE_p => nSRAMCE,
nSRAMWE_p => nSRAMWE,
SRAMADDR14_p => SRAMADDR14
);
sim: process
begin
nRST <= '0';
DATA <= ( others => 'Z');
nROMWE <= 'H';
nROMCE <= 'H';
ROMADDR1914 <= (others => 'H');
ADDR <= ( others => '1');
nCE <= '1';
nWR <= '1';
wait for 10 ns;
nRST <= '1';
DATA <= x"04";
ADDR <= x"FFFD";
wait for 5 ns;
nCE <= '0';
nWR <= '0';
wait for 15 ns;
nCE <= '1';
nWR <= '1';
wait for 5 ns;
ADDR <= x"2000";
wait for 5 ns;
nCE <= '0';
wait for 15 ns;
nCE <= '1';
wait for 5 ns;
stop(0);
end process;
end architecture; |
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_REAL)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package defines a standard for designers to use in
-- describing VHDL models that make use of common REAL constants
-- and common REAL elementary mathematical functions.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076-
-- 1993.
--
-- Notes:
-- No declarations or definitions shall be included in, or
-- excluded from, this package.
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_REAL.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_REAL package declaration. The purpose of the MATH_REAL
-- package body is to provide a guideline for implementations to
-- verify their implementation of MATH_REAL. Tool developers may
-- choose to implement the package body in the most efficient
-- manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
package MATH_REAL is
constant CopyRightNotice: STRING
:= "Copyright 1996 IEEE. All rights reserved.";
--
-- Constant Definitions
--
constant MATH_E : REAL := 2.71828_18284_59045_23536;
-- Value of e
constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
-- Value of 1/e
constant MATH_PI : REAL := 3.14159_26535_89793_23846;
-- Value of pi
constant MATH_2_PI : REAL := 6.28318_53071_79586_47693;
-- Value of 2*pi
constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
-- Value of 1/pi
constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
-- Value of pi/2
constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
-- Value of pi/3
constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
-- Value of pi/4
constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
-- Value 3*pi/2
constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
-- Natural log of 2
constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
-- Natural log of 10
constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
-- Log base 2 of e
constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765;
-- Log base 10 of e
constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880;
-- square root of 2
constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440;
-- square root of 1/2
constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730;
-- square root of pi
constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577;
-- Conversion factor from degree to radian
constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680;
-- Conversion factor from radian to degree
--
-- Function Declarations
--
function SIGN (X: in REAL ) return REAL;
-- Purpose:
-- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIGN(X)) <= 1.0
-- Notes:
-- None
function CEIL (X : in REAL ) return REAL;
-- Purpose:
-- Returns smallest INTEGER value (as REAL) not less than X
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CEIL(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function FLOOR (X : in REAL ) return REAL;
-- Purpose:
-- Returns largest INTEGER value (as REAL) not greater than X
-- Special values:
-- FLOOR(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- FLOOR(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function ROUND (X : in REAL ) return REAL;
-- Purpose:
-- Rounds X to the nearest integer value (as real). If X is
-- halfway between two integers, rounding is away from 0.0
-- Special values:
-- ROUND(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ROUND(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function TRUNC (X : in REAL ) return REAL;
-- Purpose:
-- Truncates X towards 0.0 and returns truncated value
-- Special values:
-- TRUNC(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- TRUNC(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function "MOD" (X, Y: in REAL ) return REAL;
-- Purpose:
-- Returns floating point modulus of X/Y, with the same sign as
-- Y, and absolute value less than the absolute value of Y, and
-- for some INTEGER value N the result satisfies the relation
-- X = Y*N + MOD(X,Y)
-- Special values:
-- None
-- Domain:
-- X in REAL; Y in REAL and Y /= 0.0
-- Error conditions:
-- Error if Y = 0.0
-- Range:
-- ABS(MOD(X,Y)) < ABS(Y)
-- Notes:
-- None
function REALMAX (X, Y : in REAL ) return REAL;
-- Purpose:
-- Returns the algebraically larger of X and Y
-- Special values:
-- REALMAX(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMAX(X,Y) is mathematically unbounded
-- Notes:
-- None
function REALMIN (X, Y : in REAL ) return REAL;
-- Purpose:
-- Returns the algebraically smaller of X and Y
-- Special values:
-- REALMIN(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMIN(X,Y) is mathematically unbounded
-- Notes:
-- None
procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL);
-- Purpose:
-- Returns, in X, a pseudo-random number with uniform
-- distribution in the open interval (0.0, 1.0).
-- Special values:
-- None
-- Domain:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
-- Error conditions:
-- Error if SEED1 or SEED2 outside of valid domain
-- Range:
-- 0.0 < X < 1.0
-- Notes:
-- a) The semantics for this function are described by the
-- algorithm published by Pierre L'Ecuyer in "Communications
-- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
-- The algorithm is based on the combination of two
-- multiplicative linear congruential generators for 32-bit
-- platforms.
--
-- b) Before the first call to UNIFORM, the seed values
-- (SEED1, SEED2) have to be initialized to values in the range
-- [1, 2147483562] and [1, 2147483398] respectively. The
-- seed values are modified after each call to UNIFORM.
--
-- c) This random number generator is portable for 32-bit
-- computers, and it has a period of ~2.30584*(10**18) for each
-- set of seed values.
--
-- d) For information on spectral tests for the algorithm, refer
-- to the L'Ecuyer article.
function SQRT (X : in REAL ) return REAL;
-- Purpose:
-- Returns square root of X
-- Special values:
-- SQRT(0.0) = 0.0
-- SQRT(1.0) = 1.0
-- Domain:
-- X >= 0.0
-- Error conditions:
-- Error if X < 0.0
-- Range:
-- SQRT(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of SQRT is
-- approximately given by:
-- SQRT(X) <= SQRT(REAL'HIGH)
function CBRT (X : in REAL ) return REAL;
-- Purpose:
-- Returns cube root of X
-- Special values:
-- CBRT(0.0) = 0.0
-- CBRT(1.0) = 1.0
-- CBRT(-1.0) = -1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CBRT(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of CBRT is approximately given by:
-- ABS(CBRT(X)) <= CBRT(REAL'HIGH)
function "**" (X : in INTEGER; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0
-- 0**Y = 0.0; Y > 0.0
-- X**1.0 = REAL(X); X >= 0
-- 1**Y = 1.0
-- Domain:
-- X > 0
-- X = 0 for Y > 0.0
-- X < 0 for Y = 0.0
-- Error conditions:
-- Error if X < 0 and Y /= 0.0
-- Error if X = 0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function "**" (X : in REAL; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0.0
-- 0.0**Y = 0.0; Y > 0.0
-- X**1.0 = X; X >= 0.0
-- 1.0**Y = 1.0
-- Domain:
-- X > 0.0
-- X = 0.0 for Y > 0.0
-- X < 0.0 for Y = 0.0
-- Error conditions:
-- Error if X < 0.0 and Y /= 0.0
-- Error if X = 0.0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function EXP (X : in REAL ) return REAL;
-- Purpose:
-- Returns e**X; where e = MATH_E
-- Special values:
-- EXP(0.0) = 1.0
-- EXP(1.0) = MATH_E
-- EXP(-1.0) = MATH_1_OVER_E
-- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
-- Domain:
-- X in REAL such that EXP(X) <= REAL'HIGH
-- Error conditions:
-- Error if X > LOG(REAL'HIGH)
-- Range:
-- EXP(X) >= 0.0
-- Notes:
-- a) The usable domain of EXP is approximately given by:
-- X <= LOG(REAL'HIGH)
function LOG (X : in REAL ) return REAL;
-- Purpose:
-- Returns natural logarithm of X
-- Special values:
-- LOG(1.0) = 0.0
-- LOG(MATH_E) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG is approximately given by:
-- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
function LOG2 (X : in REAL ) return REAL;
-- Purpose:
-- Returns logarithm base 2 of X
-- Special values:
-- LOG2(1.0) = 0.0
-- LOG2(2.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG2(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG2 is approximately given by:
-- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
function LOG10 (X : in REAL ) return REAL;
-- Purpose:
-- Returns logarithm base 10 of X
-- Special values:
-- LOG10(1.0) = 0.0
-- LOG10(10.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG10(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG10 is approximately given by:
-- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
function LOG (X: in REAL; BASE: in REAL) return REAL;
-- Purpose:
-- Returns logarithm base BASE of X
-- Special values:
-- LOG(1.0, BASE) = 0.0
-- LOG(BASE, BASE) = 1.0
-- Domain:
-- X > 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if X <= 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(X, BASE) is mathematically unbounded
-- Notes:
-- a) When BASE > 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
-- b) When 0.0 < BASE < 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
function SIN (X : in REAL ) return REAL;
-- Purpose:
-- Returns sine of X; X in radians
-- Special values:
-- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function COS ( X : in REAL ) return REAL;
-- Purpose:
-- Returns cosine of X; X in radians
-- Special values:
-- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
-- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(COS(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function TAN (X : in REAL ) return REAL;
-- Purpose:
-- Returns tangent of X; X in radians
-- Special values:
-- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL and
-- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
-- Error conditions:
-- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
-- INTEGER
-- Range:
-- TAN(X) is mathematically unbounded
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function ARCSIN (X : in REAL ) return REAL;
-- Purpose:
-- Returns inverse sine of X
-- Special values:
-- ARCSIN(0.0) = 0.0
-- ARCSIN(1.0) = MATH_PI_OVER_2
-- ARCSIN(-1.0) = -MATH_PI_OVER_2
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- ABS(ARCSIN(X) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCCOS (X : in REAL ) return REAL;
-- Purpose:
-- Returns inverse cosine of X
-- Special values:
-- ARCCOS(1.0) = 0.0
-- ARCCOS(0.0) = MATH_PI_OVER_2
-- ARCCOS(-1.0) = MATH_PI
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- 0.0 <= ARCCOS(X) <= MATH_PI
-- Notes:
-- None
function ARCTAN (Y : in REAL) return REAL;
-- Purpose:
-- Returns the value of the angle in radians of the point
-- (1.0, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0) = 0.0
-- Domain:
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCTAN (Y : in REAL; X : in REAL) return REAL;
-- Purpose:
-- Returns the principal value of the angle in radians of
-- the point (X, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0, X) = 0.0 if X > 0.0
-- ARCTAN(0.0, X) = MATH_PI if X < 0.0
-- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
-- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
-- Domain:
-- Y in REAL
-- X in REAL, X /= 0.0 when Y = 0.0
-- Error conditions:
-- Error if X = 0.0 and Y = 0.0
-- Range:
-- -MATH_PI < ARCTAN(Y,X) <= MATH_PI
-- Notes:
-- None
function SINH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic sine of X
-- Special values:
-- SINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- SINH(X) is mathematically unbounded
-- Notes:
-- a) The usable domain of SINH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function COSH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic cosine of X
-- Special values:
-- COSH(0.0) = 1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- COSH(X) >= 1.0
-- Notes:
-- a) The usable domain of COSH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function TANH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic tangent of X
-- Special values:
-- TANH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(TANH(X)) <= 1.0
-- Notes:
-- None
function ARCSINH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic sine of X
-- Special values:
-- ARCSINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ARCSINH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCSINH is approximately given by:
-- ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
function ARCCOSH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic cosine of X
-- Special values:
-- ARCCOSH(1.0) = 0.0
-- Domain:
-- X >= 1.0
-- Error conditions:
-- Error if X < 1.0
-- Range:
-- ARCCOSH(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of ARCCOSH is
-- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH)
function ARCTANH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic tangent of X
-- Special values:
-- ARCTANH(0.0) = 0.0
-- Domain:
-- ABS(X) < 1.0
-- Error conditions:
-- Error if ABS(X) >= 1.0
-- Range:
-- ARCTANH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCTANH is approximately given by:
-- ABS(ARCTANH(X)) < LOG(REAL'HIGH)
end MATH_REAL;
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_REAL)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package body is a nonnormative implementation of the
-- functionality defined in the MATH_REAL package declaration.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076
-- -1993.
--
-- Notes:
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_REAL.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_REAL package declaration. The purpose of the MATH_REAL
-- package body is to clarify such semantics and provide a
-- guideline for implementations to verify their implementation
-- of MATH_REAL. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
package body MATH_REAL is
--
-- Local Constants for Use in the Package Body Only
--
constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2
constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10
constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi
constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic
constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries
constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria
constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic
--
-- Local Type Declarations for Cordic Operations
--
type REAL_VECTOR is array (NATURAL range <>) of REAL;
type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL;
subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER);
subtype REAL_ARR_2 is REAL_VECTOR (0 to 1);
subtype REAL_ARR_3 is REAL_VECTOR (0 to 2);
subtype QUADRANT is INTEGER range 0 to 3;
type CORDIC_MODE_TYPE is (ROTATION, VECTORING);
--
-- Auxiliary Functions for Cordic Algorithms
--
function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL;
NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is
-- Description:
-- Returns power of two for a vector of values
-- Notes:
-- None
--
variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES);
variable TEMP : REAL := INITIAL_VALUE;
variable FLAG : BOOLEAN := TRUE;
begin
for I in 0 to NUMBER_OF_VALUES loop
V(I) := TEMP;
for P in D'RANGE loop
if I = D(P) then
FLAG := FALSE;
exit;
end if;
end loop;
if FLAG then
TEMP := TEMP/2.0;
end if;
FLAG := TRUE;
end loop;
return V;
end POWER_OF_2_SERIES;
constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES(
NATURAL_VECTOR'(100, 90),1.0,
MAX_ITER);
constant EPSILON : REAL_VECTOR_N := (
7.8539816339744827e-01,
4.6364760900080606e-01,
2.4497866312686413e-01,
1.2435499454676144e-01,
6.2418809995957351e-02,
3.1239833430268277e-02,
1.5623728620476830e-02,
7.8123410601011116e-03,
3.9062301319669717e-03,
1.9531225164788189e-03,
9.7656218955931937e-04,
4.8828121119489829e-04,
2.4414062014936175e-04,
1.2207031189367021e-04,
6.1035156174208768e-05,
3.0517578115526093e-05,
1.5258789061315760e-05,
7.6293945311019699e-06,
3.8146972656064960e-06,
1.9073486328101870e-06,
9.5367431640596080e-07,
4.7683715820308876e-07,
2.3841857910155801e-07,
1.1920928955078067e-07,
5.9604644775390553e-08,
2.9802322387695303e-08,
1.4901161193847654e-08,
7.4505805969238281e-09
);
function CORDIC ( X0 : in REAL;
Y0 : in REAL;
Z0 : in REAL;
N : in NATURAL; -- Precision factor
CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0)
-- or vectoring (Y -> 0)
) return REAL_ARR_3 is
-- Description:
-- Compute cordic values
-- Notes:
-- None
variable X : REAL := X0;
variable Y : REAL := Y0;
variable Z : REAL := Z0;
variable X_TEMP : REAL;
begin
if CORDIC_MODE = ROTATION then
for K in 0 to N loop
X_TEMP := X;
if ( Z >= 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
else
for K in 0 to N loop
X_TEMP := X;
if ( Y < 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
end if;
return REAL_ARR_3'(X, Y, Z);
end CORDIC;
--
-- Bodies for Global Mathematical Functions Start Here
--
function SIGN (X: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
if ( X > 0.0 ) then
return 1.0;
elsif ( X < 0.0 ) then
return -1.0;
else
return 0.0;
end if;
end SIGN;
function CEIL (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is X <= LARGE
-- c) Returns X if ABS(X) >= LARGE
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
begin
if ABS(X) >= LARGE then
return X;
end if;
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
if X > 0.0 then
if RD >= X then
return RD;
else
return RD + 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD <= X then
return RD + 1.0;
else
return RD;
end if;
end if;
end CEIL;
function FLOOR (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is ABS(X) <= LARGE
-- c) Returns X if ABS(X) >= LARGE
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
begin
if ABS( X ) >= LARGE then
return X;
end if;
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
if X > 0.0 then
if RD <= X then
return RD;
else
return RD - 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD >= X then
return RD - 1.0;
else
return RD;
end if;
end if;
end FLOOR;
function ROUND (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X + 0.5) if X > 0
-- c) Returns CEIL(X - 0.5) if X < 0
begin
if X > 0.0 then
return FLOOR(X + 0.5);
elsif X < 0.0 then
return CEIL( X - 0.5);
else
return 0.0;
end if;
end ROUND;
function TRUNC (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X) if X > 0
-- c) Returns CEIL(X) if X < 0
begin
if X > 0.0 then
return FLOOR(X);
elsif X < 0.0 then
return CEIL( X);
else
return 0.0;
end if;
end TRUNC;
function "MOD" (X, Y: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
variable XNEGATIVE : BOOLEAN := X < 0.0;
variable YNEGATIVE : BOOLEAN := Y < 0.0;
variable VALUE : REAL;
begin
-- Check validity of input arguments
if (Y = 0.0) then
assert FALSE
report "MOD(X, 0.0) is undefined"
severity ERROR;
return 0.0;
end if;
-- Compute value
if ( XNEGATIVE ) then
if ( YNEGATIVE ) then
VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
end if;
else
if ( YNEGATIVE ) then
VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
end if;
end if;
return VALUE;
end "MOD";
function REALMAX (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMAX(X,Y) = X when X = Y
--
begin
if X >= Y then
return X;
else
return Y;
end if;
end REALMAX;
function REALMIN (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMIN(X,Y) = X when X = Y
--
begin
if X <= Y then
return X;
else
return Y;
end if;
end REALMIN;
procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL)
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
--
variable Z, K: INTEGER;
variable TSEED1 : INTEGER := INTEGER'(SEED1);
variable TSEED2 : INTEGER := INTEGER'(SEED2);
begin
-- Check validity of arguments
if SEED1 > 2147483562 then
assert FALSE
report "SEED1 > 2147483562 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
if SEED2 > 2147483398 then
assert FALSE
report "SEED2 > 2147483398 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
-- Compute new seed values and pseudo-random number
K := TSEED1/53668;
TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211;
if TSEED1 < 0 then
TSEED1 := TSEED1 + 2147483563;
end if;
K := TSEED2/52774;
TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791;
if TSEED2 < 0 then
TSEED2 := TSEED2 + 2147483399;
end if;
Z := TSEED1 - TSEED2;
if Z < 1 then
Z := Z + 2147483562;
end if;
-- Get output values
SEED1 := POSITIVE'(TSEED1);
SEED2 := POSITIVE'(TSEED2);
X := REAL(Z)*4.656613e-10;
end UNIFORM;
function SQRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = 0.5*[F(n) + x/F(n)]
-- b) Returns 0.0 on error
--
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor
variable INIVAL: REAL;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
begin
-- Check validity of argument
if ( X < 0.0 ) then
assert FALSE
report "X < 0.0 in SQRT(X)"
severity ERROR;
return 0.0;
end if;
-- Get the square root for special cases
if X = 0.0 then
return 0.0;
else
if ( X = 1.0 ) then
return 1.0;
end if;
end if;
-- Get the square root for general cases
INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise
OLDVAL := INIVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
-- Check for relative and absolute error and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT) ) loop
OLDVAL := NEWVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
COUNT := COUNT + 1;
end loop;
return NEWVAL;
end SQRT;
function CBRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2];
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
variable INIVAL: REAL;
variable XLOCAL : REAL := X;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
begin
-- Compute root for special cases
if X = 0.0 then
return 0.0;
elsif ( X = 1.0 ) then
return 1.0;
else
if X = -1.0 then
return -1.0;
end if;
end if;
-- Compute root for general cases
if NEGATIVE then
XLOCAL := -X;
end if;
INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but
-- imprecise
OLDVAL := INIVAL;
NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR
(ABS(NEWVAL - OLDVAL) > EPS ) ) AND
( COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
COUNT := COUNT + 1;
end loop;
if NEGATIVE then
NEWVAL := -NEWVAL;
end if;
return NEWVAL;
end CBRT;
function "**" (X : in INTEGER; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
begin
-- Check validity of argument
if ( ( X < 0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
if ( ( X = 0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
-- Get value for special cases
if ( X = 0 and Y > 0.0 ) then
return 0.0;
end if;
if ( X = 1 ) then
return 1.0;
end if;
if ( Y = 0.0 and X /= 0 ) then
return 1.0;
end if;
if ( Y = 1.0) then
return (REAL(X));
end if;
-- Get value for general case
return EXP (Y * LOG (REAL(X)));
end "**";
function "**" (X : in REAL; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
begin
-- Check validity of argument
if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0.0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0.0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
-- Get value for special cases
if ( X = 0.0 and Y > 0.0 ) then
return 0.0;
end if;
if ( X = 1.0 ) then
return 1.0;
end if;
if ( Y = 0.0 and X /= 0.0 ) then
return 1.0;
end if;
if ( Y = 1.0) then
return (X);
end if;
-- Get value for general case
return EXP (Y * LOG (X));
end "**";
function EXP (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) This function computes the exponential using the following
-- series:
-- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0
-- and reduces argument X to take advantage of exp(x+y) =
-- exp(x)*exp(y)
--
-- b) This implementation limits X to be less than LOG(REAL'HIGH)
-- to avoid overflow. Returns REAL'HIGH when X reaches that
-- limit
--
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria
variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument
variable XLOCAL : REAL := ABS(X); -- Use positive value
variable OLDVAL: REAL ;
variable COUNT: INTEGER ;
variable NEWVAL: REAL ;
variable LAST_TERM: REAL ;
variable FACTOR : REAL := 1.0;
begin
-- Compute value for special cases
if X = 0.0 then
return 1.0;
end if;
if XLOCAL = 1.0 then
if RECIPROCAL then
return MATH_1_OVER_E;
else
return MATH_E;
end if;
end if;
if XLOCAL = 2.0 then
if RECIPROCAL then
return 1.0/MATH_E_P2;
else
return MATH_E_P2;
end if;
end if;
if XLOCAL = 10.0 then
if RECIPROCAL then
return 1.0/MATH_E_P10;
else
return MATH_E_P10;
end if;
end if;
if XLOCAL > LOG(REAL'HIGH) then
if RECIPROCAL then
return 0.0;
else
assert FALSE
report "X > LOG(REAL'HIGH) in EXP(X)"
severity NOTE;
return REAL'HIGH;
end if;
end if;
-- Reduce argument to ABS(X) < 1.0
while XLOCAL > 10.0 loop
XLOCAL := XLOCAL - 10.0;
FACTOR := FACTOR*MATH_E_P10;
end loop;
while XLOCAL > 1.0 loop
XLOCAL := XLOCAL - 1.0;
FACTOR := FACTOR*MATH_E;
end loop;
-- Compute value for case 0 < XLOCAL < 1
OLDVAL := 1.0;
LAST_TERM := XLOCAL;
NEWVAL:= OLDVAL + LAST_TERM;
COUNT := 2;
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT)));
NEWVAL := OLDVAL + LAST_TERM;
COUNT := COUNT + 1;
end loop;
-- Compute final value using exp(x+y) = exp(x)*exp(y)
NEWVAL := NEWVAL*FACTOR;
if RECIPROCAL then
NEWVAL := 1.0/NEWVAL;
end if;
return NEWVAL;
end EXP;
--
-- Auxiliary Functions to Compute LOG
--
function ILOGB(X: in REAL) return INTEGER IS
-- Description:
-- Returns n such that -1 <= ABS(X)/2^n < 2
-- Notes:
-- None
variable N: INTEGER := 0;
variable Y: REAL := ABS(X);
begin
if(Y = 1.0 or Y = 0.0) then
return 0;
end if;
if( Y > 1.0) then
while Y >= 2.0 loop
Y := Y/2.0;
N := N+1;
end loop;
return N;
end if;
-- O < Y < 1
while Y < 1.0 loop
Y := Y*2.0;
N := N -1;
end loop;
return N;
end ILOGB;
function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS
-- Description:
-- Returns X*2^n
-- Notes:
-- None
begin
return X*(2.0 ** N);
end LDEXP;
function LOG (X : in REAL ) return REAL IS
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
--
-- Notes:
-- a) Returns REAL'LOW on error
--
-- Copyright (c) 1992 Regents of the University of California.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. All advertising materials mentioning features or use of this
-- software must display the following acknowledgement:
-- This product includes software developed by the University of
-- California, Berkeley and its contributors.
-- 4. Neither the name of the University nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-- DAMAGE.
--
-- NOTE: This VHDL version was generated using the C version of the
-- original function by the IEEE VHDL Mathematical Package
-- Working Group (CS/JT)
constant N: INTEGER := 128;
-- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128.
-- Used for generation of extend precision logarithms.
-- The constant 35184372088832 is 2^45, so the divide is exact.
-- It ensures correct reading of logF_head, even for inaccurate
-- decimal-to-binary conversion routines. (Everybody gets the
-- right answer for INTEGERs less than 2^53.)
-- Values for LOG(F) were generated using error < 10^-57 absolute
-- with the bc -l package.
type REAL_VECTOR is array (NATURAL range <>) of REAL;
constant A1:REAL := 0.08333333333333178827;
constant A2:REAL := 0.01250000000377174923;
constant A3:REAL := 0.002232139987919447809;
constant A4:REAL := 0.0004348877777076145742;
constant LOGF_HEAD: REAL_VECTOR(0 TO N) := (
0.0,
0.007782140442060381246,
0.015504186535963526694,
0.023167059281547608406,
0.030771658666765233647,
0.038318864302141264488,
0.045809536031242714670,
0.053244514518837604555,
0.060624621816486978786,
0.067950661908525944454,
0.075223421237524235039,
0.082443669210988446138,
0.089612158689760690322,
0.096729626458454731618,
0.103796793681567578460,
0.110814366340264314203,
0.117783035656430001836,
0.124703478501032805070,
0.131576357788617315236,
0.138402322859292326029,
0.145182009844575077295,
0.151916042025732167530,
0.158605030176659056451,
0.165249572895390883786,
0.171850256926518341060,
0.178407657472689606947,
0.184922338493834104156,
0.191394852999565046047,
0.197825743329758552135,
0.204215541428766300668,
0.210564769107350002741,
0.216873938300523150246,
0.223143551314024080056,
0.229374101064877322642,
0.235566071312860003672,
0.241719936886966024758,
0.247836163904594286577,
0.253915209980732470285,
0.259957524436686071567,
0.265963548496984003577,
0.271933715484010463114,
0.277868451003087102435,
0.283768173130738432519,
0.289633292582948342896,
0.295464212893421063199,
0.301261330578199704177,
0.307025035294827830512,
0.312755710004239517729,
0.318453731118097493890,
0.324119468654316733591,
0.329753286372579168528,
0.335355541920762334484,
0.340926586970454081892,
0.346466767346100823488,
0.351976423156884266063,
0.357455888922231679316,
0.362905493689140712376,
0.368325561158599157352,
0.373716409793814818840,
0.379078352934811846353,
0.384411698910298582632,
0.389716751140440464951,
0.394993808240542421117,
0.400243164127459749579,
0.405465108107819105498,
0.410659924985338875558,
0.415827895143593195825,
0.420969294644237379543,
0.426084395310681429691,
0.431173464818130014464,
0.436236766774527495726,
0.441274560805140936281,
0.446287102628048160113,
0.451274644139630254358,
0.456237433481874177232,
0.461175715122408291790,
0.466089729924533457960,
0.470979715219073113985,
0.475845904869856894947,
0.480688529345570714212,
0.485507815781602403149,
0.490303988045525329653,
0.495077266798034543171,
0.499827869556611403822,
0.504556010751912253908,
0.509261901790523552335,
0.513945751101346104405,
0.518607764208354637958,
0.523248143765158602036,
0.527867089620485785417,
0.532464798869114019908,
0.537041465897345915436,
0.541597282432121573947,
0.546132437597407260909,
0.550647117952394182793,
0.555141507540611200965,
0.559615787935399566777,
0.564070138285387656651,
0.568504735352689749561,
0.572919753562018740922,
0.577315365035246941260,
0.581691739635061821900,
0.586049045003164792433,
0.590387446602107957005,
0.594707107746216934174,
0.599008189645246602594,
0.603290851438941899687,
0.607555250224322662688,
0.611801541106615331955,
0.616029877215623855590,
0.620240409751204424537,
0.624433288012369303032,
0.628608659422752680256,
0.632766669570628437213,
0.636907462236194987781,
0.641031179420679109171,
0.645137961373620782978,
0.649227946625615004450,
0.653301272011958644725,
0.657358072709030238911,
0.661398482245203922502,
0.665422632544505177065,
0.669430653942981734871,
0.673422675212350441142,
0.677398823590920073911,
0.681359224807238206267,
0.685304003098281100392,
0.689233281238557538017,
0.693147180560117703862);
constant LOGF_TAIL: REAL_VECTOR(0 TO N) := (
0.0,
-0.00000000000000543229938420049,
0.00000000000000172745674997061,
-0.00000000000001323017818229233,
-0.00000000000001154527628289872,
-0.00000000000000466529469958300,
0.00000000000005148849572685810,
-0.00000000000002532168943117445,
-0.00000000000005213620639136504,
-0.00000000000001819506003016881,
0.00000000000006329065958724544,
0.00000000000008614512936087814,
-0.00000000000007355770219435028,
0.00000000000009638067658552277,
0.00000000000007598636597194141,
0.00000000000002579999128306990,
-0.00000000000004654729747598444,
-0.00000000000007556920687451336,
0.00000000000010195735223708472,
-0.00000000000017319034406422306,
-0.00000000000007718001336828098,
0.00000000000010980754099855238,
-0.00000000000002047235780046195,
-0.00000000000008372091099235912,
0.00000000000014088127937111135,
0.00000000000012869017157588257,
0.00000000000017788850778198106,
0.00000000000006440856150696891,
0.00000000000016132822667240822,
-0.00000000000007540916511956188,
-0.00000000000000036507188831790,
0.00000000000009120937249914984,
0.00000000000018567570959796010,
-0.00000000000003149265065191483,
-0.00000000000009309459495196889,
0.00000000000017914338601329117,
-0.00000000000001302979717330866,
0.00000000000023097385217586939,
0.00000000000023999540484211737,
0.00000000000015393776174455408,
-0.00000000000036870428315837678,
0.00000000000036920375082080089,
-0.00000000000009383417223663699,
0.00000000000009433398189512690,
0.00000000000041481318704258568,
-0.00000000000003792316480209314,
0.00000000000008403156304792424,
-0.00000000000034262934348285429,
0.00000000000043712191957429145,
-0.00000000000010475750058776541,
-0.00000000000011118671389559323,
0.00000000000037549577257259853,
0.00000000000013912841212197565,
0.00000000000010775743037572640,
0.00000000000029391859187648000,
-0.00000000000042790509060060774,
0.00000000000022774076114039555,
0.00000000000010849569622967912,
-0.00000000000023073801945705758,
0.00000000000015761203773969435,
0.00000000000003345710269544082,
-0.00000000000041525158063436123,
0.00000000000032655698896907146,
-0.00000000000044704265010452446,
0.00000000000034527647952039772,
-0.00000000000007048962392109746,
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variable M, J:INTEGER;
variable F1, F2, G, Q, U, U2, V: REAL;
variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs
variable ONE: REAL := 1.0; --Made variable so no constant folding occurs
-- double logb(), ldexp();
variable U1:REAL;
begin
-- Check validity of argument
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = MATH_E ) then
return 1.0;
end if;
-- Argument reduction: 1 <= g < 2; x/2^m = g;
-- y = F*(1 + f/F) for |f| <= 2^-8
M := ILOGB(X);
G := LDEXP(X, -M);
J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding
F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512]
F2 := G - F1;
-- Approximate expansion for log(1+f2/F1) ~= u + q
G := 1.0/(2.0*F1+F2);
U := 2.0*F2*G;
V := U*U;
Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4)));
-- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8,
-- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits.
-- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750.
--
if ( J /= 0 or M /= 0) then
U1 := U + 513.0;
U1 := U1 - 513.0;
-- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero
-- u1 = u to 24 bits.
--
else
U1 := U;
--TRUNC(U1); --In c this is u1 = (double) (float) (u1)
end if;
U2 := (2.0*(F2 - F1*U1) - U1*F2) * G;
-- u1 + u2 = 2f/(2F+f) to extra precision.
-- log(x) = log(2^m*F1*(1+f2/F1)) =
-- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q);
-- (exact) + (tiny)
U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact
U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny
U2 := U2 + LOGF_TAIL(N)*REAL(M);
return (U1 + U2);
end LOG;
function LOG2 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG2(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = 2.0 ) then
return 1.0;
end if;
-- Compute value for general case
return ( MATH_LOG2_OF_E*LOG(X) );
end LOG2;
function LOG10 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG10(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = 10.0 ) then
return 1.0;
end if;
-- Compute value for general case
return ( MATH_LOG10_OF_E*LOG(X) );
end LOG10;
function LOG (X: in REAL; BASE: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = BASE ) then
return 1.0;
end if;
-- Compute value for general case
return ( LOG(X)/LOG(BASE));
end LOG;
function SIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) SIN(-X) = -SIN(X)
-- b) SIN(X) = X if ABS(X) < EPS
-- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS
-- d) SIN(MATH_PI_OVER_2 - X) = COS(X)
-- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS
-- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence criteria
variable N : INTEGER;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in SIN(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then
return 0.0;
end if;
if XLOCAL = MATH_PI_OVER_2 then
if NEGATIVE then
return -1.0;
else
return 1.0;
end if;
end if;
if XLOCAL = MATH_3_PI_OVER_2 then
if NEGATIVE then
return 1.0;
else
return -1.0;
end if;
end if;
if XLOCAL < EPS then
if NEGATIVE then
return -XLOCAL;
else
return XLOCAL;
end if;
else
if XLOCAL < BASE_EPS then
TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := MATH_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := MATH_2_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
TEMP := ABS(MATH_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
-- Compute value for general cases
if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then
VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1);
end if;
N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2));
case QUADRANT( N mod 4) is
when 0 =>
VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1);
when 1 =>
VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27,
ROTATION)(0);
when 2 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1);
when 3 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27,
ROTATION)(0);
end case;
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end SIN;
function COS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) COS(-X) = COS(X)
-- b) COS(X) = SIN(MATH_PI_OVER_2 - X)
-- c) COS(MATH_PI + X) = -COS(X)
-- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS
-- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
variable XLOCAL : REAL := ABS(X);
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in COS(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then
return 1.0;
end if;
if XLOCAL = MATH_PI then
return -1.0;
end if;
if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then
return 0.0;
end if;
TEMP := ABS(XLOCAL);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
TEMP := ABS(XLOCAL -MATH_2_PI);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
TEMP := ABS (XLOCAL - MATH_PI);
if TEMP < EPS then
return (-1.0 + 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
-- Compute value for general cases
return SIN(MATH_PI_OVER_2 - XLOCAL);
end COS;
function TAN (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) TAN(0.0) = 0.0
-- b) TAN(-X) = -TAN(X)
-- c) Returns REAL'LOW on error if X < 0.0
-- d) Returns REAL'HIGH on error if X > 0.0
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make 0.0 <= XLOCAL <= MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in TAN(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Check validity of argument
if XLOCAL = MATH_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'LOW);
else
return(REAL'HIGH);
end if;
end if;
if XLOCAL = MATH_3_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'HIGH);
else
return(REAL'LOW);
end if;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_PI then
return 0.0;
end if;
-- Compute value for general cases
VALUE := SIN(XLOCAL)/COS(XLOCAL);
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end TAN;
function ARCSIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCSIN(-X) = -ARCSIN(X)
-- b) Returns X on error
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
begin
-- Check validity of arguments
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCSIN(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
elsif XLOCAL = 1.0 then
if NEGATIVE then
return -MATH_PI_OVER_2;
else
return MATH_PI_OVER_2;
end if;
end if;
-- Compute value for general cases
if XLOCAL < 0.9 then
VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL)));
else
VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
end if;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end ARCSIN;
function ARCCOS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCCOS(-X) = MATH_PI - ARCCOS(X)
-- b) Returns X on error
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
begin
-- Check validity of argument
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCCOS(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 1.0 then
return 0.0;
elsif X = 0.0 then
return MATH_PI_OVER_2;
elsif X = -1.0 then
return MATH_PI;
end if;
-- Compute value for general cases
if XLOCAL > 0.9 then
VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
else
VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL));
end if;
if NEGATIVE then
VALUE := MATH_PI - VALUE;
end if;
return VALUE;
end ARCCOS;
function ARCTAN (Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCTAN(-Y) = -ARCTAN(Y)
-- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0
-- c) ARCTAN(Y) = Y for |Y| < EPS
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;
variable NEGATIVE : BOOLEAN := Y < 0.0;
variable RECIPROCAL : BOOLEAN;
variable YLOCAL : REAL := ABS(Y);
variable VALUE : REAL;
begin
-- Make argument |Y| <=1.0
if YLOCAL > 1.0 then
YLOCAL := 1.0/YLOCAL;
RECIPROCAL := TRUE;
else
RECIPROCAL := FALSE;
end if;
-- Compute value for special cases
if YLOCAL = 0.0 then
if RECIPROCAL then
if NEGATIVE then
return (-MATH_PI_OVER_2);
else
return (MATH_PI_OVER_2);
end if;
else
return 0.0;
end if;
end if;
if YLOCAL < EPS then
if NEGATIVE then
if RECIPROCAL then
return (-MATH_PI_OVER_2 + YLOCAL);
else
return -YLOCAL;
end if;
else
if RECIPROCAL then
return (MATH_PI_OVER_2 - YLOCAL);
else
return YLOCAL;
end if;
end if;
end if;
-- Compute value for general cases
VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2);
if RECIPROCAL then
VALUE := MATH_PI_OVER_2 - VALUE;
end if;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end ARCTAN;
function ARCTAN (Y : in REAL; X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
variable YLOCAL : REAL;
variable VALUE : REAL;
begin
-- Check validity of arguments
if (Y = 0.0 and X = 0.0 ) then
assert FALSE report
"ARCTAN(0.0, 0.0) is undetermined"
severity ERROR;
return 0.0;
end if;
-- Compute value for special cases
if Y = 0.0 then
if X > 0.0 then
return 0.0;
else
return MATH_PI;
end if;
end if;
if X = 0.0 then
if Y > 0.0 then
return MATH_PI_OVER_2;
else
return -MATH_PI_OVER_2;
end if;
end if;
-- Compute value for general cases
YLOCAL := ABS(Y/X);
VALUE := ARCTAN(YLOCAL);
if X < 0.0 then
VALUE := MATH_PI - VALUE;
end if;
if Y < 0.0 then
VALUE := -VALUE;
end if;
return VALUE;
end ARCTAN;
function SINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/2.0
-- b) SINH(-X) = SINH(X)
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)*0.5;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end SINH;
function COSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) + EXP(-X))/2.0
-- b) COSH(-X) = COSH(X)
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 1.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP + 1.0/TEMP)*0.5;
return VALUE;
end COSH;
function TANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X))
-- b) TANH(-X) = -TANH(X)
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP);
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end TANH;
function ARCSINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X + 1.0))
begin
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
return ( LOG( X + SQRT( X*X + 1.0)) );
end ARCSINH;
function ARCCOSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0
-- b) Returns X on error
begin
-- Check validity of arguments
if X < 1.0 then
assert FALSE
report "X < 1.0 in ARCCOSH(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 1.0 then
return 0.0;
end if;
-- Compute value for general cases
return ( LOG( X + SQRT( X*X - 1.0)));
end ARCCOSH;
function ARCTANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0
-- b) Returns X on error
begin
-- Check validity of arguments
if ABS(X) >= 1.0 then
assert FALSE
report "ABS(X) >= 1.0 in ARCTANH(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
return( 0.5*LOG( (1.0+X)/(1.0-X) ) );
end ARCTANH;
end MATH_REAL;
|
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_REAL)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package defines a standard for designers to use in
-- describing VHDL models that make use of common REAL constants
-- and common REAL elementary mathematical functions.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076-
-- 1993.
--
-- Notes:
-- No declarations or definitions shall be included in, or
-- excluded from, this package.
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_REAL.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_REAL package declaration. The purpose of the MATH_REAL
-- package body is to provide a guideline for implementations to
-- verify their implementation of MATH_REAL. Tool developers may
-- choose to implement the package body in the most efficient
-- manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
package MATH_REAL is
constant CopyRightNotice: STRING
:= "Copyright 1996 IEEE. All rights reserved.";
--
-- Constant Definitions
--
constant MATH_E : REAL := 2.71828_18284_59045_23536;
-- Value of e
constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
-- Value of 1/e
constant MATH_PI : REAL := 3.14159_26535_89793_23846;
-- Value of pi
constant MATH_2_PI : REAL := 6.28318_53071_79586_47693;
-- Value of 2*pi
constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
-- Value of 1/pi
constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
-- Value of pi/2
constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
-- Value of pi/3
constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
-- Value of pi/4
constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
-- Value 3*pi/2
constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
-- Natural log of 2
constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
-- Natural log of 10
constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
-- Log base 2 of e
constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765;
-- Log base 10 of e
constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880;
-- square root of 2
constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440;
-- square root of 1/2
constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730;
-- square root of pi
constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577;
-- Conversion factor from degree to radian
constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680;
-- Conversion factor from radian to degree
--
-- Function Declarations
--
function SIGN (X: in REAL ) return REAL;
-- Purpose:
-- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIGN(X)) <= 1.0
-- Notes:
-- None
function CEIL (X : in REAL ) return REAL;
-- Purpose:
-- Returns smallest INTEGER value (as REAL) not less than X
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CEIL(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function FLOOR (X : in REAL ) return REAL;
-- Purpose:
-- Returns largest INTEGER value (as REAL) not greater than X
-- Special values:
-- FLOOR(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- FLOOR(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function ROUND (X : in REAL ) return REAL;
-- Purpose:
-- Rounds X to the nearest integer value (as real). If X is
-- halfway between two integers, rounding is away from 0.0
-- Special values:
-- ROUND(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ROUND(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function TRUNC (X : in REAL ) return REAL;
-- Purpose:
-- Truncates X towards 0.0 and returns truncated value
-- Special values:
-- TRUNC(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- TRUNC(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function "MOD" (X, Y: in REAL ) return REAL;
-- Purpose:
-- Returns floating point modulus of X/Y, with the same sign as
-- Y, and absolute value less than the absolute value of Y, and
-- for some INTEGER value N the result satisfies the relation
-- X = Y*N + MOD(X,Y)
-- Special values:
-- None
-- Domain:
-- X in REAL; Y in REAL and Y /= 0.0
-- Error conditions:
-- Error if Y = 0.0
-- Range:
-- ABS(MOD(X,Y)) < ABS(Y)
-- Notes:
-- None
function REALMAX (X, Y : in REAL ) return REAL;
-- Purpose:
-- Returns the algebraically larger of X and Y
-- Special values:
-- REALMAX(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMAX(X,Y) is mathematically unbounded
-- Notes:
-- None
function REALMIN (X, Y : in REAL ) return REAL;
-- Purpose:
-- Returns the algebraically smaller of X and Y
-- Special values:
-- REALMIN(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMIN(X,Y) is mathematically unbounded
-- Notes:
-- None
procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL);
-- Purpose:
-- Returns, in X, a pseudo-random number with uniform
-- distribution in the open interval (0.0, 1.0).
-- Special values:
-- None
-- Domain:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
-- Error conditions:
-- Error if SEED1 or SEED2 outside of valid domain
-- Range:
-- 0.0 < X < 1.0
-- Notes:
-- a) The semantics for this function are described by the
-- algorithm published by Pierre L'Ecuyer in "Communications
-- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
-- The algorithm is based on the combination of two
-- multiplicative linear congruential generators for 32-bit
-- platforms.
--
-- b) Before the first call to UNIFORM, the seed values
-- (SEED1, SEED2) have to be initialized to values in the range
-- [1, 2147483562] and [1, 2147483398] respectively. The
-- seed values are modified after each call to UNIFORM.
--
-- c) This random number generator is portable for 32-bit
-- computers, and it has a period of ~2.30584*(10**18) for each
-- set of seed values.
--
-- d) For information on spectral tests for the algorithm, refer
-- to the L'Ecuyer article.
function SQRT (X : in REAL ) return REAL;
-- Purpose:
-- Returns square root of X
-- Special values:
-- SQRT(0.0) = 0.0
-- SQRT(1.0) = 1.0
-- Domain:
-- X >= 0.0
-- Error conditions:
-- Error if X < 0.0
-- Range:
-- SQRT(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of SQRT is
-- approximately given by:
-- SQRT(X) <= SQRT(REAL'HIGH)
function CBRT (X : in REAL ) return REAL;
-- Purpose:
-- Returns cube root of X
-- Special values:
-- CBRT(0.0) = 0.0
-- CBRT(1.0) = 1.0
-- CBRT(-1.0) = -1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CBRT(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of CBRT is approximately given by:
-- ABS(CBRT(X)) <= CBRT(REAL'HIGH)
function "**" (X : in INTEGER; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0
-- 0**Y = 0.0; Y > 0.0
-- X**1.0 = REAL(X); X >= 0
-- 1**Y = 1.0
-- Domain:
-- X > 0
-- X = 0 for Y > 0.0
-- X < 0 for Y = 0.0
-- Error conditions:
-- Error if X < 0 and Y /= 0.0
-- Error if X = 0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function "**" (X : in REAL; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0.0
-- 0.0**Y = 0.0; Y > 0.0
-- X**1.0 = X; X >= 0.0
-- 1.0**Y = 1.0
-- Domain:
-- X > 0.0
-- X = 0.0 for Y > 0.0
-- X < 0.0 for Y = 0.0
-- Error conditions:
-- Error if X < 0.0 and Y /= 0.0
-- Error if X = 0.0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function EXP (X : in REAL ) return REAL;
-- Purpose:
-- Returns e**X; where e = MATH_E
-- Special values:
-- EXP(0.0) = 1.0
-- EXP(1.0) = MATH_E
-- EXP(-1.0) = MATH_1_OVER_E
-- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
-- Domain:
-- X in REAL such that EXP(X) <= REAL'HIGH
-- Error conditions:
-- Error if X > LOG(REAL'HIGH)
-- Range:
-- EXP(X) >= 0.0
-- Notes:
-- a) The usable domain of EXP is approximately given by:
-- X <= LOG(REAL'HIGH)
function LOG (X : in REAL ) return REAL;
-- Purpose:
-- Returns natural logarithm of X
-- Special values:
-- LOG(1.0) = 0.0
-- LOG(MATH_E) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG is approximately given by:
-- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
function LOG2 (X : in REAL ) return REAL;
-- Purpose:
-- Returns logarithm base 2 of X
-- Special values:
-- LOG2(1.0) = 0.0
-- LOG2(2.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG2(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG2 is approximately given by:
-- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
function LOG10 (X : in REAL ) return REAL;
-- Purpose:
-- Returns logarithm base 10 of X
-- Special values:
-- LOG10(1.0) = 0.0
-- LOG10(10.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG10(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG10 is approximately given by:
-- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
function LOG (X: in REAL; BASE: in REAL) return REAL;
-- Purpose:
-- Returns logarithm base BASE of X
-- Special values:
-- LOG(1.0, BASE) = 0.0
-- LOG(BASE, BASE) = 1.0
-- Domain:
-- X > 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if X <= 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(X, BASE) is mathematically unbounded
-- Notes:
-- a) When BASE > 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
-- b) When 0.0 < BASE < 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
function SIN (X : in REAL ) return REAL;
-- Purpose:
-- Returns sine of X; X in radians
-- Special values:
-- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function COS ( X : in REAL ) return REAL;
-- Purpose:
-- Returns cosine of X; X in radians
-- Special values:
-- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
-- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(COS(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function TAN (X : in REAL ) return REAL;
-- Purpose:
-- Returns tangent of X; X in radians
-- Special values:
-- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL and
-- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
-- Error conditions:
-- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
-- INTEGER
-- Range:
-- TAN(X) is mathematically unbounded
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function ARCSIN (X : in REAL ) return REAL;
-- Purpose:
-- Returns inverse sine of X
-- Special values:
-- ARCSIN(0.0) = 0.0
-- ARCSIN(1.0) = MATH_PI_OVER_2
-- ARCSIN(-1.0) = -MATH_PI_OVER_2
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- ABS(ARCSIN(X) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCCOS (X : in REAL ) return REAL;
-- Purpose:
-- Returns inverse cosine of X
-- Special values:
-- ARCCOS(1.0) = 0.0
-- ARCCOS(0.0) = MATH_PI_OVER_2
-- ARCCOS(-1.0) = MATH_PI
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- 0.0 <= ARCCOS(X) <= MATH_PI
-- Notes:
-- None
function ARCTAN (Y : in REAL) return REAL;
-- Purpose:
-- Returns the value of the angle in radians of the point
-- (1.0, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0) = 0.0
-- Domain:
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCTAN (Y : in REAL; X : in REAL) return REAL;
-- Purpose:
-- Returns the principal value of the angle in radians of
-- the point (X, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0, X) = 0.0 if X > 0.0
-- ARCTAN(0.0, X) = MATH_PI if X < 0.0
-- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
-- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
-- Domain:
-- Y in REAL
-- X in REAL, X /= 0.0 when Y = 0.0
-- Error conditions:
-- Error if X = 0.0 and Y = 0.0
-- Range:
-- -MATH_PI < ARCTAN(Y,X) <= MATH_PI
-- Notes:
-- None
function SINH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic sine of X
-- Special values:
-- SINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- SINH(X) is mathematically unbounded
-- Notes:
-- a) The usable domain of SINH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function COSH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic cosine of X
-- Special values:
-- COSH(0.0) = 1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- COSH(X) >= 1.0
-- Notes:
-- a) The usable domain of COSH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function TANH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic tangent of X
-- Special values:
-- TANH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(TANH(X)) <= 1.0
-- Notes:
-- None
function ARCSINH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic sine of X
-- Special values:
-- ARCSINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ARCSINH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCSINH is approximately given by:
-- ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
function ARCCOSH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic cosine of X
-- Special values:
-- ARCCOSH(1.0) = 0.0
-- Domain:
-- X >= 1.0
-- Error conditions:
-- Error if X < 1.0
-- Range:
-- ARCCOSH(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of ARCCOSH is
-- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH)
function ARCTANH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic tangent of X
-- Special values:
-- ARCTANH(0.0) = 0.0
-- Domain:
-- ABS(X) < 1.0
-- Error conditions:
-- Error if ABS(X) >= 1.0
-- Range:
-- ARCTANH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCTANH is approximately given by:
-- ABS(ARCTANH(X)) < LOG(REAL'HIGH)
end MATH_REAL;
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_REAL)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package body is a nonnormative implementation of the
-- functionality defined in the MATH_REAL package declaration.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076
-- -1993.
--
-- Notes:
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_REAL.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_REAL package declaration. The purpose of the MATH_REAL
-- package body is to clarify such semantics and provide a
-- guideline for implementations to verify their implementation
-- of MATH_REAL. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
package body MATH_REAL is
--
-- Local Constants for Use in the Package Body Only
--
constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2
constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10
constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi
constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic
constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries
constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria
constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic
--
-- Local Type Declarations for Cordic Operations
--
type REAL_VECTOR is array (NATURAL range <>) of REAL;
type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL;
subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER);
subtype REAL_ARR_2 is REAL_VECTOR (0 to 1);
subtype REAL_ARR_3 is REAL_VECTOR (0 to 2);
subtype QUADRANT is INTEGER range 0 to 3;
type CORDIC_MODE_TYPE is (ROTATION, VECTORING);
--
-- Auxiliary Functions for Cordic Algorithms
--
function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL;
NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is
-- Description:
-- Returns power of two for a vector of values
-- Notes:
-- None
--
variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES);
variable TEMP : REAL := INITIAL_VALUE;
variable FLAG : BOOLEAN := TRUE;
begin
for I in 0 to NUMBER_OF_VALUES loop
V(I) := TEMP;
for P in D'RANGE loop
if I = D(P) then
FLAG := FALSE;
exit;
end if;
end loop;
if FLAG then
TEMP := TEMP/2.0;
end if;
FLAG := TRUE;
end loop;
return V;
end POWER_OF_2_SERIES;
constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES(
NATURAL_VECTOR'(100, 90),1.0,
MAX_ITER);
constant EPSILON : REAL_VECTOR_N := (
7.8539816339744827e-01,
4.6364760900080606e-01,
2.4497866312686413e-01,
1.2435499454676144e-01,
6.2418809995957351e-02,
3.1239833430268277e-02,
1.5623728620476830e-02,
7.8123410601011116e-03,
3.9062301319669717e-03,
1.9531225164788189e-03,
9.7656218955931937e-04,
4.8828121119489829e-04,
2.4414062014936175e-04,
1.2207031189367021e-04,
6.1035156174208768e-05,
3.0517578115526093e-05,
1.5258789061315760e-05,
7.6293945311019699e-06,
3.8146972656064960e-06,
1.9073486328101870e-06,
9.5367431640596080e-07,
4.7683715820308876e-07,
2.3841857910155801e-07,
1.1920928955078067e-07,
5.9604644775390553e-08,
2.9802322387695303e-08,
1.4901161193847654e-08,
7.4505805969238281e-09
);
function CORDIC ( X0 : in REAL;
Y0 : in REAL;
Z0 : in REAL;
N : in NATURAL; -- Precision factor
CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0)
-- or vectoring (Y -> 0)
) return REAL_ARR_3 is
-- Description:
-- Compute cordic values
-- Notes:
-- None
variable X : REAL := X0;
variable Y : REAL := Y0;
variable Z : REAL := Z0;
variable X_TEMP : REAL;
begin
if CORDIC_MODE = ROTATION then
for K in 0 to N loop
X_TEMP := X;
if ( Z >= 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
else
for K in 0 to N loop
X_TEMP := X;
if ( Y < 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
end if;
return REAL_ARR_3'(X, Y, Z);
end CORDIC;
--
-- Bodies for Global Mathematical Functions Start Here
--
function SIGN (X: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
if ( X > 0.0 ) then
return 1.0;
elsif ( X < 0.0 ) then
return -1.0;
else
return 0.0;
end if;
end SIGN;
function CEIL (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is X <= LARGE
-- c) Returns X if ABS(X) >= LARGE
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
begin
if ABS(X) >= LARGE then
return X;
end if;
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
if X > 0.0 then
if RD >= X then
return RD;
else
return RD + 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD <= X then
return RD + 1.0;
else
return RD;
end if;
end if;
end CEIL;
function FLOOR (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is ABS(X) <= LARGE
-- c) Returns X if ABS(X) >= LARGE
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
begin
if ABS( X ) >= LARGE then
return X;
end if;
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
if X > 0.0 then
if RD <= X then
return RD;
else
return RD - 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD >= X then
return RD - 1.0;
else
return RD;
end if;
end if;
end FLOOR;
function ROUND (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X + 0.5) if X > 0
-- c) Returns CEIL(X - 0.5) if X < 0
begin
if X > 0.0 then
return FLOOR(X + 0.5);
elsif X < 0.0 then
return CEIL( X - 0.5);
else
return 0.0;
end if;
end ROUND;
function TRUNC (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X) if X > 0
-- c) Returns CEIL(X) if X < 0
begin
if X > 0.0 then
return FLOOR(X);
elsif X < 0.0 then
return CEIL( X);
else
return 0.0;
end if;
end TRUNC;
function "MOD" (X, Y: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
variable XNEGATIVE : BOOLEAN := X < 0.0;
variable YNEGATIVE : BOOLEAN := Y < 0.0;
variable VALUE : REAL;
begin
-- Check validity of input arguments
if (Y = 0.0) then
assert FALSE
report "MOD(X, 0.0) is undefined"
severity ERROR;
return 0.0;
end if;
-- Compute value
if ( XNEGATIVE ) then
if ( YNEGATIVE ) then
VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
end if;
else
if ( YNEGATIVE ) then
VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
end if;
end if;
return VALUE;
end "MOD";
function REALMAX (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMAX(X,Y) = X when X = Y
--
begin
if X >= Y then
return X;
else
return Y;
end if;
end REALMAX;
function REALMIN (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMIN(X,Y) = X when X = Y
--
begin
if X <= Y then
return X;
else
return Y;
end if;
end REALMIN;
procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL)
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
--
variable Z, K: INTEGER;
variable TSEED1 : INTEGER := INTEGER'(SEED1);
variable TSEED2 : INTEGER := INTEGER'(SEED2);
begin
-- Check validity of arguments
if SEED1 > 2147483562 then
assert FALSE
report "SEED1 > 2147483562 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
if SEED2 > 2147483398 then
assert FALSE
report "SEED2 > 2147483398 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
-- Compute new seed values and pseudo-random number
K := TSEED1/53668;
TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211;
if TSEED1 < 0 then
TSEED1 := TSEED1 + 2147483563;
end if;
K := TSEED2/52774;
TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791;
if TSEED2 < 0 then
TSEED2 := TSEED2 + 2147483399;
end if;
Z := TSEED1 - TSEED2;
if Z < 1 then
Z := Z + 2147483562;
end if;
-- Get output values
SEED1 := POSITIVE'(TSEED1);
SEED2 := POSITIVE'(TSEED2);
X := REAL(Z)*4.656613e-10;
end UNIFORM;
function SQRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = 0.5*[F(n) + x/F(n)]
-- b) Returns 0.0 on error
--
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor
variable INIVAL: REAL;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
begin
-- Check validity of argument
if ( X < 0.0 ) then
assert FALSE
report "X < 0.0 in SQRT(X)"
severity ERROR;
return 0.0;
end if;
-- Get the square root for special cases
if X = 0.0 then
return 0.0;
else
if ( X = 1.0 ) then
return 1.0;
end if;
end if;
-- Get the square root for general cases
INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise
OLDVAL := INIVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
-- Check for relative and absolute error and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT) ) loop
OLDVAL := NEWVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
COUNT := COUNT + 1;
end loop;
return NEWVAL;
end SQRT;
function CBRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2];
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
variable INIVAL: REAL;
variable XLOCAL : REAL := X;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
begin
-- Compute root for special cases
if X = 0.0 then
return 0.0;
elsif ( X = 1.0 ) then
return 1.0;
else
if X = -1.0 then
return -1.0;
end if;
end if;
-- Compute root for general cases
if NEGATIVE then
XLOCAL := -X;
end if;
INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but
-- imprecise
OLDVAL := INIVAL;
NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR
(ABS(NEWVAL - OLDVAL) > EPS ) ) AND
( COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
COUNT := COUNT + 1;
end loop;
if NEGATIVE then
NEWVAL := -NEWVAL;
end if;
return NEWVAL;
end CBRT;
function "**" (X : in INTEGER; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
begin
-- Check validity of argument
if ( ( X < 0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
if ( ( X = 0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
-- Get value for special cases
if ( X = 0 and Y > 0.0 ) then
return 0.0;
end if;
if ( X = 1 ) then
return 1.0;
end if;
if ( Y = 0.0 and X /= 0 ) then
return 1.0;
end if;
if ( Y = 1.0) then
return (REAL(X));
end if;
-- Get value for general case
return EXP (Y * LOG (REAL(X)));
end "**";
function "**" (X : in REAL; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
begin
-- Check validity of argument
if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0.0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0.0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
-- Get value for special cases
if ( X = 0.0 and Y > 0.0 ) then
return 0.0;
end if;
if ( X = 1.0 ) then
return 1.0;
end if;
if ( Y = 0.0 and X /= 0.0 ) then
return 1.0;
end if;
if ( Y = 1.0) then
return (X);
end if;
-- Get value for general case
return EXP (Y * LOG (X));
end "**";
function EXP (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) This function computes the exponential using the following
-- series:
-- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0
-- and reduces argument X to take advantage of exp(x+y) =
-- exp(x)*exp(y)
--
-- b) This implementation limits X to be less than LOG(REAL'HIGH)
-- to avoid overflow. Returns REAL'HIGH when X reaches that
-- limit
--
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria
variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument
variable XLOCAL : REAL := ABS(X); -- Use positive value
variable OLDVAL: REAL ;
variable COUNT: INTEGER ;
variable NEWVAL: REAL ;
variable LAST_TERM: REAL ;
variable FACTOR : REAL := 1.0;
begin
-- Compute value for special cases
if X = 0.0 then
return 1.0;
end if;
if XLOCAL = 1.0 then
if RECIPROCAL then
return MATH_1_OVER_E;
else
return MATH_E;
end if;
end if;
if XLOCAL = 2.0 then
if RECIPROCAL then
return 1.0/MATH_E_P2;
else
return MATH_E_P2;
end if;
end if;
if XLOCAL = 10.0 then
if RECIPROCAL then
return 1.0/MATH_E_P10;
else
return MATH_E_P10;
end if;
end if;
if XLOCAL > LOG(REAL'HIGH) then
if RECIPROCAL then
return 0.0;
else
assert FALSE
report "X > LOG(REAL'HIGH) in EXP(X)"
severity NOTE;
return REAL'HIGH;
end if;
end if;
-- Reduce argument to ABS(X) < 1.0
while XLOCAL > 10.0 loop
XLOCAL := XLOCAL - 10.0;
FACTOR := FACTOR*MATH_E_P10;
end loop;
while XLOCAL > 1.0 loop
XLOCAL := XLOCAL - 1.0;
FACTOR := FACTOR*MATH_E;
end loop;
-- Compute value for case 0 < XLOCAL < 1
OLDVAL := 1.0;
LAST_TERM := XLOCAL;
NEWVAL:= OLDVAL + LAST_TERM;
COUNT := 2;
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT)));
NEWVAL := OLDVAL + LAST_TERM;
COUNT := COUNT + 1;
end loop;
-- Compute final value using exp(x+y) = exp(x)*exp(y)
NEWVAL := NEWVAL*FACTOR;
if RECIPROCAL then
NEWVAL := 1.0/NEWVAL;
end if;
return NEWVAL;
end EXP;
--
-- Auxiliary Functions to Compute LOG
--
function ILOGB(X: in REAL) return INTEGER IS
-- Description:
-- Returns n such that -1 <= ABS(X)/2^n < 2
-- Notes:
-- None
variable N: INTEGER := 0;
variable Y: REAL := ABS(X);
begin
if(Y = 1.0 or Y = 0.0) then
return 0;
end if;
if( Y > 1.0) then
while Y >= 2.0 loop
Y := Y/2.0;
N := N+1;
end loop;
return N;
end if;
-- O < Y < 1
while Y < 1.0 loop
Y := Y*2.0;
N := N -1;
end loop;
return N;
end ILOGB;
function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS
-- Description:
-- Returns X*2^n
-- Notes:
-- None
begin
return X*(2.0 ** N);
end LDEXP;
function LOG (X : in REAL ) return REAL IS
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
--
-- Notes:
-- a) Returns REAL'LOW on error
--
-- Copyright (c) 1992 Regents of the University of California.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. All advertising materials mentioning features or use of this
-- software must display the following acknowledgement:
-- This product includes software developed by the University of
-- California, Berkeley and its contributors.
-- 4. Neither the name of the University nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-- DAMAGE.
--
-- NOTE: This VHDL version was generated using the C version of the
-- original function by the IEEE VHDL Mathematical Package
-- Working Group (CS/JT)
constant N: INTEGER := 128;
-- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128.
-- Used for generation of extend precision logarithms.
-- The constant 35184372088832 is 2^45, so the divide is exact.
-- It ensures correct reading of logF_head, even for inaccurate
-- decimal-to-binary conversion routines. (Everybody gets the
-- right answer for INTEGERs less than 2^53.)
-- Values for LOG(F) were generated using error < 10^-57 absolute
-- with the bc -l package.
type REAL_VECTOR is array (NATURAL range <>) of REAL;
constant A1:REAL := 0.08333333333333178827;
constant A2:REAL := 0.01250000000377174923;
constant A3:REAL := 0.002232139987919447809;
constant A4:REAL := 0.0004348877777076145742;
constant LOGF_HEAD: REAL_VECTOR(0 TO N) := (
0.0,
0.007782140442060381246,
0.015504186535963526694,
0.023167059281547608406,
0.030771658666765233647,
0.038318864302141264488,
0.045809536031242714670,
0.053244514518837604555,
0.060624621816486978786,
0.067950661908525944454,
0.075223421237524235039,
0.082443669210988446138,
0.089612158689760690322,
0.096729626458454731618,
0.103796793681567578460,
0.110814366340264314203,
0.117783035656430001836,
0.124703478501032805070,
0.131576357788617315236,
0.138402322859292326029,
0.145182009844575077295,
0.151916042025732167530,
0.158605030176659056451,
0.165249572895390883786,
0.171850256926518341060,
0.178407657472689606947,
0.184922338493834104156,
0.191394852999565046047,
0.197825743329758552135,
0.204215541428766300668,
0.210564769107350002741,
0.216873938300523150246,
0.223143551314024080056,
0.229374101064877322642,
0.235566071312860003672,
0.241719936886966024758,
0.247836163904594286577,
0.253915209980732470285,
0.259957524436686071567,
0.265963548496984003577,
0.271933715484010463114,
0.277868451003087102435,
0.283768173130738432519,
0.289633292582948342896,
0.295464212893421063199,
0.301261330578199704177,
0.307025035294827830512,
0.312755710004239517729,
0.318453731118097493890,
0.324119468654316733591,
0.329753286372579168528,
0.335355541920762334484,
0.340926586970454081892,
0.346466767346100823488,
0.351976423156884266063,
0.357455888922231679316,
0.362905493689140712376,
0.368325561158599157352,
0.373716409793814818840,
0.379078352934811846353,
0.384411698910298582632,
0.389716751140440464951,
0.394993808240542421117,
0.400243164127459749579,
0.405465108107819105498,
0.410659924985338875558,
0.415827895143593195825,
0.420969294644237379543,
0.426084395310681429691,
0.431173464818130014464,
0.436236766774527495726,
0.441274560805140936281,
0.446287102628048160113,
0.451274644139630254358,
0.456237433481874177232,
0.461175715122408291790,
0.466089729924533457960,
0.470979715219073113985,
0.475845904869856894947,
0.480688529345570714212,
0.485507815781602403149,
0.490303988045525329653,
0.495077266798034543171,
0.499827869556611403822,
0.504556010751912253908,
0.509261901790523552335,
0.513945751101346104405,
0.518607764208354637958,
0.523248143765158602036,
0.527867089620485785417,
0.532464798869114019908,
0.537041465897345915436,
0.541597282432121573947,
0.546132437597407260909,
0.550647117952394182793,
0.555141507540611200965,
0.559615787935399566777,
0.564070138285387656651,
0.568504735352689749561,
0.572919753562018740922,
0.577315365035246941260,
0.581691739635061821900,
0.586049045003164792433,
0.590387446602107957005,
0.594707107746216934174,
0.599008189645246602594,
0.603290851438941899687,
0.607555250224322662688,
0.611801541106615331955,
0.616029877215623855590,
0.620240409751204424537,
0.624433288012369303032,
0.628608659422752680256,
0.632766669570628437213,
0.636907462236194987781,
0.641031179420679109171,
0.645137961373620782978,
0.649227946625615004450,
0.653301272011958644725,
0.657358072709030238911,
0.661398482245203922502,
0.665422632544505177065,
0.669430653942981734871,
0.673422675212350441142,
0.677398823590920073911,
0.681359224807238206267,
0.685304003098281100392,
0.689233281238557538017,
0.693147180560117703862);
constant LOGF_TAIL: REAL_VECTOR(0 TO N) := (
0.0,
-0.00000000000000543229938420049,
0.00000000000000172745674997061,
-0.00000000000001323017818229233,
-0.00000000000001154527628289872,
-0.00000000000000466529469958300,
0.00000000000005148849572685810,
-0.00000000000002532168943117445,
-0.00000000000005213620639136504,
-0.00000000000001819506003016881,
0.00000000000006329065958724544,
0.00000000000008614512936087814,
-0.00000000000007355770219435028,
0.00000000000009638067658552277,
0.00000000000007598636597194141,
0.00000000000002579999128306990,
-0.00000000000004654729747598444,
-0.00000000000007556920687451336,
0.00000000000010195735223708472,
-0.00000000000017319034406422306,
-0.00000000000007718001336828098,
0.00000000000010980754099855238,
-0.00000000000002047235780046195,
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variable M, J:INTEGER;
variable F1, F2, G, Q, U, U2, V: REAL;
variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs
variable ONE: REAL := 1.0; --Made variable so no constant folding occurs
-- double logb(), ldexp();
variable U1:REAL;
begin
-- Check validity of argument
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = MATH_E ) then
return 1.0;
end if;
-- Argument reduction: 1 <= g < 2; x/2^m = g;
-- y = F*(1 + f/F) for |f| <= 2^-8
M := ILOGB(X);
G := LDEXP(X, -M);
J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding
F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512]
F2 := G - F1;
-- Approximate expansion for log(1+f2/F1) ~= u + q
G := 1.0/(2.0*F1+F2);
U := 2.0*F2*G;
V := U*U;
Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4)));
-- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8,
-- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits.
-- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750.
--
if ( J /= 0 or M /= 0) then
U1 := U + 513.0;
U1 := U1 - 513.0;
-- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero
-- u1 = u to 24 bits.
--
else
U1 := U;
--TRUNC(U1); --In c this is u1 = (double) (float) (u1)
end if;
U2 := (2.0*(F2 - F1*U1) - U1*F2) * G;
-- u1 + u2 = 2f/(2F+f) to extra precision.
-- log(x) = log(2^m*F1*(1+f2/F1)) =
-- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q);
-- (exact) + (tiny)
U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact
U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny
U2 := U2 + LOGF_TAIL(N)*REAL(M);
return (U1 + U2);
end LOG;
function LOG2 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG2(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = 2.0 ) then
return 1.0;
end if;
-- Compute value for general case
return ( MATH_LOG2_OF_E*LOG(X) );
end LOG2;
function LOG10 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG10(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = 10.0 ) then
return 1.0;
end if;
-- Compute value for general case
return ( MATH_LOG10_OF_E*LOG(X) );
end LOG10;
function LOG (X: in REAL; BASE: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = BASE ) then
return 1.0;
end if;
-- Compute value for general case
return ( LOG(X)/LOG(BASE));
end LOG;
function SIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) SIN(-X) = -SIN(X)
-- b) SIN(X) = X if ABS(X) < EPS
-- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS
-- d) SIN(MATH_PI_OVER_2 - X) = COS(X)
-- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS
-- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence criteria
variable N : INTEGER;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in SIN(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then
return 0.0;
end if;
if XLOCAL = MATH_PI_OVER_2 then
if NEGATIVE then
return -1.0;
else
return 1.0;
end if;
end if;
if XLOCAL = MATH_3_PI_OVER_2 then
if NEGATIVE then
return 1.0;
else
return -1.0;
end if;
end if;
if XLOCAL < EPS then
if NEGATIVE then
return -XLOCAL;
else
return XLOCAL;
end if;
else
if XLOCAL < BASE_EPS then
TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := MATH_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := MATH_2_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
TEMP := ABS(MATH_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
-- Compute value for general cases
if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then
VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1);
end if;
N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2));
case QUADRANT( N mod 4) is
when 0 =>
VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1);
when 1 =>
VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27,
ROTATION)(0);
when 2 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1);
when 3 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27,
ROTATION)(0);
end case;
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end SIN;
function COS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) COS(-X) = COS(X)
-- b) COS(X) = SIN(MATH_PI_OVER_2 - X)
-- c) COS(MATH_PI + X) = -COS(X)
-- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS
-- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
variable XLOCAL : REAL := ABS(X);
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in COS(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then
return 1.0;
end if;
if XLOCAL = MATH_PI then
return -1.0;
end if;
if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then
return 0.0;
end if;
TEMP := ABS(XLOCAL);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
TEMP := ABS(XLOCAL -MATH_2_PI);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
TEMP := ABS (XLOCAL - MATH_PI);
if TEMP < EPS then
return (-1.0 + 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
-- Compute value for general cases
return SIN(MATH_PI_OVER_2 - XLOCAL);
end COS;
function TAN (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) TAN(0.0) = 0.0
-- b) TAN(-X) = -TAN(X)
-- c) Returns REAL'LOW on error if X < 0.0
-- d) Returns REAL'HIGH on error if X > 0.0
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make 0.0 <= XLOCAL <= MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in TAN(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Check validity of argument
if XLOCAL = MATH_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'LOW);
else
return(REAL'HIGH);
end if;
end if;
if XLOCAL = MATH_3_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'HIGH);
else
return(REAL'LOW);
end if;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_PI then
return 0.0;
end if;
-- Compute value for general cases
VALUE := SIN(XLOCAL)/COS(XLOCAL);
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end TAN;
function ARCSIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCSIN(-X) = -ARCSIN(X)
-- b) Returns X on error
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
begin
-- Check validity of arguments
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCSIN(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
elsif XLOCAL = 1.0 then
if NEGATIVE then
return -MATH_PI_OVER_2;
else
return MATH_PI_OVER_2;
end if;
end if;
-- Compute value for general cases
if XLOCAL < 0.9 then
VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL)));
else
VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
end if;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end ARCSIN;
function ARCCOS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCCOS(-X) = MATH_PI - ARCCOS(X)
-- b) Returns X on error
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
begin
-- Check validity of argument
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCCOS(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 1.0 then
return 0.0;
elsif X = 0.0 then
return MATH_PI_OVER_2;
elsif X = -1.0 then
return MATH_PI;
end if;
-- Compute value for general cases
if XLOCAL > 0.9 then
VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
else
VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL));
end if;
if NEGATIVE then
VALUE := MATH_PI - VALUE;
end if;
return VALUE;
end ARCCOS;
function ARCTAN (Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCTAN(-Y) = -ARCTAN(Y)
-- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0
-- c) ARCTAN(Y) = Y for |Y| < EPS
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;
variable NEGATIVE : BOOLEAN := Y < 0.0;
variable RECIPROCAL : BOOLEAN;
variable YLOCAL : REAL := ABS(Y);
variable VALUE : REAL;
begin
-- Make argument |Y| <=1.0
if YLOCAL > 1.0 then
YLOCAL := 1.0/YLOCAL;
RECIPROCAL := TRUE;
else
RECIPROCAL := FALSE;
end if;
-- Compute value for special cases
if YLOCAL = 0.0 then
if RECIPROCAL then
if NEGATIVE then
return (-MATH_PI_OVER_2);
else
return (MATH_PI_OVER_2);
end if;
else
return 0.0;
end if;
end if;
if YLOCAL < EPS then
if NEGATIVE then
if RECIPROCAL then
return (-MATH_PI_OVER_2 + YLOCAL);
else
return -YLOCAL;
end if;
else
if RECIPROCAL then
return (MATH_PI_OVER_2 - YLOCAL);
else
return YLOCAL;
end if;
end if;
end if;
-- Compute value for general cases
VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2);
if RECIPROCAL then
VALUE := MATH_PI_OVER_2 - VALUE;
end if;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end ARCTAN;
function ARCTAN (Y : in REAL; X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
variable YLOCAL : REAL;
variable VALUE : REAL;
begin
-- Check validity of arguments
if (Y = 0.0 and X = 0.0 ) then
assert FALSE report
"ARCTAN(0.0, 0.0) is undetermined"
severity ERROR;
return 0.0;
end if;
-- Compute value for special cases
if Y = 0.0 then
if X > 0.0 then
return 0.0;
else
return MATH_PI;
end if;
end if;
if X = 0.0 then
if Y > 0.0 then
return MATH_PI_OVER_2;
else
return -MATH_PI_OVER_2;
end if;
end if;
-- Compute value for general cases
YLOCAL := ABS(Y/X);
VALUE := ARCTAN(YLOCAL);
if X < 0.0 then
VALUE := MATH_PI - VALUE;
end if;
if Y < 0.0 then
VALUE := -VALUE;
end if;
return VALUE;
end ARCTAN;
function SINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/2.0
-- b) SINH(-X) = SINH(X)
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)*0.5;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end SINH;
function COSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) + EXP(-X))/2.0
-- b) COSH(-X) = COSH(X)
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 1.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP + 1.0/TEMP)*0.5;
return VALUE;
end COSH;
function TANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X))
-- b) TANH(-X) = -TANH(X)
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP);
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end TANH;
function ARCSINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X + 1.0))
begin
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
return ( LOG( X + SQRT( X*X + 1.0)) );
end ARCSINH;
function ARCCOSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0
-- b) Returns X on error
begin
-- Check validity of arguments
if X < 1.0 then
assert FALSE
report "X < 1.0 in ARCCOSH(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 1.0 then
return 0.0;
end if;
-- Compute value for general cases
return ( LOG( X + SQRT( X*X - 1.0)));
end ARCCOSH;
function ARCTANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0
-- b) Returns X on error
begin
-- Check validity of arguments
if ABS(X) >= 1.0 then
assert FALSE
report "ABS(X) >= 1.0 in ARCTANH(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
return( 0.5*LOG( (1.0+X)/(1.0-X) ) );
end ARCTANH;
end MATH_REAL;
|
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_REAL)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package defines a standard for designers to use in
-- describing VHDL models that make use of common REAL constants
-- and common REAL elementary mathematical functions.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076-
-- 1993.
--
-- Notes:
-- No declarations or definitions shall be included in, or
-- excluded from, this package.
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_REAL.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_REAL package declaration. The purpose of the MATH_REAL
-- package body is to provide a guideline for implementations to
-- verify their implementation of MATH_REAL. Tool developers may
-- choose to implement the package body in the most efficient
-- manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
package MATH_REAL is
constant CopyRightNotice: STRING
:= "Copyright 1996 IEEE. All rights reserved.";
--
-- Constant Definitions
--
constant MATH_E : REAL := 2.71828_18284_59045_23536;
-- Value of e
constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
-- Value of 1/e
constant MATH_PI : REAL := 3.14159_26535_89793_23846;
-- Value of pi
constant MATH_2_PI : REAL := 6.28318_53071_79586_47693;
-- Value of 2*pi
constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
-- Value of 1/pi
constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
-- Value of pi/2
constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
-- Value of pi/3
constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
-- Value of pi/4
constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
-- Value 3*pi/2
constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
-- Natural log of 2
constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
-- Natural log of 10
constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
-- Log base 2 of e
constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765;
-- Log base 10 of e
constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880;
-- square root of 2
constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440;
-- square root of 1/2
constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730;
-- square root of pi
constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577;
-- Conversion factor from degree to radian
constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680;
-- Conversion factor from radian to degree
--
-- Function Declarations
--
function SIGN (X: in REAL ) return REAL;
-- Purpose:
-- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIGN(X)) <= 1.0
-- Notes:
-- None
function CEIL (X : in REAL ) return REAL;
-- Purpose:
-- Returns smallest INTEGER value (as REAL) not less than X
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CEIL(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function FLOOR (X : in REAL ) return REAL;
-- Purpose:
-- Returns largest INTEGER value (as REAL) not greater than X
-- Special values:
-- FLOOR(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- FLOOR(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function ROUND (X : in REAL ) return REAL;
-- Purpose:
-- Rounds X to the nearest integer value (as real). If X is
-- halfway between two integers, rounding is away from 0.0
-- Special values:
-- ROUND(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ROUND(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function TRUNC (X : in REAL ) return REAL;
-- Purpose:
-- Truncates X towards 0.0 and returns truncated value
-- Special values:
-- TRUNC(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- TRUNC(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function "MOD" (X, Y: in REAL ) return REAL;
-- Purpose:
-- Returns floating point modulus of X/Y, with the same sign as
-- Y, and absolute value less than the absolute value of Y, and
-- for some INTEGER value N the result satisfies the relation
-- X = Y*N + MOD(X,Y)
-- Special values:
-- None
-- Domain:
-- X in REAL; Y in REAL and Y /= 0.0
-- Error conditions:
-- Error if Y = 0.0
-- Range:
-- ABS(MOD(X,Y)) < ABS(Y)
-- Notes:
-- None
function REALMAX (X, Y : in REAL ) return REAL;
-- Purpose:
-- Returns the algebraically larger of X and Y
-- Special values:
-- REALMAX(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMAX(X,Y) is mathematically unbounded
-- Notes:
-- None
function REALMIN (X, Y : in REAL ) return REAL;
-- Purpose:
-- Returns the algebraically smaller of X and Y
-- Special values:
-- REALMIN(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMIN(X,Y) is mathematically unbounded
-- Notes:
-- None
procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL);
-- Purpose:
-- Returns, in X, a pseudo-random number with uniform
-- distribution in the open interval (0.0, 1.0).
-- Special values:
-- None
-- Domain:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
-- Error conditions:
-- Error if SEED1 or SEED2 outside of valid domain
-- Range:
-- 0.0 < X < 1.0
-- Notes:
-- a) The semantics for this function are described by the
-- algorithm published by Pierre L'Ecuyer in "Communications
-- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
-- The algorithm is based on the combination of two
-- multiplicative linear congruential generators for 32-bit
-- platforms.
--
-- b) Before the first call to UNIFORM, the seed values
-- (SEED1, SEED2) have to be initialized to values in the range
-- [1, 2147483562] and [1, 2147483398] respectively. The
-- seed values are modified after each call to UNIFORM.
--
-- c) This random number generator is portable for 32-bit
-- computers, and it has a period of ~2.30584*(10**18) for each
-- set of seed values.
--
-- d) For information on spectral tests for the algorithm, refer
-- to the L'Ecuyer article.
function SQRT (X : in REAL ) return REAL;
-- Purpose:
-- Returns square root of X
-- Special values:
-- SQRT(0.0) = 0.0
-- SQRT(1.0) = 1.0
-- Domain:
-- X >= 0.0
-- Error conditions:
-- Error if X < 0.0
-- Range:
-- SQRT(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of SQRT is
-- approximately given by:
-- SQRT(X) <= SQRT(REAL'HIGH)
function CBRT (X : in REAL ) return REAL;
-- Purpose:
-- Returns cube root of X
-- Special values:
-- CBRT(0.0) = 0.0
-- CBRT(1.0) = 1.0
-- CBRT(-1.0) = -1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CBRT(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of CBRT is approximately given by:
-- ABS(CBRT(X)) <= CBRT(REAL'HIGH)
function "**" (X : in INTEGER; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0
-- 0**Y = 0.0; Y > 0.0
-- X**1.0 = REAL(X); X >= 0
-- 1**Y = 1.0
-- Domain:
-- X > 0
-- X = 0 for Y > 0.0
-- X < 0 for Y = 0.0
-- Error conditions:
-- Error if X < 0 and Y /= 0.0
-- Error if X = 0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function "**" (X : in REAL; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0.0
-- 0.0**Y = 0.0; Y > 0.0
-- X**1.0 = X; X >= 0.0
-- 1.0**Y = 1.0
-- Domain:
-- X > 0.0
-- X = 0.0 for Y > 0.0
-- X < 0.0 for Y = 0.0
-- Error conditions:
-- Error if X < 0.0 and Y /= 0.0
-- Error if X = 0.0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function EXP (X : in REAL ) return REAL;
-- Purpose:
-- Returns e**X; where e = MATH_E
-- Special values:
-- EXP(0.0) = 1.0
-- EXP(1.0) = MATH_E
-- EXP(-1.0) = MATH_1_OVER_E
-- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
-- Domain:
-- X in REAL such that EXP(X) <= REAL'HIGH
-- Error conditions:
-- Error if X > LOG(REAL'HIGH)
-- Range:
-- EXP(X) >= 0.0
-- Notes:
-- a) The usable domain of EXP is approximately given by:
-- X <= LOG(REAL'HIGH)
function LOG (X : in REAL ) return REAL;
-- Purpose:
-- Returns natural logarithm of X
-- Special values:
-- LOG(1.0) = 0.0
-- LOG(MATH_E) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG is approximately given by:
-- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
function LOG2 (X : in REAL ) return REAL;
-- Purpose:
-- Returns logarithm base 2 of X
-- Special values:
-- LOG2(1.0) = 0.0
-- LOG2(2.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG2(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG2 is approximately given by:
-- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
function LOG10 (X : in REAL ) return REAL;
-- Purpose:
-- Returns logarithm base 10 of X
-- Special values:
-- LOG10(1.0) = 0.0
-- LOG10(10.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG10(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG10 is approximately given by:
-- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
function LOG (X: in REAL; BASE: in REAL) return REAL;
-- Purpose:
-- Returns logarithm base BASE of X
-- Special values:
-- LOG(1.0, BASE) = 0.0
-- LOG(BASE, BASE) = 1.0
-- Domain:
-- X > 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if X <= 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(X, BASE) is mathematically unbounded
-- Notes:
-- a) When BASE > 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
-- b) When 0.0 < BASE < 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
function SIN (X : in REAL ) return REAL;
-- Purpose:
-- Returns sine of X; X in radians
-- Special values:
-- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function COS ( X : in REAL ) return REAL;
-- Purpose:
-- Returns cosine of X; X in radians
-- Special values:
-- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
-- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(COS(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function TAN (X : in REAL ) return REAL;
-- Purpose:
-- Returns tangent of X; X in radians
-- Special values:
-- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL and
-- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
-- Error conditions:
-- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
-- INTEGER
-- Range:
-- TAN(X) is mathematically unbounded
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function ARCSIN (X : in REAL ) return REAL;
-- Purpose:
-- Returns inverse sine of X
-- Special values:
-- ARCSIN(0.0) = 0.0
-- ARCSIN(1.0) = MATH_PI_OVER_2
-- ARCSIN(-1.0) = -MATH_PI_OVER_2
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- ABS(ARCSIN(X) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCCOS (X : in REAL ) return REAL;
-- Purpose:
-- Returns inverse cosine of X
-- Special values:
-- ARCCOS(1.0) = 0.0
-- ARCCOS(0.0) = MATH_PI_OVER_2
-- ARCCOS(-1.0) = MATH_PI
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- 0.0 <= ARCCOS(X) <= MATH_PI
-- Notes:
-- None
function ARCTAN (Y : in REAL) return REAL;
-- Purpose:
-- Returns the value of the angle in radians of the point
-- (1.0, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0) = 0.0
-- Domain:
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCTAN (Y : in REAL; X : in REAL) return REAL;
-- Purpose:
-- Returns the principal value of the angle in radians of
-- the point (X, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0, X) = 0.0 if X > 0.0
-- ARCTAN(0.0, X) = MATH_PI if X < 0.0
-- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
-- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
-- Domain:
-- Y in REAL
-- X in REAL, X /= 0.0 when Y = 0.0
-- Error conditions:
-- Error if X = 0.0 and Y = 0.0
-- Range:
-- -MATH_PI < ARCTAN(Y,X) <= MATH_PI
-- Notes:
-- None
function SINH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic sine of X
-- Special values:
-- SINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- SINH(X) is mathematically unbounded
-- Notes:
-- a) The usable domain of SINH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function COSH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic cosine of X
-- Special values:
-- COSH(0.0) = 1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- COSH(X) >= 1.0
-- Notes:
-- a) The usable domain of COSH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function TANH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic tangent of X
-- Special values:
-- TANH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(TANH(X)) <= 1.0
-- Notes:
-- None
function ARCSINH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic sine of X
-- Special values:
-- ARCSINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ARCSINH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCSINH is approximately given by:
-- ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
function ARCCOSH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic cosine of X
-- Special values:
-- ARCCOSH(1.0) = 0.0
-- Domain:
-- X >= 1.0
-- Error conditions:
-- Error if X < 1.0
-- Range:
-- ARCCOSH(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of ARCCOSH is
-- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH)
function ARCTANH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic tangent of X
-- Special values:
-- ARCTANH(0.0) = 0.0
-- Domain:
-- ABS(X) < 1.0
-- Error conditions:
-- Error if ABS(X) >= 1.0
-- Range:
-- ARCTANH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCTANH is approximately given by:
-- ABS(ARCTANH(X)) < LOG(REAL'HIGH)
end MATH_REAL;
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_REAL)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package body is a nonnormative implementation of the
-- functionality defined in the MATH_REAL package declaration.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076
-- -1993.
--
-- Notes:
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_REAL.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_REAL package declaration. The purpose of the MATH_REAL
-- package body is to clarify such semantics and provide a
-- guideline for implementations to verify their implementation
-- of MATH_REAL. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
package body MATH_REAL is
--
-- Local Constants for Use in the Package Body Only
--
constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2
constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10
constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi
constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic
constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries
constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria
constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic
--
-- Local Type Declarations for Cordic Operations
--
type REAL_VECTOR is array (NATURAL range <>) of REAL;
type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL;
subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER);
subtype REAL_ARR_2 is REAL_VECTOR (0 to 1);
subtype REAL_ARR_3 is REAL_VECTOR (0 to 2);
subtype QUADRANT is INTEGER range 0 to 3;
type CORDIC_MODE_TYPE is (ROTATION, VECTORING);
--
-- Auxiliary Functions for Cordic Algorithms
--
function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL;
NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is
-- Description:
-- Returns power of two for a vector of values
-- Notes:
-- None
--
variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES);
variable TEMP : REAL := INITIAL_VALUE;
variable FLAG : BOOLEAN := TRUE;
begin
for I in 0 to NUMBER_OF_VALUES loop
V(I) := TEMP;
for P in D'RANGE loop
if I = D(P) then
FLAG := FALSE;
exit;
end if;
end loop;
if FLAG then
TEMP := TEMP/2.0;
end if;
FLAG := TRUE;
end loop;
return V;
end POWER_OF_2_SERIES;
constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES(
NATURAL_VECTOR'(100, 90),1.0,
MAX_ITER);
constant EPSILON : REAL_VECTOR_N := (
7.8539816339744827e-01,
4.6364760900080606e-01,
2.4497866312686413e-01,
1.2435499454676144e-01,
6.2418809995957351e-02,
3.1239833430268277e-02,
1.5623728620476830e-02,
7.8123410601011116e-03,
3.9062301319669717e-03,
1.9531225164788189e-03,
9.7656218955931937e-04,
4.8828121119489829e-04,
2.4414062014936175e-04,
1.2207031189367021e-04,
6.1035156174208768e-05,
3.0517578115526093e-05,
1.5258789061315760e-05,
7.6293945311019699e-06,
3.8146972656064960e-06,
1.9073486328101870e-06,
9.5367431640596080e-07,
4.7683715820308876e-07,
2.3841857910155801e-07,
1.1920928955078067e-07,
5.9604644775390553e-08,
2.9802322387695303e-08,
1.4901161193847654e-08,
7.4505805969238281e-09
);
function CORDIC ( X0 : in REAL;
Y0 : in REAL;
Z0 : in REAL;
N : in NATURAL; -- Precision factor
CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0)
-- or vectoring (Y -> 0)
) return REAL_ARR_3 is
-- Description:
-- Compute cordic values
-- Notes:
-- None
variable X : REAL := X0;
variable Y : REAL := Y0;
variable Z : REAL := Z0;
variable X_TEMP : REAL;
begin
if CORDIC_MODE = ROTATION then
for K in 0 to N loop
X_TEMP := X;
if ( Z >= 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
else
for K in 0 to N loop
X_TEMP := X;
if ( Y < 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
end if;
return REAL_ARR_3'(X, Y, Z);
end CORDIC;
--
-- Bodies for Global Mathematical Functions Start Here
--
function SIGN (X: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
if ( X > 0.0 ) then
return 1.0;
elsif ( X < 0.0 ) then
return -1.0;
else
return 0.0;
end if;
end SIGN;
function CEIL (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is X <= LARGE
-- c) Returns X if ABS(X) >= LARGE
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
begin
if ABS(X) >= LARGE then
return X;
end if;
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
if X > 0.0 then
if RD >= X then
return RD;
else
return RD + 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD <= X then
return RD + 1.0;
else
return RD;
end if;
end if;
end CEIL;
function FLOOR (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is ABS(X) <= LARGE
-- c) Returns X if ABS(X) >= LARGE
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
begin
if ABS( X ) >= LARGE then
return X;
end if;
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
if X > 0.0 then
if RD <= X then
return RD;
else
return RD - 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD >= X then
return RD - 1.0;
else
return RD;
end if;
end if;
end FLOOR;
function ROUND (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X + 0.5) if X > 0
-- c) Returns CEIL(X - 0.5) if X < 0
begin
if X > 0.0 then
return FLOOR(X + 0.5);
elsif X < 0.0 then
return CEIL( X - 0.5);
else
return 0.0;
end if;
end ROUND;
function TRUNC (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X) if X > 0
-- c) Returns CEIL(X) if X < 0
begin
if X > 0.0 then
return FLOOR(X);
elsif X < 0.0 then
return CEIL( X);
else
return 0.0;
end if;
end TRUNC;
function "MOD" (X, Y: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
variable XNEGATIVE : BOOLEAN := X < 0.0;
variable YNEGATIVE : BOOLEAN := Y < 0.0;
variable VALUE : REAL;
begin
-- Check validity of input arguments
if (Y = 0.0) then
assert FALSE
report "MOD(X, 0.0) is undefined"
severity ERROR;
return 0.0;
end if;
-- Compute value
if ( XNEGATIVE ) then
if ( YNEGATIVE ) then
VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
end if;
else
if ( YNEGATIVE ) then
VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
end if;
end if;
return VALUE;
end "MOD";
function REALMAX (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMAX(X,Y) = X when X = Y
--
begin
if X >= Y then
return X;
else
return Y;
end if;
end REALMAX;
function REALMIN (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMIN(X,Y) = X when X = Y
--
begin
if X <= Y then
return X;
else
return Y;
end if;
end REALMIN;
procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL)
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
--
variable Z, K: INTEGER;
variable TSEED1 : INTEGER := INTEGER'(SEED1);
variable TSEED2 : INTEGER := INTEGER'(SEED2);
begin
-- Check validity of arguments
if SEED1 > 2147483562 then
assert FALSE
report "SEED1 > 2147483562 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
if SEED2 > 2147483398 then
assert FALSE
report "SEED2 > 2147483398 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
-- Compute new seed values and pseudo-random number
K := TSEED1/53668;
TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211;
if TSEED1 < 0 then
TSEED1 := TSEED1 + 2147483563;
end if;
K := TSEED2/52774;
TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791;
if TSEED2 < 0 then
TSEED2 := TSEED2 + 2147483399;
end if;
Z := TSEED1 - TSEED2;
if Z < 1 then
Z := Z + 2147483562;
end if;
-- Get output values
SEED1 := POSITIVE'(TSEED1);
SEED2 := POSITIVE'(TSEED2);
X := REAL(Z)*4.656613e-10;
end UNIFORM;
function SQRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = 0.5*[F(n) + x/F(n)]
-- b) Returns 0.0 on error
--
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor
variable INIVAL: REAL;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
begin
-- Check validity of argument
if ( X < 0.0 ) then
assert FALSE
report "X < 0.0 in SQRT(X)"
severity ERROR;
return 0.0;
end if;
-- Get the square root for special cases
if X = 0.0 then
return 0.0;
else
if ( X = 1.0 ) then
return 1.0;
end if;
end if;
-- Get the square root for general cases
INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise
OLDVAL := INIVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
-- Check for relative and absolute error and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT) ) loop
OLDVAL := NEWVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
COUNT := COUNT + 1;
end loop;
return NEWVAL;
end SQRT;
function CBRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2];
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
variable INIVAL: REAL;
variable XLOCAL : REAL := X;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
begin
-- Compute root for special cases
if X = 0.0 then
return 0.0;
elsif ( X = 1.0 ) then
return 1.0;
else
if X = -1.0 then
return -1.0;
end if;
end if;
-- Compute root for general cases
if NEGATIVE then
XLOCAL := -X;
end if;
INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but
-- imprecise
OLDVAL := INIVAL;
NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR
(ABS(NEWVAL - OLDVAL) > EPS ) ) AND
( COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
COUNT := COUNT + 1;
end loop;
if NEGATIVE then
NEWVAL := -NEWVAL;
end if;
return NEWVAL;
end CBRT;
function "**" (X : in INTEGER; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
begin
-- Check validity of argument
if ( ( X < 0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
if ( ( X = 0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
-- Get value for special cases
if ( X = 0 and Y > 0.0 ) then
return 0.0;
end if;
if ( X = 1 ) then
return 1.0;
end if;
if ( Y = 0.0 and X /= 0 ) then
return 1.0;
end if;
if ( Y = 1.0) then
return (REAL(X));
end if;
-- Get value for general case
return EXP (Y * LOG (REAL(X)));
end "**";
function "**" (X : in REAL; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
begin
-- Check validity of argument
if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0.0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0.0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
-- Get value for special cases
if ( X = 0.0 and Y > 0.0 ) then
return 0.0;
end if;
if ( X = 1.0 ) then
return 1.0;
end if;
if ( Y = 0.0 and X /= 0.0 ) then
return 1.0;
end if;
if ( Y = 1.0) then
return (X);
end if;
-- Get value for general case
return EXP (Y * LOG (X));
end "**";
function EXP (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) This function computes the exponential using the following
-- series:
-- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0
-- and reduces argument X to take advantage of exp(x+y) =
-- exp(x)*exp(y)
--
-- b) This implementation limits X to be less than LOG(REAL'HIGH)
-- to avoid overflow. Returns REAL'HIGH when X reaches that
-- limit
--
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria
variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument
variable XLOCAL : REAL := ABS(X); -- Use positive value
variable OLDVAL: REAL ;
variable COUNT: INTEGER ;
variable NEWVAL: REAL ;
variable LAST_TERM: REAL ;
variable FACTOR : REAL := 1.0;
begin
-- Compute value for special cases
if X = 0.0 then
return 1.0;
end if;
if XLOCAL = 1.0 then
if RECIPROCAL then
return MATH_1_OVER_E;
else
return MATH_E;
end if;
end if;
if XLOCAL = 2.0 then
if RECIPROCAL then
return 1.0/MATH_E_P2;
else
return MATH_E_P2;
end if;
end if;
if XLOCAL = 10.0 then
if RECIPROCAL then
return 1.0/MATH_E_P10;
else
return MATH_E_P10;
end if;
end if;
if XLOCAL > LOG(REAL'HIGH) then
if RECIPROCAL then
return 0.0;
else
assert FALSE
report "X > LOG(REAL'HIGH) in EXP(X)"
severity NOTE;
return REAL'HIGH;
end if;
end if;
-- Reduce argument to ABS(X) < 1.0
while XLOCAL > 10.0 loop
XLOCAL := XLOCAL - 10.0;
FACTOR := FACTOR*MATH_E_P10;
end loop;
while XLOCAL > 1.0 loop
XLOCAL := XLOCAL - 1.0;
FACTOR := FACTOR*MATH_E;
end loop;
-- Compute value for case 0 < XLOCAL < 1
OLDVAL := 1.0;
LAST_TERM := XLOCAL;
NEWVAL:= OLDVAL + LAST_TERM;
COUNT := 2;
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT)));
NEWVAL := OLDVAL + LAST_TERM;
COUNT := COUNT + 1;
end loop;
-- Compute final value using exp(x+y) = exp(x)*exp(y)
NEWVAL := NEWVAL*FACTOR;
if RECIPROCAL then
NEWVAL := 1.0/NEWVAL;
end if;
return NEWVAL;
end EXP;
--
-- Auxiliary Functions to Compute LOG
--
function ILOGB(X: in REAL) return INTEGER IS
-- Description:
-- Returns n such that -1 <= ABS(X)/2^n < 2
-- Notes:
-- None
variable N: INTEGER := 0;
variable Y: REAL := ABS(X);
begin
if(Y = 1.0 or Y = 0.0) then
return 0;
end if;
if( Y > 1.0) then
while Y >= 2.0 loop
Y := Y/2.0;
N := N+1;
end loop;
return N;
end if;
-- O < Y < 1
while Y < 1.0 loop
Y := Y*2.0;
N := N -1;
end loop;
return N;
end ILOGB;
function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS
-- Description:
-- Returns X*2^n
-- Notes:
-- None
begin
return X*(2.0 ** N);
end LDEXP;
function LOG (X : in REAL ) return REAL IS
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
--
-- Notes:
-- a) Returns REAL'LOW on error
--
-- Copyright (c) 1992 Regents of the University of California.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. All advertising materials mentioning features or use of this
-- software must display the following acknowledgement:
-- This product includes software developed by the University of
-- California, Berkeley and its contributors.
-- 4. Neither the name of the University nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-- DAMAGE.
--
-- NOTE: This VHDL version was generated using the C version of the
-- original function by the IEEE VHDL Mathematical Package
-- Working Group (CS/JT)
constant N: INTEGER := 128;
-- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128.
-- Used for generation of extend precision logarithms.
-- The constant 35184372088832 is 2^45, so the divide is exact.
-- It ensures correct reading of logF_head, even for inaccurate
-- decimal-to-binary conversion routines. (Everybody gets the
-- right answer for INTEGERs less than 2^53.)
-- Values for LOG(F) were generated using error < 10^-57 absolute
-- with the bc -l package.
type REAL_VECTOR is array (NATURAL range <>) of REAL;
constant A1:REAL := 0.08333333333333178827;
constant A2:REAL := 0.01250000000377174923;
constant A3:REAL := 0.002232139987919447809;
constant A4:REAL := 0.0004348877777076145742;
constant LOGF_HEAD: REAL_VECTOR(0 TO N) := (
0.0,
0.007782140442060381246,
0.015504186535963526694,
0.023167059281547608406,
0.030771658666765233647,
0.038318864302141264488,
0.045809536031242714670,
0.053244514518837604555,
0.060624621816486978786,
0.067950661908525944454,
0.075223421237524235039,
0.082443669210988446138,
0.089612158689760690322,
0.096729626458454731618,
0.103796793681567578460,
0.110814366340264314203,
0.117783035656430001836,
0.124703478501032805070,
0.131576357788617315236,
0.138402322859292326029,
0.145182009844575077295,
0.151916042025732167530,
0.158605030176659056451,
0.165249572895390883786,
0.171850256926518341060,
0.178407657472689606947,
0.184922338493834104156,
0.191394852999565046047,
0.197825743329758552135,
0.204215541428766300668,
0.210564769107350002741,
0.216873938300523150246,
0.223143551314024080056,
0.229374101064877322642,
0.235566071312860003672,
0.241719936886966024758,
0.247836163904594286577,
0.253915209980732470285,
0.259957524436686071567,
0.265963548496984003577,
0.271933715484010463114,
0.277868451003087102435,
0.283768173130738432519,
0.289633292582948342896,
0.295464212893421063199,
0.301261330578199704177,
0.307025035294827830512,
0.312755710004239517729,
0.318453731118097493890,
0.324119468654316733591,
0.329753286372579168528,
0.335355541920762334484,
0.340926586970454081892,
0.346466767346100823488,
0.351976423156884266063,
0.357455888922231679316,
0.362905493689140712376,
0.368325561158599157352,
0.373716409793814818840,
0.379078352934811846353,
0.384411698910298582632,
0.389716751140440464951,
0.394993808240542421117,
0.400243164127459749579,
0.405465108107819105498,
0.410659924985338875558,
0.415827895143593195825,
0.420969294644237379543,
0.426084395310681429691,
0.431173464818130014464,
0.436236766774527495726,
0.441274560805140936281,
0.446287102628048160113,
0.451274644139630254358,
0.456237433481874177232,
0.461175715122408291790,
0.466089729924533457960,
0.470979715219073113985,
0.475845904869856894947,
0.480688529345570714212,
0.485507815781602403149,
0.490303988045525329653,
0.495077266798034543171,
0.499827869556611403822,
0.504556010751912253908,
0.509261901790523552335,
0.513945751101346104405,
0.518607764208354637958,
0.523248143765158602036,
0.527867089620485785417,
0.532464798869114019908,
0.537041465897345915436,
0.541597282432121573947,
0.546132437597407260909,
0.550647117952394182793,
0.555141507540611200965,
0.559615787935399566777,
0.564070138285387656651,
0.568504735352689749561,
0.572919753562018740922,
0.577315365035246941260,
0.581691739635061821900,
0.586049045003164792433,
0.590387446602107957005,
0.594707107746216934174,
0.599008189645246602594,
0.603290851438941899687,
0.607555250224322662688,
0.611801541106615331955,
0.616029877215623855590,
0.620240409751204424537,
0.624433288012369303032,
0.628608659422752680256,
0.632766669570628437213,
0.636907462236194987781,
0.641031179420679109171,
0.645137961373620782978,
0.649227946625615004450,
0.653301272011958644725,
0.657358072709030238911,
0.661398482245203922502,
0.665422632544505177065,
0.669430653942981734871,
0.673422675212350441142,
0.677398823590920073911,
0.681359224807238206267,
0.685304003098281100392,
0.689233281238557538017,
0.693147180560117703862);
constant LOGF_TAIL: REAL_VECTOR(0 TO N) := (
0.0,
-0.00000000000000543229938420049,
0.00000000000000172745674997061,
-0.00000000000001323017818229233,
-0.00000000000001154527628289872,
-0.00000000000000466529469958300,
0.00000000000005148849572685810,
-0.00000000000002532168943117445,
-0.00000000000005213620639136504,
-0.00000000000001819506003016881,
0.00000000000006329065958724544,
0.00000000000008614512936087814,
-0.00000000000007355770219435028,
0.00000000000009638067658552277,
0.00000000000007598636597194141,
0.00000000000002579999128306990,
-0.00000000000004654729747598444,
-0.00000000000007556920687451336,
0.00000000000010195735223708472,
-0.00000000000017319034406422306,
-0.00000000000007718001336828098,
0.00000000000010980754099855238,
-0.00000000000002047235780046195,
-0.00000000000008372091099235912,
0.00000000000014088127937111135,
0.00000000000012869017157588257,
0.00000000000017788850778198106,
0.00000000000006440856150696891,
0.00000000000016132822667240822,
-0.00000000000007540916511956188,
-0.00000000000000036507188831790,
0.00000000000009120937249914984,
0.00000000000018567570959796010,
-0.00000000000003149265065191483,
-0.00000000000009309459495196889,
0.00000000000017914338601329117,
-0.00000000000001302979717330866,
0.00000000000023097385217586939,
0.00000000000023999540484211737,
0.00000000000015393776174455408,
-0.00000000000036870428315837678,
0.00000000000036920375082080089,
-0.00000000000009383417223663699,
0.00000000000009433398189512690,
0.00000000000041481318704258568,
-0.00000000000003792316480209314,
0.00000000000008403156304792424,
-0.00000000000034262934348285429,
0.00000000000043712191957429145,
-0.00000000000010475750058776541,
-0.00000000000011118671389559323,
0.00000000000037549577257259853,
0.00000000000013912841212197565,
0.00000000000010775743037572640,
0.00000000000029391859187648000,
-0.00000000000042790509060060774,
0.00000000000022774076114039555,
0.00000000000010849569622967912,
-0.00000000000023073801945705758,
0.00000000000015761203773969435,
0.00000000000003345710269544082,
-0.00000000000041525158063436123,
0.00000000000032655698896907146,
-0.00000000000044704265010452446,
0.00000000000034527647952039772,
-0.00000000000007048962392109746,
0.00000000000011776978751369214,
-0.00000000000010774341461609578,
0.00000000000021863343293215910,
0.00000000000024132639491333131,
0.00000000000039057462209830700,
-0.00000000000026570679203560751,
0.00000000000037135141919592021,
-0.00000000000017166921336082431,
-0.00000000000028658285157914353,
-0.00000000000023812542263446809,
0.00000000000006576659768580062,
-0.00000000000028210143846181267,
0.00000000000010701931762114254,
0.00000000000018119346366441110,
0.00000000000009840465278232627,
-0.00000000000033149150282752542,
-0.00000000000018302857356041668,
-0.00000000000016207400156744949,
0.00000000000048303314949553201,
-0.00000000000071560553172382115,
0.00000000000088821239518571855,
-0.00000000000030900580513238244,
-0.00000000000061076551972851496,
0.00000000000035659969663347830,
0.00000000000035782396591276383,
-0.00000000000046226087001544578,
0.00000000000062279762917225156,
0.00000000000072838947272065741,
0.00000000000026809646615211673,
-0.00000000000010960825046059278,
0.00000000000002311949383800537,
-0.00000000000058469058005299247,
-0.00000000000002103748251144494,
-0.00000000000023323182945587408,
-0.00000000000042333694288141916,
-0.00000000000043933937969737844,
0.00000000000041341647073835565,
0.00000000000006841763641591466,
0.00000000000047585534004430641,
0.00000000000083679678674757695,
-0.00000000000085763734646658640,
0.00000000000021913281229340092,
-0.00000000000062242842536431148,
-0.00000000000010983594325438430,
0.00000000000065310431377633651,
-0.00000000000047580199021710769,
-0.00000000000037854251265457040,
0.00000000000040939233218678664,
0.00000000000087424383914858291,
0.00000000000025218188456842882,
-0.00000000000003608131360422557,
-0.00000000000050518555924280902,
0.00000000000078699403323355317,
-0.00000000000067020876961949060,
0.00000000000016108575753932458,
0.00000000000058527188436251509,
-0.00000000000035246757297904791,
-0.00000000000018372084495629058,
0.00000000000088606689813494916,
0.00000000000066486268071468700,
0.00000000000063831615170646519,
0.00000000000025144230728376072,
-0.00000000000017239444525614834);
variable M, J:INTEGER;
variable F1, F2, G, Q, U, U2, V: REAL;
variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs
variable ONE: REAL := 1.0; --Made variable so no constant folding occurs
-- double logb(), ldexp();
variable U1:REAL;
begin
-- Check validity of argument
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = MATH_E ) then
return 1.0;
end if;
-- Argument reduction: 1 <= g < 2; x/2^m = g;
-- y = F*(1 + f/F) for |f| <= 2^-8
M := ILOGB(X);
G := LDEXP(X, -M);
J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding
F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512]
F2 := G - F1;
-- Approximate expansion for log(1+f2/F1) ~= u + q
G := 1.0/(2.0*F1+F2);
U := 2.0*F2*G;
V := U*U;
Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4)));
-- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8,
-- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits.
-- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750.
--
if ( J /= 0 or M /= 0) then
U1 := U + 513.0;
U1 := U1 - 513.0;
-- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero
-- u1 = u to 24 bits.
--
else
U1 := U;
--TRUNC(U1); --In c this is u1 = (double) (float) (u1)
end if;
U2 := (2.0*(F2 - F1*U1) - U1*F2) * G;
-- u1 + u2 = 2f/(2F+f) to extra precision.
-- log(x) = log(2^m*F1*(1+f2/F1)) =
-- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q);
-- (exact) + (tiny)
U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact
U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny
U2 := U2 + LOGF_TAIL(N)*REAL(M);
return (U1 + U2);
end LOG;
function LOG2 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG2(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = 2.0 ) then
return 1.0;
end if;
-- Compute value for general case
return ( MATH_LOG2_OF_E*LOG(X) );
end LOG2;
function LOG10 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG10(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = 10.0 ) then
return 1.0;
end if;
-- Compute value for general case
return ( MATH_LOG10_OF_E*LOG(X) );
end LOG10;
function LOG (X: in REAL; BASE: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = BASE ) then
return 1.0;
end if;
-- Compute value for general case
return ( LOG(X)/LOG(BASE));
end LOG;
function SIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) SIN(-X) = -SIN(X)
-- b) SIN(X) = X if ABS(X) < EPS
-- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS
-- d) SIN(MATH_PI_OVER_2 - X) = COS(X)
-- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS
-- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence criteria
variable N : INTEGER;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in SIN(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then
return 0.0;
end if;
if XLOCAL = MATH_PI_OVER_2 then
if NEGATIVE then
return -1.0;
else
return 1.0;
end if;
end if;
if XLOCAL = MATH_3_PI_OVER_2 then
if NEGATIVE then
return 1.0;
else
return -1.0;
end if;
end if;
if XLOCAL < EPS then
if NEGATIVE then
return -XLOCAL;
else
return XLOCAL;
end if;
else
if XLOCAL < BASE_EPS then
TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := MATH_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := MATH_2_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
TEMP := ABS(MATH_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
-- Compute value for general cases
if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then
VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1);
end if;
N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2));
case QUADRANT( N mod 4) is
when 0 =>
VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1);
when 1 =>
VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27,
ROTATION)(0);
when 2 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1);
when 3 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27,
ROTATION)(0);
end case;
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end SIN;
function COS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) COS(-X) = COS(X)
-- b) COS(X) = SIN(MATH_PI_OVER_2 - X)
-- c) COS(MATH_PI + X) = -COS(X)
-- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS
-- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
variable XLOCAL : REAL := ABS(X);
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in COS(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then
return 1.0;
end if;
if XLOCAL = MATH_PI then
return -1.0;
end if;
if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then
return 0.0;
end if;
TEMP := ABS(XLOCAL);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
TEMP := ABS(XLOCAL -MATH_2_PI);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
TEMP := ABS (XLOCAL - MATH_PI);
if TEMP < EPS then
return (-1.0 + 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
-- Compute value for general cases
return SIN(MATH_PI_OVER_2 - XLOCAL);
end COS;
function TAN (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) TAN(0.0) = 0.0
-- b) TAN(-X) = -TAN(X)
-- c) Returns REAL'LOW on error if X < 0.0
-- d) Returns REAL'HIGH on error if X > 0.0
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make 0.0 <= XLOCAL <= MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in TAN(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Check validity of argument
if XLOCAL = MATH_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'LOW);
else
return(REAL'HIGH);
end if;
end if;
if XLOCAL = MATH_3_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'HIGH);
else
return(REAL'LOW);
end if;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_PI then
return 0.0;
end if;
-- Compute value for general cases
VALUE := SIN(XLOCAL)/COS(XLOCAL);
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end TAN;
function ARCSIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCSIN(-X) = -ARCSIN(X)
-- b) Returns X on error
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
begin
-- Check validity of arguments
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCSIN(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
elsif XLOCAL = 1.0 then
if NEGATIVE then
return -MATH_PI_OVER_2;
else
return MATH_PI_OVER_2;
end if;
end if;
-- Compute value for general cases
if XLOCAL < 0.9 then
VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL)));
else
VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
end if;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end ARCSIN;
function ARCCOS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCCOS(-X) = MATH_PI - ARCCOS(X)
-- b) Returns X on error
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
begin
-- Check validity of argument
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCCOS(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 1.0 then
return 0.0;
elsif X = 0.0 then
return MATH_PI_OVER_2;
elsif X = -1.0 then
return MATH_PI;
end if;
-- Compute value for general cases
if XLOCAL > 0.9 then
VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
else
VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL));
end if;
if NEGATIVE then
VALUE := MATH_PI - VALUE;
end if;
return VALUE;
end ARCCOS;
function ARCTAN (Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCTAN(-Y) = -ARCTAN(Y)
-- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0
-- c) ARCTAN(Y) = Y for |Y| < EPS
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;
variable NEGATIVE : BOOLEAN := Y < 0.0;
variable RECIPROCAL : BOOLEAN;
variable YLOCAL : REAL := ABS(Y);
variable VALUE : REAL;
begin
-- Make argument |Y| <=1.0
if YLOCAL > 1.0 then
YLOCAL := 1.0/YLOCAL;
RECIPROCAL := TRUE;
else
RECIPROCAL := FALSE;
end if;
-- Compute value for special cases
if YLOCAL = 0.0 then
if RECIPROCAL then
if NEGATIVE then
return (-MATH_PI_OVER_2);
else
return (MATH_PI_OVER_2);
end if;
else
return 0.0;
end if;
end if;
if YLOCAL < EPS then
if NEGATIVE then
if RECIPROCAL then
return (-MATH_PI_OVER_2 + YLOCAL);
else
return -YLOCAL;
end if;
else
if RECIPROCAL then
return (MATH_PI_OVER_2 - YLOCAL);
else
return YLOCAL;
end if;
end if;
end if;
-- Compute value for general cases
VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2);
if RECIPROCAL then
VALUE := MATH_PI_OVER_2 - VALUE;
end if;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end ARCTAN;
function ARCTAN (Y : in REAL; X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
variable YLOCAL : REAL;
variable VALUE : REAL;
begin
-- Check validity of arguments
if (Y = 0.0 and X = 0.0 ) then
assert FALSE report
"ARCTAN(0.0, 0.0) is undetermined"
severity ERROR;
return 0.0;
end if;
-- Compute value for special cases
if Y = 0.0 then
if X > 0.0 then
return 0.0;
else
return MATH_PI;
end if;
end if;
if X = 0.0 then
if Y > 0.0 then
return MATH_PI_OVER_2;
else
return -MATH_PI_OVER_2;
end if;
end if;
-- Compute value for general cases
YLOCAL := ABS(Y/X);
VALUE := ARCTAN(YLOCAL);
if X < 0.0 then
VALUE := MATH_PI - VALUE;
end if;
if Y < 0.0 then
VALUE := -VALUE;
end if;
return VALUE;
end ARCTAN;
function SINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/2.0
-- b) SINH(-X) = SINH(X)
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)*0.5;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end SINH;
function COSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) + EXP(-X))/2.0
-- b) COSH(-X) = COSH(X)
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 1.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP + 1.0/TEMP)*0.5;
return VALUE;
end COSH;
function TANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X))
-- b) TANH(-X) = -TANH(X)
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP);
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end TANH;
function ARCSINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X + 1.0))
begin
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
return ( LOG( X + SQRT( X*X + 1.0)) );
end ARCSINH;
function ARCCOSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0
-- b) Returns X on error
begin
-- Check validity of arguments
if X < 1.0 then
assert FALSE
report "X < 1.0 in ARCCOSH(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 1.0 then
return 0.0;
end if;
-- Compute value for general cases
return ( LOG( X + SQRT( X*X - 1.0)));
end ARCCOSH;
function ARCTANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0
-- b) Returns X on error
begin
-- Check validity of arguments
if ABS(X) >= 1.0 then
assert FALSE
report "ABS(X) >= 1.0 in ARCTANH(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
return( 0.5*LOG( (1.0+X)/(1.0-X) ) );
end ARCTANH;
end MATH_REAL;
|
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_REAL)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package defines a standard for designers to use in
-- describing VHDL models that make use of common REAL constants
-- and common REAL elementary mathematical functions.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076-
-- 1993.
--
-- Notes:
-- No declarations or definitions shall be included in, or
-- excluded from, this package.
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_REAL.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_REAL package declaration. The purpose of the MATH_REAL
-- package body is to provide a guideline for implementations to
-- verify their implementation of MATH_REAL. Tool developers may
-- choose to implement the package body in the most efficient
-- manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
package MATH_REAL is
constant CopyRightNotice: STRING
:= "Copyright 1996 IEEE. All rights reserved.";
--
-- Constant Definitions
--
constant MATH_E : REAL := 2.71828_18284_59045_23536;
-- Value of e
constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
-- Value of 1/e
constant MATH_PI : REAL := 3.14159_26535_89793_23846;
-- Value of pi
constant MATH_2_PI : REAL := 6.28318_53071_79586_47693;
-- Value of 2*pi
constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
-- Value of 1/pi
constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
-- Value of pi/2
constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
-- Value of pi/3
constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
-- Value of pi/4
constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
-- Value 3*pi/2
constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
-- Natural log of 2
constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
-- Natural log of 10
constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
-- Log base 2 of e
constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765;
-- Log base 10 of e
constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880;
-- square root of 2
constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440;
-- square root of 1/2
constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730;
-- square root of pi
constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577;
-- Conversion factor from degree to radian
constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680;
-- Conversion factor from radian to degree
--
-- Function Declarations
--
function SIGN (X: in REAL ) return REAL;
-- Purpose:
-- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIGN(X)) <= 1.0
-- Notes:
-- None
function CEIL (X : in REAL ) return REAL;
-- Purpose:
-- Returns smallest INTEGER value (as REAL) not less than X
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CEIL(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function FLOOR (X : in REAL ) return REAL;
-- Purpose:
-- Returns largest INTEGER value (as REAL) not greater than X
-- Special values:
-- FLOOR(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- FLOOR(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function ROUND (X : in REAL ) return REAL;
-- Purpose:
-- Rounds X to the nearest integer value (as real). If X is
-- halfway between two integers, rounding is away from 0.0
-- Special values:
-- ROUND(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ROUND(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function TRUNC (X : in REAL ) return REAL;
-- Purpose:
-- Truncates X towards 0.0 and returns truncated value
-- Special values:
-- TRUNC(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- TRUNC(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function "MOD" (X, Y: in REAL ) return REAL;
-- Purpose:
-- Returns floating point modulus of X/Y, with the same sign as
-- Y, and absolute value less than the absolute value of Y, and
-- for some INTEGER value N the result satisfies the relation
-- X = Y*N + MOD(X,Y)
-- Special values:
-- None
-- Domain:
-- X in REAL; Y in REAL and Y /= 0.0
-- Error conditions:
-- Error if Y = 0.0
-- Range:
-- ABS(MOD(X,Y)) < ABS(Y)
-- Notes:
-- None
function REALMAX (X, Y : in REAL ) return REAL;
-- Purpose:
-- Returns the algebraically larger of X and Y
-- Special values:
-- REALMAX(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMAX(X,Y) is mathematically unbounded
-- Notes:
-- None
function REALMIN (X, Y : in REAL ) return REAL;
-- Purpose:
-- Returns the algebraically smaller of X and Y
-- Special values:
-- REALMIN(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMIN(X,Y) is mathematically unbounded
-- Notes:
-- None
procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL);
-- Purpose:
-- Returns, in X, a pseudo-random number with uniform
-- distribution in the open interval (0.0, 1.0).
-- Special values:
-- None
-- Domain:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
-- Error conditions:
-- Error if SEED1 or SEED2 outside of valid domain
-- Range:
-- 0.0 < X < 1.0
-- Notes:
-- a) The semantics for this function are described by the
-- algorithm published by Pierre L'Ecuyer in "Communications
-- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
-- The algorithm is based on the combination of two
-- multiplicative linear congruential generators for 32-bit
-- platforms.
--
-- b) Before the first call to UNIFORM, the seed values
-- (SEED1, SEED2) have to be initialized to values in the range
-- [1, 2147483562] and [1, 2147483398] respectively. The
-- seed values are modified after each call to UNIFORM.
--
-- c) This random number generator is portable for 32-bit
-- computers, and it has a period of ~2.30584*(10**18) for each
-- set of seed values.
--
-- d) For information on spectral tests for the algorithm, refer
-- to the L'Ecuyer article.
function SQRT (X : in REAL ) return REAL;
-- Purpose:
-- Returns square root of X
-- Special values:
-- SQRT(0.0) = 0.0
-- SQRT(1.0) = 1.0
-- Domain:
-- X >= 0.0
-- Error conditions:
-- Error if X < 0.0
-- Range:
-- SQRT(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of SQRT is
-- approximately given by:
-- SQRT(X) <= SQRT(REAL'HIGH)
function CBRT (X : in REAL ) return REAL;
-- Purpose:
-- Returns cube root of X
-- Special values:
-- CBRT(0.0) = 0.0
-- CBRT(1.0) = 1.0
-- CBRT(-1.0) = -1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CBRT(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of CBRT is approximately given by:
-- ABS(CBRT(X)) <= CBRT(REAL'HIGH)
function "**" (X : in INTEGER; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0
-- 0**Y = 0.0; Y > 0.0
-- X**1.0 = REAL(X); X >= 0
-- 1**Y = 1.0
-- Domain:
-- X > 0
-- X = 0 for Y > 0.0
-- X < 0 for Y = 0.0
-- Error conditions:
-- Error if X < 0 and Y /= 0.0
-- Error if X = 0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function "**" (X : in REAL; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0.0
-- 0.0**Y = 0.0; Y > 0.0
-- X**1.0 = X; X >= 0.0
-- 1.0**Y = 1.0
-- Domain:
-- X > 0.0
-- X = 0.0 for Y > 0.0
-- X < 0.0 for Y = 0.0
-- Error conditions:
-- Error if X < 0.0 and Y /= 0.0
-- Error if X = 0.0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function EXP (X : in REAL ) return REAL;
-- Purpose:
-- Returns e**X; where e = MATH_E
-- Special values:
-- EXP(0.0) = 1.0
-- EXP(1.0) = MATH_E
-- EXP(-1.0) = MATH_1_OVER_E
-- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
-- Domain:
-- X in REAL such that EXP(X) <= REAL'HIGH
-- Error conditions:
-- Error if X > LOG(REAL'HIGH)
-- Range:
-- EXP(X) >= 0.0
-- Notes:
-- a) The usable domain of EXP is approximately given by:
-- X <= LOG(REAL'HIGH)
function LOG (X : in REAL ) return REAL;
-- Purpose:
-- Returns natural logarithm of X
-- Special values:
-- LOG(1.0) = 0.0
-- LOG(MATH_E) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG is approximately given by:
-- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
function LOG2 (X : in REAL ) return REAL;
-- Purpose:
-- Returns logarithm base 2 of X
-- Special values:
-- LOG2(1.0) = 0.0
-- LOG2(2.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG2(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG2 is approximately given by:
-- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
function LOG10 (X : in REAL ) return REAL;
-- Purpose:
-- Returns logarithm base 10 of X
-- Special values:
-- LOG10(1.0) = 0.0
-- LOG10(10.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG10(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG10 is approximately given by:
-- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
function LOG (X: in REAL; BASE: in REAL) return REAL;
-- Purpose:
-- Returns logarithm base BASE of X
-- Special values:
-- LOG(1.0, BASE) = 0.0
-- LOG(BASE, BASE) = 1.0
-- Domain:
-- X > 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if X <= 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(X, BASE) is mathematically unbounded
-- Notes:
-- a) When BASE > 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
-- b) When 0.0 < BASE < 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
function SIN (X : in REAL ) return REAL;
-- Purpose:
-- Returns sine of X; X in radians
-- Special values:
-- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function COS ( X : in REAL ) return REAL;
-- Purpose:
-- Returns cosine of X; X in radians
-- Special values:
-- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
-- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(COS(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function TAN (X : in REAL ) return REAL;
-- Purpose:
-- Returns tangent of X; X in radians
-- Special values:
-- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL and
-- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
-- Error conditions:
-- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
-- INTEGER
-- Range:
-- TAN(X) is mathematically unbounded
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function ARCSIN (X : in REAL ) return REAL;
-- Purpose:
-- Returns inverse sine of X
-- Special values:
-- ARCSIN(0.0) = 0.0
-- ARCSIN(1.0) = MATH_PI_OVER_2
-- ARCSIN(-1.0) = -MATH_PI_OVER_2
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- ABS(ARCSIN(X) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCCOS (X : in REAL ) return REAL;
-- Purpose:
-- Returns inverse cosine of X
-- Special values:
-- ARCCOS(1.0) = 0.0
-- ARCCOS(0.0) = MATH_PI_OVER_2
-- ARCCOS(-1.0) = MATH_PI
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- 0.0 <= ARCCOS(X) <= MATH_PI
-- Notes:
-- None
function ARCTAN (Y : in REAL) return REAL;
-- Purpose:
-- Returns the value of the angle in radians of the point
-- (1.0, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0) = 0.0
-- Domain:
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCTAN (Y : in REAL; X : in REAL) return REAL;
-- Purpose:
-- Returns the principal value of the angle in radians of
-- the point (X, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0, X) = 0.0 if X > 0.0
-- ARCTAN(0.0, X) = MATH_PI if X < 0.0
-- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
-- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
-- Domain:
-- Y in REAL
-- X in REAL, X /= 0.0 when Y = 0.0
-- Error conditions:
-- Error if X = 0.0 and Y = 0.0
-- Range:
-- -MATH_PI < ARCTAN(Y,X) <= MATH_PI
-- Notes:
-- None
function SINH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic sine of X
-- Special values:
-- SINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- SINH(X) is mathematically unbounded
-- Notes:
-- a) The usable domain of SINH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function COSH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic cosine of X
-- Special values:
-- COSH(0.0) = 1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- COSH(X) >= 1.0
-- Notes:
-- a) The usable domain of COSH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function TANH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic tangent of X
-- Special values:
-- TANH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(TANH(X)) <= 1.0
-- Notes:
-- None
function ARCSINH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic sine of X
-- Special values:
-- ARCSINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ARCSINH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCSINH is approximately given by:
-- ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
function ARCCOSH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic cosine of X
-- Special values:
-- ARCCOSH(1.0) = 0.0
-- Domain:
-- X >= 1.0
-- Error conditions:
-- Error if X < 1.0
-- Range:
-- ARCCOSH(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of ARCCOSH is
-- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH)
function ARCTANH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic tangent of X
-- Special values:
-- ARCTANH(0.0) = 0.0
-- Domain:
-- ABS(X) < 1.0
-- Error conditions:
-- Error if ABS(X) >= 1.0
-- Range:
-- ARCTANH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCTANH is approximately given by:
-- ABS(ARCTANH(X)) < LOG(REAL'HIGH)
end MATH_REAL;
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_REAL)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package body is a nonnormative implementation of the
-- functionality defined in the MATH_REAL package declaration.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076
-- -1993.
--
-- Notes:
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_REAL.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_REAL package declaration. The purpose of the MATH_REAL
-- package body is to clarify such semantics and provide a
-- guideline for implementations to verify their implementation
-- of MATH_REAL. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
package body MATH_REAL is
--
-- Local Constants for Use in the Package Body Only
--
constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2
constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10
constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi
constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic
constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries
constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria
constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic
--
-- Local Type Declarations for Cordic Operations
--
type REAL_VECTOR is array (NATURAL range <>) of REAL;
type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL;
subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER);
subtype REAL_ARR_2 is REAL_VECTOR (0 to 1);
subtype REAL_ARR_3 is REAL_VECTOR (0 to 2);
subtype QUADRANT is INTEGER range 0 to 3;
type CORDIC_MODE_TYPE is (ROTATION, VECTORING);
--
-- Auxiliary Functions for Cordic Algorithms
--
function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL;
NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is
-- Description:
-- Returns power of two for a vector of values
-- Notes:
-- None
--
variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES);
variable TEMP : REAL := INITIAL_VALUE;
variable FLAG : BOOLEAN := TRUE;
begin
for I in 0 to NUMBER_OF_VALUES loop
V(I) := TEMP;
for P in D'RANGE loop
if I = D(P) then
FLAG := FALSE;
exit;
end if;
end loop;
if FLAG then
TEMP := TEMP/2.0;
end if;
FLAG := TRUE;
end loop;
return V;
end POWER_OF_2_SERIES;
constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES(
NATURAL_VECTOR'(100, 90),1.0,
MAX_ITER);
constant EPSILON : REAL_VECTOR_N := (
7.8539816339744827e-01,
4.6364760900080606e-01,
2.4497866312686413e-01,
1.2435499454676144e-01,
6.2418809995957351e-02,
3.1239833430268277e-02,
1.5623728620476830e-02,
7.8123410601011116e-03,
3.9062301319669717e-03,
1.9531225164788189e-03,
9.7656218955931937e-04,
4.8828121119489829e-04,
2.4414062014936175e-04,
1.2207031189367021e-04,
6.1035156174208768e-05,
3.0517578115526093e-05,
1.5258789061315760e-05,
7.6293945311019699e-06,
3.8146972656064960e-06,
1.9073486328101870e-06,
9.5367431640596080e-07,
4.7683715820308876e-07,
2.3841857910155801e-07,
1.1920928955078067e-07,
5.9604644775390553e-08,
2.9802322387695303e-08,
1.4901161193847654e-08,
7.4505805969238281e-09
);
function CORDIC ( X0 : in REAL;
Y0 : in REAL;
Z0 : in REAL;
N : in NATURAL; -- Precision factor
CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0)
-- or vectoring (Y -> 0)
) return REAL_ARR_3 is
-- Description:
-- Compute cordic values
-- Notes:
-- None
variable X : REAL := X0;
variable Y : REAL := Y0;
variable Z : REAL := Z0;
variable X_TEMP : REAL;
begin
if CORDIC_MODE = ROTATION then
for K in 0 to N loop
X_TEMP := X;
if ( Z >= 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
else
for K in 0 to N loop
X_TEMP := X;
if ( Y < 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
end if;
return REAL_ARR_3'(X, Y, Z);
end CORDIC;
--
-- Bodies for Global Mathematical Functions Start Here
--
function SIGN (X: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
if ( X > 0.0 ) then
return 1.0;
elsif ( X < 0.0 ) then
return -1.0;
else
return 0.0;
end if;
end SIGN;
function CEIL (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is X <= LARGE
-- c) Returns X if ABS(X) >= LARGE
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
begin
if ABS(X) >= LARGE then
return X;
end if;
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
if X > 0.0 then
if RD >= X then
return RD;
else
return RD + 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD <= X then
return RD + 1.0;
else
return RD;
end if;
end if;
end CEIL;
function FLOOR (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is ABS(X) <= LARGE
-- c) Returns X if ABS(X) >= LARGE
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
begin
if ABS( X ) >= LARGE then
return X;
end if;
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
if X > 0.0 then
if RD <= X then
return RD;
else
return RD - 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD >= X then
return RD - 1.0;
else
return RD;
end if;
end if;
end FLOOR;
function ROUND (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X + 0.5) if X > 0
-- c) Returns CEIL(X - 0.5) if X < 0
begin
if X > 0.0 then
return FLOOR(X + 0.5);
elsif X < 0.0 then
return CEIL( X - 0.5);
else
return 0.0;
end if;
end ROUND;
function TRUNC (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X) if X > 0
-- c) Returns CEIL(X) if X < 0
begin
if X > 0.0 then
return FLOOR(X);
elsif X < 0.0 then
return CEIL( X);
else
return 0.0;
end if;
end TRUNC;
function "MOD" (X, Y: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
variable XNEGATIVE : BOOLEAN := X < 0.0;
variable YNEGATIVE : BOOLEAN := Y < 0.0;
variable VALUE : REAL;
begin
-- Check validity of input arguments
if (Y = 0.0) then
assert FALSE
report "MOD(X, 0.0) is undefined"
severity ERROR;
return 0.0;
end if;
-- Compute value
if ( XNEGATIVE ) then
if ( YNEGATIVE ) then
VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
end if;
else
if ( YNEGATIVE ) then
VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
end if;
end if;
return VALUE;
end "MOD";
function REALMAX (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMAX(X,Y) = X when X = Y
--
begin
if X >= Y then
return X;
else
return Y;
end if;
end REALMAX;
function REALMIN (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMIN(X,Y) = X when X = Y
--
begin
if X <= Y then
return X;
else
return Y;
end if;
end REALMIN;
procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL)
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
--
variable Z, K: INTEGER;
variable TSEED1 : INTEGER := INTEGER'(SEED1);
variable TSEED2 : INTEGER := INTEGER'(SEED2);
begin
-- Check validity of arguments
if SEED1 > 2147483562 then
assert FALSE
report "SEED1 > 2147483562 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
if SEED2 > 2147483398 then
assert FALSE
report "SEED2 > 2147483398 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
-- Compute new seed values and pseudo-random number
K := TSEED1/53668;
TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211;
if TSEED1 < 0 then
TSEED1 := TSEED1 + 2147483563;
end if;
K := TSEED2/52774;
TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791;
if TSEED2 < 0 then
TSEED2 := TSEED2 + 2147483399;
end if;
Z := TSEED1 - TSEED2;
if Z < 1 then
Z := Z + 2147483562;
end if;
-- Get output values
SEED1 := POSITIVE'(TSEED1);
SEED2 := POSITIVE'(TSEED2);
X := REAL(Z)*4.656613e-10;
end UNIFORM;
function SQRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = 0.5*[F(n) + x/F(n)]
-- b) Returns 0.0 on error
--
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor
variable INIVAL: REAL;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
begin
-- Check validity of argument
if ( X < 0.0 ) then
assert FALSE
report "X < 0.0 in SQRT(X)"
severity ERROR;
return 0.0;
end if;
-- Get the square root for special cases
if X = 0.0 then
return 0.0;
else
if ( X = 1.0 ) then
return 1.0;
end if;
end if;
-- Get the square root for general cases
INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise
OLDVAL := INIVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
-- Check for relative and absolute error and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT) ) loop
OLDVAL := NEWVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
COUNT := COUNT + 1;
end loop;
return NEWVAL;
end SQRT;
function CBRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2];
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
variable INIVAL: REAL;
variable XLOCAL : REAL := X;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
begin
-- Compute root for special cases
if X = 0.0 then
return 0.0;
elsif ( X = 1.0 ) then
return 1.0;
else
if X = -1.0 then
return -1.0;
end if;
end if;
-- Compute root for general cases
if NEGATIVE then
XLOCAL := -X;
end if;
INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but
-- imprecise
OLDVAL := INIVAL;
NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR
(ABS(NEWVAL - OLDVAL) > EPS ) ) AND
( COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
COUNT := COUNT + 1;
end loop;
if NEGATIVE then
NEWVAL := -NEWVAL;
end if;
return NEWVAL;
end CBRT;
function "**" (X : in INTEGER; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
begin
-- Check validity of argument
if ( ( X < 0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
if ( ( X = 0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
-- Get value for special cases
if ( X = 0 and Y > 0.0 ) then
return 0.0;
end if;
if ( X = 1 ) then
return 1.0;
end if;
if ( Y = 0.0 and X /= 0 ) then
return 1.0;
end if;
if ( Y = 1.0) then
return (REAL(X));
end if;
-- Get value for general case
return EXP (Y * LOG (REAL(X)));
end "**";
function "**" (X : in REAL; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
begin
-- Check validity of argument
if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0.0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0.0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
-- Get value for special cases
if ( X = 0.0 and Y > 0.0 ) then
return 0.0;
end if;
if ( X = 1.0 ) then
return 1.0;
end if;
if ( Y = 0.0 and X /= 0.0 ) then
return 1.0;
end if;
if ( Y = 1.0) then
return (X);
end if;
-- Get value for general case
return EXP (Y * LOG (X));
end "**";
function EXP (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) This function computes the exponential using the following
-- series:
-- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0
-- and reduces argument X to take advantage of exp(x+y) =
-- exp(x)*exp(y)
--
-- b) This implementation limits X to be less than LOG(REAL'HIGH)
-- to avoid overflow. Returns REAL'HIGH when X reaches that
-- limit
--
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria
variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument
variable XLOCAL : REAL := ABS(X); -- Use positive value
variable OLDVAL: REAL ;
variable COUNT: INTEGER ;
variable NEWVAL: REAL ;
variable LAST_TERM: REAL ;
variable FACTOR : REAL := 1.0;
begin
-- Compute value for special cases
if X = 0.0 then
return 1.0;
end if;
if XLOCAL = 1.0 then
if RECIPROCAL then
return MATH_1_OVER_E;
else
return MATH_E;
end if;
end if;
if XLOCAL = 2.0 then
if RECIPROCAL then
return 1.0/MATH_E_P2;
else
return MATH_E_P2;
end if;
end if;
if XLOCAL = 10.0 then
if RECIPROCAL then
return 1.0/MATH_E_P10;
else
return MATH_E_P10;
end if;
end if;
if XLOCAL > LOG(REAL'HIGH) then
if RECIPROCAL then
return 0.0;
else
assert FALSE
report "X > LOG(REAL'HIGH) in EXP(X)"
severity NOTE;
return REAL'HIGH;
end if;
end if;
-- Reduce argument to ABS(X) < 1.0
while XLOCAL > 10.0 loop
XLOCAL := XLOCAL - 10.0;
FACTOR := FACTOR*MATH_E_P10;
end loop;
while XLOCAL > 1.0 loop
XLOCAL := XLOCAL - 1.0;
FACTOR := FACTOR*MATH_E;
end loop;
-- Compute value for case 0 < XLOCAL < 1
OLDVAL := 1.0;
LAST_TERM := XLOCAL;
NEWVAL:= OLDVAL + LAST_TERM;
COUNT := 2;
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT)));
NEWVAL := OLDVAL + LAST_TERM;
COUNT := COUNT + 1;
end loop;
-- Compute final value using exp(x+y) = exp(x)*exp(y)
NEWVAL := NEWVAL*FACTOR;
if RECIPROCAL then
NEWVAL := 1.0/NEWVAL;
end if;
return NEWVAL;
end EXP;
--
-- Auxiliary Functions to Compute LOG
--
function ILOGB(X: in REAL) return INTEGER IS
-- Description:
-- Returns n such that -1 <= ABS(X)/2^n < 2
-- Notes:
-- None
variable N: INTEGER := 0;
variable Y: REAL := ABS(X);
begin
if(Y = 1.0 or Y = 0.0) then
return 0;
end if;
if( Y > 1.0) then
while Y >= 2.0 loop
Y := Y/2.0;
N := N+1;
end loop;
return N;
end if;
-- O < Y < 1
while Y < 1.0 loop
Y := Y*2.0;
N := N -1;
end loop;
return N;
end ILOGB;
function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS
-- Description:
-- Returns X*2^n
-- Notes:
-- None
begin
return X*(2.0 ** N);
end LDEXP;
function LOG (X : in REAL ) return REAL IS
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
--
-- Notes:
-- a) Returns REAL'LOW on error
--
-- Copyright (c) 1992 Regents of the University of California.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. All advertising materials mentioning features or use of this
-- software must display the following acknowledgement:
-- This product includes software developed by the University of
-- California, Berkeley and its contributors.
-- 4. Neither the name of the University nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-- DAMAGE.
--
-- NOTE: This VHDL version was generated using the C version of the
-- original function by the IEEE VHDL Mathematical Package
-- Working Group (CS/JT)
constant N: INTEGER := 128;
-- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128.
-- Used for generation of extend precision logarithms.
-- The constant 35184372088832 is 2^45, so the divide is exact.
-- It ensures correct reading of logF_head, even for inaccurate
-- decimal-to-binary conversion routines. (Everybody gets the
-- right answer for INTEGERs less than 2^53.)
-- Values for LOG(F) were generated using error < 10^-57 absolute
-- with the bc -l package.
type REAL_VECTOR is array (NATURAL range <>) of REAL;
constant A1:REAL := 0.08333333333333178827;
constant A2:REAL := 0.01250000000377174923;
constant A3:REAL := 0.002232139987919447809;
constant A4:REAL := 0.0004348877777076145742;
constant LOGF_HEAD: REAL_VECTOR(0 TO N) := (
0.0,
0.007782140442060381246,
0.015504186535963526694,
0.023167059281547608406,
0.030771658666765233647,
0.038318864302141264488,
0.045809536031242714670,
0.053244514518837604555,
0.060624621816486978786,
0.067950661908525944454,
0.075223421237524235039,
0.082443669210988446138,
0.089612158689760690322,
0.096729626458454731618,
0.103796793681567578460,
0.110814366340264314203,
0.117783035656430001836,
0.124703478501032805070,
0.131576357788617315236,
0.138402322859292326029,
0.145182009844575077295,
0.151916042025732167530,
0.158605030176659056451,
0.165249572895390883786,
0.171850256926518341060,
0.178407657472689606947,
0.184922338493834104156,
0.191394852999565046047,
0.197825743329758552135,
0.204215541428766300668,
0.210564769107350002741,
0.216873938300523150246,
0.223143551314024080056,
0.229374101064877322642,
0.235566071312860003672,
0.241719936886966024758,
0.247836163904594286577,
0.253915209980732470285,
0.259957524436686071567,
0.265963548496984003577,
0.271933715484010463114,
0.277868451003087102435,
0.283768173130738432519,
0.289633292582948342896,
0.295464212893421063199,
0.301261330578199704177,
0.307025035294827830512,
0.312755710004239517729,
0.318453731118097493890,
0.324119468654316733591,
0.329753286372579168528,
0.335355541920762334484,
0.340926586970454081892,
0.346466767346100823488,
0.351976423156884266063,
0.357455888922231679316,
0.362905493689140712376,
0.368325561158599157352,
0.373716409793814818840,
0.379078352934811846353,
0.384411698910298582632,
0.389716751140440464951,
0.394993808240542421117,
0.400243164127459749579,
0.405465108107819105498,
0.410659924985338875558,
0.415827895143593195825,
0.420969294644237379543,
0.426084395310681429691,
0.431173464818130014464,
0.436236766774527495726,
0.441274560805140936281,
0.446287102628048160113,
0.451274644139630254358,
0.456237433481874177232,
0.461175715122408291790,
0.466089729924533457960,
0.470979715219073113985,
0.475845904869856894947,
0.480688529345570714212,
0.485507815781602403149,
0.490303988045525329653,
0.495077266798034543171,
0.499827869556611403822,
0.504556010751912253908,
0.509261901790523552335,
0.513945751101346104405,
0.518607764208354637958,
0.523248143765158602036,
0.527867089620485785417,
0.532464798869114019908,
0.537041465897345915436,
0.541597282432121573947,
0.546132437597407260909,
0.550647117952394182793,
0.555141507540611200965,
0.559615787935399566777,
0.564070138285387656651,
0.568504735352689749561,
0.572919753562018740922,
0.577315365035246941260,
0.581691739635061821900,
0.586049045003164792433,
0.590387446602107957005,
0.594707107746216934174,
0.599008189645246602594,
0.603290851438941899687,
0.607555250224322662688,
0.611801541106615331955,
0.616029877215623855590,
0.620240409751204424537,
0.624433288012369303032,
0.628608659422752680256,
0.632766669570628437213,
0.636907462236194987781,
0.641031179420679109171,
0.645137961373620782978,
0.649227946625615004450,
0.653301272011958644725,
0.657358072709030238911,
0.661398482245203922502,
0.665422632544505177065,
0.669430653942981734871,
0.673422675212350441142,
0.677398823590920073911,
0.681359224807238206267,
0.685304003098281100392,
0.689233281238557538017,
0.693147180560117703862);
constant LOGF_TAIL: REAL_VECTOR(0 TO N) := (
0.0,
-0.00000000000000543229938420049,
0.00000000000000172745674997061,
-0.00000000000001323017818229233,
-0.00000000000001154527628289872,
-0.00000000000000466529469958300,
0.00000000000005148849572685810,
-0.00000000000002532168943117445,
-0.00000000000005213620639136504,
-0.00000000000001819506003016881,
0.00000000000006329065958724544,
0.00000000000008614512936087814,
-0.00000000000007355770219435028,
0.00000000000009638067658552277,
0.00000000000007598636597194141,
0.00000000000002579999128306990,
-0.00000000000004654729747598444,
-0.00000000000007556920687451336,
0.00000000000010195735223708472,
-0.00000000000017319034406422306,
-0.00000000000007718001336828098,
0.00000000000010980754099855238,
-0.00000000000002047235780046195,
-0.00000000000008372091099235912,
0.00000000000014088127937111135,
0.00000000000012869017157588257,
0.00000000000017788850778198106,
0.00000000000006440856150696891,
0.00000000000016132822667240822,
-0.00000000000007540916511956188,
-0.00000000000000036507188831790,
0.00000000000009120937249914984,
0.00000000000018567570959796010,
-0.00000000000003149265065191483,
-0.00000000000009309459495196889,
0.00000000000017914338601329117,
-0.00000000000001302979717330866,
0.00000000000023097385217586939,
0.00000000000023999540484211737,
0.00000000000015393776174455408,
-0.00000000000036870428315837678,
0.00000000000036920375082080089,
-0.00000000000009383417223663699,
0.00000000000009433398189512690,
0.00000000000041481318704258568,
-0.00000000000003792316480209314,
0.00000000000008403156304792424,
-0.00000000000034262934348285429,
0.00000000000043712191957429145,
-0.00000000000010475750058776541,
-0.00000000000011118671389559323,
0.00000000000037549577257259853,
0.00000000000013912841212197565,
0.00000000000010775743037572640,
0.00000000000029391859187648000,
-0.00000000000042790509060060774,
0.00000000000022774076114039555,
0.00000000000010849569622967912,
-0.00000000000023073801945705758,
0.00000000000015761203773969435,
0.00000000000003345710269544082,
-0.00000000000041525158063436123,
0.00000000000032655698896907146,
-0.00000000000044704265010452446,
0.00000000000034527647952039772,
-0.00000000000007048962392109746,
0.00000000000011776978751369214,
-0.00000000000010774341461609578,
0.00000000000021863343293215910,
0.00000000000024132639491333131,
0.00000000000039057462209830700,
-0.00000000000026570679203560751,
0.00000000000037135141919592021,
-0.00000000000017166921336082431,
-0.00000000000028658285157914353,
-0.00000000000023812542263446809,
0.00000000000006576659768580062,
-0.00000000000028210143846181267,
0.00000000000010701931762114254,
0.00000000000018119346366441110,
0.00000000000009840465278232627,
-0.00000000000033149150282752542,
-0.00000000000018302857356041668,
-0.00000000000016207400156744949,
0.00000000000048303314949553201,
-0.00000000000071560553172382115,
0.00000000000088821239518571855,
-0.00000000000030900580513238244,
-0.00000000000061076551972851496,
0.00000000000035659969663347830,
0.00000000000035782396591276383,
-0.00000000000046226087001544578,
0.00000000000062279762917225156,
0.00000000000072838947272065741,
0.00000000000026809646615211673,
-0.00000000000010960825046059278,
0.00000000000002311949383800537,
-0.00000000000058469058005299247,
-0.00000000000002103748251144494,
-0.00000000000023323182945587408,
-0.00000000000042333694288141916,
-0.00000000000043933937969737844,
0.00000000000041341647073835565,
0.00000000000006841763641591466,
0.00000000000047585534004430641,
0.00000000000083679678674757695,
-0.00000000000085763734646658640,
0.00000000000021913281229340092,
-0.00000000000062242842536431148,
-0.00000000000010983594325438430,
0.00000000000065310431377633651,
-0.00000000000047580199021710769,
-0.00000000000037854251265457040,
0.00000000000040939233218678664,
0.00000000000087424383914858291,
0.00000000000025218188456842882,
-0.00000000000003608131360422557,
-0.00000000000050518555924280902,
0.00000000000078699403323355317,
-0.00000000000067020876961949060,
0.00000000000016108575753932458,
0.00000000000058527188436251509,
-0.00000000000035246757297904791,
-0.00000000000018372084495629058,
0.00000000000088606689813494916,
0.00000000000066486268071468700,
0.00000000000063831615170646519,
0.00000000000025144230728376072,
-0.00000000000017239444525614834);
variable M, J:INTEGER;
variable F1, F2, G, Q, U, U2, V: REAL;
variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs
variable ONE: REAL := 1.0; --Made variable so no constant folding occurs
-- double logb(), ldexp();
variable U1:REAL;
begin
-- Check validity of argument
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = MATH_E ) then
return 1.0;
end if;
-- Argument reduction: 1 <= g < 2; x/2^m = g;
-- y = F*(1 + f/F) for |f| <= 2^-8
M := ILOGB(X);
G := LDEXP(X, -M);
J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding
F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512]
F2 := G - F1;
-- Approximate expansion for log(1+f2/F1) ~= u + q
G := 1.0/(2.0*F1+F2);
U := 2.0*F2*G;
V := U*U;
Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4)));
-- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8,
-- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits.
-- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750.
--
if ( J /= 0 or M /= 0) then
U1 := U + 513.0;
U1 := U1 - 513.0;
-- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero
-- u1 = u to 24 bits.
--
else
U1 := U;
--TRUNC(U1); --In c this is u1 = (double) (float) (u1)
end if;
U2 := (2.0*(F2 - F1*U1) - U1*F2) * G;
-- u1 + u2 = 2f/(2F+f) to extra precision.
-- log(x) = log(2^m*F1*(1+f2/F1)) =
-- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q);
-- (exact) + (tiny)
U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact
U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny
U2 := U2 + LOGF_TAIL(N)*REAL(M);
return (U1 + U2);
end LOG;
function LOG2 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG2(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = 2.0 ) then
return 1.0;
end if;
-- Compute value for general case
return ( MATH_LOG2_OF_E*LOG(X) );
end LOG2;
function LOG10 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG10(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = 10.0 ) then
return 1.0;
end if;
-- Compute value for general case
return ( MATH_LOG10_OF_E*LOG(X) );
end LOG10;
function LOG (X: in REAL; BASE: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = BASE ) then
return 1.0;
end if;
-- Compute value for general case
return ( LOG(X)/LOG(BASE));
end LOG;
function SIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) SIN(-X) = -SIN(X)
-- b) SIN(X) = X if ABS(X) < EPS
-- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS
-- d) SIN(MATH_PI_OVER_2 - X) = COS(X)
-- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS
-- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence criteria
variable N : INTEGER;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in SIN(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then
return 0.0;
end if;
if XLOCAL = MATH_PI_OVER_2 then
if NEGATIVE then
return -1.0;
else
return 1.0;
end if;
end if;
if XLOCAL = MATH_3_PI_OVER_2 then
if NEGATIVE then
return 1.0;
else
return -1.0;
end if;
end if;
if XLOCAL < EPS then
if NEGATIVE then
return -XLOCAL;
else
return XLOCAL;
end if;
else
if XLOCAL < BASE_EPS then
TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := MATH_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := MATH_2_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
TEMP := ABS(MATH_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
-- Compute value for general cases
if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then
VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1);
end if;
N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2));
case QUADRANT( N mod 4) is
when 0 =>
VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1);
when 1 =>
VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27,
ROTATION)(0);
when 2 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1);
when 3 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27,
ROTATION)(0);
end case;
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end SIN;
function COS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) COS(-X) = COS(X)
-- b) COS(X) = SIN(MATH_PI_OVER_2 - X)
-- c) COS(MATH_PI + X) = -COS(X)
-- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS
-- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
variable XLOCAL : REAL := ABS(X);
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in COS(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then
return 1.0;
end if;
if XLOCAL = MATH_PI then
return -1.0;
end if;
if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then
return 0.0;
end if;
TEMP := ABS(XLOCAL);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
TEMP := ABS(XLOCAL -MATH_2_PI);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
TEMP := ABS (XLOCAL - MATH_PI);
if TEMP < EPS then
return (-1.0 + 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
-- Compute value for general cases
return SIN(MATH_PI_OVER_2 - XLOCAL);
end COS;
function TAN (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) TAN(0.0) = 0.0
-- b) TAN(-X) = -TAN(X)
-- c) Returns REAL'LOW on error if X < 0.0
-- d) Returns REAL'HIGH on error if X > 0.0
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make 0.0 <= XLOCAL <= MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in TAN(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Check validity of argument
if XLOCAL = MATH_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'LOW);
else
return(REAL'HIGH);
end if;
end if;
if XLOCAL = MATH_3_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'HIGH);
else
return(REAL'LOW);
end if;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_PI then
return 0.0;
end if;
-- Compute value for general cases
VALUE := SIN(XLOCAL)/COS(XLOCAL);
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end TAN;
function ARCSIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCSIN(-X) = -ARCSIN(X)
-- b) Returns X on error
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
begin
-- Check validity of arguments
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCSIN(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
elsif XLOCAL = 1.0 then
if NEGATIVE then
return -MATH_PI_OVER_2;
else
return MATH_PI_OVER_2;
end if;
end if;
-- Compute value for general cases
if XLOCAL < 0.9 then
VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL)));
else
VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
end if;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end ARCSIN;
function ARCCOS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCCOS(-X) = MATH_PI - ARCCOS(X)
-- b) Returns X on error
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
begin
-- Check validity of argument
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCCOS(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 1.0 then
return 0.0;
elsif X = 0.0 then
return MATH_PI_OVER_2;
elsif X = -1.0 then
return MATH_PI;
end if;
-- Compute value for general cases
if XLOCAL > 0.9 then
VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
else
VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL));
end if;
if NEGATIVE then
VALUE := MATH_PI - VALUE;
end if;
return VALUE;
end ARCCOS;
function ARCTAN (Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCTAN(-Y) = -ARCTAN(Y)
-- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0
-- c) ARCTAN(Y) = Y for |Y| < EPS
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;
variable NEGATIVE : BOOLEAN := Y < 0.0;
variable RECIPROCAL : BOOLEAN;
variable YLOCAL : REAL := ABS(Y);
variable VALUE : REAL;
begin
-- Make argument |Y| <=1.0
if YLOCAL > 1.0 then
YLOCAL := 1.0/YLOCAL;
RECIPROCAL := TRUE;
else
RECIPROCAL := FALSE;
end if;
-- Compute value for special cases
if YLOCAL = 0.0 then
if RECIPROCAL then
if NEGATIVE then
return (-MATH_PI_OVER_2);
else
return (MATH_PI_OVER_2);
end if;
else
return 0.0;
end if;
end if;
if YLOCAL < EPS then
if NEGATIVE then
if RECIPROCAL then
return (-MATH_PI_OVER_2 + YLOCAL);
else
return -YLOCAL;
end if;
else
if RECIPROCAL then
return (MATH_PI_OVER_2 - YLOCAL);
else
return YLOCAL;
end if;
end if;
end if;
-- Compute value for general cases
VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2);
if RECIPROCAL then
VALUE := MATH_PI_OVER_2 - VALUE;
end if;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end ARCTAN;
function ARCTAN (Y : in REAL; X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
variable YLOCAL : REAL;
variable VALUE : REAL;
begin
-- Check validity of arguments
if (Y = 0.0 and X = 0.0 ) then
assert FALSE report
"ARCTAN(0.0, 0.0) is undetermined"
severity ERROR;
return 0.0;
end if;
-- Compute value for special cases
if Y = 0.0 then
if X > 0.0 then
return 0.0;
else
return MATH_PI;
end if;
end if;
if X = 0.0 then
if Y > 0.0 then
return MATH_PI_OVER_2;
else
return -MATH_PI_OVER_2;
end if;
end if;
-- Compute value for general cases
YLOCAL := ABS(Y/X);
VALUE := ARCTAN(YLOCAL);
if X < 0.0 then
VALUE := MATH_PI - VALUE;
end if;
if Y < 0.0 then
VALUE := -VALUE;
end if;
return VALUE;
end ARCTAN;
function SINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/2.0
-- b) SINH(-X) = SINH(X)
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)*0.5;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end SINH;
function COSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) + EXP(-X))/2.0
-- b) COSH(-X) = COSH(X)
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 1.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP + 1.0/TEMP)*0.5;
return VALUE;
end COSH;
function TANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X))
-- b) TANH(-X) = -TANH(X)
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP);
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end TANH;
function ARCSINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X + 1.0))
begin
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
return ( LOG( X + SQRT( X*X + 1.0)) );
end ARCSINH;
function ARCCOSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0
-- b) Returns X on error
begin
-- Check validity of arguments
if X < 1.0 then
assert FALSE
report "X < 1.0 in ARCCOSH(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 1.0 then
return 0.0;
end if;
-- Compute value for general cases
return ( LOG( X + SQRT( X*X - 1.0)));
end ARCCOSH;
function ARCTANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0
-- b) Returns X on error
begin
-- Check validity of arguments
if ABS(X) >= 1.0 then
assert FALSE
report "ABS(X) >= 1.0 in ARCTANH(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
return( 0.5*LOG( (1.0+X)/(1.0-X) ) );
end ARCTANH;
end MATH_REAL;
|
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_REAL)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package defines a standard for designers to use in
-- describing VHDL models that make use of common REAL constants
-- and common REAL elementary mathematical functions.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076-
-- 1993.
--
-- Notes:
-- No declarations or definitions shall be included in, or
-- excluded from, this package.
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_REAL.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_REAL package declaration. The purpose of the MATH_REAL
-- package body is to provide a guideline for implementations to
-- verify their implementation of MATH_REAL. Tool developers may
-- choose to implement the package body in the most efficient
-- manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
package MATH_REAL is
constant CopyRightNotice: STRING
:= "Copyright 1996 IEEE. All rights reserved.";
--
-- Constant Definitions
--
constant MATH_E : REAL := 2.71828_18284_59045_23536;
-- Value of e
constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
-- Value of 1/e
constant MATH_PI : REAL := 3.14159_26535_89793_23846;
-- Value of pi
constant MATH_2_PI : REAL := 6.28318_53071_79586_47693;
-- Value of 2*pi
constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
-- Value of 1/pi
constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
-- Value of pi/2
constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
-- Value of pi/3
constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
-- Value of pi/4
constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
-- Value 3*pi/2
constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
-- Natural log of 2
constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
-- Natural log of 10
constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
-- Log base 2 of e
constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765;
-- Log base 10 of e
constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880;
-- square root of 2
constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440;
-- square root of 1/2
constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730;
-- square root of pi
constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577;
-- Conversion factor from degree to radian
constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680;
-- Conversion factor from radian to degree
--
-- Function Declarations
--
function SIGN (X: in REAL ) return REAL;
-- Purpose:
-- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIGN(X)) <= 1.0
-- Notes:
-- None
function CEIL (X : in REAL ) return REAL;
-- Purpose:
-- Returns smallest INTEGER value (as REAL) not less than X
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CEIL(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function FLOOR (X : in REAL ) return REAL;
-- Purpose:
-- Returns largest INTEGER value (as REAL) not greater than X
-- Special values:
-- FLOOR(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- FLOOR(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function ROUND (X : in REAL ) return REAL;
-- Purpose:
-- Rounds X to the nearest integer value (as real). If X is
-- halfway between two integers, rounding is away from 0.0
-- Special values:
-- ROUND(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ROUND(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function TRUNC (X : in REAL ) return REAL;
-- Purpose:
-- Truncates X towards 0.0 and returns truncated value
-- Special values:
-- TRUNC(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- TRUNC(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function "MOD" (X, Y: in REAL ) return REAL;
-- Purpose:
-- Returns floating point modulus of X/Y, with the same sign as
-- Y, and absolute value less than the absolute value of Y, and
-- for some INTEGER value N the result satisfies the relation
-- X = Y*N + MOD(X,Y)
-- Special values:
-- None
-- Domain:
-- X in REAL; Y in REAL and Y /= 0.0
-- Error conditions:
-- Error if Y = 0.0
-- Range:
-- ABS(MOD(X,Y)) < ABS(Y)
-- Notes:
-- None
function REALMAX (X, Y : in REAL ) return REAL;
-- Purpose:
-- Returns the algebraically larger of X and Y
-- Special values:
-- REALMAX(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMAX(X,Y) is mathematically unbounded
-- Notes:
-- None
function REALMIN (X, Y : in REAL ) return REAL;
-- Purpose:
-- Returns the algebraically smaller of X and Y
-- Special values:
-- REALMIN(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMIN(X,Y) is mathematically unbounded
-- Notes:
-- None
procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL);
-- Purpose:
-- Returns, in X, a pseudo-random number with uniform
-- distribution in the open interval (0.0, 1.0).
-- Special values:
-- None
-- Domain:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
-- Error conditions:
-- Error if SEED1 or SEED2 outside of valid domain
-- Range:
-- 0.0 < X < 1.0
-- Notes:
-- a) The semantics for this function are described by the
-- algorithm published by Pierre L'Ecuyer in "Communications
-- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
-- The algorithm is based on the combination of two
-- multiplicative linear congruential generators for 32-bit
-- platforms.
--
-- b) Before the first call to UNIFORM, the seed values
-- (SEED1, SEED2) have to be initialized to values in the range
-- [1, 2147483562] and [1, 2147483398] respectively. The
-- seed values are modified after each call to UNIFORM.
--
-- c) This random number generator is portable for 32-bit
-- computers, and it has a period of ~2.30584*(10**18) for each
-- set of seed values.
--
-- d) For information on spectral tests for the algorithm, refer
-- to the L'Ecuyer article.
function SQRT (X : in REAL ) return REAL;
-- Purpose:
-- Returns square root of X
-- Special values:
-- SQRT(0.0) = 0.0
-- SQRT(1.0) = 1.0
-- Domain:
-- X >= 0.0
-- Error conditions:
-- Error if X < 0.0
-- Range:
-- SQRT(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of SQRT is
-- approximately given by:
-- SQRT(X) <= SQRT(REAL'HIGH)
function CBRT (X : in REAL ) return REAL;
-- Purpose:
-- Returns cube root of X
-- Special values:
-- CBRT(0.0) = 0.0
-- CBRT(1.0) = 1.0
-- CBRT(-1.0) = -1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CBRT(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of CBRT is approximately given by:
-- ABS(CBRT(X)) <= CBRT(REAL'HIGH)
function "**" (X : in INTEGER; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0
-- 0**Y = 0.0; Y > 0.0
-- X**1.0 = REAL(X); X >= 0
-- 1**Y = 1.0
-- Domain:
-- X > 0
-- X = 0 for Y > 0.0
-- X < 0 for Y = 0.0
-- Error conditions:
-- Error if X < 0 and Y /= 0.0
-- Error if X = 0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function "**" (X : in REAL; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0.0
-- 0.0**Y = 0.0; Y > 0.0
-- X**1.0 = X; X >= 0.0
-- 1.0**Y = 1.0
-- Domain:
-- X > 0.0
-- X = 0.0 for Y > 0.0
-- X < 0.0 for Y = 0.0
-- Error conditions:
-- Error if X < 0.0 and Y /= 0.0
-- Error if X = 0.0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function EXP (X : in REAL ) return REAL;
-- Purpose:
-- Returns e**X; where e = MATH_E
-- Special values:
-- EXP(0.0) = 1.0
-- EXP(1.0) = MATH_E
-- EXP(-1.0) = MATH_1_OVER_E
-- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
-- Domain:
-- X in REAL such that EXP(X) <= REAL'HIGH
-- Error conditions:
-- Error if X > LOG(REAL'HIGH)
-- Range:
-- EXP(X) >= 0.0
-- Notes:
-- a) The usable domain of EXP is approximately given by:
-- X <= LOG(REAL'HIGH)
function LOG (X : in REAL ) return REAL;
-- Purpose:
-- Returns natural logarithm of X
-- Special values:
-- LOG(1.0) = 0.0
-- LOG(MATH_E) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG is approximately given by:
-- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
function LOG2 (X : in REAL ) return REAL;
-- Purpose:
-- Returns logarithm base 2 of X
-- Special values:
-- LOG2(1.0) = 0.0
-- LOG2(2.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG2(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG2 is approximately given by:
-- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
function LOG10 (X : in REAL ) return REAL;
-- Purpose:
-- Returns logarithm base 10 of X
-- Special values:
-- LOG10(1.0) = 0.0
-- LOG10(10.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG10(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG10 is approximately given by:
-- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
function LOG (X: in REAL; BASE: in REAL) return REAL;
-- Purpose:
-- Returns logarithm base BASE of X
-- Special values:
-- LOG(1.0, BASE) = 0.0
-- LOG(BASE, BASE) = 1.0
-- Domain:
-- X > 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if X <= 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(X, BASE) is mathematically unbounded
-- Notes:
-- a) When BASE > 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
-- b) When 0.0 < BASE < 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
function SIN (X : in REAL ) return REAL;
-- Purpose:
-- Returns sine of X; X in radians
-- Special values:
-- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function COS ( X : in REAL ) return REAL;
-- Purpose:
-- Returns cosine of X; X in radians
-- Special values:
-- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
-- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(COS(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function TAN (X : in REAL ) return REAL;
-- Purpose:
-- Returns tangent of X; X in radians
-- Special values:
-- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL and
-- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
-- Error conditions:
-- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
-- INTEGER
-- Range:
-- TAN(X) is mathematically unbounded
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function ARCSIN (X : in REAL ) return REAL;
-- Purpose:
-- Returns inverse sine of X
-- Special values:
-- ARCSIN(0.0) = 0.0
-- ARCSIN(1.0) = MATH_PI_OVER_2
-- ARCSIN(-1.0) = -MATH_PI_OVER_2
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- ABS(ARCSIN(X) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCCOS (X : in REAL ) return REAL;
-- Purpose:
-- Returns inverse cosine of X
-- Special values:
-- ARCCOS(1.0) = 0.0
-- ARCCOS(0.0) = MATH_PI_OVER_2
-- ARCCOS(-1.0) = MATH_PI
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- 0.0 <= ARCCOS(X) <= MATH_PI
-- Notes:
-- None
function ARCTAN (Y : in REAL) return REAL;
-- Purpose:
-- Returns the value of the angle in radians of the point
-- (1.0, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0) = 0.0
-- Domain:
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCTAN (Y : in REAL; X : in REAL) return REAL;
-- Purpose:
-- Returns the principal value of the angle in radians of
-- the point (X, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0, X) = 0.0 if X > 0.0
-- ARCTAN(0.0, X) = MATH_PI if X < 0.0
-- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
-- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
-- Domain:
-- Y in REAL
-- X in REAL, X /= 0.0 when Y = 0.0
-- Error conditions:
-- Error if X = 0.0 and Y = 0.0
-- Range:
-- -MATH_PI < ARCTAN(Y,X) <= MATH_PI
-- Notes:
-- None
function SINH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic sine of X
-- Special values:
-- SINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- SINH(X) is mathematically unbounded
-- Notes:
-- a) The usable domain of SINH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function COSH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic cosine of X
-- Special values:
-- COSH(0.0) = 1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- COSH(X) >= 1.0
-- Notes:
-- a) The usable domain of COSH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function TANH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic tangent of X
-- Special values:
-- TANH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(TANH(X)) <= 1.0
-- Notes:
-- None
function ARCSINH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic sine of X
-- Special values:
-- ARCSINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ARCSINH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCSINH is approximately given by:
-- ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
function ARCCOSH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic cosine of X
-- Special values:
-- ARCCOSH(1.0) = 0.0
-- Domain:
-- X >= 1.0
-- Error conditions:
-- Error if X < 1.0
-- Range:
-- ARCCOSH(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of ARCCOSH is
-- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH)
function ARCTANH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic tangent of X
-- Special values:
-- ARCTANH(0.0) = 0.0
-- Domain:
-- ABS(X) < 1.0
-- Error conditions:
-- Error if ABS(X) >= 1.0
-- Range:
-- ARCTANH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCTANH is approximately given by:
-- ABS(ARCTANH(X)) < LOG(REAL'HIGH)
end MATH_REAL;
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_REAL)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package body is a nonnormative implementation of the
-- functionality defined in the MATH_REAL package declaration.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076
-- -1993.
--
-- Notes:
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_REAL.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_REAL package declaration. The purpose of the MATH_REAL
-- package body is to clarify such semantics and provide a
-- guideline for implementations to verify their implementation
-- of MATH_REAL. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
package body MATH_REAL is
--
-- Local Constants for Use in the Package Body Only
--
constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2
constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10
constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi
constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic
constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries
constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria
constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic
--
-- Local Type Declarations for Cordic Operations
--
type REAL_VECTOR is array (NATURAL range <>) of REAL;
type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL;
subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER);
subtype REAL_ARR_2 is REAL_VECTOR (0 to 1);
subtype REAL_ARR_3 is REAL_VECTOR (0 to 2);
subtype QUADRANT is INTEGER range 0 to 3;
type CORDIC_MODE_TYPE is (ROTATION, VECTORING);
--
-- Auxiliary Functions for Cordic Algorithms
--
function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL;
NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is
-- Description:
-- Returns power of two for a vector of values
-- Notes:
-- None
--
variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES);
variable TEMP : REAL := INITIAL_VALUE;
variable FLAG : BOOLEAN := TRUE;
begin
for I in 0 to NUMBER_OF_VALUES loop
V(I) := TEMP;
for P in D'RANGE loop
if I = D(P) then
FLAG := FALSE;
exit;
end if;
end loop;
if FLAG then
TEMP := TEMP/2.0;
end if;
FLAG := TRUE;
end loop;
return V;
end POWER_OF_2_SERIES;
constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES(
NATURAL_VECTOR'(100, 90),1.0,
MAX_ITER);
constant EPSILON : REAL_VECTOR_N := (
7.8539816339744827e-01,
4.6364760900080606e-01,
2.4497866312686413e-01,
1.2435499454676144e-01,
6.2418809995957351e-02,
3.1239833430268277e-02,
1.5623728620476830e-02,
7.8123410601011116e-03,
3.9062301319669717e-03,
1.9531225164788189e-03,
9.7656218955931937e-04,
4.8828121119489829e-04,
2.4414062014936175e-04,
1.2207031189367021e-04,
6.1035156174208768e-05,
3.0517578115526093e-05,
1.5258789061315760e-05,
7.6293945311019699e-06,
3.8146972656064960e-06,
1.9073486328101870e-06,
9.5367431640596080e-07,
4.7683715820308876e-07,
2.3841857910155801e-07,
1.1920928955078067e-07,
5.9604644775390553e-08,
2.9802322387695303e-08,
1.4901161193847654e-08,
7.4505805969238281e-09
);
function CORDIC ( X0 : in REAL;
Y0 : in REAL;
Z0 : in REAL;
N : in NATURAL; -- Precision factor
CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0)
-- or vectoring (Y -> 0)
) return REAL_ARR_3 is
-- Description:
-- Compute cordic values
-- Notes:
-- None
variable X : REAL := X0;
variable Y : REAL := Y0;
variable Z : REAL := Z0;
variable X_TEMP : REAL;
begin
if CORDIC_MODE = ROTATION then
for K in 0 to N loop
X_TEMP := X;
if ( Z >= 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
else
for K in 0 to N loop
X_TEMP := X;
if ( Y < 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
end if;
return REAL_ARR_3'(X, Y, Z);
end CORDIC;
--
-- Bodies for Global Mathematical Functions Start Here
--
function SIGN (X: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
if ( X > 0.0 ) then
return 1.0;
elsif ( X < 0.0 ) then
return -1.0;
else
return 0.0;
end if;
end SIGN;
function CEIL (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is X <= LARGE
-- c) Returns X if ABS(X) >= LARGE
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
begin
if ABS(X) >= LARGE then
return X;
end if;
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
if X > 0.0 then
if RD >= X then
return RD;
else
return RD + 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD <= X then
return RD + 1.0;
else
return RD;
end if;
end if;
end CEIL;
function FLOOR (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is ABS(X) <= LARGE
-- c) Returns X if ABS(X) >= LARGE
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
begin
if ABS( X ) >= LARGE then
return X;
end if;
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
if X > 0.0 then
if RD <= X then
return RD;
else
return RD - 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD >= X then
return RD - 1.0;
else
return RD;
end if;
end if;
end FLOOR;
function ROUND (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X + 0.5) if X > 0
-- c) Returns CEIL(X - 0.5) if X < 0
begin
if X > 0.0 then
return FLOOR(X + 0.5);
elsif X < 0.0 then
return CEIL( X - 0.5);
else
return 0.0;
end if;
end ROUND;
function TRUNC (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X) if X > 0
-- c) Returns CEIL(X) if X < 0
begin
if X > 0.0 then
return FLOOR(X);
elsif X < 0.0 then
return CEIL( X);
else
return 0.0;
end if;
end TRUNC;
function "MOD" (X, Y: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
variable XNEGATIVE : BOOLEAN := X < 0.0;
variable YNEGATIVE : BOOLEAN := Y < 0.0;
variable VALUE : REAL;
begin
-- Check validity of input arguments
if (Y = 0.0) then
assert FALSE
report "MOD(X, 0.0) is undefined"
severity ERROR;
return 0.0;
end if;
-- Compute value
if ( XNEGATIVE ) then
if ( YNEGATIVE ) then
VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
end if;
else
if ( YNEGATIVE ) then
VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
end if;
end if;
return VALUE;
end "MOD";
function REALMAX (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMAX(X,Y) = X when X = Y
--
begin
if X >= Y then
return X;
else
return Y;
end if;
end REALMAX;
function REALMIN (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMIN(X,Y) = X when X = Y
--
begin
if X <= Y then
return X;
else
return Y;
end if;
end REALMIN;
procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL)
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
--
variable Z, K: INTEGER;
variable TSEED1 : INTEGER := INTEGER'(SEED1);
variable TSEED2 : INTEGER := INTEGER'(SEED2);
begin
-- Check validity of arguments
if SEED1 > 2147483562 then
assert FALSE
report "SEED1 > 2147483562 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
if SEED2 > 2147483398 then
assert FALSE
report "SEED2 > 2147483398 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
-- Compute new seed values and pseudo-random number
K := TSEED1/53668;
TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211;
if TSEED1 < 0 then
TSEED1 := TSEED1 + 2147483563;
end if;
K := TSEED2/52774;
TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791;
if TSEED2 < 0 then
TSEED2 := TSEED2 + 2147483399;
end if;
Z := TSEED1 - TSEED2;
if Z < 1 then
Z := Z + 2147483562;
end if;
-- Get output values
SEED1 := POSITIVE'(TSEED1);
SEED2 := POSITIVE'(TSEED2);
X := REAL(Z)*4.656613e-10;
end UNIFORM;
function SQRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = 0.5*[F(n) + x/F(n)]
-- b) Returns 0.0 on error
--
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor
variable INIVAL: REAL;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
begin
-- Check validity of argument
if ( X < 0.0 ) then
assert FALSE
report "X < 0.0 in SQRT(X)"
severity ERROR;
return 0.0;
end if;
-- Get the square root for special cases
if X = 0.0 then
return 0.0;
else
if ( X = 1.0 ) then
return 1.0;
end if;
end if;
-- Get the square root for general cases
INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise
OLDVAL := INIVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
-- Check for relative and absolute error and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT) ) loop
OLDVAL := NEWVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
COUNT := COUNT + 1;
end loop;
return NEWVAL;
end SQRT;
function CBRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2];
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
variable INIVAL: REAL;
variable XLOCAL : REAL := X;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
begin
-- Compute root for special cases
if X = 0.0 then
return 0.0;
elsif ( X = 1.0 ) then
return 1.0;
else
if X = -1.0 then
return -1.0;
end if;
end if;
-- Compute root for general cases
if NEGATIVE then
XLOCAL := -X;
end if;
INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but
-- imprecise
OLDVAL := INIVAL;
NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR
(ABS(NEWVAL - OLDVAL) > EPS ) ) AND
( COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
COUNT := COUNT + 1;
end loop;
if NEGATIVE then
NEWVAL := -NEWVAL;
end if;
return NEWVAL;
end CBRT;
function "**" (X : in INTEGER; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
begin
-- Check validity of argument
if ( ( X < 0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
if ( ( X = 0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
-- Get value for special cases
if ( X = 0 and Y > 0.0 ) then
return 0.0;
end if;
if ( X = 1 ) then
return 1.0;
end if;
if ( Y = 0.0 and X /= 0 ) then
return 1.0;
end if;
if ( Y = 1.0) then
return (REAL(X));
end if;
-- Get value for general case
return EXP (Y * LOG (REAL(X)));
end "**";
function "**" (X : in REAL; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
begin
-- Check validity of argument
if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0.0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0.0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
-- Get value for special cases
if ( X = 0.0 and Y > 0.0 ) then
return 0.0;
end if;
if ( X = 1.0 ) then
return 1.0;
end if;
if ( Y = 0.0 and X /= 0.0 ) then
return 1.0;
end if;
if ( Y = 1.0) then
return (X);
end if;
-- Get value for general case
return EXP (Y * LOG (X));
end "**";
function EXP (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) This function computes the exponential using the following
-- series:
-- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0
-- and reduces argument X to take advantage of exp(x+y) =
-- exp(x)*exp(y)
--
-- b) This implementation limits X to be less than LOG(REAL'HIGH)
-- to avoid overflow. Returns REAL'HIGH when X reaches that
-- limit
--
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria
variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument
variable XLOCAL : REAL := ABS(X); -- Use positive value
variable OLDVAL: REAL ;
variable COUNT: INTEGER ;
variable NEWVAL: REAL ;
variable LAST_TERM: REAL ;
variable FACTOR : REAL := 1.0;
begin
-- Compute value for special cases
if X = 0.0 then
return 1.0;
end if;
if XLOCAL = 1.0 then
if RECIPROCAL then
return MATH_1_OVER_E;
else
return MATH_E;
end if;
end if;
if XLOCAL = 2.0 then
if RECIPROCAL then
return 1.0/MATH_E_P2;
else
return MATH_E_P2;
end if;
end if;
if XLOCAL = 10.0 then
if RECIPROCAL then
return 1.0/MATH_E_P10;
else
return MATH_E_P10;
end if;
end if;
if XLOCAL > LOG(REAL'HIGH) then
if RECIPROCAL then
return 0.0;
else
assert FALSE
report "X > LOG(REAL'HIGH) in EXP(X)"
severity NOTE;
return REAL'HIGH;
end if;
end if;
-- Reduce argument to ABS(X) < 1.0
while XLOCAL > 10.0 loop
XLOCAL := XLOCAL - 10.0;
FACTOR := FACTOR*MATH_E_P10;
end loop;
while XLOCAL > 1.0 loop
XLOCAL := XLOCAL - 1.0;
FACTOR := FACTOR*MATH_E;
end loop;
-- Compute value for case 0 < XLOCAL < 1
OLDVAL := 1.0;
LAST_TERM := XLOCAL;
NEWVAL:= OLDVAL + LAST_TERM;
COUNT := 2;
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT)));
NEWVAL := OLDVAL + LAST_TERM;
COUNT := COUNT + 1;
end loop;
-- Compute final value using exp(x+y) = exp(x)*exp(y)
NEWVAL := NEWVAL*FACTOR;
if RECIPROCAL then
NEWVAL := 1.0/NEWVAL;
end if;
return NEWVAL;
end EXP;
--
-- Auxiliary Functions to Compute LOG
--
function ILOGB(X: in REAL) return INTEGER IS
-- Description:
-- Returns n such that -1 <= ABS(X)/2^n < 2
-- Notes:
-- None
variable N: INTEGER := 0;
variable Y: REAL := ABS(X);
begin
if(Y = 1.0 or Y = 0.0) then
return 0;
end if;
if( Y > 1.0) then
while Y >= 2.0 loop
Y := Y/2.0;
N := N+1;
end loop;
return N;
end if;
-- O < Y < 1
while Y < 1.0 loop
Y := Y*2.0;
N := N -1;
end loop;
return N;
end ILOGB;
function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS
-- Description:
-- Returns X*2^n
-- Notes:
-- None
begin
return X*(2.0 ** N);
end LDEXP;
function LOG (X : in REAL ) return REAL IS
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
--
-- Notes:
-- a) Returns REAL'LOW on error
--
-- Copyright (c) 1992 Regents of the University of California.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. All advertising materials mentioning features or use of this
-- software must display the following acknowledgement:
-- This product includes software developed by the University of
-- California, Berkeley and its contributors.
-- 4. Neither the name of the University nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-- DAMAGE.
--
-- NOTE: This VHDL version was generated using the C version of the
-- original function by the IEEE VHDL Mathematical Package
-- Working Group (CS/JT)
constant N: INTEGER := 128;
-- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128.
-- Used for generation of extend precision logarithms.
-- The constant 35184372088832 is 2^45, so the divide is exact.
-- It ensures correct reading of logF_head, even for inaccurate
-- decimal-to-binary conversion routines. (Everybody gets the
-- right answer for INTEGERs less than 2^53.)
-- Values for LOG(F) were generated using error < 10^-57 absolute
-- with the bc -l package.
type REAL_VECTOR is array (NATURAL range <>) of REAL;
constant A1:REAL := 0.08333333333333178827;
constant A2:REAL := 0.01250000000377174923;
constant A3:REAL := 0.002232139987919447809;
constant A4:REAL := 0.0004348877777076145742;
constant LOGF_HEAD: REAL_VECTOR(0 TO N) := (
0.0,
0.007782140442060381246,
0.015504186535963526694,
0.023167059281547608406,
0.030771658666765233647,
0.038318864302141264488,
0.045809536031242714670,
0.053244514518837604555,
0.060624621816486978786,
0.067950661908525944454,
0.075223421237524235039,
0.082443669210988446138,
0.089612158689760690322,
0.096729626458454731618,
0.103796793681567578460,
0.110814366340264314203,
0.117783035656430001836,
0.124703478501032805070,
0.131576357788617315236,
0.138402322859292326029,
0.145182009844575077295,
0.151916042025732167530,
0.158605030176659056451,
0.165249572895390883786,
0.171850256926518341060,
0.178407657472689606947,
0.184922338493834104156,
0.191394852999565046047,
0.197825743329758552135,
0.204215541428766300668,
0.210564769107350002741,
0.216873938300523150246,
0.223143551314024080056,
0.229374101064877322642,
0.235566071312860003672,
0.241719936886966024758,
0.247836163904594286577,
0.253915209980732470285,
0.259957524436686071567,
0.265963548496984003577,
0.271933715484010463114,
0.277868451003087102435,
0.283768173130738432519,
0.289633292582948342896,
0.295464212893421063199,
0.301261330578199704177,
0.307025035294827830512,
0.312755710004239517729,
0.318453731118097493890,
0.324119468654316733591,
0.329753286372579168528,
0.335355541920762334484,
0.340926586970454081892,
0.346466767346100823488,
0.351976423156884266063,
0.357455888922231679316,
0.362905493689140712376,
0.368325561158599157352,
0.373716409793814818840,
0.379078352934811846353,
0.384411698910298582632,
0.389716751140440464951,
0.394993808240542421117,
0.400243164127459749579,
0.405465108107819105498,
0.410659924985338875558,
0.415827895143593195825,
0.420969294644237379543,
0.426084395310681429691,
0.431173464818130014464,
0.436236766774527495726,
0.441274560805140936281,
0.446287102628048160113,
0.451274644139630254358,
0.456237433481874177232,
0.461175715122408291790,
0.466089729924533457960,
0.470979715219073113985,
0.475845904869856894947,
0.480688529345570714212,
0.485507815781602403149,
0.490303988045525329653,
0.495077266798034543171,
0.499827869556611403822,
0.504556010751912253908,
0.509261901790523552335,
0.513945751101346104405,
0.518607764208354637958,
0.523248143765158602036,
0.527867089620485785417,
0.532464798869114019908,
0.537041465897345915436,
0.541597282432121573947,
0.546132437597407260909,
0.550647117952394182793,
0.555141507540611200965,
0.559615787935399566777,
0.564070138285387656651,
0.568504735352689749561,
0.572919753562018740922,
0.577315365035246941260,
0.581691739635061821900,
0.586049045003164792433,
0.590387446602107957005,
0.594707107746216934174,
0.599008189645246602594,
0.603290851438941899687,
0.607555250224322662688,
0.611801541106615331955,
0.616029877215623855590,
0.620240409751204424537,
0.624433288012369303032,
0.628608659422752680256,
0.632766669570628437213,
0.636907462236194987781,
0.641031179420679109171,
0.645137961373620782978,
0.649227946625615004450,
0.653301272011958644725,
0.657358072709030238911,
0.661398482245203922502,
0.665422632544505177065,
0.669430653942981734871,
0.673422675212350441142,
0.677398823590920073911,
0.681359224807238206267,
0.685304003098281100392,
0.689233281238557538017,
0.693147180560117703862);
constant LOGF_TAIL: REAL_VECTOR(0 TO N) := (
0.0,
-0.00000000000000543229938420049,
0.00000000000000172745674997061,
-0.00000000000001323017818229233,
-0.00000000000001154527628289872,
-0.00000000000000466529469958300,
0.00000000000005148849572685810,
-0.00000000000002532168943117445,
-0.00000000000005213620639136504,
-0.00000000000001819506003016881,
0.00000000000006329065958724544,
0.00000000000008614512936087814,
-0.00000000000007355770219435028,
0.00000000000009638067658552277,
0.00000000000007598636597194141,
0.00000000000002579999128306990,
-0.00000000000004654729747598444,
-0.00000000000007556920687451336,
0.00000000000010195735223708472,
-0.00000000000017319034406422306,
-0.00000000000007718001336828098,
0.00000000000010980754099855238,
-0.00000000000002047235780046195,
-0.00000000000008372091099235912,
0.00000000000014088127937111135,
0.00000000000012869017157588257,
0.00000000000017788850778198106,
0.00000000000006440856150696891,
0.00000000000016132822667240822,
-0.00000000000007540916511956188,
-0.00000000000000036507188831790,
0.00000000000009120937249914984,
0.00000000000018567570959796010,
-0.00000000000003149265065191483,
-0.00000000000009309459495196889,
0.00000000000017914338601329117,
-0.00000000000001302979717330866,
0.00000000000023097385217586939,
0.00000000000023999540484211737,
0.00000000000015393776174455408,
-0.00000000000036870428315837678,
0.00000000000036920375082080089,
-0.00000000000009383417223663699,
0.00000000000009433398189512690,
0.00000000000041481318704258568,
-0.00000000000003792316480209314,
0.00000000000008403156304792424,
-0.00000000000034262934348285429,
0.00000000000043712191957429145,
-0.00000000000010475750058776541,
-0.00000000000011118671389559323,
0.00000000000037549577257259853,
0.00000000000013912841212197565,
0.00000000000010775743037572640,
0.00000000000029391859187648000,
-0.00000000000042790509060060774,
0.00000000000022774076114039555,
0.00000000000010849569622967912,
-0.00000000000023073801945705758,
0.00000000000015761203773969435,
0.00000000000003345710269544082,
-0.00000000000041525158063436123,
0.00000000000032655698896907146,
-0.00000000000044704265010452446,
0.00000000000034527647952039772,
-0.00000000000007048962392109746,
0.00000000000011776978751369214,
-0.00000000000010774341461609578,
0.00000000000021863343293215910,
0.00000000000024132639491333131,
0.00000000000039057462209830700,
-0.00000000000026570679203560751,
0.00000000000037135141919592021,
-0.00000000000017166921336082431,
-0.00000000000028658285157914353,
-0.00000000000023812542263446809,
0.00000000000006576659768580062,
-0.00000000000028210143846181267,
0.00000000000010701931762114254,
0.00000000000018119346366441110,
0.00000000000009840465278232627,
-0.00000000000033149150282752542,
-0.00000000000018302857356041668,
-0.00000000000016207400156744949,
0.00000000000048303314949553201,
-0.00000000000071560553172382115,
0.00000000000088821239518571855,
-0.00000000000030900580513238244,
-0.00000000000061076551972851496,
0.00000000000035659969663347830,
0.00000000000035782396591276383,
-0.00000000000046226087001544578,
0.00000000000062279762917225156,
0.00000000000072838947272065741,
0.00000000000026809646615211673,
-0.00000000000010960825046059278,
0.00000000000002311949383800537,
-0.00000000000058469058005299247,
-0.00000000000002103748251144494,
-0.00000000000023323182945587408,
-0.00000000000042333694288141916,
-0.00000000000043933937969737844,
0.00000000000041341647073835565,
0.00000000000006841763641591466,
0.00000000000047585534004430641,
0.00000000000083679678674757695,
-0.00000000000085763734646658640,
0.00000000000021913281229340092,
-0.00000000000062242842536431148,
-0.00000000000010983594325438430,
0.00000000000065310431377633651,
-0.00000000000047580199021710769,
-0.00000000000037854251265457040,
0.00000000000040939233218678664,
0.00000000000087424383914858291,
0.00000000000025218188456842882,
-0.00000000000003608131360422557,
-0.00000000000050518555924280902,
0.00000000000078699403323355317,
-0.00000000000067020876961949060,
0.00000000000016108575753932458,
0.00000000000058527188436251509,
-0.00000000000035246757297904791,
-0.00000000000018372084495629058,
0.00000000000088606689813494916,
0.00000000000066486268071468700,
0.00000000000063831615170646519,
0.00000000000025144230728376072,
-0.00000000000017239444525614834);
variable M, J:INTEGER;
variable F1, F2, G, Q, U, U2, V: REAL;
variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs
variable ONE: REAL := 1.0; --Made variable so no constant folding occurs
-- double logb(), ldexp();
variable U1:REAL;
begin
-- Check validity of argument
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = MATH_E ) then
return 1.0;
end if;
-- Argument reduction: 1 <= g < 2; x/2^m = g;
-- y = F*(1 + f/F) for |f| <= 2^-8
M := ILOGB(X);
G := LDEXP(X, -M);
J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding
F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512]
F2 := G - F1;
-- Approximate expansion for log(1+f2/F1) ~= u + q
G := 1.0/(2.0*F1+F2);
U := 2.0*F2*G;
V := U*U;
Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4)));
-- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8,
-- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits.
-- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750.
--
if ( J /= 0 or M /= 0) then
U1 := U + 513.0;
U1 := U1 - 513.0;
-- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero
-- u1 = u to 24 bits.
--
else
U1 := U;
--TRUNC(U1); --In c this is u1 = (double) (float) (u1)
end if;
U2 := (2.0*(F2 - F1*U1) - U1*F2) * G;
-- u1 + u2 = 2f/(2F+f) to extra precision.
-- log(x) = log(2^m*F1*(1+f2/F1)) =
-- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q);
-- (exact) + (tiny)
U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact
U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny
U2 := U2 + LOGF_TAIL(N)*REAL(M);
return (U1 + U2);
end LOG;
function LOG2 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG2(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = 2.0 ) then
return 1.0;
end if;
-- Compute value for general case
return ( MATH_LOG2_OF_E*LOG(X) );
end LOG2;
function LOG10 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG10(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = 10.0 ) then
return 1.0;
end if;
-- Compute value for general case
return ( MATH_LOG10_OF_E*LOG(X) );
end LOG10;
function LOG (X: in REAL; BASE: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = BASE ) then
return 1.0;
end if;
-- Compute value for general case
return ( LOG(X)/LOG(BASE));
end LOG;
function SIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) SIN(-X) = -SIN(X)
-- b) SIN(X) = X if ABS(X) < EPS
-- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS
-- d) SIN(MATH_PI_OVER_2 - X) = COS(X)
-- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS
-- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence criteria
variable N : INTEGER;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in SIN(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then
return 0.0;
end if;
if XLOCAL = MATH_PI_OVER_2 then
if NEGATIVE then
return -1.0;
else
return 1.0;
end if;
end if;
if XLOCAL = MATH_3_PI_OVER_2 then
if NEGATIVE then
return 1.0;
else
return -1.0;
end if;
end if;
if XLOCAL < EPS then
if NEGATIVE then
return -XLOCAL;
else
return XLOCAL;
end if;
else
if XLOCAL < BASE_EPS then
TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := MATH_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := MATH_2_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
TEMP := ABS(MATH_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
-- Compute value for general cases
if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then
VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1);
end if;
N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2));
case QUADRANT( N mod 4) is
when 0 =>
VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1);
when 1 =>
VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27,
ROTATION)(0);
when 2 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1);
when 3 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27,
ROTATION)(0);
end case;
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end SIN;
function COS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) COS(-X) = COS(X)
-- b) COS(X) = SIN(MATH_PI_OVER_2 - X)
-- c) COS(MATH_PI + X) = -COS(X)
-- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS
-- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
variable XLOCAL : REAL := ABS(X);
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in COS(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then
return 1.0;
end if;
if XLOCAL = MATH_PI then
return -1.0;
end if;
if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then
return 0.0;
end if;
TEMP := ABS(XLOCAL);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
TEMP := ABS(XLOCAL -MATH_2_PI);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
TEMP := ABS (XLOCAL - MATH_PI);
if TEMP < EPS then
return (-1.0 + 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
-- Compute value for general cases
return SIN(MATH_PI_OVER_2 - XLOCAL);
end COS;
function TAN (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) TAN(0.0) = 0.0
-- b) TAN(-X) = -TAN(X)
-- c) Returns REAL'LOW on error if X < 0.0
-- d) Returns REAL'HIGH on error if X > 0.0
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make 0.0 <= XLOCAL <= MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in TAN(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Check validity of argument
if XLOCAL = MATH_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'LOW);
else
return(REAL'HIGH);
end if;
end if;
if XLOCAL = MATH_3_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'HIGH);
else
return(REAL'LOW);
end if;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_PI then
return 0.0;
end if;
-- Compute value for general cases
VALUE := SIN(XLOCAL)/COS(XLOCAL);
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end TAN;
function ARCSIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCSIN(-X) = -ARCSIN(X)
-- b) Returns X on error
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
begin
-- Check validity of arguments
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCSIN(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
elsif XLOCAL = 1.0 then
if NEGATIVE then
return -MATH_PI_OVER_2;
else
return MATH_PI_OVER_2;
end if;
end if;
-- Compute value for general cases
if XLOCAL < 0.9 then
VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL)));
else
VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
end if;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end ARCSIN;
function ARCCOS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCCOS(-X) = MATH_PI - ARCCOS(X)
-- b) Returns X on error
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
begin
-- Check validity of argument
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCCOS(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 1.0 then
return 0.0;
elsif X = 0.0 then
return MATH_PI_OVER_2;
elsif X = -1.0 then
return MATH_PI;
end if;
-- Compute value for general cases
if XLOCAL > 0.9 then
VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
else
VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL));
end if;
if NEGATIVE then
VALUE := MATH_PI - VALUE;
end if;
return VALUE;
end ARCCOS;
function ARCTAN (Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCTAN(-Y) = -ARCTAN(Y)
-- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0
-- c) ARCTAN(Y) = Y for |Y| < EPS
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;
variable NEGATIVE : BOOLEAN := Y < 0.0;
variable RECIPROCAL : BOOLEAN;
variable YLOCAL : REAL := ABS(Y);
variable VALUE : REAL;
begin
-- Make argument |Y| <=1.0
if YLOCAL > 1.0 then
YLOCAL := 1.0/YLOCAL;
RECIPROCAL := TRUE;
else
RECIPROCAL := FALSE;
end if;
-- Compute value for special cases
if YLOCAL = 0.0 then
if RECIPROCAL then
if NEGATIVE then
return (-MATH_PI_OVER_2);
else
return (MATH_PI_OVER_2);
end if;
else
return 0.0;
end if;
end if;
if YLOCAL < EPS then
if NEGATIVE then
if RECIPROCAL then
return (-MATH_PI_OVER_2 + YLOCAL);
else
return -YLOCAL;
end if;
else
if RECIPROCAL then
return (MATH_PI_OVER_2 - YLOCAL);
else
return YLOCAL;
end if;
end if;
end if;
-- Compute value for general cases
VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2);
if RECIPROCAL then
VALUE := MATH_PI_OVER_2 - VALUE;
end if;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end ARCTAN;
function ARCTAN (Y : in REAL; X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
variable YLOCAL : REAL;
variable VALUE : REAL;
begin
-- Check validity of arguments
if (Y = 0.0 and X = 0.0 ) then
assert FALSE report
"ARCTAN(0.0, 0.0) is undetermined"
severity ERROR;
return 0.0;
end if;
-- Compute value for special cases
if Y = 0.0 then
if X > 0.0 then
return 0.0;
else
return MATH_PI;
end if;
end if;
if X = 0.0 then
if Y > 0.0 then
return MATH_PI_OVER_2;
else
return -MATH_PI_OVER_2;
end if;
end if;
-- Compute value for general cases
YLOCAL := ABS(Y/X);
VALUE := ARCTAN(YLOCAL);
if X < 0.0 then
VALUE := MATH_PI - VALUE;
end if;
if Y < 0.0 then
VALUE := -VALUE;
end if;
return VALUE;
end ARCTAN;
function SINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/2.0
-- b) SINH(-X) = SINH(X)
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)*0.5;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end SINH;
function COSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) + EXP(-X))/2.0
-- b) COSH(-X) = COSH(X)
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 1.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP + 1.0/TEMP)*0.5;
return VALUE;
end COSH;
function TANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X))
-- b) TANH(-X) = -TANH(X)
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP);
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end TANH;
function ARCSINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X + 1.0))
begin
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
return ( LOG( X + SQRT( X*X + 1.0)) );
end ARCSINH;
function ARCCOSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0
-- b) Returns X on error
begin
-- Check validity of arguments
if X < 1.0 then
assert FALSE
report "X < 1.0 in ARCCOSH(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 1.0 then
return 0.0;
end if;
-- Compute value for general cases
return ( LOG( X + SQRT( X*X - 1.0)));
end ARCCOSH;
function ARCTANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0
-- b) Returns X on error
begin
-- Check validity of arguments
if ABS(X) >= 1.0 then
assert FALSE
report "ABS(X) >= 1.0 in ARCTANH(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
return( 0.5*LOG( (1.0+X)/(1.0-X) ) );
end ARCTANH;
end MATH_REAL;
|
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_REAL)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package defines a standard for designers to use in
-- describing VHDL models that make use of common REAL constants
-- and common REAL elementary mathematical functions.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076-
-- 1993.
--
-- Notes:
-- No declarations or definitions shall be included in, or
-- excluded from, this package.
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_REAL.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_REAL package declaration. The purpose of the MATH_REAL
-- package body is to provide a guideline for implementations to
-- verify their implementation of MATH_REAL. Tool developers may
-- choose to implement the package body in the most efficient
-- manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
package MATH_REAL is
constant CopyRightNotice: STRING
:= "Copyright 1996 IEEE. All rights reserved.";
--
-- Constant Definitions
--
constant MATH_E : REAL := 2.71828_18284_59045_23536;
-- Value of e
constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
-- Value of 1/e
constant MATH_PI : REAL := 3.14159_26535_89793_23846;
-- Value of pi
constant MATH_2_PI : REAL := 6.28318_53071_79586_47693;
-- Value of 2*pi
constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
-- Value of 1/pi
constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
-- Value of pi/2
constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
-- Value of pi/3
constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
-- Value of pi/4
constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
-- Value 3*pi/2
constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
-- Natural log of 2
constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
-- Natural log of 10
constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
-- Log base 2 of e
constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765;
-- Log base 10 of e
constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880;
-- square root of 2
constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440;
-- square root of 1/2
constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730;
-- square root of pi
constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577;
-- Conversion factor from degree to radian
constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680;
-- Conversion factor from radian to degree
--
-- Function Declarations
--
function SIGN (X: in REAL ) return REAL;
-- Purpose:
-- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIGN(X)) <= 1.0
-- Notes:
-- None
function CEIL (X : in REAL ) return REAL;
-- Purpose:
-- Returns smallest INTEGER value (as REAL) not less than X
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CEIL(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function FLOOR (X : in REAL ) return REAL;
-- Purpose:
-- Returns largest INTEGER value (as REAL) not greater than X
-- Special values:
-- FLOOR(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- FLOOR(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function ROUND (X : in REAL ) return REAL;
-- Purpose:
-- Rounds X to the nearest integer value (as real). If X is
-- halfway between two integers, rounding is away from 0.0
-- Special values:
-- ROUND(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ROUND(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function TRUNC (X : in REAL ) return REAL;
-- Purpose:
-- Truncates X towards 0.0 and returns truncated value
-- Special values:
-- TRUNC(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- TRUNC(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function "MOD" (X, Y: in REAL ) return REAL;
-- Purpose:
-- Returns floating point modulus of X/Y, with the same sign as
-- Y, and absolute value less than the absolute value of Y, and
-- for some INTEGER value N the result satisfies the relation
-- X = Y*N + MOD(X,Y)
-- Special values:
-- None
-- Domain:
-- X in REAL; Y in REAL and Y /= 0.0
-- Error conditions:
-- Error if Y = 0.0
-- Range:
-- ABS(MOD(X,Y)) < ABS(Y)
-- Notes:
-- None
function REALMAX (X, Y : in REAL ) return REAL;
-- Purpose:
-- Returns the algebraically larger of X and Y
-- Special values:
-- REALMAX(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMAX(X,Y) is mathematically unbounded
-- Notes:
-- None
function REALMIN (X, Y : in REAL ) return REAL;
-- Purpose:
-- Returns the algebraically smaller of X and Y
-- Special values:
-- REALMIN(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMIN(X,Y) is mathematically unbounded
-- Notes:
-- None
procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL);
-- Purpose:
-- Returns, in X, a pseudo-random number with uniform
-- distribution in the open interval (0.0, 1.0).
-- Special values:
-- None
-- Domain:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
-- Error conditions:
-- Error if SEED1 or SEED2 outside of valid domain
-- Range:
-- 0.0 < X < 1.0
-- Notes:
-- a) The semantics for this function are described by the
-- algorithm published by Pierre L'Ecuyer in "Communications
-- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
-- The algorithm is based on the combination of two
-- multiplicative linear congruential generators for 32-bit
-- platforms.
--
-- b) Before the first call to UNIFORM, the seed values
-- (SEED1, SEED2) have to be initialized to values in the range
-- [1, 2147483562] and [1, 2147483398] respectively. The
-- seed values are modified after each call to UNIFORM.
--
-- c) This random number generator is portable for 32-bit
-- computers, and it has a period of ~2.30584*(10**18) for each
-- set of seed values.
--
-- d) For information on spectral tests for the algorithm, refer
-- to the L'Ecuyer article.
function SQRT (X : in REAL ) return REAL;
-- Purpose:
-- Returns square root of X
-- Special values:
-- SQRT(0.0) = 0.0
-- SQRT(1.0) = 1.0
-- Domain:
-- X >= 0.0
-- Error conditions:
-- Error if X < 0.0
-- Range:
-- SQRT(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of SQRT is
-- approximately given by:
-- SQRT(X) <= SQRT(REAL'HIGH)
function CBRT (X : in REAL ) return REAL;
-- Purpose:
-- Returns cube root of X
-- Special values:
-- CBRT(0.0) = 0.0
-- CBRT(1.0) = 1.0
-- CBRT(-1.0) = -1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CBRT(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of CBRT is approximately given by:
-- ABS(CBRT(X)) <= CBRT(REAL'HIGH)
function "**" (X : in INTEGER; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0
-- 0**Y = 0.0; Y > 0.0
-- X**1.0 = REAL(X); X >= 0
-- 1**Y = 1.0
-- Domain:
-- X > 0
-- X = 0 for Y > 0.0
-- X < 0 for Y = 0.0
-- Error conditions:
-- Error if X < 0 and Y /= 0.0
-- Error if X = 0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function "**" (X : in REAL; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0.0
-- 0.0**Y = 0.0; Y > 0.0
-- X**1.0 = X; X >= 0.0
-- 1.0**Y = 1.0
-- Domain:
-- X > 0.0
-- X = 0.0 for Y > 0.0
-- X < 0.0 for Y = 0.0
-- Error conditions:
-- Error if X < 0.0 and Y /= 0.0
-- Error if X = 0.0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function EXP (X : in REAL ) return REAL;
-- Purpose:
-- Returns e**X; where e = MATH_E
-- Special values:
-- EXP(0.0) = 1.0
-- EXP(1.0) = MATH_E
-- EXP(-1.0) = MATH_1_OVER_E
-- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
-- Domain:
-- X in REAL such that EXP(X) <= REAL'HIGH
-- Error conditions:
-- Error if X > LOG(REAL'HIGH)
-- Range:
-- EXP(X) >= 0.0
-- Notes:
-- a) The usable domain of EXP is approximately given by:
-- X <= LOG(REAL'HIGH)
function LOG (X : in REAL ) return REAL;
-- Purpose:
-- Returns natural logarithm of X
-- Special values:
-- LOG(1.0) = 0.0
-- LOG(MATH_E) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG is approximately given by:
-- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
function LOG2 (X : in REAL ) return REAL;
-- Purpose:
-- Returns logarithm base 2 of X
-- Special values:
-- LOG2(1.0) = 0.0
-- LOG2(2.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG2(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG2 is approximately given by:
-- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
function LOG10 (X : in REAL ) return REAL;
-- Purpose:
-- Returns logarithm base 10 of X
-- Special values:
-- LOG10(1.0) = 0.0
-- LOG10(10.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG10(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG10 is approximately given by:
-- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
function LOG (X: in REAL; BASE: in REAL) return REAL;
-- Purpose:
-- Returns logarithm base BASE of X
-- Special values:
-- LOG(1.0, BASE) = 0.0
-- LOG(BASE, BASE) = 1.0
-- Domain:
-- X > 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if X <= 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(X, BASE) is mathematically unbounded
-- Notes:
-- a) When BASE > 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
-- b) When 0.0 < BASE < 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
function SIN (X : in REAL ) return REAL;
-- Purpose:
-- Returns sine of X; X in radians
-- Special values:
-- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function COS ( X : in REAL ) return REAL;
-- Purpose:
-- Returns cosine of X; X in radians
-- Special values:
-- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
-- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(COS(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function TAN (X : in REAL ) return REAL;
-- Purpose:
-- Returns tangent of X; X in radians
-- Special values:
-- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL and
-- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
-- Error conditions:
-- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
-- INTEGER
-- Range:
-- TAN(X) is mathematically unbounded
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function ARCSIN (X : in REAL ) return REAL;
-- Purpose:
-- Returns inverse sine of X
-- Special values:
-- ARCSIN(0.0) = 0.0
-- ARCSIN(1.0) = MATH_PI_OVER_2
-- ARCSIN(-1.0) = -MATH_PI_OVER_2
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- ABS(ARCSIN(X) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCCOS (X : in REAL ) return REAL;
-- Purpose:
-- Returns inverse cosine of X
-- Special values:
-- ARCCOS(1.0) = 0.0
-- ARCCOS(0.0) = MATH_PI_OVER_2
-- ARCCOS(-1.0) = MATH_PI
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- 0.0 <= ARCCOS(X) <= MATH_PI
-- Notes:
-- None
function ARCTAN (Y : in REAL) return REAL;
-- Purpose:
-- Returns the value of the angle in radians of the point
-- (1.0, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0) = 0.0
-- Domain:
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCTAN (Y : in REAL; X : in REAL) return REAL;
-- Purpose:
-- Returns the principal value of the angle in radians of
-- the point (X, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0, X) = 0.0 if X > 0.0
-- ARCTAN(0.0, X) = MATH_PI if X < 0.0
-- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
-- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
-- Domain:
-- Y in REAL
-- X in REAL, X /= 0.0 when Y = 0.0
-- Error conditions:
-- Error if X = 0.0 and Y = 0.0
-- Range:
-- -MATH_PI < ARCTAN(Y,X) <= MATH_PI
-- Notes:
-- None
function SINH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic sine of X
-- Special values:
-- SINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- SINH(X) is mathematically unbounded
-- Notes:
-- a) The usable domain of SINH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function COSH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic cosine of X
-- Special values:
-- COSH(0.0) = 1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- COSH(X) >= 1.0
-- Notes:
-- a) The usable domain of COSH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function TANH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic tangent of X
-- Special values:
-- TANH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(TANH(X)) <= 1.0
-- Notes:
-- None
function ARCSINH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic sine of X
-- Special values:
-- ARCSINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ARCSINH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCSINH is approximately given by:
-- ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
function ARCCOSH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic cosine of X
-- Special values:
-- ARCCOSH(1.0) = 0.0
-- Domain:
-- X >= 1.0
-- Error conditions:
-- Error if X < 1.0
-- Range:
-- ARCCOSH(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of ARCCOSH is
-- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH)
function ARCTANH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic tangent of X
-- Special values:
-- ARCTANH(0.0) = 0.0
-- Domain:
-- ABS(X) < 1.0
-- Error conditions:
-- Error if ABS(X) >= 1.0
-- Range:
-- ARCTANH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCTANH is approximately given by:
-- ABS(ARCTANH(X)) < LOG(REAL'HIGH)
end MATH_REAL;
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_REAL)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package body is a nonnormative implementation of the
-- functionality defined in the MATH_REAL package declaration.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076
-- -1993.
--
-- Notes:
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_REAL.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_REAL package declaration. The purpose of the MATH_REAL
-- package body is to clarify such semantics and provide a
-- guideline for implementations to verify their implementation
-- of MATH_REAL. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
package body MATH_REAL is
--
-- Local Constants for Use in the Package Body Only
--
constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2
constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10
constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi
constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic
constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries
constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria
constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic
--
-- Local Type Declarations for Cordic Operations
--
type REAL_VECTOR is array (NATURAL range <>) of REAL;
type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL;
subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER);
subtype REAL_ARR_2 is REAL_VECTOR (0 to 1);
subtype REAL_ARR_3 is REAL_VECTOR (0 to 2);
subtype QUADRANT is INTEGER range 0 to 3;
type CORDIC_MODE_TYPE is (ROTATION, VECTORING);
--
-- Auxiliary Functions for Cordic Algorithms
--
function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL;
NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is
-- Description:
-- Returns power of two for a vector of values
-- Notes:
-- None
--
variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES);
variable TEMP : REAL := INITIAL_VALUE;
variable FLAG : BOOLEAN := TRUE;
begin
for I in 0 to NUMBER_OF_VALUES loop
V(I) := TEMP;
for P in D'RANGE loop
if I = D(P) then
FLAG := FALSE;
exit;
end if;
end loop;
if FLAG then
TEMP := TEMP/2.0;
end if;
FLAG := TRUE;
end loop;
return V;
end POWER_OF_2_SERIES;
constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES(
NATURAL_VECTOR'(100, 90),1.0,
MAX_ITER);
constant EPSILON : REAL_VECTOR_N := (
7.8539816339744827e-01,
4.6364760900080606e-01,
2.4497866312686413e-01,
1.2435499454676144e-01,
6.2418809995957351e-02,
3.1239833430268277e-02,
1.5623728620476830e-02,
7.8123410601011116e-03,
3.9062301319669717e-03,
1.9531225164788189e-03,
9.7656218955931937e-04,
4.8828121119489829e-04,
2.4414062014936175e-04,
1.2207031189367021e-04,
6.1035156174208768e-05,
3.0517578115526093e-05,
1.5258789061315760e-05,
7.6293945311019699e-06,
3.8146972656064960e-06,
1.9073486328101870e-06,
9.5367431640596080e-07,
4.7683715820308876e-07,
2.3841857910155801e-07,
1.1920928955078067e-07,
5.9604644775390553e-08,
2.9802322387695303e-08,
1.4901161193847654e-08,
7.4505805969238281e-09
);
function CORDIC ( X0 : in REAL;
Y0 : in REAL;
Z0 : in REAL;
N : in NATURAL; -- Precision factor
CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0)
-- or vectoring (Y -> 0)
) return REAL_ARR_3 is
-- Description:
-- Compute cordic values
-- Notes:
-- None
variable X : REAL := X0;
variable Y : REAL := Y0;
variable Z : REAL := Z0;
variable X_TEMP : REAL;
begin
if CORDIC_MODE = ROTATION then
for K in 0 to N loop
X_TEMP := X;
if ( Z >= 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
else
for K in 0 to N loop
X_TEMP := X;
if ( Y < 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
end if;
return REAL_ARR_3'(X, Y, Z);
end CORDIC;
--
-- Bodies for Global Mathematical Functions Start Here
--
function SIGN (X: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
if ( X > 0.0 ) then
return 1.0;
elsif ( X < 0.0 ) then
return -1.0;
else
return 0.0;
end if;
end SIGN;
function CEIL (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is X <= LARGE
-- c) Returns X if ABS(X) >= LARGE
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
begin
if ABS(X) >= LARGE then
return X;
end if;
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
if X > 0.0 then
if RD >= X then
return RD;
else
return RD + 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD <= X then
return RD + 1.0;
else
return RD;
end if;
end if;
end CEIL;
function FLOOR (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is ABS(X) <= LARGE
-- c) Returns X if ABS(X) >= LARGE
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
begin
if ABS( X ) >= LARGE then
return X;
end if;
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
if X > 0.0 then
if RD <= X then
return RD;
else
return RD - 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD >= X then
return RD - 1.0;
else
return RD;
end if;
end if;
end FLOOR;
function ROUND (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X + 0.5) if X > 0
-- c) Returns CEIL(X - 0.5) if X < 0
begin
if X > 0.0 then
return FLOOR(X + 0.5);
elsif X < 0.0 then
return CEIL( X - 0.5);
else
return 0.0;
end if;
end ROUND;
function TRUNC (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X) if X > 0
-- c) Returns CEIL(X) if X < 0
begin
if X > 0.0 then
return FLOOR(X);
elsif X < 0.0 then
return CEIL( X);
else
return 0.0;
end if;
end TRUNC;
function "MOD" (X, Y: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
variable XNEGATIVE : BOOLEAN := X < 0.0;
variable YNEGATIVE : BOOLEAN := Y < 0.0;
variable VALUE : REAL;
begin
-- Check validity of input arguments
if (Y = 0.0) then
assert FALSE
report "MOD(X, 0.0) is undefined"
severity ERROR;
return 0.0;
end if;
-- Compute value
if ( XNEGATIVE ) then
if ( YNEGATIVE ) then
VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
end if;
else
if ( YNEGATIVE ) then
VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
end if;
end if;
return VALUE;
end "MOD";
function REALMAX (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMAX(X,Y) = X when X = Y
--
begin
if X >= Y then
return X;
else
return Y;
end if;
end REALMAX;
function REALMIN (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMIN(X,Y) = X when X = Y
--
begin
if X <= Y then
return X;
else
return Y;
end if;
end REALMIN;
procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL)
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
--
variable Z, K: INTEGER;
variable TSEED1 : INTEGER := INTEGER'(SEED1);
variable TSEED2 : INTEGER := INTEGER'(SEED2);
begin
-- Check validity of arguments
if SEED1 > 2147483562 then
assert FALSE
report "SEED1 > 2147483562 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
if SEED2 > 2147483398 then
assert FALSE
report "SEED2 > 2147483398 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
-- Compute new seed values and pseudo-random number
K := TSEED1/53668;
TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211;
if TSEED1 < 0 then
TSEED1 := TSEED1 + 2147483563;
end if;
K := TSEED2/52774;
TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791;
if TSEED2 < 0 then
TSEED2 := TSEED2 + 2147483399;
end if;
Z := TSEED1 - TSEED2;
if Z < 1 then
Z := Z + 2147483562;
end if;
-- Get output values
SEED1 := POSITIVE'(TSEED1);
SEED2 := POSITIVE'(TSEED2);
X := REAL(Z)*4.656613e-10;
end UNIFORM;
function SQRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = 0.5*[F(n) + x/F(n)]
-- b) Returns 0.0 on error
--
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor
variable INIVAL: REAL;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
begin
-- Check validity of argument
if ( X < 0.0 ) then
assert FALSE
report "X < 0.0 in SQRT(X)"
severity ERROR;
return 0.0;
end if;
-- Get the square root for special cases
if X = 0.0 then
return 0.0;
else
if ( X = 1.0 ) then
return 1.0;
end if;
end if;
-- Get the square root for general cases
INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise
OLDVAL := INIVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
-- Check for relative and absolute error and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT) ) loop
OLDVAL := NEWVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
COUNT := COUNT + 1;
end loop;
return NEWVAL;
end SQRT;
function CBRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2];
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
variable INIVAL: REAL;
variable XLOCAL : REAL := X;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
begin
-- Compute root for special cases
if X = 0.0 then
return 0.0;
elsif ( X = 1.0 ) then
return 1.0;
else
if X = -1.0 then
return -1.0;
end if;
end if;
-- Compute root for general cases
if NEGATIVE then
XLOCAL := -X;
end if;
INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but
-- imprecise
OLDVAL := INIVAL;
NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR
(ABS(NEWVAL - OLDVAL) > EPS ) ) AND
( COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
COUNT := COUNT + 1;
end loop;
if NEGATIVE then
NEWVAL := -NEWVAL;
end if;
return NEWVAL;
end CBRT;
function "**" (X : in INTEGER; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
begin
-- Check validity of argument
if ( ( X < 0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
if ( ( X = 0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
-- Get value for special cases
if ( X = 0 and Y > 0.0 ) then
return 0.0;
end if;
if ( X = 1 ) then
return 1.0;
end if;
if ( Y = 0.0 and X /= 0 ) then
return 1.0;
end if;
if ( Y = 1.0) then
return (REAL(X));
end if;
-- Get value for general case
return EXP (Y * LOG (REAL(X)));
end "**";
function "**" (X : in REAL; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
begin
-- Check validity of argument
if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0.0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0.0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
-- Get value for special cases
if ( X = 0.0 and Y > 0.0 ) then
return 0.0;
end if;
if ( X = 1.0 ) then
return 1.0;
end if;
if ( Y = 0.0 and X /= 0.0 ) then
return 1.0;
end if;
if ( Y = 1.0) then
return (X);
end if;
-- Get value for general case
return EXP (Y * LOG (X));
end "**";
function EXP (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) This function computes the exponential using the following
-- series:
-- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0
-- and reduces argument X to take advantage of exp(x+y) =
-- exp(x)*exp(y)
--
-- b) This implementation limits X to be less than LOG(REAL'HIGH)
-- to avoid overflow. Returns REAL'HIGH when X reaches that
-- limit
--
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria
variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument
variable XLOCAL : REAL := ABS(X); -- Use positive value
variable OLDVAL: REAL ;
variable COUNT: INTEGER ;
variable NEWVAL: REAL ;
variable LAST_TERM: REAL ;
variable FACTOR : REAL := 1.0;
begin
-- Compute value for special cases
if X = 0.0 then
return 1.0;
end if;
if XLOCAL = 1.0 then
if RECIPROCAL then
return MATH_1_OVER_E;
else
return MATH_E;
end if;
end if;
if XLOCAL = 2.0 then
if RECIPROCAL then
return 1.0/MATH_E_P2;
else
return MATH_E_P2;
end if;
end if;
if XLOCAL = 10.0 then
if RECIPROCAL then
return 1.0/MATH_E_P10;
else
return MATH_E_P10;
end if;
end if;
if XLOCAL > LOG(REAL'HIGH) then
if RECIPROCAL then
return 0.0;
else
assert FALSE
report "X > LOG(REAL'HIGH) in EXP(X)"
severity NOTE;
return REAL'HIGH;
end if;
end if;
-- Reduce argument to ABS(X) < 1.0
while XLOCAL > 10.0 loop
XLOCAL := XLOCAL - 10.0;
FACTOR := FACTOR*MATH_E_P10;
end loop;
while XLOCAL > 1.0 loop
XLOCAL := XLOCAL - 1.0;
FACTOR := FACTOR*MATH_E;
end loop;
-- Compute value for case 0 < XLOCAL < 1
OLDVAL := 1.0;
LAST_TERM := XLOCAL;
NEWVAL:= OLDVAL + LAST_TERM;
COUNT := 2;
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT)));
NEWVAL := OLDVAL + LAST_TERM;
COUNT := COUNT + 1;
end loop;
-- Compute final value using exp(x+y) = exp(x)*exp(y)
NEWVAL := NEWVAL*FACTOR;
if RECIPROCAL then
NEWVAL := 1.0/NEWVAL;
end if;
return NEWVAL;
end EXP;
--
-- Auxiliary Functions to Compute LOG
--
function ILOGB(X: in REAL) return INTEGER IS
-- Description:
-- Returns n such that -1 <= ABS(X)/2^n < 2
-- Notes:
-- None
variable N: INTEGER := 0;
variable Y: REAL := ABS(X);
begin
if(Y = 1.0 or Y = 0.0) then
return 0;
end if;
if( Y > 1.0) then
while Y >= 2.0 loop
Y := Y/2.0;
N := N+1;
end loop;
return N;
end if;
-- O < Y < 1
while Y < 1.0 loop
Y := Y*2.0;
N := N -1;
end loop;
return N;
end ILOGB;
function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS
-- Description:
-- Returns X*2^n
-- Notes:
-- None
begin
return X*(2.0 ** N);
end LDEXP;
function LOG (X : in REAL ) return REAL IS
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
--
-- Notes:
-- a) Returns REAL'LOW on error
--
-- Copyright (c) 1992 Regents of the University of California.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. All advertising materials mentioning features or use of this
-- software must display the following acknowledgement:
-- This product includes software developed by the University of
-- California, Berkeley and its contributors.
-- 4. Neither the name of the University nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-- DAMAGE.
--
-- NOTE: This VHDL version was generated using the C version of the
-- original function by the IEEE VHDL Mathematical Package
-- Working Group (CS/JT)
constant N: INTEGER := 128;
-- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128.
-- Used for generation of extend precision logarithms.
-- The constant 35184372088832 is 2^45, so the divide is exact.
-- It ensures correct reading of logF_head, even for inaccurate
-- decimal-to-binary conversion routines. (Everybody gets the
-- right answer for INTEGERs less than 2^53.)
-- Values for LOG(F) were generated using error < 10^-57 absolute
-- with the bc -l package.
type REAL_VECTOR is array (NATURAL range <>) of REAL;
constant A1:REAL := 0.08333333333333178827;
constant A2:REAL := 0.01250000000377174923;
constant A3:REAL := 0.002232139987919447809;
constant A4:REAL := 0.0004348877777076145742;
constant LOGF_HEAD: REAL_VECTOR(0 TO N) := (
0.0,
0.007782140442060381246,
0.015504186535963526694,
0.023167059281547608406,
0.030771658666765233647,
0.038318864302141264488,
0.045809536031242714670,
0.053244514518837604555,
0.060624621816486978786,
0.067950661908525944454,
0.075223421237524235039,
0.082443669210988446138,
0.089612158689760690322,
0.096729626458454731618,
0.103796793681567578460,
0.110814366340264314203,
0.117783035656430001836,
0.124703478501032805070,
0.131576357788617315236,
0.138402322859292326029,
0.145182009844575077295,
0.151916042025732167530,
0.158605030176659056451,
0.165249572895390883786,
0.171850256926518341060,
0.178407657472689606947,
0.184922338493834104156,
0.191394852999565046047,
0.197825743329758552135,
0.204215541428766300668,
0.210564769107350002741,
0.216873938300523150246,
0.223143551314024080056,
0.229374101064877322642,
0.235566071312860003672,
0.241719936886966024758,
0.247836163904594286577,
0.253915209980732470285,
0.259957524436686071567,
0.265963548496984003577,
0.271933715484010463114,
0.277868451003087102435,
0.283768173130738432519,
0.289633292582948342896,
0.295464212893421063199,
0.301261330578199704177,
0.307025035294827830512,
0.312755710004239517729,
0.318453731118097493890,
0.324119468654316733591,
0.329753286372579168528,
0.335355541920762334484,
0.340926586970454081892,
0.346466767346100823488,
0.351976423156884266063,
0.357455888922231679316,
0.362905493689140712376,
0.368325561158599157352,
0.373716409793814818840,
0.379078352934811846353,
0.384411698910298582632,
0.389716751140440464951,
0.394993808240542421117,
0.400243164127459749579,
0.405465108107819105498,
0.410659924985338875558,
0.415827895143593195825,
0.420969294644237379543,
0.426084395310681429691,
0.431173464818130014464,
0.436236766774527495726,
0.441274560805140936281,
0.446287102628048160113,
0.451274644139630254358,
0.456237433481874177232,
0.461175715122408291790,
0.466089729924533457960,
0.470979715219073113985,
0.475845904869856894947,
0.480688529345570714212,
0.485507815781602403149,
0.490303988045525329653,
0.495077266798034543171,
0.499827869556611403822,
0.504556010751912253908,
0.509261901790523552335,
0.513945751101346104405,
0.518607764208354637958,
0.523248143765158602036,
0.527867089620485785417,
0.532464798869114019908,
0.537041465897345915436,
0.541597282432121573947,
0.546132437597407260909,
0.550647117952394182793,
0.555141507540611200965,
0.559615787935399566777,
0.564070138285387656651,
0.568504735352689749561,
0.572919753562018740922,
0.577315365035246941260,
0.581691739635061821900,
0.586049045003164792433,
0.590387446602107957005,
0.594707107746216934174,
0.599008189645246602594,
0.603290851438941899687,
0.607555250224322662688,
0.611801541106615331955,
0.616029877215623855590,
0.620240409751204424537,
0.624433288012369303032,
0.628608659422752680256,
0.632766669570628437213,
0.636907462236194987781,
0.641031179420679109171,
0.645137961373620782978,
0.649227946625615004450,
0.653301272011958644725,
0.657358072709030238911,
0.661398482245203922502,
0.665422632544505177065,
0.669430653942981734871,
0.673422675212350441142,
0.677398823590920073911,
0.681359224807238206267,
0.685304003098281100392,
0.689233281238557538017,
0.693147180560117703862);
constant LOGF_TAIL: REAL_VECTOR(0 TO N) := (
0.0,
-0.00000000000000543229938420049,
0.00000000000000172745674997061,
-0.00000000000001323017818229233,
-0.00000000000001154527628289872,
-0.00000000000000466529469958300,
0.00000000000005148849572685810,
-0.00000000000002532168943117445,
-0.00000000000005213620639136504,
-0.00000000000001819506003016881,
0.00000000000006329065958724544,
0.00000000000008614512936087814,
-0.00000000000007355770219435028,
0.00000000000009638067658552277,
0.00000000000007598636597194141,
0.00000000000002579999128306990,
-0.00000000000004654729747598444,
-0.00000000000007556920687451336,
0.00000000000010195735223708472,
-0.00000000000017319034406422306,
-0.00000000000007718001336828098,
0.00000000000010980754099855238,
-0.00000000000002047235780046195,
-0.00000000000008372091099235912,
0.00000000000014088127937111135,
0.00000000000012869017157588257,
0.00000000000017788850778198106,
0.00000000000006440856150696891,
0.00000000000016132822667240822,
-0.00000000000007540916511956188,
-0.00000000000000036507188831790,
0.00000000000009120937249914984,
0.00000000000018567570959796010,
-0.00000000000003149265065191483,
-0.00000000000009309459495196889,
0.00000000000017914338601329117,
-0.00000000000001302979717330866,
0.00000000000023097385217586939,
0.00000000000023999540484211737,
0.00000000000015393776174455408,
-0.00000000000036870428315837678,
0.00000000000036920375082080089,
-0.00000000000009383417223663699,
0.00000000000009433398189512690,
0.00000000000041481318704258568,
-0.00000000000003792316480209314,
0.00000000000008403156304792424,
-0.00000000000034262934348285429,
0.00000000000043712191957429145,
-0.00000000000010475750058776541,
-0.00000000000011118671389559323,
0.00000000000037549577257259853,
0.00000000000013912841212197565,
0.00000000000010775743037572640,
0.00000000000029391859187648000,
-0.00000000000042790509060060774,
0.00000000000022774076114039555,
0.00000000000010849569622967912,
-0.00000000000023073801945705758,
0.00000000000015761203773969435,
0.00000000000003345710269544082,
-0.00000000000041525158063436123,
0.00000000000032655698896907146,
-0.00000000000044704265010452446,
0.00000000000034527647952039772,
-0.00000000000007048962392109746,
0.00000000000011776978751369214,
-0.00000000000010774341461609578,
0.00000000000021863343293215910,
0.00000000000024132639491333131,
0.00000000000039057462209830700,
-0.00000000000026570679203560751,
0.00000000000037135141919592021,
-0.00000000000017166921336082431,
-0.00000000000028658285157914353,
-0.00000000000023812542263446809,
0.00000000000006576659768580062,
-0.00000000000028210143846181267,
0.00000000000010701931762114254,
0.00000000000018119346366441110,
0.00000000000009840465278232627,
-0.00000000000033149150282752542,
-0.00000000000018302857356041668,
-0.00000000000016207400156744949,
0.00000000000048303314949553201,
-0.00000000000071560553172382115,
0.00000000000088821239518571855,
-0.00000000000030900580513238244,
-0.00000000000061076551972851496,
0.00000000000035659969663347830,
0.00000000000035782396591276383,
-0.00000000000046226087001544578,
0.00000000000062279762917225156,
0.00000000000072838947272065741,
0.00000000000026809646615211673,
-0.00000000000010960825046059278,
0.00000000000002311949383800537,
-0.00000000000058469058005299247,
-0.00000000000002103748251144494,
-0.00000000000023323182945587408,
-0.00000000000042333694288141916,
-0.00000000000043933937969737844,
0.00000000000041341647073835565,
0.00000000000006841763641591466,
0.00000000000047585534004430641,
0.00000000000083679678674757695,
-0.00000000000085763734646658640,
0.00000000000021913281229340092,
-0.00000000000062242842536431148,
-0.00000000000010983594325438430,
0.00000000000065310431377633651,
-0.00000000000047580199021710769,
-0.00000000000037854251265457040,
0.00000000000040939233218678664,
0.00000000000087424383914858291,
0.00000000000025218188456842882,
-0.00000000000003608131360422557,
-0.00000000000050518555924280902,
0.00000000000078699403323355317,
-0.00000000000067020876961949060,
0.00000000000016108575753932458,
0.00000000000058527188436251509,
-0.00000000000035246757297904791,
-0.00000000000018372084495629058,
0.00000000000088606689813494916,
0.00000000000066486268071468700,
0.00000000000063831615170646519,
0.00000000000025144230728376072,
-0.00000000000017239444525614834);
variable M, J:INTEGER;
variable F1, F2, G, Q, U, U2, V: REAL;
variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs
variable ONE: REAL := 1.0; --Made variable so no constant folding occurs
-- double logb(), ldexp();
variable U1:REAL;
begin
-- Check validity of argument
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = MATH_E ) then
return 1.0;
end if;
-- Argument reduction: 1 <= g < 2; x/2^m = g;
-- y = F*(1 + f/F) for |f| <= 2^-8
M := ILOGB(X);
G := LDEXP(X, -M);
J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding
F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512]
F2 := G - F1;
-- Approximate expansion for log(1+f2/F1) ~= u + q
G := 1.0/(2.0*F1+F2);
U := 2.0*F2*G;
V := U*U;
Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4)));
-- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8,
-- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits.
-- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750.
--
if ( J /= 0 or M /= 0) then
U1 := U + 513.0;
U1 := U1 - 513.0;
-- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero
-- u1 = u to 24 bits.
--
else
U1 := U;
--TRUNC(U1); --In c this is u1 = (double) (float) (u1)
end if;
U2 := (2.0*(F2 - F1*U1) - U1*F2) * G;
-- u1 + u2 = 2f/(2F+f) to extra precision.
-- log(x) = log(2^m*F1*(1+f2/F1)) =
-- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q);
-- (exact) + (tiny)
U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact
U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny
U2 := U2 + LOGF_TAIL(N)*REAL(M);
return (U1 + U2);
end LOG;
function LOG2 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG2(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = 2.0 ) then
return 1.0;
end if;
-- Compute value for general case
return ( MATH_LOG2_OF_E*LOG(X) );
end LOG2;
function LOG10 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG10(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = 10.0 ) then
return 1.0;
end if;
-- Compute value for general case
return ( MATH_LOG10_OF_E*LOG(X) );
end LOG10;
function LOG (X: in REAL; BASE: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = BASE ) then
return 1.0;
end if;
-- Compute value for general case
return ( LOG(X)/LOG(BASE));
end LOG;
function SIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) SIN(-X) = -SIN(X)
-- b) SIN(X) = X if ABS(X) < EPS
-- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS
-- d) SIN(MATH_PI_OVER_2 - X) = COS(X)
-- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS
-- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence criteria
variable N : INTEGER;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in SIN(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then
return 0.0;
end if;
if XLOCAL = MATH_PI_OVER_2 then
if NEGATIVE then
return -1.0;
else
return 1.0;
end if;
end if;
if XLOCAL = MATH_3_PI_OVER_2 then
if NEGATIVE then
return 1.0;
else
return -1.0;
end if;
end if;
if XLOCAL < EPS then
if NEGATIVE then
return -XLOCAL;
else
return XLOCAL;
end if;
else
if XLOCAL < BASE_EPS then
TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := MATH_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := MATH_2_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
TEMP := ABS(MATH_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
-- Compute value for general cases
if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then
VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1);
end if;
N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2));
case QUADRANT( N mod 4) is
when 0 =>
VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1);
when 1 =>
VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27,
ROTATION)(0);
when 2 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1);
when 3 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27,
ROTATION)(0);
end case;
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end SIN;
function COS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) COS(-X) = COS(X)
-- b) COS(X) = SIN(MATH_PI_OVER_2 - X)
-- c) COS(MATH_PI + X) = -COS(X)
-- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS
-- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
variable XLOCAL : REAL := ABS(X);
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in COS(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then
return 1.0;
end if;
if XLOCAL = MATH_PI then
return -1.0;
end if;
if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then
return 0.0;
end if;
TEMP := ABS(XLOCAL);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
TEMP := ABS(XLOCAL -MATH_2_PI);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
TEMP := ABS (XLOCAL - MATH_PI);
if TEMP < EPS then
return (-1.0 + 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
-- Compute value for general cases
return SIN(MATH_PI_OVER_2 - XLOCAL);
end COS;
function TAN (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) TAN(0.0) = 0.0
-- b) TAN(-X) = -TAN(X)
-- c) Returns REAL'LOW on error if X < 0.0
-- d) Returns REAL'HIGH on error if X > 0.0
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make 0.0 <= XLOCAL <= MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
assert FALSE
report "XLOCAL <= 0.0 after reduction in TAN(X)"
severity ERROR;
XLOCAL := -XLOCAL;
end if;
-- Check validity of argument
if XLOCAL = MATH_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'LOW);
else
return(REAL'HIGH);
end if;
end if;
if XLOCAL = MATH_3_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'HIGH);
else
return(REAL'LOW);
end if;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_PI then
return 0.0;
end if;
-- Compute value for general cases
VALUE := SIN(XLOCAL)/COS(XLOCAL);
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end TAN;
function ARCSIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCSIN(-X) = -ARCSIN(X)
-- b) Returns X on error
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
begin
-- Check validity of arguments
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCSIN(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
elsif XLOCAL = 1.0 then
if NEGATIVE then
return -MATH_PI_OVER_2;
else
return MATH_PI_OVER_2;
end if;
end if;
-- Compute value for general cases
if XLOCAL < 0.9 then
VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL)));
else
VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
end if;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end ARCSIN;
function ARCCOS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCCOS(-X) = MATH_PI - ARCCOS(X)
-- b) Returns X on error
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
begin
-- Check validity of argument
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCCOS(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 1.0 then
return 0.0;
elsif X = 0.0 then
return MATH_PI_OVER_2;
elsif X = -1.0 then
return MATH_PI;
end if;
-- Compute value for general cases
if XLOCAL > 0.9 then
VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
else
VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL));
end if;
if NEGATIVE then
VALUE := MATH_PI - VALUE;
end if;
return VALUE;
end ARCCOS;
function ARCTAN (Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCTAN(-Y) = -ARCTAN(Y)
-- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0
-- c) ARCTAN(Y) = Y for |Y| < EPS
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;
variable NEGATIVE : BOOLEAN := Y < 0.0;
variable RECIPROCAL : BOOLEAN;
variable YLOCAL : REAL := ABS(Y);
variable VALUE : REAL;
begin
-- Make argument |Y| <=1.0
if YLOCAL > 1.0 then
YLOCAL := 1.0/YLOCAL;
RECIPROCAL := TRUE;
else
RECIPROCAL := FALSE;
end if;
-- Compute value for special cases
if YLOCAL = 0.0 then
if RECIPROCAL then
if NEGATIVE then
return (-MATH_PI_OVER_2);
else
return (MATH_PI_OVER_2);
end if;
else
return 0.0;
end if;
end if;
if YLOCAL < EPS then
if NEGATIVE then
if RECIPROCAL then
return (-MATH_PI_OVER_2 + YLOCAL);
else
return -YLOCAL;
end if;
else
if RECIPROCAL then
return (MATH_PI_OVER_2 - YLOCAL);
else
return YLOCAL;
end if;
end if;
end if;
-- Compute value for general cases
VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2);
if RECIPROCAL then
VALUE := MATH_PI_OVER_2 - VALUE;
end if;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end ARCTAN;
function ARCTAN (Y : in REAL; X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
variable YLOCAL : REAL;
variable VALUE : REAL;
begin
-- Check validity of arguments
if (Y = 0.0 and X = 0.0 ) then
assert FALSE report
"ARCTAN(0.0, 0.0) is undetermined"
severity ERROR;
return 0.0;
end if;
-- Compute value for special cases
if Y = 0.0 then
if X > 0.0 then
return 0.0;
else
return MATH_PI;
end if;
end if;
if X = 0.0 then
if Y > 0.0 then
return MATH_PI_OVER_2;
else
return -MATH_PI_OVER_2;
end if;
end if;
-- Compute value for general cases
YLOCAL := ABS(Y/X);
VALUE := ARCTAN(YLOCAL);
if X < 0.0 then
VALUE := MATH_PI - VALUE;
end if;
if Y < 0.0 then
VALUE := -VALUE;
end if;
return VALUE;
end ARCTAN;
function SINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/2.0
-- b) SINH(-X) = SINH(X)
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)*0.5;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end SINH;
function COSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) + EXP(-X))/2.0
-- b) COSH(-X) = COSH(X)
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 1.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP + 1.0/TEMP)*0.5;
return VALUE;
end COSH;
function TANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X))
-- b) TANH(-X) = -TANH(X)
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP);
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end TANH;
function ARCSINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X + 1.0))
begin
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
return ( LOG( X + SQRT( X*X + 1.0)) );
end ARCSINH;
function ARCCOSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0
-- b) Returns X on error
begin
-- Check validity of arguments
if X < 1.0 then
assert FALSE
report "X < 1.0 in ARCCOSH(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 1.0 then
return 0.0;
end if;
-- Compute value for general cases
return ( LOG( X + SQRT( X*X - 1.0)));
end ARCCOSH;
function ARCTANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0
-- b) Returns X on error
begin
-- Check validity of arguments
if ABS(X) >= 1.0 then
assert FALSE
report "ABS(X) >= 1.0 in ARCTANH(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
return( 0.5*LOG( (1.0+X)/(1.0-X) ) );
end ARCTANH;
end MATH_REAL;
|
-------------------------------------------------------------------------------
-- File Name : DC_CR_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : DC_CR_ROM
--
-- Content : DC_CR_ROM Chrominance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090329: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity DC_CR_ROM is
port
(
CLK : in std_logic;
RST : in std_logic;
VLI_size : in std_logic_vector(3 downto 0);
VLC_DC_size : out std_logic_vector(3 downto 0);
VLC_DC : out unsigned(10 downto 0)
);
end entity DC_CR_ROM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of DC_CR_ROM is
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- DC-ROM
-------------------------------------------------------------------
p_DC_CR_ROM : process(CLK)
begin
if CLK'event and CLK = '1' then
case VLI_size is
when X"0" =>
VLC_DC_size <= X"2";
VLC_DC <= resize("00", VLC_DC'length);
when X"1" =>
VLC_DC_size <= X"2";
VLC_DC <= resize("01", VLC_DC'length);
when X"2" =>
VLC_DC_size <= X"2";
VLC_DC <= resize("10", VLC_DC'length);
when X"3" =>
VLC_DC_size <= X"3";
VLC_DC <= resize("110", VLC_DC'length);
when X"4" =>
VLC_DC_size <= X"4";
VLC_DC <= resize("1110", VLC_DC'length);
when X"5" =>
VLC_DC_size <= X"5";
VLC_DC <= resize("11110", VLC_DC'length);
when X"6" =>
VLC_DC_size <= X"6";
VLC_DC <= resize("111110", VLC_DC'length);
when X"7" =>
VLC_DC_size <= X"7";
VLC_DC <= resize("1111110", VLC_DC'length);
when X"8" =>
VLC_DC_size <= X"8";
VLC_DC <= resize("11111110", VLC_DC'length);
when X"9" =>
VLC_DC_size <= X"9";
VLC_DC <= resize("111111110", VLC_DC'length);
when X"A" =>
VLC_DC_size <= X"A";
VLC_DC <= resize("1111111110", VLC_DC'length);
when X"B" =>
VLC_DC_size <= X"B";
VLC_DC <= resize("11111111110", VLC_DC'length);
when others =>
VLC_DC_size <= X"0";
VLC_DC <= (others => '0');
end case;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : DC_CR_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : DC_CR_ROM
--
-- Content : DC_CR_ROM Chrominance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090329: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity DC_CR_ROM is
port
(
CLK : in std_logic;
RST : in std_logic;
VLI_size : in std_logic_vector(3 downto 0);
VLC_DC_size : out std_logic_vector(3 downto 0);
VLC_DC : out unsigned(10 downto 0)
);
end entity DC_CR_ROM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of DC_CR_ROM is
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- DC-ROM
-------------------------------------------------------------------
p_DC_CR_ROM : process(CLK)
begin
if CLK'event and CLK = '1' then
case VLI_size is
when X"0" =>
VLC_DC_size <= X"2";
VLC_DC <= resize("00", VLC_DC'length);
when X"1" =>
VLC_DC_size <= X"2";
VLC_DC <= resize("01", VLC_DC'length);
when X"2" =>
VLC_DC_size <= X"2";
VLC_DC <= resize("10", VLC_DC'length);
when X"3" =>
VLC_DC_size <= X"3";
VLC_DC <= resize("110", VLC_DC'length);
when X"4" =>
VLC_DC_size <= X"4";
VLC_DC <= resize("1110", VLC_DC'length);
when X"5" =>
VLC_DC_size <= X"5";
VLC_DC <= resize("11110", VLC_DC'length);
when X"6" =>
VLC_DC_size <= X"6";
VLC_DC <= resize("111110", VLC_DC'length);
when X"7" =>
VLC_DC_size <= X"7";
VLC_DC <= resize("1111110", VLC_DC'length);
when X"8" =>
VLC_DC_size <= X"8";
VLC_DC <= resize("11111110", VLC_DC'length);
when X"9" =>
VLC_DC_size <= X"9";
VLC_DC <= resize("111111110", VLC_DC'length);
when X"A" =>
VLC_DC_size <= X"A";
VLC_DC <= resize("1111111110", VLC_DC'length);
when X"B" =>
VLC_DC_size <= X"B";
VLC_DC <= resize("11111111110", VLC_DC'length);
when others =>
VLC_DC_size <= X"0";
VLC_DC <= (others => '0');
end case;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
architecture rtl of fifo is
signal sig8 : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0),
elementB(3 downto 0)
),
element3(3 downto 0)(
elementC(4 downto 1),
elementD(1 downto 0)),
element5(
elementE(3 downto 0)(6 downto 0),
elementF(7 downto 0)
),
element6(4 downto 0),
element7(7 downto 0)
);
begin
end architecture rtl;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
library lib_fifo_v1_0_4;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 1, --req for proper fifo operation
C_DCOUNT_WIDTH => CNTRL_FIFO_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty
and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1_9.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => m_axi_sg_aclk ,
ARST => skid_rst ,
skid_stop => mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1 : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_dma_v7_1_9.axi_dma_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
-- C_DEPTH => CNTRL_FIFO_DEPTH ,
-- C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_mm2s_stop_d1 <= '0';
p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1 <= mm2s_stop;
p_mm2s_stop_d1 <= mm2s_stop_reg;
p_mm2s_stop_d2 <= p_mm2s_stop_d1;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1_9.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
library lib_fifo_v1_0_4;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 1, --req for proper fifo operation
C_DCOUNT_WIDTH => CNTRL_FIFO_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty
and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1_9.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => m_axi_sg_aclk ,
ARST => skid_rst ,
skid_stop => mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1 : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_dma_v7_1_9.axi_dma_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
-- C_DEPTH => CNTRL_FIFO_DEPTH ,
-- C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_mm2s_stop_d1 <= '0';
p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1 <= mm2s_stop;
p_mm2s_stop_d1 <= mm2s_stop_reg;
p_mm2s_stop_d2 <= p_mm2s_stop_d1;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1_9.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
library lib_fifo_v1_0_4;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 1, --req for proper fifo operation
C_DCOUNT_WIDTH => CNTRL_FIFO_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty
and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1_9.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => m_axi_sg_aclk ,
ARST => skid_rst ,
skid_stop => mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1 : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_dma_v7_1_9.axi_dma_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
-- C_DEPTH => CNTRL_FIFO_DEPTH ,
-- C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_mm2s_stop_d1 <= '0';
p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1 <= mm2s_stop;
p_mm2s_stop_d1 <= mm2s_stop_reg;
p_mm2s_stop_d2 <= p_mm2s_stop_d1;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1_9.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tma_nov is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(5 downto 0)
);
end tma_nov;
architecture behaviour of tma_nov is
constant I0: std_logic_vector(4 downto 0) := "11110";
constant T1: std_logic_vector(4 downto 0) := "00000";
constant T3: std_logic_vector(4 downto 0) := "00001";
constant T4: std_logic_vector(4 downto 0) := "01101";
constant T5: std_logic_vector(4 downto 0) := "00101";
constant T6: std_logic_vector(4 downto 0) := "11010";
constant T7: std_logic_vector(4 downto 0) := "11111";
constant T8: std_logic_vector(4 downto 0) := "11100";
constant T9: std_logic_vector(4 downto 0) := "10011";
constant T2: std_logic_vector(4 downto 0) := "10100";
constant R1: std_logic_vector(4 downto 0) := "00100";
constant R2: std_logic_vector(4 downto 0) := "01011";
constant R3: std_logic_vector(4 downto 0) := "00011";
constant R4: std_logic_vector(4 downto 0) := "00010";
constant R6: std_logic_vector(4 downto 0) := "00111";
constant R7: std_logic_vector(4 downto 0) := "11011";
constant R8: std_logic_vector(4 downto 0) := "11000";
constant R5: std_logic_vector(4 downto 0) := "00110";
constant I2: std_logic_vector(4 downto 0) := "01000";
constant I1: std_logic_vector(4 downto 0) := "01001";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "------";
case current_state is
when I0 =>
if std_match(input, "11110--") then next_state <= T1; output <= "000000";
elsif std_match(input, "101-1--") then next_state <= R1; output <= "000000";
end if;
when T1 =>
if std_match(input, "1110---") then next_state <= T3; output <= "100000";
elsif std_match(input, "100----") then next_state <= T9; output <= "100000";
elsif std_match(input, "101--1-") then next_state <= T9; output <= "100000";
end if;
when T3 =>
if std_match(input, "111----") then next_state <= T4; output <= "110000";
elsif std_match(input, "100----") then next_state <= T9; output <= "110000";
elsif std_match(input, "101--1-") then next_state <= T9; output <= "110000";
end if;
when T4 =>
if std_match(input, "111----") then next_state <= T5; output <= "001000";
elsif std_match(input, "100----") then next_state <= T9; output <= "001000";
elsif std_match(input, "101--1-") then next_state <= T9; output <= "001000";
end if;
when T5 =>
if std_match(input, "111-0--") then next_state <= T6; output <= "101000";
elsif std_match(input, "100----") then next_state <= T9; output <= "101000";
elsif std_match(input, "101-1--") then next_state <= T9; output <= "101000";
end if;
when T6 =>
if std_match(input, "101-0--") then next_state <= T7; output <= "011000";
elsif std_match(input, "101-1--") then next_state <= T8; output <= "011000";
elsif std_match(input, "100----") then next_state <= T9; output <= "011000";
end if;
when T7 =>
if std_match(input, "10-----") then next_state <= I2; output <= "111000";
end if;
when T8 =>
if std_match(input, "10-----") then next_state <= I2; output <= "000100";
end if;
when T9 =>
if std_match(input, "101-0--") then next_state <= T2; output <= "100100";
elsif std_match(input, "100----") then next_state <= T2; output <= "100100";
end if;
when T2 =>
if std_match(input, "10-----") then next_state <= T8; output <= "010100";
end if;
when R1 =>
if std_match(input, "101-1--") then next_state <= R2; output <= "100010";
elsif std_match(input, "100----") then next_state <= I1; output <= "100010";
elsif std_match(input, "101-0--") then next_state <= I2; output <= "100010";
end if;
when R2 =>
if std_match(input, "101-1--") then next_state <= R3; output <= "010010";
elsif std_match(input, "100----") then next_state <= I1; output <= "010010";
elsif std_match(input, "101-0--") then next_state <= I2; output <= "010010";
end if;
when R3 =>
if std_match(input, "101-1--") then next_state <= R4; output <= "110010";
elsif std_match(input, "101-0-0") then next_state <= R6; output <= "110010";
elsif std_match(input, "101-0-1") then next_state <= R8; output <= "110010";
elsif std_match(input, "100----") then next_state <= R5; output <= "110010";
end if;
when R4 =>
if std_match(input, "101-0-0") then next_state <= R6; output <= "001010";
elsif std_match(input, "101-0-1") then next_state <= R8; output <= "001010";
elsif std_match(input, "100----") then next_state <= R5; output <= "001010";
end if;
when R6 =>
if std_match(input, "101-0--") then next_state <= R7; output <= "011010";
elsif std_match(input, "101-1--") then next_state <= R5; output <= "011010";
elsif std_match(input, "100----") then next_state <= R5; output <= "011010";
end if;
when R7 =>
if std_match(input, "10-----") then next_state <= I2; output <= "111010";
end if;
when R8 =>
if std_match(input, "10-----") then next_state <= R5; output <= "000110";
end if;
when R5 =>
if std_match(input, "101----") then next_state <= I2; output <= "100110";
elsif std_match(input, "100----") then next_state <= I1; output <= "100110";
end if;
when I2 =>
if std_match(input, "-------") then next_state <= I0; output <= "000001";
end if;
when I1 =>
if std_match(input, "111-0--") then next_state <= I0; output <= "010111";
end if;
when others => next_state <= "-----"; output <= "------";
end case;
end process;
end behaviour;
|
-------------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2014, Digilent RO. All rights reserved
--
-------------------------------------------------------------------------------
-- FILE NAME : ram2ddr.vhd
-- MODULE NAME : RAM to DDR2 Interface Converter with internal XADC
-- instantiation
-- AUTHOR : Mihaita Nagy
-- AUTHOR'S EMAIL : mihaita.nagy@digilent.ro
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2014-02-04 Mihaita Nagy Created
-- 1.1 2014-04-04 Mihaita Nagy Fixed double registering write bug
-------------------------------------------------------------------------------
-- DESCRIPTION : This module implements a simple Static RAM to DDR2 interface
-- converter designed to be used with Digilent Nexys4-DDR board
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------
entity Ram2Ddr is
port (
-- Common
clk_200MHz_i : in std_logic; -- 200 MHz system clock
rst_i : in std_logic; -- active high system reset
device_temp_i : in std_logic_vector(11 downto 0);
-- RAM interface
ram_a : in std_logic_vector(26 downto 0);
ram_dq_i : in std_logic_vector(15 downto 0);
ram_dq_o : out std_logic_vector(15 downto 0);
ram_cen : in std_logic;
ram_oen : in std_logic;
ram_wen : in std_logic;
ram_ub : in std_logic;
ram_lb : in std_logic;
-- DDR2 interface
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0)
);
end Ram2Ddr;
architecture Behavioral of Ram2Ddr is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
component mig_7series_0
port (
-- Inouts
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
-- Inputs
sys_clk_i : in std_logic;
sys_rst : in std_logic;
-- user interface signals
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(127 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(15 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(127 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
init_calib_complete : out std_logic);
end component;
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
-- FSM
type state_type is (stIdle, stPreset, stSendData, stSetCmdRd, stSetCmdWr,
stWaitCen);
------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------
-- ddr commands
constant CMD_WRITE : std_logic_vector(2 downto 0) := "000";
constant CMD_READ : std_logic_vector(2 downto 0) := "001";
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
-- state machine
signal cState, nState : state_type;
-- global signals
signal mem_ui_clk : std_logic;
signal mem_ui_rst : std_logic;
signal rst : std_logic;
signal rstn : std_logic;
signal sreg : std_logic_vector(1 downto 0);
-- ram internal signals
signal ram_a_int : std_logic_vector(26 downto 0);
signal ram_dq_i_int : std_logic_vector(15 downto 0);
signal ram_cen_int : std_logic;
signal ram_oen_int : std_logic;
signal ram_wen_int : std_logic;
signal ram_ub_int : std_logic;
signal ram_lb_int : std_logic;
-- ddr user interface signals
signal mem_addr : std_logic_vector(26 downto 0); -- address for current request
signal mem_cmd : std_logic_vector(2 downto 0); -- command for current request
signal mem_en : std_logic; -- active-high strobe for 'cmd' and 'addr'
signal mem_rdy : std_logic;
signal mem_wdf_rdy : std_logic; -- write data FIFO is ready to receive data (wdf_rdy = 1 & wdf_wren = 1)
signal mem_wdf_data : std_logic_vector(127 downto 0);
signal mem_wdf_end : std_logic; -- active-high last 'wdf_data'
signal mem_wdf_mask : std_logic_vector(15 downto 0);
signal mem_wdf_wren : std_logic;
signal mem_rd_data : std_logic_vector(127 downto 0);
signal mem_rd_data_end : std_logic; -- active-high last 'rd_data'
signal mem_rd_data_valid : std_logic; -- active-high 'rd_data' valid
signal calib_complete : std_logic; -- active-high calibration complete
------------------------------------------------------------------------
-- Signal attributes (debugging)
------------------------------------------------------------------------
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of cState : signal is "GRAY";
attribute ASYNC_REG : string;
attribute ASYNC_REG of sreg : signal is "TRUE";
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Registering the active-low reset for the MIG component
------------------------------------------------------------------------
RSTSYNC: process(clk_200MHz_i)
begin
if rising_edge(clk_200MHz_i) then
sreg <= sreg(0) & rst_i;
rstn <= not sreg(1);
end if;
end process RSTSYNC;
------------------------------------------------------------------------
-- DDR controller instance
------------------------------------------------------------------------
Inst_DDR: mig_7series_0
port map (
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
-- Inputs
sys_clk_i => clk_200MHz_i,
sys_rst => rstn,
-- user interface signals
app_addr => mem_addr,
app_cmd => mem_cmd,
app_en => mem_en,
app_wdf_data => mem_wdf_data,
app_wdf_end => mem_wdf_end,
app_wdf_mask => mem_wdf_mask,
app_wdf_wren => mem_wdf_wren,
app_rd_data => mem_rd_data,
app_rd_data_end => mem_rd_data_end,
app_rd_data_valid => mem_rd_data_valid,
app_rdy => mem_rdy,
app_wdf_rdy => mem_wdf_rdy,
app_sr_req => '0',
app_sr_active => open,
app_ref_req => '0',
app_ref_ack => open,
app_zq_req => '0',
app_zq_ack => open,
ui_clk => mem_ui_clk,
ui_clk_sync_rst => mem_ui_rst,
device_temp_i => device_temp_i,
init_calib_complete => calib_complete);
------------------------------------------------------------------------
-- Registering all inputs of the state machine to 'mem_ui_clk' domain
------------------------------------------------------------------------
REG_IN: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
ram_a_int <= ram_a;
ram_dq_i_int <= ram_dq_i;
ram_cen_int <= ram_cen;
ram_oen_int <= ram_oen;
ram_wen_int <= ram_wen;
ram_ub_int <= ram_ub;
ram_lb_int <= ram_lb;
end if;
end process REG_IN;
------------------------------------------------------------------------
-- State Machine
------------------------------------------------------------------------
-- Register states
SYNC_PROCESS: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if mem_ui_rst = '1' then
cState <= stIdle;
else
cState <= nState;
end if;
end if;
end process SYNC_PROCESS;
-- Next state logic
NEXT_STATE_DECODE: process(cState, calib_complete, ram_cen_int,
mem_rdy, mem_wdf_rdy, ram_wen_int, ram_oen_int)
begin
nState <= cState;
case(cState) is
-- If calibration is done successfully and CEN is
-- deasserted then start a new transaction
when stIdle =>
if ram_cen_int = '0' and
calib_complete = '1' then
nState <= stPreset;
end if;
-- In this state we store the address and data to
-- be written or the address to read from. We need
-- this additional state to make sure that all input
-- transitions are fully settled and registered
when stPreset =>
if ram_wen_int = '0' then
nState <= stSendData;
elsif ram_oen_int = '0' then
nState <= stSetCmdRd;
end if;
-- In a write transaction the data it written first
-- giving higher priority to 'mem_wdf_rdy' frag over
-- 'mem_rdy'
when stSendData =>
if mem_wdf_rdy = '1' then
nState <= stSetCmdWr;
end if;
-- Sending the read command and wait for the 'mem_rdy'
-- frag to be asserted (in case it's not)
when stSetCmdRd =>
if mem_rdy = '1' then
nState <= stWaitCen;
end if;
-- Sending the write command after the data has been
-- written to the controller FIFO and wait ro the
-- 'mem_rdy' frag to be asserted (in case it's not)
when stSetCmdWr =>
if mem_rdy = '1' then
nState <= stWaitCen;
end if;
-- After sending all the control signals and data, we
-- wait for the external CEN to signal transaction
-- end
when stWaitCen =>
if ram_cen_int = '1' then
nState <= stIdle;
end if;
when others => nState <= stIdle;
end case;
end process;
------------------------------------------------------------------------
-- Generating the FIFO control and command signals according to the
-- current state of the FSM
------------------------------------------------------------------------
MEM_WR_CTL: process(cState)
begin
if cState = stSendData then
mem_wdf_wren <= '1';
mem_wdf_end <= '1';
else
mem_wdf_wren <= '0';
mem_wdf_end <= '0';
end if;
end process MEM_WR_CTL;
MEM_CTL: process(cState)
begin
if cState = stSetCmdRd then
mem_en <= '1';
mem_cmd <= CMD_READ;
elsif cState = stSetCmdWr then
mem_en <= '1';
mem_cmd <= CMD_WRITE;
else
mem_en <= '0';
mem_cmd <= (others => '0');
end if;
end process MEM_CTL;
------------------------------------------------------------------------
-- Decoding the least significant 3 bits of the address and creating
-- accordingly the 'mem_wdf_mask'
------------------------------------------------------------------------
WR_DATA_MSK: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stPreset then
case(ram_a_int(2 downto 0)) is
when "000" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111111111111101";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111111111110";
else -- 16-bit
mem_wdf_mask <= "1111111111111100";
end if;
when "001" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111111111110111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111111111011";
else -- 16-bit
mem_wdf_mask <= "1111111111110011";
end if;
when "010" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111111111011111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111111101111";
else -- 16-bit
mem_wdf_mask <= "1111111111001111";
end if;
when "011" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111111101111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111110111111";
else -- 16-bit
mem_wdf_mask <= "1111111100111111";
end if;
when "100" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111110111111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111011111111";
else -- 16-bit
mem_wdf_mask <= "1111110011111111";
end if;
when "101" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111011111111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111101111111111";
else -- 16-bit
mem_wdf_mask <= "1111001111111111";
end if;
when "110" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1101111111111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1110111111111111";
else -- 16-bit
mem_wdf_mask <= "1100111111111111";
end if;
when "111" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "0111111111111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1011111111111111";
else -- 16-bit
mem_wdf_mask <= "0011111111111111";
end if;
when others => null;
end case;
end if;
end if;
end process WR_DATA_MSK;
------------------------------------------------------------------------
-- Registering write data and read/write address
------------------------------------------------------------------------
WR_DATA_ADDR: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stPreset then
mem_wdf_data <= ram_dq_i_int & ram_dq_i_int & ram_dq_i_int &
ram_dq_i_int & ram_dq_i_int & ram_dq_i_int &
ram_dq_i_int & ram_dq_i_int;
end if;
end if;
end process WR_DATA_ADDR;
WR_ADDR: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stPreset then
mem_addr <= ram_a_int(26 downto 3) & "000";
end if;
end if;
end process WR_ADDR;
------------------------------------------------------------------------
-- Mask and output the read data from the FIFO
------------------------------------------------------------------------
RD_DATA: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stWaitCen and mem_rd_data_valid = '1' and
mem_rd_data_end = '1' then
case(ram_a_int(2 downto 0)) is
when "000" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(15 downto 8) &
mem_rd_data(15 downto 8);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(7 downto 0) &
mem_rd_data(7 downto 0);
else -- 16-bit
ram_dq_o <= mem_rd_data(15 downto 0);
end if;
when "001" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(31 downto 24) &
mem_rd_data(31 downto 24);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(23 downto 16) &
mem_rd_data(23 downto 16);
else -- 16-bit
ram_dq_o <= mem_rd_data(31 downto 16);
end if;
when "010" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(47 downto 40) &
mem_rd_data(47 downto 40);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(39 downto 32) &
mem_rd_data(39 downto 32);
else -- 16-bit
ram_dq_o <= mem_rd_data(47 downto 32);
end if;
when "011" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(63 downto 56) &
mem_rd_data(63 downto 56);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(55 downto 48) &
mem_rd_data(55 downto 48);
else -- 16-bit
ram_dq_o <= mem_rd_data(63 downto 48);
end if;
when "100" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(79 downto 72) &
mem_rd_data(79 downto 72);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(71 downto 64) &
mem_rd_data(71 downto 64);
else -- 16-bit
ram_dq_o <= mem_rd_data(79 downto 64);
end if;
when "101" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(95 downto 88) &
mem_rd_data(95 downto 88);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(87 downto 80) &
mem_rd_data(87 downto 80);
else -- 16-bit
ram_dq_o <= mem_rd_data(95 downto 80);
end if;
when "110" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(111 downto 104) &
mem_rd_data(111 downto 104);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(103 downto 96) &
mem_rd_data(103 downto 96);
else -- 16-bit
ram_dq_o <= mem_rd_data(111 downto 96);
end if;
when "111" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(127 downto 120) &
mem_rd_data(127 downto 120);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(119 downto 112) &
mem_rd_data(119 downto 112);
else -- 16-bit
ram_dq_o <= mem_rd_data(127 downto 112);
end if;
when others => null;
end case;
end if;
end if;
end process RD_DATA;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
generic(
size : integer := 24
);
port(
audio_mixed_a_b_left_out : out std_logic_vector(size - 1 downto 0);
audio_mixed_a_b_right_out : out std_logic_vector(size - 1 downto 0);
audio_channel_a_left_in : in std_logic_vector(size - 1 downto 0);
audio_channel_a_right_in : in std_logic_vector(size - 1 downto 0);
audio_channel_b_left_in : in std_logic_vector(size - 1 downto 0);
audio_channel_b_right_in : in std_logic_vector(size - 1 downto 0)
);
end entity top_level;
architecture RTL of top_level is
begin
audio_mixed_a_b_left_out <=std_logic_vector(unsigned( audio_channel_a_left_in (size - 1 downto 0)) + unsigned( audio_channel_b_left_in (size - 1 downto 0)));
audio_mixed_a_b_right_out <=std_logic_vector(unsigned( audio_channel_a_right_in(size - 1 downto 0)) + unsigned( audio_channel_b_right_in(size - 1 downto 0)));
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
generic(
size : integer := 24
);
port(
audio_mixed_a_b_left_out : out std_logic_vector(size - 1 downto 0);
audio_mixed_a_b_right_out : out std_logic_vector(size - 1 downto 0);
audio_channel_a_left_in : in std_logic_vector(size - 1 downto 0);
audio_channel_a_right_in : in std_logic_vector(size - 1 downto 0);
audio_channel_b_left_in : in std_logic_vector(size - 1 downto 0);
audio_channel_b_right_in : in std_logic_vector(size - 1 downto 0)
);
end entity top_level;
architecture RTL of top_level is
begin
audio_mixed_a_b_left_out <=std_logic_vector(unsigned( audio_channel_a_left_in (size - 1 downto 0)) + unsigned( audio_channel_b_left_in (size - 1 downto 0)));
audio_mixed_a_b_right_out <=std_logic_vector(unsigned( audio_channel_a_right_in(size - 1 downto 0)) + unsigned( audio_channel_b_right_in(size - 1 downto 0)));
end architecture RTL;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux IS
GENERIC(select_width, line_width : positive);
PORT(
INPUT : IN std_logic_vector(2**select_width*line_width-1 DOWNTO 0);
SEL : IN std_logic_vector(select_width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(line_width-1 DOWNTO 0)
);
END mux;
ARCHITECTURE recursive OF mux IS
SIGNAL submux_0_OUT, submux_1_OUT : std_logic_vector(line_width-1 DOWNTO 0);
COMPONENT mux
GENERIC(select_width, line_width : positive);
PORT(
INPUT : IN std_logic_vector(2**select_width*line_width-1 DOWNTO 0);
SEL : IN std_logic_vector(select_width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(line_width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : mux USE ENTITY WORK.mux(recursive);
BEGIN
mux2to1: IF select_width=1 GENERATE
OUTPUT <= INPUT(2*line_width-1 DOWNTO line_width) WHEN SEL="1"
ELSE INPUT(line_width-1 DOWNTO 0);
END GENERATE;
muxNto1: IF select_width>1 GENERATE
submux_0: mux
GENERIC MAP(select_width => select_width-1, line_width => line_width)
PORT MAP(INPUT => INPUT(2**(select_width-1)*line_width-1 DOWNTO 0),
SEL => SEL(select_width-2 DOWNTO 0),
OUTPUT => submux_0_OUT);
submux_1: mux
GENERIC MAP(select_width => select_width-1, line_width => line_width)
PORT MAP(INPUT => INPUT(2**select_width*line_width-1 DOWNTO 2**(select_width-1)*line_width),
SEL => SEL(select_width-2 DOWNTO 0),
OUTPUT => submux_1_OUT);
OUTPUT <= submux_1_OUT WHEN SEL(select_width-1)='1' ELSE submux_0_OUT;
END GENERATE;
END recursive;
|
-------------------------------------------------------------------------------
--
-- The L port controller.
--
-- $Id: t400_io_l.vhd,v 1.4 2006-06-05 20:33:24 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_io_l is
generic (
opt_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
in_en_i : in boolean;
-- Control Interface ------------------------------------------------------
op_i : in io_l_op_t;
en2_i : in std_logic;
m_i : in dw_t;
a_i : in dw_t;
pm_data_i : in byte_t;
q_o : out byte_t;
-- Microbus Interface -----------------------------------------------------
cs_n_i : in std_logic;
rd_n_i : in std_logic;
wr_n_i : in std_logic;
-- Port L Interface -------------------------------------------------------
io_l_i : in byte_t;
io_l_o : out byte_t;
io_l_en_o : out byte_t
);
end t400_io_l;
use work.t400_io_pack.all;
architecture rtl of t400_io_l is
signal q_q : byte_t;
signal en2_s : std_logic;
begin
-----------------------------------------------------------------------------
-- Process q_reg
--
-- Purpose:
-- Implements the Q register.
--
q_reg: process (ck_i, por_i)
begin
if por_i then
q_q <= (others => '0');
elsif ck_i'event and ck_i = '1' then
if ck_en_i then
case op_i is
-- Load Q from accumulator and data memory --------------------------
when IOL_LOAD_AM =>
q_q(7 downto 4) <= a_i;
q_q(3 downto 0) <= m_i;
-- Load Q from program memory ---------------------------------------
when IOL_LOAD_PM =>
q_q <= pm_data_i;
when others =>
null;
end case;
end if;
-- Microbus functionality
if opt_microbus_g = t400_opt_microbus_c and
cs_n_i = '0' and wr_n_i = '0' then
q_q <= to_X01(io_l_i);
end if;
end if;
end process q_reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Multiplexer providing read data to the system.
-----------------------------------------------------------------------------
q_o <= to_X01(io_l_i)
when op_i = IOL_OUTPUT_L else
q_q;
-----------------------------------------------------------------------------
-- Dedicated output enable when in Microbus mode
-----------------------------------------------------------------------------
en2_s <= cs_n_i nor rd_n_i
when opt_microbus_g = t400_opt_microbus_c else
en2_i;
-----------------------------------------------------------------------------
-- Process out_driver
--
-- Purpose:
-- Implements the output driver data and enable.
--
out_driver: process (en2_s,
q_q)
begin
-- bit 7
io_l_o(7) <= io_out_f(dat => q_q(7),
opt => opt_out_type_7_g);
io_l_en_o(7) <= io_en_f (en => en2_s, dat => q_q(7),
opt => opt_out_type_7_g);
-- bit 6
io_l_o(6) <= io_out_f(dat => q_q(6),
opt => opt_out_type_6_g);
io_l_en_o(6) <= io_en_f (en => en2_s, dat => q_q(6),
opt => opt_out_type_6_g);
-- bit 5
io_l_o(5) <= io_out_f(dat => q_q(5),
opt => opt_out_type_5_g);
io_l_en_o(5) <= io_en_f (en => en2_s, dat => q_q(5),
opt => opt_out_type_5_g);
-- bit 4
io_l_o(4) <= io_out_f(dat => q_q(4),
opt => opt_out_type_4_g);
io_l_en_o(4) <= io_en_f (en => en2_s, dat => q_q(4),
opt => opt_out_type_4_g);
-- bit 3
io_l_o(3) <= io_out_f(dat => q_q(3),
opt => opt_out_type_3_g);
io_l_en_o(3) <= io_en_f (en => en2_s, dat => q_q(3),
opt => opt_out_type_3_g);
-- bit 2
io_l_o(2) <= io_out_f(dat => q_q(2),
opt => opt_out_type_2_g);
io_l_en_o(2) <= io_en_f (en => en2_s, dat => q_q(2),
opt => opt_out_type_2_g);
-- bit 1
io_l_o(1) <= io_out_f(dat => q_q(1),
opt => opt_out_type_1_g);
io_l_en_o(1) <= io_en_f (en => en2_s, dat => q_q(1),
opt => opt_out_type_1_g);
-- bit 0
io_l_o(0) <= io_out_f(dat => q_q(0),
opt => opt_out_type_0_g);
io_l_en_o(0) <= io_en_f (en => en2_s, dat => q_q(0),
opt => opt_out_type_0_g);
end process out_driver;
--
-----------------------------------------------------------------------------
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.3 2006/06/05 14:21:21 arniml
-- latch io_l_i upon input enable trigger
--
-- Revision 1.2 2006/05/23 01:14:28 arniml
-- use to_X01 for primary input bus
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
|
architecture ARCH of ENTITY is
begin
-- Passing
PROC_2 : process (a) is
begin
a := b or -- c = '2';
c or
d = '1';
c1 := d;
e12 := f and g and h
or i and j;
case CASE_LOGIC is
when a = 1 =>
a := b or
c and
d = '1';
when b = 1 =>
if a = 1 then
c12 := d or e or
f and g;
e1 := f and x or y;
end if;
end case;
a :=
b;
end process PROC_2;
-- Violations
PROC_2 : process (a) is
begin
a := b or -- c = '2';
c or
d = '1';
c1 := d;
e12 := f and g and h
or i and j;
case CASE_LOGIC is
when a = 1 =>
a := b or
c and
d = '1';
when b = 1 =>
if a = 1 then
c12 := d or e or
f and g;
e1 := f and x or y;
end if;
end case;
a :=
b;
end process PROC_2;
end architecture ARCH;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity barrel_tb is
end entity;
architecture barrel_tb of barrel_tb is
component barrel is
port (
clk : in std_logic;
se : in std_logic_vector(1 downto 0);
I : in std_logic_vector(3 downto 0);
Q,Q2 : out std_logic_vector(3 downto 0)
);
end component;
for barrel_0 : barrel use entity work.barrel;
signal clk : std_logic :='1';
signal se : std_logic_vector(1 downto 0);
signal Q,Q2,I : std_logic_vector(3 downto 0);
constant period : time := 10 ns;
begin
barrel_0: barrel port map(clk=>clk, se=>se, I=>I, Q=>Q, Q2=>Q2);
clk_proc:
process
begin
clk<=not clk;
wait for period/2;
end process;
stim_proc:
process
begin
I<="1001";
se<="00";
wait for 20 ns;
se<="01";
wait for 20 ns;
se<="10";
wait for 20 ns;
se<="11";
wait for 20 ns;
wait;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:38:44 05/01/2014
-- Design Name:
-- Module Name: fft_1d - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fft_1d is
Port ( clk : in STD_LOGIC);
end fft_1d;
architecture Behavioral of fft_1d is
begin
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_aa
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:11 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_aa-e.vhd,v 1.3 2005/07/15 16:20:07 wig Exp $
-- $Date: 2005/07/15 16:20:07 $
-- $Log: ent_aa-e.vhd,v $
-- Revision 1.3 2005/07/15 16:20:07 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- Generated use statements
library use_a;
use use_a.c_a.c_b.all;
use use_a.c_a2.all;
--
--
-- Start of Generated Entity ent_aa
--
entity ent_aa is
-- Generics:
-- No Generated Generics for Entity ent_aa
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_aa
port_aa_1 : out std_ulogic;
port_aa_2 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
port_aa_3 : out std_ulogic;
port_aa_4 : in std_ulogic;
port_aa_5 : out std_ulogic_vector(3 downto 0);
port_aa_6 : out std_ulogic_vector(3 downto 0);
sig_07 : out std_ulogic_vector(5 downto 0);
sig_08 : out std_ulogic_vector(8 downto 2);
sig_13 : out std_ulogic_vector(4 downto 0)
-- End of Generated Port for Entity ent_aa
);
end ent_aa;
--
-- End of Generated Entity ent_aa
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package hash_array_pkg is
type hash_array is array(integer range <>) of std_logic_vector(127 downto 0);
type md5_indata_t is
record
data_0 : std_logic_vector(31 downto 0);
data_1 : std_logic_vector(31 downto 0);
start : std_logic;
len : std_logic_vector(7 downto 0);
end record;
type md5_indata_t_array is array(integer range <>) of md5_indata_t;
end hash_array_pkg; |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_64x512_hf_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_64x512_hf_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_64x512_hf_top;
architecture xilinx of fifo_64x512_hf_top is
SIGNAL clk_i : std_logic;
component fifo_64x512_hf is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_64x512_hf PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Mon Sep 16 05:33:22 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_pointer_basic_0_1_stub.vhdl
-- Design : design_1_pointer_basic_0_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
s_axi_pointer_basic_io_AWADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_pointer_basic_io_AWVALID : in STD_LOGIC;
s_axi_pointer_basic_io_AWREADY : out STD_LOGIC;
s_axi_pointer_basic_io_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_pointer_basic_io_WVALID : in STD_LOGIC;
s_axi_pointer_basic_io_WREADY : out STD_LOGIC;
s_axi_pointer_basic_io_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_pointer_basic_io_BVALID : out STD_LOGIC;
s_axi_pointer_basic_io_BREADY : in STD_LOGIC;
s_axi_pointer_basic_io_ARADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_pointer_basic_io_ARVALID : in STD_LOGIC;
s_axi_pointer_basic_io_ARREADY : out STD_LOGIC;
s_axi_pointer_basic_io_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_pointer_basic_io_RVALID : out STD_LOGIC;
s_axi_pointer_basic_io_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
interrupt : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_pointer_basic_io_AWADDR[4:0],s_axi_pointer_basic_io_AWVALID,s_axi_pointer_basic_io_AWREADY,s_axi_pointer_basic_io_WDATA[31:0],s_axi_pointer_basic_io_WSTRB[3:0],s_axi_pointer_basic_io_WVALID,s_axi_pointer_basic_io_WREADY,s_axi_pointer_basic_io_BRESP[1:0],s_axi_pointer_basic_io_BVALID,s_axi_pointer_basic_io_BREADY,s_axi_pointer_basic_io_ARADDR[4:0],s_axi_pointer_basic_io_ARVALID,s_axi_pointer_basic_io_ARREADY,s_axi_pointer_basic_io_RDATA[31:0],s_axi_pointer_basic_io_RRESP[1:0],s_axi_pointer_basic_io_RVALID,s_axi_pointer_basic_io_RREADY,ap_clk,ap_rst_n,interrupt";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "pointer_basic,Vivado 2018.2";
begin
end;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY mult_n IS
GENERIC(
Nb: INTEGER := 9
);
PORT(
in_a: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
in_b: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
mult_out: OUT STD_LOGIC_VECTOR(2*Nb-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE beh_mult OF mult_n IS
SIGNAL mult_signed: SIGNED((2*Nb)-1 DOWNTO 0);
BEGIN
multiplication: PROCESS(in_a, in_b)
BEGIN
mult_signed <= SIGNED(in_a) * SIGNED(in_b);
END PROCESS;
mult_out <= STD_LOGIC_VECTOR(mult_signed);
END beh_mult;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_570 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_570;
architecture augh of add_570 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_570 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_570;
architecture augh of add_570 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity FPMultiply_top is
port(switches : in std_logic_vector(7 downto 0);
result : out std_logic_vector(7 downto 0));
end FPMultiply_top;
architecture Behavioral of FPMultiply_top is
component FPMultiply is
port( A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
R : out std_logic_vector(31 downto 0));
end component;
signal result_s : std_logic_vector(31 downto 0);
signal A_s, B_s : std_logic_vector(31 downto 0);
begin
A_s <= x"0000000" & switches(3 downto 0);
B_s <= x"0000000" & switches(7 downto 4);
fpm : FPMultiply
port map( A => A_s,
B => B_s,
R => result_s);
result <= result_s(7 downto 0);
end Behavioral;
|
--
-- Copyright (c) 2011 OrphanedGland (wilhelm.klink@gmail.com)
-- Send donations to : 1PioyqqFWXbKryxysGqoq5XAu9MTRANCEP
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- SHA256 core using H+K+W precalculation technique
-- Inspired by fpgaminer's sha256_transform.v
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sha256_pc is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end entity sha256_pc;
architecture sha256_pc_rtl of sha256_pc is
alias slv is std_logic_vector;
subtype msg is unsigned(511 downto 0);
subtype word is unsigned(31 downto 0);
function e0(x: unsigned(31 downto 0)) return unsigned is
begin
return (x(1 downto 0) & x(31 downto 2)) xor (x(12 downto 0) & x(31 downto 13)) xor (x(21 downto 0) & x(31 downto 22));
end e0;
function e1(x: unsigned(31 downto 0)) return unsigned is
begin
return (x(5 downto 0) & x(31 downto 6)) xor (x(10 downto 0) & x(31 downto 11)) xor (x(24 downto 0) & x(31 downto 25));
end e1;
function s0(x: unsigned(31 downto 0)) return unsigned is
variable y : unsigned(31 downto 0);
begin
y(31 downto 29) := x(6 downto 4) xor x(17 downto 15);
y(28 downto 0) := (x(3 downto 0) & x(31 downto 7)) xor (x(14 downto 0) & x(31 downto 18)) xor x(31 downto 3);
return y;
end s0;
function s1(x: unsigned(31 downto 0)) return unsigned is
variable y : unsigned(31 downto 0);
begin
y(31 downto 22) := x(16 downto 7) xor x(18 downto 9);
y(21 downto 0) := (x(6 downto 0) & x(31 downto 17)) xor (x(8 downto 0) & x(31 downto 19)) xor x(31 downto 10);
return y;
end s1;
function ch(x: unsigned(31 downto 0); y: unsigned(31 downto 0); z: unsigned(31 downto 0)) return unsigned is
begin
return (x and y) xor (not(x) and z);
end ch;
function maj(x: unsigned(31 downto 0); y: unsigned(31 downto 0); z: unsigned(31 downto 0)) return unsigned is
begin
return (x and y) xor (x and z) xor (y and z);
end maj;
type msg_array is array(0 to 63) of msg;
type word_array is array(0 to 63) of word;
type hash_array is array(0 to 7) of word;
constant k : word_array := ( X"428a2f98", X"71374491", X"b5c0fbcf", X"e9b5dba5", X"3956c25b", X"59f111f1", X"923f82a4", X"ab1c5ed5",
X"d807aa98", X"12835b01", X"243185be", X"550c7dc3", X"72be5d74", X"80deb1fe", X"9bdc06a7", X"c19bf174",
X"e49b69c1", X"efbe4786", X"0fc19dc6", X"240ca1cc", X"2de92c6f", X"4a7484aa", X"5cb0a9dc", X"76f988da",
X"983e5152", X"a831c66d", X"b00327c8", X"bf597fc7", X"c6e00bf3", X"d5a79147", X"06ca6351", X"14292967",
X"27b70a85", X"2e1b2138", X"4d2c6dfc", X"53380d13", X"650a7354", X"766a0abb", X"81c2c92e", X"92722c85",
X"a2bfe8a1", X"a81a664b", X"c24b8b70", X"c76c51a3", X"d192e819", X"d6990624", X"f40e3585", X"106aa070",
X"19a4c116", X"1e376c08", X"2748774c", X"34b0bcb5", X"391c0cb3", X"4ed8aa4a", X"5b9cca4f", X"682e6ff3",
X"748f82ee", X"78a5636f", X"84c87814", X"8cc70208", X"90befffa", X"a4506ceb", X"bef9a3f7", X"c67178f2" );
constant h_default : hash_array := ( X"6a09e667", X"bb67ae85", X"3c6ef372", X"a54ff53a", X"510e527f", X"9b05688c", X"1f83d9ab", X"5be0cd19" );
signal w : msg_array;
signal new_w : word_array;
signal t1 : word_array;
signal t2 : word_array;
signal a : word_array;
signal b : word_array;
signal c : word_array;
signal d : word_array;
signal e : word_array;
signal f : word_array;
signal g : word_array;
signal h : word_array;
signal hkw_precalc : word_array;
signal hash : hash_array;
signal h_init : hash_array;
signal q_w : msg_array;
signal q_a : word_array;
signal q_b : word_array;
signal q_c : word_array;
signal q_d : word_array;
signal q_e : word_array;
signal q_f : word_array;
signal q_g : word_array;
signal q_h : word_array;
signal q_hkw_precalc : word_array;
signal q_hash : hash_array;
signal q_msg : msg;
begin
output_mapping: for i in 0 to 7 generate
--digest((i+1)*32-1 downto i*32) <= slv(q_hash(7-i));
digest((i+1)*32-1 downto i*32) <= slv(q_hash(i));
end generate output_mapping;
default_h_gen: if default_h = true generate
h_init <= h_default;
end generate default_h_gen;
h_gen: if default_h = false generate
h_array_gen: for i in 0 to 7 generate
h_init(i) <= unsigned(h_in((i+1)*32-1 downto i*32));
end generate h_array_gen;
end generate h_gen;
hkw_precalc(0) <= h_init(7) + k(0) + unsigned(msg_in(31 downto 0));
hash_pipeline: for i in 0 to 63 generate
first_stage: if i = 0 generate
t1_no_precalc_gen: if default_h = true generate
-- no point precalculating when constants are used, so save a clock cycle
t1(i) <= h_init(7) + e1(h_init(4)) + ch(h_init(4), h_init(5), h_init(6)) + k(i) + w(i)(31 downto 0);
w(i) <= unsigned(msg_in);
end generate t1_no_precalc_gen;
t1_precalc_gen: if default_h = false generate
t1(i) <= e1(h_init(4)) + ch(h_init(4), h_init(5), h_init(6)) + q_hkw_precalc(i);
w(i) <= q_msg;
end generate t1_precalc_gen;
t2(i) <= e0(h_init(0)) + maj(h_init(0), h_init(1), h_init(2));
a(i) <= t1(i) + t2(i);
b(i) <= h_init(0);
c(i) <= h_init(1);
d(i) <= h_init(2);
e(i) <= h_init(3) + t1(i);
f(i) <= h_init(4);
g(i) <= h_init(5);
h(i) <= h_init(6);
hkw_precalc(i+1) <= h_init(6) + k(i+1) + w(i)(63 downto 32);
end generate first_stage;
other_stages: if i /= 0 generate
t1(i) <= e1(q_e(i-1)) + ch(q_e(i-1), q_f(i-1), q_g(i-1)) + q_hkw_precalc(i);
t2(i) <= e0(q_a(i-1)) + maj(q_a(i-1), q_b(i-1), q_c(i-1));
new_w(i) <= s1(q_w(i-1)(479 downto 448)) + q_w(i-1)(319 downto 288) + s0(q_w(i-1)(63 downto 32)) + q_w(i-1)(31 downto 0);
w(i) <= new_w(i) & q_w(i-1)(511 downto 32);
a(i) <= t1(i) + t2(i);
b(i) <= q_a(i-1);
c(i) <= q_b(i-1);
d(i) <= q_c(i-1);
e(i) <= q_d(i-1) + t1(i);
f(i) <= q_e(i-1);
g(i) <= q_f(i-1);
h(i) <= q_g(i-1);
precalc: if i /= 63 generate
hkw_precalc(i+1) <= q_g(i-1) + k(i+1) + w(i)(63 downto 32);
end generate precalc;
end generate other_stages;
end generate hash_pipeline;
hash(0) <= q_a(63) + h_init(0);
hash(1) <= q_b(63) + h_init(1);
hash(2) <= q_c(63) + h_init(2);
hash(3) <= q_d(63) + h_init(3);
hash(4) <= q_e(63) + h_init(4);
hash(5) <= q_f(63) + h_init(5);
hash(6) <= q_g(63) + h_init(6);
hash(7) <= q_h(63) + h_init(7);
registers : process(clk, reset) is
begin
if reset = '1' then
null;
elsif rising_edge(clk) then
q_msg <= unsigned(msg_in);
q_w <= w;
q_a <= a;
q_b <= b;
q_c <= c;
q_d <= d;
q_e <= e;
q_f <= f;
q_g <= g;
q_h <= h;
q_hkw_precalc <= hkw_precalc;
q_hash <= hash;
end if;
end process registers;
end architecture sha256_pc_rtl;
|
--
-- Copyright (c) 2011 OrphanedGland (wilhelm.klink@gmail.com)
-- Send donations to : 1PioyqqFWXbKryxysGqoq5XAu9MTRANCEP
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- SHA256 core using H+K+W precalculation technique
-- Inspired by fpgaminer's sha256_transform.v
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sha256_pc is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end entity sha256_pc;
architecture sha256_pc_rtl of sha256_pc is
alias slv is std_logic_vector;
subtype msg is unsigned(511 downto 0);
subtype word is unsigned(31 downto 0);
function e0(x: unsigned(31 downto 0)) return unsigned is
begin
return (x(1 downto 0) & x(31 downto 2)) xor (x(12 downto 0) & x(31 downto 13)) xor (x(21 downto 0) & x(31 downto 22));
end e0;
function e1(x: unsigned(31 downto 0)) return unsigned is
begin
return (x(5 downto 0) & x(31 downto 6)) xor (x(10 downto 0) & x(31 downto 11)) xor (x(24 downto 0) & x(31 downto 25));
end e1;
function s0(x: unsigned(31 downto 0)) return unsigned is
variable y : unsigned(31 downto 0);
begin
y(31 downto 29) := x(6 downto 4) xor x(17 downto 15);
y(28 downto 0) := (x(3 downto 0) & x(31 downto 7)) xor (x(14 downto 0) & x(31 downto 18)) xor x(31 downto 3);
return y;
end s0;
function s1(x: unsigned(31 downto 0)) return unsigned is
variable y : unsigned(31 downto 0);
begin
y(31 downto 22) := x(16 downto 7) xor x(18 downto 9);
y(21 downto 0) := (x(6 downto 0) & x(31 downto 17)) xor (x(8 downto 0) & x(31 downto 19)) xor x(31 downto 10);
return y;
end s1;
function ch(x: unsigned(31 downto 0); y: unsigned(31 downto 0); z: unsigned(31 downto 0)) return unsigned is
begin
return (x and y) xor (not(x) and z);
end ch;
function maj(x: unsigned(31 downto 0); y: unsigned(31 downto 0); z: unsigned(31 downto 0)) return unsigned is
begin
return (x and y) xor (x and z) xor (y and z);
end maj;
type msg_array is array(0 to 63) of msg;
type word_array is array(0 to 63) of word;
type hash_array is array(0 to 7) of word;
constant k : word_array := ( X"428a2f98", X"71374491", X"b5c0fbcf", X"e9b5dba5", X"3956c25b", X"59f111f1", X"923f82a4", X"ab1c5ed5",
X"d807aa98", X"12835b01", X"243185be", X"550c7dc3", X"72be5d74", X"80deb1fe", X"9bdc06a7", X"c19bf174",
X"e49b69c1", X"efbe4786", X"0fc19dc6", X"240ca1cc", X"2de92c6f", X"4a7484aa", X"5cb0a9dc", X"76f988da",
X"983e5152", X"a831c66d", X"b00327c8", X"bf597fc7", X"c6e00bf3", X"d5a79147", X"06ca6351", X"14292967",
X"27b70a85", X"2e1b2138", X"4d2c6dfc", X"53380d13", X"650a7354", X"766a0abb", X"81c2c92e", X"92722c85",
X"a2bfe8a1", X"a81a664b", X"c24b8b70", X"c76c51a3", X"d192e819", X"d6990624", X"f40e3585", X"106aa070",
X"19a4c116", X"1e376c08", X"2748774c", X"34b0bcb5", X"391c0cb3", X"4ed8aa4a", X"5b9cca4f", X"682e6ff3",
X"748f82ee", X"78a5636f", X"84c87814", X"8cc70208", X"90befffa", X"a4506ceb", X"bef9a3f7", X"c67178f2" );
constant h_default : hash_array := ( X"6a09e667", X"bb67ae85", X"3c6ef372", X"a54ff53a", X"510e527f", X"9b05688c", X"1f83d9ab", X"5be0cd19" );
signal w : msg_array;
signal new_w : word_array;
signal t1 : word_array;
signal t2 : word_array;
signal a : word_array;
signal b : word_array;
signal c : word_array;
signal d : word_array;
signal e : word_array;
signal f : word_array;
signal g : word_array;
signal h : word_array;
signal hkw_precalc : word_array;
signal hash : hash_array;
signal h_init : hash_array;
signal q_w : msg_array;
signal q_a : word_array;
signal q_b : word_array;
signal q_c : word_array;
signal q_d : word_array;
signal q_e : word_array;
signal q_f : word_array;
signal q_g : word_array;
signal q_h : word_array;
signal q_hkw_precalc : word_array;
signal q_hash : hash_array;
signal q_msg : msg;
begin
output_mapping: for i in 0 to 7 generate
--digest((i+1)*32-1 downto i*32) <= slv(q_hash(7-i));
digest((i+1)*32-1 downto i*32) <= slv(q_hash(i));
end generate output_mapping;
default_h_gen: if default_h = true generate
h_init <= h_default;
end generate default_h_gen;
h_gen: if default_h = false generate
h_array_gen: for i in 0 to 7 generate
h_init(i) <= unsigned(h_in((i+1)*32-1 downto i*32));
end generate h_array_gen;
end generate h_gen;
hkw_precalc(0) <= h_init(7) + k(0) + unsigned(msg_in(31 downto 0));
hash_pipeline: for i in 0 to 63 generate
first_stage: if i = 0 generate
t1_no_precalc_gen: if default_h = true generate
-- no point precalculating when constants are used, so save a clock cycle
t1(i) <= h_init(7) + e1(h_init(4)) + ch(h_init(4), h_init(5), h_init(6)) + k(i) + w(i)(31 downto 0);
w(i) <= unsigned(msg_in);
end generate t1_no_precalc_gen;
t1_precalc_gen: if default_h = false generate
t1(i) <= e1(h_init(4)) + ch(h_init(4), h_init(5), h_init(6)) + q_hkw_precalc(i);
w(i) <= q_msg;
end generate t1_precalc_gen;
t2(i) <= e0(h_init(0)) + maj(h_init(0), h_init(1), h_init(2));
a(i) <= t1(i) + t2(i);
b(i) <= h_init(0);
c(i) <= h_init(1);
d(i) <= h_init(2);
e(i) <= h_init(3) + t1(i);
f(i) <= h_init(4);
g(i) <= h_init(5);
h(i) <= h_init(6);
hkw_precalc(i+1) <= h_init(6) + k(i+1) + w(i)(63 downto 32);
end generate first_stage;
other_stages: if i /= 0 generate
t1(i) <= e1(q_e(i-1)) + ch(q_e(i-1), q_f(i-1), q_g(i-1)) + q_hkw_precalc(i);
t2(i) <= e0(q_a(i-1)) + maj(q_a(i-1), q_b(i-1), q_c(i-1));
new_w(i) <= s1(q_w(i-1)(479 downto 448)) + q_w(i-1)(319 downto 288) + s0(q_w(i-1)(63 downto 32)) + q_w(i-1)(31 downto 0);
w(i) <= new_w(i) & q_w(i-1)(511 downto 32);
a(i) <= t1(i) + t2(i);
b(i) <= q_a(i-1);
c(i) <= q_b(i-1);
d(i) <= q_c(i-1);
e(i) <= q_d(i-1) + t1(i);
f(i) <= q_e(i-1);
g(i) <= q_f(i-1);
h(i) <= q_g(i-1);
precalc: if i /= 63 generate
hkw_precalc(i+1) <= q_g(i-1) + k(i+1) + w(i)(63 downto 32);
end generate precalc;
end generate other_stages;
end generate hash_pipeline;
hash(0) <= q_a(63) + h_init(0);
hash(1) <= q_b(63) + h_init(1);
hash(2) <= q_c(63) + h_init(2);
hash(3) <= q_d(63) + h_init(3);
hash(4) <= q_e(63) + h_init(4);
hash(5) <= q_f(63) + h_init(5);
hash(6) <= q_g(63) + h_init(6);
hash(7) <= q_h(63) + h_init(7);
registers : process(clk, reset) is
begin
if reset = '1' then
null;
elsif rising_edge(clk) then
q_msg <= unsigned(msg_in);
q_w <= w;
q_a <= a;
q_b <= b;
q_c <= c;
q_d <= d;
q_e <= e;
q_f <= f;
q_g <= g;
q_h <= h;
q_hkw_precalc <= hkw_precalc;
q_hash <= hash;
end if;
end process registers;
end architecture sha256_pc_rtl;
|
--
-- Copyright (c) 2011 OrphanedGland (wilhelm.klink@gmail.com)
-- Send donations to : 1PioyqqFWXbKryxysGqoq5XAu9MTRANCEP
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- SHA256 core using H+K+W precalculation technique
-- Inspired by fpgaminer's sha256_transform.v
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sha256_pc is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end entity sha256_pc;
architecture sha256_pc_rtl of sha256_pc is
alias slv is std_logic_vector;
subtype msg is unsigned(511 downto 0);
subtype word is unsigned(31 downto 0);
function e0(x: unsigned(31 downto 0)) return unsigned is
begin
return (x(1 downto 0) & x(31 downto 2)) xor (x(12 downto 0) & x(31 downto 13)) xor (x(21 downto 0) & x(31 downto 22));
end e0;
function e1(x: unsigned(31 downto 0)) return unsigned is
begin
return (x(5 downto 0) & x(31 downto 6)) xor (x(10 downto 0) & x(31 downto 11)) xor (x(24 downto 0) & x(31 downto 25));
end e1;
function s0(x: unsigned(31 downto 0)) return unsigned is
variable y : unsigned(31 downto 0);
begin
y(31 downto 29) := x(6 downto 4) xor x(17 downto 15);
y(28 downto 0) := (x(3 downto 0) & x(31 downto 7)) xor (x(14 downto 0) & x(31 downto 18)) xor x(31 downto 3);
return y;
end s0;
function s1(x: unsigned(31 downto 0)) return unsigned is
variable y : unsigned(31 downto 0);
begin
y(31 downto 22) := x(16 downto 7) xor x(18 downto 9);
y(21 downto 0) := (x(6 downto 0) & x(31 downto 17)) xor (x(8 downto 0) & x(31 downto 19)) xor x(31 downto 10);
return y;
end s1;
function ch(x: unsigned(31 downto 0); y: unsigned(31 downto 0); z: unsigned(31 downto 0)) return unsigned is
begin
return (x and y) xor (not(x) and z);
end ch;
function maj(x: unsigned(31 downto 0); y: unsigned(31 downto 0); z: unsigned(31 downto 0)) return unsigned is
begin
return (x and y) xor (x and z) xor (y and z);
end maj;
type msg_array is array(0 to 63) of msg;
type word_array is array(0 to 63) of word;
type hash_array is array(0 to 7) of word;
constant k : word_array := ( X"428a2f98", X"71374491", X"b5c0fbcf", X"e9b5dba5", X"3956c25b", X"59f111f1", X"923f82a4", X"ab1c5ed5",
X"d807aa98", X"12835b01", X"243185be", X"550c7dc3", X"72be5d74", X"80deb1fe", X"9bdc06a7", X"c19bf174",
X"e49b69c1", X"efbe4786", X"0fc19dc6", X"240ca1cc", X"2de92c6f", X"4a7484aa", X"5cb0a9dc", X"76f988da",
X"983e5152", X"a831c66d", X"b00327c8", X"bf597fc7", X"c6e00bf3", X"d5a79147", X"06ca6351", X"14292967",
X"27b70a85", X"2e1b2138", X"4d2c6dfc", X"53380d13", X"650a7354", X"766a0abb", X"81c2c92e", X"92722c85",
X"a2bfe8a1", X"a81a664b", X"c24b8b70", X"c76c51a3", X"d192e819", X"d6990624", X"f40e3585", X"106aa070",
X"19a4c116", X"1e376c08", X"2748774c", X"34b0bcb5", X"391c0cb3", X"4ed8aa4a", X"5b9cca4f", X"682e6ff3",
X"748f82ee", X"78a5636f", X"84c87814", X"8cc70208", X"90befffa", X"a4506ceb", X"bef9a3f7", X"c67178f2" );
constant h_default : hash_array := ( X"6a09e667", X"bb67ae85", X"3c6ef372", X"a54ff53a", X"510e527f", X"9b05688c", X"1f83d9ab", X"5be0cd19" );
signal w : msg_array;
signal new_w : word_array;
signal t1 : word_array;
signal t2 : word_array;
signal a : word_array;
signal b : word_array;
signal c : word_array;
signal d : word_array;
signal e : word_array;
signal f : word_array;
signal g : word_array;
signal h : word_array;
signal hkw_precalc : word_array;
signal hash : hash_array;
signal h_init : hash_array;
signal q_w : msg_array;
signal q_a : word_array;
signal q_b : word_array;
signal q_c : word_array;
signal q_d : word_array;
signal q_e : word_array;
signal q_f : word_array;
signal q_g : word_array;
signal q_h : word_array;
signal q_hkw_precalc : word_array;
signal q_hash : hash_array;
signal q_msg : msg;
begin
output_mapping: for i in 0 to 7 generate
--digest((i+1)*32-1 downto i*32) <= slv(q_hash(7-i));
digest((i+1)*32-1 downto i*32) <= slv(q_hash(i));
end generate output_mapping;
default_h_gen: if default_h = true generate
h_init <= h_default;
end generate default_h_gen;
h_gen: if default_h = false generate
h_array_gen: for i in 0 to 7 generate
h_init(i) <= unsigned(h_in((i+1)*32-1 downto i*32));
end generate h_array_gen;
end generate h_gen;
hkw_precalc(0) <= h_init(7) + k(0) + unsigned(msg_in(31 downto 0));
hash_pipeline: for i in 0 to 63 generate
first_stage: if i = 0 generate
t1_no_precalc_gen: if default_h = true generate
-- no point precalculating when constants are used, so save a clock cycle
t1(i) <= h_init(7) + e1(h_init(4)) + ch(h_init(4), h_init(5), h_init(6)) + k(i) + w(i)(31 downto 0);
w(i) <= unsigned(msg_in);
end generate t1_no_precalc_gen;
t1_precalc_gen: if default_h = false generate
t1(i) <= e1(h_init(4)) + ch(h_init(4), h_init(5), h_init(6)) + q_hkw_precalc(i);
w(i) <= q_msg;
end generate t1_precalc_gen;
t2(i) <= e0(h_init(0)) + maj(h_init(0), h_init(1), h_init(2));
a(i) <= t1(i) + t2(i);
b(i) <= h_init(0);
c(i) <= h_init(1);
d(i) <= h_init(2);
e(i) <= h_init(3) + t1(i);
f(i) <= h_init(4);
g(i) <= h_init(5);
h(i) <= h_init(6);
hkw_precalc(i+1) <= h_init(6) + k(i+1) + w(i)(63 downto 32);
end generate first_stage;
other_stages: if i /= 0 generate
t1(i) <= e1(q_e(i-1)) + ch(q_e(i-1), q_f(i-1), q_g(i-1)) + q_hkw_precalc(i);
t2(i) <= e0(q_a(i-1)) + maj(q_a(i-1), q_b(i-1), q_c(i-1));
new_w(i) <= s1(q_w(i-1)(479 downto 448)) + q_w(i-1)(319 downto 288) + s0(q_w(i-1)(63 downto 32)) + q_w(i-1)(31 downto 0);
w(i) <= new_w(i) & q_w(i-1)(511 downto 32);
a(i) <= t1(i) + t2(i);
b(i) <= q_a(i-1);
c(i) <= q_b(i-1);
d(i) <= q_c(i-1);
e(i) <= q_d(i-1) + t1(i);
f(i) <= q_e(i-1);
g(i) <= q_f(i-1);
h(i) <= q_g(i-1);
precalc: if i /= 63 generate
hkw_precalc(i+1) <= q_g(i-1) + k(i+1) + w(i)(63 downto 32);
end generate precalc;
end generate other_stages;
end generate hash_pipeline;
hash(0) <= q_a(63) + h_init(0);
hash(1) <= q_b(63) + h_init(1);
hash(2) <= q_c(63) + h_init(2);
hash(3) <= q_d(63) + h_init(3);
hash(4) <= q_e(63) + h_init(4);
hash(5) <= q_f(63) + h_init(5);
hash(6) <= q_g(63) + h_init(6);
hash(7) <= q_h(63) + h_init(7);
registers : process(clk, reset) is
begin
if reset = '1' then
null;
elsif rising_edge(clk) then
q_msg <= unsigned(msg_in);
q_w <= w;
q_a <= a;
q_b <= b;
q_c <= c;
q_d <= d;
q_e <= e;
q_f <= f;
q_g <= g;
q_h <= h;
q_hkw_precalc <= hkw_precalc;
q_hash <= hash;
end if;
end process registers;
end architecture sha256_pc_rtl;
|
--
-- Copyright (c) 2011 OrphanedGland (wilhelm.klink@gmail.com)
-- Send donations to : 1PioyqqFWXbKryxysGqoq5XAu9MTRANCEP
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- SHA256 core using H+K+W precalculation technique
-- Inspired by fpgaminer's sha256_transform.v
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sha256_pc is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end entity sha256_pc;
architecture sha256_pc_rtl of sha256_pc is
alias slv is std_logic_vector;
subtype msg is unsigned(511 downto 0);
subtype word is unsigned(31 downto 0);
function e0(x: unsigned(31 downto 0)) return unsigned is
begin
return (x(1 downto 0) & x(31 downto 2)) xor (x(12 downto 0) & x(31 downto 13)) xor (x(21 downto 0) & x(31 downto 22));
end e0;
function e1(x: unsigned(31 downto 0)) return unsigned is
begin
return (x(5 downto 0) & x(31 downto 6)) xor (x(10 downto 0) & x(31 downto 11)) xor (x(24 downto 0) & x(31 downto 25));
end e1;
function s0(x: unsigned(31 downto 0)) return unsigned is
variable y : unsigned(31 downto 0);
begin
y(31 downto 29) := x(6 downto 4) xor x(17 downto 15);
y(28 downto 0) := (x(3 downto 0) & x(31 downto 7)) xor (x(14 downto 0) & x(31 downto 18)) xor x(31 downto 3);
return y;
end s0;
function s1(x: unsigned(31 downto 0)) return unsigned is
variable y : unsigned(31 downto 0);
begin
y(31 downto 22) := x(16 downto 7) xor x(18 downto 9);
y(21 downto 0) := (x(6 downto 0) & x(31 downto 17)) xor (x(8 downto 0) & x(31 downto 19)) xor x(31 downto 10);
return y;
end s1;
function ch(x: unsigned(31 downto 0); y: unsigned(31 downto 0); z: unsigned(31 downto 0)) return unsigned is
begin
return (x and y) xor (not(x) and z);
end ch;
function maj(x: unsigned(31 downto 0); y: unsigned(31 downto 0); z: unsigned(31 downto 0)) return unsigned is
begin
return (x and y) xor (x and z) xor (y and z);
end maj;
type msg_array is array(0 to 63) of msg;
type word_array is array(0 to 63) of word;
type hash_array is array(0 to 7) of word;
constant k : word_array := ( X"428a2f98", X"71374491", X"b5c0fbcf", X"e9b5dba5", X"3956c25b", X"59f111f1", X"923f82a4", X"ab1c5ed5",
X"d807aa98", X"12835b01", X"243185be", X"550c7dc3", X"72be5d74", X"80deb1fe", X"9bdc06a7", X"c19bf174",
X"e49b69c1", X"efbe4786", X"0fc19dc6", X"240ca1cc", X"2de92c6f", X"4a7484aa", X"5cb0a9dc", X"76f988da",
X"983e5152", X"a831c66d", X"b00327c8", X"bf597fc7", X"c6e00bf3", X"d5a79147", X"06ca6351", X"14292967",
X"27b70a85", X"2e1b2138", X"4d2c6dfc", X"53380d13", X"650a7354", X"766a0abb", X"81c2c92e", X"92722c85",
X"a2bfe8a1", X"a81a664b", X"c24b8b70", X"c76c51a3", X"d192e819", X"d6990624", X"f40e3585", X"106aa070",
X"19a4c116", X"1e376c08", X"2748774c", X"34b0bcb5", X"391c0cb3", X"4ed8aa4a", X"5b9cca4f", X"682e6ff3",
X"748f82ee", X"78a5636f", X"84c87814", X"8cc70208", X"90befffa", X"a4506ceb", X"bef9a3f7", X"c67178f2" );
constant h_default : hash_array := ( X"6a09e667", X"bb67ae85", X"3c6ef372", X"a54ff53a", X"510e527f", X"9b05688c", X"1f83d9ab", X"5be0cd19" );
signal w : msg_array;
signal new_w : word_array;
signal t1 : word_array;
signal t2 : word_array;
signal a : word_array;
signal b : word_array;
signal c : word_array;
signal d : word_array;
signal e : word_array;
signal f : word_array;
signal g : word_array;
signal h : word_array;
signal hkw_precalc : word_array;
signal hash : hash_array;
signal h_init : hash_array;
signal q_w : msg_array;
signal q_a : word_array;
signal q_b : word_array;
signal q_c : word_array;
signal q_d : word_array;
signal q_e : word_array;
signal q_f : word_array;
signal q_g : word_array;
signal q_h : word_array;
signal q_hkw_precalc : word_array;
signal q_hash : hash_array;
signal q_msg : msg;
begin
output_mapping: for i in 0 to 7 generate
--digest((i+1)*32-1 downto i*32) <= slv(q_hash(7-i));
digest((i+1)*32-1 downto i*32) <= slv(q_hash(i));
end generate output_mapping;
default_h_gen: if default_h = true generate
h_init <= h_default;
end generate default_h_gen;
h_gen: if default_h = false generate
h_array_gen: for i in 0 to 7 generate
h_init(i) <= unsigned(h_in((i+1)*32-1 downto i*32));
end generate h_array_gen;
end generate h_gen;
hkw_precalc(0) <= h_init(7) + k(0) + unsigned(msg_in(31 downto 0));
hash_pipeline: for i in 0 to 63 generate
first_stage: if i = 0 generate
t1_no_precalc_gen: if default_h = true generate
-- no point precalculating when constants are used, so save a clock cycle
t1(i) <= h_init(7) + e1(h_init(4)) + ch(h_init(4), h_init(5), h_init(6)) + k(i) + w(i)(31 downto 0);
w(i) <= unsigned(msg_in);
end generate t1_no_precalc_gen;
t1_precalc_gen: if default_h = false generate
t1(i) <= e1(h_init(4)) + ch(h_init(4), h_init(5), h_init(6)) + q_hkw_precalc(i);
w(i) <= q_msg;
end generate t1_precalc_gen;
t2(i) <= e0(h_init(0)) + maj(h_init(0), h_init(1), h_init(2));
a(i) <= t1(i) + t2(i);
b(i) <= h_init(0);
c(i) <= h_init(1);
d(i) <= h_init(2);
e(i) <= h_init(3) + t1(i);
f(i) <= h_init(4);
g(i) <= h_init(5);
h(i) <= h_init(6);
hkw_precalc(i+1) <= h_init(6) + k(i+1) + w(i)(63 downto 32);
end generate first_stage;
other_stages: if i /= 0 generate
t1(i) <= e1(q_e(i-1)) + ch(q_e(i-1), q_f(i-1), q_g(i-1)) + q_hkw_precalc(i);
t2(i) <= e0(q_a(i-1)) + maj(q_a(i-1), q_b(i-1), q_c(i-1));
new_w(i) <= s1(q_w(i-1)(479 downto 448)) + q_w(i-1)(319 downto 288) + s0(q_w(i-1)(63 downto 32)) + q_w(i-1)(31 downto 0);
w(i) <= new_w(i) & q_w(i-1)(511 downto 32);
a(i) <= t1(i) + t2(i);
b(i) <= q_a(i-1);
c(i) <= q_b(i-1);
d(i) <= q_c(i-1);
e(i) <= q_d(i-1) + t1(i);
f(i) <= q_e(i-1);
g(i) <= q_f(i-1);
h(i) <= q_g(i-1);
precalc: if i /= 63 generate
hkw_precalc(i+1) <= q_g(i-1) + k(i+1) + w(i)(63 downto 32);
end generate precalc;
end generate other_stages;
end generate hash_pipeline;
hash(0) <= q_a(63) + h_init(0);
hash(1) <= q_b(63) + h_init(1);
hash(2) <= q_c(63) + h_init(2);
hash(3) <= q_d(63) + h_init(3);
hash(4) <= q_e(63) + h_init(4);
hash(5) <= q_f(63) + h_init(5);
hash(6) <= q_g(63) + h_init(6);
hash(7) <= q_h(63) + h_init(7);
registers : process(clk, reset) is
begin
if reset = '1' then
null;
elsif rising_edge(clk) then
q_msg <= unsigned(msg_in);
q_w <= w;
q_a <= a;
q_b <= b;
q_c <= c;
q_d <= d;
q_e <= e;
q_f <= f;
q_g <= g;
q_h <= h;
q_hkw_precalc <= hkw_precalc;
q_hash <= hash;
end if;
end process registers;
end architecture sha256_pc_rtl;
|
----------------------------------------------------------------------------------
-- Company: Federal University of Santa Catarina
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
entity mipsMulticiclo is
port(
clock, reset: in std_logic;
gpio: inout std_logic_vector(31 downto 0)
);
end entity;
architecture estrutural of mipsMulticiclo is
component blocoOperativo is
port(
clock, reset: in std_logic;
PCEscCond, PCEsc, IouD, LerMem, EscMem, MemParaReg, IREsc, RegDst, EscReg, ULAFonteA: in std_logic;
ULAFonteB, ULAOp, FontePC: in std_logic_vector(1 downto 0);
opcode: out std_logic_vector(5 downto 0)
);
end component;
component blocoControle is
port(
clock, reset: in std_logic;
PCEscCond, PCEsc, IouD, LerMem, EscMem, MemParaReg, IREsc, RegDst, EscReg, ULAFonteA: out std_logic;
ULAFonteB, ULAOp, FontePC: out std_logic_vector(1 downto 0);
opcode: in std_logic_vector(5 downto 0)
);
end component;
signal PCEscCond, PCEsc, IouD, LerMem, EscMem, MemParaReg, IREsc, RegDst, EscReg, ULAFonteA: std_logic;
signal ULAFonteB, ULAOp, FontePC: std_logic_vector(1 downto 0);
signal opcode: std_logic_vector(5 downto 0);
begin
controle: blocoControle port map (clock, reset, PCEscCond, PCEsc, IouD, LerMem, EscMem, MemParaReg, IREsc, RegDst,
EscReg, ULAFonteA, ULAFonteB, ULAOp, FONtePC, opcode);
operativo: blocoOperativo port map (clock, reset, PCEscCond, PCEsc, IouD, LerMem, EscMem, MemParaReg, IREsc, RegDst,
EscReg, ULAFonteA, ULAFonteB, ULAOp, FONtePC, opcode);
end architecture; |
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2020 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- 8-bit binary counter with output register; 3-state
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_74590 is
generic (
latency : integer := 3
);
port (
emuclk : in std_logic;
p1 : out ttl_t; -- Q1
p2 : out ttl_t; -- Q2
p3 : out ttl_t; -- Q3
p4 : out ttl_t; -- Q4
p5 : out ttl_t; -- Q5
p6 : out ttl_t; -- Q6
p7 : out ttl_t; -- Q7
p9 : out ttl_t; -- RCOn
p10 : in ttl_t; -- MRCn (counter reset)
p11 : in ttl_t; -- CPC (counter clock)
p12 : in ttl_t; -- CEn (clock enable of CPC)
p13 : in ttl_t; -- CPR (output register clock)
p14 : in ttl_t; -- OEn
p15 : out ttl_t -- Q0
);
end entity;
architecture rtl of ttl_74590 is
signal cpc_ena : std_logic;
signal cpr_ena : std_logic;
signal p1_loc : ttl_t;
signal p2_loc : ttl_t;
signal p3_loc : ttl_t;
signal p4_loc : ttl_t;
signal p5_loc : ttl_t;
signal p6_loc : ttl_t;
signal p7_loc : ttl_t;
signal p9_loc : ttl_t;
signal p15_loc : ttl_t;
signal counter_reg : unsigned(7 downto 0) := (others => '0');
signal output_reg : unsigned(7 downto 0) := (others => '0');
begin
cpc_edge_inst : entity work.ttl_edge
port map (emuclk => emuclk, edge => '1', d => p11, ena => cpc_ena);
cpr_edge_inst : entity work.ttl_edge
port map (emuclk=> emuclk, edge => '1', d => p13, ena => cpr_ena);
p1_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p1_loc, q => p1);
p2_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p2_loc, q => p2);
p3_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p3_loc, q => p3);
p4_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p4_loc, q => p4);
p5_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p5_loc, q => p5);
p6_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p6_loc, q => p6);
p7_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p7_loc, q => p7);
p9_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p9_loc, q => p9);
p15_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p15_loc, q => p15);
p1_loc <= std2ttl(output_reg(1));
p2_loc <= std2ttl(output_reg(2));
p3_loc <= std2ttl(output_reg(3));
p4_loc <= std2ttl(output_reg(4));
p5_loc <= std2ttl(output_reg(5));
p6_loc <= std2ttl(output_reg(6));
p7_loc <= std2ttl(output_reg(7));
p9_loc <= ZERO when counter_reg = X"FF" else ONE;
p15_loc <= std2ttl(output_reg(0));
process(emuclk)
begin
if rising_edge(emuclk) then
if (cpc_ena = '1') and is_low(p12) then
counter_reg <= counter_reg + 1;
end if;
if cpr_ena = '1' then
output_reg <= counter_reg;
end if;
if is_low(p10) then
-- Asynchronous reset, clears counter but not the output register
counter_reg <= (others => '0');
end if;
end if;
end process;
end architecture;
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