content stringlengths 1 1.04M ⌀ |
|---|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:55:04 01/15/2015
-- Design Name:
-- Module Name: componant_1_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependenc... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:55:04 01/15/2015
-- Design Name:
-- Module Name: componant_1_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependenc... |
entity textio5 is
end entity;
use std.textio.all;
architecture test of textio5 is
begin
process is
file fptr : text;
variable l : line;
begin
file_open(fptr, "tmp.txt", WRITE_MODE);
write(l, string'("0123"));
tee(fptr, l);
write(l, string'("4567"));
tee... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
architecture RTL of FIFO is
shared variable v_shar_var1 : integer;
begin
process
variable v_var1 : integer;
begin
end process;
end architecture RTL;
-- Violations below
architecture RTL of FIFO is
shared variable shar_var1 : integer;
begin
process
variable var1 : integer;
begin
end pro... |
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : cntr_tb.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram1 is
generic (
WIDTHB : integer := 32;
SIZEB : integer := 64;
ADDRWIDTHB : integer := 6
);
port (
clkB : in std_logic;
enB : in std_logic;
weB : in std_logic;
addrB : in std_logi... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as publis... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
--------------------------------------------------------------------------------
-------------------------------------------------------------------------... |
entity test is
end entity test;
architecture beh of test is
signal sig : bit_vector(-1 downto 0);
signal sig2 : bit_vector(0 to -1);
begin
process(sig,sig2)
begin
sig <= (sig'range => '0'); -- OK
sig2 <= (sig2'range => '0'); -- OK
end process;
end architecture beh... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nxor00 is
port(
Anx: in std_logic ;
Bnx: in std_logic ;
Ynx: out std_logic );
end;
architecture nxor0 of nxor00 is
begin
Ynx <= not(Anx xor Bnx);
end nxor0;
|
library verilog;
use verilog.vl_types.all;
entity controller is
port(
clk : in vl_logic;
coin_Detected : in vl_logic;
value_cents : in vl_logic_vector(7 downto 0);
soda_price_0 : in vl_logic_vector(7 downto 0);
soda_price_1 : in vl_... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--**********************************************************************************************
-- JTAG "Flash" programmer for AVR Core(cp2 Clock Domain)
-- Version 0.5
-- Modified 20.06.2006
-- Designed by Ruslan Lepetenok
--****************************************************************************************... |
--**********************************************************************************************
-- JTAG "Flash" programmer for AVR Core(cp2 Clock Domain)
-- Version 0.5
-- Modified 20.06.2006
-- Designed by Ruslan Lepetenok
--****************************************************************************************... |
--**********************************************************************************************
-- JTAG "Flash" programmer for AVR Core(cp2 Clock Domain)
-- Version 0.5
-- Modified 20.06.2006
-- Designed by Ruslan Lepetenok
--****************************************************************************************... |
--**********************************************************************************************
-- JTAG "Flash" programmer for AVR Core(cp2 Clock Domain)
-- Version 0.5
-- Modified 20.06.2006
-- Designed by Ruslan Lepetenok
--****************************************************************************************... |
BuzzerRe_inst : BuzzerRe PORT MAP (
clock => clock_sig,
cout => cout_sig,
q => q_sig
);
|
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- ... |
entity comp6_bot is
generic (num : integer := 2 );
port (
x : in bit_vector(7 downto 0);
y : out bit_vector(7 downto 0) );
end entity;
architecture rtl of comp6_bot is
function cfunc (constant val : integer) return integer is
variable tmp : integer;
begin tmp := 0;
for i in 0 to 3 lo... |
entity comp6_bot is
generic (num : integer := 2 );
port (
x : in bit_vector(7 downto 0);
y : out bit_vector(7 downto 0) );
end entity;
architecture rtl of comp6_bot is
function cfunc (constant val : integer) return integer is
variable tmp : integer;
begin tmp := 0;
for i in 0 to 3 lo... |
entity comp6_bot is
generic (num : integer := 2 );
port (
x : in bit_vector(7 downto 0);
y : out bit_vector(7 downto 0) );
end entity;
architecture rtl of comp6_bot is
function cfunc (constant val : integer) return integer is
variable tmp : integer;
begin tmp := 0;
for i in 0 to 3 lo... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19.08.2016 14:48:09
-- Design Name:
-- Module Name: Switches_LEDS - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:20:53 12/04/2017
-- Design Name:
-- Module Name: Barra4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision... |
architecture test of test2 is
constant foo : bar := "hel""lo";
begin end;
|
--**********************************************************************************************
--
-- Version 0.1
-- Modified 31.12.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
... |
--**********************************************************************************************
--
-- Version 0.1
-- Modified 31.12.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
... |
--**********************************************************************************************
--
-- Version 0.1
-- Modified 31.12.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
... |
--**********************************************************************************************
--
-- Version 0.1
-- Modified 31.12.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
... |
--**********************************************************************************************
--
-- Version 0.1
-- Modified 31.12.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
... |
--**********************************************************************************************
--
-- Version 0.1
-- Modified 31.12.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
... |
--**********************************************************************************************
--
-- Version 0.1
-- Modified 31.12.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
... |
--**********************************************************************************************
--
-- Version 0.1
-- Modified 31.12.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
... |
--
-- Input filter
--
-- Author: Sebastian Witt
-- Data: 06.03.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at ... |
--
-- Input filter
--
-- Author: Sebastian Witt
-- Data: 06.03.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at ... |
--
-- Input filter
--
-- Author: Sebastian Witt
-- Data: 06.03.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at ... |
--
-- Input filter
--
-- Author: Sebastian Witt
-- Data: 06.03.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at ... |
--
-- Input filter
--
-- Author: Sebastian Witt
-- Data: 06.03.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
architecture rtl of fifo is
begin
process begin
loop end loop;
LOOP end LOOP;
end process;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity uart_peripheral_fast is
generic (
g_divisor : natural := 35 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
entity dma_bus_arbiter_pri is
generic (
g_ports : positive := 3 );
port (
clock : in std_logic;
reset : in std_logic;
reqs : in t_dma_req_array(0 to... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
entity dma_bus_arbiter_pri is
generic (
g_ports : positive := 3 );
port (
clock : in std_logic;
reset : in std_logic;
reqs : in t_dma_req_array(0 to... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
entity dma_bus_arbiter_pri is
generic (
g_ports : positive := 3 );
port (
clock : in std_logic;
reset : in std_logic;
reqs : in t_dma_req_array(0 to... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
entity dma_bus_arbiter_pri is
generic (
g_ports : positive := 3 );
port (
clock : in std_logic;
reset : in std_logic;
reqs : in t_dma_req_array(0 to... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
entity dma_bus_arbiter_pri is
generic (
g_ports : positive := 3 );
port (
clock : in std_logic;
reset : in std_logic;
reqs : in t_dma_req_array(0 to... |
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_t_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 10:12:12 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
... |
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- Containing RapidIO packet switching functionality contained in the top
-- entity... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20.06.2016 06:22:11
-- Design Name:
-- Module Name: tb_tcp_engine_add_data - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-... |
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- The above libaries lines must be included in every VHDL file, before EVERY ENTITY!
--
-- Main circuit Entity: connects all wires to the FPGA IO pins.
-- PORT mapping - declare all wire connections to INput or OUTput pins.
-- Note that all signal ... |
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Thu Jun 01 02:21:04 2017
--Host : GILAMONSTER running 64-bit major release ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee.std_logic_1164.all;
use work.btrace_pack.all;
entity top is
port(clk, rst: in std_logic;
btns, btnr, btnu: in std_logic;
rgb: out std_logic_vector(11 downto 0);
hsync, vsync, led: out std_logic);
end top;
architecture arch of top is
c... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: tcp_engine - Behavioral
--
-- Description: Implement the TCP/IP session protocol.
--
------------------------------------------------------------------------------... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_core is
generic (
CONFIG_NUM_GPIO : natural := 2;
GP_OFFSET : natural := 16
);
port (
gpio : inout unsigned(CONFIG_NUM_GPIO*16-1 downto 0);
-- Inter-module connection wires for pin muxing: {
gpio_in : out std_... |
---- qspi_look_up_logic - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012... |
---- qspi_look_up_logic - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.Std_Logic_1164.all;
--Multiplexador 2x1
entity mux2x1 is
port (IN0,IN1: in std_logic_vector(29 downto 0);
REG: out std_logic_vector(29 downto 0);
SW: in std_logic
);
end mux2x1;
--Definicao Arquitetura
architecture circuito of mux2x1 is
begin
REG <= IN0 when SW = '0' else
IN1;
end... |
library ieee;
use ieee.std_logic_1164.all;
entity HA_tb is
end HA_tb;
architecture tb of HA_tb is
component HA is
port( A, B : in std_logic;
Sout, Cout : out std_logic);
end component;
signal A, B, Sout, Cout: std_logic;
begin
mapping: HA port map(A, B, Sout, Cout);
process
variabl... |
architecture RTL of FIFO is
begin
process
variable var1 : integer;
begin
end process;
process (a, b)
variable var1 : integer;
begin
end process;
process is
variable var1 : integer;
begin
end process;
-- Violations below
process
variable var1 : integer;
begin
end proc... |
-- Module Name: InputGate - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
entity test1 is
port (
a : in std_logic;
b : in std_logic;
c : out std_logic );
end entity;
architecture Behavioral of test1 is
begin
c <= a and b;
end Behavioral;
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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